IDT IDT74ALVCHR16501

IDT74ALVCHR16501
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT UNIVERSAL IDT74ALVCHR16501
BUS TRANSCEIVER WITH
3-STATE OUTPUTS
AND BUS-HOLD
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
µ W typ. static)
• CMOS power levels (0.4µ
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
This 18-bit universal bus transceiver is built using advanced dual metal
CMOS technology. Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch enable (LEAB and LEBA) and clock (CLKAB and
CLKBA) inputs. For A-to-B data flow, the device operates in the transparent
mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB
is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/
flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs
are active. When OEAB is low, the outputs are in the high-impedance state. Data
flow from B to A is similiar to that of A to B but uses OEBA, LEBA, and CLKBA.
The output enables are complementary (OEAB is active high and OEBA is active
low).
The ALVCHR16501 has series resistors in the device output structure which
will significantly reduce reduce line noise when used with light loads. This driver
has been designed to drive ±12mA at the designated threshold levels.
The ALVCHR16501 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low Switching Noise
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
OEAB
CLKAB
LEAB
LEBA
CLKBA
OEBA
A1
1
55
2
28
30
27
3
1D
54
B1
C1
CLK
1D
C1
CLK
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
JANUARY 2004
1
© 2004 Integrated Device Technology, Inc.
DSC-4613/2
IDT74ALVCHR16501
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
Description
VTERM(2)
Max
Unit
Terminal Voltage with Respect to GND
–0.5 to +4.6
V
VTERM(3)
Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
TSTG
Storage Temperature
–65 to +150
°C
–50 to +50
mA
±50
mA
OEAB
1
56
GND
LEAB
2
55
CLKAB
IOUT
DC Output Current
A1
3
54
B1
IIK
GND
4
53
GND
Continuous Clamp Current,
VI < 0 or VI > VCC
A2
5
52
B2
IOK
Continuous Clamp Current, VO < 0
–50
mA
A3
6
mA
B3
Continuous Current through each
VCC or GND
±100
51
ICC
ISS
VCC
7
50
VCC
A4
8
49
B4
A5
9
48
B5
A6
10
47
B6
GND
11
46
GND
A7
12
45
B7
A8
13
44
B8
A9
14
43
B9
A10
15
42
B10
A11
16
41
B11
A12
17
40
B12
Symbol
Conditions
Typ.
Max.
Unit
GND
18
39
GND
CIN
Input Capacitance
VIN = 0V
5
7
pF
A13
19
38
B13
COUT
Output Capacitance
VOUT = 0V
7
9
pF
CI/O
I/O Port Capacitance
VIN = 0V
7
9
pF
A14
20
37
B14
A15
21
36
B15
VCC
22
35
VCC
A16
23
34
B16
A17
24
33
B17
GND
25
32
GND
A18
26
31
B18
OEBA
27
30
CLKBA
LEBA
28
29
GND
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Parameter(1)
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
TSSOP
TOP VIEW
Description
OEAB
A-to-B Output Enable Input
OEBA
B-to-A Output Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input
LEBA
B-to-A Latch Enable Input
CLKAB
A-to-B Clock Input
CLKBA
B-to-A Clock Input
Ax
A-to-B Data Inputs or B-to-A 3-State Outputs(1)
Bx
B-to-A Data Inputs or A-to-B 3-State Outputs(1)
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
2
IDT74ALVCHR16501
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLE(1,2)
Inputs
Output
OEAB
LEAB
CLKAB
Ax
Bx
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
↑
L
L
H
L
↑
H
H
H
L
L
X
B(3)
H
L
H
X
B(4)
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, and
CLKBA.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑ = LOW-to-HIGH Transition
3. Output level before the indicated steady-state input conditions were established
4. Output level before the indicated steady-state input conditions were established,
provided that CLKAB was LOW before LEAB went LOW.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
Symbol
VIH
VIL
Min.
Typ.(1)
Max.
Unit
VCC = 2.3V to 2.7V
1.7
—
—
V
VCC = 2.7V to 3.6V
2
—
—
VCC = 2.3V to 2.7V
—
—
0.7
VCC = 2.7V to 3.6V
—
—
0.8
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Test Conditions
V
IIH
Input HIGH Current
VCC = 3.6V
VI = VCC
—
—
±5
µA
IIL
Input LOW Current
VCC = 3.6V
VI = GND
—
—
±5
µA
IOZH
High Impedance Output Current
VCC = 3.6V
VO = VCC
—
—
±10
µA
IOZL
(3-State Output pins)
VO = GND
—
—
±10
VIK
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
—
–0.7
–1.2
V
VH
ICCL
ICCH
ICCZ
∆ICC
Input Hysteresis
Quiescent Power Supply Current
VCC = 3.3V
VCC = 3.6V
VIN = GND or VCC
—
—
100
0.1
—
40
mV
µA
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
750
µA
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74ALVCHR16501
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
BUS-HOLD CHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
Bus-Hold Input Sustain Current
VCC = 3V
VI = 2V
IBHL
IBHH
Bus-Hold Input Sustain Current
VCC = 2.3V
IBHL
IBHHO
Bus-Hold Input Overdrive Current
Min.
VCC = 3.6V
Typ.(2)
Max.
Unit
µA
– 75
—
—
VI = 0.8V
75
—
—
VI = 1.7V
– 45
—
—
VI = 0.7V
45
—
—
—
±500
VI = 0 to 3.6V
—
µA
µA
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol
VOH
Test Conditions(1)
Parameter
Output HIGH Voltage
Unit
—
V
IOH = – 4mA
1.9
—
IOH = – 6mA
1.7
—
IOH = – 4mA
2.2
—
VCC = 2.3V
IOH = – 8mA
2
—
IOH = – 6mA
2.4
—
IOH = – 12mA
2
—
VCC = 2.3V to 3.6V
IOL = 0.1mA
—
0.2
VCC = 2.3V
IOL = 4mA
—
0.4
IOL = 6mA
—
0.55
VCC = 2.7V
IOL = 4mA
—
0.4
IOL = 8mA
—
0.6
IOL = 6mA
—
0.55
IOL = 12mA
—
0.8
VCC = 3V
Output LOW Voltage
Max.
IOH = – 0.1mA
VCC = 2.7V
VOL
Min.
VCC – 0.2
VCC = 2.3V to 3.6V
VCC = 3V
V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
Symbol
Parameter
CPD
Power Dissipation Capacitance Outputs enabled
CPD
Power Dissipation Capacitance Outputs disabled
Test Conditions
CL = 0pF, f = 10Mhz
4
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Typical
Typical
Unit
—
—
pF
—
—
IDT74ALVCHR16501
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
Symbol
VCC = 2.7V
VCC = 3.3V ± 0.3V
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
1.2
5.9
—
5.2
1
4.5
ns
1.6
6.8
—
6
1.3
5.2
ns
1.7
7.2
—
6.3
1.4
5.5
ns
1.4
7.3
—
6.7
1.1
5.6
ns
1.1
6.8
—
6
1
5.2
ns
2
6
—
5.1
1.3
4.7
ns
2.2
6.9
—
6.2
1.4
5.5
ns
tPLH
Propagation Delay
tPHL
Ax to Bx or Bx to Ax
tPLH
Propagation Delay
tPHL
LEBA to Ax or LEAB to Bx
tPLH
Propagation Delay
tPHL
CLKBA to Ax or CLKAB to Bx
tPZH
Output Enable Time
tPZL
OEBA to Ax
tPZH
Output Enable Time
tPZL
OEAB to Bx
tPHZ
Output Disable Time
tPLZ
OEBA to Ax
tPHZ
Output Disable Time
tPLZ
OEAB to Bx
tSU
Set-up Time, data before CLK↑
2.2
—
2.1
—
1.7
—
ns
tH
Hold Time, data after CLK↑
0.6
—
0.6
—
0.7
—
ns
tSU
Set-up Time, data before LE↓
CLK LOW
1.9
—
1.6
—
1.5
—
ns
CLK HIGH
1.3
—
1.1
—
1
—
tH
Hold Time, data after LE↓, CLK HIGH or LOW
1.4
—
1.7
—
1.4
—
ns
tW
Pulse Width, LE HIGH
3.3
—
3.3
—
3.3
—
ns
tW
Pulse Width, CLK HIGH or LOW
3.3
—
3.3
—
3.3
—
ns
Output Skew(2)
—
—
—
—
—
500
ps
tSK(o)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2 Skew between any two outputs of the same package and switching in the same direction.
5
IDT74ALVCHR16501
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
Symbol
VCC(2)= 2.5V±0.2V
Unit
VLOAD
6
6
2 x Vcc
V
VIH
2.7
2.7
Vcc
V
VT
1.5
1.5
Vcc / 2
V
VLZ
300
300
150
mV
VHZ
300
300
150
mV
CL
50
50
30
pF
(1, 2)
VIN
tPHL
VIH
VT
0V
ALVC Link
DISABLE
ENABLE
CONTROL
INPUT
GND
tPZL
D.U.T.
OUTPUT
SWITCH
NORMALLY
CLOSED
LOW
tPZH
OUTPUT
SWITCH
NORMALLY
OPEN
HIGH
500Ω
CL
ALVC Link
Test Circuit for All Outputs
tPLH
Propagation Delay
VOUT
RT
tPHL
OPPOSITE PHASE
INPUT TRANSITION
Open
500Ω
tPLH
OUTPUT
VLOAD
VCC
Pulse
Generator
VIH
VT
0V
VOH
VT
VOL
SAME PHASE
INPUT TRANSITION
tPLZ
VLOAD/2
VT
VIH
VT
0V
VLOAD/2
VLZ
VOL
tPHZ
VOH
VHZ
0V
VT
0V
ALVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
DATA
INPUT
SWITCH POSITION
Test
GND
All Other Tests
Open
INPUT
OUTPUT 1
tPLH1
SYNCHRONOUS
CONTROL
VIH
VT
0V
VOH
VT
VOL
tSK (x)
OUTPUT 2
LOW-HIGH-LOW
PULSE
VT
tW
HIGH-LOW-HIGH
PULSE
VT
ALVC Link
tPHL2
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
tH
Set-up, Hold, and Release Times
VOH
VT
VOL
tPLH2
tSU
ALVC Link
tPHL1
tSK (x)
tREM
ASYNCHRONOUS
CONTROL
VLOAD
Disable High
Enable High
tH
TIMING
INPUT
Switch
Open Drain
Disable Low
Enable Low
tSU
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
ALVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
6
IDT74ALVCHR16501
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
ALVC X
XX
Bus-Hold
Temp. Range
XXX
Family
XX
XXX
Device Type Package
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
PA
Thin Shrink Small Outline Package
501
18-Bit Universal Bus Transceiver with 3-State Outputs
R16
Double-Density, ±12mA
H
Bus-Hold
74
– 40°C to +85°C
for SALES:
800-345-7015 or 408-727-6116
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www.idt.com
7
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