HD74AC107/HD74ACT107 Dual JK Flip-Flop (with Separate Clear and Clock) REJ03D0243–0200Z (Previous ADE-205-363 (Z)) Rev.2.00 Jul.16.2004 Description The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. The sequence of operation is as follows: 1) isolate slave from master; 2) enter information from J and K inputs to master; 3) disable J and K inputs; 4) transfer information from master to slave. Features • Outputs Source/Sink 24 mA • HD74ACT107 has TTL-Compatible Inputs • Ordering Information: Ex. HD74AC107 Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74AC107FPEL SOP-14 pin (JEITA) FP-14DAV FP EL (2,000 pcs/reel) HD74AC107RPEL SOP-14 pin (JEDEC) FP-14DNV RP EL (2,500 pcs/reel) Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code. Pin Arrangement J1 1 14 VCC Q1 2 13 CD1 Q1 3 12 CP1 K1 4 11 K2 Q2 5 10 CD2 Q2 6 9 CP2 GND 7 8 J2 (Top view) Rev.2.00, Jul.16.2004, page 1 of 6 HD74AC107/HD74ACT107 Logic Symbol 1 12 4 J1 Q1 3 CP1 K1 CD1 Q1 13 2 8 J2 9 CP2 11 VCC = Pin14 GND = Pin7 K2 CD2 Q2 6 Q2 5 10 Pin Names J1, J2, K1, K2 CP1, CP2 CD1, CD2 Q1, Q2, Q1, Q 2 Data Inputs Clock Pulse Inputs (Active Falling Edge) Direct Clear Inputs (Active Low) Outputs Truth Table Inputs Outputs @ tn J @ tn + 1 Q K L L L H Qn L H H H L tn tn + 1 L H H Qn : : : : High Voltage Level Low Voltage Level Bit time before clock pulse. Bit time after clock pulse. Logic Diagram CD J Q #CP #CP Q K CP #CP CP CP CP Rev.2.00, Jul.16.2004, page 2 of 6 CP CP #CP CP HD74AC107/HD74ACT107 Absolute Maximum Ratings Item Symbol Ratings Unit Condition Supply voltage DC input diode current VCC IIK –0.5 to 7 –20 V mA VI 20 –0.5 to Vcc+0.5 mA V VI = Vcc+0.5V DC input voltage DC output diode current IOK –50 50 mA mA VO = –0.5V VO = Vcc+0.5V DC output voltage DC output source or sink current VO IO –0.5 to Vcc+0.5 ±50 V mA DC VCC or ground current per output pin Storage temperature ICC, IGND Tstg ±50 –65 to +150 mA °C VI = –0.5V Recommended Operating Conditions: HD74AC107 Item Symbol Ratings Unit Supply voltage Input and output voltage VCC VI, VO 2 to 6 0 to VCC V V Operating temperature Input rise and fall time (except Schmitt inputs) VIN 30% to 70% VCC Ta tr, tf –40 to +85 8 °C ns/V Condition VCC = 3.0V VCC = 4.5 V VCC = 5.5 V DC Characteristics: HD74AC107 Item Input Voltage Symbol Unit Condition min. 2.1 typ. 1.5 max. — min. 2.1 max. — 4.5 5.5 3.15 3.85 2.25 2.75 — — 3.15 3.85 — — 3.0 4.5 — — 1.50 2.25 0.9 1.35 — — 0.9 1.35 5.5 3.0 — 2.9 2.75 2.99 1.65 — — 2.9 1.65 — 4.5 5.5 4.4 5.4 4.49 5.49 — — 4.4 5.4 — — 3.0 4.5 2.58 3.94 — — — — 2.48 3.80 — — 5.5 3.0 4.94 — — 0.002 — 0.1 4.80 — — 0.1 4.5 5.5 — — 0.001 0.001 0.1 0.1 — — 0.1 0.1 3.0 4.5 — — — — 0.32 0.32 — — 0.37 0.37 IIN 5.5 5.5 — — — — 0.32 ±0.1 — — 0.37 ±1.0 µA VIN = VCC or GND IOLD IOHD 5.5 5.5 — — — — — — 86 –75 — — mA mA VOLD = 1.1 V VOHD = 3.85 V — 40 µA VIN = VCC or ground VOH VOL Input leakage current Dynamic output current* Ta = –40 to +85°°C 3.0 VIH VIL Output voltage Ta = 25°°C Vcc (V) Quiescent supply 5.5 — — 4.0 ICC current *Maximum test duration 2.0 ms, one output loaded at a time. Rev.2.00, Jul.16.2004, page 3 of 6 V VOUT = 0.1 V or VCC –0.1 V VOUT = 0.1 V or VCC –0.1 V V VIN = VIL or VIH IOUT = –50 µA VIN = VIL or VIH IOH = –12 mA IOH = –24 mA IOH = –24 mA VIN = VIL or VIH IOUT = 50 µA VIN = VIL or VIH IOL = 12 mA IOL = 24 mA IOL = 24 mA HD74AC107/HD74ACT107 Recommended Operating Conditions: HD74ACT107 Item Symbol Ratings Unit Supply voltage Input and output voltage VCC VI, VO 2 to 6 0 to VCC V V Operating temperature Input rise and fall time (except Schmitt inputs) VIN 0.8 to 2.0 V Ta tr, tf –40 to +85 8 °C ns/V Condition VCC = 4.5V VCC = 5.5V DC Characteristics: HD74ACT107 Item Input voltage Output voltage Symbol Ta = 25°°C VCC (V) Ta = –40 to +85°°C VIH 4.5 min. 2.0 VIL 5.5 4.5 2.0 — 1.5 1.5 — 0.8 2.0 — — 0.8 VOH 5.5 4.5 — 4.4 1.5 4.49 0.8 — — 4.4 0.8 — 5.5 4.5 5.4 3.94 5.49 — — — 5.4 3.80 — — 5.5 4.5 4.94 — — 0.001 — 0.1 4.80 — — 0.1 5.5 4.5 — — 0.001 — 0.1 0.32 — — 0.1 0.37 VOL typ. 1.5 max. — min. 2.0 max. — Unit V Condition VOUT = 0.1 V or Vcc–0.1 V VOUT = 0.1 V or Vcc–0.1 V V VIN = VIL or VIH IOUT = –50 µA VIN = VIL IOH = –24 mA IOH = –24 mA VIN = VIL or VIH IOUT = 50 µA VIN = VIL IOL = 24 mA Input current IIN 5.5 5.5 — — — — 0.32 ±0.1 — — 0.37 ±1.0 µA VIN = VCC or GND ICC/input current Dynamic output current* ICCT IOLD 5.5 5.5 — — 0.6 — — — — 86 1.5 — mA mA VIN = VCC–2.1 V VOLD = 1.1 V IOHD ICC 5.5 5.5 — — — — — 4.0 –75 — — 40 mA µA VOHD = 3.85 V VIN = VCC or ground Quiescent supply current IOL = 24 mA *Maximum test duration 2.0 ms, one output loaded at a time. AC Characteristics: HD74AC107 Ta = +25°C CL = 50 pF Item Maximum clock frequency Propagation delay CP to Q or Q Propagation delay Ta = –40°C to +85°C CL = 50 pF fmax VCC (V)*1 Min 3.3 125 Typ — Max — Min 100 — MHz tPLH 5.0 3.3 150 1.0 — 9.5 — 13.0 125 1.0 — 14.0 ns 1.0 1.0 7.5 10.0 10.0 13.5 1.0 1.0 11.0 14.5 ns Symbol Max Unit tPHL 5.0 3.3 CP to Q or Q Propagation delay tPLH 5.0 3.3 1.0 1.0 8.0 9.5 10.5 13.0 1.0 1.0 11.5 14.0 ns CD to Q Propagation delay tPHL 5.0 3.3 1.0 1.0 7.5 9.5 10.0 13.0 1.0 1.0 11.0 14.0 ns 1.0 7.5 10.0 1.0 11.0 5.0 CD to Q Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V Rev.2.00, Jul.16.2004, page 4 of 6 HD74AC107/HD74ACT107 Operating Requirements: HD74AC107 Ta = –40°C to +85°C CL = 50 pF Ta = +25°C CL = 50 pF Setup time Symbol VCC (V)*1 Typ tsu 3.3 3.0 J or k to CP Hold time th 5.0 3.3 2.0 –1.5 4.0 0.0 4.5 0.0 CP to J or k Pulse width tw 5.0 3.3 –0.5 2.0 0.0 5.5 0.0 7.0 CP or CD Recovery time trec 5.0 3.3 2.0 1.5 4.5 3.0 5.0 3.0 5.0 1.0 3.0 3.0 Item CD to CP Note: Guaranteed Minimum 5.5 6.0 Unit ns 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V AC Characteristics: HD74ACT107 Ta = +25°C CL = 50 pF Item Maximum clock frequency Propagation delay CP to Q or Q Propagation delay CP to Q or Q Propagation delay CD to Q Propagation delay CD to Q Note: Ta = –40°C to +85°C CL = 50 pF fmax VCC (V)*1 Min 5.0 100 Typ — Max — 80 — MHz tPLH 5.0 1.0 9.5 12.5 1.0 13.5 ns tPHL 5.0 1.0 10.5 13.0 1.0 14.0 tPLH 5.0 1.0 8.5 11.0 1.0 12.0 tPHL 5.0 1.0 8.5 11.0 1.0 12.0 Symbol Min Max Unit 1. Voltage Range 5.0 is 5.0 V ± 0.5 V Operating Requirements: HD74ACT107 Ta = +25°C CL = 50 pF Item Symbol VCC (V)*1 Typ tsu 5.0 2.5 Setup time J or k to CP Hold time 5.0 th CP to J or k Pulse width tw 5.0 CP or CD Recovery time trec 5.0 CD to CP Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V Ta = –40°C to +85°C CL = 50 pF Guaranteed Minimum 7.0 8.0 0.0 1.5 1.5 4.5 7.0 8.0 — 3.0 3.0 Unit ns Capacitance Item Input capacitance CIN 4.5 pF VCC = 5.5 V Power dissipation capacitance CPD 35.0 pF VCC = 5.0 V Rev.2.00, Jul.16.2004, page 5 of 6 Symbol Typ Unit Condition HD74AC107/HD74ACT107 Package Dimensions As of January, 2003 Unit: mm 10.06 10.5 Max 8 5.5 14 1 1.42 Max *0.20 ± 0.05 2.20 Max 7 *0.40 ± 0.06 1.15 0˚ – 8˚ 0.10 ± 0.10 1.27 0.20 7.80 +– 0.30 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-14DAV — Conforms 0.23 g As of January, 2003 Unit: mm 8.65 9.05 Max 8 1 7 *0.20 ± 0.05 0.635 Max 1.75 Max 3.95 14 + 0.10 6.10 – 0.30 1.08 0.67 0.60 +– 0.20 0.14 – 0.04 *0.40 ± 0.06 + 0.11 0˚ – 8˚ 1.27 0.15 0.25 M *Ni/Pd/Au plating Rev.2.00, Jul.16.2004, page 6 of 6 Package Code JEDEC JEITA Mass (reference value) FP-14DNV Conforms Conforms 0.13 g Sales Strategic Planning Div. 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