PDF

TSL2014
896 × 1 Linear Sensor Array
General Description
The TSL2014 linear sensor array consists of two sections of 448
photodiodes and associated charge amplifier circuitry that can
be connected to form a contiguous 896 × 1 array. The pixels
measure 120μm (H) by 70μm (W) with 125μm center-to-center
spacing and 55μm spacing between pixels. Operation is
simplified by internal control logic that requires only a
serial-input (SI) signal and a clock.
The TSL2014 is intended for use in a wide variety of applications
including mark detection and code reading, optical character
recognition (OCR) and contact imaging, edge detection and
positioning as well as optical linear and rotary encoding.
Ordering Information and Content Guide appear at end of
datasheet.
Key Benefits & Features
The benefits and features of the TSL2014 Linear Sensor Array,
are listed below:
Figure 1:
Added Value of Using TSL2014
Benefits
Features
• Provides High Density Pixel Count
• 896 x 1 Sensor-Element Organization
• Enables High Resolution Scanning
• 200 Dots-Per-Inch (DPI) Sensor Pitch
• Enables Capacitive Threshold Sensing
• High Linearity and Uniformity
• Provides Full Dynamic Range
• Rail-to-Rail Output Swing
• Wide Dynamic Range... 2000:1 (66dB)
• Output Referenced to Ground
• Low Image Lag... 0.5% Typ
• Operation to 5MHz
• Single 5V Supply
• 112mm Active Length
ams Datasheet
[v1-00] 2016-Mar-31
Page 1
Document Feedback
TSL2014 − General Description
Block Diagram
The functional blocks of this device are shown below:
Figure 2:
TSL2014 Block Diagram
Page 2
Document Feedback
ams Datasheet
[v1-00] 2016-Mar-31
TSL2014 − Detailed Description
The sensor consists of 896 photodiodes arranged in a linear
array. Light energy impinging on a photodiode generates
photocurrent, which is integrated by the active integration
circuitry associated with that pixel. During the integration
period, a sampling capacitor connects to the output of the
integrator through an analog switch. The amount of charge
accumulated at each pixel is directly proportional to the light
intensity and the integration time. The integration time is the
interval between two consecutive output periods.
Detailed Description
The output and reset of the integrators is controlled by a 448-bit
shift register and reset logic. A 448-pixel output cycle is initiated
by clocking in a logic 1 into the SI input of a section for one
positive going clock edge (see Figure 10 and Figure 11)1. The
two 448-pixel sections may be operated independently using
a single clock input or connected in series to form a 896-pixel
array. Each section has an independent output (AO), which may
be connected together for the 896-pixel function.
When operating in the 896-pixel mode, as the SI pulse is clocked
through the 896-bit shift register, the charge on the sampling
capacitor of each pixel is sequentially connected to a
charge-coupled output amplifier that generates a voltage
output, AO. When the bit position goes low, the pixel integrator
is reset. On the 897 th clock rising edge, the SI pulse is clocked
out of the shift register (S2) and the output assumes a
high-impedance state. Note that this 897 th clock pulse is
required to terminate the output of the 896 th pixel and return
the internal logic to a known state. A subsequent SI pulse can
be presented as early as the 898 th clock pulse, thereby initiating
another pixel output cycle.
The voltage developed at analog output (AO) is given by:
(EQ1)
Vout = Vdrk + (Re) (Ee) (t int)
where:
• V out is the analog output voltage for white condition
• V drk is the analog output voltage for dark condition
• R e is the device responsivity for a given wavelength of
light given in V/(μJ/cm2)
• E e is the incident irradiance in μW/cm 2
• t int is integration time in seconds
1. For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock.
ams Datasheet
[v1-00] 2016-Mar-31
Page 3
Document Feedback
TSL2014 − Pin Assignments
AO is driven by a source follower that requires an external
pulldown resistor (330Ω typical). The output is nominally 0V for
no light input, 2V for normal white-level, and 3.4V for saturation
light level. When the device is not in the output phase, AO is in
a high impedance state.
A 0.1μF bypass capacitor should be connected between VDD
and ground as close as possible to the device.
Pin Assignments
The TSL2014 pin assignments are described below:
Figure 3:
Pin Diagram of Package (Top View)
PACKAGE
(TOP VIEW)
VDD 1
SI1 2
AO1 3
SO1 4
SI2 5
CLK 6
GND 7
AO2 8
SO2 9
VDD 10
Page 4
Document Feedback
ams Datasheet
[v1-00] 2016-Mar-31
TSL2014 − Pin Assignments
Figure 4:
Terminal Functions
Terminal
I/O
Description
Name
No.
VDD
1, 10
SI1
2
I
Serial input (section 1). SI1 defines the start of the data-out sequence.
AO1
3
O
Analog output of section 1.
SO1
4
O
Serial output (section 1). SO1 signals the end of the data out sequence
and provides a signal to drive the input of section 2 (SI2) in serial mode.
SI2
5
I
Serial input (section 2). SI2 defines the start of the data-out sequence.
CLK
6
I
Clock. The clock controls the charge transfer, pixel output and reset.
GND
7
AO2
8
O
Analog output of section 2.
SO2
9
O
Serial output (section 2). SO2 signals the end of the data out sequence
and provides a signal to drive the input of another device for cascading.
ams Datasheet
[v1-00] 2016-Mar-31
Supply voltage. Supply voltage for both analog and digital circuits.
Ground (substrate). All voltages are referenced to GND.
Page 5
Document Feedback
TSL2014 − Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only. Functional operation of the device at these or any
other conditions beyond those indicated under Electrical
Characteristics is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Absolute Maximum Ratings
Figure 5:
Absolute Maximum Ratings
Symbol
Min
Max
Unit
Supply voltage range
-0.3
6
V
VI
Input voltage range
-0.3
VDD + 0.3V
V
IIK
Input clamp current, (VI < 0) or (VI > VDD)
-20
20
mA
IOK
Output clamp current, (VO < 0) or (VO > VDD)
-25
25
mA
VO
Voltage range applied to any output in the high impedance or
power-off state
-0.3
VDD + 0.3V
V
IO
Continuous output current, (VO = 0 to VDD)
-25
25
mA
Continuous current through VDD or GND
-150
150
mA
IO
Analog output current range
-25
25
mA
TA
Operating free-air temperature range
-25
85
°C
Storage temperature range
-25
85
°C
260
°C
VDD
Tstrg
Parameter
Lead temperature on solder pads for 10 seconds
ESDHBM
ESD tolerance, human body model
Page 6
Document Feedback
±2000
V
ams Datasheet
[v1-00] 2016-Mar-31
TSL2014 − Electrical Characteristics
All limits are guaranteed. The parameters with min and max
values are guaranteed with production tests or
SQC (Statistical Quality Control) methods.
Electrical Characteristics
Figure 6:
Recommended Operating Conditions (see Figure 10 and Figure 11)
Symbol
VDD
Parameter
Supply voltage
Min
Nom
Max
Unit
4.5
5
5.5
V
VI
Input voltage
0
VDD
V
VIH
High-level input voltage
2
VDD
V
VIL
Low-level input voltage
0
0.8
V
400
1000
nm
5
5000
kHz
λ
Wavelength of light source
fclock
Clock frequency
tint
Sensor integration time, serial
0.1792
100
ms
tint
Sensor integration time, parallel
0.090
100
ms
TA
Operating free-air temperature
0
70
°C
RL
Load resistance
300
4700
Ω
CL
Load capacitance
330
pF
Figure 7:
Electrical Characteristics at fclock = 200kHz, V DD = 5V, TA = 25°C, λp = 640nm, tint = 5ms, RL = 330Ω,
Ee = 18μW/cm2 (unless otherwise noted)
Symbol
Parameter
Test
Conditions
Min
Typ
Max
Unit
1.6
2
2.4
V
0
0.05
0.15
V
7%
20%
Vout
Analog output voltage
(white, average over 896 pixels)
Vdrk
Analog output voltage
(dark, average over 896 pixels)
PRNU
Pixel response non-uniformity
See note (2) and
See note (3)
Nonlinearity of analog output
voltage
See note (3)
±0.4%
FS
Output noise voltage
See note (4)
1
mVrms
Re
Responsivity
ams Datasheet
[v1-00] 2016-Mar-31
See note (1)
16
22
28
V/
(μJ/cm2)
Page 7
Document Feedback
TSL2014 − Electrical Characteristics
Symbol
Parameter
SE
Saturation exposure
Vsat
Analog output saturation voltage
DSNU
IL
Test
Conditions
Min
See note (5)
2.5
Typ
Max
Unit
155
nJ/cm2
3.4
V
Dark signal non-uniformity
All pixels
See note (6)
25
Image lag
See note (7)
0.5%
120
mV
80
mA
IDD
Supply current, output idle
IIH
High-level input current
VI = VDD
10
μA
IIL
Low-level input current
VI = 0
10
μA
VOH
VOL
Ci(SI)
Ci(CLK)
High level output voltage SO1 and
SO2
Low level output voltage SO1 and
SO2
53
IO = 50μA
4.5
4.95
V
IO = 4mA
4.6
IO = 50μA
0.01
IO = 4mA
0.4
0.1
V
Input capacitance, SI
35
pF
Input capacitance, CLK
70
pF
Note(s):
1. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640nm.
2. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.
3. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
4. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
5. Minimum saturation exposure is calculated using the minimum Vsat, the maximum Vdrk, and the maximum Re.
6. DSNU is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination.
7. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:
V out ( IL ) – V drk
IL = -------------------------------------------- × 100
V out ( white ) – V drk
Page 8
Document Feedback
ams Datasheet
[v1-00] 2016-Mar-31
TSL2014 − Electrical Characteristics
Figure 8:
Timing Requirements (see Figure 10 and Figure 11)
Symbol
Parameter
Min
Nom
Max
Unit
tsu(SI)
Setup time, serial input (1)
20
ns
th(SI)
Hold time, serial input (1), (2)
0
ns
tw
Pulse duration, clock high or low
50
ns
tr , tf
Input transition (rise and fall) time
0
500
ns
Note(s):
1. Input pulses have the following characteristics: tr = 6ns, t f = 6ns.
2. SI must go low before the rising edge of the next clock pulse.
Figure 9:
Dynamic Characteristics over Recommended Ranges of Supply Voltage and Operating Free-Air
Temperature (see Figure 11)
Symbol
Parameter
ts
Analog output settling time to ±1%
tpd
Propagation delay time, SO1 andSO2
ams Datasheet
[v1-00] 2016-Mar-31
Test Conditions
RL = 330Ω, CL = 10pF
Min
Typ
Max
Unit
185
ns
50
ns
Page 9
Document Feedback
TSL2014 − Typical Characteristics
Typical Characteristics
Figure 10:
Timing Waveforms (Each Section)
CLK
SI
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
449 Clock Cycles
AO
Hi-Z
Hi-Z
Figure 11:
Operational Waveforms (Each Section)
tw
1 (449)
2 (450)
448 (896)
449 (897)
5V
CLK
2.5 V
2.5 V
2.5 V
0V
tsu(SI)
5V
SI1 (SI2) 2.5 V
2.5 V
0V
th(SI)
tpd(SO)
tpd(SO)
SO1 (SO2)
ts
ts
AO1 (A02)
Pixel 1 (449)
Page 10
Document Feedback
Pixel 448 (896)
ams Datasheet
[v1-00] 2016-Mar-31
TSL2014 − Typical Characteristics
Figure 12:
Photodiode Spectral Responsivity
1
TA = 25°C
Normalized Responsivity
0.8
0.6
0.4
0.2
0
300
400
500
600
700
800
900
1000 1100
λ − Wavelength − nm
Figure 13:
Analog Output Settling Time vs. Load Capacitance and
Resistance
600
470 pF
VDD = 5 V
Vout = 1 V
ts — Settling Time to 1% — ns
500
220 pF
400
100 pF
300
10 pF
200
100
0
0
200
400
600
1000
800
1200
RL − Load Resistance − Ω
ams Datasheet
[v1-00] 2016-Mar-31
Page 11
Document Feedback
TSL2014 − Application Information
Application Information
Integration Time
The integration time of the linear array is the period during
which light is sampled and charge accumulates on each pixel’s
integrating capacitor. The flexibility to adjust the integration
period is a powerful and useful feature of the ams AG TSL2xx
linear array family. By changing the integration time, a desired
output voltage can be obtained on the output pin while
avoiding saturation for a wide range of light levels.
Each pixel of the linear array consists of a light-sensitive
photodiode. The photodiode converts light intensity to a
voltage. The voltage is sampled on the Sampling Capacitor by
closing switch S2 (position 1) (see Figure 2 on page 2). Logic
controls the resetting of the Integrating Capacitor to zero by
closing switch S1 (position 2).
At SI input (Start Integration), pixel 1 is accessed. During this
event, S2 moves from position 1 (sampling) to position 3
(holding). This holds the sampled voltage for pixel 1. Switch S1
for pixel 1 is then moved to position 2. This resets (clears) the
voltage previously integrated for that pixel so that pixel 1 is now
ready to start a new integration cycle. When the next clock
period starts, the S1 switch is returned to position 1 to be ready
to start integrating again. S2 is returned to position 1 to start
sampling the next light integration. Then the next pixel starts
the same procedure. The integration time is the time from a
specific pixel read to the next time that pixel is read again. If
either the clock speed or the time between successive SI pulses
is changed, the integration time will vary. After the final (n th)
pixel in the array is read on the output, the output goes into a
high-impedance mode. A new SI pulse can occur on the (n+1)
clock causing a new cycle of integration/output to begin. Note
that the time between successive SI pulses must not exceed the
maximum integration time of 100msec.
The minimum integration time for any given array is determined
by time required to clock out all the pixels in the array and the
time to discharge the pixels. The time required to discharge the
pixels is a constant. Therefore, the minimum integration period
is simply a function of the clock frequency and the number of
pixels in the array. A slower clock speed increases the minimum
integration time and reduces the maximum light level for
saturation on the output. The minimum integration time shown
in this data sheet is based on the maximum clock frequency of
5 MHz.
The minimum integration time can be calculated from the
equation:
(EQ2)
1
T int ( min ) =  ------------------------------------------------------------------------- × n
 maximum clock frequency
where:
n is the number of pixels
Page 12
Document Feedback
ams Datasheet
[v1-00] 2016-Mar-31
TSL2014 − Application Information
In the case of the TSL2014, the minimum integration time would
be:
Tint(min) = 200ns × 896 = 179.2μs
It is important to note that not all pixels will have the same
integration time if the clock frequency is varied while data is
being output.
It is good practice on initial power up to run the clock (n+1)
times after the first SI pulse to clock out indeterminate data
from power up. After that, the SI pulse is valid from the time
following (n+1) clocks. The output will go into a
high-impedance state after the n+1 high clock edge. It is good
practice to leave the clock in a low state when inactive because
the SI pulse required to start a new cycle is a low-to-high
transition.
The integration time chosen is valid as long as it falls in the
range between the minimum and maximum limits for
integration time. If the amount of light incident on the array
during a given integration period produces a saturated output
(Max Voltage output), then the data is not accurate. If this
occurs, the integration period should be reduced until the
analog output voltage for each pixel falls below the saturation
level. The goal of reducing the period of time the light sampling
window is active is to lower the output voltage level to prevent
saturation. However, the integration time must still be greater
than or equal to the minimum integration period.
If the light intensity produces an output below desired signal
levels, the output voltage level can be increased by increasing
the integration period provided that the maximum integration
time is not exceeded. The maximum integration time is limited
by the length of time the integrating capacitors on the pixels
can hold their accumulated charge. The maximum integration
time should not exceed 100ms for accurate measurements.
Although the linear array is capable of running over a wide
range of operating frequencies up to a maximum of 5MHz, the
speed of the A/D converter used in the application is likely to
be the limiter for the maximum clock frequency. The voltage
output is available for the whole period of the clock, so the
setup and hold times required for the analog-to-digital
conversion must be less than the clock period.
ams Datasheet
[v1-00] 2016-Mar-31
Page 13
Document Feedback
TSL2014 − Application Information
Connection Diagrams
Figure 14:
Connection Diagrams
TSL2014
TSL2014
VDD 1
VDD 1
SI1 2
SI Input
AO1 3
AO 1
RL
330 W
Clock Input
AO 2
RL
330 W
SO1 4
AO 1/AO 2
SI1 2
AO1 3
SO1 4
SI2 5
SI2 5
CLK 6
CLK 6
Clock Input
GND 7
GND 7
AO2 8
AO2 8
SO2 9
VDD 10
PARALLEL
Page 14
Document Feedback
SI Input
RL
330 W
SO2 9
VDD 10
SERIAL
ams Datasheet
[v1-00] 2016-Mar-31
TSL2014 − Mechanical Information
Mechanical Information
Figure 15:
TSL2014 Mechanical Specifications
1.93 (49,02)
1.92 (48,77)
0.10 (2,54) BSC
0.021 (0,533) DIA
10 Places
0.040 (1,016)
0.030 (0,762)
Pixel 896
1.815 (46,10)
1.715 (43,56)
Pin 1
Pin 10
0.085 (2,159) MIN
DETAIL A
0.305 (7,747)
0.295 (7,493)
1
0.667 (16,942)
0.647 (16,434)
CL
0.170 (4,32)
0.150 (3,80)
0.08 (2,032)
0.07 (1,778)
0.040 (1,016)
0.030 (0,762)
3
0.0562 (1,427)
y j 0.0462 (1,173)
Pixel 1
0.170 (4,32)
0.150 (3,80)
4.734 (120,24)
4.714 (119,73)
0.048 (1,22)
0.038 (0,97)
Cover Glass
0.027 (0,690)
DETAIL A
0.130 (3,30)
0.120 (3,00)
0.0625 (1,5875) TYP
Bypass Capacitor
Bonded Array Die
Note(s):
1. All linear dimensions are in inches (millimeters).
2. Cover glass index of refraction is 1.52.
3. Pixel centers are located along the centerline of the mounting holes.
4. This drawing is subject to change without notice.
ams Datasheet
[v1-00] 2016-Mar-31
Page 15
Document Feedback
TSL2014 − Ordering & Contact Information
Ordering & Contact Information
Figure 16:
Ordering Information
Ordering Code
Type
Delivery Form
Delivery Quantity
TSL2014
896 x 1 Array
Box
30 pcs/box
Buy our products or get free samples online at:
www.ams.com/ICdirect
Technical Support is available at:
www.ams.com/Technical-Support
Provide feedback about this document at:
www.ams.com/Document-Feedback
For further information and requests, e-mail us at:
[email protected]
For sales offices, distributors and representatives, please visit:
www.ams.com/contact
Headquarters
ams AG
Tobelbaderstrasse 30
8141 Premstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
Page 16
Document Feedback
ams Datasheet
[v1-00] 2016-Mar-31
TSL2014 − RoHS Compliant & ams Green Statement
RoHS Compliant & ams Green
Statement
RoHS: The term RoHS compliant means that ams AG products
fully comply with current RoHS directives. Our semiconductor
products do not contain any chemicals for all 6 substance
categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to
be soldered at high temperatures, RoHS compliant products are
suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br): ams Green
defines that in addition to RoHS compliance, our products are
free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous
material).
Important Information: The information provided in this
statement represents ams AG knowledge and belief as of the
date that it is provided. ams AG bases its knowledge and belief
on information provided by third parties, and makes no
representation or warranty as to the accuracy of such
information. Efforts are underway to better integrate
information from third parties. ams AG has taken and continues
to take reasonable steps to provide representative and accurate
information but may not have conducted destructive testing or
chemical analysis on incoming materials and chemicals. ams AG
and ams AG suppliers consider certain information to be
proprietary, and thus CAS numbers and other limited
information may not be available for release.
ams Datasheet
[v1-00] 2016-Mar-31
Page 17
Document Feedback
TSL2014 − Copyrights & Disclaimer
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten,
Austria-Europe. Trademarks Registered. All rights reserved. The
material herein may not be reproduced, adapted, merged,
translated, stored, or used without the prior written consent of
the copyright owner.
Devices sold by ams AG are covered by the warranty and patent
indemnification provisions appearing in its General Terms of
Trade. ams AG makes no warranty, express, statutory, implied,
or by description regarding the information set forth herein.
ams AG reserves the right to change specifications and prices
at any time and without notice. Therefore, prior to designing
this product into a system, it is necessary to check with ams AG
for current information. This product is intended for use in
commercial applications. Applications requiring extended
temperature range, unusual environmental requirements, or
high reliability applications, such as military, medical
life-support or life-sustaining equipment are specifically not
recommended without additional processing by ams AG for
each application. This product is provided by ams AG “AS IS”
and any express or implied warranties, including, but not
limited to the implied warranties of merchantability and fitness
for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any
damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interruption of business or
indirect, special, incidental or consequential damages, of any
kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation
or liability to recipient or any third party shall arise or flow out
of ams AG rendering of technical or other services.
Page 18
Document Feedback
ams Datasheet
[v1-00] 2016-Mar-31
TSL2014 − Document Status
Document Status
Document Status
Product Preview
Preliminary Datasheet
Datasheet
Datasheet (discontinued)
ams Datasheet
[v1-00] 2016-Mar-31
Product Status
Definition
Pre-Development
Information in this datasheet is based on product ideas in
the planning phase of development. All specifications are
design goals without any warranty and are subject to
change without notice
Pre-Production
Information in this datasheet is based on products in the
design, validation or qualification phase of development.
The performance and parameters shown in this document
are preliminary without any warranty and are subject to
change without notice
Production
Information in this datasheet is based on products in
ramp-up to full production or full production which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade
Discontinued
Information in this datasheet is based on products which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade, but these products have been superseded and
should not be used for new designs
Page 19
Document Feedback
TSL2014 − Revision Information
Revision Information
Changes from 040C (2011-Aug) to current revision 1-00 (2016-Mar-31)
Page
Content of TAOS datasheet was converted to latest ams design
Added Ordering Information
16
Note(s):
1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
2. Correction of typographical errors is not explicitly mentioned.
Page 20
Document Feedback
ams Datasheet
[v1-00] 2016-Mar-31
TSL2014 − Content Guide
Content Guide
ams Datasheet
[v1-00] 2016-Mar-31
1
1
2
General Description
Key Benefits & Features
Block Diagram
3
4
6
7
10
Detailed Description
Pin Assignments
Absolute Maximum Ratings
Electrical Characteristics
Typical Characteristics
12
12
14
Application Information
Integration Time
Connection Diagrams
15
16
17
18
19
20
Mechanical Information
Ordering & Contact Information
RoHS Compliant & ams Green Statement
Copyrights & Disclaimer
Document Status
Revision Information
Page 21
Document Feedback