WM8738 w 24-Bit Stereo ADC DESCRIPTION The WM8738 is a high performance stereo audio ADC designed for consumer applications. Stereo line-level audio inputs are provided, along with a control input pin to allow operation of the audio interface in either one of two industry standard modes. The device also has a selectable digital high pass filter to remove residual DC offsets. Stereo 24-bit multi-bit sigma delta ADCs are provided, along with oversampling digital interpolation filters. 24-bit digital audio output word lengths and sampling rates from 32kHz to 96kHz are supported. The device is available in a small 14-lead SOIC package. FEATURES Audio Performance - 90 dB SNR (‘A’ weighted @ 48kHz) 3.0 – 5.5V Analogue Supply Operation 3.0 – 3.6V Digital Supply Operation ADC Sampling Frequency: 32kHz – 96kHz Selectable ADC High Pass Filter Selectable Audio Data Interface Modes 2 - I S or Left Justified 14-lead SOIC Package APPLICATIONS CD and Minidisc Recorders DVD Players General Purpose Audio Conversion BLOCK DIAGRAM WOLFSON MICROELECTRONICS plc Production Data, February 2012, Rev 4.5 To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews Copyright 2012 Wolfson Microelectronics plc WM8738 Production Data TABLE OF CONTENTS DESCRIPTION ....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................ 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION .......................................................................................... 3 ORDERING INFORMATION .................................................................................. 3 PIN DESCRIPTION ................................................................................................ 4 ABSOLUTE MAXIMUM RATINGS ........................................................................ 5 RECOMMENDED OPERATING CONDITIONS ..................................................... 5 ELECTRICAL CHARACTERISTICS ..................................................................... 6 TERMINOLOGY .............................................................................................................. 7 DIGITAL AUDIO INTERFACE TIMING ................................................................. 8 INTERNAL POWER ON RESET CIRCUIT ............................................................ 9 DEVICE DESCRIPTION ...................................................................................... 12 INTRODUCTION ........................................................................................................... 12 ADC ............................................................................................................................... 12 ADC DIGITAL FILTER ................................................................................................... 12 AUDIO DATA SAMPLING RATES ................................................................................ 13 DIGITAL AUDIO INTERFACES ..................................................................................... 14 DIGITAL FILTER CHARACTERISTICS .............................................................. 15 ADC FILTER RESPONSES ................................................................................. 15 ADC HIGH PASS FILTER ............................................................................................. 15 APPLICATIONS INFORMATION ........................................................................ 16 RECOMMENDED EXTERNAL COMPONENTS ........................................................... 16 RECOMMENDED EXTERNAL COMPONENTS VALUES ............................................ 16 PACKAGE DIMENSIONS .................................................................................... 17 IMPORTANT NOTICE ......................................................................................... 18 ADDRESS: .................................................................................................................... 18 REVISION HISTORY ........................................................................................... 19 w PD, Rev 4.5, February 2012 2 WM8738 Production Data PIN CONFIGURATION DVDD 1 14 DGND SDATO 2 13 MCLK BCLK 3 12 LRCLK FMT 4 11 NOHP CAP 5 10 AGND VREF 6 9 AVDD RIN 7 8 LIN WM8738 ORDERING INFORMATION DEVICE TEMPERATURE RANGE WM8738CGED -40 to +85 C WM8738CGED/R -40 to +85 C o o PACKAGE 14-lead SOIC (Pb-free) 14-lead SOIC (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE MSL1 260°C MSL1 260°C Note: Reel quantity = 3,000 w PD, Rev 4.5, February 2012 3 WM8738 Production Data PIN DESCRIPTION PIN NAME TYPE 1 DVDD Supply DESCRIPTION 2 SDATO Digital Output 3 BCLK Digital Input ADC audio interface data clock (5V tolerant) 4 FMT Digital input (with pull down) Audio interface format selection (5V tolerant) Digital positive supply ADC digital data output 2 ‘0’ = I S ‘1’ = Left Justified Reference de-coupling pin 5 CAP Analogue 6 VREF Analogue Output 7 RIN Analogue Input Right channel ADC input 8 LIN Analogue Input Left channel ADC input 9 AVDD Supply Analogue positive supply 10 AGND Supply Analogue ground supply and chip substrate 11 NOHP Digital Input (with pull down) Digital highpass filter bypass; (5V tolerant) Buffered reference decoupling pin ‘0’ = Enabled ‘1’ = Bypassed 12 LRCLK Digital Input Data left/right word clock (5V tolerant) 13 MCLK Digital Input Master clock input (5V tolerant) 14 DGND Supply Digital supply ground Note: 1. Digital input pins have Schmitt trigger input buffers and are 5V tolerant. w PD, Rev 4.5, February 2012 4 WM8738 Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. CONDITION Digital supply voltage Analogue supply voltage MIN MAX -0.3V +4.2V -0.3V +7.0V Voltage range digital inputs DGND -0.3V +7.0V Voltage range analogue inputs AGND -0.3V AVDD +0.3V Master Clock Frequency 37MHz Operating temperature range, TA -40C Storage temperature prior to soldering +85C 30C max / 85% RH max Storage temperature after soldering -65C +150C Notes 1. Analogue and digital grounds must always be within 0.3V of each other. 2. The digital supply voltage must always be less than or equal to the analogue supply voltage. RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital supply range DVDD 3.0 3.6 V Analogue supply range AVDD 3.0 5.5 V Ground Analogue supply current DGND,AGND AVDD = 5.0V, 0 V 30 mA 19 mA (DVDD at 3.3V) Analogue supply current AVDD = 3.3V, (DVDD at 3.3V) Supply Current Low Power Mode (DVDD at 3.3V) Supply Current Low Power Mode (DVDD at 3.3V) Digital supply current AVDD = 5.0V AVDD = 3.3V DVDD = 3.3V 180 110 4 A A mA AVDD = 5.0V or 3.3V w PD, Rev 4.5, February 2012 5 WM8738 Production Data ELECTRICAL CHARACTERISTICS Test Conditions o AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, TA = +25 C, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Logic Levels (TTL Levels) Input LOW level VIL Input HIGH level VIH 0.8 2.0 Output LOW VOL IOL = 1mA Output HIGH VOH IOH = 1mA Pull down resistance (FMT, NOHP) RPD V V 0.1 x DVDD 0.9 x DVDD V V 100 k Analogue Reference Levels Reference voltage VCAP Buffered reference voltage VREF Potential divider output impedance RCAP AVDD/2 – 50mV AVDD/2 AVDD/2 + 50mV V 60 k VCAP 40 50 V Input to ADC Input Signal Level (0dB) VRIN / VLIN 1.0 Vrms A-weighted, 0dB gain @ fs = 48KHz 90 dB SNR (Note 1) A-weighted, 0dB gain @ fs = 96KHz 90 dB SNR (Note 1) A-weighted, 0dB gain @ fs = 48KHz, AVDD = 3.3V 90 dB 97 dB -1dB input, 0dB gain -87 dB 1KHz input 95 dB SNR (Note 1) Dynamic Range (Note 2) DNR Total Harmonic Distortion (THD) A-weighted, -60dB full scale input 85 (Note 3) ADC channel separation (Note 5) Power Supply Rejection Ratio 1kHz 100mVp-p 50 dB 20Hz to 20kHz 45 dB Input Resistance 20 k Input Capacitance 10 pF PSRR 100mVp-p Notes 1. Ratio of output level with 1kHz full scale input, to the output level with the input open circuited, measured ‘A’ weighted over a 20Hz to 20kHz bandwidth using an Audio analyser. 2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. VREF and CAP de-coupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance). 4. This data is measured, using an active filter on the device inputs. w PD, Rev 4.5, February 2012 6 WM8738 Production Data TERMINOLOGY 1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No ‘Auto-zero’ or Automute function is employed in achieving these results). 2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). 3. THD (dB) - THD is a ratio, of the r.m.s. values, of Distortion/Signal. 4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). 5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. 6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region. w PD, Rev 4.5, February 2012 7 WM8738 Production Data DIGITAL AUDIO INTERFACE TIMING tMCLKL M CLK tMCLKH tMCLKY Figure 1 Master Clock Timing Requirements Test Conditions o AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, TA = +25 C, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT System Clock Timing Information MCLK System clock pulse width high TMCLKH 10 ns MCLK System clock pulse width low TMCLKL 10 ns MCLK System clock cycle time TMCLKY 27 ns t BCH t BCL BCLK t BCY LRCLK t LRH t DD t LRS U SDATO Figure 2 Digital Audio Data Timing Test Conditions o AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, TA = +25 C, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 80 ns BCLK pulse width high tBCH 40 ns BCLK pulse width low tBCL 40 ns LRCLK set-up time to BCLK rising edge tLRSU 10 ns LRCLK hold time from BCLK rising edge tLRH 10 ns SDATO propagation delay from BCLK falling edge tDD 10 ns w PD, Rev 4.5, February 2012 8 WM8738 Production Data INTERNAL POWER ON RESET CIRCUIT AVDD VDD DVDD T1 100K CAP INTERNAL PORB Power On Reset Circuit T2 100K Figure 2 Internal Power On Reset Circuit Schematic The WM8738 includes an internal Power On Reset Circuit which is used reset the digital logic into a default state after power up. Figure 2 shows a schematic of the internal POR circuit. The circuit monitors DVDD and CAP and asserts PORB low if DVDD or CAP are below the minimum threshold Vpor_off. On power up, the POR circuit requires AVDD to be present to operate. PORB is asserted low until AVDD and DVDD and CAP are established. When AVDD, DVDD, and CAP have been established, PORB is released high, all registers are in their default state and writes to the digital interface may take place. On power down, PORB is asserted low whenever DVDD or CAP drop below the minimum threshold Vpor_off. In most applications the time required for the device to release PORB high will be determined by the charge time of the CAP node. w PD, Rev 4.5, February 2012 9 WM8738 Production Data Figure 3 Typical Power up sequence where DVDD is powered before AVDD Figure 4 Typical Power up sequence where AVDD is powered before DVDD Typical POR Operation (typical values, not tested) w SYMBOL MIN TYP MAX UNIT Vpora 0.5 0.7 1.0 V Vporr 0.5 0.7 1.1 V Vpora_off 1.0 1.4 2.0 V Vpord_off 0.6 0.8 1.0 V PD, Rev 4.5, February 2012 10 WM8738 Production Data In a real application the designer is unlikely to have control of the relative power up sequence of AVDD and DVDD. Using the POR circuit to monitor CAP ensures a reasonable delay between applying power to the device and Device Ready. Figure 3 and Figure 4 show typical power up scenarios in a real system. Both AVDD and DVDD must be established and CAP must have reached the threshold Vporr before the device is ready and can be written to. Any writes to the device before Device Ready will be ignored. Figure 3 shows DVDD powering up before AVDD. Figure 4 shows AVDD powering up before DVDD. In both cases, the time from applying power to Device Ready is dominated by the charge time of CAP. A 10uF cap is recommended for decoupling on CAP. The charge time for CAP will dominate the time required for the device to become ready after power is applied. The time required for VMIDADC to reach the threshold is a function of the CAP resistor string and the decoupling capacitor. The Resistor string has a typical equivalent resistance of 50k (+/-20%). Assuming a 10uF capacitor, the time required for CAP to reach threshold of 1V is approx 110ms. w PD, Rev 4.5, February 2012 11 WM8738 Production Data DEVICE DESCRIPTION INTRODUCTION The WM8738 is an ADC designed for audio recording. It’s features, performance and low power consumption make it ideal for recordable CD or DVD players, karaoke, MP3 players and mini-disc players. The on-board stereo analogue to digital converter (ADC) is of a high quality using a multi-bit highorder oversampling architecture delivering optimum performance with low power consumption. The ADC includes a selectable digital high pass filter to remove unwanted DC components from the audio signal. The device supports system clock inputs of 256, 384, 512fs or 768fs (fs is the sampling rate) 2 The output from the ADC is available on the digital audio interface in either I S or left justified audio data formats. The line inputs are biased internally through the operational amplifier to VCAP. ADC The WM8738 uses a multi-bit over sampled sigma-delta ADC. A single channel of the ADC is illustrated in Figure 3. LIN/RIN ANALOG INTEGRATOR TO ADC DIGITAL FILTERS MULTI BITS Figure 3 Multi-Bit Oversampling Sigma Delta ADC Schematic The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input is 1.0V rms at AVDD = 5.0 volts. Any voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with AVDD. The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. ADC DIGITAL FILTER The ADC digital filters contain a digital high pass filter, selectable via pin NOHP. NOHP = 0 Digital high pass filter enabled NOHP = 1 Digital high pass filter bypassed The high-pass filter response detailed in Digital Filter Characteristics. The operation of the high pass filter removes residual DC offsets that are present on the audio signal. w PD, Rev 4.5, February 2012 12 WM8738 Production Data AUDIO DATA SAMPLING RATES In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s Master Clock. The external master system clock can be applied directly through the MCLK input pin. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the ADC. The master clock for WM8738 supports audio sampling rates from 256fs to 768fs, where fs is the audio sampling frequency LRCLK, typically 32kHz, 44.1kHz, 48kHz, or 96kHz. The master clock is used to operate the digital filters and the noise shaping circuits. The WM8738 has a master clock detection circuit that automatically determines the relationship between the master clock frequency and the sampling rate (to within +/- 32 system clocks). If there is a greater than 32 clocks error the interface is disabled and maintains the output level at the last sample. The master clock must be synchronised with LRCLK, although the WM8738 is tolerant of phase variations or jitter on this clock. Table 1 shows the typical master clock frequency inputs for the WM8738. If MCLK is stopped for greater than 10us then the device will enter a low power mode where the current taken from AVDD is greatly reduced. Note that when the device enters this mode the references are powered down. Table 1 shows the common MCLK frequencies for different sample rates. SAMPLING RATE (LRCLK) Master Clock Frequency (MHz) 256fs 384fs 512fs 768fs 32kHz 8.192 12.288 16.384 24.576 44.1kHz 11.2896 16.9340 22.5792 33.8688 48kHz 12.288 18.432 24.576 36.864 96kHz 24.576 36.864 Unavailable Unavailable Table 1 Master Clock Frequency Selection w PD, Rev 4.5, February 2012 13 WM8738 Production Data DIGITAL AUDIO INTERFACES The WM8738 has two data output formats, selectable via the FMT pin. 2 FMT = 0 ADC audio data output is I S FMT = 1 ADC audio data output is Left Justified Both of these modes are MSB first. The digital audio interface takes the data from the internal ADC digital filter. SDATO is the formatted digital audio data stream output from the ADC digital filters with left and right channels multiplexed together. LRCLK is an alignment clock that controls whether Left or Right channel data is present on the SDATO line. SDATO and LRCLK are synchronous with the BCLK signal with each data bit transition signified by a low to high BCLK transition. LEFT JUSTIFIED MODE In left justified mode, the MSB of the ADC data is output on SDATO and changes on the same falling edge of BCLK as LRCLK and may be sampled on the rising edge of BCLK. LRCLK is high during the left samples and low during the right samples. 1/fs L EF T C H AN N EL R IGH T C H AN N EL LRCLK BCLK SD ATO 1 2 3 n-2 n-1 M SB n 1 LSB 2 3 n-2 n-1 M SB n LSB Figure 4 Left Justified Mode Timing Diagram 2 I S MODE 2 In I S mode, the MSB of the ADC data is output on SDATO and changes on the first falling edge of BCLK following an LRCLK transition and may be sampled on the rising edge of BCLK. LRCLK is low during the left samples and high during the right samples. 1/fs L EF T C H AN N EL R IGH T C H AN N EL LRCLK BCLK 1 BCLK 1 BCLK SD ATO 1 2 3 M SB n-2 n-1 n LSB 1 M SB 2 3 n-2 n-1 n LSB 2 Figure 5 I S Mode Timing Diagram w PD, Rev 4.5, February 2012 14 WM8738 Production Data DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS MIN Passband SYMBOL 0.01 dB 0 Stopband -6dB TYP MAX UNIT 0.4535fs dB 0.01 dB 0.5fs Passband ripple Stopband 0.5465fs Stopband Attenuation f > 0.5465fs Group Delay -65 dB 22 Samples Table 2 Digital Filter Characteristics ADC FILTER RESPONSES 0.02 0 0.015 0.01 Response (dB) Response (dB) -20 -40 0.005 0 -0.005 -60 -0.01 -0.015 -80 -0.02 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 Figure 6 ADC Digital Filter Frequency Response 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 7 ADC Digital Filter Ripple ADC HIGH PASS FILTER The WM8738 has a selectable digital highpass filter to remove DC offsets. The filter response is characterised by the following polynomial. H(z) = 1 - z-1 1 - 0.9995z-1 Response (dB) 0 -5 -10 -15 0 0.0005 0.001 Frequency (Fs) 0.0015 0.002 Figure 8 ADC Highpass Filter Response w PD, Rev 4.5, February 2012 15 WM8738 Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS DVDD 1 DVDD AVDD + C1 C2 AVDD 9 C3 14 AGND DGND + C4 10 AGND LIN DVDD 4 R Hardware Control C5 8 R 1 R 4 C6 FMT 2 WM8738 DVDD 11 R NOHP RIN C 7 7 3 C 13 3 Audio Serial Data I/F 12 2 MCLK VREF 8 6 BCLK C9 C10 + LRCLK SDATO CAP AGND 5 C 11 C 12 + AGND Notes: 1. AGND and DGND should be connected as close to the WM8738 as possible. 2. C2, C3, C9 and C11 should be positioned as close to the WM8738 as possible. 3. Capacitor types should be carefully chosen. Capacitors with very low ESR are recommended for optimum performance. Figure 9 External Components Diagram RECOMMENDED EXTERNAL COMPONENTS VALUES COMPONENT REFERENCE SUGGESTED VALUE DESCRIPTION C1 and C4 10F C2 and C3 0.1F De-coupling for DVDD and AVDD C5 and C7 1F Analogue input AC coupling caps C6 and C8 4.7nF Analogue input filtering (RC) capacitor R2 and R3 10k Current limiting resistors De-coupling for DVDD and AVDD R1 and R4 680 Analogue input filtering (RC) resistor C9 0.1F Reference de-coupling capacitors for VREF pin C10 10F C11 0.1F C12 10F Reference de-coupling capacitors for CAP pin Table 3 External Components Description w PD, Rev 4.5, February 2012 16 WM8738 Production Data PACKAGE DIMENSIONS DM001.C D: 14 PIN SOIC 3.9mm Wide Body e B 14 8 H E 1 7 D L h x 45o A1 -CA C 0.10 (0.004) A A1 B C D E e H h L Dimensions (mm) MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.27 o o 8 0 REF: JEDEC.95, MS-012 Symbols SEATING PLANE Dimensions (Inches) MIN MAX 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.3367 0.3444 0.1497 0.1574 0.05 BSC 0.2284 0.2440 0.0099 0.0196 0.0160 0.0500 o o 0 8 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-012, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. w PD, Rev 4.5, February 2012 17 WM8738 Production Data IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: [email protected] w PD, Rev 4.5, February 2012 18 WM8738 Production Data REVISION HISTORY DATE REV ORIGINATOR CHANGES 26/09/11 4.5 JMacD Order codes changed from WM8738GED/V and WM8738GED/RV to WM8738CGED and WM8738CGED/R to reflect copper wire bonding and MSL change. 26/09/11 4.5 JMacD MSL changed from MSL2 to MSL1. 29/02/12 4.5 JMacD Operating Temp Range updated to -40 to +85 C. w o PD, Rev 4.5, February 2012 19