Ultralow Jitter Clock Generators and Distributors Maximize Data Converter SNR Linear Technology clock generators and distributors are ideal for producing the ultralow jitter clocks essential to clocking data converters with high signal-to-noise ratio (SNR). Maintaining low jitter on the data converter clock is fundamental to achieving outstanding SNR levels when digitizing or synthesizing direct RF or high analog frequencies. Our clocking solutions achieve the best data converter SNR yet are simple to synchronize. The simulation and design are streamlined by free, user friendly software tools that enable effortless design and accurately predict behavior. 2.7GHz Multi-Output Clock Synthesizer with Integrated VCO and Sync Functions 1.4GHz Clocking Solution with 18fsRMS Additive Jitter and EZSync R DIV R DIV REF SYNC EZSYNC LTC6950 REF VCO N DIV DEL 0-63 DIV 1-63 DEL 0-63 DIV 1-63 DEL 0-63 DIV 1-63 DEL 0-63 DIV 1-63 DEL 0-63 DIV 1-63 N DIV VCO P DIV LVPECL SYNC SYNC CONTROL LVDS/ CMOS LTC6951 DEL 0-250 DIV 1-512 DEL 0-255 DIV 1-512 DEL 0-255 DIV 1-512 DEL 0-255 DIV 1-512 DEL 0-255 DIV 1-512 CML LVDS Low Phase Noise Reference Buffer and Logic Converter Clock Distribution Solution with < 20fsRMS Additive Jitter and EZSync UP TO 1.8GHz DEL 0-63 DIV 1-63 SYNC EZSYNC DEL 0-63 DIV 1-63 DEL 0-63 DIV 1-63 FILTA Sine Wave or Logic Input LVPECL, LVDS OR CMOS FILTB IN+ LVPECL, LVDS OR CMOS IN– DC-300MHz LTC6954 LTC6957 Clock Generator and Distributor Selection Guide Part Number LTC®6950 LTC6951 LTC6954 LTC6957 Integrated Integrated PLL VCO ü ü ü Max Output Frequency (MHz) 1400 2700 1800 300 JESD204B # of Max Output Subclass 1 Outputs Divide Ratio EZSync™ ParallelSync™ Compatible 5 5 3 2 63 2048 63 1 ü ü ü L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and EZSync, ParallelSync, ClockWizard, LTC6951Wizard and EZ204Sync are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. ü ü Design, Simulation and Demo Board Control Tool ClockWizard™ LTC6951Wizard™ LTC6954_GUI Synchronization and the Generation of Large Clock Trees Many data converter applications require the generation of a large number of synchronized clocks. The LTC695x family of devices simplifies clock expansion and the creation of clock trees in systems with multiple daughter cards or with a large number of data converters. EZSync Linear Technology’s proprietary EZSync output synchronization method guarantees repeatable and deterministic phase relationships between all clock divider outputs on all EZSync supporting devices. EZSync synchronization is ideal for aligning the outputs of parallel and series (cascaded) connected devices. This scheme is useful when creating large clock distribution trees or when producing JESD204B compliant clocks. EZSync CONTROLLER REF CLK REF OUT4+ OUT4– 125MHz OUT3+ – 2000MHz OUT3 OUT0+ LTC6951 OUT0– SYNC OUT1+ OUT1– 1000MHz EZSync FOLLOWERS EZSync FOLLOWER 500MHz OUT2+ OUT2– IN+ IN– LTC6954-1 500MHz SYNC SYNC PULSE OUT0+ OUT0– 250MHz OUT1+ OUT1– 15.625MHz OUT2+ OUT2– 250MHz VCO+ VCO– EZSync Timing • >1ms sync pulse • < 10µs skew between SYNC pins VCO+ VCO– LV/CM+ LV/CM– 15.625MHz PECLO+ PECLO– 250MHz LTC6950 PECL1+ PECL1– SYNC PECL1– SYNC PECL2+ PECL2– EZSync CONTROLLER 250MHz PECL3+ PECL3– 15.625MHz REF CLK REF OUT4+ OUT4– OUT3+ OUT3– OUT1+ OUT1– OUT2+ OUT2– PECLO+ PECLO– PECL1+ SYNC PECL2+ PECL2– PECL3+ PECL3– VCO+ VCO– LTC6950 SYNC PULSE LV/CM+ LV/CM– LTC6950 PECL1– OUT0+ LTC6951 OUT0– SYNC A clock divider’s output produces random phases with respect to the other dividers every time the system is powered. This is true even if all dividers are inside the same IC. The majority of applications with multiple data converters require consistent and repeatable phase relationships between the clocks driving the data converters. EZSync synchronization solves this issue by a simple configuration via SPI in combination with driving a single CMOScompatible sync pulse with easily attainable timing requirements. PECL2+ PECL2– PECL3+ PECL3– VCO+ VCO– 15.625MHz PECLO+ PECLO– LTC6950 PECL1+ 11 REPEATABLE RISING-EDGE ALIGNED OUTPUTS EZSync FOLLOWER LV/CM+ LV/CM– SYNC LV/CM+ LV/CM– PECLO+ PECLO– PECL1+ PECL1– PECL2+ PECL2– PECL3+ PECL3– VCO+ VCO– LV/CM+ LV/CM– PECLO+ PECLO– PECL1+ LTC6950 PECL1– SYNC PECL2+ PECL2– PECL3+ PECL3– VCO+ VCO– LV/CM+ LV/CM– PECLO+ PECLO– PECL1+ LTC6950 PECL1– SYNC PECL2+ PECL2– PECL3+ PECL3– 25 REPEATABLE RISING-EDGE ALIGNED OUTPUTS ParallelSync The ParallelSync multichip parallel synchronization feature allows the outputs of multiple LTC6951 ICs to be retimed to the common reference clock. This permits reference-aligned synchronization in the reference clock domain with easy-to-meet nanosecond range setup and hold time requirements. This reference distribution parallel synchronization example makes use of the LTC6950 to distribute the reference clock with minimal additive jitter, and delivers the world class jitter performance of the LTC6951 on each of the daughter cards. All LTC6951 outputs on all daughter cards are retimed to the reference clock, making them all reliably synchronized with each other. REF CLK PECLO+ PECLO– VCO REF+ REF– OUT4+ OUT4– PECL1+ PECL1– LTC6950 SYNC OUT3+ OUT3– PECL2+ PECL2– OUT0+ OUT0– LTC6951 PECL3+ PECL3– OUT1+ OUT1– SYNC LV/CM+ LV/CM– OUT2+ OUT2– DAUGHTER CARD #1 DAUGHTER CARD #2 DAUGHTER CARD #3 DAUGHTER CARD #4 JESD204B Subclass 1 Support The EZ204Sync™ JESD204B subclass 1 compatible synchronization method builds on the previous two synchronization approaches. It enables the generation of the SYSREF and DEVCLK signals essential to this JEDEC standard across multiple parallel connected LTC6951 ICs along with any other EZSync compatible clock devices. The LTC6950 distributes the reference clock while appropriately dividing it down to optimize the phase noise performance of the following PLLs. The LTC6950 outputs are edge aligned via EZSync. The LTC6951 ParallelSync output retiming to the reference is enabled through the SPI port on all LTC6951 devices to ensure the DEVCLK and SYSREF signals are all synchronized. The SYSREF generating devices can be optionally powered down after JESD204B initialization to save power. REF+ REF– LTC6951 REF CLK LV/CM+ LV/CM– PECLO+ PECLO– VCO LTC6950 SYNC PULSE SYNC PECL1+ PECL1– PECL2+ PECL2– 50MHz SYNC 3.125MHz REF+ REF– PECL3+ PECL3– LTC6951 SYNC REF+ REF– LTC6951 SOFTWARE SYNC (SPI) SYNC REF+ REF– LTC6951 SYNC OUT4+ OUT4– OUT3+ OUT3– OUT0+ OUT0– OUT1+ OUT1– OUT2+ OUT2– OUT4+ OUT4– OUT3+ OUT3– OUT0+ OUT0– OUT1+ OUT1– OUT2+ OUT2– 250MHz DEVCLK SIGNALS 1GHz 15.625MHz SYSREF SIGNALS 62.5MHz OUT4+ OUT4– OUT3+ OUT3– OUT0+ OUT0– OUT1+ OUT1– OUT2+ OUT2– DEVCLK SIGNALS OUT4+ OUT4– OUT3+ OUT3– OUT0+ OUT0– OUT1+ OUT1– OUT2+ OUT2– SYSREF SIGNALS Control, Design, Simulate and Visualize with a Click of the Button The free GUIs offered by Linear Technology have the ability to design the loop filter components for the integrated PLL, predict the resulting phase noise and jitter performance, and plot the clock outputs in the time domain to illustrate the phase relationships between the outputs. These tools save time and help the system designer make optimal decisions. These tools also offer the means to control the demo board systems and simplify the evaluation process of the clock generator and distributor ICs. Set your frequency goals and find the loop filter component values of the PLL. This saves hours of design time and ensures the correct PLL parameters are chosen. Accurately simulate the expected phase noise to better predict the system behavior. Import and export phase noise graphs to simplify the simulation process of the complete system. Integrate the phase noise over a given bandwidth to arrive at the double sideband jitter value necessary to predict the data converter behavior. Plot the output clocks in the time domain to visualize the phase relationships based on the synchronization and delay settings. This ability immensely helps the system designer better understand the available synchronization methods and saves time during the hardware debug phase. www.linear.com/clocking n 1-800-4-LINEAR 0316