IDT 709179L12PFI

PRELIMINARY
IDT709179L
HIGH-SPEED 32K x 9
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Features
◆
◆
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 7.5/9/12ns (max.)
– Industrial: 9ns (max)
Low-power operation
– IDT709179L
Active: 1.2W (typ.)
Standby: 2.5mW (typ.)
Flow-Through or Pipelined output mode on either Port via
the FT/PIPE pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
◆
◆
◆
◆
additional logic
Full synchronous operation on both ports
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 7.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 12ns cycle time, 83MHz operation in Pipelined output mode
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 100-pin Thin Quad Flatpack (TQFP) package
Functional Block Diagram
R/WR
OER
R/WL
OEL
CE0L
CE1L
FT/PIPEL
0/1
1
0
0
1
0/1
FT/PIPER
I/O0R - I/O8R
I/O0L - I/O8L
I/O
Control
I/O
Control
A14L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
CE0R
CE1R
1
0
0/1
1
0
0/1
A14R
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A0R
CLKR
ADSR
CNTENR
CNTRSTR
5644 drw 01
AUGUST 2001
1
©2001 Integrated Device Technology, Inc.
DSC-5644/1
Preliminary
Industrial and Commercial Temperature Ranges
IDT709179L
High-Speed 32K x 9 Synchronous Pipelined Dual-Port Static RAM
Description
The IDT709179 is a high-speed 32K x 9 bit synchronous Dual-Port
RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times.
With an input data register, the IDT709179 has been optimized for
applications having unidirectional or bidirectional data flow in bursts.
An automatic power down feature, controlled by CE0 and CE1, permits
the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using IDT’s CMOS high-performance technology,
these devices typically operate on only 1.2W of power.
Index
NC
NC
A7L
A8L
A9L
A10L
A11L
A12L
A13L
A14L
NC
NC
VCC
NC
NC
NC
NC
CE0L
CE1L
CNTRSTL
R/WL
OEL
FT/PIPEL
NC
NC
NC
NC
NC
A6L
A5L
A4L
A3L
A2L
A1L
A0L
CNTENL
CLKL
ADSL
GND
GND
ADSR
CLKR
CNTENR
A0R
A1R
A2R
A3R
A4R
A5R
A6R
Pin Configurations(1,2,3)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
2
74
3
73
4
72
1
5
71
6
7
70
69
8
68
9
10
67
11
IDT709179PF
PN100-1(4)
66
100-Pin TQFP
Top View(5)
63
62
12
13
14
65
64
16
61
60
17
59
18
58
57
15
19
21
56
55
22
23
54
53
24
52
20
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R
NC
NC
GND
NC
NC
NC
NC
CE0R
CE1R
CNTRSTR
R/WR
OER
FT/PIPER
GND
NC
GND
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
GND
I/O1L
I/O0L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
NC
NC
5644 drw 02
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
6.42
,
Preliminary
Industrial and Commercial Temperature Ranges
IDT709179L
High-Speed 32K x 9 Synchronous Pipelined Dual-Port Static RAM
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enables
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L - A14L
A0R - A14R
Address
I/O0L - I/O8L
I/O0R - I/O8R
Data Input/Output
CLK L
CLKR
Clock
ADSL
ADSR
Address Strobe
CNTENL
CNTENR
Counter Enable
CNTRSTL
CNTRSTR
Counter Reset
FT/PIPEL
FT/PIPER
Flow-Through/Pipeline
VCC
Power
GND
Ground
5644 tbl 01
Truth Table I—Read/Write and Enable Control(1,2,3)
OE
CLK
CE0
CE1
R/W
I/O0-8
X
↑
H
X
X
High-Z
Deselected—Power Down
X
↑
X
L
X
High-Z
Deselected—Power Down
X
↑
L
H
L
DATAIN
Write
L
↑
L
H
H
DATAOUT
Read
H
X
L
H
X
High-Z
Mode
Outputs Disabled
5644 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
Truth Table II—Address Counter Control(1,2,6)
Address
Previous
Address
Addr
Used
CLK (6)
ADS
CNTEN
CNTRST
I/O (3)
An
X
An
↑
L (4)
X
H
D I/O (n)
X
An
An + 1
↑
H
L(5)
H
D I/O(n+ 1)
Co unte r E nab le d — Inte rnal A d d re s s g e ne ratio n
X
An + 1
An + 1
↑
H
H
H
D I/O(n+ 1)
E xte rnal A d d re s s B lo ck e d — Co unte r d is ab le d (A n + 1 re use d )
Ao
↑
X
(4)
X
X
X
L
D I/O(0)
MODE
E xte rnal A d d re s s Use d
Co unte r Re se t to A d d re ss 0
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0 and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other signals including CE0 and CE1.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.
6. While an external address is being loaded (ADS = VIL), R/W = VIH is recommended to ensure data is not written arbitrarily.
6.42
3
5644 tbl 03
Preliminary
Industrial and Commercial Temperature Ranges
IDT709179L
High-Speed 32K x 9 Synchronous Pipelined Dual-Port Static RAM
Recommended Operating
Recommended DC Operating
(1)
Temperature and Supply Voltage
Conditions
Grade
Commercial
Industrial
Symbol
Ambient
Temperature(2)
GND
Vcc
0OC to +70OC
0V
5.0V + 10%
-40OC to +85OC
0V
5.0V + 10%
Parameter
VCC
Supply Voltage
GND
Ground
VIH
Input High Voltage
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
2.2
____
(1)
6.0
V
5644 tbl 04
NOTES:
1. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
2. This is the parameter TA. This is the "instant on" case temperature.
(2)
VTERM
Rating
Terminal Voltage
with Respect
to GND
Commercial
& Industrial
Unit
-0.5 to +7.0
V
-0.5
0.8
V
5644 tbl 05
NOTES:
1. VTERM must not exceed V cc + 10%.
2. VIL > -1.5V for pulse width less than 10ns.
(TA = +25°C, f = 1.0MHz)
Symbol
CIN
COUT(3)
TBIAS
Temperature
Under Bias
-55 to +125
o
TSTG
Storage
Temperature
-65 to +150
o
IOUT
DC Output
Current
50
Input Low Voltage
____
Capacitance(1)
Absolute Maximum Ratings(1)
Symbol
VIL
(2)
C
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
Max.
Unit
VIN = 3dV
9
pF
VOUT = 3dV
10
pF
5644 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch from
0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
C
mA
5644 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range (VCC = 5.0V ± 10%)
709179L
Symbol
Parameter
(1)
Test Conditions
Min.
Max.
Unit
5
µA
|ILI|
Input Leakage Current
VCC = 5.5V, VIN = 0V to V CC
___
|ILO|
Output Leakage Current
CE0 = VIH or CE1 = VIL, VOUT = 0V to V CC
___
5
µA
VOL
Output Low Voltage
IOL = +4mA
___
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
___
V
5644 tbl 08
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
4
6.42
Preliminary
Industrial and Commercial Temperature Ranges
IDT709179L
High-Speed 32K x 9 Synchronous Pipelined Dual-Port Static RAM
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VCC = 5V ± 10%)
709179L7
Com'l Only
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Test Condition
Version
709179L9
Com'l
& Ind
709179L12
Com'l Only
Typ. (4)
Max.
Typ. (4)
Max.
Typ. (4)
Max.
Unit
mA
Dynamic Operating
Current
(Both Ports Active)
CEL and CER= V IL
Outputs Disabled
f = fMAX(1)
COM'L
L
275
465
250
400
230
355
IND
L
____
____
250
430
____
____
Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = VIH
f = fMAX(1)
COM'L
L
95
150
80
135
70
110
IND
L
____
____
80
160
____
____
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and
CE"B" = V IH (3)
Active Port Outputs
Disabled, f=fMAX(1)
COM'L
L
200
295
175
275
150
240
IND
L
____
____
175
295
____
____
Full Standby Current
(Both Ports CMOS Level Inputs)
Both Ports CE R and
CEL > VCC - 0.2V
V IN > VCC - 0.2V or
V IN < 0.2V, f = 0(2)
COM'L
L
0.5
3.0
0.5
3.0
0.5
3.0
IND
L
____
____
0.5
6.0
____
____
Full Standby Current
(One Port CMOS Level Inputs)
CE"A" < 0.2V and
CE"B" > VCC - 0.2V (5)
V IN > VCC - 0.2V or
V IN < 0.2V, Active Port
Outp uts Disabled , f = fMAX(1)
COM'L
L
190
290
170
270
140
225
IND
L
____
____
170
290
____
____
mA
mA
mA
mA
5644 tbl 09
NOTES:
1. At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC , using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. I CC DC(f=0) = 150mA (Typ).
5. CE X = VIL means CE0X = VIL and CE1X = VIH
CE X = VIH means CE0X = VIH or CE1X = VIL
CE X < 0.2V means CE0X < 0.2V and CE 1X > VCC - 0.2V
CE X > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6.42
5
IDT709179L
High-Speed 32K x 9 Synchronous Pipelined Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns Max.
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
Figures 1,2 and 3
5644 tbl 10
5V
5V
893Ω
893Ω
DATAOUT
DATAOUT
30pF
347Ω
5644 drw 04
5644 drw 05
Figure 1. AC Output Test load.
8
7
Figure 2. Output Test Load
(For tCKLZ , tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
- 10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
6
tCD1,
tCD2
(Typical, ns)
5
4
3
2
1
0
-1
5pF*
347Ω
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
5644 drw 06
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6
6.42
Preliminary
Industrial and Commercial Temperature Ranges
IDT709179L
High-Speed 32K x 9 Synchronous Pipelined Dual-Port Static RAM
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3) (VCC = 5V ± 10%, TA = 0°C to +70°C)
709179L7
Com'l Only
Symbol
tCYC1
Parameter
(2)
Clock Cycle Time (Flow-Through)
(2)
Min.
Max.
22
____
709179L9
Com'l
& Ind
Min.
Max.
25
____
15
____
12
____
12
____
709179L12
Com'l Only
Min.
Max.
Unit
30
____
ns
20
____
ns
12
____
ns
12
____
ns
ns
tCYC2
Clock Cycle Time (Pipelined)
12
____
tCH1
Clock High Time (Flow-Through)(2)
7.5
____
tCL1
(2)
7.5
____
5
____
6
____
8
____
ns
tCH2
Clock Low Time (Flow-Through)
(2)
Clock High Time (Pipelined)
(2)
tCL2
Clock Low Time (Pipelined)
5
____
6
____
8
____
tR
Clock Rise Time
____
3
____
3
____
3
ns
tF
Clock Fall Time
____
3
____
3
____
3
ns
4
____
4
____
4
____
ns
0
____
1
____
1
____
ns
4
____
4
____
ns
1
____
1
____
ns
4
____
4
____
ns
1
____
1
____
ns
ns
tSA
tHA
Address Setup Time
Address Hold Time
tSC
Chip Enable Setup Time
4
____
tHC
Chip Enable Hold Time
0
____
4
____
0
____
4
____
4
____
4
____
ns
tSW
tHW
tSD
R/W Setup Time
R/W Hold Time
Input Data Setup Time
tHD
Input Data Hold Time
0
____
1
____
1
____
tSAD
ADS Setup Time
4
____
4
____
4
____
ns
tHAD
ADS Hold Time
0
____
1
____
1
____
ns
tSCN
CNTEN Setup Time
4
____
4
____
4
____
ns
tHCN
CNTEN Hold Time
0
____
1
____
1
____
ns
tSRST
CNTRST Setup Time
4
____
4
____
4
____
ns
tHRST
CNTRST Hold Time
0
____
1
____
1
____
ns
____
9
____
12
____
12
ns
2
____
2
____
2
____
ns
1
7
1
7
1
7
ns
tOE
Output Enable to Data Valid
tOLZ
Output Enable to Output Low-Z(1)
tOHZ
(1)
tCD1
tCD2
Output Enable to Output High-Z
(2)
____
Clock to Data Valid (Flow-Through)
(2)
Clock to Data Valid (Pipelined)
18
____
20
____
25
ns
____
7.5
____
9
____
12
ns
ns
tDC
Data Output Hold After Clock High
2
____
2
____
2
____
tCKHZ
Clock High to Output High-Z(1)
2
9
2
9
2
9
ns
tCKLZ
Clock High to Output Low-Z(1)
2
____
2
____
2
____
ns
Port-to-Port Delay
tCWDD
Write Port Clock High to Read Data Delay
____
28
____
35
____
40
ns
tCCS
Clock-to-Clock Setup Time
____
10
____
15
____
15
ns
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device
characterization, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) to either the Left or Right ports when FT/PIPE = VIH. Flow-Through parameters (tCYC1, tCD1 ) apply when
FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER and FT/PIPEL.
6.42
7
5644 tbl 11
Preliminary
Industrial and Commercial Temperature Ranges
IDT709179L
High-Speed 32K x 9 Synchronous Pipelined Dual-Port Static RAM
Timing Waveform of Read Cycle for
Flow-Through Output (FT/PIPE"X" = VIL)(3,6)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
tSW
tHW
tSA
tHA
tSC
tHC
CE1
R/W
(5)
ADDRESS
An
An + 1
tCD1
tCKLZ
An + 3
tCKHZ (1)
Qn
DATAOUT
OE
An + 2
tDC
Qn + 1
(1)
tOHZ
Qn + 2
(1)
tOLZ
tDC
(1)
(2)
tOE
5644 drw 07
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE"X" = VIH)(3,6)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tSC
tHC
(4)
CE1
R/W
(5)
ADDRESS
tHC
tSW
tHW
tSA
tHA
An
An + 1
(1 Latency)
An + 2
tDC
tCD2
DATAOUT
Qn
tCKLZ
An + 3
Qn + 1
(1)
tOHZ
Qn + 2
(1)
tOLZ
(6)
(1)
(2)
OE
tOE
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL, CNTEN and CNTRST = VIH.
4. The output is disabled (High-Impedance state) by CE0 = V IH or CE1 = V IL following the next rising edge of the clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
6. "X" here denotes Left or Right port. The diagram is with respect to that port.
8
6.42
5644 drw 08
Preliminary
Industrial and Commercial Temperature Ranges
IDT709179L
High-Speed 32K x 9 Synchronous Pipelined Dual-Port Static RAM
Timing Waveform of a Bank Select Pipelined Read(1,2)
tCH2
tCYC2
tCL2
CLK
tSA
A0
ADDRESS(B1)
CE0(B1)
tHA
tSC
tHC
tSC
tHC
tCD2
Q0
A0
tSC
tCD2
Q3
tCKLZ
(3)
tCKHZ (3)
tHA
A6
A5
A4
A3
A2
A1
tSC
CE0(B2)
tCKHZ
Q1
tDC
tDC
ADDRESS(B2)
(3)
tCD2
DATAOUT(B1)
tSA
A6
A5
A4
A3
A2
A1
tHC
tHC
tCKHZ (3)
tCD2
DATAOUT(B2)
tCKLZ
(3)
tCD2
Q2
tCKLZ
Q4
(3)
5644 drw 09
Timing Waveform of Write with Port-to-Port Flow-Through Read(4,5,7)
CLK "A"
tSW tHW
R/W "A"
tSA
ADDRESS "A"
NO
MATCH
MATCH
tSD
DATAIN "A"
tHA
tHD
VALID
tCCS
(6)
CLK "B"
tCD1
R/W "B"
ADDRESS "B"
tSW
tHW
tSA
tHA
NO
MATCH
MATCH
tCWDD
(6)
tCD1
DATAOUT "B"
VALID
VALID
tDC
tDC
5644 drw 10
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT709179 for this waveform, and are setup for depth expansion in this example.
ADDRESS(B1) = ADDRESS(B2) in this situation.
2. OE and ADS = VIL; CE1(B1) , CE1(B2), R/W, CNTEN, and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. t CWDD does not apply in this case.
7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".
6.42
9
Preliminary
Industrial and Commercial Temperature Ranges
IDT709179L
High-Speed 32K x 9 Synchronous Pipelined Dual-Port Static RAM
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
tSC tHC
CE1
tSW tHW
R/W
(4)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
An + 3
An + 2
An + 4
tSD tHD
DATAIN
Dn + 2
tCD2
(2)
tCKHZ
(1)
(1)
tCKLZ
tCD2
Qn + 3
Qn
DATAOUT
(5)
READ
NOP
WRITE
READ
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Timing Waveforn of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
tCH2
tCYC2
tCL2
CLK
CE0
tSC tHC
CE1
tSW tHW
R/W
(4)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
tSD
DATAIN
An + 4
An + 5
tHD
Dn + 2
tCD2
(2)
An + 3
Dn + 3
tCKLZ(1)
tCD2
Qn
DATAOUT
Qn + 4
tOHZ(1)
OE
READ
WRITE
READ
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NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0 and ADS = V IL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
10
6.42
Preliminary
Industrial and Commercial Temperature Ranges
IDT709179L
High-Speed 32K x 9 Synchronous Pipelined Dual-Port Static RAM
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
tCH1
tCYC1
tCL1
CLK
CE0
tSC tHC
CE1
tSW tHW
R/W
tSW tHW
(4)
ADDRESS
tSA
An
tHA
An +1
An + 2
An + 4
An + 3
An + 2
tSD tHD
DATAIN
Dn + 2
tCD1
(2)
tCD1
Qn
DATAOUT
tCD1
tCD1
Qn + 3
Qn + 1
tDC
tCKHZ
(5)
NOP
READ
(1)
tCKLZ
WRITE
(1)
tDC
READ
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Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3)
tCYC1
tCH1
tCL1
CLK
CE0
tSC tHC
CE1
tSW tHW
R/W
tSW tHW
(4)
ADDRESS
tSA
An
tHA
An + 2
An +1
DATAIN
Dn + 2
(2)
DATAOUT
An + 3
An + 4
An + 5
tSD tHD
Dn + 3
tDC
tCD1
Qn
tOE
tCD1
(1)
tCKLZ
tOHZ(1)
tCD1
Qn + 4
tDC
OE
READ
WRITE
READ
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NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals.
3. CE 0 and ADS = VIL; CE 1, CNTEN, and CNTRST = V IH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
11
Preliminary
Industrial and Commercial Temperature Ranges
IDT709179L
High-Speed 32K x 9 Synchronous Pipelined Dual-Port Static RAM
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCH2
tCYC2
tCL2
CLK
tSA
ADDRESS
tHA
An
tSAD tHAD
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tCD2
DATAOUT
Qx - 1(2)
Qn + 2(2)
Qn + 1
Qn
Qx
Qn + 3
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
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Timing Waveform of Flow-Through Read with Address Counter Advance(1)
tCH1
tCYC1
tCL1
CLK
tSA
ADDRESS
tHA
An
tSAD tHAD
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tCD1
DATAOUT
Qx(2)
Qn
Qn + 1
Qn + 2
Qn + 3(2)
Qn + 4
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
READ
WITH
COUNTER
5644 drw 16
NOTES:
1. CE0 and OE = VIL; CE 1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output
remains constant for subsequent clocks.
12
6.42
Preliminary
Industrial and Commercial Temperature Ranges
IDT709179L
High-Speed 32K x 9 Synchronous Pipelined Dual-Port Static RAM
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 2
An + 1
An + 4
An + 3
tSAD tHAD
ADS
CNTEN
tSD tHD
Dn + 1
Dn
DATAIN
WRITE
EXTERNAL
ADDRESS
Dn + 1
Dn + 4
Dn + 3
Dn + 2
WRITE
WRITE
WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
5644 drw 17
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
tCH2
tCYC2
tCL2
CLK
tSA tHA
ADDRESS(4)
INTERNAL(3)
ADDRESS
An
Ax(6)
0
1
An + 2
An + 1
An + 1
An
tSW tHW
R/W
ADS
CNTEN
tSRST tHRST
CNTRST
tSD
tHD
D0
DATAIN
Qn
Q1
Q0
DATAOUT(5)
.
COUNTER(6)
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
READ
ADDRESS n+1
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NOTES:
1. CE0 and R/W = VIL; CE1 and CNTRST = VIH.
2. CE0 = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’ Address is written
to during this cycle.
6.42
13
Preliminary
Industrial and Commercial Temperature Ranges
IDT709179L
High-Speed 32K x 9 Synchronous Pipelined Dual-Port Static RAM
A Functional Description
Depth and Width Expansion
The IDT709179 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold
times on address, data, and all critical control inputs. All internal
registers are clocked on the rising edge of the clock signal, however,
the self-timed internal write pulse is independent of the LOW to HIGH
transition of the clock signal.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to stall the
operation of the address counters for fast interleaved memory applications.
CE0 = VIH or CE1 = VIL for one clock cycle will power down the
internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT709179's for depth expansion
configurations. When the Pipelined output mode is enabled, two cycles are
required with CE0 = VIL and CE1 = VIH to re-activate the outputs.
The IDT709179 features dual chip enables (refer to Truth Table I) in
order to facilitate rapid and simple depth expansion with no requirements
for external logic. Figure 4 illustrates how to control the various chip
enables in order to expand two devices in depth.
The IDT709179 can also be used in applications requiring expanded
width, as indicated in Figure 4. Since the banks are allocated at the
discretion of the user, the external controller can be set up to drive the
input signals for the various devices as required to allow for 18-bit
or wider applications.
A15
IDT709179
CE0
CE1
CE1
VCC
CE1
IDT709179
VCC
CE1
CE0
CE0
Control Inputs
CE0
Control Inputs
Control Inputs
IDT709179
IDT709179
Control Inputs
5644 drw 19
Figure 4. Depth and Width Expansion with IDT709179
14
6.42
CNTRST
CLK
ADS
CNTEN
R/W
OE
Preliminary
Industrial and Commercial Temperature Ranges
IDT709179L
High-Speed 32K x 9 Synchronous Pipelined Dual-Port Static RAM
Ordering Information
IDT
XXXXX
A
99
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
100-pin TQFP (PN100-1)
7
9
12
Commercial Only
Commercial & Industrial
Commercial Only
L
Low Power
Speed in nanoseconds
709179 288K (32K x 9-Bit) Synchronous Dual-Port RAM
5644 drw 20
Datasheet Document History
08/1/01:
Initial Data Sheet
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6.42
15
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