IDT IDT70V3389S4BCI

HIGH-SPEED 3.3V 64K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
◆
High-speed clock to data access
– Commercial: 4.2/5/6ns (max.)
– Industrial: 5/6ns (max)
◆
Pipelined output mode
◆
Counter enable and reset features
◆
Dual chip enables allow for depth expansion without
additional logic
◆
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
◆
◆
◆
◆
◆
IDT70V3389S
address inputs @ 133MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, single 3.3V (±150mV) power supply for
core
LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is
available for selected speeds
Available in a 128-pin Thin Quad Plastic Flatpack (TQFP),
208-pin fine pitch Ball Grid Array, and 256-pin Ball
Grid Array
Functional Block Diagram
UBL
UBR
LBL
LBR
R/WL
R/WR
B
W
0
L
CE0L
CE1L
B
W
1
L
B B
WW
1 0
R R
CE0R
CE1R
OEL
OER
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
64K x 18
MEMORY
ARRAY
I/O0 L - I/O1 7 L
Din_L
Din_R
I/O0R - I/O17R
CLKL
CLKR
A15L
A0L
CNTRSTL
ADSL
CNTENL
Counter/
Address
Reg.
ADDR_L
ADDR_R
Counter/
Address
Reg.
A 15R
A0R
CNTRSTR
ADSR
CNTENR
4832 tbl 01
APRIL 2001
1
©2001 Integrated Device Technology, Inc.
DSC 4832/8
.
IDT70V3389S
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Description:
The IDT70V3389 is a high-speed 64K x 18 bit synchronous Dual-Port
RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on control,
data, and address inputs provide minimal setup and hold times. The timing
latitude provided by this approach allows systems to be designed with very
short cycle times. With an input data register, the IDT70V3389 has been
optimized for applications having unidirectional or bidirectional data flow
Industrial and Commercial Temperature Ranges
in bursts. An automatic power down feature, controlled by CE0 and CE1,
permits the on-chip circuitry of each port to enter a very low standby power
mode.
The 70V3389 can support an Ioperating voltage of either 3.3V or 2.5V
on one or both ports, controllable by the OPT pins. The power supply for
the core of the device (VDD) remains at 3.3V.
Pin Configuration(1,2,3,4)
1
2
3
4
5
6
7
8
9
10 11
12
13 14
15
16 17
I/O9L
NC
VSS
NC
NC
NC
A12L
A8L
NC
VDD
CLKL
CNTENL
A4L
A0L
OPTL
NC
VSS
A
NC
VSS
NC
VSS
NC
A13L
A9L
NC
CE0L
VSS
ADSL
A5L
A1L
VSS
VDDQR
I/O8L
NC
B
VDDQL
I/O9R
VDDQR
VDD
NC
A14L
A10L
UBL
CE1L
VSS
R/WL
A6L
A2L
VDD
I/O8R
NC
VSS
C
NC
VSS
I/O10L
NC
A15L
A11L
A7L
LBL
VDD
OEL
CNTRSTL
A3L
VDD
NC
VDDQL
I/O7L
I/O7R
D
I/O11L
NC
VDDQR I/O10R
I/O6L
NC
VSS
NC
E
VDDQL
I/O11R
NC
VSS
VSS
I/O6R
NC
VDDQR
F
NC
VSS
I/O12L
NC
NC
VDDQL
I/O5L
NC
G
VDD
NC
VDDQR I/O12R
VDD
NC
VSS
I/O5R
H
VDDQL
VDD
VSS
VSS
VSS
VDD
VSS
VDDQR
J
I/O14R
VSS
I/O13R
VSS
I/O3R
VDDQL
I/O4R
VSS
K
NC
I/O14L
VDDQR
I/O13L
NC
I/O3L
VSS
I/O4L
L
VDDQL
NC
I/O15R
VSS
VSS
NC
I/O2R
VDDQR
M
NC
VSS
NC
I/O15L
I/O1R
VDDQL
NC
I/O2L
N
I/O16R
I/O16L
VDDQR
NC
NC
NC
A12R
A8R
NC
VDD
CLKR CNTEN R
A4R
NC
I/O1L
VSS
NC
P
VSS
NC
I/O17R
NC
NC
A13R
A9R
NC
CE0R
VSS
ADSR
A5R
A1R
VSS
VDDQL
I/O0R
VDDQR
R
NC
I/O17L
VDDQL
VSS
NC
A14R
A10R
UBR
CE1R
VSS
R/WR
A6R
A2R
VSS
NC
VSS
NC
T
VSS
NC
VDD
NC
A15R
A11R
A7R
LBR
VDD
OER CNTRSTR
A3R
A0R
VDD
OPTR
NC
I/O0L
U
70V3389BF
BF-208(5)
208-Pin fpBGA
Top View(6)
4832 tbl 02
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT70V3389S
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3,4) (con't.)
70V3389BC
BC-256(5)
256-Pin BGA
Top View(6)
A1
NC
B1
NC
C1
NC
D1
NC
E1
A2
NC
B2
NC
C2
I/O9L
D2
I/O9R
E2
I/O10R I/O10L
F2
F1
I/O11L
G1
NC
H1
NC
J1
NC
G2
NC
H2
I/O12R
J2
A3
NC
B3
NC
C3
VSS
D3
NC
E3
NC
F3
A4
NC
B4
NC
C4
NC
D4
VDD
E4
VDDQL
F4
I/O11R VDDQL
G3
G4
I/O12L VDDQR
H3
NC
J3
H4
NC
L1
I/O15L
M1
K2
NC
L2
NC
M2
I/O16R I/O16L
N1
NC
P1
NC
R1
NC
T1
NC
N2
I/O17R
P2
I/O17L
R2
NC
T2
NC
K3
J4
K4
I/O14L VDDQL
L3
L4
I/O15R VDDQR
M3
NC
N3
NC
P3
NC
R3
NC
T3
NC
A6
A14L
A11L
B5
A15L
C5
A13L
D5
M4
VDDQR
N4
VDD
P4
NC
R4
NC
T4
NC
B6
A12L
C6
A10L
D6
A7
A8L
B7
A9L
C7
A7L
D7
A8
A9
NC
CE1L
B9
B8
UBL
C8
LBL
D9
D8
A11
OEL CNTENL
B10
B11
CE0L R/WL CNTRSTL
C9
NC
A10
C10
C11
CLKL ADSL
D10
D11
A12
A5L
B12
A4L
C12
A6L
D12
A13
A2L
B13
A1L
C13
A3L
D13
VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD
E5
VDD
F5
VDD
G5
VSS
H5
VDDQR VSS
I/O13L I/O14R I/O13R VDDQL
K1
A5
J5
VSS
K5
VSS
L5
VDD
M5
VDD
N5
E6
VDD
F6
VSS
G6
VSS
H6
VSS
J6
VSS
K6
VSS
L6
VSS
M6
VDD
N6
E7
VSS
F7
VSS
G7
VSS
H7
VSS
J7
VSS
K7
VSS
L7
VSS
M7
VSS
N7
E8
E9
VSS
VSS
F9
F8
VSS
G8
VSS
G9
VSS
H8
VSS
H9
VSS
J8
VSS
J9
VSS
K8
VSS
K9
VSS
L8
VSS
L9
VSS
M8
VSS
M9
VSS
N8
VSS
N9
E10
VSS
F10
VSS
G10
VSS
H10
VSS
J10
VSS
K10
VSS
L10
VSS
M10
VSS
N10
E11
VDD
F11
VSS
G11
VSS
H11
VSS
J11
VSS
K11
VSS
L11
VSS
M11
VDD
N11
E12
F12
A13R
R5
A15R
T5
A14R
P6
A10R
R6
A12R
T6
A11R
P7
A7R
R7
A9R
T7
A8R
P9
P8
NC
LBR
R9
R8
UBR
T8
P11
CLKR ADSR
R10
R11
CE0R R/WR CNTRSTR
T9
NC
P10
CE1R
T10
T11
OER CNTENR
F13
A0L
B14
VDD
C14
OPTL
D14
NC
E14
NC
F14
VDD VDDQR I/O6R
G12
VSS
H12
VSS
J12
VSS
K12
VSS
L12
VDD
M12
VDD
N12
VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL
P5
E13
VDD VDDQR
A14
P12
A6R
R12
A4R
T12
A5R
G13
G14
VDDQL I/O5L
H13
VDDQL
J13
H14
NC
J14
A15
A16
NC
B16
B15
NC
VDDQR
L13
K14
NC
L14
VDDQL I/O2L
M13
M14
VDDQL I/O1R
N13
VDD
P13
A3R
R13
A1R
T13
A2R
N14
NC
P14
NC
R14
OPTR
T14
A0R
NC
C16
C15
NC
D15
I/O8L
D16
NC
I/O8R
E16
E15
I/O7L
F15
I/O7R
F16
NC
G15
I/O6L
G16
NC
NC
H16
H15
NC
I/O5R
J16
J15
VDDQR I/O4R I/O3R
K13
NC
I/O4L
K16
K15
NC
L15
I/O3L
L16
NC
I/O2R
M16
M15
I/O1L
NC
N16
N15
I/O0R
P15
NC
P16
NC
I/O0L
R16
R15
NC
T15
NC
,
T16
NC
NC
4832 drw 02c
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
3
,
IDT70V3389S
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
70V3389PRF
PK-128(5)
128-Pin TQFP
Top View(6)
A 13R
A 12R
A 11R
A 10R
A9R
A8R
A7R
UBR
LBR
CE1R
CE0R
VDD
VDD
VSS
VSS
CLKR
OER
R/WR
ADSR
CNTENR
CNTRSTR
A6R
A5R
A4R
A3R
A2R
VDDQL
VSS
IO10L
IO10R
VDDQR
VSS
IO11L
IO11R
IO12L
IO12R
VDD
VDD
VSS
VSS
IO13R
IO13L
IO14R
IO14L
IO15R
IO15L
VDDQL
VSS
IO16R
IO16L
VDDQR
VSS
IO17R
IO17L
NC
NC
A15R
A14R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
A14L
A15L
VSS
NC
IO9L
IO9R
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
A13L
A12L
A11L
A10L
A9L
A8L
A7L
UBL
LBL
CE1L
CE0L
VDD
VDD
VSS
VSS
CLKL
OEL
R/WL
ADSL
CNTENL
CNTRST L
A6L
A5L
A4L
A3L
A2L
Pin Configuration(1,2,3,4) (con't.)
A1L
A0L
OPTL
NC (VSS)(7)
IO8L
IO8R
NC (VSS)(7)
VSS
VDDQL
IO7L
IO7R
VSS
VDDQR
IO6L
IO6R
IO5L
IO5R
VDD
VDD
VSS
VSS
IO4R
IO4L
IO3R
IO3L
IO2R
IO2L
VSS
VDDQL
IO1R
IO1L
VSS
VDDQR
IO0R
IO0L
OPTR
A0R
A1R
4832 drw 02a
.
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 14mm x 20mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
7. In the 70V3379 (32K x 18) and 70V3389 (64K x 18), pins 96 and 99 are NC. The upgrade devices 70V3399 (128K x 18) and 70V3319 (256K x 18) assign
these pins as VSS. Customers who plan to take advantage of the upgrade path should treat these pins as VSS on the 70V3379 and 70V3389. If no upgrade is
needed, the pins can be treated as NC.
6.42
4
IDT70V3389S
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enables
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L - A15L
A0R - A15R
Address
I/O0L - I/O17L
I/O0R - I/O17R
Data Input/Output
CLKL
CLK R
Clock
ADSL
ADSR
Address Strobe Enable
CNTENL
CNTENR
Counter Enable
CNTRSTL
CNTRSTR
Counter Reset
UBL - LBL
UBR - LBR
Byte Enables (9-bit bytes)
VDDQL
VDDQR
Power (I/O Bus) (3.3V or 2.5V)(1)
OPTL
OPTR
Option for selecting VDDQX(1,2)
VDD
Power (3.3V)(1)
VSS
Ground (0V)
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
4832 tbl 01
Truth Table I—Read/Write and Enable Control(1,2,3)
OE
CLK
CE0
CE1
UB
LB
R/W
Upper Byte
I/O9-18
Lower Byte
I/O0-8
X
↑
L
H
H
H
X
High-Z
High-Z
X
↑
L
H
H
L
L
High-Z
DIN
Write to Lower Byte Only
X
↑
L
H
L
H
L
DIN
High-Z
Write to Upper Byte Only
X
↑
L
H
L
L
L
DIN
DIN
L
↑
L
H
H
L
H
High-Z
DOUT
Read Lower Byte Only
L
↑
L
H
L
H
H
DOUT
High-Z
Read Upper Byte Only
L
↑
L
H
L
L
H
DOUT
DOUT
Read Both Bytes
H
↑
L
H
L
L
X
High-Z
High-Z
Outputs Disabled
MODE
All Bytes Deselected
Write to Both Bytes
4832 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = VIH.
3. OE is an asynchronous input signal.
6.42
5
IDT70V3389S
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Truth Table II—Address Counter Control(1,2)
Address
X
Previous
Address
X
Addr
Used
CLK
0
↑
ADS
CNTEN
X
CNTRST
I/O(3)
MODE
X
(4)
L
DI/O (0)
Counter Reset to Address 0
An
X
An
↑
L
X
H
DI/O (n)
External Address Used
An
Ap
Ap
↑
H
H
H
DI/O (p)
External Address Blocked—Counter disabled (Ap reused)
X
Ap
Ap + 1
↑
H
L(5)
H
DI/O (p+1)
(4)
Counter Enabled—Internal Address generation
4832 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.
3. Outputs are in Pipelined mode: the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other memory control signals including CE0, CE 1 and BEn
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
Recommended Operating
Temperature and Supply Voltage(1,2)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Ambient
Temperature
GND
VDD
VDD
Core Supply Voltage
3.15
3.3
3.45
V
0OC to +70OC
0V
3.3V + 150mV
VDDQ
I/O Supply Voltage (3)
2.375
2.5
2.625
V
-40OC to +85OC
0V
3.3V + 150mV
VSS
Ground
0
0
0
Grade
Commercial
Industrial
Recommended DC Operating
Conditions with VDDQ at 2.5V
4832 tbl 04
NOTES:
1. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
2. This is the parameter TA. This is the "instant on" case temperature.
V
(2)
VIH
Input High Voltage (3)
(Address & Control Inputs)
1.7
____
V DDQ + 125mV
VIH
Input High Voltage - I/O(3)
1.7
____
V DDQ + 125mV (2)
V
VIL
Input Low Voltage
-0.3(1)
____
0.7
V
V
4832 tb l 05a
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDDQ + 125mV.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIL (0V), and V DDQX for that port must be
supplied as indicated above.
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
& Industrial
Unit
VTERM(2)
Terminal Voltage
with Respect to
GND
-0.5 to +4.6
V
TBIAS
Temperature
Under Bias
-55 to +125
o
Recommended DC Operating
Conditions with VDDQ at 3.3V
Symbol
TSTG
Storage
Temperature
IOUT
DC Output Current
-65 to +150
50
C
o
C
mA
6.42
6
Min.
Typ.
Max.
Unit
VDD
Core Supply Voltage
3.15
3.3
3.45
V
VDDQ
I/O Supply Voltage
(3)
3.15
3.3
3.45
V
VSS
Ground
0
0
0
VDDQ + 150mV
(2)
V
V
VIH
Input High Voltage
(Address & Control Inputs)(3)
2.0
____
VIH
Input High Voltage - I/O(3)
2.0
____
VDDQ + 150mV(2)
V
____
0.8
V
4832 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or
4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV.
Parameter
VIL
Input Low Voltage
(1)
-0.3
4832 tbl 05b
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDDQ + 150mV.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIH (3.3V), and VDDQX for that port must be
supplied as indicated above.
IDT70V3389S
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Capacitance(1)
(TA = +25°C, F = 1.0MHZ) TQFP ONLY
Symbol
CIN
Parameter
Input Capacitance
(3)
COUT
Output Capacitance
Conditions(2)
Max.
Unit
VIN = 3dV
8
pF
VOUT = 3dV
10.5
pF
4832 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)
70V3389S
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|ILI|
Input Leakage Current(1)
VDDQ = Max., VIN = 0V to V DDQ
___
10
µA
|ILO|
Output Leakage Current
CE0 = VIH or CE1 = VIL, VOUT = 0V to V DDQ
___
10
µA
IOL = +4mA, VDDQ = Min.
___
0.4
V
V
V
VOL (3.3V)
Output Low Voltage
(2)
(2)
IOH = -4mA, VDDQ = Min.
2.4
___
VOL (2.5V)
Output Low Voltage
(2)
IOL = +2mA, VDDQ = Min.
___
0.4
VOH (2.5V)
Output High Voltage (2)
IOH = -2mA, VDDQ = Min.
2.0
___
VOH (3.3V)
Output High Voltage
V
4832 tbl 08
NOTE:
1. At VDD < - 2.0V input leakages are undefined.
2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.4 for details.
6.42
7
IDT70V3389S
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV)
70V3389S4
Com 'l Only
Sym bol
IDD
ISB1
ISB2
ISB3
ISB4
Param eter
Test Condition
Version
70V3389S5
Com 'l
& Ind
70V3389S6
Com 'l
& Ind
Typ. (4)
Max.
Typ. (4)
Max.
Typ. (4)
Max.
Unit
mA
Dynam ic Ope rating
Current (Bo th
P orts A ctive )
CEL and CER= V IL ,
Outputs Disab led ,
f = fMAX (1)
COM 'L
S
375
460
285
360
245
310
IND
S
____
____
285
415
245
360
S tand by Current
(Bo th P orts - TTL
Le ve l Inp uts )
CEL = CER = V IH
f = fMAX (1)
COM 'L
S
145
190
105
145
95
125
IND
S
____
____
105
175
95
150
S tand by Current
(One Po rt - TTL
Le ve l Inp uts )
CE"A" = V IL and CE"B" = V IH (5)
A ctiv e P ort Outp uts Dis ab le d,
f= fMAX(1)
COM 'L
S
265
325
190
260
175
225
IND
S
____
____
190
300
175
260
Full S tandb y Current
(B oth P orts - CM OS
Le ve l Inp uts )
B oth P orts CEL and
CER > V DD - 0.2V, V IN > V DD - 0.2V
o r V IN < 0.2V , f = 0 (2)
COM 'L
S
6
15
6
15
6
15
IND
S
____
____
6
30
6
30
Full S tandb y Current
(One Po rt - CM OS
Le ve l Inp uts )
CE"A" < 0.2V and CE"B" > V DD - 0.2V (5) COM 'L
V IN > V DD - 0.2V or V IN < 0.2V, Ac tive
IND
P ort, Outp uts Disable d , f = f MAX(1)
S
265
325
180
260
170
225
S
____
____
180
300
170
260
mA
mA
mA
mA
4832 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC , using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC (f=0) = 120mA (Typ).
5. CEX = V IL means CE 0X = V IL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
6.42
8
IDT70V3389S
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
2.5V
Input Pulse Levels (Address & Controls)
GND to 3.0V/GND to 2.35V
Input Pulse Levels (I/Os)
GND to 3.0V/GND to 2.35V
833Ω
3ns
Input Rise/Fall Times
Input Timing Reference Levels
1.5V/1.25V
Output Reference Levels
1.5V/1.25V
DATAOUT
5pF*
770Ω
Figures 1, 2, and 3
Output Load
4832 tbl 10
,
3.3V
50Ω
50Ω
DATAOUT
1.5V/1.25
10pF
(Tester)
590Ω
,
DATAOUT
4832 drw 03
435Ω
5pF*
Figure 1. AC Output Test load.
4832 drw 04
Figure 2. Output Test Load
(For tCKLZ , tCKHZ, tOLZ, and tOHZ ).
*Including scope and jig.
10.5pF is the I/O capacitance of this
device, and 10pF is the AC Test Load
Capacitance.
7
6
5
4
∆tCD
(Typical, ns) 3
2
1
•
20.5
•
30
•
•
50
80
100
200
-1
Capacitance (pF)
4832 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
9
,
IDT70V3389S
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
Temperature Range (Read and Write Cycle Timing)(1,2)
(VDD = 3.3V ± 150mV, TA = 0°C to +70°C)
70V3389S4
Com'l Only
Symbol
tCYC2
tCH2
tCL2
Parameter
Clock Cycle Time (Pipelined)
Clock High Time (Pipelined)
Clock Low Time (Pipelined)
Min.
Max.
7.5
____
3
____
3
____
70V3389S5
Com'l
& Ind
70V3389S6
Com'l
& Ind
Min.
Max.
10
____
Min.
Max.
Unit
12
____
4
____
ns
5
____
4
____
ns
5
____
3
____
ns
3
____
3
ns
tR
Clock Rise Time
____
tF
Clock Fall Time
____
3
____
3
____
3
ns
tSA
Address Setup Time
1.8
____
2.0
____
2.0
____
ns
tHA
Address Hold Time
0.7
____
0.7
____
1.0
____
ns
tSC
Chip Enable Setup Time
1.8
____
2.0
____
2.0
____
ns
0.7
____
0.7
____
1.0
____
ns
1.8
____
2.0
____
2.0
____
ns
0.7
____
1.0
____
ns
tHC
tSB
Chip Enable Hold Time
Byte Enable Setup Time
tHB
Byte Enable Hold Time
0.7
____
tSW
R/W Setup Time
1.8
____
2.0
____
2.0
____
ns
tHW
R/W Hold Time
0.7
____
0.7
____
1.0
____
ns
tSD
Input Data Setup Time
1.8
____
2.0
____
2.0
____
ns
tHD
Input Data Hold Time
0.7
____
0.7
____
1.0
____
ns
tSAD
ADS Setup Time
1.8
____
2.0
____
2.0
____
ns
tHAD
ADS Hold Time
0.7
____
0.7
____
1.0
____
ns
tSCN
CNTEN Setup Time
1.8
____
2.0
____
2.0
____
ns
tHCN
CNTEN Hold Time
0.7
____
0.7
____
1.0
____
ns
tSRST
CNTRST Setup Time
1.8
____
2.0
____
2.0
____
ns
tHRST
CNTRST Hold Time
0.7
____
0.7
____
1.0
____
ns
Output Enable to Data Valid
____
4
____
5
____
6
ns
tOE
(1)
tOLZ
Output Enable to Output Low-Z
0
____
0
____
0
____
ns
tOHZ
Output Enable to Output High-Z
1
4
1
4.5
1
5
ns
tCD2
Clock to Data Valid (Pipelined)
____
4.2
____
5
____
6
ns
____
1
____
1
____
ns
tDC
Data Output Hold After Clock High
1
tCKHZ
Clock High to Output High-Z
1
3
1
4.5
1.5
6
ns
1
____
1
____
1
____
ns
6
____
8
____
10
____
ns
tCKLZ
Clock High to Output Low-Z
Port-to-Port Delay
tCO
Clock-to-Clock Offset
NOTES:
1. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE).
2. These values are valid for either level of VDDQ (3.3V/2.5V). See page 4 for details on selecting the desired I/O voltage levels for each port.
6.42
10
4830 tbl 11
IDT70V3389S
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation(2)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tSC
tHC
tHC
(3)
CE1
tSB
tHB
tSB
UB, LB(0-3)
tHB
(5)
R/W
(4)
ADDRESS
tSW
tHW
tSA
tHA
An
An + 1
(1 Latency)
An + 2
tDC
tCD2
DATAOUT
Qn
tCKLZ
OE
An + 3
Qn + 1
Qn + 2
(5)
(1)
tOHZ
tOLZ
(1)
tOE
NOTES:
4832 drw 06
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and CNTRST = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB, LB = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If UB or LB was HIGH, then the appropriate Byte of DATA OUT for Qn + 2 would be disabled (High-Impedance state).
Timing Waveform of a Multi-Device Pipelined Read(1,2)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
A0
ADDRESS(B1)
tSC
tHC
CE0(B1)
tSC
tHC
tCD2
tCD2
Q0
DATAOUT(B1)
tCKHZ
A1
tSC
tCKHZ
A6
A5
A4
A3
A2
tSC
CE0(B2)
Q3
tCKLZ
tDC
tHA
A0
ADDRESS(B2)
tCD2
Q1
tDC
tSA
A6
A5
A4
A3
A2
A1
tHC
tHC
tCD2
DATAOUT(B2)
tCKHZ
tCD2
Q4
Q2
tCKLZ
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3389 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1) , CE1(B2), R/W, CNTEN, and CNTRST = VIH.
6.42
11
tCKLZ
4832 drw 07
IDT70V3389S
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2)
CLKL
tSW
tHW
tSA
tHA
R/WL
ADDRESSL
NO
MATCH
MATCH
tSD
DATAINL
tHD
VALID
tCO(3)
CLKR
tCD2
R/WR
ADDRESSR
tSW
tHW
tSA
tHA
NO
MATCH
MATCH
DATAOUTR
VALID
tDC
4832 drw 08
NOTES:
1. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = V IH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from right port read is not valid until following right port clock cycle (ie, time from write to valid read on opposite port will
be tCO + 2 tCYC2 + tCD2 ). If tCO > minimum, then data from right port read is available on first right port clock cycle (ie, time from write to valid read on opposite
port will be tCO + tCYC + tCD2 ).
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(2)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
tSB
tHB
CE1
UB, LB
tSW tHW
R/W
(3)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
An + 3
An + 2
An + 4
tSD tHD
DATAIN
Dn + 2
tCD2
(1)
tCKHZ
tCKLZ
tCD2
Qn + 3
Qn
DATAOUT
READ
(4)
NOP
WRITE
READ
4832 drw 09
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
12
IDT70V3389S
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)(2)
tCH2
tCYC2
tCL2
CLK
CE0
tSC
tHC
tSB
tHB
CE1
UB, LB
tSW tHW
R/W
(3)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
tSD
DATAIN
Dn + 2
tCD2
(1)
Qn
DATAOUT
An + 4
An + 3
An + 5
tHD
Dn + 3
tCKLZ
tCD2
Qn + 4
(4)
tOHZ
OE
READ
WRITE
READ
4832 drw 10
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE 0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH .
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use
only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCH2
tCYC2
tCL2
CLK
tSA
ADDRESS
tHA
An
tSAD tHAD
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tCD2
DATAOUT
Qx - 1(2)
Qn + 2(2)
Qn + 1
Qn
Qx
Qn + 3
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
READ
WITH
COUNTER
4832 drw 11
NOTES:
1. CE0, OE, UB, LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = V IL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
the data output remains constant for subsequent clocks.
6.42
13
IDT70V3389S
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance(1)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 2
An + 1
An + 4
An + 3
tSAD tHAD
ADS
tSCN tHCN
CNTEN
tSD tHD
Dn + 1
Dn
DATAIN
WRITE
EXTERNAL
ADDRESS
Dn + 1
Dn + 4
Dn + 3
Dn + 2
WRITE
WRITE
WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
4832 drw 12
Timing Waveform of Counter Reset(2)
tCH2
tCYC2
tCL2
CLK
tSA tHA
(4)
An
ADDRESS
INTERNAL(3)
ADDRESS
Ax
0
1
An + 2
An + 1
An
An + 1
tSW tHW
R/W
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tSRST tHRST
CNTRST
tSD
tHD
D0
DATAIN
(5)
Q1
Q0
DATAOUT
(6)
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
Qn
READ
ADDRESS n+1
NOTES:
4832 drw 13
1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
2. CE0, UB, LB = V IL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle: ADDR 0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6.42
14
IDT70V3389S
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Functional Description
Depth and Width Expansion
The IDT70V3389 provides a true synchronous Dual-Port Static RAM
interface. Registered inputs provide minimal set-up and hold times on
address, data, and all critical control inputs. All internal registers are clocked
on the rising edge of the clock signal, however, the self-timed internal write
pulse is independent of the LOW to HIGH transition of the clock signal.
An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall
the operation of the address counters for fast interleaved
memory applications.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70V3389s for depth expansion configurations. Two cycles are required with CE0 LOW and CE1
HIGH to re-activate the outputs.
The IDT70V3389 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70V3389 can also be used in applications requiring expanded
width, as indicated in Figure 4. Through combining the control signals, the
devices can be grouped as necessary to accommodate applications
needing 36-bits or wider.
A16
CE0
IDT70V3389
CE1
CE1
CE1
VDD
IDT70V3389
VDD
CE1
CE0
CE0
Control Inputs
CE0
Control Inputs
Control Inputs
IDT70V3389
IDT70V3389
Control Inputs
4832 drw 14
Figure 4. Depth and Width Expansion with IDT70V3389
6.42
15
UB, LB
R/W,
OE,
CLK,
ADS,
CNTRST,
CNTEN
.
IDT70V3389S
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT
XXXXX
A
99
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BF
PRF
BC
208-pin fpBGA (BF-208)
128-pin TQFP (PK-128)
256-pin BGA (BC-256)
4
5
6
Commercial Only
Commercial & Industrial
Commercial & Industrial
S
Standard Power
Speed in nanoseconds
70V3389 1Mbit (64K x 18-Bit) Synchronous Dual-Port RAM
4832 drw 15A
6.42
16
.
IDT70V3389S
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Datasheet Document History
1/18/99:
3/15/99:
4/28/99:
6/8/99:
6/15/99:
7/14/99:
8/4/99:
10/1/99:
11/12/99:
2/28/00:
5/1/00:
1/10/01:
4/10/01:
Initial Public Release
Page 9 Additional notes
Added fpBGA paclage
Page 2 Changed package body height from 1.5mm to 1.4mm
Page 5 Deleted note 6 for Table II
Page 2 Corrected pin T3 to VDDQL
Page 6 Improved power numbers
Upgraded speed to 133MHz, added 2.5V I/O capability
Replaced IDT logo
Added new BGA package, added full 2.5V interface capability
Page 2 Added ball pitch
Page 3 Renamed pins
Page 6 Made corrections to Truth Table
Page 9 Changed Ω numbers in figure 2
Page 4 Added information to pin and pin notes
Page 6 Increated storage temperature parameter
Clarified TA Parameter
Page 8 DC Electrical parameters–changed wording from "open" to "disabled"
Removed note 7 on DC Characteristics table
Removed Preliminary status
Added Industrial Temperature Ranges and removed related notes
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for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
17
for Tech Support:
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[email protected].com