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ispLSI 2064VE
3.3V In-System Programmable
High Density SuperFAST™ PLD
Functional Block Diagram
• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 64 and 32 I/O Pin Versions, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible with
ispLSI 2064V Devices
Input Bus
Output Routing Pool (ORP)
Input Bus
Output Routing Pool (ORP)
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 280MHz Maximum Operating Frequency
— tpd = 3.5ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
A1
A2
Logic
Array
B3
B2
D Q
GLB
B4
D Q
B1
D Q
D Q
Input Bus
Global Routing Pool
(GRP)
A0
• 3.3V LOW VOLTAGE 2064 ARCHITECTURE
— Interfaces with Standard 5V TTL Devices
B5
Output Routing Pool (ORP)
B6
B7
B0
A3
A5
A4
A6
A7
Output Routing Pool (ORP)
Input Bus
0139A/2064V
• IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of Wired-OR
or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
Description
The ispLSI 2064VE is a High Density Programmable
Logic Device available in 64 and 32 I/O-pin versions. The
device contains 64 Registers, four Dedicated Input pins,
three Dedicated Clock Input pins, two dedicated Global
OE input pins and a Global Routing Pool (GRP). The
GRP provides complete interconnectivity between all of
these elements. The ispLSI 2064VE features in-system
programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary
Scan Testable. The ispLSI 2064VE offers non-volatile
reprogrammability of the logic, as well as the interconnect, to provide truly reconfigurable systems.
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
The basic unit of logic on the ispLSI 2064VE device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 2064VE device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
• LEAD-FREE PACKAGE OPTIONS
Copyright © 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2064ve_09
1
August 2004
Specifications ispLSI 2064VE
Functional Block Diagram
Generic Logic
Blocks (GLBs)
B7
A6
I/O 28
I/O 29
I/O 30
I/O 31
Input Bus
I/O 24
I/O 25
I/O 26
I/O 27
BSCAN
I/O 20
I/O 21
I/O 22
I/O 23
Output Routing Pool (ORP)
I/O 18
I/O 19
RESET
I/O 16
I/O 17
TDI/IN 0
TDO/IN 1
TDO/IN 2
B2
A2
B1
A3
B0
A5
BSCAN
The 64-I/O 2064VE contains 64 I/O cells, while the 32I/O version contains 32 I/O cells. Each I/O cell is directly
connected to an I/O pin and can be individually programmed to be a combinatorial input, output or
bi-directional I/O pin with 3-state control. The signal
levels are TTL compatible voltages and the output drivers
can source 4 mA or sink 8 mA. Each output can be
programmed independently for fast or slow output slew
rate to minimize overall output switching noise. Device
pins can be safely driven to 5-Volt signal levels to support
mixed-voltage systems.
I/O 19
I/O 18
I/O 17
I/O 16
GOE0/IN 3
A4
A6
A7
Output Routing Pool (ORP)
0139B/2064VE
I/O 22
I/O 21
I/O 20
Input Bus
Input Bus
Input Bus
TCK/IN 3
A7
Global Routing Pool
(GRP)
A1
Input Bus
I/O 8
A5
CLK 0
CLK 1
CLK 2
A4
I/O 4
I/O 5
I/O 6
I/O 7
I/O 35
I/O 34
I/O 33
I/O 32
B3
Output Routing Pool (ORP)
B0
B4
TMS/IN 2
CLK 0
CLK 1
CLK 2
A3
I/O 39
I/O 38
I/O 37
I/O 36
B5
A0
I/O 9
I/O 10
I/O 11
B1
I/O 43
I/O 42
I/O 41
I/O 40
B6
I/O 23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 46
I/O 45
I/O 44
Output Routing Pool (ORP)
A2
Output Routing Pool (ORP)
B2
Y0
Y1
Y2
TDI/IN 0
TMS/IN 1
Output Routing Pool (ORP)
I/O 12
I/O 13
I/O 14
I/O 15
Global Routing Pool
(GRP)
A1
Output Routing Pool (ORP)
Megablock
B4
B3
A0
Input Bus
I/O 8
I/O 9
I/O 10
I/O 11
B5
I/O 47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
B6
GOE1/Y0
RESET/Y1
TCK/Y2
Output Routing Pool (ORP)
B7
Generic Logic
Blocks (GLBs)
Input Bus
I/O 12
I/O 13
I/O 14
I/O 15
Input Bus
Megablock
I/O 27
I/O 26
I/O 25
I/O 24
I/O 31
I/O 30
I/O 29
I/O 28
I/O 51
I/O 50
I/O 49
I/O 48
I/O 55
I/O 54
I/O 53
I/O 52
I/O 56
I/O 58
I/O 57
I/O 59
I/O 63
I/O 62
I/O 61
I/O 60
GOE 1
GOE 0
Figure 1. ispLSI 2064VE Functional Block Diagram (64-I/O and 32-I/O Versions)
0139B/2064VE.32IO
Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock
can be generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2064VE are individually programmable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the Lattice software tools.
Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and
two or one ORPs are connected together to make a
Megablock (see Figure 1). The outputs of the eight GLBs
are connected to a set of 32 or 16 universal I/O cells by
two or one ORPs. Each ispLSI 2064VE device contains
two Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2064VE device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
2
Specifications ispLSI 2064VE
Absolute Maximum Ratings 1
Supply Voltage Vcc ................................................... -0.5 to +5.4V
Input Voltage Applied ..................................... -0.5 to +5.6V
Off-State Output Voltage Applied .................. -0.5 to +5.6V
Storage Temperature ..................................... -65 to 150°C
Case Temp. with Power Applied .................... -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ............ 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
PARAMETER
VCC
Supply Voltage
VIL
VIH
Input Low Voltage
MIN.
MAX.
UNITS
Commercial
TA = 0°C to + 70°C
3.0
3.6
V
Industrial
TA = -40°C to + 85°C
3.0
3.6
V
0.8
V
VSS – 0.5
Input High Voltage
2.0
5.25
V
Table 2-0005/2064V
Capacitance (TA=25°C, f=1.0 MHz)
TYPICAL
UNITS
8
pf
VCC = 3.3V, VIN = 0.0V
I/O Capacitance
6
pf
VCC = 3.3V, VI/O = 0.0V
Clock and Global Output Enable Capacitance
10
pf
VCC = 3.3V, VY = 0.0V
SYMBOL
C1
C2
C3
PARAMETER
Dedicated Input Capacitance
TEST CONDITIONS
Table 2-0006/2064VE
Erase Reprogram Specifications
PARAMETER
Erase/Reprogram Cycles
MINIMUM
MAXIMUM
UNITS
10000
–
Cycles
Table 2-0008/2064VE
3
Specifications ispLSI 2064VE
Switching Test Conditions
Input Pulse Levels
Figure 2. Test Load
GND to 3.0V
Input Rise and Fall Time
≤ 1.5 ns 10% to 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
+ 3.3V
R1
See Figure 2
Device
Output
Table 2-0003/2064VE
3-state levels are measured 0.5V from
steady-state active level.
Test
Point
R2
CL*
Output Load Conditions (see Figure 2)
TEST CONDITION
R1
R2
CL
316Ω
348Ω
35pF
Active High
∞
348Ω
35pF
Active Low
316Ω
348Ω
35pF
Active High to Z
at VOH -0.5V
∞
348Ω
5pF
Active Low to Z
at VOL +0.5V
316Ω
348Ω
5pF
A
B
C
*CL includes Test Fixture and Probe Capacitance.
0213A/2064V
Table 2-0004/2064V
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
VOL
VOH
IIL
PARAMETER
CONDITION
3
MIN.
TYP.
MAX. UNITS
Output Low Voltage
IOL= 8 mA
–
–
0.4
V
Output High Voltage
IOH = -4 mA
2.4
–
–
V
0V ≤ VIN ≤ VIL (Max.)
–
–
-10
µA
(VCC – 0.2)V ≤ VIN ≤ VCC
–
–
10
µA
VCC ≤ VIN ≤ 5.25V
–
–
10
µA
0V ≤ VIN ≤ VIL
–
–
-150
µA
I/O Active Pull-Up Current
Input or I/O Low Leakage Current
IIH
Input or I/O High Leakage Current
IIL-isp
IIL-PU
IOS1
BSCAN Input Low Leakage Current
0V ≤ VIN ≤ VIL
–
–
-150
µA
Output Short Circuit Current
VCC = 3.3V, VOUT = 0.5V
–
–
-100
mA
ICC2, 4
Operating Power Supply Current
VIL = 0.0V, VIH = 3.0V
–
90
–
mA
fCLOCK = 1 MHz
Table 2-0007/2064VE
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using four 16-bit counters.
3. Typical values are at VCC = 3.3V and TA= 25°C.
4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum ICC .
4
Specifications ispLSI 2064VE
External Timing Parameters
Over Recommended Operating Conditions
3
PARAMETER
tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
TEST
COND.
#
DESCRIPTION
-280
1
-200
MIN. MAX. MIN. MAX.
UNITS
A
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
–
3.5
–
4.5
ns
A
2
Data Propagation Delay
–
5.5
–
7.0
ns
A
3
Clock Frequency with Internal Feedback
280
–
200
–
MHz
2
1
tsu2 + tco1
–
4
Clock Frequency with External Feedback (
182
–
133
–
MHz
–
5
Clock Frequency, Max. Toggle
)
300
–
200
–
MHz
–
6
GLB Reg. Setup Time before Clock, 4 PT Bypass
2.3
–
3.0
–
ns
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
–
2.5
–
3.5
ns
–
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0
–
0.0
–
ns
GLB Reg. Setup Time before Clock
–
9
3.0
–
4.0
–
ns
A
10 GLB Reg. Clock to Output Delay
–
3.3
–
4.5
ns
0.0
–
0.0
–
ns
–
5.5
–
6.0
ns
–
11 GLB Reg. Hold Time after Clock
A
12 Ext. Reset Pin to Output Delay, ORP Bypass
–
13 Ext. Reset Pulse Duration
3.5
–
4.0
–
ns
B
14 Input to Output Enable
–
6.0
–
8.0
ns
C
15 Input to Output Disable
–
6.0
–
8.0
ns
B
16 Global OE Output Enable
–
3.5
–
5.0
ns
C
17 Global OE Output Disable
–
3.5
–
5.0
ns
–
18 External Synchronous Clock Pulse Duration, High
1.6
–
2.5
–
ns
–
19 External Synchronous Clock Pulse Duration, Low
1.6
–
2.5
–
ns
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
5
Table 2-0030A/2064VE v.0.0
Specifications ispLSI 2064VE
External Timing Parameters
Over Recommended Operating Conditions
3
PARAMETER
tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
-135
-100
TEST
COND.
#
A
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
–
7.5
–
10.0
ns
A
2
Data Propagation Delay
–
10.0
–
13.0
ns
DESCRIPTION
1
MIN. MAX. MIN. MAX.
2
UNITS
A
3
Clock Frequency with Internal Feedback
135
–
100
–
MHz
–
4
Clock Frequency with External Feedback ( tsu2 + tco1)
100
–
77
–
MHz
–
5
Clock Frequency, Max. Toggle
143
–
100
–
MHz
1
–
6
GLB Reg. Setup Time before Clock, 4 PT Bypass
5.0
–
6.5
–
ns
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
–
4.0
–
5.0
ns
–
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0
–
0.0
–
ns
–
9
GLB Reg. Setup Time before Clock
6.0
–
8.0
–
ns
A
10 GLB Reg. Clock to Output Delay
–
5.0
–
6.0
ns
0.0
–
0.0
–
ns
–
9.0
–
12.5
ns
–
11 GLB Reg. Hold Time after Clock
A
12 Ext. Reset Pin to Output Delay, ORP Bypass
–
13 Ext. Reset Pulse Duration
5.0
–
6.5
–
ns
B
14 Input to Output Enable
–
12.0
–
15.0
ns
C
15 Input to Output Disable
–
12.0
–
15.0
ns
B
16 Global OE Output Enable
–
7.0
–
9.0
ns
C
17 Global OE Output Disable
–
7.0
–
9.0
ns
–
18 External Synchronous Clock Pulse Duration, High
3.5
–
5.0
–
ns
–
19 External Synchronous Clock Pulse Duration, Low
3.5
–
5.0
–
ns
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
6
Table 2-0030B/2064VE v.0.0
Specifications ispLSI 2064VE
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER
2
#
DESCRIPTION
-280
-200
MIN. MAX. MIN. MAX.
UNITS
Inputs
tio
tdin
20 Input Buffer Delay
–
0.4
–
0.5
ns
21 Dedicated Input Delay
–
0.8
–
1.1
ns
22 GRP Delay
–
0.4
–
0.6
ns
23 4 Product Term Bypass Path Delay (Combinatorial)
–
1.1
–
1.4
ns
24 4 Product Term Bypass Path Delay (Registered)
–
1.6
–
1.9
ns
25 1 Product Term/XOR Path Delay
–
2.3
–
2.9
ns
26 20 Product Term/XOR Path Delay
–
2.3
–
2.9
ns
–
2.3
–
2.9
ns
–
0.0
–
0.0
ns
29 GLB Register Setup Time before Clock
0.6
–
1.2
–
ns
30 GLB Register Hold Time after Clock
1.7
–
1.8
–
ns
31 GLB Register Clock to Output Delay
–
0.2
–
0.3
ns
32 GLB Register Reset to Output Delay
–
0.4
–
0.4
ns
33 GLB Product Term Reset to Register Delay
–
4.1
–
4.3
ns
34 GLB Product Term Output Enable to I/O Cell Delay
–
2.9
–
3.9
ns
0.8
2.9
1.0
4.0
ns
36 ORP Delay
–
1.2
–
1.5
ns
37 ORP Bypass Delay
–
0.4
–
0.5
ns
38 Output Buffer Delay
–
1.2
–
1.5
ns
39 Output Slew Limited Delay Adder
–
1.8
–
2.0
ns
40 I/O Cell OE to Output Enabled
–
2.3
–
3.0
ns
41 I/O Cell OE to Output Disabled
–
2.3
–
3.0
ns
42 Global Output Enable
–
1.2
–
2.0
ns
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
0.7
0.7
1.2
1.2
ns
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
0.9
0.9
1.4
1.4
ns
–
3.5
–
3.6
ns
GRP
tgrp
GLB
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
27 XOR Adjacent Path Delay
3
28 GLB Register Bypass Delay
35 GLB Product Term Clock Delay
ORP
torp
torpbp
Outputs
tob
tsl
toen
todis
tgoe
Clocks
tgy0
tgy1/2
Global Reset
tgr
45 Global Reset to GLB
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
7
Table 2-0036A/2064VE v.0.0
Specifications ispLSI 2064VE
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER
2
#
DESCRIPTION
-100
-135
MIN. MAX. MIN. MAX.
UNITS
Inputs
tio
tdin
20 Input Buffer Delay
–
0.5
–
0.7
ns
21 Dedicated Input Delay
–
1.7
–
2.5
ns
22 GRP Delay
–
1.2
–
1.8
ns
23 4 Product Term Bypass Path Delay (Combinatorial)
–
3.7
–
5.2
ns
24 4 Product Term Bypass Path Delay (Registered)
–
3.7
–
4.7
ns
25 1 Product Term/XOR Path Delay
–
4.7
–
6.2
ns
26 20 Product Term/XOR Path Delay
–
4.7
–
6.2
ns
–
4.7
–
6.2
ns
–
0.5
–
1.0
ns
29 GLB Register Setup Time before Clock
1.2
–
1.7
–
ns
30 GLB Register Hold Time after Clock
3.8
–
4.8
–
ns
31 GLB Register Clock to Output Delay
–
0.3
–
0.3
ns
32 GLB Register Reset to Output Delay
–
1.1
–
3.1
ns
33 GLB Product Term Reset to Register Delay
–
6.1
–
7.1
ns
34 GLB Product Term Output Enable to I/O Cell Delay
–
6.9
–
9.1
ns
1.6
5.0
2.6
5.6
ns
36 ORP Delay
–
1.5
–
1.7
ns
37 ORP Bypass Delay
–
0.5
–
0.7
ns
38 Output Buffer Delay
–
1.6
–
1.6
ns
39 Output Slew Limited Delay Adder
–
2.0
–
2.0
ns
40 I/O Cell OE to Output Enabled
–
3.4
–
3.4
ns
41 I/O Cell OE to Output Disabled
–
3.4
–
3.4
ns
42 Global Output Enable
–
3.6
–
5.6
ns
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
1.6
1.6
2.4
2.4
ns
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
1.8
1.8
2.6
2.6
ns
–
5.8
–
7.1
ns
GRP
tgrp
GLB
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
27 XOR Adjacent Path Delay
3
28 GLB Register Bypass Delay
35 GLB Product Term Clock Delay
ORP
torp
torpbp
Outputs
tob
tsl
toen
todis
tgoe
Clocks
tgy0
tgy1/2
Global Reset
tgr
45 Global Reset to GLB
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
8
Table 2-0036B/2064VE v.0.0
Specifications ispLSI 2064VE
ispLSI 2064VE Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Ded. In
I/O Pin
(Input)
Comb 4 PT Bypass #23
#21
I/O Delay
GRP
Reg 4 PT Bypass
GLB Reg Bypass
ORP Bypass
#20
#22
#24
#28
#37
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
#25, 26, 27
D
Q
#38,
39
#36
RST
#45
Reset
#29, 30,
31, 32
Control RE
PTs
OE
#33, 34, CK
35
#40, 41
#43, 44
Y0,1,2
#42
GOE 0,1
0491/2064
Derivations of tsu, th and tco from the Product Term Clock
tsu
th
tco
=
=
=
2.1ns =
=
=
=
2.3ns =
Logic + Reg su - Clock (min)
(tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.4 + 0.4 + 2.3) + (0.6) - (0.4 + 0.4 + 0.8)
=
=
=
6.3ns =
Clock (max) + Reg co + Output
(tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.4 + 0.4 + 2.9) + (0.2) + (1.2 + 1.2)
Clock (max) + Reg h - Logic
(tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.4 + 0.4 + 2.9) + (1.7) - (0.4 + 0.4 + 2.3)
Note: Calculations are based on timing specifications for the ispLSI 2064VE-280L.
Table 2-0042/2064VE
9
I/O Pin
(Output)
Specifications ispLSI 2064VE
Power Consumption
used. Figure 3 shows the relationship between power
and operating speed.
Power consumption in the ispLSI 2064VE device depends on two primary factors: the speed at which the
device is operating and the number of Product Terms
Figure 3. Typical Device Power Consumption vs fmax
180
160
ispLSI 2064VE
ICC (mA)
140
120
100
80
0
50
100
150
200
250
300
fmax (MHz)
Notes: Configuration of four 16-bit counters
Typical current at 3.3V, 25° C
ICC can be estimated for the ispLSI 2064VE using the following equation:
ICC(mA) = 8 + (# of PTs * 0.67) + (# of Nets * Fmax * 0.0045)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two GLB
loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating
conditions and the program in the device, the actual ICC should be verified.
0127/2064VE
10
Specifications ispLSI 2064VE
64-I/O Signal Descriptions
Signal Name
Description
RESET
Active Low (0) Reset pin resets all the registers in the device.
GOE 0, GOE1
Global Output Enable input pins.
Y0, Y1, Y2
Dedicated Clock Input – These clock inputs are connected to one of the clock inputs of all the GLBs in
the device.
BSCAN
Input – Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to
enable the programming mode. The TMS, TDI, TDO and TCK controls become active.
TDI/IN 0
Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a serial data input
pin to load programming data into the device. When BSCAN is high, it functions as a dedicated input pin.
TCK/IN 3
Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a clock pin for the
Boundary Scan state machine. (2) When BSCAN is high, it functions as a dedicated input pin.
TMS/IN 1
Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a mode control pin
for the Boundary Scan state machine. (2) When BSCAN is high, it functions as a dedicated input pin.
TDO/IN 2
Output/Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as an output
pin to read serial shift register data. (2) When BSCAN is high, it functions as a dedicated input pin.
GND
Ground (GND)
VCC
Vcc
NC1
No Connect
I/O
Input/Output Pins – These are the general purpose I/O pins used by the logic array.
1. NC pins are not to be connected to any active signals, VCC or GND.
32-I/O Signal Descriptions
Signal Name
Description
GOE 0/IN 3
This pin performs one of two functions. It can be programmed to function as a Global Output Enable
pin or a Dedicated Input pin.
GOE 1/Y0
This pin performs one of two functions. (1) It can be programmed to function as a GLobal Output Enable
or a Dedicated Clock input. (2) This clock input is connected to one of the clock inputs of all GLBs on
the device.
RESET/Y1
This pin performs two functions: (1) Active Low (0) Reset pin which resets all of the registers in the
device. (2) When active low (0), it functions as a dedicated clock input.
BSCAN
Input – Dedicated in-system programming Boundary Scan Enable input pin. This pin is brought low to
enable the programming mode. The TMS, TDI, TDO and TCK controls become active.
TDI/IN 0
Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a serial data input
pin to load programming data into the device. (2) When BSCAN is high, it functions as a dedicated input
pin.
TMS/IN 2
Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a mode control pin
for the Boundary Scan state machine. (2) When BSCAN is high, it functions as a dedicated input pin.
TDO/IN 1
Output/Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as an output
pin to read serial shift register data. (2) When BSCAN is high, it functions as a dedicated input pin.
TCK/Y2
Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a clock pin for the
Boundary Scan state machine. (2) When BSCAN is high, it functions as a dedicated clock input.
GND
Ground (GND)
VCC
Vcc
NC1
No Connect
I/O
Input/Output pins – These are the general purpose I/O pins used by the logic array.
1. NC pins are not to be connected to any active signals, VCC or GND.
11
Specifications ispLSI 2064VE
64-I/O Signal Locations
Signal
I/O Locations
100-Ball caBGA
100
Signal caBGA
100-Pin TQFP
RESET
D2
11
GOE 0, GOE 1
F9, E1
62, 13
Y0, Y1, Y2
E3, F6, F8
10, 65, 60
BSCAN
E5
15
TDI/IN 0
F2
16
TCK/IN 3
G10
59
TMS/IN 1
J5
37
TDO/IN 2
GND
B6
B7, F1, G9, K6
87
14, 39, 61, 86
VCC
A5, E2, F10, J4
12, 36, 63, 89
NC1
A6, A8, C3, C4,
D1, D6, D8, E7,
E9, E10, F4,
G3, G5, H7, H8,
K3, K5
4, 9, 21, 25,
31, 38, 44, 50,
54, 64, 66, 71,
75, 81, 88, 94,
100
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
I/O 36
I/O 37
I/O 38
I/O 39
I/O 40
I/O 41
I/O 42
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
I/O 48
I/O 49
I/O 50
I/O 51
I/O 52
I/O 53
I/O 54
I/O 55
I/O 56
I/O 57
I/O 58
I/O 59
I/O 60
I/O 61
I/O 62
I/O 63
1. NC pins are not to be connected to any active signals,
VCC or GND.
32-I/O Signal Locations
Signal
44-Pin TQFP
44-Pin PLCC
GOE 0/ IN 3
40
2
GOE 1/Y0
5
11
RESET/Y1
29
35
BSCAN
7
13
TDI/IN 0
8
14
TMS/IN 2
30
36
TDO/IN 1
18
24
TCK/Y2
GND
27
17, 39
33
1, 23
VCC
6, 28
12, 34
NC1
—
—
1. NC pins are not to be connected to any active signals,
VCC or GND.
12
G1
F3
E4
H1
G2
J1
H2
K1
J2
K2
H3
J3
G4
H4
K4
H5
F5
J6
K7
H6
K8
G6
J7
K9
J8
K10
J9
J10
H9
H10
G7
G8
D10
E8
F7
C10
D9
B10
C9
A10
B9
A9
C8
B8
D7
C7
A7
C6
E6
B5
A4
C5
A3
D5
B4
A2
B3
A1
B2
B1
C2
C1
D4
D3
100
TQFP
44
TQFP
44
PLCC
17
18
19
20
22
23
24
26
27
28
29
30
32
33
34
35
40
41
42
43
45
46
47
48
49
51
52
53
55
56
57
58
67
68
69
70
72
73
74
76
77
78
79
80
82
83
84
85
90
91
92
93
95
96
97
98
99
1
2
3
5
6
7
8
9
10
11
12
13
14
15
16
19
20
21
22
23
24
25
26
31
32
33
34
35
36
37
38
41
42
43
44
1
2
3
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
16
17
18
19
20
21
22
25
26
27
28
29
30
31
32
37
38
39
40
41
42
43
44
3
4
5
6
7
8
9
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Specifications ispLSI 2064VE
Signal Configuration
ispLSI 2064VE 100-Ball caBGA Signal Diagram (0.8mm Ball Pitch/10.0 x 10.0mm Body Size)
10
9
8
7
6
5
4
3
2
1
A
I/O
39
I/O
41
NC1
I/O
46
NC1
VCC
I/O
50
I/O
52
I/O
55
I/O
57
A
B
I/O
37
I/O
40
I/O
43
GND
TDO/
IN 2
I/O
49
I/O
54
I/O
56
I/O
58
I/O
59
B
C
I/O
35
I/O
38
I/O
42
I/O
45
I/O
47
I/O
51
NC1
NC1
I/O
60
I/O
61
C
D
I/O
32
I/O
36
NC1
I/O
44
NC1
I/O
53
I/O
62
I/O
63
RESET
NC1
D
E
NC1
NC1
I/O
33
NC1
I/O
48
BSCAN
I/O
2
Y0
VCC
GOE
1
E
F
VCC
GOE
0
Y2
I/O
34
Y1
I/O
16
NC1
I/O
1
TDI/
IN 0
GND
F
G
TCK/
IN 3
GND
I/O
31
I/O
30
I/O
21
NC1
I/O
12
NC1
I/O
4
I/O
0
G
H
I/O
29
I/O
28
NC1
NC1
I/O
19
I/O
15
I/O
13
I/O
10
I/O
6
I/O
3
H
J
I/O
27
I/O
26
I/O
24
I/O
22
I/O
17
TMS/
IN 1
VCC
I/O
11
I/O
8
I/O
5
J
K
I/O
25
I/O
23
I/O
20
I/O
18
GND
NC1
I/O
14
NC1
I/O
9
I/O
7
K
3
2
1
ispLSI 2064VE
Bottom View
10
9
8
7
6
5
4
100-BGA/2064VE
1NCs
are not to be connected to any active signals, VCC or GND.
Note: Ball A1 indicator dot on top side of package.
13
Specifications ispLSI 2064VE
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
ispLSI 2064VE
Top View
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC1
I/O 38
I/O 37
I/O 36
NC1
I/O 35
I/O 34
I/O 33
I/O 32
NC1
Y1
NC1
VCC
GOE 0
GND
Y2
TCK/IN 3
I/O 31
I/O 30
I/O 29
I/O 28
NC1
I/O 27
I/O 26
I/O 25
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
1NC
I/O 12
I/O 13
I/O 14
I/O 15
VCC
TMS/IN 1
1NC
GND
I/O 16
I/O 17
I/O 18
I/O 19
1NC
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
1NC
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O 57
I/O 58
I/O 59
1NC
I/O 60
I/O 61
I/O 62
I/O 63
1NC
Y0
RESET
VCC
GOE 1
GND
BSCAN
TDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 3
1NC
I/O 4
I/O 5
I/O 6
1NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
NC1
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
NC1
I/O 51
I/O 50
I/O 49
I/O 48
VCC
NC1
TDO/IN 2
GND
I/O 47
I/O 46
I/O 45
I/O 44
NC1
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
ispLSI 2064VE 100-Pin TQFP Pinout Diagram (0.5mm Lead Pitch/14.0 x 14.0mm Body Size)
100 TQFP/2064VE
1. NC pins are not to be connected to any active signals, VCC or GND.
14
Specifications ispLSI 2064VE
Pin Configuration
I/O 20
I/O 19
I/O 21
I/O 22
I/O 23
GOE 0/IN 3
GND
I/O 24
I/O 26
I/O 25
I/O 27
ispLSI 2064VE 44-Pin PLCC Pinout Diagram (0.05in Lead Pitch/0.65 x 0.65in Body Size)
6 5 4 3 2 1 44 43 42 41 40
I/O 28
I/O 29
I/O 30
I/O 31
GOE1/Y0
VCC
7
8
9
10
11
39
I/O 18
38
37
I/O 17
36
TMS/IN 2
I/O 16
12
ispLSI 2064VE
35
34
RESET/Y1
VCC
Top View
BSCAN
13
33
TCK/Y2
TDI/IN 0
14
32
I/O 15
I/O 0
15
31
I/O 14
I/O 1
I/O 2
16
17
30
29
I/O 13
I/O 12
I/O 10
I/O 11
I/O 9
I/O 8
TDO/IN 1
GND
I/O 7
I/O 6
I/O 4
I/O 5
I/O 3
18 19 20 21 22 23 24 25 26 27 28
44 PLCC/2064VE
Pin Configuration
I/O 21
I/O 20
I/O 19
I/O 22
GND
I/O 23
GOE 0/IN 3
I/O 24
I/O 26
I/O 25
I/O 27
ispLSI 2064VE 44-Pin TQFP Pinout Diagram (0.8mm Lead Pitch/10.0 x 10.0mm Body Size)
44 43 42 41 40 39 38 37 36 35 34
I/O 28
I/O 29
I/O 30
I/O 31
GOE1/Y0
VCC
1
2
3
4
5
ispLSI 2064VE
6
Top View
33
I/O 18
32
31
I/O 17
I/O 16
30
TMS/IN 2
29
28
RESET/Y1
VCC
BSCAN
7
27
TCK/Y2
TDI/IN 0
8
26
I/O 15
I/O 0
I/O 1
9
10
I/O 14
I/O 13
I/O 2
11
25
24
23
I/O 12
I/O 9
I/O 10
I/O 11
I/O 8
GND
TDO/IN 1
I/O 7
I/O 6
I/O 4
I/O 5
I/O 3
12 13 14 15 16 17 18 19 20 21 22
44 TQFP/2064VE
15
Specifications ispLSI 2064VE
Part Number Description
ispLSI 2064VE – XXX X XXXXX X
Device Family
Grade
Blank = Commercial
I = Industrial
Device Number
Package
T100 = 100-Pin TQFP
TN100 = Lead-Free 100-Pin TQFP
B100 = 100-Ball caBGA
T44 = 44-Pin TQFP
TN44 = Lead-Free 44-Pin TQFP
J44 = 44-Pin PLCC
Speed
280 = 280 MHz fmax
200 = 200 MHz fmax
135 = 135 MHz fmax
100 = 100 MHz fmax
Power
L = Low
ispLSI 2064VE Ordering Information
Conventional Packaging
COMMERCIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
I/Os
ORDERING NUMBER
PACKAGE
280
3.5
64
ispLSI 2064VE-280LT100
100-Pin TQFP
280
3.5
64
ispLSI 2064VE-280LB100
100-Ball caBGA
280
3.5
32
ispLSI 2064VE-280LT44
44-Pin TQFP
200
4.5
64
ispLSI 2064VE-200LT100
100-Pin TQFP
200
4.5
64
ispLSI 2064VE-200LB100
100-Ball caBGA
200
4.5
32
ispLSI 2064VE-200LJ44
44-Pin PLCC
200
4.5
32
ispLSI 2064VE-200LT44
44-Pin TQFP
135
7.5
64
ispLSI 2064VE-135LT100
100-Pin TQFP
135
7.5
64
ispLSI 2064VE-135LB100
100-Ball caBGA
135
7.5
32
ispLSI 2064VE-135LJ44
44-Pin PLCC
135
7.5
32
ispLSI 2064VE-135LT44
44-Pin TQFP
100
10
64
ispLSI 2064VE-100LT100
100-Pin TQFP
100
10
64
ispLSI 2064VE-100LB100
100-Ball caBGA
100
10
32
ispLSI 2064VE-100LJ44
44-Pin PLCC
100
10
32
ispLSI 2064VE-100LT44
44-Pin TQFP
Table 2-0041A/2064VE
INDUSTRIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
I/Os
ORDERING NUMBER
PACKAGE
135
7.5
64
ispLSI 2064VE-135LT100I
100-Pin TQFP
135
7.5
32
ispLSI 2064VE-135LT44I
44-Pin TQFP
Table 2-0041B/2064VE
16
Specifications ispLSI 2064VE
ispLSI 2064VE Ordering Information (Cont.)
Lead-Free Packaging
COMMERCIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
I/Os
ORDERING NUMBER
PACKAGE
280
3.5
64
ispLSI 2064VE-280LTN100
Lead-Free 100-Pin TQFP
280
3.5
32
ispLSI 2064VE-280LTN44
Lead-Free 44-Pin TQFP
200
4.5
64
ispLSI 2064VE-200LTN100
Lead-Free 100-Pin TQFP
200
4.5
32
ispLSI 2064VE-200LTN44
Lead-Free 44-Pin TQFP
135
7.5
64
ispLSI 2064VE-135LTN100
Lead-Free 100-Pin TQFP
135
7.5
32
ispLSI 2064VE-135LTN44
Lead-Free 44-Pin TQFP
100
10
64
ispLSI 2064VE-100LTN100
Lead-Free 100-Pin TQFP
100
10
32
ispLSI 2064VE-100LTN44
Lead-Free 44-Pin TQFP
INDUSTRIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
I/Os
ORDERING NUMBER
PACKAGE
135
7.5
64
ispLSI 2064VE-135LTN100I
Lead-Free 100-Pin TQFP
135
7.5
32
ispLSI 2064VE-135LTN44I
Lead-Free 44-Pin TQFP
17