LATTICE ISPLSI2032VE

®
ispLSI 2032VE
3.3V In-System Programmable
High Density SuperFAST™ PLD
Functional Block Diagram
Global Routing Pool
(GRP)
Input Bus
• 3.3V LOW VOLTAGE 2032 ARCHITECTURE
— Interfaces With Standard 5V TTL Devices
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 225 MHz Maximum Operating Frequency
— tpd = 4.0 ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
Output Routing Pool (ORP)
A0
A1
A2
D Q
GLB
Logic
Array
A7
A6
D Q
D Q
A5
D Q
A3
Input Bus
• SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 1000 PLD Gates
— 32 I/O Pins, Two Dedicated Inputs
— 32 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible
with ispLSI 2032V Devices
Output Routing Pool (ORP)
Features
A4
0139Bisp/2000
Description
• IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability Using Boundary
Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
The ispLSI 2032VE is a High Density Programmable
Logic Device that can be used in both 3.3V and 5V
systems. The device contains 32 Registers, 32 Universal
I/O pins, two Dedicated Input Pins, three Dedicated
Clock Input Pins, one dedicated Global OE input pin and
a Global Routing Pool (GRP). The GRP provides
complete interconnectivity between all of these elements.
The ispLSI 2032VE features in-system programmability
through the Boundary Scan Test Access Port (TAP) and
is 100% IEEE 1149.1 Boundary Scan Testable. The
ispLSI 2032VE offers non-volatile reprogrammability of
the logic, as well as the interconnect to provide truly
reconfigurable systems.
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
The basic unit of logic on the ispLSI 2032VE device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. A7 (see Figure 1). There are a total of eight GLBs in the
ispLSI 2032VE device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2032ve_07
1
September 2000
Specifications ispLSI 2032VE
Functional Block Diagram
Figure 1. ispLSI 2032VE Functional Block Diagram
GOE 0
I/O 12
I/O 13
I/O 14
I/O 15
A1
I/O 31
I/O 30
I/O 29
I/O 28
A7
Global Routing Pool
(GRP)
A6
A2
A5
A3
A4
I/O 27
Input Bus
I/O 9
I/O 10
I/O 11
Output Routing Pool (ORP)
I/O 8
Input Bus
I/O 4
I/O 5
I/O 6
I/O 7
A0
Output Routing Pool (ORP)
I/O 0
I/O 1
I/O 2
I/O 3
I/O 26
I/O 25
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16
TDI/IN 0
TDO/IN 1
CLK 0
CLK 1
CLK 2
Generic Logic
Blocks (GLBs)
TMS/NC
BSCAN
Y0
Y1*
TCK/Y2
Note: *Y1 and RESET are multiplexed on the same pin
0139B/2032VE
The device also has 32 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, output or bidirectional I/O pin with 3-state control. The signal levels
are TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate
to minimize overall output switching noise. Device pins
can be safely driven to 5 Volt signal levels to support
mixed-voltage systems.
Clocks in the ispLSI 2032VE device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock
can be generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2032VE are individually programmable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the ORP. Each ispLSI
2032VE device contains one Megablock.
The GRP has as its inputs the outputs from all of the GLBs
and all of the inputs from the bi-directional I/O cells. All of
these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
2
Specifications ispLSI 2032VE
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +5.4V
Input Voltage Applied ............................... -0.5 to +5.6V
Off-State Output Voltage Applied ............ -0.5 to +5.6V
Storage Temperature .............................. -65 to +150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
PARAMETER
Commercial
VCC
Supply Voltage
VIL
VIH
Input Low Voltage
Industrial
MIN.
MAX.
UNITS
TA = 0°C to + 70°C
3.0
3.6
V
TA = -40°C to + 85°C
3.0
3.6
V
0.8
V
5.25
V
VSS – 0.5
Input High Voltage
2.0
Table 2-0005/2032VE
Capacitance (TA=25°C, f=1.0 MHz)
TYPICAL
UNITS
8
pf
VCC = 3.3V, VIN = 0.0V
I/O Capacitance
6
pf
VCC = 3.3V, VI/O = 0.0V
Clock Capacitance
10
pf
VCC = 3.3V, VY = 0.0V
SYMBOL
C1
C2
C3
PARAMETER
Dedicated Input Capacitance
TEST CONDITIONS
Table 2-0006/2032VE
Erase Reprogram Specifications
PARAMETER
MINIMUM
MAXIMUM
UNITS
10,000
–
Cycles
Erase/Reprogram Cycles
Table 2-0008A/2032VE
3
Specifications ispLSI 2032VE
Switching Test Conditions
Input Pulse Levels
Figure 2. Test Load
GND to 3.0V
≤ 1.5 ns
Input Rise and Fall Time
10% to 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
+ 3.3V
R1
Device
Output
See Figure 2
Table 2-0003/2032VE
3-state levels are measured 0.5V from
steady-state active level.
R2
Output Load Conditions (see Figure 2)
TEST CONDITION
A
B
C
Test
Point
R1
R2
CL
316Ω
348Ω
35pF
Active High
∞
348Ω
35pF
Active Low
316Ω
348Ω
35pF
Active High to Z
at VOH -0.5V
∞
348Ω
5pF
Active Low to Z
at VOL +0.5V
316Ω
348Ω
5pF
C L*
*CL includes Test Fixture and Probe Capacitance.
0213A/2032VE
Table 2-0004A/2032VE
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
VOL
VOH
IIL
IIH
IIL-isp
IIL-PU
IOS1
ICC2, 4, 5
PARAMETER
CONDITION
3
MIN.
TYP.
MAX. UNITS
Output Low Voltage
IOL= 8 mA
–
–
0.4
V
Output High Voltage
IOH = -4 mA
2.4
–
–
V
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (Max.)
–
–
-10
µA
Input or I/O High Leakage Current
(VCC - 0.2)V ≤ VIN ≤ VCC
–
–
10
µA
VCC ≤ VIN ≤ 5.25V
–
–
10
µA
BSCAN Input Low Leakage Current
0V ≤ VIN ≤ VIL
–
–
-150
µA
I/O Active Pull-Up Current
0V ≤ VIN ≤ VIL
–
–
-150
µA
Output Short Circuit Current
VCC = 3.3V, VOUT = 0.5V
–
–
-100
mA
Operating Power Supply Current
VIL = 0.0V, VIH = 3.0V -300/-225
–
80
–
mA
fTOGGLE = 1 MHz
–
65
–
mA
Others
Table 2-0007/2032VE
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using two 16-bit counters.
3. Typical values are at VCC = 3.3V and TA = 25°C.
4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to Power Consumption section
of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate
maximum ICC .
5. Unused inputs at VIL = 0V.
4
Specifications ispLSI 2032VE
External Timing Parameters
Over Recommended Operating Conditions
-225 4
3
PARAMETER
tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
1.
2.
3.
4.
-180
TEST
COND.
#
A
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
–
4.0
–
5.0
ns
A
2
Data Propagation Delay
–
6.0
–
7.5
ns
A
3
Clock Frequency with Internal Feedback 2
225
–
180
–
MHz
–
4
Clock Frequency with External Feedback ( tsu2 + tco1)
154
–
125
–
MHz
–
5
Clock Frequency, Max. Toggle
250
–
200
–
MHz
DESCRIPTION
1
MIN. MAX. MIN. MAX.
1
UNITS
–
6
GLB Reg. Setup Time before Clock, 4 PT Bypass
2.5
–
3.0
–
ns
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
–
3.0
–
4.0
ns
–
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0
–
0.0
–
ns
–
9
GLB Reg. Setup Time before Clock
3.5
–
4.0
–
ns
A
10 GLB Reg. Clock to Output Delay
–
4.0
–
5.0
ns
0.0
–
0.0
–
ns
–
5.0
–
6.0
ns
–
11 GLB Reg. Hold Time after Clock
A
12 Ext. Reset Pin to Output Delay, ORP Bypass
–
13 Ext. Reset Pulse Duration
3.5
–
4.0
–
ns
B
14 Input to Output Enable
–
7.0
–
10.0
ns
C
15 Input to Output Disable
–
7.0
–
10.0
ns
B
16 Global OE Output Enable
–
3.5
–
5.0
ns
C
17 Global OE Output Disable
–
3.5
–
5.0
ns
–
18 External Synchronous Clock Pulse Duration, High
2.0
–
2.5
–
ns
–
19 External Synchronous Clock Pulse Duration, Low
2.0
–
2.5
–
ns
Unless noted otherwise, all parameters use a GRP load of 4, 20 PTXOR path, ORP and Y0 clock.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
-225 speed grade supercedes earlier -200. All parameters other than fmax (internal) are the same.
5
Table 2-0030A/2032VE
Specifications ispLSI 2032VE
External Timing Parameters
Over Recommended Operating Conditions
3
PARAMETER
tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
-135
-110
TEST
COND.
#
A
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
–
7.5
–
10.0
ns
A
2
Data Propagation Delay
–
10.0
–
13.0
ns
DESCRIPTION
1
MIN. MAX. MIN. MAX.
2
UNITS
A
3
Clock Frequency with Internal Feedback
135
–
111
–
MHz
–
4
Clock Frequency with External Feedback ( tsu2 + tco1)
100
–
77.0
–
MHz
–
5
Clock Frequency, Max. Toggle
167
–
125
–
MHz
–
6
GLB Reg. Setup Time before Clock, 4 PT Bypass
4.0
–
5.5
–
ns
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
–
4.5
–
5.0
ns
–
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0
–
0.0
–
ns
–
9
GLB Reg. Setup Time before Clock
5.5
–
7.5
–
ns
1
A
10 GLB Reg. Clock to Output Delay
–
5.5
–
6.5
ns
–
11 GLB Reg. Hold Time after Clock
0.0
–
0.0
–
ns
A
12 Ext. Reset Pin to Output Delay, ORP Bypass
–
9.0
–
12.5
ns
5.0
–
6.5
–
ns
–
12.0
–
14.5
ns
–
13 Ext. Reset Pulse Duration
B
14 Input to Output Enable
C
15 Input to Output Disable
–
12.0
–
14.5
ns
B
16 Global OE Output Enable
–
6.0
–
7.0
ns
C
17 Global OE Output Disable
–
6.0
–
7.0
ns
–
18 External Synchronous Clock Pulse Duration, High
3.0
–
4.0
–
ns
–
19 External Synchronous Clock Pulse Duration, Low
3.0
–
4.0
–
ns
1. Unless noted otherwise, all parameters use a GRP load of 4, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
6
Table 2-0030B/2032VL
Specifications ispLSI 2032VE
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER
2
#
DESCRIPTION
-225
-180
MIN. MAX. MIN. MAX.
UNITS
Inputs
tio
tdin
20 Input Buffer Delay
–
0.6
–
0.8
ns
21 Dedicated Input Delay
–
1.3
–
1.5
ns
22 GRP Delay
–
0.7
–
0.7
ns
23 4 Product Term Bypass Path Delay (Combinatorial)
–
1.2
–
1.8
ns
24 4 Product Term Bypass Path Delay (Registered)
–
1.2
–
2.1
ns
25 1 Product Term/XOR Path Delay
–
2.2
–
3.1
ns
26 20 Product Term/XOR Path Delay
–
2.2
–
3.1
ns
–
2.2
–
3.1
ns
–
0.0
–
0.2
ns
29 GLB Register Setup Time before Clock
0.8
–
0.9
–
ns
30 GLB Register Hold Time after Clock
1.7
–
2.1
–
ns
31 GLB Register Clock to Output Delay
–
0.7
–
0.8
ns
32 GLB Register Reset to Output Delay
–
1.3
–
1.3
ns
33 GLB Product Term Reset to Register Delay
–
3.2
–
4.0
ns
34 GLB Product Term Output Enable to I/O Cell Delay
–
4.2
–
5.7
ns
0.5
2.8
1.4
3.6
ns
36 ORP Delay
–
1.3
–
1.4
ns
37 ORP Bypass Delay
–
0.3
–
0.4
ns
38 Output Buffer Delay
–
1.2
–
1.3
ns
39 Output Slew Limited Delay Adder
–
2.0
–
2.0
ns
40 I/O Cell OE to Output Enabled
–
1.5
–
2.8
ns
41 I/O Cell OE to Output Disabled
–
1.5
–
2.8
ns
42 Global Output Enable
–
2.0
–
2.2
ns
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
–
0.8
1.5
1.5
ns
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
–
1.0
1.7
1.7
ns
45 Global Reset to GLB
–
2.2
–
3.0
ns
GRP
tgrp
GLB
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
27 XOR Adjacent Path Delay
3
28 GLB Register Bypass Delay
35 GLB Product Term Clock Delay
ORP
torp
torpbp
Outputs
tob
tsl
toen
todis
tgoe
Clocks
tgy0
tgy1/2
Global Reset
tgr
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
7
Table 2-0036A/2032VE
Specifications ispLSI 2032VE
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER
#2
DESCRIPTION
-135
-110
MIN. MAX. MIN. MAX.
UNITS
Inputs
tio
tdin
20 Input Buffer Delay
–
0.8
–
1.3
ns
21 Dedicated Input Delay
–
1.7
–
2.5
ns
22 GRP Delay
–
0.9
–
1.2
ns
23 4 Product Term Bypass Path Delay (Combinatorial)
–
3.9
–
4.8
ns
24 4 Product Term Bypass Path Delay (Registered)
–
2.9
–
3.4
ns
25 1 Product Term/XOR Path Delay
–
4.4
–
5.4
ns
26 20 Product Term/XOR Path Delay
–
4.4
–
5.4
ns
–
4.4
–
5.4
ns
–
1.0
–
1.4
ns
29 GLB Register Setup Time before Clock
1.1
–
1.4
–
ns
30 GLB Register Hold Time after Clock
2.9
–
4.1
–
ns
31 GLB Register Clock to Output Delay
–
0.9
–
1.0
ns
32 GLB Register Reset to Output Delay
–
1.8
–
2.7
ns
33 GLB Product Term Reset to Register Delay
–
6.1
–
7.1
ns
34 GLB Product Term Output Enable to I/O Cell Delay
–
6.9
–
8.6
ns
1.7
4.1
2.5
4.4
ns
36 ORP Delay
–
1.5
–
1.9
ns
37 ORP Bypass Delay
–
0.5
–
0.9
ns
38 Output Buffer Delay
–
1.4
–
1.8
ns
39 Output Slew Limited Delay Adder
–
2.0
–
2.0
ns
40 I/O Cell OE to Output Enabled
–
3.4
–
3.4
ns
41 I/O Cell OE to Output Disabled
–
3.4
–
3.4
ns
42 Global Output Enable
–
2.6
–
3.6
ns
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
1.7
1.7
1.8
1.8
ns
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
1.9
1.9
2.0
2.0
ns
–
5.3
–
7.1
ns
GRP
tgrp
GLB
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
27 XOR Adjacent Path Delay
3
28 GLB Register Bypass Delay
35 GLB Product Term Clock Delay
ORP
torp
torpbp
Outputs
tob
tsl
toen
todis
tgoe
Clocks
tgy0
tgy1/2
Global Reset
tgr
45 Global Reset to GLB
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
8
Table 2-0036A/2032VE
Specifications ispLSI 2032VE
ispLSI 2032VE Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Ded. In
I/O Pin
(Input)
Comb 4 PT Bypass #23
#21
I/O Delay
GRP
Reg 4 PT Bypass
GLB Reg Bypass
ORP Bypass
#20
#22
#24
#28
#37
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
#25, 26, 27
D
Q
#38,
39
#36
RST
#45
Reset
#29, 30,
31, 32
Control RE
PTs
OE
#33, 34, CK
35
#40, 41
#43, 44
Y0,1,2
#42
GOE 0
0491/2032VE
Derivations of tsu, th and tco from the Product Term Clock
tsu
=
=
=
2.5ns =
Logic + Reg su - Clock (min)
(tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.6 + 0.7 + 2.2) + (6.8) - (0.6 + 0.7 + 0.5)
th
=
=
=
2.3ns =
Clock (max) + Reg h - Logic
(tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.6 + 0.7 + 2.8) + (1.7) - (0.6 + 0.7 + 2.2)
tco
=
=
=
7.3ns =
Clock (max) + Reg co + Output
(tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.6 + 0.7 + 2.8) + (0.7) + (1.3 + 1.2)
Note: Calculations are based on timing specifications for the ispLSI 2032VE-225L.
Table 2-0042/2032VE
9
I/O Pin
(Output)
Specifications ispLSI 2032VE
Power Consumption
Power consumption in the ispLSI 2032VE device depends on two primary factors: the speed at which the
device is operating and the number of product terms
used. Figure 3 shows the relationship between power
and operating speed.
Figure 3. Typical Device Power Consumption vs fmax
150
125
ispLSI 2032VE-225
ICC (mA)
100
75
ispLSI 2032VE-180
and slower
50
25
0
25
50
75
100
125
150
175
200
225
fmax (MHz)
Notes: Configuration of two 16-bit counters
Typical current at 3.3V, 25° C
ICC can be estimated for the ispLSI 2032VE using the following equation:
For ispLSI 2032VE-225: ICC(mA) = 4.5 + (# of PTs * 1.29) + (# of nets * Max freq * 0.0068)
For ispLSI 2032VE-180 and slower: ICC(mA) = 4.5 + (# of PTs * 1.05) + (# of nets * Max freq * 0.0068)
Where:
# of PTs = Number of product terms used in design
# of nets = Number of signals used in device
Max freq = Highest clock frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two
GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to
operating conditions and the program in the device, the actual ICC should be verified.
0127A/2032VE
10
Specifications ispLSI 2032VE
Signal Descriptions
Signal Name
Description
GOE 0
Global Output Enable Pin
Y0
Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the
device.
RESET/Y1
This pin performs two functions: (1) Dedicated clock input. This clock input is brought into the Clock
Deistribution Network and can optionally be routed to any GLB and/or I/O cell on the device. (2) Active
Low (0) Reset pin which resets all of the GLB and I/O registers in the device.
BSCAN
Input – Dedicated in-system programming Boundary Scan Enable input pin. This pin is brought low to
enable the programming mode. The TMS, TDI, TDO and TCK controls become active.
TDI/IN 0
Input – This pin performs two functions. When BSCAN is logic low, it functions as an input pin to load
programming data into the device. TDI/IN0 is also used as one of the two control pins for the ISP State
Machine. When BSCAN is high, it functions as a dedicated input pin.
TMS/NC1
Input – When in ISP Mode, controls operation of the ISP State Machine.
TDO/IN 1
Output/Input – This pin performs two functions. When BSCAN is logic low, it functions as an output pin
pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin.
TCK/Y2
Input – This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the
Serial Shift Register. When BSCAN is high, it functions as a dedicated clock input. This clock input is
brought into the Clock Distribution Network and can optionally be routed to any GLB and/or I/O cell on
the device.
GND
Ground (GND)
VCC
Vcc
NC1
No Connect
I/O
Input/Output pins – These are the general purpose I/O pins used by the logic array.
Signal Locations
Signal
44-Pin TQFP
44-Pin PLCC
48-Pin TQFP
49-Ball caBGA
GOE 0
40
2
43
A4
Y0
5
11
5
C1
RESET/Y1
29
35
31
D7
BSCAN
7
13
7
D1
TDI/IN 0
8
14
8
E2
TMS/NC1
30
36
32
C6
TDO/IN 1
18
24
19
G4
TCK/Y2
27
33
29
E7
GND
17, 39
1, 23
18, 42
C4, E4
VCC
6, 28
12, 34
6, 30
D3, D5
NC1
—
—
12, 24, 36, 48
A1, A7, D4, G1, G7
I/O Locations
Signal
44-Pin TQFP
44-Pin PLCC
15, 16, 17, 18, 19, 20, 21
48-Pin TQFP
49-Ball caBGA
I/O 0 - I/O 6
9, 10, 11, 12, 13, 14, 15
9, 10, 11, 13, 14, 15, 16
E1, F2, F1, E3, F3, G2, F4
I/O 7 - I/O 13
16, 19, 20, 21, 22, 23, 24 22, 25, 26, 27, 28, 29, 30
17, 20, 21, 22, 23, 25, 26
G3, F5, G5, F6, G6, E5, E6
I/O 14 - I/O 20
25, 26, 31, 32, 33, 34, 35 31, 32, 37, 38, 39, 40, 41
27, 28, 33, 34, 35, 37, 38
F7, D6, C7, B6, B7, C5, B5
I/O 21 - I/O 27
36, 37, 38, 41, 42, 43, 44 42, 43, 44, 3, 4, 5, 6
39, 40, 41, 44, 45, 46, 47
A6, B4, A5, B3, A3, B2, A2
I/O 28 - I/O 31
1, 2, 3, 4
1, 2, 3, 4
C3, C2, B1, D2
7, 8, 9, 10
1. NC pins are not to be connected to any active signals, VCC or GND.
11
Specifications ispLSI 2032VE
Pin Configuration
I/O 21
I/O 20
I/O 19
I/O 22
GND
I/O 23
GOE 0
I/O 24
I/O 26
I/O 25
I/O 27
ispLSI 2032VE 44-Pin TQFP Pinout Diagram
44 43 42 41 40 39 38 37 36 35 34
I/O 28
I/O 29
I/O 30
I/O 31
1
2
3
4
5
33
I/O 18
32
31
I/O 17
I/O 16
30
TMS/NC1
RESET/Y1
VCC
6
ispLSI 2032VE
29
28
BSCAN
7
Top View
27
TCK/Y2
TDI/IN 0
8
26
I/O 15
9
10
11
25
24
23
I/O 14
I/O 13
I/O 12
Y0
VCC
I/O 0
I/O 1
I/O 2
I/O 9
I/O 10
I/O 11
I/O 8
GND
TDO/IN 1
I/O 7
I/O 6
I/O 4
I/O 5
I/O 3
12 13 14 15 16 17 18 19 20 21 22
0851/2032VE
1. NC pins are not to be connected to any active signals, VCC or GND.
Pin Configuration
I/O 21
I/O 20
I/O 19
I/O 22
GND
I/O 23
GOE 0
I/O 24
I/O 26
I/O 25
I/O 27
ispLSI 2032VE 44-Pin PLCC Pinout Diagram
6 5 4 3 2 1 44 43 42 41 40
I/O 28
I/O 29
I/O 30
I/O 31
Y0
VCC
7
8
9
10
11
39
I/O 18
38
37
I/O 17
I/O 16
36
TMS/NC1
RESET/Y1
VCC
12
ispLSI 2032VE
35
34
Top View
BSCAN
13
33
TCK/Y2
TDI/IN 0
14
32
I/O 15
I/O 0
I/O 1
I/O 2
15
16
17
31
30
29
I/O 14
I/O 13
I/O 12
I/O 9
I/O 10
I/O 11
I/O 8
TDO/IN 1
GND
I/O 7
I/O 6
I/O 4
I/O 5
I/O 3
18 19 20 21 22 23 24 25 26 27 28
0123/2032VE
1. NC pins are not to be connected to any active signals, VCC or GND.
12
Specifications ispLSI 2032VE
Pin Configuration
I/O 21
I/O 20
I/O 19
I/O 22
GND
I/O 23
GOE 0
I/O 24
I/O 26
I/O 25
I/O 27
NC2
ispLSI 2032VE 48-Pin TQFP Pinout Diagram
48 47 46 45 44 43 42 41 40 39 38 37
I/O 28
I/O 29
I/O 30
I/O 31
Y0
VCC
BSCAN
1TDI/IN
0
I/O 0
I/O 1
I/O 2
2NC
36
NC2
35
I/O 18
34
33
I/O 17
I/O 16
32
TMS/NC2
31
30
RESET/Y11
VCC
8
29
TCK/Y21
9
10
11
12
28
I/O 15
27
26
25
I/O 14
I/O 13
I/O 12
1
2
3
4
5
6
ispLSI 2032VE
7
Top View
I/O 9
I/O 10
I/O 11
2NC
I/O 8
1
1TDO/IN
I/O 7
GND
I/O 6
I/O 4
I/O 5
I/O 3
13 14 15 16 17 18 19 20 21 22 23 24
48TQFP/2032VE
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, VCC or GND.
Signal Configuration
ispLSI 2032VE 49-Ball caBGA Signal Diagram
7
6
5
4
3
2
1
A
NC1
I/O
21
I/O
23
GOE
0
I/O
25
I/O
27
NC1
A
B
I/O
18
I/O
17
I/O
20
I/O
22
I/O
24
I/O
26
I/O
30
B
C
I/O
16
TMS/
NC1
I/O
19
GND
I/O
28
I/O
29
Y0
C
D
RESET/
Y1
I/O
15
VCC
NC1
VCC
I/O
31
BSCAN
D
E
TCK/
Y2
I/O
13
I/O
12
GND
I/O
3
TDI/
IN0
I/O
0
E
F
I/O
14
I/O
10
I/O
8
I/O
6
I/O
4
I/O
1
I/O
2
F
G
NC1
I/O
11
I/O
9
TDO/
IN1
I/O
7
I/O
5
NC1
G
2
1
ispLSI 2032VE
Bottom View
7
6
5
4
3
49-BGA/2032VE
1. NCs are not to be connected to any active signals, VCC or GND.
Note: Ball A1 indicator dot on top side of package.
13
Specifications ispLSI 2032VE
Part Number Description
ispLSI 2032VE – XXX
X XXX X
Device Family
Device Number
2032VE
Grade
Blank = Commercial
I = Industrial
Speed
225 = 225 MHz fmax
180 = 180 MHz fmax
135 = 135 MHz fmax
110 = 110 MHz fmax
Package
T44 = 44-Pin TQFP
T48 = 48-Pin TQFP
J44 = 44-Pin PLCC
B49 = 49-Ball caBGA
Power
L = Low
0212A/2032VE
ispLSI 2032VE Ordering Information
COMMERCIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
ORDERING NUMBER
PACKAGE
225
225
4.0
4.0
ispLSI 2032VE-225LT44
ispLSI 2032VE-225LT48
44-Pin TQFP
48-Pin TQFP
225
225
4.0
4.0
ispLSI 2032VE-225LJ44
ispLSI 2032VE-225LB49
44-Pin PLCC
49-Ball caBGA
180
5.0
ispLSI 2032VE-180LT44
44-Pin TQFP
180
5.0
180
180
5.0
5.0
ispLSI 2032VE-180LT48
ispLSI 2032VE-180LJ44
ispLSI 2032VE-180LB49
48-Pin TQFP
44-Pin PLCC
49-Ball caBGA
135
7.5
ispLSI 2032VE-135LT44
44-Pin TQFP
135
7.5
ispLSI 2032VE-135LT48
48-Pin TQFP
135
7.5
ispLSI 2032VE-135LJ44
44-Pin PLCC
135
7.5
ispLSI 2032VE-135LB49
49-Ball caBGA
110
110
10
10
ispLSI 2032VE-110LT44
ispLSI 2032VE-110LT48
44-Pin TQFP
48-Pin TQFP
110
10
ispLSI 2032VE-110LJ44
44-Pin PLCC
110
10
ispLSI 2032VE-110LB49
49-Ball caBGA
Table 2-0041A/2032VE
INDUSTRIAL
FAMILY
fmax (MHz)
tpd (ns)
ORDERING NUMBER
PACKAGE
ispLSI
180
5.0
ispLSI 2032VE-180LT44I
44-Pin TQFP
Table 2-0041B/2032VE
14