ispLSI 3256 ® High Density Programmable Logic Functional Block Diagram A0 A1 OR Array A2 A3 B3 N C0 C1 C2 R F2 D Q F1 Twin GLB F0 D Q D Q E3 E2 D Q E1 Global Routing Pool E0 C3 Output Routing Pool • 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE D Q D Q Array B1 Boundary Scan G0 F3 D Q D Output Routing Pool B0 B2 G1 D Q OR • IN-SYSTEM PROGRAMMABLE — In-System Programmable™ (ISP™) 5-Volt Only — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging G2 S H0 Output Routing Pool H1 D0 D1 D2 Output Routing Pool • HIGH PERFORMANCE E CMOS TECHNOLOGY — fmax = 77 MHz Maximum Operating Frequency — tpd = 15 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power Output Routing Pool G3 H2 ES IG N ® Output Routing Pool H3 EW 2 Output Routing Pool • HIGH-DENSITY PROGRAMMABLE LOGIC — 128 I/O Pins — 11000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic AND Array Features D3 Output Routing Pool 0139A FO Description • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Five Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity SI 32 56 A The ispLSI 3256 is a High Density Programmable Logic Devices containing 384 Registers, 128 Universal I/O pins, five Dedicated Clock Input Pins, eight Output Routing Pools (ORP), and a Global Routing Pool (GRP) which allows complete inter-connectivity between all of these elements. The ispLSI 3256 features 5-Volt in-system programmability and in-system diagnostic capabilities. The ispLSI 3256 offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. • ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms U SE is pL The basic unit of logic on the ispLSI 3256 device is the Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3. There are a total of 32 of these Twin GLBs in the ispLSI device. Each Twin GLB has 24 inputs, a programmable AND array and two OR/Exclusive-OR Arrays, and eight outputs which can be configured to be either combinatorial or registered. All Twin GLB inputs come from the GRP. Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 3256_07 1 May 1999 Specifications ispLSI 3256 Functional Block Diagram I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 H0 G3 G2 G0 A0 F3 A1 F2 A2 F1 A3 F0 Global Routing Pool (GRP) B0 E3 B1 E2 B2 E1 B3 E0 C0 C1 C2 TMS/MODE TCLK/SCLK BSCAN/ispEN I/O 99 I/O 98 I/O 97 I/O 96 I/O 103 I/O 102 I/O 101 I/O 100 G1 ISP and Boundary Scan TAP C3 D0 D1 D2 D3 Output Routing Pool (ORP) Output Routing Pool (ORP) Input Bus Input Bus TDO/SDO I/O 91 I/O 90 I/O 89 I/O 88 I/O 87 I/O 86 I/O 85 I/O 84 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 Y0 Y1 Y2 Y3 Y4 I/O 60 I/O 61 I/O 62 I/O 63 I/O 56 I/O 57 I/O 58 I/O 59 I/O 52 I/O 53 I/O 54 I/O 55 I/O 48 I/O 49 I/O 50 I/O 51 I/O 44 I/O 45 I/O 46 I/O 47 I/O 40 I/O 41 I/O 42 I/O 43 I/O 36 I/O 37 I/O 38 I/O 39 I/O 32 I/O 33 I/O 34 I/O 35 TRST I/O 83 I/O 82 I/O 81 I/O 80 RESET 0139isp/3256 2 TDI/SDI I/O 95 I/O 94 I/O 93 I/O 92 Input Bus H1 Output Routing Pool (ORP) Output Routing Pool (ORP) H2 I/O 107 I/O 106 I/O 105 I/O 104 I/O 111 I/O 110 I/O 109 I/O 108 I/O 115 I/O 114 I/O 113 I/O 112 Output Routing Pool (ORP) Input Bus I/O 20 I/O 21 I/O 22 I/O 23 Input Bus I/O 16 I/O 17 I/O 18 I/O 19 Input Bus Output Routing Pool (ORP) Input Bus I/O 12 I/O 13 I/O 14 I/O 15 Output Routing Pool (ORP) I/O 8 I/O 9 I/O 10 I/O 11 Output Routing Pool (ORP) I/O 4 I/O 5 I/O 6 I/O 7 I/O 119 I/O 118 I/O 117 I/O 116 Input Bus H3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 123 I/O 122 I/O 121 I/O 120 I/O 127 I/O 126 I/O 125 I/O 124 Generic Logic Blocks CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1 TOE GOE1 GOE0 Figure 1. ispLSI 3256 Functional Block Diagram Specifications ispLSI 3256 Description (continued) All local logic block outputs are brought back into the GRP so they can be connected to the inputs of any other logic block on the device. The device also has 128 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, a registered input, a latched input, an output or a bidirectional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Clocks in the ispLSI 3256 device are provided through five dedicated clock pins. The five pins provide three clocks to the Twin GLBs and two clocks to the I/O cells. The table below lists key attributes of the device along with the number of resources available. An additional feature of the ispLSI 3256 is the Boundary Scan capability, which is composed of cells connected between the on-chip system logic and the device's input and output pins. All I/O pins have associated boundary scan registers, with 3-state I/O using three boundary scan registers and inputs using one. The 128 I/O Cells are grouped into eight sets of 16 bits. Each of these I/O groups is associated with a logic Megablock through the use of the ORP. These groups of 16 I/O cells share one Product Term Output Enable which is associated with a specific pair of Megablocks and two Global Output Enables. The ispLSI 3256 supports all IEEE 1149.1 mandatory instructions, which include BYPASS, EXTEST and SAMPLE. Key Attributes of the ispLSI 3256 Four Twin GLBs, 16 I/O Cells and one ORP are connected together to make a logic Megablock. The Megablock is defined by the resources that it shares. The outputs of the four Twin GLBs are connected to a set of 16 I/O cells by the ORP. The ispLSI 3256 device contains eight of these Megablocks. Attribute The GRP has as its inputs the outputs from all of the Twin GLBs and all of the inputs from the bidirectional I/O cells. All of these signals are made available to the inputs of the Twin GLBs. Delays through the GRP have been equalized to minimize timing skew and logic glitching. Quantity Twin GLBs 32 Registers 384 I/O Pins 128 Global Clocks 5 Global OE 2 Test OE 1 Table - 003Aisp/3256 3 Specifications ispLSI 3256 Absolute Maximum Ratings 1 Supply Voltage Vcc .................................. -0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C Max. Junction Temp. (TJ) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Condition PARAMETER SYMBOL TA VCC VIL VIH Ambient Temperature Supply Voltage MIN. MAX. UNITS 0 70 °C 4.75 5.25 V Input Low Voltage 0 0.8 V Input High Voltage 2.0 VCC +1 V Table 2 - 0005/3256 Capacitance (TA=25°C,f=1.0 MHz) SYMBOL C1 C2 MAXIMUM PARAMETER 1 UNITS TEST CONDITIONS I/O Capacitance 10 pf VCC = 5.0V, VI/O = 2.0V Clock Capacitance 12 pf VCC = 5.0V, VY = 2.0V Table 2 - 0006/3256 1. Characterized but not 100% tested. Data Retention Specifications PARAMETER MINIMUM MAXIMUM UNITS 20 – Years 10000 – Cycles Data Retention ispLSI Erase/Reprogram Cycles Table 2- 0008B 4 Specifications ispLSI 3256 Switching Test Conditions Input Pulse Levels Figure 2. Test Load GND to 3.0V + 5V ≤ 3ns 10% to 90% Input Rise and Fall Time Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load R1 Device Output See figure 2 3-state levels are measured 0.5V from steady-state active level. Table 2 - 0003 Test Point CL* R2 *CL includes Test Fixture and Probe Capacitance. Output Load conditions (See figure 2) 0213A TEST CONDITION R1 A B C R2 CL 470Ω 390Ω 35pF Active High ∞ 390Ω 35pF Active Low 470Ω 390Ω 35pF Active High to Z at VOH -0.5V ∞ 390Ω 5pF Active Low to Z at VOL +0.5V 470Ω 390Ω 5pF Table 2 - 0004A DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL VOL VOH IIL IIH IIL-isp IIL-PU IOS1 ICC 2,4 CONDITION PARAMETER 3 MIN. TYP. MAX. UNITS Output Low Voltage IOL= 8 mA – – 0.4 V Output High Voltage IOH = -4 mA 2.4 – – V Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (Max.) – – -10 µA Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC – – 10 µA Bscan/ispEN Input Low Leakage Current 0V ≤ VIN ≤ VIL – – -150 µA I/O Active Pull-Up Current 0V ≤ VIN ≤ VIL – – -150 µA Output Short Circuit Current VCC = 5V, VOUT = 0.5V – – -200 mA Operating Power Supply Current VIL = 0.0V, VIH = 3.0V fTOGGLE = 1 MHz – 150 270 mA Table 2 - 0007isp/3256 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using sixteen 16-bit counters. 3. Typical values are at VCC = 5V and TA = 25°C. 4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC. 5 Specifications ispLSI 3256 External Switching Characteristics1, 2, 3 Over Recommended Operating Conditions 5 PARAMETER tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis ttoeen ttoedis twh twl tsu3 th3 1. 2. 3. 4. 5. TEST #2 COND. -50 -70 DESCRIPTION1 MIN. MAX. MIN. MAX. UNITS A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 15.0 – 20.0 ns A 2 Data Propagation Delay – 18.0 – 24.5 ns 77 – 57 – MHz A 3 Clock Frequency with Internal Feedback 3 1 tsu2 + tco1 – 4 Clock Frequency with External Feedback ( 50 – 37 – MHz – 5 Clock Frequency, Max. Toggle 4 ) 83 – 63 – MHz – 6 GLB Reg. Setup Time before Clock, 4 PT Bypass 9.5 – 12.5 – ns A 7 GLB Reg. Clock to Output Delay, ORP Bypass – 9.0 – 12.0 ns – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – 0.0 – ns – 9 GLB Reg. Setup Time before Clock 11.0 – 15.0 – ns – 10 GLB Reg. Clock to Output Delay – 10.5 – 14.0 ns – 11 GLB Reg. Hold Time after Clock 0.0 – 0.0 – ns A 12 Ext. Reset Pin to Output Delay – 13 Ext. Reset Pulse Duration B – 15.0 – 20.0 ns 10.0 – 13.5 – ns 14 Input to Output Enable – 18.0 – 24.5 ns C 15 Input to Output Disable – 18.0 – 24.5 ns B 16 Global OE Output Enable – 11.0 – 13.5 ns C 17 Global OE Output Disable – 11.0 – 13.5 ns B 18 Test OE Output Enable – 17.0 – 23.0 ns C 19 Test OE Output Disable – 17.0 – 23.0 ns – 20 External Synchronous Clock Pulse Duration, High 6.0 – 8.0 – ns – 21 External Synchronous Clock Pulse Duration, Low 6.0 – 8.0 – ns – 22 I/O Reg. Setup Time before Ext. Sync. Clock (Y3, Y4) 5.0 – 7.0 – ns – 23 I/O Reg. Hold Time after Ext. Sync. Clock (Y3, Y4) 0.0 – 0.0 – ns Unless noted otherwise, all parameters use 20 PTXOR path and ORP. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Reference Switching Test Conditions section. 6 Table 2 - 0030A/3256 Specifications ispLSI 3256 Internal Timing Parameters1 Over Recommended Operating Conditions PARAMETER 2 # -50 -70 DESCRIPTION MIN. MAX. MIN. MAX. UNITS Inputs tiobp tiolat tiosu tioh tioco tior 24 I/O Register Bypass – 2.4 – 3.3 ns 25 I/O Latch Delay – 12.4 – 15.8 ns 26 I/O Register Setup Time before Clock 6.2 – 8.6 – ns 27 I/O Register Hold Time after Clock -5.2 – -7.0 – ns 28 I/O Register Clock to Out Delay – 4.2 – 5.3 ns 29 I/O Register Reset to Out Delay – 3.6 – 4.9 ns 30 GRP Delay – 3.0 – 4.1 ns 31 4 Product Term Bypass Path Delay – 5.9 – 7.6 ns 32 1 Product Term/XOR Path Delay – 6.4 – 8.8 ns 33 20 Product Term/XOR Path Delay – 7.4 – 10.1 ns – 8.1 – 11.1 ns – 0.1 – 0.1 ns 36 GLB Register Setup Time before Clock 1.8 – 2.4 – ns 37 GLB Register Hold Time after Clock 6.0 – 8.2 – ns 38 GLB Register Clock to Output Delay – 1.8 – 2.2 ns 39 GLB Register Reset to Output Delay – 2.8 – 3.8 ns 40 GLB Product Term Reset to Register Delay – 10.5 – 14.2 ns 41 GLB Product Term Output Enable to I/O Cell Delay – 5.4 – 7.3 ns 3.2 6.3 4.3 8.5 ns 43 ORP Delay – 2.7 – 3.6 ns 44 ORP Bypass Delay – 1.2 – 1.6 ns GRP tgrp GLB t4ptbp t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck 34 XOR Adjacent Path Delay 3 35 GLB Register Bypass Delay 42 GLB Product Term Clock Delay ORP torp torpbp 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. 7 Table 2 - 0036A/3256 Specifications ispLSI 3256 Internal Timing Parameters1 Over Recommended Operating Conditions PARAMETER 2 # -50 -70 DESCRIPTION MIN. MAX. MIN. MAX. UNITS Outputs tob tobs toen todis 45 Output Buffer Delay – 2.4 – 3.3 ns 46 Output Buffer Delay, Slow Slew – 12.4 – 13.3 ns 47 I/O Cell OE to Output Enabled – 7.2 – 9.8 ns 48 I/O Cell OE to Output Disabled – 7.2 – 9.8 ns 49 Clock Delay, Y0 or Y1 or Y2 to Global GLB Clock Line 3.6 3.6 4.9 4.9 ns 50 Clock Delay, Y3 or Y4 to I/O Cell Global Clock Line 1.2 5.2 1.6 7.0 ns – 7.1 – 9.6 ns Clocks tgy0/1/2 tioy3/4 Global Reset tgr 51 Global Reset to GLB and I/O Registers 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 8 Table 2 - 0037A/3256 Specifications ispLSI 3256 ispLSI 3256 Timing Model I/O Cell GRP GLB ORP I/O Cell Feedback I/O Reg Bypass I/O Pin (Input) #24 #51 GRP #30 Input D Register Q RST #25 - 29 4 PT Bypass GLB Reg Bypass ORP Bypass #31 #35 #44 20 PT XOR Delays GLB Reg Delay ORP Delay D #32 - 34 Q #43 RST #51 Reset Y3,4 #36 - 39 #50 Control RE PTs OE #40 - 42 CK #49 Y0,1,2 GOE0,1 TOE 0902/3256 Derivations of tsu, th and tco from the Product Term Clock 1 tsu = = = 8.0 ns = Logic + Reg su - Clock (min) (tiobp + tgrp + t20ptxor) + (tgsu) - (tiobp + tgrp + tptck(min)) (#24+ #30+ #33) + (#36) - (#24+ #30+ #42) (2.4 + 3.0 + 9.4) + (1.8) - (2.4 + 3.0 + 3.2) th = = = 2.9 ns = Clock (max) + Reg h - Logic (tiobp + tgrp + tptck(max)) + (tgh) - (tiobp + tgrp + t20ptxor) (#24+ #30+ #42) + (#37) - (#24+ #30+ #33) (2.4 + 3.0 + 6.3) + (6.0) - (2.4 + 3.0 + 9.4) tco = = = 18.6 ns = Clock (max) + Reg co + Output (tiobp + tgrp + tptck(max)) + (tgco) + (torp + tob) (#24 + #30 + #42) + (#38) + (#43 + #45) (2.4 + 3.0 + 6.3) + (1.8) + (2.7 + 2.4) Table 2- 0042-16/3256 Note: Calculations are based on timing specs for the ispLSI 3256-70L. 9 #45, 46 #47, 48 I/O Pin (Output) Specifications ispLSI 3256 Power Consumption Power Consumption in the ispLSI 3256 device depends on two primary factors: the speed at which the device is operating and the number of product terms used. Figure 3 shows the relationship between power and operating speed. Figure 3. Typical Device Power Consumption vs fmax ICC (mA) 250 ispLSI 3256 200 150 0 10 20 30 40 50 60 70 fmax (MHz) Notes: Configuration of 16 16-bit Counters Typical Current at 5V, 25° C ICC can be estimated for the ispLSI 3256 using the following equation: ICC = 44 + (# of PTs * 0.18) + (# of nets * Max. freq * 0.013) where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 0127A-16-80-isp/3256 10 Specifications ispLSI 3256 Pin Description NAME MQFP PIN NUMBERS 25, 32, 37, 42, 48, 54, 59, 65, 70, 76, 82, 87, 93, 106, 113, 118, 123, 129, 135, 140, 146, 152, 157, 3, 8, 15, GOE0 and GOE1 TOE 100 and 99 98 Global Output Enable input pins. Test output enable pin. TOE tristates all I/O pins when a logic low is driven. RESET 20 Y0, Y1 and Y2 18, 19, 103 Y3 and Y4 102, 101 Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the GLBs on the device. Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the I/O cells in the device. BSCAN/ispEN 2 21 Input – Dedicated in-system programming enable input pin. When this pin is high, the BSCAN TAP controller pins TMS, TDI, TDO and TCK are enabled. When this pin is brought low, the ISP state machine control pins MODE, SDI, SDO and SLCK are enabled. High-to-low transition of this pin will put the device in the programming mode and put all I/O pins in high-Z state. TDI/SDI 2 22 TCLK/SCLK 2 23 TMS/MODE 2 24 TRST/NC1, 2 97 TDO/SDO 2 104 Input - This pin performs two functions. It is the Test Data input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI is also used as one of the two control pins for the isp state machine. Input - This pin performs two functions. It is the Test Clock input pin when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. Input - This pin performs two functions. It is the Test Mode Select input pin when ispEN is logic high. When ispEN is logic low, it functions as pin to control the operation of the isp state machine. Input - Test Reset, active low to reset the Boundary Scan State Machine. Output - This pin performs two functions. When ispEN is logic low, it functions as the pin to read the isp data. When ispEN is high it functions as Test Data Out. GND 1, 81, 12, 111, 10, 107, 31, 131, 28, 34, 39, 44, 50, 56, 61, 67, 73, 78, 84, 89, 95, 109, 115, 120, 126, 132, 137, 142, 148, 154, 159, 5, 11, 17 Input/Output Pins - These are the general purpose I/O pins used by the logic array. I/O 0 - I/O 4 I/O 5 - I/O 9 I/O 10 - I/O 14 I/O 15 - I/O 19 I/O 20 - I/O 24 I/O 25 - I/O 29 I/O 30 - I/O 34 I/O 35 - I/O 39 I/O 40 - I/O 44 I/O 45 - I/O 49 I/O 50 - I/O 54 I/O 55 - I/O 59 I/O 60 - I/O 64 I/O 65 - I/O 69 I/O 70 - I/O 74 I/O 75 - I/O 79 I/O 80 - I/O 84 I/O 85 - I/O 89 I/O 90 - I/O 94 I/O 95 - I/O 99 I/O 100 - I/O 104 I/O 105 - I/O 109 I/O 110 - I/O 114 I/O 115 - I/O 119 I/O 120 - I/O 124 I/O 125 - I/O 127 VCC 26, 33, 38, 43, 49, 55, 60, 66, 72, 77, 83, 88, 94, 108, 114, 119, 124, 130, 136, 141, 147, 153, 158, 4, 9, 16, DESCRIPTION 27, 125, 51, 151 29, 35, 40, 46, 52, 57, 62, 68, 74, 79, 85, 90, 96, 110, 116, 121, 127, 133, 138, 144, 149, 155, 160, 6, 13, 45, 143 71, 30, 36, 41, 47, 53, 58, 64, 69, 75, 80, 86, 92, 105, 112, 117, 122, 128, 134, 139, 145, 150, 156, 2, 7, 14, 63, Ground (GND) 91, VCC Table 2 - 0002Bisp/3256 1. NC pins are not to be connected to any active signal, Vcc or GND. 2. Pins have dual function capability. 11 Specifications ispLSI 3256 Pin Configuration 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 I/O 113 I/O 112 I/O 111 I/O 110 I/O 109 I/O 108 I/O 107 I/O 106 I/O 105 VCC I/O 104 I/O 103 I/O 102 I/O 101 I/O 100 I/O 99 I/O 98 GND I/O 97 I/O 96 I/O 95 I/O 94 I/O 93 I/O 92 I/O 91 I/O 90 I/O 89 I/O 88 I/O 87 VCC I/O 86 I/O 85 I/O 84 I/O 83 I/O 82 GND I/O 81 I/O 80 I/O 79 I/O 78 ispLSI 3256 160-pin MQFP ispLSI 3256 Top View 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 I/O 71 I/O 70 I/O 69 VCC I/O 68 I/O 67 I/O 66 GND I/O 65 I/O 64 TDO/SDO2 Y2 Y3 Y4 GOE0 GOE1 TOE TRST/NC1, 2 I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 VCC I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 GND 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O 14 I/O 15 I/O 16 I/O 17 GND I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 VCC I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 GND I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 VCC I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 I/O 48 I/O 49 GND I/O 114 I/O 115 I/O 116 I/O 117 I/O 118 I/O 119 I/O 120 I/O 121 GND I/O 122 VCC I/O 123 I/O 124 I/O 125 I/O 126 I/O 127 Y0 Y1 RESET 2BSCAN/ispEN 2TDI/SDI 2TCLK/SCLK 2TMS/MODE I/O 0 I/O 1 GND I/O 2 I/O 3 I/O 4 VCC I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 1. NC pins are not to be connected to any active signal, Vcc or GND. 2. Pins have dual function capability. 12 160-MQFP/3256 Specifications ispLSI 3256 Part Number Description ispLSI 3256 – XX X X X Device Family Package M = MQFP Speed 70 = 77 MHz fmax 50 = 57 MHz fmax Power L = Low ES IG N Device Number S Grade Blank = Commercial D 0212Aisp/3256 ORDERING NUMBER 77 15 ispLSI 3256-70LM 160-Pin MQFP 57 20 ispLSI 3256-50LM 160-Pin MQFP U SE is pL SI 32 56 A FO R N tpd (ns) FAMILY fmax (MHz) ispLSI EW Ordering Information 13 PACKAGE Table 2 - 0041A-08isp/3256