ispLSI 3256A Data Sheet

ispLSI® 3256A Device Datasheet
June 2010
All Devices Discontinued!
Product Change Notification (PCN) #09-10 has been issued to discontinue all devices in
this data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
ispLSI 3256A
Ordering Part Number
ispLSI 3256A-70LQ
ispLSI 3256A-90LQ
ispLSI 3256A-70LQI
Product Status
Reference PCN
Discontinued
PCN#09-10
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
ispLSI 3256A
®
In-System Programmable High Density PLD
Functional Block Diagram
Output Routing Pool
Output Routing Pool
H3
G3
H2
H1
H0
A0
A1
OR
G2
G1
G0
Boundary
Scan
D Q
F3
D Q
F2
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Output Routing Pool
• HIGH-DENSITY PROGRAMMABLE LOGIC
— 128 I/O Pins
— 11000 PLD Gates
— 384 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
Output Routing Pool
Features
• HIGH-PERFORMANCE E CMOS TECHNOLOGY
— fmax = 90 MHz Maximum Operating Frequency
— tpd = 12 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
A3
Output Routing Pool
• IN-SYSTEM PROGRAMMABLE
— 5V In-System Programmable (ISP™) using Lattice
ISP or Boundary Scan Test (IEEE 1149.1) Protocol
— Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
Twin
GLB
D Q
Array
B1
F1
D Q
OR
B0
D Q
F0
D Q
E3
D Q
E2
D Q
B2
E1
Global Routing Pool
B3
E0
C0
C1
C2
C3
Output Routing Pool
D0
D1
D2
Output Routing Pool
®
AND Array
2
Array
A2
D3
Output Routing Pool
0139A
Description
• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE
The ispLSI 3256A is a High-Density Programmable Logic
Device containing 384 Registers, 128 Universal I/O pins,
five Dedicated Clock Input Pins, eight Output Routing
Pools (ORP) and a Global Routing Pool (GRP) which
allows complete inter-connectivity between all of these
elements. The ispLSI 3256A features 5V in-system
programmability and in-system diagnostic capabilities.
The ispLSI 3256A offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Five Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
The basic unit of logic on the ispLSI 3256A device is the
Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3.
There are a total of 32 Twin GLBs in the ispLSI 3256A
device. Each Twin GLB has 24 inputs, a programmable
AND array and two OR/Exclusive-OR Arrays, and eight
outputs which can be configured to be either combinatorial or registered. All Twin GLB inputs come from the
GRP.
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
3256a_09
1
May 1999
Specifications ispLSI 3256A
Functional Block Diagram
Input Bus
TMS/MODE
TCLK/SCLK
BSCAN/ispEN
I/O 99
I/O 98
I/O 97
I/O 96
I/O 103
I/O 102
I/O 101
I/O 100
I/O 107
I/O 106
I/O 105
I/O 104
I/O 111
I/O 110
I/O 109
I/O 108
I/O 115
I/O 114
I/O 113
I/O 112
I/O 119
I/O 118
I/O 117
I/O 116
I/O 123
I/O 122
I/O 121
I/O 120
I/O 127
I/O 126
I/O 125
I/O 124
Generic
Logic
Blocks
Input Bus
Output Routing Pool (ORP)
Output Routing Pool (ORP)
ISP and
Boundary
Scan TAP
TDI/SDI
TRST
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
G3
G2
G1
G0
A0
F3
A1
F2
A2
F1
A3
F0
E3
B1
E2
B2
E1
B3
E0
C0
C1
C2
C3
D0
D1
D2
D3
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
Input Bus
Y0
Y1
Y2
Y3
Y4
I/O 60
I/O 61
I/O 62
I/O 63
I/O 56
I/O 57
I/O 58
I/O 59
I/O 52
I/O 53
I/O 54
I/O 55
I/O 48
I/O 49
I/O 50
I/O 51
I/O 44
I/O 45
I/O 46
I/O 47
I/O 40
I/O 41
I/O 42
I/O 43
I/O 36
I/O 37
I/O 38
I/O 39
I/O 32
I/O 33
I/O 34
I/O 35
I/O 87
I/O 86
I/O 85
I/O 84
I/O 79
I/O 78
I/O 77
I/O 76
RESET
0139isp/3256A
2
I/O 91
I/O 90
I/O 89
I/O 88
I/O 83
I/O 82
I/O 81
I/O 80
Global Routing Pool
(GRP)
B0
TDO/SDO
I/O 95
I/O 94
I/O 93
I/O 92
Input Bus
H0
Input Bus
I/O 20
I/O 21
I/O 22
I/O 23
Input Bus
I/O 16
I/O 17
I/O 18
I/O 19
H1
Output Routing Pool (ORP)
I/O 12
I/O 13
I/O 14
I/O 15
H2
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
I/O 8
I/O 9
I/O 10
I/O 11
Input Bus
I/O 4
I/O 5
I/O 6
I/O 7
Output Routing Pool (ORP)
I/O 0
I/O 1
I/O 2
I/O 3
Output Routing Pool (ORP)
H3
Output Routing Pool (ORP)
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TOE
GOE1
GOE0
Figure 1. ispLSI 3256A Functional Block Diagram
I/O 75
I/O 74
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
Specifications ispLSI 3256A
Description (continued)
All local logic block outputs are brought back into the
GRP so they can be connected to the inputs of any other
logic block on the device. The device also has 128 I/O
cells, each of which is directly connected to an I/O pin.
Each I/O cell can be individually programmed to be a
combinatorial input, a registered input, a latched input, an
output or a bidirectional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
An additional feature of the ispLSI 3256A is its Boundary
Scan capability, which is composed of cells connected
between the on-chip system logic and the device’s input
and output pins. All I/O pins have associated boundary
scan registers, with 3-state I/O using three boundary
scan registers and inputs using one.
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The ispLSI 3256A supports the full boundary scan IEEE
1149.1 specification for ISP programming and boardlevel tests via the TAP controller port. It is also fully
backward compatible to the Lattice ISP interface. While
fully JEDEC file and functionally compatible with the
earlier ispLSI 3256 devices, the 3256A requires a modified Boundary Scan Description Library (BSDL) model to
support boundary scan test and programming. As a
result, existing 3256 test programs that use the boundary
scan test feature must be updated to use the 3256A.
Please contact Lattice Applications for the new model.
The 128 I/O cells are grouped into eight sets of 16 bits.
Each of these I/O groups is associated with a logic
Megablock through the use of the ORP. These groups of
16 I/O cells share one Product Term Output Enable which
is associated with a specific pair of Megablocks and two
Global Output Enables.
Four Twin GLBs, 16 I/O cells and one ORP are connected together to make a logic Megablock. The
Megablock is defined by the resources that it shares. The
outputs of the four Twin GLBs are connected to a set of
16 I/O cells by the ORP. The ispLSI 3256A device
contains eight of these Megablocks.
The ispLSI 3256A supports all IEEE 1149.1 mandatory
instructions, which include BYPASS, EXTEST and
SAMPLE.
Key Attributes of the ispLSI 3256A
Attribute
The GRP has as its inputs the outputs from all of the Twin
GLBs and all of the inputs from the bidirectional I/O cells.
All of these signals are made available to the inputs of the
Twin GLBs. Delays through the GRP have been equalized to minimize timing skew and logic glitching.
Clocks in the ispLSI 3256A device are provided through
five dedicated clock pins. The five pins provide three
clocks to the Twin GLBs and two clocks to the I/O cells.
Quantity
Twin GLBs
32
Registers
384
I/O Pins
128
Global Clocks
5
Global OE
2
Test OE
1
Table 1-0003A/3256
The table at right lists key attributes of the device along
with the number of resources available.
3
Specifications ispLSI 3256A
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
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Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
PARAMETER
SYMBOL
MIN.
MAX.
UNITS
Commercial
TA = 0°C to + 70°C
4.75
5.25
V
Industrial
TA = -40°C to + 85°C
4.5
5.5
V
Input Low Voltage
0
0.8
V
Input High Voltage
2.0
VCC
Supply Voltage
VIL
VIH
Vcc+1
V
Table 2-0005/3256A
Capacitance (TA=25°C,f=1.0 MHz)
TYPICAL
UNITS
I/O Capacitance (Commercial/Industrial)
9
pf
VCC = 5.0V, VI/O = 2.0V
Clock Capacitance
11
pf
VCC = 5.0V, VY = 2.0V
SYMBOL
C1
C2
PARAMETER
TEST CONDITIONS
Table 2-0006/3256A
Data Retention Specifications
PARAMETER
MINIMUM
MAXIMUM
20
–
Years
10000
–
Cycles
Data Retention
ispLSI Erase/Reprogram Cycles
UNITS
Table 2-0008/3256A
4
Specifications ispLSI 3256A
Switching Test Conditions
Input Pulse Levels
Figure 2. Test Load
GND to 3.0V
+ 5V
≤ 3ns 10% to 90%
Input Rise and Fall Time
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
R1
Device
Output
See Figure 2
Table 2-0003/3256A
3-state levels are measured 0.5V from
steady-state active level.
Test
Point
CL*
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R2
*CL includes Test Fixture and Probe Capacitance.
Output Load conditions (See Figure 2)
0213A
TEST CONDITION
A
B
C
R1
R2
CL
470Ω
390Ω
35pF
Active High
∞
390Ω
35pF
Active Low
470Ω
390Ω
35pF
Active High to Z
at VOH -0.5V
∞
390Ω
5pF
Active Low to Z
at VOL +0.5V
470Ω
390Ω
5pF
Table 2 - 0004A
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
VOL
VOH
IIL
IIH
IIL-isp
IIL-PU
IOS1
ICC2, 4
CONDITION
PARAMETER
3
MIN.
TYP.
MAX. UNITS
Output Low Voltage
IOL= 8 mA
–
–
0.4
V
Output High Voltage
IOH = -4 mA
2.4
–
–
V
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (Max.)
–
–
-10
µA
Input or I/O High Leakage Current
3.5V ≤ VIN ≤ VCC
–
–
10
µA
ispEN Input Low Leakage Current
0V ≤ VIN ≤ VIL
–
–
-150
µA
I/O Active Pull-Up Current
0V ≤ VIN ≤ VIL
–
–
-150
µA
Output Short Circuit Current
VCC = 5V, VOUT = 0.5V
–
–
-200
mA
Operating Power Supply Current
VIL = 0.0V, VIH = 3.0V
Commercial
–
200
–
mA
fCLOCK = 1 MHz
Industrial
–
200
–
mA
Table 2-0007/3256A
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using 16 16-bit counters.
3. Typical values are at VCC = 5V and TA= 25°C.
4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum ICC .
5
Specifications ispLSI 3256A
External Switching Characteristics1, 2, 3
Over Recommended Operating Conditions
5
PARAMETER
DESCRIPTION
-70
-90
1
-50
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
A
1 Data Prop. Delay, 4PT Bypass, ORP Bypass
–
12.0
–
15.0
–
20.0
ns
A
2 Data Prop. Delay
–
15.0
–
18.0
–
24.5
ns
90.0
–
77.0
–
57.0
–
MHz
61.0
–
50.0
–
37.0
–
MHz
125
–
83.0
–
63.0
–
MHz
8.0
–
9.5
–
12.5
–
ns
–
12.0
ns
0.0
–
ns
A
–
3 Clk Frequency with Internal Feedback
4 Clk Frequency with Ext. Feedback
(
3
1
tsu2 + tco1
)
1.
2.
3.
4.
5.
4
–
5 Clk Frequency, Max. Toggle
–
6 GLB Reg. Setup Time before Clk, 4 PT Bypass
A
7 GLB Reg. Clk to Output Delay, ORP Bypass
–
7.5
–
9.0
–
8 GLB Reg. Hold Time after Clk, 4 PT Bypass
0.0
–
0.0
–
–
9 GLB Reg. Setup Time before Clk
9.0
–
11.0
–
–
10 GLB Reg. Clk to Output Delay
–
9.0
–
10.5
–
11 GLB Reg. Hold Time after Clk
0.0
–
0.0
–
A
12 Ext. Reset Pin to Output Delay
–
13.5
–
15.0
–
13 Ext. Reset Pulse Duration
6.5
–
10.0
–
B
14 Input to Output Enable
–
16.0
–
18.0
C
15 Input to Output Disable
–
16.0
–
18.0
B
16 Global OE Output Enable
–
10.0
–
11.0
C
17 Global OE Output Disable
–
10.0
–
B
18 Test OE Output Enable
–
10.0
–
C
19 Test OE Output Disable
–
10.0
–
20 Ext. Synchronous Clk Pulse Duration, High
4.0
–
21 Ext. Synchronous Clk Pulse Duration, Low
–
–
23 I/O Reg Hold Time after Ext. Sync Clk (Y3, Y4)
USE 3256A70 FOR
NEW DESIG
NS
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tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
ttoeen
ttoedis
twh
twl
tsu3
th3
TEST
2
#
COND.
15.0
–
ns
–
14.0
ns
0.0
–
ns
–
20.0
ns
13.5
–
ns
–
24.5
ns
–
24.5
ns
–
13.5
ns
11.0
–
13.5
ns
17.0
–
23.0
ns
–
17.0
–
23.0
ns
–
6.0
–
8.0
–
ns
4.0
–
6.0
–
8.0
–
ns
22 I/O Reg Setup Time before Ext. Sync Clk (Y3, Y4) 5.0
–
5.0
–
7.0
–
ns
–
0.0
–
0.0
–
ns
0.0
Unless noted otherwise, all parameters use 20 PTXOR path and ORP.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
Reference Switching Test Conditions section.
6
Table 2-0030C/3256A
Specifications ispLSI 3256A
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER
#
2
-90
DESCRIPTION
-70
-50
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
24 I/O Register Bypass
–
1.9
–
2.4
–
3.3
ns
25 I/O Latch Delay
–
10.9
–
12.4
–
15.8
ns
5.7
–
6.2
–
8.6
ns
26 I/O Register Setup Time before Clock
–
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tiobp
tiolat
tiosu
tioh
tioco
tior
FOR NEW D
ESIGNS
Inputs
-3.7
–
-5.2
–
-7.0
–
ns
28 I/O Register Clock to Out Delay
–
4.2
–
4.2
–
5.3
ns
29 I/O Register Reset to Out Delay
–
2.8
–
3.6
–
4.9
ns
30 GRP Delay
–
2.4
–
3.0
–
4.1
ns
31 4 Product Term Bypass Path Delay (Comb.)
–
4.8
–
5.9
–
7.6
ns
32 4 Product Term Bypass Path Delay (Reg.)
–
4.8
–
5.9
–
7.6
ns
33 1 Product Term/XOR Path Delay
–
5.4
–
6.4
–
8.8
ns
34 20 Product Term/XOR Path Delay
–
6.4
–
7.4
–
10.1
ns
35 XOR Adjacent Path Delay 3
–
6.9
–
8.1
–
11.1
ns
36 GLB Register Bypass Delay
–
0.1
–
0.1
37 GLB Register Setup Time before Clock
1.0
–
1.8
–
38 GLB Register Hold Time after Clock
4.8
–
6.0
–
39 GLB Register Clock to Output Delay
–
1.6
–
1.8
40 GLB Register Reset to Output Delay
–
2.6
–
2.8
41 GLB Product Term Reset to Register Delay
–
8.6
–
10.5
27 I/O Register Hold Time after Clock
GRP
tgrp
t4ptbp
t4ptbp
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
–
4.9
–
5.4
2.8
5.3
3.2
6.3
44 ORP Delay
–
2.3
–
45 ORP Bypass Delay
–
0.9
–
42 GLB Product Term Output Enable to I/O Cell Delay
43 GLB Product Term Clock Delay
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
7
–
0.1
ns
2.4
–
ns
8.2
–
ns
–
2.2
ns
–
3.8
ns
–
14.2
ns
–
7.3
ns
4.3
8.5
ns
2.7
–
3.6
ns
1.2
–
1.6
ns
ORP
torp
torpbp
USE 3256A70
GLB
Table 2-0036C/3256A
Specifications ispLSI 3256A
Internal Timing Parameters1
Over Recommended Operating Conditions
2
#
-70
-90
DESCRIPTION
-50
MIN. MAX. MIN. MAX. MIN. MAX.
Outputs
46 Output Buffer Delay
–
1.9
–
2.4
47 Output Buffer Delay, Slew Limited Adder
–
11.9
–
12.4
48 I/O Cell OE to Output Enabled
–
6.8
–
7.2
UNITS
–
3.3
ns
–
13.3
ns
–
9.8
ns
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tob
tobs
toen
todis
USE 3256A70 FOR
NEW DESIG
NS
PARAMETER
49 I/O Cell OE to Output Disabled
–
6.8
–
7.2
50 Clock Delay, Y0 or Y1 or Y2 to Global GLB Clock Line
2.7
2.7
3.6
3.6
51 Clock Delay, Y3 or Y4 to I/O Cell Global Clock Line
0.7
3.7
1.2
5.2
52 Global Reset to GLB and I/O Registers
–
6.7
–
7.1
53 Global OE Pad Buffer
–
2.3
–
2.8
54 Test OE Pad Buffer
–
3.2
–
9.8
Clocks
tgy0/1/2
tioy3/4
Global Reset
tgr
tgoe
ttoe
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
8
–
9.8
ns
4.9
4.9
ns
1.6
7.0
ns
–
9.6
ns
–
3.7
ns
13.2
ns
–
Table 2-0037C/3256A
Specifications ispLSI 3256A
ispLSI 3256A Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
#31
I/O Reg Bypass
I/O Pin
(Input)
#24
#30
Input
D Register Q
RST
#25 - 29
4 PT Bypass
GLB Reg Bypass
ORP Bypass
#32
#36
#45
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
D
#33 - 35
Q
#44
#46, 47
#48, 49
I/O Pin
(Output)
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
#52
GRP
RST
#52
Reset
Y3,4
#37 - 40
#51
Control RE
PTs
OE
#41 - 43 CK
#50
Y0,1,2
#53
GOE0,1
#54
TOE
0902/3256A
Derivations of tsu, th and tco from the Product Term Clock 1
tsu
=
=
=
4.6 ns =
Logic + Reg su - Clock (min)
(tiobp + tgrp + t20ptxor) + (tgsu) - (tiobp + tgrp + tptck(min))
(#24+ #30+ #34) + (#37) - (#24+ #30+ #43)
(1.9 + 2.4 + 6.4) + (1.0) - (1.9 + 2.4 + 2.8)
th
=
=
=
3.7 ns =
Clock (max) + Reg h - Logic
(tiobp + tgrp + tptck(max)) + (tgh) - (tiobp + tgrp + t20ptxor)
(#24+ #30+ #43) + (#38) - (#24+ #30+ #34)
(1.9 + 2.4 + 5.3) + (4.8) - (1.9 + 2.4 + 6.4)
tco
=
=
=
15.4 ns =
Clock (max) + Reg co + Output
(tiobp + tgrp + tptck(max)) + (tgco) + (torp + tob)
(#24 + #30 + #43) + (#39) + (#44 + #46)
(1.9 + 2.4 + 5.3) + (1.6) + (2.3 + 1.9)
Table 2-0042/3256A
Note: Calculations are based on timing specs for the ispLSI 3256A-90L.
9
Specifications ispLSI 3256A
Power Consumption
Power consumption in the ispLSI 3256A device depends
on two primary factors: the speed at which the device is
operating and the number of product terms used.
Figure 3 shows the relationship between power and
operating speed.
Figure 3. Typical Device Power Consumption vs fmax
ispLSI 3256A
ICC (mA)
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
400
300
200
0
10
20
30
40
50
60
70
80
90
100
fmax (MHz)
Notes: Configuration of 16 16-bit Counters
Typical Current at 5V, 25° C
ICC can be estimated for the ispLSI 3256A using the following equation:
ICC = 40 + (# of PTs * 0.31) + (# of nets * Max. freq * 0.0094) where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two
GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to
operating conditions and the program in the device, the actual ICC should be verified.
0127A-16-80-isp/3256A
10
Specifications ispLSI 3256A
Pin Description
NAME
PQFP/MQFP PIN NUMBERS
29,
35,
40,
46,
52,
57,
62,
68,
74,
79,
85,
90,
96,
110,
116,
121,
127,
133,
138,
144,
149,
155,
160,
6,
13,
30,
36,
41,
47,
53,
58,
64,
69,
75,
80,
86,
92,
105,
112,
117,
122,
128,
134,
139,
145,
150,
156,
2,
7,
14,
DESCRIPTION
I/O 0 - I/O 4
I/O 5 - I/O 9
I/O 10 - I/O 14
I/O 15 - I/O 19
I/O 20 - I/O 24
I/O 25 - I/O 29
I/O 30 - I/O 34
I/O 35 - I/O 39
I/O 40 - I/O 44
I/O 45 - I/O 49
I/O 50 - I/O 54
I/O 55 - I/O 59
I/O 60 - I/O 64
I/O 65 - I/O 69
I/O 70 - I/O 74
I/O 75 - I/O 79
I/O 80 - I/O 84
I/O 85 - I/O 89
I/O 90 - I/O 94
I/O 95 - I/O 99
I/O 100 - I/O 104
I/O 105 - I/O 109
I/O 110 - I/O 114
I/O 115 - I/O 119
I/O 120 - I/O 124
I/O 125 - I/O 127
25,
32,
37,
42,
48,
54,
59,
65,
70,
76,
82,
87,
93,
106,
113,
118,
123,
129,
135,
140,
146,
152,
157,
3,
8,
15,
GOE0 and GOE1
TOE
100 and 99
98
Global Output Enable input pins.
Test output enable pin - This pin tristates all I/O pins when a logic low is
driven
RESET
20
Y0, Y1 and Y2
18, 19, 103
Y3 and Y4
102, 101
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
Dedicated Clock inputs. These clock inputs are connected to one of the
clock inputs of all the GLBs on the device.
Dedicated Clock inputs. These clock inputs are connected to one of the
clock inputs of all the I/O cells in the device.
BSCAN/ispEN
21
Input – Dedicated in-system programming enable input pin. When this pin is high,
the BSCAN TAP controller pins TMS, TDI, TDO and TCK are enabled. When this
pin is brought low, the ISP state machine control pins MODE, SDI, SDO and
SLCK are enabled. High-to-low transition of this pin will put the device in the
programming mode and put all I/O pins in high-Z state.
TDI/SDI
22
Input – This pin performs two functions depending on the state of the
BSCAN/ispEN pin. It is the Test Data input to the TAP Controller when the ispEN
is logic high. TDI is used to load BSCAN test data or programming data. When
ispEN is logic low, it functions as an input pin to load programming data into the
ISP state machine.
TCK/SCLK
23
Input – This pin performs two functions, depending on the state of the
BSCAN/ispEN pin. It is the Test Clock input pin when BSCAN/ispEN is logic high.
When BSCAN/ispEN is logic low, it functions as the clock for the ISP state
machine.
TMS/MODE
24
Input – This pin performs two functions, depending on the state of the
BSCAN/ispEN pin. It is the Test Mode Select input pin when BSCAN/ispEN is
logic high. When BSCAN/ispEN is logic low, it functions to control the operation of
the ISP state machine.
28,
34,
39,
44,
50,
56,
61,
67,
73,
78,
84,
89,
95,
109,
115,
120,
126,
132,
137,
142,
148,
154,
159,
5,
11,
17
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
26,
33,
38,
43,
49,
55,
60,
66,
72,
77,
83,
88,
94,
108,
114,
119,
124,
130,
136,
141,
147,
153,
158,
4,
9,
16,
TRST
97
Input – Test Reset, active low to reset the Boundary Scan state machine.
TDO/SDO
104
Output – This pin performs two functions, depending on the state of the
BSCAN/ispEN pin. It is the Test Data Output pin when BSCAN/ispEN is logic high,
and either BSCAN test data or programming data is shifted out. When
BSCAN/ispEN is logic low, it is the Serial Data Output of the ISP state machine.
GND
1,
81,
10,
107,
27,
125,
45,
143
63,
Ground (GND)
VCC
12,
111,
31,
131,
51,
151
71,
91,
VCC
Table 2-0002/3256A.a
11
Specifications ispLSI 3256A
Pin Configuration
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
I/O 113
I/O 112
I/O 111
I/O 110
I/O 109
I/O 108
I/O 107
I/O 106
I/O 105
VCC
I/O 104
I/O 103
I/O 102
I/O 101
I/O 100
I/O 99
I/O 98
GND
I/O 97
I/O 96
I/O 95
I/O 94
I/O 93
I/O 92
I/O 91
I/O 90
I/O 89
I/O 88
I/O 87
VCC
I/O 86
I/O 85
I/O 84
I/O 83
I/O 82
GND
I/O 81
I/O 80
I/O 79
I/O 78
ispLSI 3256A 160-Pin MQFP and 160-Pin PQFP Pinout Diagram
ispLSI 3256A
Top View
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
VCC
I/O 68
I/O 67
I/O 66
GND
I/O 65
I/O 64
TDO/SDO*
Y2
Y3
Y4
GOE0
GOE1
TOE
TRST
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
VCC
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
GND
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O 14
I/O 15
I/O 16
I/O 17
GND
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
VCC
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
GND
I/O 34
I/O 35
I/O 36
I/O 37
I/O 38
I/O 39
I/O 40
VCC
I/O 41
I/O 42
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
I/O 48
I/O 49
GND
I/O 114
I/O 115
I/O 116
I/O 117
I/O 118
I/O 119
I/O 120
I/O 121
GND
I/O 122
VCC
I/O 123
I/O 124
I/O 125
I/O 126
I/O 127
Y0
Y1
RESET
*BSCAN/ispEN
*TDI/SDI
*TCK/SCLK
*TMS/MODE
I/O 0
I/O 1
GND
I/O 2
I/O 3
I/O 4
VCC
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
160-PQFP/3256A
*Pins have dual function capability.
12
Specifications ispLSI 3256A
Part Number Description
ispLSI
3256A – XX
X
X
Device Family
X
Grade
Blank = Commercial
I = Industrial
Device Number
Package
M = MQFP
Q = PQFP
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
Speed
90 = 90 MHz fmax
70 = 77 MHz fmax
50 = 57 MHz fmax
Power
L = Low
0212/3256A
Ordering Information
COMMERCIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
ORDERING NUMBER
PACKAGE
90
12
ispLSI 3256A-90LM*
160-Pin MQFP
90
12
ispLSI 3256A-90LQ
160-Pin PQFP
77
15
ispLSI 3256A-70LM*
160-Pin MQFP
77
15
ispLSI 3256A-70LQ
160-Pin PQFP
57
20
ispLSI 3256A-50LM**
160-Pin MQFP
INDUSTRIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
ORDERING NUMBER
Table 2-0041B/3256A
PACKAGE
77
15
ispLSI 3256A-70LQI
160-Pin PQFP
57
20
ispLSI 3256A-50LMI**
160-Pin MQFP
*Use ispLSI 3256A in PQFP package for all new designs.
**Use ispLSI 3256A-70LQ/I for all new designs.
Table 2-0041C/3256A
13