ispLSI 1048C Data Sheet

ispLSI® 1048C Device Datasheet
September 2010
All Devices Discontinued!
Product Change Notifications (PCNs) have been issued to discontinue all devices in this
data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
ispLSI 1048C
Ordering Part Number
ispLSI 1048C-50LQ
ispLSI 1048C-70LQ
ispLSI 1048C-50LQI
ispLSI 1048C-50LG/883
5962-9558701MXC
Product Status
Discontinued
Reference PCN
PCN#13-10
PCN#05A-10
5555 N.E. Moore Ct.  Hillsboro, Oregon 97124-6421  Phone (503) 268-8000  FAX (503) 268-8347
Internet: http://www.latticesemi.com
ispLSI 1048C
®
In-System Programmable High Density PLD
Functional Block Diagram
• HIGH-DENSITY PROGRAMMABLE LOGIC
— 8000 PLD Gates
— 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output
Enables
— 288 Registers
— High-Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 70 MHz Maximum Operating Frequency
— fmax = 50 MHz for Industrial and Military/883 Devices
— tpd = 16 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 100% Tested at Time of Manufacture
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
Output Routing Pool
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
E7 E6 E5 E4 E3 E2 E1 E0
D7
D Q
A2
A3
Logic
D6
D5
D Q
D4
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Output Routing Pool
A0
A1
A4
Global Routing Pool (GRP)
Array
D Q
GLB
D3
D2
A5
D Q
A6
D1
A7
Output Routing Pool
Features
D0
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3 C4 C5 C6 C7
Output Routing Pool
Output Routing Pool
CLK
0139G1A-isp
Description
The ispLSI 1048C is a High-Density Programmable Logic
Device containing 288 Registers, 96 Universal I/O pins,
12 Dedicated Input pins, two Global Output Enables
(GOE), four Dedicated Clock Input pins and a Global
Routing Pool (GRP). The GRP provides complete
interconnectivity between all of these elements. The
ispLSI 1048C features 5-Volt in-system programming
and in-system diagnostic capabilities. It is the first device
which offers non-volatile reprogrammability of the logic,
and the interconnect to provide truly reconfigurable systems. Compared to the ispLSI 1048, the ispLSI 1048C
offers two additional dedicated inputs and two new Global Output Enable pins.
The basic unit of logic on the ispLSI 1048C device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. F7 in figure 1. There are a total of 48 GLBs in the ispLSI
1048C devices. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
other GLB on the device.
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
1048C_09
1
January 2002
Specifications ispLSI 1048C
Functional Block Diagram
Figure 1. ispLSI 1048C Functional Block Diagram
I/O I/O I/O I/O
95 94 93 92
I/O I/O I/O I/O
91 90 89 88
I/O I/O I/O I/O
87 86 85 84
I/O I/O I/O I/O
83 82 81 80
IN IN
11 10
I/O I/O I/O I/O
79 78 77 76
I/O I/O I/O I/O
75 74 73 72
I/O I/O I/O I/O
71 70 69 68
I/O I/O I/O I/O
67 66 65 64
IN
9
IN
8
RESET
Input Bus
Input Bus
Output Routing Pool (ORP)
Output Routing Pool (ORP)
GOE0
Generic
Logic Blocks
(GLBs)
GOE1
F6
F5
F4
F3
F2
F1
F0
E7
E6
E5
E4
E3
E2
E1
E0
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F7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
A0
D6
A1
D5
Global
Routing
Pool
(GRP)
A2
A3
A4
D4
D3
D2
A5
D1
A6
D0
lnput Bus
Input Bus
I/O 4
I/O 5
I/O 6
I/O 7
Output Routing Pool (ORP)
I/O 0
I/O 1
I/O 2
I/O 3
Output Routing Pool (ORP)
D7
IN 7
IN 6
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
A7
SDI/IN 0
MODE/IN 1
B0
B1
B2
B3
B4
B5
B6
B7
C0
C1
C2
C3
C4
C5
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
Input Bus
C6
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
C7
Clock
Distribution
Network
Megablock
ispEN
IN2 SDO/
IN3
I/O I/O I/O I/O
16 17 18 19
I/O I/O I/O I/O
20 21 22 23
I/O I/O I/O I/O
24 25 26 27
I/O I/O I/O I/O
28 29 30 31
IN SCLK/ I/O I/O I/O I/O
4 IN 5 32 33 34 35
I/O I/O I/O I/O
36 37 38 39
I/O I/O I/O I/O
40 41 42 43
I/O I/O I/O I/O
44 45 46 47
Y Y Y Y
0 1 2 3
0139F(2)-48B-isp
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
The device also has a 96 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
registered input, latched input, output or bi-directional
I/O pin with 3-state control. Additionally, all outputs have
selectable polarity, active high or active low. The signal
voltage levels are TTL-compatible, and the output drivers
can source 4 mA or sink 8 mA.
Clocks in the ispLSI 1048C device are selected using the
Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (D0 on the
ispLSI 1048C device). The logic of this GLB allows the
user to create an internal clock from a combination of
internal signals.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock as
shown in figure 1. The outputs of the eight GLBs are
connected to a set of 16 universal I/O cells by the ORP.
Each ispLSI 1048C device contains six Megablocks.
2
Specifications ispLSI 1048C
Absolute Maximum Ratings
1
Supply Voltage Vcc .................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
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Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL
VCC
PARAMETER
MAX.
UNITS
Commercial
TA = 0˚C to +70˚C
4.75
5.25
Industrial
TA = -40˚C to +85˚C
4.5
5.5
Military/883
TC = -55°C to +125°C
4.5
5.5
Input Low Voltage
0
0.8
V
Input High Voltage
2.0
Vcc + 1
V
Supply Voltage
VIL
VIH
MIN.
V
Table 2- 0005Aisp w/mil.eps
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL
C1
C2
1
MAXIMUM
PARAMETER
Dedicated Input Capacitance
UNITS
TEST CONDITIONS
Commercial/Industrial
8
pf
VCC=5.0V, VIN=2.0V
Military
10
pf
VCC=5.0V, VIN=2.0V
10
pf
VCC=5.0V, VI/O, VY=2.0V
I/O and Clock Capacitance
Table 2- 0006
1. Characterized but not 100% tested.
Data Retention Specifications
PARAMETER
MINIMUM
MAXIMUM
20
—
Years
10000
—
Cycles
Data Retention
Erase/Reprogram Cycles
UNITS
Table 2- 0008B
3
Specifications ispLSI 1048C
Switching Test Conditions
Input Pulse Levels
Figure 2. Test Load
GND to 3.0V
Input Rise and Fall Time
≤ 3ns 10% to 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
+ 5V
R1
See figure 2
Device
Output
Test
Point
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3-state levels are measured 0.5V from steady-state
active level.
Table 2- 0003
CL*
R2
Output Load Conditions (see figure 2)
Test Condition
R1
R2
CL
470Ω
390Ω
35pF
Active High
∞
390Ω
35pF
Active Low
470Ω
390Ω
35pF
Active High to Z
at VOH - 0.5V
∞
390Ω
5pF
Active Low to Z
470Ω
390Ω
5pF
A
B
C
*CL includes Test Fixture and Probe Capacitance.
at VOL + 0.5V
Table 2- 0004A
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
VOL
VOH
IIL
IIH
IIL-isp
IIL-PU
IOS1
ICC2,4
PARAMETER
CONDITION
MIN.
TYP.3
MAX.
UNITS
–
0.4
V
Output Low Voltage
IOL =8 mA
–
Output High Voltage
IOH =-4 mA
2.4
–
–
V
Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.)
–
–
-10
μA
Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC
–
–
10
μA
ispEN Input Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.)
–
–
-150
μA
I/O Active Pull-Up Current
0V ≤ VIN ≤ VIL
–
–
-150
μA
Output Short Circuit Current
VCC = 5V, VOUT = 0.5V
–
–
-200
mA
VIL = 0.5V, VIH = 3.0V Commercial
–
165
235
mA
fTOGGLE = 1 MHz
–
165
260
mA
Operating Power Supply Current
Industrial/Military
1. One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.
2. Measured using twelve 16-bit counters.
3. Typical values are at VCC = 5V and TA = 25oC.
4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum
Table 2- 0007A-48-isp
ICC.
4
Specifications ispLSI 1048C
External Timing Parameters
Over Recommended Operating Conditions
4 2
PARAMETER TEST #
COND.
-50
MIN. MAX. MIN. MAX.
UNITS
A
1
Data Propagation Delay, 4PT bypass, ORP bypass
–
16.0
–
22.0
ns
A
2
Data Propagation Delay
–
19.0
–
26.0
ns
70.4
–
50.3
–
MHz
47.6
–
34.5
–
MHz
83.3
–
58.8
–
MHz
9.5
–
13.0
–
ns
A
3
Clock Frequency with Internal
Feedback3
–
1
4 Clock Frequency with External Feedback ( tsu2 + tco1 )
1
5 Clock Frequency, Max Toggle ( twh + tw1 )
–
6
GLB Reg. Setup Time before Clock, 4PT bypass
A
7
GLB Reg. Clock to Output Delay, ORP bypass
–
10.0
–
14.0
ns
–
8
GLB Reg. Hold Time after Clock, 4 PT bypass
0
–
0
–
ns
–
9
GLB Reg. Setup Time before Clock
11.0
–
15.0
–
ns
–
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tpd1
tpd2
fmax (Int.)
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
tsu3
th3
-70
DESCRIPTION1
1.
2.
3.
4.
–
10 GLB Reg. Clock to Output Delay
–
11.5
–
16.0
ns
–
11 GLB Reg. Hold Time after Clock
0
–
0
–
ns
A
12 Ext. Reset Pin to Output Delay
–
15.0
–
20.5
ns
–
13 Ext. Reset Pulse Duration
10.0
–
13.5
–
ns
B
14 Input to Output Enable
–
20.0
–
27.5
ns
C
15 Input to Output Disable
–
20.0
–
27.5
ns
B
16 Global OE Output Enable
–
15.0
–
20.5
ns
C
17 Global OE Output Disable
–
15.0
–
20.5
ns
–
20 Ext. Sync. Clock Pulse Duration, High
6.0
–
8.5
–
ns
–
21 Ext. Sync. Clock Pulse Duration, Low
6.0
–
8.5
–
ns
–
22 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)
2.0
–
3.0
–
ns
–
23 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
6.5
–
9.0
–
ns
Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-Bit counter using GRP feedback.
Reference Switching Test Conditions section.
5
Table 2- 0030-48C/70, 50
Specifications ispLSI 1048C
Internal Timing Parameters1
PARAMETER
2
-70
DESCRIPTION
-50
MIN. MAX. MIN. MAX.
UNITS
24
I/O Register Bypass
–
3.1
–
4.3
ns
25
I/O Latch Delay
–
4.0
–
5.5
ns
26
I/O Register Setup Time before Clock
6.5
–
9.1
–
ns
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Inputs
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
GRP
tgrp1
tgrp4
tgrp8
tgrp16
tgrp48
GLB
t4ptbp
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
ORP
torp
torpbp
#
27
I/O Register Hold Time after Clock
0.1
–
0.3
–
ns
28
I/O Register Clock to Out Delay
–
3.4
–
4.6
ns
29
I/O Register Reset to Out Delay
–
3.7
–
5.1
ns
30
Dedicated Input Delay
–
5.4
–
7.4
ns
31
GRP Delay, 1 GLB Load
–
4.5
–
6.2
ns
32
GRP Delay, 4 GLB Loads
–
4.9
–
6.7
ns
33
GRP Delay, 8 GLB Loads
–
5.8
–
8.0
ns
34
GRP Delay, 16 GLB Loads
–
7.6
–
10.5
ns
35
GRP Delay, 48 GLB Loads
–
16.5
–
22.7
ns
36
4 Product Term Bypass Path Delay
–
4.0
–
5.5
ns
37
1 Product Term/XOR Path Delay
–
4.9
–
6.7
ns
38
20 Product Term/XOR Path Delay
–
5.5
–
7.5
ns
–
6.5
–
8.9
ns
–
0.9
–
1.2
ns
Delay3
39
XOR Adjacent Path
40
GLB Register Bypass Delay
41
GLB Register Setup Time before Clock
2.9
–
3.9
–
ns
42
GLB Register Hold Time after Clock
5.3
–
7.3
–
ns
43
GLB Register Clock to Output Delay
–
1.5
–
2.3
ns
44
GLB Register Reset to Output Delay
–
2.1
–
2.8
ns
45
GLB Product Term Reset to Register Delay
–
8.1
–
11.1
ns
46
GLB Product Term Output Enable to I/O Cell Delay
–
7.0
–
9.6
ns
47
GLB Product Term Clock Delay
2.5
6.0
3.4
8.2
ns
48
ORP Delay
–
2.5
–
3.4
ns
49
ORP Bypass Delay
–
1.0
–
1.4
ns
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
6
Table 2- 0036-48C/70, 50
Specifications ispLSI 1048C
Internal Timing Parameters1
ispLSI 1048C Timing Model
PARAMETER
#
2
-50
UNITS
MIN. MAX. MIN. MAX.
Output Buffer Delay
–
2.1
–
2.9
ns
I/O Cell OE to Output Enabled
–
5.0
–
6.9
ns
I/O Cell OE to Output Disabled
–
5.0
–
6.9
ns
–
10.0
–
13.6
ns
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
5.4
5.4
7.4
7.4
ns
Clock Delay, Y1 or Y2 to Global GLB Clock Line
4.5
6.4
6.1
8.7
ns
Clock Delay, Clock GLB to Global GLB Clock Line
1.9
5.5
2.6
7.6
ns
Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
4.5
6.4
6.1
8.7
ns
Clock Delay, Clock GLB to I/O Cell Global Clock Line
1.9
5.5
2.6
7.6
ns
–
8.3
–
11.4
ns
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Outputs
tob
50
toen
51
todis
52
tgoe
53
Clocks
tgy0
54
tgy1/2
55
tgcp
56
tioy2/3
57
tiocp
58
Global Reset
tgr
59
-70
DESCRIPTION
Global OE
Global Reset to GLB and I/O Registers
1. Internal Timing Parameters are not tested and are for reference only.
7
Table 2- 0037-48C/70, 50
Specifications ispLSI 1048C
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Ded. In
I/O Pin
(Input)
#59
#30
I/O Reg Bypass
4 PT Bypass
GLB Reg Bypass
ORP Bypass
#24
#32
#36
#40
#49
Input
D Register Q
RST
#25 - 29
GRP
Loading
Delay
#31, 33,
34, 35
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
GRP 4
#37, 38, 39
Q
I/O Pin
(Output)
#51, 52
#48
RST
#59
#41, 42,
43, 44
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Reset
D
#50
Clock
Distribution
Y1,2,3
#55, 56,
57, 58
Control RE
PTs
OE
#45, 46, CK
47
#54
Y0
GOE0, 1
#53
0491A/48
Derivations of tsu, th and tco from the Product Term Clock1
tsu
= Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min))
= (#24 + #32 + #38) + (#41) - (#24 + #32 + #47)
5.9 ns = (3.1 + 4.9 + 5.5) + (2.9) - (3.1 + 4.9 + 2.5)
th
= Clock (max) + Reg h - Logic
= (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
= (#24 + #32 + #47) + (#42) - (#24 + #32 + #38 )
5.8 ns = (3.1 + 4.9 + 6.0) + (5.3) - (3.1 + 4.9 + 5.5)
tco
= Clock (max) + Reg co + Output
= (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)
= (#24 + #32 + #47) + (#43) + (#48 + #50)
20.1 ns = (3.1 + 4.9 +6.0) + (1.5) + (2.5 + 2.1)
Derivations of tsu, th and tco from the Clock GLB1
tsu
= Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min))
= (#24 + #32 + #38) + (#41) - (#54 + #43 + #56)
7.6 ns = (3.1 + 4.9 + 5.5) + (2.9) - (5.4 + 1.5 + 1.9)
th
= Clock (max) + Reg h - Logic
= (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
= (#54 + #43 + #56) + (#42) - (#24 + #32 + #38)
4.2 ns = (5.4 + 1.5 + 5.5) + (5.3) - (3.1 + 4.9 + 5.5)
tco
= Clock (max) + Reg co + Output
= (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
= (#54 + #43 + #56) + (#43) + (#48 + #50)
18.5 ns = (5.4 + 1.5 + 5.5) + (1.5) + (2.5 + 2.1)
1. Calculations are based upon timing specifications for the ispLSI 1048C-70
8
Table 2- 0042-48C
Specifications ispLSI 1048C
Maximum GRP Delay vs GLB Loads
11
ispLSI 1048C-50
10
8
ispLSI 1048C-70
7
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
GRP Delay (ns)
9
6
5
4
3
4
1
8
12
16
GLB Loads
0126A-48C-80-isp
Power Consumption
Power consumption in the ispLSI 1048C device depends
on two primary factors: the speed at which the device is
operating, and the number of Product Terms used. Fig-
ure 3 shows the relationship between power and operating speed.
ICC (mA)
Figure 3. Typical Device Power Consumption vs fmax
250
ispLSI 1048C
200
150
100
50
0
10
20
30
40
50
60
70
80
fmax (MHz)
Notes: Configuration of Twelve 16-bit Counters
Typical Current at 5V, 25˚C
ICC can be estimated for the ispLSI 1048C using the following equation:
ICC = 73 + (# of PTs * 0.23) + (# of nets * Max. freq * 0.010) where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB
loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating
conditions and the program in the device, the actual ICC should be verified.
0127A-48C-80-isp
9
Specifications ispLSI 1048C
Pin Description
NAME
21, 22, 23, 24, 25,
27, 28, 29, 30, 31,
34, 35, 36, 37, 38,
40, 41, 42, 43, 44,
52, 53, 54, 55, 56,
58, 59, 60, 61, 62,
66, 67, 68, 69, 70,
72, 73, 74, 75, 76,
85, 86, 87, 88, 89,
91, 92, 93, 94, 95,
98, 99,100,101,102,
104,105,106,107,108,
117,118,119,120,121,
123,124,125,126,127,
2, 3, 4, 5, 6,
8, 9, 10, 11, 12,
26
32
39
45
57
63
71
77
90
96
103
109
122
128
7
13
DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
PQFP PIN NUMBERS
GOE0, GOE1
64, 114
Global output enables for all I/Os.
IN 2, IN 4
IN 6 - IN 11
47, 51
84,110,111, 115,116, 14
Dedicated input pins to the device.
ispEN
18
SDI/IN 01
20
MODE/IN 11
46
SDO/IN 31
50
SCLK/IN 51
78
RESET
19
Y0
15
Y1
83
Y2
80
Y3
79
GND
VCC
1, 17, 33, 49, 65, 81
97, 112
16, 48, 82, 113
Input – Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.
Input – This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
Input – This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
Input/Output – This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.
Input – This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.
Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
Ground (GND)
VCC
Table 2- 0002C-48C
1. Pins have dual function capability.
10
Specifications ispLSI 1048C
Pin Description
NAME
DESCRIPTION
CPGA PIN NUMBERS
J2,
L2,
M3,
P4,
N9,
N11,
M12,
L14,
F13,
D13,
C12,
A11,
B6,
B4,
C3,
D1,
J3,
K3,
P2,
M5,
M9,
M10,
N14,
K12,
F12,
E12,
A13,
C10,
C6,
C5,
B1,
E3,
GOE0, GOE1
N13,
B7,
IN 2, IN 4
IN 6 - IN 11
P7,
F14,
P9
A9,
K1,
N1,
N3,
N5,
P10,
P13,
M13,
K13,
E14,
B14,
B12,
B10,
A5,
A2,
C2,
E2,
L1,
M2,
M4,
P5,
P11,
N12,
L12,
K14,
D14,
C13,
C11,
A10,
A4,
B3,
D3,
E1,
K2,
L3,
P3,
M6,
N10,
M11,
M14,
J12,
E13,
D12,
A12,
C9,
B5,
C4,
C1,
F3,
M1,
P1,
N4,
N6,
P12,
P14,
L13,
J13,
C14,
A14,
B11,
B9,
A3,
A1,
D2,
F2
Input/Output Pins - These are the general purpose I/O pins used
by the logic array.
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
ispEN
H2
SDI/IN 01
J1
MODE/IN 11
P6
SDO/IN 31
P8
SCLK/IN 51
J14
RESET
H1
Y0
G1
Y1
G14
Y2
H13
Y3
H14
GND
B2,
M8,
C7,
N7
VCC
Global output enables for all I/Os.
Dedicated input pins to the device.
A8,
A7,
A6,
F1
Input – Dedicated in-system programming enable input pin. This
pin is brought low to enable the programming mode. The MODE,
SDI, SDO and SCLK options become active.
Input – This pin performs two functions. It is a dedicated input pin
when ispEN is logic high. When ispEN is logic low, it functions as
an input pin to load programming data into the device. SDI/IN 0
also is used as one of the two control pins for the isp state machine.
Input – This pin performs two functions. It is a dedicated input pin
when ispEN is logic high. When ispEN is logic low, it functions as
a pin to control the operation of the isp state machine.
Input/Output – This pin performs two functions. It is a dedicated
input pin when ispEN is logic high. When ispEN is logic low, it
functions as an output pin to read serial shift register data.
Input – This pin performs two functions. It is a dedicated input
when ispEN is logic high. When ispEN is logic low, it functions as
a clock pin for the Serial Shift Register.
Active Low (0) Reset pin which resets all of the GLB and I/O
registers in the device.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on
the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/
or any I/O cell on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on
the device.
B8, B13, C8, H3, H12,
N2,
N8
G2, G3, G12, G13, M7,
Ground (GND)
VCC
Table 2- 0002C-48C/CPGA
1. Pins have dual function capability.
11
Specifications ispLSI 1048C
Pin Configuration
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
IN 10
IN 9
GOE 1
VCC
GND
IN 8
IN 7
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 63
I/O 62
I/O 61
I/O 60
GND
ispLSI 1048C 128-Pin PQFP Pinout Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 6
Y1
VCC
GND
Y2
Y3
IN 5/SCLK1
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
GND
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
GND
I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
IN11
Y0
VCC
GND
ispEN
RESET
1 SDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
ispLSI 1048C
GND
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
1 MODE/IN 1
IN 2
VCC
GND
1 SDO/IN 3
IN 4
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
GOE 0
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Top View
1. Pins have dual function capability.
0124-48C
12
Specifications ispLSI 1048C
Pin Configuration
ispLSI 1048C 133-Pin CPGA Pinout Diagram
13
12
I/O59
I/O61
I/O56
GND
PIN A1
11
10
9
8
7
6
5
4
3
2
1
I/O64
I/O66
I/O69
IN7
IN8
IN9
IN10
I/O74
I/O75
I/O77
I/O80
I/O83
A
I/O62
I/O65
I/O68
I/O71
GND
GOE1
I/O72
I/O76
I/O78
I/O81
GND
I/O85
B
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
14
I/O82
I/O84
I/O86
I/O88
C
INDEX
I/O87
I/O89
I/O90
D
I/O55
I/O91
I/O92
I/O93
E
I/O48
I/O49
I/O94
I/O95
IN11
F
Y1
Vcc
Vcc
Vcc
Vcc
Y0
G
Y3
Y2
GND
GND
ispEN
RESET
H
SCLK/
IN51
I/O47
I/O46
I/O1
I/O0
SDI/
IN01
J
I/O45
I/O44
I/O43
I/O7
I/O4
I/O2
K
I/O42
I/O41
I/O39
I/O10
I/O6
I/O3
L
I/O40
I/O38
I/O36
I/O34
I/O37
GOE0
I/O33
I/O30
I/O28
I/O24
I/O35
I/O32
I/O29
I/O27
I/O26
IN4
I/O53
I/O57
I/O60
I/O51
I/O54
I/O58
I/O50
I/O52
IN6
I/O63
I/O67
I/O70
GND
Vcc
I/O73
I/O79
ispLSI 1048C/883
Bottom View
I/O31
I/O25
Vcc
I/O22
I/O19
I/O15
I/O12
I/O9
I/O5
M
GND
Vcc
I/O23
I/O20
I/O17
I/O14
GND
I/O8
N
SDO/
IN31
IN2
MODE/
IN11
I/O21
I/O18
I/O16
I/O13
I/O11
P
GND
133 CPGA Pinout.eps
1. Pins have dual function capability.
13
Specifications ispLSI 1048C
Part Number Description
ispLSI 1048C — XX
X
X
X
Device Family
Grade
Blank = Commercial
I = Industrial
/883 = 883 Military Process
Device Number
Package
Q = PQFP
G = CPGA
Power
L = Low
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
Speed
70 = 70 MHz fmax
50 = 50 MHz fmax
0212-80B-isp1048C
Ordering Information
COMMERCIAL
Family
fmax (MHz) tpd (ns)
ispLSI
Ordering Number
Package
70
16
ispLSI 1048C-70LQ
128-Pin PQFP
50
22
ispLSI 1048C-50LQ
128-Pin PQFP
INDUSTRIAL
Family
fmax (MHz) tpd (ns)
ispLSI
50
22
Ordering Number
Package
ispLSI 1048C-50LQI
128-Pin PQFP
MILITARY
Family
ispLSI
fmax (MHz) tpd (ns)
50
22
Ordering Number
SMD Number
Package
ispLSI 1048C-50LG/883
5962-9558701MXC
133-Pin CPGA
Table 2- 0041A-48C-isp
14