ISL8563 TM Data Sheet tle 85 jec V V, cro , kb /TI 62, /TI 32 s ers ei ) tho w rsi por n, ico cto V March 2001 File Number +3V to +5.5V, 1Microamp, 250kbps, EIA/TIA-562, EIA/TIA-232 Transmitters/Receivers Features The Intersil ISL8563 contains 3.0V to 5.5V powered transmitters/receivers which meet ElA/TIA-562 and ElA/TIA-232 specifications, even at VCC = 3.0V. Targeted applications are PDAs, Palmtops, and notebook and laptop computers where the low operational, and even lower standby, power consumption is critical. Efficient on-chip charge pumps, coupled with a manual powerdown function, reduce the standby supply current to a 1µA trickle. Small footprint packaging, and the use of small, low value capacitors ensure board space savings as well. Data rates greater than 250kbps are guaranteed at worst case load conditions. The ISL8563 is fully compatible with 3.3V only systems, mixed 3.3V and 5.0V systems, and 5.0V only systems. • Available as ±15kV ESD Protected Version (ISL8563E) This product features an improved charge pump which delivers ±5V transmitter supplies, allowing the use of the ISL8563 in RS-562 and RS-232 applications. RS-562 applications will benefit from the improved noise immunity afforded by the ±5V output swing capability. • Any System Requiring RS-562/RS-232 Communication Ports - Battery Powered, Hand-Held, and Portable Equipment - Laptop Computers, Notebooks, Palmtops - Digital Cameras - Bar Code Readers • Drop in Replacement for MAX563, with Improved Output Voltage (±5V) for Enhanced Noise Immunity Table 1 summarizes the features of the device represented by this data sheet, while Application Note AN9863 summarizes the features of each device comprising the 3V RS-232 family. For a drop-in compatible part with ±15kV ESD protection, please see the ISL8563E data sheet. • Latch-Up Free • On-Chip Voltage Converters Require Only Four External 0.1µF Capacitors • Receivers Active in Powerdown • Receiver Hysteresis For Improved Noise Immunity • Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps • Guaranteed Minimum Slew Rate . . . . . . . . . . . . . . . 4V/µs • Wide Power Supply Range. . . . . . . . Single +3V to +5.5V • Low Supply Current in Powerdown State . . . . . . . . . . . 1µA Applications Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • Application Note AN9863, “3V to +5.5V, 250K-1Mbps, RS-232 Transmitters/Receivers” Ordering Information PART NO. • Meets EIA/TIA-562, and EIA/TIA-232 Specifications at 3V Pinout TEMP. RANGE ( oC) PACKAGE PKG. NO. ISL8563CB 0 to 70 18 Ld SOIC M18.3 ISL8563CB-T 0 to 70 Tape and Reel M18.3 ISL8563CP 0 to 70 18 Ld PDIP E18.3 ISL8563IB -40 to 85 18 Ld SOIC M18.3 ISL8563IB-T -40 to 85 Tape and Reel M18.3 ISL8563 (PDIP, SOIC) TOP VIEW EN 1 ect 18 SHDN C1+ 2 17 VCC V+ 3 16 GND C1- 4 15 T1OUT C2+ 5 14 R1 IN C2- 6 13 R1 OUT V- 7 12 T1IN T2 OUT 8 11 T2IN R2IN 9 an y el, , 6005 10 R2 OUT TABLE 1. SUMMARY OF FEATURES PART NUMBER ISL8563 NO. OF NO. OF Tx. Rx. 2 2 1 NO. OF MONITOR Rx. (R OUTB) DATA RATE (kbps) Rx. ENABLE FUNCTION? READY OUTPUT? MANUAL POWERDOWN? AUTOMATIC POWERDOWN FUNCTION? 0 250 YES NO YES NO CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001, All Rights Reserved ISL8563 Pin Descriptions PIN VCC FUNCTION System Power Supply Input (3.0V to 5.5V). V+ Internally Generated Positive Transmitter Supply (+5.5V). V- Internally Generated Negative Transmitter Supply (-5.5V). GND Ground Connection. C1+ External Capacitor (Voltage Doubler) is connected to this lead. C1- External Capacitor (Voltage Doubler) is connected to this lead. C2+ External Capacitor (Voltage Inverter) is connected to this lead. C2- External Capacitor (Voltage Inverter) is connected to this lead. TIN TTL/CMOS Compatible Transmitter Inputs with pull-up resistors. TOUT RIN RS-562/RS-232 level (nominally ±5.5V) transmitter outputs. RS-562/RS-232 compatible receiver inputs. ROUT TTL/CMOS Level Receiver Outputs. EN Active Low Receiver Enable Control. SHDN Active Low Input which shuts down transmitters and on-board power supply, to place device in low power mode. Typical Operating Circuit ISL8563 +3.3V C1 0.1µF C2 0.1µF + 0.1 µF 2 + 4 5 + 6 17 C1+ C3 0.1µF VCC V+ 3 C1C2+ 7 VC2- + VCC T1IN TTL/CMOS LOGIC LEVELS T2IN R1OUT 12 400k Ω T1 15 VCC 11 400k Ω T2 T1OUT T2OUT 14 5k Ω R1 R1IN 9 10 R2OUT R2IN 5k Ω R2 SHDN GND 16 2 C4 0.1µF 8 13 1 EN + 18 VCC RS-562/232 LEVELS ISL8563 Absolute Maximum Ratings Thermal Information VCC to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V Input Voltages TIN, EN, SHDN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V RIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V Output Voltages TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V ROUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V CC +0.3V Short Circuit Duration TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table Thermal Resistance (Typical, Note 1) θJA (oC/W) 18 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . 80 18 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 75 Moisture Sensitivity (see Technical Brief TB363) All Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range ISL8563CX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC ISL8563IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Test Conditions: VCC = 3V to 5.5V, C1 - C 4 = 0.1µF; Unless Otherwise Specified. Typicals are at TA = 25oC Electrical Specifications PARAMETER TEST CONDITIONS TEMP (oC) MIN TYP MAX UNITS RS-562/RS-232 TRANSMITTERS Output Voltage Swing All Transmitter Outputs Loaded with 3kΩ to Ground Full ±5.0 ±5.4 - V Maximum Data Rate RL = 3kΩ, C L = 1000pF, One Transmitter Switching and Maintaining ±5V Output Swing Full 250 500 - kbps Input Logic Threshold Low TIN Full - - 0.8 V Input Logic Threshold High TIN VCC = 3.0V to 5.0V Full 2.4 - - V Transmitter Pull-Up Input Current TIN SHDN = VCC SHDN = GND Full - 2 20 µA Full - ±0.01 ±1.0 µA Full - - ±10 µA VOUT = ±12V, VCC = 0V or 3.6V to 5.5V, SHDN = GND Output Leakage Current Output Resistance V CC = V+ = V- = 0V, Transmitter Output = ±2V Full 300 10M - Ω Output Short-Circuit Current V OUT = 0V Full - ±35 ±60 mA Full -25 - 25 V Input Threshold Low V CC = 3.3V Full - 1.2 0.6 V V CC = 5.0V Full - 1.5 0.8 V Input Threshold High V CC = 3.3V Full 2.4 1.5 - V V CC = 5.0V Full 2.4 1.8 - V Full 0.1 0.5 1.0 V Full 3 5 7 kΩ - - 0.4 V RS-562/RS-232 RECEIVERS Input Voltage Range V CC = 3.0V to 3.6V Input Hysteresis Input Resistance Output Voltage Low IOUT = 3.2mA Full Output Voltage High IOUT = -1.0mA Full Output Leakage Current EN = VCC Full EN Input Logic Threshold Low EN Input Logic Threshold High V CC = 3.0V to 5.0V VCC -0.6 VCC -0.1 - V - ±0.05 ±10 µA Full - - 0.8 V Full 2.4 - - V Full 3.0 - 5.5 V Full - 0.5 6.0 mA POWER SUPPLY Operating Supply Voltage Supply Current SHDN = VCC Supply Current, Powerdown SHDN = GND All Outputs Unloaded All Outputs loaded, RL = 3kΩ SHDN Input Leakage Current 3 25 - 14 - mA 25 - 1 10 µA Full - 1 25 µA Full - ±0.01 ±1.0 µA ISL8563 Test Conditions: VCC = 3V to 5.5V, C1 - C 4 = 0.1µF; Unless Otherwise Specified. Typicals are at TA = 25oC (Continued) Electrical Specifications TEMP (oC) MIN TYP MAX UNITS SHDN Input Logic Threshold Low Full - - 0.8 V SHDN Input Logic Threshold High V CC = 3.0V to 5.0V AC CHARACTERISTICS Full 2.4 - - V PARAMETER TEST CONDITIONS Transition Region Slew Rate V CC = 3.3V, RL = 3kΩ to 7kΩ, Measured From 3V to -3V or -3V to 3V, CL = 50pF to 2500pF 25 4 - 30 V/µs Transmitter Propagation Delay Transmitter Input to Transmitter Output, CL = 1000pF, R L = 3kΩ tPHL (Note 2) Full - 1 3.5 µs tPLH (Note 2) Full - 1 3.5 µs Receiver Input to Receiver Output, CL = 150pF tPHL (Note 3) Full - 0.3 1.0 µs tPLH (Note 3) Full - 0.3 1.0 µs Receiver Output Enable Time Figure 1 tER Full - 125 500 ns Receiver Output Disable Time Figure 1 tDR Full - 160 500 ns Transmitter Output Enable Time Figure 2 tET 25 - 17 - µs tDT Receiver Propagation Delay Transmitter Output Disable Time Figure 2 25 - 600 - ns Transmitter Skew tPHL - tPLH (Note 2) 25 - 100 - ns Receiver Skew tPHL - tPLH (Note 3) 25 - 100 - ns Human Body Model 25 - ±15 - kV IEC1000-4-2 Contact Discharge 25 - ±8 - kV ESD PERFORMANCE RS-562 Pins (TOUT, RIN) All Other Pins IEC1000-4-2 Air Gap Discharge 25 - ±8 - kV Human Body Model 25 - ±3 - kV NOTES: 2. Transmitter is measured at the transmitter zero crossing points. 3. Receiver is measured at the receiver 50 percent crossing points. Test Waveforms VCC VCC EN INPUT 0V 0V SHDN INPUT tER tET RECEIVER 0.5VCC OUTPUT C = 150pF to GND L RL = 1k Ω to 0.5VCC VCC - 0.6V +0.4V VCC +3.7V TRANSMITTER OUTPUT SHDN INPUT 0V CL = 50pF RL = 3kΩ VCC 0V EN INPUT 0V tDR tDT VOH RECEIVER OUTPUT VOL -3.7V V+ +3.7V VOH - 0.1V 0.5VCC VOL + 0.1V CL = 150pF to GND RL = 1k Ω to 0.5VCC FIGURE 1. RECEIVER OUTPUT ENABLE AND DISABLE TIMING 4 TRANSMITTER OUTPUT 0V V- -3.7V CL = 50pF RL = 3kΩ FIGURE 2. TRANSMITTER OUTPUT ENABLE AND DISABLE TIMING ISL8563 Detailed Description The ISL8563 operates from a single +3V to +5.5V supply, guarantees a 250kbps minimum data rate, requires only four small external 0.1µF capacitors, features low power consumption, and meets all ElA/TIA-562 and EIA/TIA-232 specifications. The circuit is divided into three sections: The charge pump, the transmitters, and the receivers. (VCC = 0V). The receivers’ Schmitt trigger input stage uses hysteresis (even in powerdown) to increase noise immunity and decrease errors due to slow input signal transitions. The ISL8563 inverting receivers disable only when EN is driven high. Standard receivers driving powered down peripherals must be disabled to prevent current flow through the peripheral’s protection diodes (see Figures 4 and 5). Charge-Pump Intersil’s new ISL8563 utilizes regulated on-chip dual charge pumps as voltage doublers, and voltage inverters to generate ±5.5V transmitter supplies from a VCC supply as low as 3.0V. This allows these devices to maintain RS-232 compliant output levels over the ±10% tolerance range of 3.3V powered systems. The efficient on-chip power supplies require only four small, external 0.1µF capacitors for the voltage doubler and inverter functions over the full VCC range. The charge pumps operate discontinuously (i.e., they turn off as soon as the V+ and V- supplies are pumped up to the nominal values), resulting in significant power savings. Transmitters The transmitters are proprietary, low dropout, inverting drivers that translate TTL/CMOS inputs to EIA/TIA-562/232 output levels. Coupled with the on-chip ±5.5V supplies, these transmitters deliver true RS-562/232 levels over a wide range of single supply system voltages. All transmitter outputs disable and assume a high impedance state when the device enters the powerdown mode (see Table 2). These outputs may be driven to ±12V when disabled. All devices guarantee a 250kbps data rate (VOUT = ±5V) for full load conditions (3kΩ and 1000pF), VCC ≥ 3.0V, with one transmitter operating at full speed. Under more typical conditions of V CC ≥ 3.3V, RL = 3kΩ, and CL = 250pF, one transmitter easily operates at 900kbps. Unused transmitter inputs may be left unconnected because they will be pulled to VCC by the on-chip pull-up resistors. Forcing the ISL8563 into power down disables the pull-up resistors to further minimize power. Receivers The ISL8563 contains standard inverting receivers that three-state via the EN control line. All the receivers convert RS-562/232 signals to CMOS output levels and accept inputs up to ±25V while presenting the required 3kΩ to 7kΩ input impedance (see Figure 3) even if the power is off VCC RXIN RXOUT -25V ≤ VRIN ≤ +25V 5k Ω GND ≤ VROUT ≤ VCC GND FIGURE 3. INVERTING RECEIVER CONNECTIONS Powerdown Functionality This 3V device requires a nominal supply current of 0.3mA during normal operation (not in powerdown mode). This is considerably less than the 5mA to 11mA current required by 5V devices. The already low current requirement drops significantly when the device enters powerdown mode. In powerdown, supply current drops to 1µA, because the onchip charge pump turns off (V+ collapses to V CC, Vcollapses to GND), the transmitter outputs three-state, and the transmitter input pull-ups disable. This micro-power mode makes the ISL8563 ideal for battery powered and portable applications. Software Controlled (Manual) Powerdown The ISL8563, is forced into its low power, stand by state via a simple shutdown (SHDN) pin. Driving this pin high enables normal operation, while driving it low forces the IC into its powerdown state. Connect SHDN to VCC if the powerdown function isn’t needed. Note that all the receiver outputs remain enabled during shutdown (see Table 2). For the lowest power consumption during powerdown, the receivers should also be disabled by driving the EN input high (see next section, and Figures 4 and 5). The time required to exit powerdown, and resume transmission is less than 30µs. Receiver ENABLE Control The device also features an EN input to control the receiver outputs. Driving EN high disables all the receiver outputs placing them in a high impedance state. This is useful to eliminate supply current, due to a receiver output forward biasing the protection diode, when driving the input of a powered down (VCC = GND) peripheral (see Figure 4). The enable input has no effect on transmitters. TABLE 2. POWERDOWN AND ENABLE LOGIC TRUTH TABLE SHDN INPUT EN INPUT TRANSMITTER OUTPUTS L L High-Z Active Manual Powerdown L H High-Z High-Z Manual Powerdown w/Rcvr. Disabled H L Active Active Normal Operation H H Active High-Z Normal Operation w/Rcvr. Disabled 5 RECEIVER OUTPUTS MODE OF OPERATION ISL8563 Transmitter Outputs When Exiting Powerdown VCC VCC VCC Figure 6 shows the response of two transmitter outputs when exiting powerdown mode. As they activate, the two transmitter outputs properly go to opposite RS-562/232 levels, with no glitching, ringing, nor undesirable transients. Each transmitter is loaded with 3kΩ in parallel with 2500pF. Note that the transmitters enable only when the magnitude of the supplies exceed approximately 3V. CURRENT FLOW VOUT = VCC Rx POWERED DOWN UART Tx SHDN = GND GND OLD RS-562/232 CHIP 5V/DIV. SHDN FIGURE 4. POWER DRAIN THROUGH POWERED DOWN PERIPHERAL T1 VCC 2V/DIV. TRANSITION DETECTOR TO WAKE-UP LOGIC ISL8563 T2 VCC = +3.3V C1 - C4 = 0.1µF VCC TIME (20 µs/DIV.) RX POWERED DOWN UART VOUT = HI-Z R2OUT TX R2IN FIGURE 6. TRANSMITTER OUTPUTS WHEN EXITING POWERDOWN High Data Rates T1IN T1OUT SHDN = GND, EN = VCC FIGURE 5. DISABLED RECEIVERS PREVENT POWER DRAIN Capacitor Selection The charge pumps operate with 0.1µF (or greater) capacitors for 3.0V ≤ VCC ≤ 5.5V. Increasing the capacitor values (by a factor of 2) reduces ripple on the transmitter outputs and slightly reduces power consumption. C2, C3, and C4 can be increased without increasing C1’s value, however, do not increase C1 without also increasing C2, C3, and C4 to maintain the proper ratios (C1 to the other capacitors). The ISL8563 maintains the RS-232 ±5V minimum transmitter output voltages even at high data rates. Figure 7 details a transmitter loopback test circuit, and Figure 8 illustrates the loopback test result at 120kbps. For this test, all transmitters were simultaneously driving RS-232 loads in parallel with 1000pF, at 120kbps. Figure 9 shows the loopback results for a single transmitter driving 1000pF and an RS-232 load at 250kbps. The static transmitters were also loaded with an RS-232 receiver. VCC 0.1µF + + VCC C1+ V+ C1 C1- When using minimum required capacitor values, make sure that capacitor values do not degrade excessively with temperature. If in doubt, use capacitors with a larger nominal value. The capacitor’s equivalent series resistance (ESR) usually rises at low temperatures and it influences the amount of ripple on V+ and V-. + 6 V- 400kΩ TIN ROUT EN VCC ISL8563 VCC C2- Power Supply Decoupling In most circumstances a 0.1µF bypass capacitor is adequate. In applications that are particularly sensitive to power supply noise, decouple VCC to ground with a capacitor of the same value as the charge-pump capacitor C1. Connect the bypass capacitor as close as possible to the IC. C2+ C2 + C3 C4 + TOUT RIN 1000pF 5K SHDN FIGURE 7. TRANSMITTER LOOPBACK TEST CIRCUIT ISL8563 Interconnection with 3V and 5V Logic 5V/DIV. The ISL8563 directly interface with most 5V logic families, including ACT and HCT CMOS. See Table 3 for more information on possible combinations of interconnections. T1IN TABLE 3. LOGIC FAMILY COMPATIBILITY WITH VARIOUS SUPPLY VOLTAGES T1OUT SYSTEM POWER-SUPPLY VOLTAGE (V) VCC SUPPLY VOLTAGE (V) 3.3 3.3 5 5 5 3.3 R1OUT VCC = +3.3V C1 - C4 = 0.1µF 5µs/DIV. FIGURE 8. LOOPBACK TEST AT 120kbps COMPATIBILITY Compatible with all CMOS families. Compatible with all TTL and CMOS logic families. Compatible with ACT and HCT CMOS, and with TTL. Incompatible with AC, HC, or CD4000 CMOS. 5V/DIV. T1IN T1OUT R1OUT VCC = +3.3V C1 - C4 = 0.1 µF 2µs/DIV. FIGURE 9. LOOPBACK TEST AT 250kbps Typical Performance Curves VCC = 3.3V, TA = 25oC 25 VOUT+ 4 20 SLEW RATE (V/µs) TRANSMITTER OUTPUT VOLTAGE (V) 6 2 1 TRANSMITTER AT 250kbps 1 TRANSMITTER AT 30kbps 0 -2 15 -SLEW +SLEW 10 VOUT - -4 -6 0 1000 2000 3000 4000 5000 LOAD CAPACITANCE (pF) FIGURE 10. TRANSMITTER OUTPUT VOLTAGE vs LOAD CAPACITANCE 7 5 0 1000 2000 3000 4000 LOAD CAPACITANCE (pF) FIGURE 11. SLEW RATE vs LOAD CAPACITANCE 5000 ISL8563 Typical Performance Curves VCC = 3.3V, TA = 25oC (Continued) 3.5 45 40 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 250kbps 35 30 25 120kbps 20 15 NO LOAD ALL OUTPUTS STATIC 3.0 20kbps 10 2.5 2.0 1.5 1.0 0.5 5 0 0 1000 2000 3000 4000 5000 0 2.5 3.0 LOAD CAPACITANCE (pF) FIGURE 12. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA 3.5 4.0 PASSIVATION: 100 mils x 100 mils (2540µm x 2540µm) METALLIZATION: Type: Silox Thickness: 13kÅ TRANSISTOR COUNT: Type: Metal 1: AISi(1%) Thickness: Metal 1: 8kÅ Type: Metal 2: AISi (1%) Thickness: Metal 2: 10kÅ 338 PROCESS: Si Gate CMOS SUBSTRATE POTENTIAL (POWERED UP): Floating 8 5.0 5.5 FIGURE 13. SUPPLY CURRENT vs SUPPLY VOLTAGE Die Characteristics DIE DIMENSIONS: 4.5 SUPPLY VOLTAGE (V) 6.0 ISL8563 Dual-In-Line Plastic Packages (PDIP) E18.3 (JEDEC MS-001-BC ISSUE D) N 18 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 C D 0.845 0.880 eB D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. e 0.100 BSC 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. L 0.115 N 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 9 0.204 18 0.355 21.47 22.35 5 2.54 BSC - 7.62 BSC 6 0.430 - 0.150 2.93 18 10.92 7 3.81 4 9 Rev. 0 12/93 ISL8563 Small Outline Plastic Packages (SOIC) M18.3 (JEDEC MS-013-AB ISSUE C) N 18 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA 0.25(0.010) M H B M INCHES E -B1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.4469 0.4625 11.35 11.75 3 E 0.2914 0.2992 7.40 7.60 4 e µα B S 0.050 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N α NOTES: MILLIMETERS 18 0o 18 8o 0o 7 8o Rev. 0 12/93 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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