RFD16N03L, RFD16N03LSM
Data Sheet
16A, 30V, 0.025 Ohm, Logic Level,
N-Channel Power MOSFETs
These are N-Channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI circuits, gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switching regulators, switching converters, motor drivers and
relay drivers. This performance is accomplished through a
special gate oxide design which provides full rated
conductance at gate bias in the 3V to 5V range, thereby
facilitating true on-off power control directly from logic level
(5V) integrated circuits.
Formerly developmental type TA49030.
Ordering InformationS
PART NUMBER
April 1999
File Number
4013.2
Features
• 16A, 30V
• rDS(ON) = 0.025Ω
• Temperature Compensating PSPICE™ Model
• Can be Driven Directly from CMOS, NMOS,
and TTL Circuits
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
PACKAGE
BRAND
DRAIN
RFD16N03L
TO-251AA
16N03L
RFD16N03LSM
TO-252AA
16N03L
NOTE: When ordering, use the entire part number. Add the suffix 9A,
to obtain the TO-252AA variant in tape and reel, e.g. RFD16N03LSM9A.
GATE
SOURCE
Packaging
JEDEC TO-251AA
JEDEC TO-252AA
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
GATE
SOURCE
6-156
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE™ is a trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
RFD16N03L, RFD16N03LSM
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Continuous Drain Current (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
RFD16N03L, RFD16N03LSM
30
30
±10
16
Refer to Peak Current Curve
Figures 6, 16, 17
90
0.606
-55 to 175
UNITS
V
V
V
A
300
260
oC
oC
W
W/oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
LC1. TJ = 25oC to 150oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V (Figure 13)
30
-
-
V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 12)
1
-
2
V
-
-
1
µA
Zero Gate Voltage Drain Current
IDSS
VDS = 30V,
VGS = 0V
Gate to Source Leakage Current
IGSS
VGS = ±10V
Drain to Source On Resistance
rDS(ON)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
TC = 25oC
TC = 150oC
Gate Charge at 5V
Threshold Gate Charge
-
50
µA
-
±100
nA
ID = 16A, VGS = 5V (Figure 11)
-
-
0.025
Ω
VDD = 15V, ID ≈ 16A,
RL = 0.93Ω, VGS = 5V,
RGS = 5Ω
(Figures 18, 19)
-
-
120
ns
-
15
-
ns
-
95
-
ns
td(OFF)
-
25
-
ns
tf
-
27
-
ns
tOFF
Total Gate Charge
-
Qg(TOT)
VGS = 0V to 10V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDD = 24V,
ID = 16A,
RL = 1.5Ω
IG(REF) = 0.6mA
(Figures 15, 20, 21
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 14)
-
-
80
ns
-
50
60
nC
-
30
36
nC
-
1.5
1.8
nC
-
1650
-
pF
-
575
-
pF
-
200
-
pF
Thermal Resistance, Junction to Case
RθJC
Figure 3
-
-
1.65
oC/W
Thermal Resistance, Junction to Ambient
RθJA
TO-251 and TO-252
-
-
100
oC/W
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Diode Reverse Recovery Time
trr
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISD = 16A
-
-
1.5
V
ISD = 16A, dISD/dt = 100A/µs
-
-
75
ns
NOTES:
2. Pulse Test: Pulse Width ≤ 300ms, Duty Cycle ≤ 2%.
3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance curve (Figure 3).
6-157
RFD16N03L, RFD16N03LSM
Typical Performance Curves Unless Otherwise Specified
20
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
15
10
5
0.2
0
0
0
25
50
75
100
125
TC , CASE TEMPERATURE (oC)
175
150
25
FIGURE 1. NORMALIZED POWER DISSIPATION vs
CASE TEMPERATURE
50
75
100
125
TC, CASE TEMPERATURE (oC)
150
175
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
0.5
0.2
0.1
PDM
0.1
0.05
t1
0.02
0.01
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
t1 , RECTANGULAR PULSE DURATION (s)
101
100
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
TC = 25oC
ID, DRAIN CURRENT (A)
TJ = MAX RATED
100
100µs
1ms
10
10ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
VDSS MAX = 30V
100ms
DC
1
10
1
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
6-158
50
IDM, PEAK CURRENT CAPABILITY (A)
500
VGS = 10V
VGS = 5V
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
I
= I25
175 - TC
150
100
TC = 25oC
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-5
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
100
FIGURE 5. PEAK CURRENT CAPABILITY
101
RFD16N03L, RFD16N03LSM
Typical Performance Curves Unless Otherwise Specified (Continued)
100
VGS = 5V
VGS = 10V
100
STARTING TJ = 25oC
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
200
STARTING TJ = 150oC
10
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV=(L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1]
75
VGS = 4.5V
VGS = 4V
50
VGS = 3.5V
25
PULSE DURATION = 250µs, TC = 25oC
VGS = 3V
0
1
0.001
0.01
0.1
1
tAV, TIME IN AVALANCHE (ms)
10
0
100
2.0
3.0
4.0
1.0
VDS, DRAIN TO SOURCE VOLTAGE (V)
5.0
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
100
175oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
-55oC
75
25oC
50
25
75
ID = 16A
ID = 8A
50
ID = 2A
25
TJ = 25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
2.5
0
1.5
3.0
4.5
6.0
VGS, GATE TO SOURCE VOLTAGE (V)
0
7.5
VDD = 15V, IDD = 16A, RL = 0.93Ω
3.5
4.0
5.0
4.5
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
2.0
tr
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
250
3.0
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
200
SWITCHING TIME (ns)
ID = 32A
ON RESISTANCE (mΩ)
100
FIGURE 7. SATURATION CHARACTERISTICS
rDS(ON), DRAIN TO SOURCE
IDS(ON), DRAIN TO SOURCE CURRENT (A)
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
tf
150
td(ON)
100
td(OFF)
50
VGS = 5V, ID = 16A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
1.5
1.0
0.5
0
0
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 10. SWITCHING TIME vs GATE RESISTANCE
6-159
50
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
200
RFD16N03L, RFD16N03LSM
Typical Performance Curves Unless Otherwise Specified (Continued)
2.0
VGS = VDS, ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.5
1.0
0.5
0
-80
-40
1.5
1.0
0.5
0
-80
200
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
ID = 250µA
-40
0
40
80
120
160
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
VDS , DRAIN TO SOURCE VOLTAGE (V)
30
2500
VGS = 0V, f = 1MHz
C, CAPACITANCE (pF)
2000
CISS
1500
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
1000
COSS
500
CRSS
5
VDD = BVDSS
4
18
3
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
12
2
RL = 1.875Ω
IG(REF) = 0.6mA
VGS = 5V
6
20
25
5
10
15
20
VDS, DRAIN TO SOURCE VOLTAGE (V)
VDD = BVDSS
24
0
0
0
200
TJ , JUNCTION TEMPERATURE (oC)
IG(REF)
IG(ACT)
t, TIME (s)
1
80
0
IG(REF)
IG(ACT)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
BVDSS
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
tP
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
0V
tP
IAS
0
0.01Ω
tAV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
6-160
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
VGS , GATE TO SOURCE VOLTAGE (V)
NORMALIZED GATE
THRESHOLD VOLTAGE
2.0
RFD16N03L, RFD16N03LSM
Test Circuits and Waveforms
(Continued)
tON
tOFF
td(ON)
VDS
td(OFF)
tf
tr
VDS
90%
90%
RL
VGS
+
-
DUT
10%
10%
VDD
90%
RGS
VGS
50%
10%
VGS
FIGURE 18. RESISTIVE SWITCHING TEST CIRCUIT
50%
PULSE WIDTH
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
DUT
IG(REF)
VGS = 5V
VGS
-
VGS = 1V
0
Qg(TH)
IG(REF)
0
FIGURE 20. GATE CHARGE TEST CIRCUIT
6-161
FIGURE 21. GATE CHARGE WAVEFORMS
RFD16N03L, RFD16N03LSM
PSPICE Electrical Model
.SUBCKT RFD16N03L 2 1 3;
rev 12/12/94
CA 12 8 2.55e-9
CB 15 14 2.64e-9
CIN 6 8 1.45e-9
LDRAIN
DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD
5
10
5
51
ESG
+
1
9
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
+
+
-
DBODY
21
-
MOS1
6
RIN
S1A
S1B
S2A
S2B
17
18
MOS2
CIN
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 0.14e-3
RGATE 9 20 0.89
RIN 6 8 1e9
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 10.31e-3
RVTO 18 19 RVTOMOD 1
11
EBREAK
16
VTO
-
EVTO
18
20 8
DBREAK
RDRAIN
6
8
IT 8 17 1
GATE LGATE RGATE
ESCL
+
1
1
1
8 1
LDRAIN 2 5 1e-9
LGATE 1 9 3.4e-9
LSOURCE 3 7 3.4e-9
RSCL1
RSCL2
EBREAK 11 7 17 18 33.3
EDS 14 8 5 8
EGS 13 8 6 8
ESG 6 10 6 8
EVTO 20 6 18
2
DRAIN
DPLCAP
8
RSOURCE
LSOURCE
3
SOURCE
7
S1A
12
S2A
13
8
S1B
14
13
13
15
17
RBREAK
S2B
18
RVTO
CB
CA
IT
+
6
EGS
8
-
+
EDS
-
14
5
8
19
-
VBAT
+
VBAT 8 19 DC 1
VTO 21 6 0.583
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/176,6))}
.MODEL DBDMOD D (IS = 3.61e-13 RS = 5.06e-3 TRS1 = 3.05e-3 TRS2 = 7.57e-6 CJO = 2.16e-9 TT = 2.18e-8)
.MODEL DBKMOD D (RS = 1.66e-1 TRS1 = -2.97e-3 TRS2 = 7.57e-6)
.MODEL DPLCAPMOD D (CJO = 0.96e-9 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 2.313 KP = 53.82 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 8.95e-4 TC2 = -1e-7)
.MODEL RDSMOD RES (TC1 = 3.92e-3 TC2 = 1.29e-5)
.MODEL RSCLMOD RES (TC1 = 2.03e-3 TC2 = 0.45e-5)
.MODEL RVTOMOD RES (TC1 = -2.27e-3 TC2 = -5.75e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.82 VOFF= -2.82)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.82 VOFF= -4.82)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.67 VOFF= 2.33)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.33 VOFF= -2.67)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.
6-162
RFD16N03L, RFD16N03LSM
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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6-163
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