X9317
®
Low Noise, Low Power, 100 Taps
Data Sheet
September 9, 2005
Digitally Controlled Potentiometer
(XDCP™)
FN8183.1
Features
• Solid-State Potentiometer
The Intersil X9317 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by a 3-wire interface.
The potentiometer is implemented by a resistor array
composed of 99 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS, U/D, and INC inputs.
The position of the wiper can be stored in nonvolatile
memory and then be recalled upon a subsequent power-up
operation.
The device can be used as a three-terminal potentiometer
for voltage control or as a two-terminal variable resistor for
current control in a wide variety of applications.
• 3-Wire Serial Up/Down Interface
• 100 Wiper Tap Points
- Wiper position stored in nonvolatile memory and
recalled on power-up
• 99 Resistive Elements
- Temperature compensated
- End to end resistance range ±20%
• Low Power CMOS
- VCC = 2.7V to 5.5V, and 5V ±10%
- Standby current < 1µA
• High Reliability
- Endurance, 100,000 data changes per bit
- Register data retention, 100 years
• RTOTAL Values = 1kΩ, 10kΩ, 50kΩ, 100kΩ
• Packages
- 8 Ld SOIC, DIP, TSSOP, and MSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• LCD Bias Control
• DC Bias Adjustment
• Gain and Offset Trim
• Laser Diode Bias Control
• Voltage Regulator Output Control
Pinouts
X9317
(8 LD DIP, 8 LD SOIC, 8 LD MSOP)
TOP VIEW
X9317
(8 LD TSSOP)
TOP VIEW
CS
1
VCC
2
INC
3
U/D
X9317
4
1
8
RL/VL
INC
1
7
RW/VW
U/D
2
6
VSS
RH
3
5
RH/VH
VSS
4
X9317
8
VCC
7
CS
6
RL
5
RW
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas, Inc. Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9317
Ordering Information
PART NUMBER
PART MARKING
X9317ZM8*
VCC LIMITS (V)
RTOTAL (kΩ)
TEMPERATURE
RANGE (°C)
5 ±10%
1
0 to 70
8 Ld MSOP
8 Ld MSOP (Pb-free)
PACKAGE
X9317ZM8Z* (Note)
DDA
0 to 70
X9317ZM8I*
AFI
-40 to 85
8 Ld MSOP
X9317ZM8IZ* (Note)
DCY
-40 to 85
8 Ld MSOP (Pb-free)
X9317ZP
X9317ZS8*
X9317ZS8Z* (Note)
X9317ZS8I*
X9317ZS8IZ* (Note)
X9317ZV8*
X9317ZV8Z* (Note)
X9317ZV8I*
X9317ZV8IZ* (Note)
X9317ZP
0 to 70
8 Ld PDIP
X9317Z
0 to 70
8 Ld SOIC
X9317Z Z
0 to 70
8 Ld SOIC (Pb-free)
X9317Z I
-40 to 85
8 Ld SOIC
X9317Z Z I
-40 to 85
8 Ld SOIC (Pb-free)
9317Z
0 to 70
8 Ld TSSOP
9317Z Z
0 to 70
8 Ld TSSOP (Pb-free)
317ZI
-40 to 85
8 Ld TSSOP
-40 to 85
8 Ld TSSOP (Pb-free)
9317ZI Z
X9317WM8*
ABF
X9317WM8Z* (Note)
DCW
10
0 to 70
8 Ld MSOP
0 to 70
8 Ld MSOP (Pb-free)
X9317WM8I*
ADS
-40 to 85
8 Ld MSOP
X9317WM8IZ* (Note)
DCT
-40 to 85
8 Ld MSOP (Pb-free)
X9317WP
X9317WP
0 to 70
8 Ld PDIP
X9317WPI
X9317WP I
-40 to 85
8 Ld PDIP
X9317W
0 to 70
8 Ld SOIC
8 Ld SOIC (Pb-free)
X9317WS8*
X9317WS8Z* (Note)
X9317W Z
0 to 70
X9317WS8I*
X9317W I
-40 to 85
8 Ld SOIC
X9317W Z I
-40 to 85
8 Ld SOIC (Pb-free)
X9317WS8IZ* (Note)
X9317WV8*
X9317WV8Z* (Note)
X9317WV8I*
X9317WV8IZ* (Note)
9317W
0 to 70
8 Ld TSSOP
9317W Z
0 to 70
8 Ld TSSOP (Pb-free)
317WI
-40 to 85
8 Ld TSSOP
9317WI Z
-40 to 85
8 Ld TSSOP (Pb-free)
X9317UM8*
AEC
X9317UM8Z* (Note)
X9317UM8I*
X9317UM8IZ* (Note)
50
0 to 70
8 Ld MSOP
DCS
0 to 70
8 Ld MSOP (Pb-free)
AFE
-40 to 85
8 Ld MSOP
DCR
-40 to 85
8 Ld MSOP (Pb-free)
X9317UP
X9317UP
0 to 70
8 Ld PDIP
X9317UPI
X9317UP I
-40 to 85
8 Ld PDIP
0 to 70
8 Ld SOIC
X9317U
0 to 70
8 Ld SOIC
X9317U Z
0 to 70
8 Ld SOIC (Pb-free)
X9317US
X9317US8*
X9317US8Z* (Note)
X9317US8I*
X9317US8IZ* (Note)
X9317UV8*
X9317UV8Z* (Note)
X9317UV8I*
X9317UV8IZ* (Note)
2
X9317U I
-40 to 85
8 Ld SOIC
X9317U Z I
-40 to 85
8 Ld SOIC (Pb-free)
9317U
0 to 70
8 Ld TSSOP
9317U Z
0 to 70
317UI
-40 to 85
8 Ld TSSOP
8 Ld TSSOP (Pb-free)
9317UI Z
-40 to 85
8 Ld TSSOP (Pb-free)
FN8183.1
September 9, 2005
X9317
Ordering Information (Continued)
PART NUMBER
PART MARKING
VCC LIMITS (V)
RTOTAL (kΩ)
100
TEMPERATURE
RANGE (°C)
PACKAGE
X9317TM8*
AGD
0 to 70
8 Ld MSOP
X9317TM8Z* (Note)
DCN
0 to 70
8 Ld MSOP (Pb-free)
X9317TM8I*
AGF
-40 to 85
X9317TM8IZ* (Note)
DCL
-40 to 85
X9317TP
8 Ld MSOP
8 Ld MSOP (Pb-free)
0 to 70
8 Ld PDIP
X9317TPI
X9317TP I
-40 to 85
8 Ld PDIP
X9317TS8
X9317T
0 to 70
8 Ld SOIC
X9317T Z
0 to 70
8 Ld SOIC (Pb-free)
X9317T I
-40 to 85
8 Ld SOIC
X9317T Z I
-40 to 85
8 Ld SOIC (Pb-free)
X9317TS8Z (Note)
X9317TS8I
X9317TS8IZ (Note)
X9317TV8*
X9317TV8Z* (Note)
9317T Z
X9317TV8I*
X9317TV8IZ* (Note)
9317TI Z
X9317ZM8-2.7*
AFH
X9317ZM8Z-2.7* (Note)
AOA
2.7-5.5
1
0 to 70
8 Ld TSSOP
0 to 70
8 Ld TSSOP (Pb-free)
-40 to 85
8 Ld TSSOP
-40 to 85
8 Ld TSSOP (Pb-free)
0 to 70
8 Ld MSOP
0 to 70
8 Ld MSOP (Pb-free)
X9317ZM8I-2.7*
AFJ
-40 to 85
8 Ld MSOP
X9317ZM8IZ-2.7* (Note)
DCZ
-40 to 85
8 Ld MSOP (Pb-free)
X9317Z F
0 to 70
8 Ld SOIC
X9317Z Z F
0 to 70
8 Ld SOIC (Pb-free)
X9317Z G
-40 to 85
X9317Z Z G
-40 to 85
317ZF
0 to 70
8 Ld TSSOP
9317ZF Z
0 to 70
8 Ld TSSOP (Pb-free)
317ZG
-40 to 85
8 Ld TSSOP
317ZG Z
-40 to 85
8 Ld TSSOP (Pb-free)
X9317ZS8-2.7*
X9317ZS8Z-2.7* (Note)
X9317ZS8I-2.7*
X9317ZS8IZ-2.7* (Note)
X9317ZV8-2.7*
X9317ZV8Z-2.7* (Note)
X9317ZV8I-2.7*
X9317ZV8IZ-2.7* (Note)
X9317WM8-2.7*
ACZ
X9317WM8Z-2.7* (Note)
X9317WM8I-2.7*
10
8 Ld SOIC
8 Ld SOIC (Pb-free)
0 to 70
8 Ld MSOP
DCX
0 to 70
8 Ld MSOP (Pb-free)
ADT
-40 to 85
8 Ld MSOP
X9317WP-2.7
X9317WP F
0 to 70
8 Ld PDIP
X9317WPI-2.7
X9317WP G
-40 to 85
8 Ld PDIP
X9317W F
0 to 70
8 Ld SOIC
X9317W Z F
0 to 70
8 Ld SOIC (Pb-free)
X9317W G
-40 to 85
8 Ld SOIC
X9317W Z G
-40 to 85
8 Ld SOIC (Pb-free)
X9317WS8-2.7*
X9317WS8Z-2.7* (Note)
X9317WS8I-2.7*
X9317WS8IZ-2.7* (Note)
X9317WV8-2.7*
X9317WV8Z-2.7* (Note)
X9317WV8I-2.7*
X9317WV8IZ-2.7* (Note)
3
317WF
0 to 70
8 Ld TSSOP
9317WF Z
0 to 70
8 Ld TSSOP (Pb-free)
317WG
-40 to 85
8 Ld TSSOP
AKZ
-40 to 85
8 Ld TSSOP (Pb-free)
FN8183.1
September 9, 2005
X9317
Ordering Information (Continued)
PART NUMBER
PART MARKING
VCC LIMITS (V)
RTOTAL (kΩ)
PACKAGE
X9317UM8-2.7*
AED
0 to 70
8 Ld MSOP
X9317UM8Z-2.7* (Note)
AOB
0 to 70
8 Ld MSOP (Pb-free)
X9317UM8I-2.7*
AFF
-40 to 85
X9317UM8IZ-2.7* (Note)
50
TEMPERATURE
RANGE (°C)
8 Ld MSOP
AOH
-40 to 85
X9317UP-2.7
X9317UP F
0 to 70
8 Ld PDIP
X9317UPI-2.7
X9317UP G
-40 to 85
8 Ld PDIP
X9317U F
0 to 70
8 Ld SOIC
X9317U Z F
0 to 70
8 Ld SOIC (Pb-free)
X9317US8-2.7*
X9317US8Z-2.7* (Note)
X9317US8I-2.7*
X9317US8IZ-2.7* (Note)
X9317UV8-2.7*
X9317UV8Z-2.7* (Note)
X9317UV8I-2.7*
X9317UV8IZ-2.7* (Note)
8 Ld MSOP (Pb-free)
X9317U G
-40 to 85
8 Ld SOIC
X9317U Z G
-40 to 85
8 Ld SOIC (Pb-free)
9317UF
0 to 70
8 Ld TSSOP
9317UF Z
0 to 70
9317UG
-40 to 85
8 Ld TSSOP
-40 to 85
8 Ld TSSOP (Pb-free)
9317UG Z
X9317TM8-2.7*
AGE
X9317TM8Z-2.7* (Note)
DCP
100
8 Ld TSSOP (Pb-free)
0 to 70
8 Ld MSOP
0 to 70
8 Ld MSOP (Pb-free)
X9317TM8I-2.7*
AGG
-40 to 85
8 Ld MSOP
X9317TM8IZ-2.7* (Note)
DCM
-40 to 85
8 Ld MSOP (Pb-free)
X9317TP-2.7
X9317TPI-2.7
0 to 70
8 Ld PDIP
-40 to 85
8 Ld PDIP
0 to 70
8 Ld SOIC
X9317T Z F
0 to 70
8 Ld SOIC (Pb-free)
X9317T G
-40 to 85
8 Ld SOIC
X9317T Z G
-40 to 85
8 Ld SOIC (Pb-free)
0 to 70
8 Ld TSSOP
9317TF Z
0 to 70
8 Ld TSSOP (Pb-free)
317TG
-40 to 85
8 Ld TSSOP
9317TG Z
-40 to 85
8 Ld TSSOP (Pb-free)
X9317TP G
X9317TS8-2.7*
X9317TS8Z-2.7* (Note)
X9317TS8I-2.7*
X9317TS8IZ-2.7* (Note)
X9317TV8-2.7*
X9317TV8Z-2.7* (Note)
X9317TV8I-2.7*
X9317TV8IZ-2.7* (Note)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Add "T1" suffix for tape and reel.
4
FN8183.1
September 9, 2005
X9317
Block Diagram
U/D
INC
CS
VCC (Supply Voltage)
Up/Down
Counter
98
97
RH
Up/Down
(U/D)
Control
and
Memory
Increment
(INC)
7-Bit
Nonvolatile
Memory
RW
Device Select
(CS)
RH
99
96
One
of
One
Hundred
Decoder
Wiper
Switches
Resistor
Array
RL
2
VSS (Ground)
General
VCC
VSS
Store and
Recall
Control
Circuitry
1
0
RL
RW
Detailed
Pin Descriptions
DIP/SOIC
SYMBOL
BRIEF DESCRIPTION
1
INC
Increment. Toggling INC while CS is low moves the wiper either up or down.
2
U/D
Up/Down. The U/D input controls the direction of the wiper movement.
3
RH
The high terminal is equivalent to one of the fixed terminals of a mechanical potentiometer.
4
VSS
Ground.
5
RW
The wiper terminal is equivalent to the movable terminal of a mechanical potentiometer.
6
RL
The low terminal is equivalent to one of the fixed terminals of a mechanical potentiometer.
7
CS
Chip Select. The device is selected when the CS input is LOW, and de-selected when CS is high.
8
VCC
Supply Voltage.
5
FN8183.1
September 9, 2005
X9317
Absolute Maximum Ratings
Junction Temperature Under Bias . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on CS, INC, U/D and VCC
with Respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
RH, RW, RL to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6V
Lead Temperature (soldering 10s). . . . . . . . . . . . . . . . . . . . . . 300°C
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±8.8mA
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation
of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Potentiometer Specifications VCC = Full Range, TA = Full Operating Temperature Range unless otherwise stated
SYMBOL
PARAMETER
TEST CONDITIONS/NOTES
MIN
TYP
(Note 4)
MAX
UNIT
RTOTAL
End to end resistance tolerance
See ordering information for values
-20
+20
%
VRH/RL
RH/RL terminal voltage
VSS = 0V
VSS
VCC
V
Power rating
RTOTAL ≥ 10kΩ
10
mW
RTOTAL = 1kΩ
25
mW
RW
IW
Wiper resistance
IW = 1mA, VCC = 5V
200
400
Ω
IW = 1mA, VCC = 2.7V
400
1000
Ω
+4.4
mA
Wiper current (Note 5)
See test circuit
Noise (Note 7)
Ref: 1kHz
-4.4
Resolution
Absolute linearity (Note 1)
V(RH) = VCC,
V(RL) = 0V
Relative linearity (Note 2)
%
+1
MI
(Note 3)
-0.2
+0.2
MI
(Note 3)
-20
ppm/°C
+20
10/10/25
ppm/°C
Potentiometer capacitances
See equivalent circuit
Supply Voltage
X9317
4.5
5.5
V
X9317-2.7
2.7
5.5
V
MAX
UNIT
DC Electrical Specifications
SYMBOL
1
±300
Ratiometric temperature coefficient
(Notes 5, 6)
VCC
dBV
-1
RTOTAL temperature coefficient (Note 5)
CH/CL/CW
(Note 5)
-120
pF
VCC = 5V ±10%, TA = Full Operating Temperature Range unless otherwise stated
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 4)
ICC1
VCC active current (Increment)
CS = VIL, U/D = VIL or VIH and INC =
VIL/VIH @ min. tCYC
RL, RH, RW not connected
50
µA
ICC2
VCC active current (Store)
(non-volatile write)
CS = VIH, U/D = VIL or VIH and INC = VIL
or VIH. RL, RH, RW not connected
400
µA
ISB
Standby supply current
CS ≥ VIH, U/D and INC = VIL
RL, RH, RW not connected
1
µA
ILI
CS, INC, U/D input leakage current
VIN = VSS to VCC
-10
+10
µA
VIH
CS, INC, U/D input HIGH voltage
VCC x
0.7
VCC +
0.5
V
VIL
CS, INC, U/D input LOW voltage
-0.5
VCC x
0.1
V
6
FN8183.1
September 9, 2005
X9317
DC Electrical Specifications
SYMBOL
VCC = 5V ±10%, TA = Full Operating Temperature Range unless otherwise stated (Continued)
PARAMETER
CIN (Note 5)
CS, INC, U/D input capacitance
TEST CONDITIONS
TYP
(Note 4)
MIN
MAX
UNIT
10
pF
VCC = 5V, VIN = VSS, TA = 25°C,
f = 1MHz
Endurance and Data Retention VCC = 5V ±10%, TA = Full Operating Temperature Range
PARAMETER
MIN
UNIT
Minimum endurance
100,000
Data changes per bit
Data retention
100
Years
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(RW(n)(actual))-V(RW(n)(expected))]/MI
V(RW(n)(expected)) = n(V(RH)-V(RL))/99 + V(RL), with n from 0 to 99.
2. Relative linearity is a measure of the error in step size between taps = [V(RW(n+1))-(V(RW(n)) - MI)]/MI.
3. 1 Ml = Minimum Increment = [V(RH)-V(RL)]/99.
4. Typical values are for TA = 25°C and nominal supply voltage.
5. This parameter is not 100% tested.
6. Ratiometric temperature coefficient = (V(RW)T1(n)-V(RW)T2(n))/[V(RW)T1(n)(T1-T2) x 106], with T1 & T2 being 2 temperatures, and n from 0 to 99.
7. Measured with wiper at tap position 99, RL grounded, using test circuit.
Test Circuit
Equivalent Circuit
RTOTAL
Test Point
RH
CH
RW
Force
Current
CL
CW
RL
10pF
25pF
10pF
RW
AC Conditions of Test
AC Electrical Specifications
SYMBOL
tCl
Input pulse levels
0V to 3V
Input rise and fall times
10ns
Input reference levels
1.5V
VCC = 5V ±10%, TA = Full Operating Temperature Range unless otherwise stated
PARAMETER
MIN
TYP (Note 4)
MAX
UNIT
CS to INC setup
50
ns
tlD (Note 5)
INC HIGH to U/D change
100
ns
tDI (Note 5)
U/D to INC setup
1
µs
tlL
INC LOW period
960
ns
tlH
INC HIGH period
960
ns
tlC
INC inactive to CS inactive
1
µs
tCPHS
CS deselect time (STORE)
10
ms
CS deselect time (NO STORE)
100
ns
tCPHNS
(Note 5)
tIW
INC to RW change
1
7
5
µs
FN8183.1
September 9, 2005
X9317
AC Electrical Specifications
SYMBOL
tCYC
tR , tF
(Note 5)
VCC = 5V ±10%, TA = Full Operating Temperature Range unless otherwise stated (Continued)
PARAMETER
MIN
INC cycle time
TYP (Note 4)
tWR
UNIT
2
µs
INC input rise and fall time
tPU (Note 5) Power up to wiper stable
tR VCC
(Note 5)
MAX
VCC power-up rate
0.2
Store Cycle
5
Power Up and Down Requirements
The recommended power up sequence is to apply VCC/VSS
first, then the potentiometer voltages. During power-up, the
data sheet parameters for the DCP do not fully apply until 1
millisecond after VCC reaches its final value. The VCC ramp
500
µs
5
µs
50
V/ms
10
ms
spec is always in effect. In order to prevent unwanted tap
position changes, or an inadvertent store, bring the CS and
INC high before or concurrently with the VCC pin on
powerup.
AC Timing
CS
tCYC
tCI
tIL
tIH
tCPHNS
tCPHS
tIC
90%
90%
10%
INC
tID
tDI
tF
tR
U/D
tIW
MI
RW
(3)
Typical Performance Characteristics
0
-50
PPM
-100
-150
-200
-250
-300
-350
-55 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105115125
TEMPERATURE (°C)
FIGURE 1. TYPICAL TOTAL RESISTANCE TEMPERATURE
COEFFICIENT
8
FN8183.1
September 9, 2005
X9317
Pin Descriptions
Pin Names
RH and RL
SYMBOL
The high (RH) and low (RL) terminals of the X9317 are
equivalent to the fixed terminals of a mechanical
potentiometer. The terminology of RL and RH references the
relative position of the terminal in relation to wiper movement
direction selected by the U/D input and not the voltage
potential on the terminal.
RW
Rw is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the control inputs.
The wiper terminal series resistance is typically 200Ω.
Up/Down (U/D)
The U/D input controls the direction of the wiper movement
and whether the counter is incremented or decremented.
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the
counter in the direction indicated by the logic level on the
U/D input.
Chip Select (CS)
The device is selected when the CS input is LOW. The
current counter value is stored in nonvolatile memory when
CS is returned HIGH while the INC input is also HIGH. After
the store operation is complete the X9317 will be placed in
the low power standby mode until the device is selected
once again.
Pin Configuration
DIP/SOIC/MSOP
8
VCC
7
CS
3
6
RL
4
5
RW
INC
1
U/D
2
RH
VSS
X9317
TSSOP
RL/VL
7
RW/VW
3
6
VSS
4
5
RH/VH
1
VCC
2
INC
U/D
X9317
RH
High terminal
RW
Wiper terminal
RL
Low terminal
VSS
Ground
VCC
Supply voltage
U/D
Up/Down control input
INC
Increment control input
CS
Chip select control input
Principles of Operation
There are three sections of the X9317: the control section,
the nonvolatile memory, and the resistor array. The control
section operates just like an up/down counter. The output of
this counter is decoded to turn on a single electronic switch
connecting a point on the resistor array to the wiper output.
The contents of the counter can be stored in nonvolatile
memory and retained for future use. The resistor array is
comprised of 99 individual resistors connected in series.
Electronic switches at either end of the array and between
each resistor provide an electrical connection to the wiper
pin, RW.
The wiper acts like its mechanical equivalent and does not
move beyond the first or last position. That is, the counter
does not wrap around when clocked to either extreme.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions. If
the wiper is moved several positions, multiple taps are
connected to the wiper for tIW (INC to VW change). The
RTOTAL value for the device can temporarily be reduced by
a significant amount if the wiper is moved several positions.
When the device is powered-down, the last wiper position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled
and the wiper is set to the value last stored.
Instructions and Programming
8
CS
DESCRIPTION
The INC, U/D and CS inputs control the movement of the
wiper along the resistor array. With CS set LOW the device
is selected and enabled to respond to the U/D and INC
inputs. HIGH to LOW transitions on INC will increment or
decrement (depending on the state of the U/D input) a seven
bit counter. The output of this counter is decoded to select
one of one hundred wiper positions along the resistive array.
The value of the counter is stored in nonvolatile memory
whenever CS transitions HIGH while the INC input is also
HIGH.
9
FN8183.1
September 9, 2005
X9317
The system may select the X9317, move the wiper and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
performed as described above and once the new position is
reached, the system must keep INC LOW while taking CS
HIGH. The new wiper position will be maintained until
changed by the system or until a powerup/down cycle
recalled the previously stored data.
This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during
system operation minor adjustments could be made. The
adjustments might be based on user preference, system
parameter changes due to temperature drift, etc.
The state of U/D may be changed while CS remains LOW.
This allows the host system to enable the device and then
move the wiper up and down until the proper trim is attained.
Mode Selection
CS
INC
U/D
MODE
L
H
Wiper up
L
L
Wiper down
H
X
Store wiper position to nonvolatile
memory
X
X
Standby
L
X
No store, return to standby
L
H
Wiper Up (not recommended)
L
L
Wiper Down (not recommended)
H
10
FN8183.1
September 9, 2005
X9317
Applications Information
computer-based digital controls, and (3) the retentivity of
nonvolatile memory used for the storage of multiple
potentiometer settings or data.
Electronic digitally controlled (XDCP) potentiometers provide
three powerful application advantages; (1) the variability and
reliability of a solid-state potentiometer, (2) the flexibility of
Basic Configurations of Electronic Potentiometers
VREF
VREF
RH
RW
RL
I
Three terminal potentiometer;
variable voltage divider
Two terminal variable resistor;
variable current
Basic Circuits
Buffered Reference Voltage
Single Supply Inverting Amplifier
Cascading Techniques
R1
+V
+V
+V
R1
+5V
RW
+
VREF
VS
LMC7101
VOUT
-
+5V
R2
X
RW
100K
+V
VO
+
+5V
LMC7101
(a)
Voltage Regulator
VIN
100K
RW
VOUT = VW/RW
(b)
VO = (R2/R1)VS
Offset Voltage Adjustment
VO (REG)
317
R1
Comparator with Hysteresis
R2
LT311A
VS
VS
R1
-
+5V
100kΩ
VO
+
+
Iadj
10kΩ
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
10kΩ
}
LMC7101
10kΩ
}
R2
VO
R1
R2
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
+5V
(for additional circuits see AN115)
11
FN8183.1
September 9, 2005
X9317
Packaging Information
8-Lead Plastic Dual In-Line (DIP) Package Type P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
Pin 1 Index
Pin 1
0.300
(7.62) Ref.
Half Shoulder Width On
All End Pins Optional
0.145 (3.68)
0.128 (3.25)
Seating
Plane
0.025 (0.64)
0.015 (0.38)
0.065 (1.65)
0.045 (1.14)
0.150 (3.81)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
.073 (1.84)
Max.
Typ. 0.010 (0.25)
0.060 (1.52)
0.020 (0.51)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
0°
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
12
FN8183.1
September 9, 2005
X9317
Packaging Information
8-Lead Plastic Small Outline Gull Wing Package Type S (SOIC)
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
X 45°
0.020 (0.50)
0.050"Typical
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
FOOTPRINT
0.030"
Typical
8 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
13
FN8183.1
September 9, 2005
X9317
Packaging Information
8-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.114 (2.9)
.122 (3.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
(4.16) (7.72)
Detail A (20X)
(1.78)
.031 (.80)
.041 (1.05)
(0.42)
(0.65)
All Measurements Are Typical
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
14
FN8183.1
September 9, 2005
X9317
Packaging Information
M Package
8-Lead Miniature Small Outline Gull Wing Package Type MSOP
0.118 ± 0.002
(3.00 ± 0.05)
0.012 + 0.006 / -0.002
(0.30 + 0.15 / -0.05)
0.0256 (0.65) Typ.
R 0.014 (0.36)
0.118 ± 0.002
(3.00 ± 0.05)
0.030 (0.76)
0.0216 (0.55)
0.036 (0.91)
0.032 (0.81)
0.040 ± 0.002
(1.02 ± 0.05)
7° Typ.
0.008 (0.20)
0.004 (0.10)
0.0256" Typical
0.150 (3.81)
Ref.
0.193 (4.90)
Ref.
0.007 (0.18)
0.005 (0.13)
0.025"
Typical
0.220"
FOOTPRINT
0.020"
Typical
8 Places
NOTE:
1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
15
FN8183.1
September 9, 2005