UNISONIC TECHNOLOGIES CO., LTD LXXLD50 CMOS IC 0.8V REFERENCE ULTRA LOW DROPOUT LINEAR REGULATOR DESCRIPTION The UTC LXXLD50 is a 5A ultra low dropout linear regulator providing designers with well supply voltage for applications of NB and front-side-bus termination on motherboards. HSOP-8 A control voltage for the circuitry and a main supply voltage for power conversion are needed as supply voltages to reduce power dissipation and provide extremely low dropout. The UTC LXXLD50 contains some function circuits. A Power-OnReset (POR) circuit monitors both supply voltages to prevent undesired operations. A thermal shutdown and current limit circuits prevent this device from being damaged due to thermal and current over-loads. A POK indicates the output status with a pre-set time delay. It can control other converter for power sequence. The UTC LXXLD50 can be enabled by other power system. Pulling and holding the EN pin below 0.3V shuts off the output. The UTC LXXLD50 is ideal for applications,such as front side bus VTT (1.2V/5A), note book PC applications, and motherboard applications. FEATURES * Low Dropout VD=0.2V(Typ.)@ IOUT=5A * Low ESR Output Capacitor * VREF=0.8V * High Output Accuracy : ±1.5% Over Line, Load and Temperature * Fast Transient Response * 1.2V, 1.5V, 1.8V, 2.5V Output Options by Connecting ADJ to GND and Output Voltage can be Adjusted by External Resistors * Power-On-Reset Monitoring both Supply Voltages ( VCNTL and VIN Pins) * Protection function: Internal Soft-Start Current-Limit Protection Under-Voltage Protection Thermal Shutdown with Hysteresis Over-Voltage Protection * Power-OK Output with a Delay Time * Shutdown for Standby or Suspend Mode * Lead Free Available (RoHS Compliant) ORDERING INFORMATION Ordering Number LXXLD50G-SH2-R Note: XX: Output Voltage, refer to Marking Information. www.unisonic.com.tw Copyright © 2016 Unisonic Technologies Co., Ltd Package HSOP-8 Packing Tape Reel 1 of 11 QW-R502-474.D LXXLD50 CMOS IC MARKING INFORMATION PACKAGE VOLTAGE CODE HSOP-8 25 : 2.5V AD: ADJ PIN CONFIGURATION PIN DESCRIPTION PIN NO. 1 PIN NAME GND 2 ADJ 3 VOUT 4 VOUT 5 VIN 6 VCNTL 7 POK 8 EN MARKING DESCRIPTION Ground pin of the circuitry. All voltage levels are measured with respect to this pin. This pin, when grounded, sets the output voltage by the internal feedback resistors; If external feedback resistors are used, the output voltage will be VOUT=0.8· (1+R1/R2) (V) where R1 is connected from VOUT to ADJ with Kelvin sensing and R2 is connected from ADJ to GND. A bypass capacitor may be connected with R1in parallel to improve load transient response. The recommended R2 and R1 are in the range of 100~10kΩ. Output of the regulator. Please connect Pin 3 and 4 together using wide tracks. It is necessary to connect a output capacitor with this pin for closed-loop compensation and improving transient responses. Main supply input pins for power conversions. The Exposed Pad provide a very low impedance input path for the main supply voltage. Please tie the Exposed Pad and VIN Pin (Pin 8) together to reduce the dropout voltage. The voltage at this pins is monitored for Power-On Reset purpose. Power input pin of the control circuitry. Connecting this pin to a +5V (recommended) supply voltage provides the bias for the control circuitry. The voltage at this pin is monitored for Power-On Reset purpose. Power-OK signal output pin. This pin is an open-drain output used to indicate status of output voltage by sensing FB voltage. This pin is pulled low when the rising FB voltage is not above the VPOK threshold or the falling FB voltage is below the VPNOK threshold, indicating the output is not OK. Enable control pin. Pulling and holding this pin below 0.3V shuts down the output. When re-enabled, the IC undergoes a new soft-start cycle . Left this pin open, an internal current source 10mA pulls this pin up to VCNTL voltage, enabling the regulator. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 2 of 11 QW-R502-474.D LXXLD50 CMOS IC BLOCK DIAGRAM EN OV + 1V VCNTL Soft-Start and Control Logic UV + 0.4V ADJ 0.2V PowerOn-Reset Thermal Limit Current Limit VOUT + EA FB - 0.8V REF VIN RFB1 Sense select + - + POK - Delay RFB2 GND 90% VREF POK UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 3 of 11 QW-R502-474.D LXXLD50 CMOS IC ABSOLUTE MAXIMUM RATING PARAMETER SYMBOL RATINGS UNIT VCNTL Supply Voltage (VCNTL to GND) VCNTL -0.3 ~ 7 V VIN Supply Voltage (VIN to GND) VIN -0.3 ~ 3.3 V EN and FB to GND VI/O -0.3 ~ VCNTL+0.3 V POK to GND VPOK -0.3 ~ 7 V Average Power Dissipation PD 3 W Peak Power Dissipation (<20mS) PPEAK 20 W Junction Temperature TJ 150 °C Storage Temperature TSTG -65 ~ 150 °C Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. THERMAL CHARACTERISTICS PARAMETER SYMBOL RATINGS UNIT Junction to Ambient θJA 40 °C/W Note: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of SOP-8-P is soldered directly on the PCB. RECOMMENDED OPERATING CONDITIONS PARAMETER VCNTL Supply Voltage VIN Supply Voltage VCNTL=3.3±5% Output Voltage VCNTL=5.0±5% VOUT Output Current Operating Junction Temperature SYMBOL VCNTL VIN VOUT IOUT TJ UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw RATINGS 3.1 ~ 6 1.1 ~ 3.3 0.8 ~ 1.2 +0.8 ~ VIN-0.2 0~5 -25 ~ 125 UNIT V V V V A °С 4 of 11 QW-R502-474.D LXXLD50 CMOS IC ELECTRICAL CHARACTERISTICS (Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.5V, VOUT = 1.2V or VIN = 1.8V, VOUT = 1.5V or VIN = 2.1V, VOUT = 1.8V or VIN = 2.8V, VOUT = 2.5V and TA = 0 ~ 70°C, unless otherwise specified. Typical values refer to TA = 25°C.) PARAMETER SUPPLY CURRENT VCNTL Supply Current VCNTL Shutdown Current POWER-ON-RESET VCNTL POR Threshold VCNTL POR Hysteresis VIN POR Threshold VIN POR Hysteresis OUTPUT VOLTAGE Reference Voltage Output Voltage Accuracy Line Regulation Load Regulation DROPOUT VOLTAGE SYMBOL ICNTL ISD VREF TEST CONDITIONS MIN TYP MAX UNIT EN = VCNTL, EN = GND 0.4 1 200 8 380 mA μA VCNTL Rising 2.7 3.1 V V VIN Rising 0.8 2.9 0.4 0.9 0.5 ADJ =VOUT IOUT=0A ~ 5A, TJ= -25 ~125°C VCNTL=3.3 ~ 5.5V IOUT=0A ~ 5A V 0.8 +1.5 0.3 0.15 V % % % 0.2 0.25 0.3 V V 8 9 6.7 8.8 A A A A °C °C V % -1.5 0.06 0.06 IOUT = 5A, VCNTL=5V, TJ= 25°C IOUT = 5A, VCNTL=5V, TJ= -50~125°C Dropout Voltage 1.0 PROTECTION Current Limit ILIMIT Thermal Shutdown Temperature TSD Thermal Shutdown Hysteresis Under-Voltage Threshold Over-Voltage Threshold VOVP/Vnormal ENABLE AND SOFT-START EN Logic High Threshold Voltage EN Hysteresis EN Pin Pull-Up Current Soft-Start Interval TSS POWER OK AND DELAY POK Threshold Voltage for Power OK VPOK POK Threshold Voltage for Power Not VPNOK OK POK Low Voltage POK Delay Time TDELAY ADJ Adjust Pin threshold VCNTL=5V, TJ= 25°C VCNTL=5V, TJ= -25 ~ 125°C VCNTL=3.3V, TJ= 25°C VCNTL=3.3V, TJ= -25 ~ 125°C TJ Rising 150 25 0.4 125 ADJ Falling Output Voltage up regulation voltage VEN Rising 0.3 0.4 30 10 1.2 0.5 V mV μA ms VADJ Rising 90% 92% 94% VREF VADJ Falling 79% 81% 83% VREF 1 0.2 1.5 0.4 10 V mS 0.1 0.2 0.4 V EN=GND POK sinks 5mA UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 7 6 6.3 6 5 of 11 QW-R502-474.D LXXLD50 CMOS IC FUNCTIONAL DESCRIPTION Power-On-Reset A POR (Power-On-Reset) circuit is designed to monitor the two supply voltages at VCNTL pin and VIN pin to avoid the unexpected operations. During powering on process, the POR circuit would initiate a soft-start process after the two supply voltages above their rising POR threshold voltages. The POR function also pulls low the POK pin regardless the output voltage when the voltage at VCNTL pin drops below its falling POR threshold. Internal Soft-Start The built-in soft-start circuit controls rise rate of the output voltage to limit the current surge at start-up. The soft-start interval is approximately 1.2mS (TYP.). Output Voltage Regulation The error amplifier compares a temperature-compensated 0.8V reference with the feedback voltage, which is characterized with high bandwidth and DC gain to provide fast transient response and less load regulation. The output voltage can be adjusted by an output NMOS to get the preset voltage. The difference which is amplified by the error amplifier provides load current from VIN pin to VOUT pin. Current-Limit The current-limit protection circuit is used to protect this device against the maximum current, which occurs in overload or short-circuit conditions. For the UTC LXXLD50, the current is monitored through the output NMOS. Under-Voltage Protection (UVP) The UTC LXXLD50 monitors the voltage on internal feed back signal after soft-start process is finished. Thus, the Under-Voltage circuit is inactive during soft-start. When the voltage on FB signal goes below the under-voltage threshold, the UVP circuit shuts off the output immediately. Last for a period, this device starts a new soft-start to regulate output. Over-Voltage Protection (OVP) The UTC LXXLD50 monitors the output voltage. When the voltage on VOUT pin goes high beyond normal regulation voltage by 25%, the OVP circuit shuts off the output immediately. After a while, the LXXLD50 starts a new soft-start to regulate output. Thermal Shutdown The thermal shutdown protection circuit is designed to prevent the junction temperature beyond a certain value. If the junction temperature becomes higher than +150°C, the output NMOS is turned off through a thermal sensor, allowing the device to cool down. The regulator regulates the output again through initiation of a new soft-start cycle after the junction temperature cools by 25°C, resulting in a pulsed output during continuous thermal overload conditions. The average junction temperature is reduced by the 25°C hysteresis during continuous thermal overload conditions, making this device use longer. Also, the power dissipation should be externally limited to ensure junction temperature under +125°C during normal operation. Enable Control If the EN pin is applied to a logic low signal (VEN< 0.3V), the output would be shut down. Following a shutdown, a logic high signal re-enables the output through initiation of a new soft-start cycle. Left open, this pin is pulled up by an internal current source (10μA Typical) to enable operation. For a low cost-effectiveness, an external transistor is not required. Power-OK and Delay For the UTC LXXLD50, the Power-OK circuit indicates the status of the output voltage by monitoring the internal feedback voltage (VFB). When the feedback voltage becomes equal to the rising Power-OK threshold (VPOK), an internal delay function starts to perform a delay time. At the end of the delay time, the IC shuts off the internal NMOS of the POK to indicate the output is OK. When the feedback voltage becomes equal to the falling Power-OK threshold (VPNOK), the IC immediately turns on the NMOS of the POK to indicate the output is not OK without a delay time. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 6 of 11 QW-R502-474.D LXXLD50 CMOS IC APPLICATION INFORMATION Power Sequencing Less consideration could be taken into the power sequencing of VIN and VCNTL. But do not apply a voltage to VOUT for a long time when the main voltage applied at VIN is not present. The reason is the internal parasitic diode from VOUT to VIN conducts and dissipates power without protections due to the forward-voltage. Output Capacitor For the maximum device performance and improving system stability, transient response over temperature and current, a well-suitable output capacitor is needed. The selected output capacitor should be qualified perfect ESR (equivalent series resistance) and capacitor value for a better system stability and load transient. The UTC LXXLD50 is designed with a programmable feedback compensation adjusted by an external feedback network for the use of wide ranges of ESR and capacitance in all applications. The output capacitors can be ultra-low-ESR capacitors, such as ceramic chip capacitors; low-ESR bulk capacitors, such as solid Tantalum, POSCap, and Aluminum electrolytic capacitors, and their values can be increased without limit. During load transients, the output capacitors, depending on the stepping amplitude and slew rate of load current, are used to reduce the slew rate of the current seen by the UTC LXXLD50 and help the device to minimize the variations of output voltage for good transient response. Therefore, low-ESR bulk capacitors are universally to be expected for the applications with large stepping load current. In addition, decoupling ceramic capacitors must be located to the load and GND as close as possible and the layout’s impedance should be maintained minimum. Input Capacitor The input capacitors should be chosen properly due to supply current to protect the input rail against dropping during stepping load transients. Because the parasitic inductor from the voltage sources or other bulk capacitors to the VIN pin limit the slew rate of the surge currents. More parasitic inductance needs more input capacitance. More capacitance reduces the variations of the VIN pin voltage. For the UTC LXXLD50, input capacitors with low-ESR are not needed. Ultra-low-ESR capacitors (such as ceramic chip capacitors) are good options, and an aluminum electrolytic capacitor (>100μF, ESR <300mΩ) is recommended as the input capacitor. Feedback Network In the following, the feedback network between VOUT, GND and FB pins is shown in Figure 1. It works with the internal error amplifier to provide proper frequency response for the linear regulator. As seen in Figure 1, the ESR is the equivalent series resistance of the output capacitor. The COUT is ideal capacitance in the output capacitor. The VOUT is the setting of the output voltage. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 7 of 11 QW-R502-474.D LXXLD50 CMOS IC TYPICAL APPLICATION CIRCUIT 1. Using an Output Capacitor with ESR≥18mΩ ADJ Mode VCNTL +5V CCNTL 1µF 6 R3 1k CIN 100µF VCNTL 7 P OK POK VIN 5 3 VOUT 4 VOUT EN 8 EN Enable GND 1 VIN +1.5V VOUT COUT 220µF ADJ 2 R2 2k R1 1k C1 33nF (in the range of 12 ~ 48nF) Fixed Voltage Mode UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 8 of 11 QW-R502-474.D LXXLD50 CMOS IC TYPICAL APPLICATION CIRCUIT (Cont.) 2. Using an MLCC as the Output Capacitor ADJ Mode Fixed Voltage Mode VOUT (V) 1.05 1.5 1.8 R1 (kΩ) 43 27 15 UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw R2 (kΩ) 137.6 30.86 12 C1 (pF) 47 82 150 9 of 11 QW-R502-474.D LXXLD50 TYPICAL CHARACTERISTICS 0.805 1.0 0.802 Reference Voltage,VREF (V) Quiescent Current,IQ (mA) VCNTL Supply Current vs. Junction Temperature 1.1 0.9 0.8 0.7 0.6 Output Voltage, VOUT (mV) Output Current, IOUT (A) 0.799 0.796 0.793 0.79 20 40 60 80 100 120 140 Temperature, ( C) -40 -20 0 Output Voltage, Enable Voltage, VOUT (V) VEN (V) -40 -20 0 Reference Voltage vs. Junction Temperature 20 40 60 80 100 120 140 Temperature, ( C) Power-OK Voltage, VP-OK (V) CMOS IC Output Voltage, Power-OK Voltage, VOUT (V) VP-OK (V) POK Delay VOUT VPOK VIN = 1.5V, VCNTL = 5V,VOUT = 1.2V -COUT = 220µF/6.3V, CIN = 100µF/6.3V, RL=1Ω VOUT1 Time (µs) UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 10 of 11 QW-R502-474.D LXXLD50 CMOS IC UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 11 of 11 QW-R502-474.D