ANPEC APL5912_09

APL5912
0.8V Reference Ultra Low Dropout ([email protected]) Linear Regulator
Features
•
General Description
Ultra Low Dropout
The APL5912 is a 5A ultra low dropout linear regulator.
This product is specifically designed to provide well sup-
- 0.2V (Typical) at 5A Output Current
•
ply voltage for front-side-bus termination on motherboard
and NB applications. The IC needs two supply voltages, a
Low ESR Output Capacitor (Multi-layer Chip
Capacitors (MLCC)) Applicable
•
0.8V Reference Voltage
•
High Output Accuracy
control voltage for the circuitry and a main supply voltage
for power conversion, to reduce power dissipation and
provide extremely low dropout.
The APL5912 integrates many functions. A Power-On-
- ±1.5% Over Line, Load and Temperature
•
•
Reset (POR) circuit monitors both supply voltages to prevent wrong operations. A thermal shutdown and current-
Fast Transient Response
Adjustable Output Voltage by External
limit functions protect the device against thermal and current over-loads. A POK indicates the output status with
Resistors
•
Power-On-Reset Monitoring on Both VCNTL and
time delay which is set internally. It can control other converter for power sequence. The APL5912 is enabled by
VIN Pins
•
Internal Soft-Start
•
Current-Limit Protection
•
Under-Voltage Protection
•
Thermal Shutdown with Hysteresis
•
Power-OK Output with a Delay Time
•
Shutdown for Standby or Suspend Mode
•
Simple SOP-8P Package with Exposed Pad
•
Lead Free and Green Devices Available
other power system. Pulling and holding the EN pin below 0.3V shuts off the output.
The APL5912 is available in a SOP-8P package which
features small size as SOP-8 and an Exposed Pad to
reduce the junction-to-case resistance, being applicable
in 2~2.5W applications.
Pin Configuration
GND
FB
VOUT
VOUT
(RoHS Compliant)
1
8
2
7
3
4
VIN
6
5
EN
POK
VCNTL
VIN
Applications
SOP-8P (Top View)
•
Front Side Bus VTT (1.2V/5A)
•
Note Book PC Applications
•
Motherboard Applications
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Oct., 2009
= Exposed Pad
(connected to the VIN plane for better
heat dissipation)
1
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APL5912
Ordering and Marking Information
Package Code
KA : SOP-8P
Operating Ambient Temperature Range
C : 0 to 70 oC
Handing Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APL5912
Assembly Material
Handling Code
Temperature Range
Package Code
APL5912
XXXXX
APL5912 KA :
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings
Symbol
VCNTL
(Note 1)
Parameter
VCNTL Supply Voltage (VCNTL to GND)
VIN
VIN Supply Voltage (VIN to GND)
VI/O
EN and FB to GND
VPOK
POK to GND
PD
Power Dissipation
Rating
Unit
-0.3 ~ 7
V
-0.3 ~ 3.3
V
-0.3 ~ VCNTL+0.3
V
-0.3 ~ 7
V
3
W
TJ
Junction Temperature
150
o
TSTG
Storage Temperature
-65 ~ 150
o
260
o
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
C
C
C
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
θJA
θJC
Parameter
Junction-to-Ambient Thermal Resistance in Free Air
Typical Value
(Note 2)
SOP-8P
Junction-to-Case Thermal Resistance
40
o
17
o
(Note 3)
SOP-8P
Unit
C/W
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of SOP-8P is soldered directly on the PCB.
Note 3: The “Thermal Pad Temperature” is measured on the PCB copper area connected to the thermal pad of package.
1
2
3
4
8
VIN
7
6
5
Measured Point
PCB Copper
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Oct., 2009
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APL5912
Recommended Operating Conditions
Parameter
Symbol
VCNTL
VIN
VCNTL Supply Voltage
VIN Supply Voltage
Range
Unit
3.1 ~ 6
V
1.0 ~ 3.3
V
0.8 ~ 1.2
0.8 ~ VIN-0.2
V
Output Voltage
VOUT
IOUT
TJ
VCNTL=3.3±5%
VCNTL=5.0±5%
VOUT Output Current
0~6
Junction Temperature
A
o
-25 ~ 125
C
Electrical Characteristics
Refer to “Typical Application Circuits”. These specifications apply over, VCNTL=5V, VIN=1.5V, VOUT = 1.2V and TA=0 to 70°C, unless
otherwise specified. Typical values refer to TA =25°C.
Symbol
Parameter
APL5912
Test Conditions
Unit
Min.
Typ.
Max.
0.4
1
2
mA
-
180
380
µA
2.7
2.9
3.1
V
-
0.4
-
V
0.8
0.9
0.99
V
-
0.5
-
V
SUPPLY CURRENT
ICNTL
ISD
VCNTL Supply Current
EN = VCNTL, VFB is well regulated
VCNTL Shutdown Current
EN = GND
POWER-ON-RESET
VCNTL POR Threshold
VCNTL Rising
VCNTL POR Hysteresis
VIN POR Threshold
VIN Rising
VIN POR Hysteresis
OUTPUT VOLTAGE
VREF
Reference Voltage
FB =VOUT
-
0.8
-
V
Output Voltage Accuracy
IOUT=0A ~ 5A, TJ= -25 ~125oC
-1.5
-
+1.5
%
Line Regulation
VCNTL=3.3 ~ 5.5V
-0.13
-
0.13
%/V
Load Regulation
IOUT=0A ~ 5A
-
0.06
0.15
%
-
0.15
0.2
V
IOUT = 5A, VCNTL=5V, TJ= -25~125 C
-
-
0.25
V
VCNTL=5V, TJ= 25oC
7
8
9
A
6
-
-
A
6.8
7.8
8.8
A
6
-
-
DROPOUT VOLTAGE
Dropout Voltage
IOUT = 5A, VCNTL=5V, TJ= 25oC
o
PROTECTION
o
ILIM
Current Limit
VCNTL=5V, TJ= -25 ~ 125 C
o
VCNTL=3.3V, TJ= 25 C
VCNTL=3.3V, TJ= -25 ~ 125oC
TSD
Thermal Shutdown Temperature
TJ Rising
Thermal Shutdown Hysteresis
Under-Voltage Threshold
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Oct., 2009
VFB Falling
3
-
150
A
-
o
o
-
50
-
-
0.4
-
C
C
V
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APL5912
Electrical Characteristics (Cont.)
Refer to “Typical Application Circuits”. These specifications apply over, VCNTL=5V, VIN=1.5V, VOUT = 1.2V and TA=0 to 70°C, unless
otherwise specified. Typical values refer to TA =25°C.
Symbol
Parameter
APL5912
Test Conditions
Unit
Min.
Typ.
Max.
0.3
0.4
0.5
V
-
30
-
mV
-
10
-
µA
-
2
-
ms
ENABLE AND SOFT-START
EN Logic High Threshold Voltage
VEN Rising
EN Hysteresis
EN Pin Pull-Up Current
TSS
EN=GND
Soft-Start Interval
POWER-OK AND DELAY
VPOK
POK Threshold Voltage for Power OK
VFB Rising
90%
92%
94%
VREF
VPNOK
POK Threshold Voltage for Power Not OK
VFB Falling
79%
81%
83%
VREF
POK Low Voltage
POK sinks 5mA
-
0.25
0.4
V
1
3
10
ms
TDELAY
POK Delay Time
Copyright  ANPEC Electronics Corp.
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APL5912
Typical Operating Characteristics
VCNTL Supply Current vs.
Junction Temperature
Current-Limit vs. Junction Temperature
1.0
8.6
VOUT=1.2V
8.4
VCNTL= 5V
VCNTL=5V
8.2
0.7
Current-Limit, ILIM (A)
VCNTL Supply Current, ICNTL (mA)
0.9
0.8
0.6
VCNTL= 3.3V
0.5
0.4
0.3
0.2
8
7.8
7.6
VCNTL=3.3V
7.4
7.2
0.1
0.0
-50
-25
0
25
50
75
100
7
125
-50
-25
0
50
75
100
125
Junction Temperature (°C)
Junction Temperature (°C)
Dropout Voltage vs. Output Current
Dropout Voltage vs. Output Current
250
200
VCNTL=3.3V
VOUT=1.2V
200
VCNTL=5V
VOUT=1.2V
TJ=125°C
TJ=75°C
Dropout Voltage (mV)
Dropout Voltage (mV)
25
150
TJ=25°C
100
TJ=0°C
50
TJ=-25°C
1
2
3
4
100
TJ=25°C
TJ=0°C
50
0
5
0
Output Current, lOUT(A)
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Oct., 2009
TJ=75°C
TJ=-25°C
0
0
TJ=125°C
150
1
2
3
4
5
Output Current, lOUT(A)
5
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APL5912
Typical Operating Characteristics
Reference Voltage vs. Junction Temperature
POK Delay Time vs. Junction Temperature
4.5
4.3
0.806
4.1
0.804
POK Delay Time (ms)
Reference Voltage, VREF (mV)
0.808
0.802
0.800
0.798
0.796
3.9
VCNTL=5V
3.7
3.5
3.3
VCNTL=3.3V
3.1
2.9
0.794
2.7
0.792
2.5
-50
-25
0
25
50
75
100
125
-50
Junction Temperature (°C)
-25
0
VCNTL PSRR
75
100
125
0
VCNTL = 4.5V~5.5V
VIN = 1.5V
VOUT = 1.2V
IOUT = 5A
CIN = 100µF
COUT = 330µF(ESR=30mΩ)
-10
-20
Amplitude (dB)
Ripple Rejection (dB)
-20.00
50
VIN PSRR
0.00
-10.00
25
Junction Temperature (°C)
-30.00
-40.00
VCNTL = 5V
VIN = 1.5V(lower bound)
VINPK-PK = 100mV
CIN = 47µF
COUT = 330µF(30m ohm)
IOUT = 5A
VOUT = 1.2V
-30
-40
-50.00
-50
-60.00
-60
-70.00
100
1000
10000
100000
100
1000000
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Oct., 2009
1000
10000
100000
1000000
Frequency (Hz)
6
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APL5912
Operating Waveforms
Test Circuit
R4
C2
1µF
L1
1µH
2.2
+5V
5
C8
R8
8.2K 470pF
VCC
OCSET
PHASE
Q1
APM2014N L2
3.3µH
2
VIN
+1.5V
8
U2
APW7057
LGATE
POK
VCNTL
5
GND
3
R5
1.75k
EN
Enable
8
POK
VIN
CIN
100µF
C5
1000µF x2
Q2
APM2014N
4
FB
VCNTL
+5V
6
UGATE
6
C9
47µF
CVCNTL
1µF
C6
0.1µF
Q3
Shutdown
C4
470µF x2
1
BOOT
7
C3
1µF
D1
1N4148
VOUT
R3
1K
7
3
4
VOUT
U1
APL5912
2
EN
FB
GND
R2
2K
COUT
220µF
1
R1
1K
R7
2K
C7
0.1µF
VOUT
+1.2V/5A
C1
33nF
R6
0
1. Load transient Response
1.1 Using an Output Capacitor with ESR≥18mΩ
- COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V
- IOUT = 10mA to 5A to 10mA, Rise time = Fall time = 1µs
IOUT = 10mA ->5A
IOUT = 10mA -> 5A ->10mA
IOUT = 5A ->10mA
R1=1kΩ, R2=2kΩ, C1=33nF
1
1
1
VOUT
VOUT
IOUT
IOUT
VOUT
IOUT
2
2
Ch1 : VOUT, 50mV/Div
2
Ch1 : VOUT, 50mV/Div
Ch1 : VOUT, 50mV/Div
Ch2 : IOUT, 2A/Div
Ch2 : IOUT, 2A/Div
Ch2 : IOUT, 2A/Div
Time : 2µs/Div
Time : 20µs/Div
Time : 2µs/Div
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Oct., 2009
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APL5912
Operating Waveforms (Cont.)
1.2 Using an MLCC as the Output Capacitor
- COUT = 22µF/6.3V (ESR = 3mΩ), CIN = 22µF/6.3V
- IOUT = 10mA to 5A to 10mA, Rise time = Fall time = 1µs
IOUT = 10mA -> 5A
IOUT = 10mA -> 5A ->10mA
IOUT = 5A ->10mA
R1=39kΩ, R2=78kΩ,
R3=30nF
1
1
VOUT
1
VOUT
VOUT
IOUT
IOUT
IOUT
2
2
2
Ch1 : VOUT, 100mV/Div
Ch1 : VOUT, 100mV/Div
Ch1 : VOUT, 100mV/Div
Ch2 : IOUT, 2A/Div
Ch2 : IOUT, 2A/Div
Ch2 : IOUT, 2A/Div
Time : 2µs/Div
Time : 20µs/Div
Time : 2µs/Div
2. Power ON and Power OFF :
- VIN = 1.5V, VCNTL = 5V,VOUT = 1.2V
- COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL = 1Ω
Power OFF
Power ON
VIN
Ch1
Ch1
VVIN
IN
VOUT
VOUT
OUT
V
Ch2
VCNTL
Ch2
VVCNTL
CNTL
VPOK
VVPOK
POK
Ch3
Ch3
Ch4
Ch4
Ch1 : VIN, 1V/div
Ch1 : VIN, 1V/div
Ch2 : VOUT,1V/div
Ch2 : VOUT, 1V/div
Ch3 : VPOK,1V/div
Ch4 : VCNTL,2V/div
Time : 10ms/div
Ch3 : VPOK, 1V/div
Ch4 : VCNTL, 2V/div
Time : 10ms/div
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Oct., 2009
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APL5912
Operating Waveforms (Cont.)
3. Shutdown and Enable :
- VIN = 1.5V, VCNTL = 5V, VOUT = 1.2V
- COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL = 1Ω
Enable
Shutdown
VVEN
EN
Ch1
VVEN
EN
Ch1
V
VOUT
OUT
VOUT
V
OUT
Ch2
Ch2
IIOUT
OUT
IIOUT
OUT
Ch3
Ch3
VVPOK
POK
VVPOK
POK
Ch4
Ch4
Ch1 : VEN, 5V/div
Ch1 : VEN, 5V/div
Ch2 : VOUT, 1V/div
Ch2 : VOUT, 1V/div
Ch3 : IOUT, 1A/div
Ch4 : VPOK, 1V/div
Time : 1ms/div
Ch3 : IOUT, 1A/div
Ch4 : VPOK, 1V/div
Time : 1ms/div
4. POK Delay :
- VIN = 1.5V, VCNTL = 5V, VOUT = 1.2V
- COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL = 1Ω
VIN
IN
V
Ch1
POK Delay
VVOUT
OUT
Ch2
VVPOK
POK
Ch3
Ch1 : VIN, 5V/div
Ch2 : VOUT, 1V/div
Ch3 : VPOK, 1V/div
Time : 1ms/div
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Oct., 2009
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APL5912
Pin Description
PIN
FUNCTION
NO.
NAME
1
GND
2
FB
3,4
VOUT
5
VIN
6
VCNTL
7
POK
8
EN
-
Exposed Pad
Ground pin of the circuitry. All voltage levels are measured with respect to this pin.
Connecting this pin to an external resistor divider receives the feedback voltage of the
regulator. The output voltage set by the resistor divider is determined by :
R1 

VOUT = 0.8 ⋅ 1 +

R2


where R1 is connected from VOUT to FB with Kelvin sensing and R2 is connected from FB to
GND. A bypass capacitor may be connected with R1 in parallel to improve load transient
response.
Output of the regulator. Please connect Pin 3 and 4 together using wide tracks. It is necessary
to connect a output capacitor with this pin for closed-loop compensation and improve transient
responses.
Main supply input pins for power conversions. The Exposed Pad provides a very low
impedance input path for the main supply voltage. Please tie the Exposed Pad and VIN Pin
(Pin 8) together to reduce the dropout voltage. The voltage at this pins is monitored for
Power-On-Reset purpose.
Power input pin of the control circuitry. Connecting this pin to a +5V (recommended) supply
voltage provides the bias for the control circuitry. The voltage at this pin is monitored for
Power-On-Reset purpose.
Power-OK signal output pin. This pin is an open-drain output used to indicate status of output
voltage by sensing FB voltage. This pin is pulled low when the rising FB voltage is not above
the VPOK threshold or the falling FB voltage is below the VPNOK threshold, indicating the output is
not OK.
Enable control pin. Pulling and holding this pin below 0.3V shuts down the output. When
re-enabled, the IC undergoes a new soft-start cycle. When leave this pin open, an internal
current source 10µA pulls this pin up to VCNTL voltage, enabling the regulator.
Main supply input pins for power conversions. The Exposed Pad provides a very low
impedance input path for the main supply voltage. Please tie the Exposed Pad and VIN Pin
(Pin 8) together to reduce the dropout voltage. The voltage at this pins is monitored for
Power-On-Reset purpose.
Block Diagram
EN
VCNTL
VIN
PowerOn-Reset
UV
Soft-Start
and
Control Logic
Thermal
Limit
0.4V
VREF
0.8V
EAMP
VOUT
FB
Current
Limit
POK
Delay
GND
90%
VREF
POK
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Oct., 2009
10
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APL5912
Typical Application Circuit
1. Using an Output Capacitor with ESR≥18mΩ
VCNTL
+5V
CCNTL
1µF
6
R3
1k
VCNTL
7
POK
5
VIN
POK
3
4
VOUT
VOUT
8
EN
APL5912
EN
FB
VOUT
+1.2V / 5A
COUT
220µF
2
R1
1k
GND
Enable
VIN
+1.5V
CIN
100µF
1
R2
2k
C1
33nF
(in the range of 12 ~ 48nF)
2. Using an MLCC as the Output Capacitor
6
R3
1k
POK
VIN
POK
VOUT
VOUT
VIN
+1.5V
CIN
22µF
VCNTL
7
VCNTL
+5V
R4
10 (in the range of 5.1~15Ω)
CCNTL
1µF
5
3
4
COUT
22µF
APL5912
8
EN
EN
FB
2
R1
39k
GND
Enable
VOUT
+1.2V / 5A
1
R2
78k
C1
30pF
VOUT(V)
R1 (kΩ)
R2 (kΩ)
C1 (pF)
1.05
43
137.6
27
1.5
27
30.86
36
1.8
15
12
68
Copyright  ANPEC Electronics Corp.
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APL5912
Function Description
the output again through initiation of a new soft-start cycle
after the junction temperature cools by 50oC, resulting in
Power-On-Reset
A Power-On-Reset (POR) circuit monitors both input voltages at VCNTL and VIN pins to prevent wrong logic
a pulsed output during continuous thermal overload
conditions. The thermal shutdown is designed with a
controls. The POR function initiates a soft-start process
after the two supply voltages exceed their rising POR
50oC hysteresis to lower the average junction temperature during continuous thermal overload conditions, ex-
threshold voltages during powering on. The POR function also pulls low the POK pin regardless the output
tending lifetime of the device.
For normal operation, device power dissipation should
voltage when the VCNTL voltage falls below its falling
POR threshold.
be externally limited so that junction temperatures will
not exceed +125°C.
Internal Soft-Start
Enable Control
An internal soft-start function controls rising rate of the
output voltage to limit the current surge at start-up. The
typical soft-start interval is about 2ms.
The APL5912 has a dedicated enable pin (EN). A logic
low signal (VEN< 0.3V) applied to this pin shuts down the
Output Voltage Regulation
output. Following a shutdown, a logic high signal re-enables the output through initiation of a new soft-start cycle.
An error amplifier works with a temperature-compensated 0.8V reference and an output NMOS regu-
Left open, this pin is pulled up by an internal current source
(10µA typical) to enable operation. It’s not necessary to use
lates output to the preset voltage. The error ampli-
an external transistor to save cost.
fier is designed with high bandwidth and DC gain
Power-OK and Delay
provides very fast transient response and less load
The APL5912 indicates the status of the output voltage by
regulation. It compares the reference with the feedback voltage and amplifies the difference to drive
monitoring the feedback voltage (VFB) on FB pin. As the
VFB rises and reaches the rising Power-OK threshold
the output NMOS which provides load current from
VIN to VOUT.
(VPOK), an internal delay function starts to perform a delay
time. At the end of the delay time, the IC turns off the
Current-Limit
internal NMOS of the POK to indicate the output is OK. As
the VFB falls and reaches the falling Power-OK threshold
The APL5912 monitors the current via the output NMOS
and limits the maximum current to prevent load and
APL5912 from damages during overload or short-circuit
(VPNOK), the IC immediately turns on the NMOS of the POK
to indicate the output is not OK without a delay time.
conditions.
Under-Voltage Protection (UVP)
The APL5912 monitors the voltage on FB pin after softstart process is finished. Therefore, the UVP is disable
during soft-start. When the voltage on FB pin falls below
the under-voltage threshold, the UVP circuit shuts off the
output immediately. After a while, the APL5912 starts a
new soft-start to regulate output.
Thermal Shutdown
A thermal shutdown circuit limits the junction temperature of APL5912. When the junction temperature exceeds
+150°C, a thermal sensor turns off the output NMOS,
allowing the device to cool down. The regulator regulates
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Oct., 2009
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APL5912
Application Information
Power Sequencing
capacitors) and low-ESR bulk capacitors (such as solid
tantalum, POSCap, and Aluminum electrolytic capacitors)
The power sequencing of VIN and VCNTL is not necessary to be concerned. However, do not apply a voltage to
can all be used as an input capacitor of VIN. For most
applications, the recommended input capacitance of VIN
VOUT for a long time when the main voltage applied at
VIN is not present. The reason is the internal parasitic
is 10µF at least. If the drop of the input voltage is not
cared, the input capacitance can be less than 10µF. More
diode from VOUT to VIN conducts and dissipates power
without protections due to the forward-voltage
capacitance reduces the variations of the input voltage of
VIN pin.
Output Capacitor
Feedback Network
The APL5912 requires a proper output capacitor to maintain stability and improve transient response over tem-
Figure 1 shows the feedback network among VOUT, GND,
perature and current. The output capacitor selection is to
select proper ESR (equivalent series resistance) and
and FB pins. It works with the internal error amplifier to
provide proper frequency response for the linear regulator.
capacitance of the output capacitor for good stability and
load transient response.
The ESR is the equivalent series resistance of the output
capacitor. The COUT is ideal capacitance in the output
The APL5912 is designed with a programmable feedback compensation adjusted by an external feedback net-
capacitor. The VOUT is the setting of the output voltage.
work for the use of wide ranges of ESR and capacitance in
all applications. Ultra-low-ESR capacitors (such as ceramic chip capacitors) and low-ESR bulk capacitors (such
as solid tantalum, POSCap, and Aluminum electrolytic
R1
C1
ESR
FB
V ERR
capacitors) can all be used as an output capacitor. The
value of the output capacitors can be increased without
C OUT
V FB
EAMP
VREF
limit.
During load transients, the output capacitors, depending
on the stepping amplitude and slew rate of load current,
are used to reduce the slew rate of the current seen by
R2
Figure 1
the APL5912 and help the device to minimize the variations of output voltage for good transient response. For
The feedback network selection, depending on the values of the ESR and COUT, has been classified into three
conditions :
the applications with large stepping load current, the lowESR bulk capacitors are normally recommended.
• Condition 1 : Large ESR ( ≥18mΩ)
- Select the R1 in the range of 400Ω ~ 2.4kΩ
Decoupling ceramic capacitors must be placed at the load
and ground pins as close as possible and the imped-
- Calculate the R2 as the following:
ance of the layout must be minimized.
R2(kΩ) = R1(kΩ) ⋅
Input Capacitor
0.8(V)
.......... (1)
VOUT(V) - 0.8(V)
- Calculate the C1 as the following:
The APL5912 requires proper input capacitors to supply
current surge during stepping load transients to prevent
the input rail from dropping. Because the parasitic induc-
10 ⋅
VOUT(V)
VOUT(V)
≤ C1(nF) ≤ 40 ⋅
...... (2)
R1(kΩ )
R1(kΩ )
• Condition 2 : Middle ESR
- Calculate the R1 as the following:
tor from the voltage sources or other bulk capacitors to
the VIN pin limit the slew rate of the surge currents, more
parasitic inductance needs more input capacitance.
Ultra-low-ESR capacitors (such as ceramic chip
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Oct., 2009
V OUT
VOUT
APL5912
R1(kΩ) =
13
1500
− 37.5 ⋅ VOUT(V) + 30 ......... (3)
ESR(mΩ)
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APL5912
Application Information (Cont.)
Feedback Network (Cont.)
The reason to have three conditions described above is
Select a proper R1(selected) to be a little larger than the
to optimize the load transient responses for all kinds of
calculated R1.
- Calculate the C1 as the following:
the output capacitor. For stability only, the Condition 2,
C1(pF) = [ESR(mΩ) + 50] ⋅
regardless of equation (5), is enough for all kinds of out-
COUT(µF)
................... (4)
R1(kΩ)
put capacitor.
PCB Layout Consideration (See Figure 2)
Where R1=R1(selected)
1. Please solder the Exposed Pad and VIN together on
Select a proper C1 (selected) to be a little smaller than the
the PCB. The main current flow is through the exposed
pad.
calculated C1.
- The C1 calculated from equation (4) must meet the
2. Please place the input capacitors for VIN and VCNTL
pins near pins as close as possible.
following equation :

  37.5 ⋅ VOUT(V) 
50
C1(pF) ≥ 5.1 ⋅ 1 +
 ⋅ 1 +
 .. (5)
R1(kΩ)
 ESR(mΩ)  

3. Ceramic decoupling capacitors for load must be placed
near the load as close as possible.
Where R1=R1(calculated) from equation (3)
4. To place APL5912 and output capacitors near the load
is good for performance.
If the C1(calculated) can not meet the equation (5),
please use the Condition 3.
5. The negative pins of the input and output capacitors
and the GND pin of the APL5912 are connected to the
- Use equation (2) to calculate the R2.
• Condition 3: Low ESR (eg. Ceramic Capacitors)
ground plane of the load.
6. Please connect PIN 3 and 4 together by a wide track or
- Calculate the R1 as the following:
R1(k Ω ) = (5.9 ⋅ ESR(m Ω ) + 294) ⋅ COUT (µF) − 37.5 ⋅ VOUT (V) .. (6)
plane on the Top layer.
7. Large current paths must have wide tracks.
Select a proper R1(selected) to be a little larger than the
calculated R1. The minimum selected R1 is equal to
8. See the Typical Application
- Connect the one pin of the R2 to the GND of APL5912.
1kΩ when the calculated R1 is smaller than 1k or
negative.
VCNTL
CCNTL
CIN
- Calculate the C1 as the following :
VCNTL
C1(pF) =
VIN
VIN
 37.5 ⋅ VOUT(V) 
(0.17 ⋅ ESR(mΩ) + 8.5) ⋅ COUT(µF) ⋅ 1 +
 .. (7)
R1(kΩ)


APL5912
VOUT
VOUT
VOUT
Where R1=R1(selected)
COUT
C1
Select a proper C1(selected) to be a little smaller than
the calculated C1.
FB
Load
GND
- The C1 calculated from equation (7) must meet the
following equation :
R1
R2

1.25 ⋅ VOUT(V) 
C1(pF) ≥ 0.033 +
 ⋅ ESR(mΩ) ⋅ COUT(µF) .. (8)
R1(kΩ)


Figure 2
- Connect the one pin of R1 to the Pin 3 of APL5912
Where R1=R1(calculated) from equation (6)
- Connect the one pin of C1 to the Pin 3 of APL5912
If the C1(calculated) can not meet the equation (8),
please use the Condition 2.
- Use equation (2) to calculate the R2.
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Oct., 2009
14
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APL5912
Application Information (Cont.)
Thermal Consideration
See Figure 3. The SOP-8P is a cost-effective package
featuring a small size like a standard SOP-8 and a bottom exposed pad to minimize the thermal resistance of
the package, being applicable to high current applications.
The exposed pad must be soldered to the top VIN plane.
The copper of the VIN plane on the Top layer conducts heat
into the PCB and air. Please enlarge the area to reduce
the case-to-ambient resistance (θCA).
102 mil
118 mil
1
8
2
7
SOP-8P
3
6
5
4
Top
VOUT
plane
Die
Exposed
Pad
Top
VIN
plane
Ambient
Air
PCB
Figure 3
Recommended Minimum Footprint
8
7
6
5
0.072
0.024
0.118
0.212
0.138
1
2
0.050
3
4
Unit : Inch
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Oct., 2009
15
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APL5912
Package Information
SOP-8P
D
SEE VIEW A
h X 45o
E
THERMAL
PAD
E1
E2
D1
c
A1
0.25
A2
A
b
e
GAUGE PLANE
SEATING PLANE
θ
L
VIEW A
S
Y
M
B
O
L
SOP-8P
MILLIMETERS
MIN.
INCHES
MIN.
MAX.
A
MAX.
1.60
A1
0.00
0.063
0.15
0.000
0.006
0.049
A2
1.25
b
0.31
0.51
0.012
0.020
c
0.17
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
0.138
D1
2.50
3.50
0.098
E
5.80
6.20
0.228
0.244
E1
3.80
4.00
0.150
0.157
E2
2.00
3.00
0.079
0.118
e
1.27 BSC
0.050 BSC
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
0
o
0C
o
o
8C
0C
8oC
Note : 1. Followed from JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Oct., 2009
16
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APL5912
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
A
H
T1
C
d
D
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.40±0.20
5.20±0.20
2.10±0.20
SOP-8P
4.0±0.10
8.0±0.10
W
E1
12.0±0.30 1.75±0.10
F
5.5±0.05
(mm)
Devices Per Unit
Package Type
Unit
Quantity
SOP- 8P
Tape & Reel
2500
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Oct., 2009
17
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APL5912
Taping Direction Information
SOP-8P
USER DIRECTION OF FEED
Classification Profile
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Oct., 2009
18
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APL5912
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Oct., 2009
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
19
Description
5 Sec, 245°C
1000 Hrs, Bias @ 125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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APL5912
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.10 - Oct., 2009
20
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