Datasheet

UNISONIC TECHNOLOGIES CO., LTD
UC2843B
LINEAR INTEGRATED CIRCUIT
HIGH-PERFORMANCE
CURRENT-MODE PWM
CONTROLLERS

DESCRIPTION
The UTC UC2843B provides off-line or DC-DC
fixed-frequency current-mode control design with minimum
external components. Internally-implemented circuits include an
under-voltage lockout (UVLO) and a precision reference with
accuracy at the error amplifier input. The UTC UC2843B also
contain internal circuits which include a pulse width modulation
(PWM) comparator providing current-limit control, logic ensuring
latched operation, and a totem-pole output stage designed to
source or sink high-peak current. The output stage is low when it
is in off-state condition and suitable for N-channel MOSFETs
driving.
The UTC UC2843B also has following advantages: the
start-up current lower than 0.5mA while the oscillator discharge
current is specified to 8.3mA (Typ.). In UVLO conditions, the
output has a maximum saturation voltage of 1.2V when sinking
[email protected] = 5V.
The typical UVLO threshold of the UTC UC2843B is 8.4V
(on) and 7.6V (off) and can operate to duty cycles approximately
100%.

FEATURES
* Current mode operation:500 kHz
* Low start-up current value<0.5mA
* Latching PWM for cycle-by-cycle current limiting
* Trimmed oscillator discharge current

* Automatic feed-forward compensation
* Internally trimmed reference with UVLO
* High-current totem-pole output UVLO with hysteresis
* Double-pulse suppression
ORDERING INFORMATION
Ordering Number
Lead Free
Halogen Free
UC2843BL-S08-R
UC2843BG-S08-R
UC2843BL-S08-T
UC2843BG-S08-T
UC2843BL-D08-T
UC2843BG-D08-T
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Copyright © 2013 Unisonic Technologies Co., Ltd
Package
Packing
SOP-8
SOP-8
DIP-8
Tape Reel
Tube
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QW-R103-048.D
UC2843B
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LINEAR INTEGRATED CIRCUIT
PIN CONFIGURATION
COMP 1
VFB 2


8 VREF
7 VCC
ISENSE 3
6 OUTPUT
RT/CT 4
5 GND
PIN DESCRIPTION
PIN NO.
1
PIN NAME
COMP
2
VFB
3
ISENSE
4
RT/CT
5
GND
6
OUTPUT
7
VCC
8
VREF
DESCRIPTION
This pin is the Error Amplifier output and is made available for loop compensation.
This is the inverting input of the Error Amplifier. It is normally connected to the
switching power supply output through a resistor divider.
A voltage proportional to inductor current is connected to this input. The PWM uses
this information to terminate the output switch conduction.
The Oscillator frequency and maximum Output duty cycle are programmed by
connecting resistor RT to VREF and capacitor CT to ground. Operation to 500 kHz is
possible.
This pin is the combined control circuitry and power ground.
This output directly drives the gate of a power MOSFET. Peak currents up to 1.0A are
sourced and sunk by this pin.
This pin is the positive supply of the control IC.
This is the reference output. It provides charging current for capacitor CT through
resistor RT.
BLOCK DIAGRAM
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LINEAR INTEGRATED CIRCUIT
ABSOLUTE MAXIMUM RATING (TA=25°C, unless otherwise specified)
PARAMETER
Supply Voltage (Low impedance source)
Analog Input Voltage (VFB and ISENSE)
Supply Current
Error Amplifier Output Sink Current
Output Current
RATINGS
UNIT
30
V
-0.3~+6.3
V
30
mA
10
mA
±1
A
800
SOP-8
Power Dissipation
mW
PD
DIP-8
1250
Output Energy (Capacitive load)
W
5
μJ
Junction Temperature
TJ
150
°C
Operating Temperature
TOPR
-40~+85
°C
Storage Temperature
TSTG
-65~+150
°C
Notes: 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
2. All voltages are concerning the device GND terminal.

SYMBOL
VCC
VIN
ICC
IO(SINK)
IOUT
THERMAL DATA
PARAMETER
SYMBOL
Thermal Resistance Junction to Ambient

SOP-8
DIP-8
θJA
UNIT
C/W
C/W
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
VCC
Supply Voltage
Input Voltage
RT/CT
VFB and ISENSE
Output Voltage (OUTPUT)
Supply Current, Externally Limited
Output Current
Reference Output Current
Oscillator Frequency
Operating Temperature

RATINGS
156
100
VIN
VOUT
ICC
IOUT
IO(REF)
fOSC
TA
MIN
TYP
0
0
0
100
-40
MAX
30
5.5
5.5
30
25
200
-20
500
+85
UNIT
V
V
V
V
mA
mA
mA
kHz
°C
ELECTRICAL CHARACTERISTICS
(VCC=15V, RT =10kΩ, CT=3.3nF, TJ=25°C, unless otherwise specified)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
REFERENCE SECTION
Reference Output Voltage
VREF
IOUT =1mA, TJ =25°C
4.95
Line Regulation
∆VOUT
VCC = 12V~25V
Load Regulation
∆VOUT
IOUT = 1mA~20mA
Average Temperature Coefficient Of
TS
Output Voltage
Total Output Variation
VREF
VCC =12V~25V, IOUT =1mA~20mA 4.9
Output Noise Voltage
eN
f = 10Hz~10kHz, TJ =25°C
Long Term Stability
TJ=25°C For 1000 hours
Output Short Circuit Current
ISC
-30
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TYP
MAX
UNIT
5
6
6
5.05
20
25
V
mV
mV
0.2
0.4
mV/°C
5.1
V
μV
mV
mA
50
5
-100
25
-180
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ELECTRICAL CHARACTERISTICS(Cont.)
PARAMETER
OSCILLATOR SECTION
Frequency
SYMBOL
fOSC
Frequency Change with Voltage
Frequency Change with
Temperature
Oscillator Voltage Swing
Discharge Current
ERROR-AMPLIFIER SECTION
Voltage Feedback Input
Input Bias Current
Open Loop Voltage Gain
Unity Gain Bandwidth
Power Supply Rejection Ratio
Output Sink Current
Output Source Current
Output Voltage Swing High State
CURRENT-SENSE SECTION
Current Sense Input Voltage Gain
Maximum Current Sense Input
Threshold
Power Supply Rejection Ratio
Input Bias Current
Propagation Delay
OUTPUT SECTION
∆fOSC
∆V
∆fOSC
∆T
VOSC
IDISC
VFB
II(BIAS)
GVO
GBW
PSRR
ISINK
ISOURCE
VOH
VOL
TEST CONDITIONS
TJ =25°C, RT =62kΩ, CT =1nF,
Min =225 kHz, Max =275 kHz
TJ = Full range
TYP
MAX
UNIT
49
52
55
kHz
56
kHz
1
%
48
VCC = 12V ~ 25V
0.2
TJ = Full range
5
Peak to peak
TJ =25°C, RT/CT =2V
RT/CT =2V
7.8
7.5
COMP =2.5V
2.45
VOUT =2V~4V
65
0.7
60
2
-0.5
5
VCC =12V~25V
VFB =2.7V, COMP=1.1V
VFB =2.3V, COMP =5V
VFB =2.3V, RL =15kΩ to GND
VFB =2.7V, RL =15kΩ to GND
1.7
8.3
%
8.8
8.8
V
mA
mA
2.5
-0.3
90
1
70
6
-0.8
6
0.7
2.55
-1
1.1
V
μA
dB
MHz
dB
mA
mA
V
V
GV
(Note 2,3)
2.85
3
3.15
V/V
VTH
COMP =5V (Note 2)
0.9
1
1.1
V
70
-2
150
-10
300
dB
μA
ns
13.5
13.5
0.1
1.5
0.4
2.2
V
V
V
V
0.7
1.2
V
50
50
150
150
ns
ns
7.8
8.4
9
V
7
7.6
8.2
V
94
96
100
0
%
%
0.5
17
30
0.3
11
34
mA
mA
V
PSRR
II(BIAS)
tD
High-Level Output Voltage
VOH
Low-Level Output Voltage
VOL
VCC =12V~25V (Note 2)
VFB =0V~2V
IOH =-20mA
IOH =-200mA
IOL =20mA
IOL =200mA
Under-Voltage Lockout
VUVLO
VCC =5V, IOL=1mA
Output Voltage
Output Voltage Rise Time
tR
CL =1nF, TJ = 25°C
Output Voltage Fall Time
tF
CL =1nF, TJ = 25°C
UNDERVOLTAGE-LOCKOUT SECTION
Startup Threshold
VTH
Minimum Operating Voltage
VCC(MIN)
After Start-Up
PULSE-WIDTH MODULATOR SECTION
Maximum Duty Cycle
DC(MAX)
Minimum Duty Cycle
DC(MIN)
SUPPLY VOLTAGE
Power Startup Supply Current
ICC+IC
Power Operating Supply Current
ICC+IC
VFB and ISENSE at 0V
Power Supply Zener Voltage
VZ
ICC =25mA
Notes: 1. Adjust VCC above the start threshold before setting it to 15V.
2. Measured at the trip point of the latch, with VFB at 0V.
3. Measured between ISENSE and COMP, with the input changing from 0V ~ 0.8V.
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LINEAR INTEGRATED CIRCUIT
APPLICATION INFORMATION
Error amplifier (EA) configuration circuit:
0.5mA
2.5V
EA
VFB
Z1
Z2
Error
Amplifier
COMP
Note: Error amplifier can source or sink up to 0.5mA.
Current-sense circuit:
Notes: 1. Peak current (IS) is determined by the formula: IS(max) = 1V/RS
2. A small RC filter formed by resistor RF and capacitor CF may be required to suppress switch transients.
The oscillator frequency is set using the circuit:
VREF
RT
RT/CT
CT
GND
The frequency is calculated as followed:
f = 1 / RTCT
For RT > 5kΩ:
f = 1.72 / RTCT
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LINEAR INTEGRATED CIRCUIT
APPLICATION INFORMATION(Cont.)
Open-Loop Laboratory Test Fixture
In the open-loop laboratory test fixture, high peak currents and loads need grounding techniques. The transistor
and 5-kΩ potentiometer sample the oscillator waveform, applying an adjustable ramp to the ISENSE terminal. Timing
and bypass capacitors should be connected closely to the GND terminal in a single-point ground.
Shutdown Technique
The PWM controller can be shut down through two methods: the one is raising voltage (above 1 V) at ISENSE, the
other is pulling the COMP terminal below a voltage two diode drops above ground. Either method can leave the
output of the PWM comparator high (refer to block diagram). To reset the PWM latch is dominant so the output can
stay low in the case of the next clock cycle is coming and the COMP or ISENSE terminal is removed beyond this
shutdown condition. For example, an externally-latched shutdown can be accomplished by adding an SCR reset by
cycling VCC below the lower UVLO threshold. So the reference turns off then allows the SCR to reset at this
condition.
1kΩ
VREF
COMP
Shutdown
330Ω
ISENSE
500Ω
To Current-Sense
Resistor
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LINEAR INTEGRATED CIRCUIT
APPLICATION INFORMATION(Cont.)
Shutdown Technique (cont.)
A fraction of the triangular-wave oscillator can be summed resistively with the current-sense signal providing
slope compensation for converters, which requiring duty cycles over 50%. Please note that capacitor C forms a filter
with R2 to suppress the leading-edge switch spikes.
VREF
0.1µF
RT
RT/CT
CT
R1
ISENSE
R2
ISENSE
C
RSENSE
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Supply Current, ICC (mA)
TYPICAL CHARACTERISTICS
Timing Resistor, RT (kΩ)

LINEAR INTEGRATED CIRCUIT
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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