Datasheet

UNISONIC TECHNOLOGIES CO., LTD
UCS16505S
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LINEAR INTEGRATED CIRCUIT
HIGH PERFORMANCE
CURRENT MODE POWER
SWITCH
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DESCRIPTION
The UTC UCS16505S is an integrated PWM controller and Power
MOSFET specifically designed for switching operation with minimal
external components. The UTC UCS16505S is designed to provide
several special enhancements to satisfy the needs, for example,
Power-Saving mode for low standby power, Frequency Hopping ,
Constant Output Power Limiting , Slope Compensation ,Over Current
Protection (OCP), Over Voltage Protection (OVP), Over Load
Protection (OLP), Under Voltage Lock Out (UVLO), Over Temperature
Protection (OTP), etc. IC will be shutdown or can auto-restart in
situations.
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FEATURE
* Internal Power MOSFET (650V)
* Programming Gate Driver Capability
* Frequency hopping for Improved EMI Performance.
* Lower than 0.3W Standby Power Design
* Linearly decreasing frequency to 26KHz during light load
* Internal Soft start
* Internal Slope Compensation
* Constant Power Limiting for universal AC input Range
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ORDERING INFORMATION
Ordering Number
Lead Free
Halogen Free
UCS16505SL-D08-T
UCS16505SG-D08-T
UCS16505SG-S08-R
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* Gate Output Maximum Voltage Clamp(16V)
* Over temperature protection
* Overload protection
* Over voltage protection
* Leading edge blanking
* Cycle-by-Cycle current limiting
* Under Voltage Lock Out
Package
Packing
DIP-8
SOP-8
Tube
Tape Reel
MARKING
DIP-8
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Copyright © 2015 Unisonic Technologies Co., Ltd
SOP-8
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UCS16505S
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LINEAR INTEGRATED CIRCUIT
PIN CONFIGURATION
PIN DESCRIPTION
PIN NO.
1
2
3
4
5
6
7
8
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PIN NAME
VCC-G
VCC
FB
CS
DRAIN
DRAIN
GND
GND
DESCRIPTION
Supply voltage
Supply voltage
Feedback
Current sense input
Power MOSFET drain
Power MOSFET drain
Ground
Ground
BLOCK DIAGRAM
VCC
VCC-G
2
1
HVStartup
Frequency
Hopping
OVP
Oscillator
UVLO
Reference voltage
Logic
Control
6
DRAIN
5
DRAIN
Soft Start
Latch
Delay
Time
OTP
Burstmode
Driver
S
Q
R
Q
OLP
FB 3
PWM COMP
Slope
Compensation
Constant Power
Limit
OCP
LEB
4
CS
8
GND
7
GND
Notes: OLP (Over Load Protection)
OVP (Over Voltage Protection)
OTP (Over Temperature Protection)
OCP (Over Current Protection)
UVLO (Under Voltage Latch-Out)
LEB (Led Edge Blanking)
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LINEAR INTEGRATED CIRCUIT
ABSOLUTE MAXIMUM RATING (TA=25°C, unless otherwise specified)
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage
VCC
32
V
Input Voltage to FB Pin
VFB
-0.3 ~ 6.5
V
Input Voltage to CS Pin
VCS
-0.3 ~ 6.5
V
Junction Temperature
TJ
+150
°C
Operating Temperature
TOPR
-40 ~ +125
°C
Storage Temperature
TSTG
-50 ~ +150
°C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
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OPERATING RANGE
PARAMETER
Supply Voltage

SYMBOL
VCC
RATINGS
10 ~ 24
UNIT
V
ELECTRICAL CHARACTERISTICS (TA=25°C, VCC=15V, unless otherwise specified)
PARAMETER
SYMBOL
SUPPLY SECTION
Start Up Current
IST
Supply Current with switch
IOP
VDD Zener Clamp current
vCLAMP
UNDER-VOLTAGE LOCKOUT SECTION
Start Threshold Voltage
VTHD(ON)
Min. Operating Voltage
VCC(MIN)
CONTROL SECTION
Feedback Source Current
IFB
VFB Open Loop Voltage Level
VFB_Open
Burst-Mode Out FB Voltage
VFB(OUT)
Burst-Mode Enter FB Voltage
VFB(IN)
Normal initial
Switching frequency
F(SW)
Power-Saving
Duty Cycle
DMAX
Frequency Hopping
FJ(SW)
Frequency Variation VS VCC Deviation
FDV
Frequency Variation VS Temperature Deviation
FDT
Soft-Start Time
TSOFTS
PROTECTION SECTION
OVP threshold
VOVP
OLP threshold
VFB(OLP)
Delay Time Of OLP
TD-OLP
OTP Threshold
T(THR)
CURRENT LIMITING SECTION
Leading Edge Blanking Time
tLEB
Peak Current Limitation
VCS
Threshold Voltage For Valley
VSENSE-L
POWER MOS-TRANSISTOR SECTION
Drain-Source Breakdown Voltage
VDSS
Turn-on voltage between gate and source
VTH
Drain-Source Diode Continuous Source Current
IS
Static Drain-Source On-State Resistance
RDS(ON)
Notes: 1. Pulse Test: Pulse width≤300μs, Duty cycle≤2%.
2. Essentially independent of operating temperature.
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TEST CONDITIONS
VCC = VTHD(ON)-1V
VFB= 3.5V
IVDD=20mA
MIN
TYP
MAX
UNIT
28
2
0.8
30
15
1.8
32
μA
mA
V
18
6.5
20
8
22
9.5
V
V
VFB=0
VCS =0
VCS =0
VFB = 3.5V
Before enter burst mode
VFB=3.5V, VCS=0
60
20
240
5.4
1.8
1.6
65
70
78
±4
VCC=10 ~ 20V
T=-40 ~ 85°C
10
10
5
VFB=3.5V
VCS=0
25
60
VFB=3.9V
VFB=3.9V
0.5
VGS=0V, ID=250μA
VDS=VGS, ID=250μA
650
2
VGS=10V,ID=1.1A
27
4.2
88
140
350
0.92
0.58
29
120
uA
V
V
V
kHz
kHz
%
kHz
%
%
ms
V
V
ms
°C
0.66
nS
V
V
4
1
13
V
V
A
Ω
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LINEAR INTEGRATED CIRCUIT
FUNCTIONAL DESCRIPTION
The internal reference voltages and bias circuit work at VCC> VTHD(ON), and shutdown at VCC<VCC(MIN).
(1) Soft-Start
When every IC power on, driver output duty cycle will be decided by inter-slope voltage VSOFTS and VCS on
current sense resistor at beginning. After the whole soft-start phase end, and driver duty cycle depend on VFB and
VCS. The relation among VSOFTS, VFB and VOUT as followed Fig.3. Furthermore, soft-start phase should end before VCC
reach VCC(MIN) during VCC power on. Otherwise, if soft-start phase remain not end before VCC reach VCC(MIN) during
VCC power on, IC will enter auto-restart phase and not set up VOUT.
Fig.3 Soft-start phase
(2) Switching Frequency Set
The maximum switching frequency is set to 65kHz. Switching frequency is modulated by output power POUT
during IC operating. At no load or light load condition, most of the power dissipation in a switching mode power
supply is from switching loss on the MOSFET transistor, the core loss of the transformer and the loss on the snubber
circuit. The magnitude of power loss is in proportion to the number of switching events within a fixed period of time.
So lower Switching frequency at lower load, which more and more improve IC’s efficiency at light load. At from no
load to light load condition, The IC will operate at from Burst mode to Reducing Frequency Mode. The relation curve
between fSW and POUT/POUT(MAX) as followed Fig.4.
70
1%~100% Load @ 115 & 230 Vac
60
FSW (KHz)
55
115V
40
230V
25
10
1%
19%
9%
30%
100%
POUT/POUT(max)
Fig.4 The relation curve between fSW and relative output power POUT/ POUT (MAX)
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LINEAR INTEGRATED CIRCUIT
FUNCTIONAL DESCRIPTION(Cont.)
(3) Internal Synchronized Slope Compensation
Built-in slope compensation circuit adds voltage ramp onto the current sense input voltage for PWM
generation, this greatly improves the close loop stability at CCM and prevents the sub-harmonic oscillation and thus
reduces the output ripple voltage.
(4) Frequency Hopping For EMI Improvement
The Frequency Hopping is implemented in the IC; there are two oscillators built-in the IC. The first oscillator
is to set the normal switching frequency; the switching frequency is modulated with a period signal generated by the
2nd oscillator. The relation between the first oscillator and the 2nd oscillator as followed Fig.5. So the tone energy is
evenly spread out, the spread spectrum minimizes the conduction band EMI and therefore eases the system design
in meeting stringent EMI requirement.
Fig.5 Frequency Hopping
(5) Constant Output Power Limit
When the primary current, across the primary wind of transfer, reaches the limit current, the output GATE drive
will be turned off after a small propagation delay tD. This propagation delay will introduce an additional current
proportional to tD×VIN/Lp. Since the propagation delay is nearly constant regardless of the input line voltage VIN.
Higher input line voltage will result in a larger additional current and hence the output power limit is also higher than
that under low input line voltage. To compensate for this output power limit variation across a wide AC input range,
the threshold voltage is adjusted by adding a positive ramp. This ramp signal rises from 0.6V to 0.9V, and then
flattens out at 0.9V. A smaller threshold voltage forces the output GATE drive to terminate earlier. This reduces the
total PWM turn-on time and makes the output power equal to that of low line input. This proprietary internal
compensation ensures a constant output power limit for a wide AC input voltage range (90VAC to 264VAC).
(6) Protection section
The IC takes on more protection functions such as OLP, OVP and OTP etc. In case of those failure modes for
continual blanking time, the driver is shut down. At the same time, IC enters auto-restart, VCC power on and driver is
reset after VCC power on again.
OLP
After power on, IC will shutdown driver if over load state occurs for continual TD-OLP. OLP case as followed Fig.6.
The test circuit as followed Fig.8.
OVP
OVP will shutdown the switching of the power MOSFET whenever VCC>VOVP. The OVP case as followed Fig.7.
the test circuit as followed Fig.9.
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LINEAR INTEGRATED CIRCUIT
FUNCTIONAL DESCRIPTION(Cont.)
Fig.6 OLP case
Fig.7 OVP case
15V
VDD
470u
33n
500Ω/1W
15V
VCC
IC3
8
1
470u
2
33n
2.5V
Fig.8 OLP test circuit
Drain
7
UTC
UCS16505S
3
6
4
5
VOVP
VCC
Fig.9 OVP test circuit
OTP
OTP will shut down driver when junction temperature TJ>T(THR) for continual a blanking time.
(7) Driver Output Section
The driver-stage drives the gate of the MOSFET and is optimized to minimize EMI and to provide high circuit
efficiency. This is done by reducing the switch on slope when reaching the MOSFET threshold. This is achieved by a
slope control of the rising edge at the driver’s output. The output driver is clamped by an internal 15V Zener diode in
order to protect power MOSFET transistors against undesirable gate over voltage.
(8) Inside power switch MOS transistor
Specific power MOS transistor parameter is as “POWER MOS TRANSISTOR SECTION” in electrical
characteristics table.
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LINEAR INTEGRATED CIRCUIT
TYPICAL APPLICATION CIRCUIT
Fig.10 UTC UCS16505S Typical Application Circuit
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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