LINEAR TECHNOLOGY AUGUST 1996 IN THIS ISSUE . . . COVER ARTICLE Safe Hot Swapping Using the LTC®1421 ........ 1 Robert Reay and James Herr VOLUME VI NUMBER 3 Safe Hot Swapping Using the LTC1421 by Robert Reay and James Herr Issue Highlights .............. 2 DESIGN FEATURES The Care and Feeding of High Performance ADCs: Get All the Bits You Paid For ........................................ 8 William C. Rempfer LTC1433/LTC1434: High Efficiency, Constant-Frequency Monolithic Buck Converter ...................................... 13 San-Hwa Chee The LTC1343 and LTC1344 Form a Software-Selectable Multiple-Protocol Interface Port Using a DB-25 Connector ...................................... 15 Robert Reay DESIGN IDEAS Li-Ion Battery Charger Does Not Require Precision Resistors ....................... 25 Arie Ravid Constant-Voltage Load Box for Battery Simulation ...................................... 26 Jon Dutra LT1510 Charger with –∆V Termination ............ 27 Arie Ravid (more Design Ideas on pages 28–41. Complete list on page 25) Design Tools .................. 43 Sales Offices ................. 44 When a circuit board is inserted into a live backplane, the large bypass capacitors on the board can draw huge inrush currents from the backplane power bus as they charge. The inrush current, on the order of 10 to 100 amps, can destroy the board’s bypass capacitors, metal traces or connector pins. The inrush current can also cause a glitch on the backplane power bus, which may force all of the other boards in the system to reset. At the same time, the system data bus can be disrupted when the board’s data pins make or break contact. The LTC1421 can turn on up to three board supply voltages at a programmable rate, allowing boards to be safely inserted in or removed from a live backplane. The chip also provides board connection sensing, a method for halting the system data bus during insertion or removal, flexible supply voltage monitoring, power-on reset outputs, short-circuit protection and digital input or pushbutton power cycling control. Typical Application Figure 1 shows a typical application using the LTC1421. The power supplies on the board are controlled by placing external N-channel pass transistors Q1, Q2 and Q3 in the power path for VCC, VDD and VEE, where VCC and VDD can range from 3.0V to 12.0V. By ramping the gates of the pass transistors up or down at a controlled rate, the transient surge current (I = C × dv/dt) drawn from the main backplane supply will be limited to a safe value. The LTC1421 is designed for use with a staggered 3-level connector. Ground should make connection first to discharge any static buildup. VCC, VDD, VEE and DISABLE should make connection second and the data bus and all other pins last. The connection sense pins CON1 and CON2 must be located on opposite ends of the connector because most people will rock the board back and forth during insertion. The system timing is shown in Figure 2. When the supply pins make contact, (Figure 2, time point 1), the LTC1421 prevents transistors Q1 and Q2 from turning on by holding their gates (GATELO and GATEHI) at ground, while C3 and R4 keep Q3 off by pulling its gate to –12V. The Schottky diode in the output stage of CPON allows the pin to be pulled below ground. The two connection sense pins, CON1 and CON2, are initially pulled to VCCLO by 10k pullup resistors. PWRGD and RESET are held low while VCCLO and VCCHI are pulled to ground by internal transistors N1 and N2. At the same time, DISABLE is pulled high, turning on transistor Q4, which will halt traffic on the backplane data bus before the data pins make contact. CON1 and CON2 are the last pins to make contact and are shorted to ground on the backplane side of the connector. After continued on page 3 , LTC and LT are registered trademarks of Linear Technology Corporation. Adaptive Power, C-Load, LinearView, Micropower SwitcherCAD and Burst Mode are trademarks of Linear Technology Corporation. Other product names may be trademarks of the companies that manufacture the products. EDITOR'S PAGE Issue Highlights This issue of Linear Technology features more exciting new products from Linear Technology’s design team. Our lead article explains “safe hot swapping” using the LTC1421 hot swap controller. This device prevents inrush currents that can destroy components and traces. It also eliminates glitches that disrupt the system bus when a circuit board is plugged into a “live” backplane. The LTC1421 can turn on up to three board supply voltages at programmable rates. The part provides board connection sensing, which can be used to halt the system bus during board insertion or removal, power-on reset outputs, short-circuit protection and digital input or pushbutton power cycling. Also in this issue, we have an in-depth examination of the “Care and Feeding of High Performance ADCs,” such as the 1.25Msps, 12-bit LTC1410. Designers will be finding many new applications for these parts because of their excellent specifications and attractive pricing. This article provides the layout, bypassing and other design techniques that will allow you to obtain maximum performance from these precision parts. In the area of power products, we introduce the LTC1433 and LTC1434 high efficiency, constant-frequency monolithic buck converters. These devices achieve high efficiency and constant frequency at low load currents using the Adaptive Power™ mode first introduced in the LTC1435– LTC1439 family of DC/DC controllers. Also new are a pair of interface products, the LTC1343 and LTC1344. The LTC1343 contains four drivers and four receivers and the LTC1344 contains six switchable resistive terminators. Together, these two devices can implement a software-selectable, multiple-protocol serial port that supports a wide range of protocols. This month, we have a generous helping of Design Ideas, including two battery chargers, plus a constant-voltage load box for battery simulation; some unusual amplifier 2 LTC in the News... “Technology stocks have fallen so far in recent months that they have become tantalizing to bottom-fishing value investors, who rarely get a chance to buy normally pricey computer and semiconductor makers,” wrote E.S. Browning, staff reporter of the Wall Street Journal, in an article in the Dow Jones Newswire. “These companies now look like real bargains,” he writes. Chicago Corp. analyst David Wu said, “Linear is a good company in a great business with high barriers to entry.” He added that he looks for a resumption of double-digit growth after a period of adjustment, which could take a year. Even more bullish on Linear is Ed Jamieson, manager of the Franklin Small Cap Growth fund, who told Barron’s Financial Weekly in July that he believes LTC can produce 25%–50% returns in the next 12 months. “Historically, its market grew 35% a year…. It’s crazy not to think this company will reemerge.” The perceptions of these shrewd industry observers are turning out to be prophetic. On July 23, LTC announced that net sales for its fiscal year ended June 30 were a record $377,771,000, an increase of 43% over the previous year. The company also reported record net income for the year of $133,964,000 or $1.72 per share, an increase of 58% over $84,696,000 or $1.11 per share reported for fiscal 1995. According to Robert H. Swanson, Jr., president and CEO of Linear Technology Corp., “1996 was a very strong year for us in sales, profits and cash growth. Our rate of sales growth was higher than our historical average in response to a very robust market early in the year. The current environment is balancing out some of this accelerated growth and our sales for the fourth quarter were less than the previous quarter for the first time in ten years,” Swanson said. “Net income as a percentage of sales continued to be the strongest in the industry. The long term prospects for our business are excellent and we continue to invest in the plant infrastructure and technical talent to maximize our opportunities. In the short term, however, reduced backlog and shorter lead times have caused the business to be more dependent on orders that are received and shipped in the same quarter,” Swanson said. applications featuring the LT1210 and the LT1336; a micropower voltage-tofrequency converter; a circuit for measuring small capacitance changes and several power supply designs. Also new from Linear Technology this month are the LinearView™ CD-ROM and the Micropower SwitcherCAD™ design software. The LinearView CD-ROM contains all product data from Linear Technology’s Databooks (volumes I– IV) and applications information from Linear’s Applications Handbooks (volumes I and II), plus the complete collections of Design Notes and back issues of Linear Technology magazine. MicroPower SwitcherCAD is a powerful tool for designing DC/DC converters based on Linear Technology’s micropower switching regulator ICs. Given basic design parameters, MicropowerSCAD selects a circuit topology and offers you a selection of appropriate Linear Technology switching regulator ICs. MicropowerSCAD also performs circuit simulations to select the other components that surround the DC/ DC converter. See page 43 for ordering information for either LinearView or Micropower SwitcherCAD. As always, we welcome your questions and comments. Call (408) 432-1900 to talk to the authors of any of this issue’s articles about your application needs. Linear Technology Magazine • August 1996 DESIGN FEATURES they have stopped bouncing (Figure 2, time point 2), the LTC1421 will wait for 20ms. At the end of 20ms, if VCCLO and VCCHI have exceeded the undervoltage lockout threshold (2.45V), and VOUTLO is less than 100mV above ground, the LTC1421 is ready to turn on the supplies (Figure 2, time point 3). A 20µA reference current is connected to the RAMP pin, the charge R4 20k 5% Q3 1/2 Si4936DY C3 0.047µF Q2 1/2 Si4936DY R2 0.025 12V R1 0.005 5V VCC + 50mV – AUX VCC 20 VOUTLO 16 VOUTHI 17 GATEHI CHARGE PUMP N2 C5 220µF VEE –12V 1A VDD 12V 1A VCC 5V 5A C4 2200µF N1 + – + AUX VCC 21 GATELO 18 SETHI + 50mV – – AUXVCC 24 + C1 1.0µF 19 VCCHI 23 VCCLO 22 SETLO + R5 16k 5% C6 220µF + CRAMP 0.1µF Q1 MTB50N06E 10 RAMP –12V pacitors C4 and C5 is I = (CBYPASS × 20µA)/CRAMP. The internal charge pumps are designed to provide at least 8V of gate drive to Q1 and Q2. The negative supply voltage is controlled using the CPON pin. When the board first makes connection, transistor Q3 is turned off by R4 and C3. After the charge pump turns on, CPON is pulled to VCCLO and the gate of Q3 ramp up with a time constant determined by R4, R5 and C3. pumps turn on, CPON pulls high and the voltage at GATEHI begins to rise with a slope equal to 20µA/CRAMP. The voltage at the GATELO pin is clamped one Schottky diode drop below GATEHI. The ramp time for each supply is t = (VSUPPLY × CRAMP)/20µA. Because the N-channel transistors Q1 and Q2 act as source followers, the voltage at VOUTLO and VOUTHI have the same ramp rate. Therefore, the inrush current into the bypass ca- + Hot Swapping, continued from page 1 CP2 CP1 BOARD 73.5k – + 100mV – CP3 71.5k – BACKPLANE + UNDER VOLTAGE LOCKOUT CPON 9 11 FB 26.7k + CP4 D1 FAULT 4 20µA 20µA FAULT 6 PWRGD 20µA CON2 2 RESET TIMING POR 3 + CP5 GND 12 LTC1421 GND QS3384 1 BEA 13 BEB µP 7 RESET 15 COMPOUT – DISABLE 5 DATA BUS I/O DIGITAL CONTROL CON1 1 POR 8 REF 1.232V REFERENCE R3 1k 14 COMP – 13 COMP + RESET R8 10k 5% I/O R6 107k 1% R7 13.7k 1% DATA BUS VCC Figure 1. LTC1421 typical application Linear Technology Magazine • August 1996 3 DESIGN FEATURES As soon as VCCLO reaches the 4.65V reset threshold, (Figure 2, time point 4), the PWRGD signal immediately pulls high. After a 200ms delay, the RESET signal pulls high, (Figure 2, time point 6), and the DISABLE pin pulls low, thus enabling the system data bus. In this application, the free comparator, CP5, is used to monitor the 12V supply. When VOUTHI reaches 1 10.8V, the COMPOUT signal pulls high (Figure 2, time point 5). Monitoring The Supply Voltages The LTC1421 features a 1.232V reference, internal resistor divider from VCCLO and precision voltage comparators CP4 and CP5 (Figure 1) to monitor the supply voltages. The reset thresh- 2 3 4 5 old voltage for VOUTLO is determined by the FB pin connection as summarized in Table 1. When the VOUTLO voltage rises above its reset threshold voltage, the comparator (CP4) output goes low, and PWRGD is immediately pulled high to VCCLO by a weak pull-up current source or external resistor. After a 200ms delay, RESET is pulled high. 6 200ms 20ms VCCLO VCCHI DISABLE CON1 CON2 5V CPON –12V 10.8V VOUTHI 4.65V VOUTLO PWRGD RESET COMPOUT Figure 2. Typical insertion timing 4 Linear Technology Magazine • August 1996 DESIGN FEATURES 5V 12V 20 VOUTLO 16 VOUTHI VCCLO 73.5k 20µA CP4 71.5k – PWRGD 6 11 FB 10k 5% 107k 1% 26.7k + 15 COMPOUT VCCLO RESET TIMING + CP5 20µA RESET 7 13 COMP+ 14 COMP– – 8 1.232V 13.7k 1% REF LTC1421 Figure 3. Monitoring a 12V supply with a 10.8V threshold; the 5V supply generates a reset when it dips below 4.65V. The weak pull-up current sources to VCCLO on PWRGD and RESET have a series diode so the pins can be pulled above VCCLO by an external pull-up resistor without forcing current back into VCCLO. When VCCLO drops below its reset threshold, the comparator (CP4) output goes high, and PWRGD immediately pulls low. After a 64µs delay, RESET is pulled low. The RESET delay allows the PWRGD signal to be used as an early warning that a reset is about to occur. If the PWRGD signal is used as an interrupt input to a microprocessor, a short power-down routine can be run before the reset occurs. The uncommitted voltage comparator (CP5) can be used to monitor output voltages other than VOUTLO. Figure 3 shows how the comparator can be used to monitor a 12V supply with a 10.8V threshold, while the 5V 3.3V 5V 20 VOUTLO 16 VOUTHI VCCLO 73.5k 107k 1% 20µA CP4 71.5k – PWRGD 6 11 FB 26.7k 10k 5% + 15 COMPOUT supply generates a reset when it dips below 4.65V. The FB pin is left floating. Figure 4 shows how to monitor a 5V supply with a 4.65V threshold, while the 3.3V supply generates a reset when it dips below 2.9V. The FB pin is tied to VCCLO. Figure 5 shows how the comparator can be used to generate a reset when the 12V supply drops below 10.8V. The 5V supply also generates a reset when it dips below 4.65V. When 12V dips below 10.8V, COMPOUT will pull the FB pin low, setting the internal threshold voltage for CP5 to 5.88V. Since VOUTLO is less than 5.88V, PWRGD immediately goes low, followed by RESET 64µs later. Figure 6 shows how comparator CP5 can be used to override the internal reset voltage threshold. A 5k resistor is tied from the FB pin to VOUTLO, setting the internal threshold to about 2.9V. The new reset threshold voltage is set by the external resistor divider connected to CP5, in this case 4.5V. When VOUTLO drops below the new threshold voltage, COMPOUT pulls FB to ground, changing the internal threshold to 5.88V and generating a reset. Finally, Figure 7 shows how CP5 can be used to monitor a negative supply voltage. Electronic Circuit Breaker The LTC1421 features an electronic circuit-breaker function that protects against short circuits or excessive current on the supplies by placing sense resistors (R1 and R2) between the supply input and sense pin of either supply. The circuit breaker will be tripped whenever the voltage across the sense resistor is greater than 50mV for more than 20µs. When the VCCLO RESET 7 RESET TIMING + CP5 20µA 14 COMP– – 8 1.232V Table 1. Reset voltage thresholds 13 COMP+ 38.3k 1% REF LTC1421 Figure 4. Monitoring a 5V supply with a 4.65V threshold; the 3.3V supply generates a reset when it dips below 2.9V. Linear Technology Magazine • August 1996 Feedback Pin VOUTLO Reset Voltage Floating 4.65V VOUTLO 2.90V GND 5.88V 5 DESIGN FEATURES 73.5k 20µA CP4 PWRGD 6 71.5k 11 FB 107k 1% 26.7k 15 COMPOUT VCCLO CP5 20µA RESET 7 RESET TIMING 13 COMP+ 14 COMP– 13.7k 1% 8 REF 1.232V LTC1421 Figure 5. Generating a reset when the 12V supply drops below 10.8V; the 5V supply also generates a reset when it dips below 4.65V. Figure 9 shows the typical poweron reset cycle. After the POR pin is held low for 20ms, internal transistors N1 and N2 are turned on to start discharging VOUTLO and VOUTHI. At the same time, GATEHI and GATELO are also actively pulled down internally, while CPON goes low. When VOUTHI reaches the reset threshold, the COMPOUT pin pulls low (time point 3). When VOUTLO reaches the reset threshold, PWRGD immediately pulls low, followed by RESET 64µs later. When VOUTLO is discharged within 100mV of ground, the LTC1421 will reset and start a normal power-up sequence. 5V 20 VOUTLO 16 VOUTHI 12V VCCLO 73.5k 20µA CP4 PWRGD 6 71.5k – 11 FB 5k 5% 102k 1% 26.7k + 15 COMPOUT VCCLO CP5 20µA RESET 7 RESET TIMING + – The POR can be used to completely cycle the power supplies on the board or to reset the electronic circuitbreaker feature. The POR pin can be connected to a grounded push button or toggle switch, or to a logic signal from the backplane through the connector. VCCLO – Power-On Reset 16 VOUTHI + When a short circuit occurs on the board, it is possible to draw enough current to cause the backplane supply voltage to collapse to a low enough voltage that the LTC1421 gate drive circuitry is unable to shut off the N-channel pass transistors (Q1 and Q2). This could also happen if VCCLO breaks contact but VCCHI remains connected. To prevent the system from freezing up in a permanent short condition, the gate-discharge circuitry inside the LTC1421 is powered from the AUXVCC pin, which, in turn, is powered from VCCLO through an internal Schottky diode and current limiting resistor (Figure 8). When VCCLO collapses, there is enough energy stored on the 1.0µF capacitor connected to AUXVCC to keep the gate discharge circuitry alive long enough to fully turn off the external N-channels. 12V 20 VOUTLO + Auxiliary VCC 5.0V – circuit breaker trips, both N-channel transistors (Q1 and Q2) are immediately turned off and the FAULT pin is pulled low. When VCCLO drops below the 4.65V threshold, PWRGD is pulled low and RESET is pulled low 64µs later. The chip will remain in the tripped state until a power-on reset is generated, (pulling the POR pin low momentarily), or the power on VCCHI and VCCLO is cycled. If the circuit breaker feature is not used, VCCLO can be shorted to SETLO and VCCHI to SETHI. 13 COMP+ 14 COMP– 8 1.232V 38.3k 1% REF LTC1421 Authors can be contacted at (408) 432-1900 6 Figure 6. CP5 can be used to override the internal reset voltage threshold. A 5k resistor is tied from the FB pin to VOUTLO, setting the internal threshold to about 2.9V. The new reset threshold voltage is set by the external resistor divider connected to CP5. Linear Technology Magazine • August 1996 DESIGN FEATURES 5V VCCLO 20 VOUTLO 23 16 VOUTHI 12V VCCLO 10k 10k 5% 73.5k 21 20µA CP4 71.5k – PWRGD 6 AUXVCC 11 FB 24 GATE DRIVE CIRCUITRY 17 GATELO GATEHI 1.0µF 26.7k + LTC1421 15 COMPOUT VCCLO Figure 8. Auxiliary VCC circuitry RESET TIMING + CP5 20µA RESET 7 13 COMP+ Conclusion 14 COMP– With the explosion of systems requiring distributed power, the need for products that can be safely inserted into a live backplane has increased. Up to now, the design of the protection circuitry has required the talents of an analog guru, but with the LTC1421, safe hot swapping becomes as easy as hooking up an IC, a couple of power FETs and a handful of resistors and capacitors. – 8 REF 1.232V 13.7k 1% LTC1421 107k 1% –12V Figure 7. CP5 can be used to monitor a negative supply voltage. 1 2 3 4 20ms 5 6 7 8 64µs 9 200ms POR CPON VOUTHI 10.8V 10.8V VOUTLO 4.65V 4.65V 100mV PWRGD RESET COMPOUT Figure 9. LTC1421 typical power-on reset cycle Linear Technology Magazine • August 1996 7 DESIGN FEATURES The Care and Feeding of High Performance ADCs: Get All the Bits You Paid For by William C. Rempfer Introduction A new generation of ADCs currently appearing on the scene brings higher performance and lower cost to new markets. Figure 1 shows an example of how high speed 12-bit converters are becoming affordable for the first time to a new range of applications. At the same time, the new converters achieve better dynamic performance with high frequency input signals. All this means that more system designers are facing the challenge of using high performance ADCs. In this article, we will talk about some of the problems designers encounter, how to recognize their symptoms and how to avoid them. We will focus on the particular case of the LTC1410, a 1.25Msps, 12-bitADC. The same considerations become important in higher resolution ADCs at lower speeds. Conversely, lower resolution ADCs will need this same attention at higher speeds. input, but many. Ground pins, supply pins and reference pins also act as inputs and must be given special care to prevent noise and unwanted signals from corrupting the ADC output. Grounding, bypassing of the supplies and the reference and driving the analog and clock inputs are the major weapons in this battle against corruption. Ground Planes and Grounding Designing a high speed ADC system without using a proper ground is like trying to play basketball on a huge trampoline. No matter how well you mount the baskets to the court, the whole court will bounce and wobble as the players jump and try to shoot. To play the game, you must have a solid floor. Similarly, to give a solid Providing a clean analog input signal to an ADC doesn’t always guarantee a clean digital output signal. This is because an ADC has not just one LIST PRICE OF 12-BIT 1.25Msps ADCs 5V –5V An ADC Has Many Inputs 10µF 10µF 0.1µF 0.1µF AIN+ AIN– X X AVDD DVDD VSS REFCOMP XX XX AGND 10µF 0.1µF $100 ground for your data converter circuit, you must use an analog ground plane. This will put your circuit on a solid foundation. Figure 2 shows grounding techniques for the LTC1410, a 1.25Msps, 12-bit ADC. This provides an example that can be modified for the particular high performance converter used. All bypass caps, reference caps and ground connections for the ADC should be tied to the analog ground plane. Tie them as close together as possible to reduce the sensitivity to currents that may flow in the ground plane. The input signal circuitry, filter caps and op amp bypass caps (not shown) should also be grounded to the ground plane near the ADC. Noise from digital components in the system must be kept out of the analog ground. To do this, boards DIGITAL GROUND LTC1410 SO-28 ANALOG GROUND X OGND DIGITAL LOGIC SUPPLY D0-D3 V+ (LTC1410) DGND DIGITAL LOGIC X D4-D11 DGND 1988 1989 1990 1991 1992 1993 1994 1995 1996 X = VIA TO GROUND PLANE X INTRODUCTION YEAR Figure 1. High performance 1.25Mbps, 12-bit ADCs are becoming affordable to a new range of applications. More system designers will need to know how to use them effectively. 8 Figure 2. High performance ADC layout must have separate analog and digital ground planes, bypass caps with short connections and digital outputs routed away from the inputs. Linear Technology Magazine • August 1996 DESIGN FEATURES The high conversion rates of high performance converters require proper bypassing on the supply pins. The key to good bypassing is low lead inductance between the ADC and the bypass capacitors. The goal is to force AC currents to flow in the shortest possible loop from the supply pin through the bypass cap and back through ground to the ground pin. In Figure 2, the first components placed around the ADC are the bypass caps, which are located as close as possible to the supply pins. The capacitors must have low inductance and low equivalent series resistance (ESR). Tantalum 10µF surface mount devices are good if they are used in conjunction with 0.1µF ceramics. Even better are the new surface mount ceramic capacitors, which can be used alone. They come in values of 10µF or more and have ESR values as low as 20mΩ. Figure 3a shows the differential nonlinearity (DNL) of the LTC1410 with good supply bypassing. Figure 3b shows the effects of 2 inches of lead length (corresponding to roughly 60nH of inductance) in series with the supply bypass caps. This is an exaggerated case of poor bypassing layout, which causes the DNL to deLinear Technology Magazine • August 1996 DNL ERROR (LSBs) 0.5 0. –0.5 –1.0 0 512 1024 1536 2048 2560 OUTPUT CODE 3072 3584 4096 0 512 1024 1536 2048 2560 OUTPUT CODE 3072 3584 4096 0 512 1024 1536 2048 2560 OUTPUT CODE 3072 3584 4096 1.0 0.5 DNL ERROR (LSBs) Supply Bypassing 1.0 0. –0.5 –1.0 1.0 0.5 DNL ERROR (LSBs) should be designed with separate analog and digital ground planes, as shown in Figure 2. (The figure shows a 2-layer board layout. If more layers are available, separate layers may be used for analog and digital ground planes.) All noisy digital logic devices must be on the digital ground plane. All the grounds and bypass caps of the ADC (even the digital ones) should tie to the analog ground plane. Tie the two ground planes together at only one point to keep digital currents from taking shortcuts through the analog ground. The ideal connection point is the ground pin for the ADC output drivers (or the digital ground pin). If that is not possible, a different connection point can be used (for example, at the power supply). In any case, be sure to use only a single connection point. 0. –0.5 –1.0 Figure 3. Poor layout will degrade the differential nonlinearity (DNL) of fast ADCs: a. (top) a clean LTC1410 layout with bypass cap wires of less than 0.5 inch; b. (middle) 2-inch wires to supply-bypass caps; c. (bottom) a wire of more than 2 inches to the reference-bypass cap. 9 DESIGN FEATURES grade beyond 1LSB, reducing the accuracy to 11 bits. For best performance, use supply bypass leads of less than one-half inch. A little care pays off with excellent performance. Reference Bypassing The analog reference input provides the scale factor for the conversion. For a clean data output the reference must be stable. Dynamic currents pulled from the reference by the ADC as it converts perturb the reference unless it is properly bypassed. Surface mount tantalum or ceramic capacitors provide good results. They should be located near the reference pin and should be grounded very near the ADC analog ground pin, as shown in Figure 2. Figure 3c shows the easily recognizable signature of a reference bypassing problem—a bow-tie shape to the error curve. This occurs because reference perturbations feed in with full strength for inputs near plus or minus full scale but have less effect for inputs near zero scale. This degradation in DNL results from several inches of lead length in series with the reference bypass cap. Once again, this is an exaggerated case to make the consequences of poor bypassing more visible. To maintain high accuracy, keep the lead lengths less than half an inch. Driving the Analog Input Switched Capacitor Inputs The inputs to switched capacitor ADCs are easy to drive if you allow for the fact that they draw a small inputcurrent transient at the end of each conversion. This happens when the internal sampling capacitors switch back onto the input to acquire the next sample. For accurate results, the circuitry driving the analog input must settle from this transient before the next conversion is started. There are two ways to accomplish this. One is to drive the ADC with an op amp that settles from a load transient in less than the acquisition time of the ADC. Fortunately, most op amps settle much more quickly from 10 a load transient than from an input step, so meeting this requirement is not too difficult. The LT1363, for example, is a good choice for driving the LTC1410 input. A second solution to handling the input transient is to use an input RC filter with a capacitor much larger than the ADC input capacitance. This larger capacitor provides the charge for the sampling capacitor, which eliminates the voltage transient altogether. Figure 4 shows such a filter for the LTC1410. The 1000pF capacitor provides the input charge for the ADC’s sampling capacitor. The LT1363’s capacitive load driving capability makes it a good choice for use with this filter. Filter Wideband Noise from the Input Signal Many new converters have wide S/H input bandwidths. This is great for capturing high frequency input signals, but for lower input bandwidth applications the converter will pick up any wideband noise that may be in the input signal. To avoid this, use a filter at the ADC input to pass only your desired signal bandwidth. The simple filter in Figure 4 bandlimits the input signal to 3MHz and still allows clean sampling up to the Nyquist frequency (625kHz). Figure 7a shows the Nyquist performance of the LTC1410 using this filter. The signal to noise and distortion ratio (SINAD) is 71.5dB and total harmonic distortion (THD) is –84dB. Choosing an Op Amp To drive high performance ADCs, you will need a high performance op amp. The noise and distortion of good ADCs are now so low that they no longer mask the performance of the op amp. This adds another tradeoff to op amp selection. High speed, current feedback op amps have lower DC precision and don’t settle as well to high accuracy (for example, 0.01%) as the voltage feedback types. However, they have the best distortion and drive for high speed AC frequency domain applications. Figure 5a shows the FFT result of an LT1227 current feedback amp driving a 172kHz signal into the LTC1410. The distortion (THD) of –82dB is about 3dB worse than the –85dB of the ADC alone. High speed voltage feedback amplifiers have better precision and settling. They work well in frequency domain applications but are best suited for high speed, time domain or multiplexed applications where their DC precision and settling are required. Figure 5b shows the voltage feedback LT1363’s 2dB further degradation in distortion (to –80dB) under the same conditions. Slower op amps like the OP-27/ OP-37 are excellent in noise and precision but are simply not fast enough for high frequency applications. They distort as they are pushed beyond their slewing capabilities (as shown in the FFT plot of Figure 5c). Driving the Convert-Start Input An improperly driven conversion-start input can create conversion errors in a couple of ways. First, if an ADC has internal timing, the returning edge of the convert signal (the opposite edge LTC1410 ±2.5V INPUT + 50Ω AIN+ LT1363 – 1000pF 20MHz S/H AIN– ADC AGND Figure 4. Many new ADCs have wide-bandwidth sample-and-holds. In lower bandwidth applications, a simple RC filter will remove wideband noise that may be present in the input signal. Linear Technology Magazine • August 1996 DESIGN FEATURES 0 FSAMPLE = 1.25Msps FIN = 172kHz THD = 82.6dB –20 AMPLITUDE (dB) –40 –60 –80 –100 –120 0 100K 200K 300K 400K INPUT FREQUENCY (Hz) 500K 600K 0 FSAMPLE = 1.25Msps FIN = 172kHz THD = 80.9dB –20 AMPLITUDE (dB) –40 –60 –80 –100 –120 0 100K 200K 300K 400K INPUT FREQUENCY (Hz) 500K 600K 0 FSAMPLE = 1.25Msps FIN = 172kHz THD = 26.6dB –20 AMPLITUDE (dB) –40 –60 from the one that starts the conversion) can couple noise into the converter if it occurs during the conversion time. To avoid this, use a narrow pulse for convert-start instead of a square wave. This ensures that it either returns quickly (after the sample is taken but before the conversion gets underway), or returns after the conversion is over. (This does not apply to those ADCs that draw all their timing from a clock input and require precise 50% dutycycle clock inputs.) A convert-start signal that overshoots or rings can also degrade performance. If it overshoots beyond the supply rails it can turn on the ADC’s input protection diodes and couple noise into the converter. If it rings, it may still be bouncing around as the ADC’s sample-and-hold captures the input signal, which can affect the conversion result. Normally, overshoot and ringing are not a problem with high speed CMOS logic on a well designed board but they are still things to watch out for. High frequency or high slew rate input signals impose another requirement on the ADC: low aperture jitter. Aperture jitter is the variation in the ADC’s aperture delay from conversion to conversion and results in an uncertainty in the time when the input sample is taken. Figure 6 shows how this jitter causes an equivalent input noise by working against the slew rate of the analog input signal. The faster the input signal slew rate, the worse the noise for a given jitter. The best possible SINAD for an ADC is limited by the jitter according to the formula: SINAD(dB) ≤ 20log[1/(2π × tJITTER(RMS) × fINPUT)] –80 where: tJITTER(RMS) = the RMS jitter in seconds –100 –120 fINPUT = the analog input frequency in Hz 0 100K 200K 300K 400K INPUT FREQUENCY (Hz) 500K 600K Figure 5. Op amp selection is important when an ADC has low distortion levels. a. (top) Current feedback op amps such as the LT1227 (seen here driving the LTC1410) provide the lowest THD in the FFT output; b. (middle) Fast voltage feedback op amps do nearly as well in THD as current feedback amps and offer better precision; c. (bottom) slower op amps pushed beyond their slew limits will severely distort fast signals. Linear Technology Magazine • August 1996 The LTC1410’s 5ps (RMS) aperture jitter allows clean sampling of inputs far beyond the Nyquist frequency. However, to achieve this performance, the convert-start input signal applied to the ADC must also have low jitter. Figure 7a shows the 11 DESIGN FEATURES 0 FSAMPLE = 1.25Msps WITH NO JITTER FIN = 600kHz SINAD = 71.5dB –20 –40 AMPLITUDE (dB) ADC, driven from a low jitter source, capturing a 600kHz input with 71.5dB SINAD. As Figure 7b shows, adding 70ps of jitter to the conversion-start input signal will raise the noise floor, and reduce the SINAD, by 3dB. If generating a lower jitter signal is a problem, one trick is to start with a higher frequency clock, which will usually have lower jitter, and then divide the frequency down with fast logic (which retains the lower jitter) to get the desired sample clock. –60 –80 –100 Routing the Data Outputs –120 0K 100K 200K 300K 400K INPUT FREQUENCY (Hz) 500K 600K 500K 600K 0 FSAMPLE = 1.25Msps WITH 70ps (RMS) JITTER FIN = 600kHz SINAD = 68.5dB –20 –40 AMPLITUDE (dB) One of the worst potential sources of digital noise and coupling in an ADC is its output data bus. Fortunately, the user can control this with proper board layout. First, to prevent the data outputs of the ADC from capacitively coupling to the analog input circuitry, they should be routed in the opposite direction. This will naturally occur if separate digital and analog ground plane layouts are used, as in Figure 2. Second, the digital –60 –80 IDEAL SAMPLING INSTANT ADC CONVERSION START SIGNAL –100 –120 ADC ANALOG INPUT SIGNAL 0 100K 200K 300K 400K INPUT FREQUENCY (Hz) Figure 7. Jitter in the conversion signal creates noise: a. (top) with a low jitter source, the LTC1410 will give 71.5dB SINAD when sampling a Nyquist input signal; b. (bottom) adding 70ps of jitter to the convert-start signal will raise the noise floor by 3dB to 68.5dB. EFFECTIVE NOISE DUE TO APERTURE JITTER ∆V ∆t APERTURE JITTER Figure 6. Aperture jitter in a sampling ADC or jitter in the conversion-start signal applied to the ADC can degrade its noise performance. The time jitter works against the slope of the analog input signal to generate an effective noise voltage that appears in the ADC’s output spectrum. 12 output drivers in the ADC switch quickly and will create large current transients if they are loaded with too much capacitance. Locating the receiving buffers or latches close to the ADC will minimize loading. Although reduced, some capacitive currents still flow, and it is important to control their return path to the driver of the ADC. Starting from the output drivers of the ADC, the current goes through the output lines, charges the input capacitance of the receiving latches or buffers, and returns through the digital ground plane to the ADC’s output driver. For a falling edge, this current returns into the output driver ground pin. For a rising edge, it returns to the ground point of the output driver’s supplybypass cap. Tying the digital and analog grounds together at the ADC output driver ground pin (as in Figure 2) helps prevent this current from flowing across the analog ground plane. If the grounds must be tied at the power supply instead of at the ADC, the return currents will flow through the analog ground plane. In this case, it is especially important to minimize these currents by minimizing the capacitance on the digital outputs. Linear Technology Magazine • August 1996 DESIGN FEATURES LTC1433/LTC1434: High Efficiency, Constant-Frequency Monolithic Buck Converter by San-Hwa Chee In portable communications products where high efficiency and constant frequency operation are prime requirements, the LTC1433 and LTC1434 are a perfect fit. These two new devices are packed with features but still fit in a small footprint. The LTC1433 comes in a 16-pin narrow SSOP, whereas the LTC1434 comes in a 20-pin narrow SSOP. The LTC1434 provides an additional feature that allows the device to be synchronized with an external clock through its internal PLL. High efficiency and constant frequency at low load current are achieved by using the new Adaptive Power™ output stage, first introduced in the LTC1435–LTC1439 DC/DC controllers (“New LTC1435–LT1439 DC/DC Controllers Feature Value and Performance”; Linear Technology VI:1 (February 1996)). The LTC1433 and LTC1434 combine Adaptive Power operation with internal power MOSFETs for the first time, with operating frequency programmable up to 500kHz by means of a single external capacitor. What is Adaptive Power With no load, the devices require Mode Operation? only 470µA of quiescent current, which drops to 15µA in full shutdown. In dropout conditions, the internal 0.6Ω (at an input supply of 10V) power P-channel MOSFET switch is turned on continuously (DC), thereby maximizing the life of the battery source. In the event of an output short circuit, the oscillator frequency is reduced by a factor of 4.5 to prevent inductor-current runaway. In addition, an internal sense resistor limits the switch current to 1.2A. Both devices contain a low-battery detector and a power-on reset (POR) timer that generates a signal delayed by 65,536 oscillator clock cycles after the output is within 5% of regulated output voltage. A soft-start pin allows the LTC1433/LTC1434 to power up gently and also serves as a shutdown pin. For maximum flexibility, internal resistive feedback dividers are selectable via programming pins for 3.3V or 5V, or can be configured with an adjustable output voltage to meet any requirement. Both devices function down to an input voltage of 3.5V and up to an absolute maximum of 13.5V. The LTC1433/LTC1434 have two internal P-channel MOSFETs of different sizes, with each drain bonded out separately. To maximize efficiency, only the smaller sized P-channel MOSFET is switched on and off at low load currents. This reduces gatecharge losses without changing the operating frequency. At higher load currents, both MOSFETs are switched, since losses due to drops across the FETs are more significant than gate-charge losses. The 100 VIN = 5V 90 EFFICIENCY (%) Introduction 80 VIN = 12V VIN = 9V 70 60 50 40 0.001 0.01 0.10 1.00 LOAD CURRENT (A) Figure 2. Efficiency versus load current for Figure 1’s circuit BSW L1 0.1µF * MBRS130LT3 ** COILCRAFT DO3316-104 † AVX TPSD107M010R0100 †† AVX TPSE686M020R0150 LTC1433 LTC1434 68µF†† 20V SSW + D1 100µH L1** VOUT 3.3V + D1* † 100µF 10V 1 SSW 2 NC 3 BSW PWRVIN 16 PGND 15 SVIN 14 13 C LTC1433 OSC 5 SGND POR 12 6 RUN/SS ITH 11 INPUT VOLTAGE 3.6V TO 12V Figure 3. Single-inductor configuration 10kΩ L1 4 NC 0.1µF 7 LBO 8 LBI VOSENSE 10 VPROG 9 BSW POWER ON RESET 680pF 5.1kΩ 47pF 6800pF LTC1433 LTC1434 D1 L2 SSW D2 Figure 1. Typical application using the LTC1433 Linear Technology Magazine • August 1996 Figure 4. Dual-inductor configuration 13 DESIGN FEATURES 100 3.4 3.3 VIN = 5V 5.0 3.2 70 VOUT = 3.3V COSC = 47pF VIN = 9V 60 ONE 22 µH INDUCTOR ON SSW & BSW 100 µH ON SSW 22 µH ON BSW SOLID LINE 50 DOTTED LINE 40 0.001 0.01 0.10 3.1 3.0 2.9 IOUT = 400mA 2.8 2.7 2.6 VPROG = 0V COSC = 50pF L = 20µH IOUT = 500mA 2.5 2.4 3.2 1.00 IOUT = 200mA 4.9 OUTPUT VOLTAGE (V) 80 OUTPUT VOLTAGE (V) EFFICIENCY (%) 90 5.1 IOUT = 300mA 4.8 4.7 IOUT = 300mA 4.6 4.5 4.4 VPROG = VIN COSC = 50pF L = 20µH IOUT = 400mA 4.3 4.2 3.6 4.0 4.4 4.8 5.2 4.6 SUPPLY VOLTAGE (V) LOAD CURRENT (A) 4.8 5.2 5.0 5.4 5.6 5.8 6.0 6.2 SUPPLY VOLTAGE (V) Figure 5. Efficiency comparison between single- and dual-inductor configurations Figure 6. Dropout characteristics at different load currents for VOUT = 3.3V Figure 7. Dropout characteristics at different load currents for VOUT = 5.0V LTC1433/LTC1434 monitor two conditions to determine when to switch to low current mode: inductor current and error amplifier output voltage (on the ITH pin). If the peak current of the inductor does not exceed 260mA and the voltage at the ITH pin does not exceed 0.6V, the small MOSFET will be used. When either one of the conditions is exceeded, the large MOSFET will be used on the next clock cycle. works all the way down to 3.6V at a load current of 250mA before dropping out and the oscillator frequency is a constant 210kHz down to 20mA load current. current rating. As can be seen from Figure 5, the average efficiency gain over the region where the small P-channel is ON is about 3%. Hence, the dual inductor configuration is good for applications that require maximum efficiency at low load currents, while retaining constantfrequency operation. Efficiency Figure 1 shows a practical LTC1433 circuit that can be used for cellular telephone applications. Efficiency curves for this circuit at various input voltages are shown in Figure 2. Note that the efficiency reaches 93% at a supply voltage of 5V and a load current of about 150mA. This high efficiency makes the LTC1433 and LTC1434 attractive for all other powersensitive applications. The circuit Efficiency Considerations Since there are two separate pins for the drains of the small and large P-channel switches, we could use two inductors to further enhance the efficiency of the regulator over the low current range. Figures 3 and 4 show the single-inductor and dual-inductor circuit configurations, respectively. To reduce core losses, a higher value inductor can be used on the small P-channel switch. Since this switch only carries a small part of the overall current, the user can still specify a small physical size inductor without sacrificing on copper losses. The Schottky on the small P-channel drain (SSW) can also be chosen with a lower 100% Duty Cycle in Dropout When the input voltage decreases, the inductor’s ripple current starts to decrease and the duty cycle increases to provide the required output current. Further decrease in input voltage will eventually cause the ITH voltage to be at its maximum limit. Any decrease in input voltage from this point will result in the P-channel switch being turned on continuously. The dropout voltage, VIN – VOUT, is governed by the switch resistance, load current and the voltage drop across continued on page 42 * MOTOROLA MBRS130LT3 ** COILCRAFT DO3316 SERIES † AVX TPSD107M010R0100 †† AVX TPSE107M016R0100 + VOUT –5.0V VIN (V) 14 IOUT MAX (mA) 3.0 180 4.0 240 5.0 290 6.0 340 7.0 410 7.5 420 L1** 68µH 100µF† 10V D1* 0.01µF 1 SSW 2 NC 3 BSW 4 NC 5 SGND 6 RUN/SS 7 LBO 8 LBI LTC1433 PWRVIN 16 PGND 15 SVIN 14 COSC 13 POR 12 ITH 11 VOSENSE 10 VPROG INPUT VOLTAGE 3V TO 7.5V 100µF†† 16V 100pF + 0.1µF 6800pF 9 680pF 5.1kΩ Figure 8. Positive-to-negative (–5.0V) converter Linear Technology Magazine • August 1996 DESIGN FEATURES The LTC1343 and LTC1344 Form a Software-Selectable Multiple-Protocol Interface Port Using a DB-25 Connector by Robert Reay Introduction With the explosive growth in data networking equipment has come the need to support many different serial protocols using only one connector. The problem facing interface designers is to make the circuitry for each serial protocol share the same connector pins without introducing conflicts. The main source of frustration is that each serial protocol requires a different line termination that is not easily or cheaply switched. With the introduction of the LTC1343 and LTC1344, a complete software-selectable serial interface port using an inexpensive DB-25 connector becomes possible. The chips form a serial interface port that supports the V.28 (RS232), V.35, V.36, RS449, EIA-530, EIA-530A or X.21 protocols in either DTE or DCE mode CTS DSR DCD and is both NET1 and NET2 compliant. The port runs from a single 5V supply and supports an echoed clock and loop-back configuration that helps eliminate glue logic between the serial controller and the line transceivers. A typical application is shown in Figure 1. Two LTC1343s and one LTC1344 form the interface port using a DB-25 connector, shown here in DTE mode. Each LTC1343 contains four drivers and four receivers and the LTC1344 contains six switchable resistive terminators. The first LTC1343 is connected to the clock and data signal lines along with the diagnostic LL (local loop-back) and TM (test mode) signals. The second LTC1343 is connected to the control- DTR RTS RL D3 D2 D1 TM RXD RXC TXC D4 R3 R2 Review of Interface Standards The serial interface standards RS232, EIA-530, EIA-530A, RS449, V.35, V.36 and X.21 specify the function of each signal line, the electrical characteristics of each signal, the connector type, SCTE TXD LL D3 D2 D1 LTC1343 LTC1343 R4 signal lines along with the diagnostic RL (remote loop-back) signal. The single-ended driver and receiver could be separated to support the RI (ringindicate) signal. The switchable line terminators in the LTC1344 are connected only to the high speed clock and data signals. When the interface protocol is changed via the digital mode selection pins (not shown), the drivers and receivers are automatically reconfigured and the appropriate line terminators are connected. D4 R1 R3 R4 R1 R2 LTC1344 13 5 22 6 10 8 23 20 19 4 21 1 7 25 16 3 9 17 12 15 11 24 14 2 18 LL A (141) TXD A (103) TXD B SCTE A (113) SCTE B TXC A (114) TXC B RXC A (115) RXC B RXD A (104) RXD B TM A (142) SGND (102) SHIELD (101) RTS A (105) RL A (140) RTS B DTR A (108) DTR B DCD A (109) DCD B DSR A (107) CTS A (106) DSR B CTS B DB-25 CONNECTOR Figure 1. LTC1343/LTC1344 typical application Linear Technology Magazine • August 1996 15 DESIGN FEATURES A' A BALANCED INTERCONNECTING CABLE GENERATOR R1 51.5Ω LOAD CABLE TERMINATION S1 RECEIVER LTC1343 R8 6k R2 51.5Ω B' V.10 (RS423) Interface A typical V.10 unbalanced interface is shown in Figure 2. A V.10 singleended generator (output A with ground C) is connected to a differential receiver with input A' connected to A and input B' connected to the signalreturn ground C. The receiver’s R7 10k GND Figure 3. V.10 receiver configuration Figure 2. Typical V.10 interface the transmission rate and the data exchange protocols. The RS422 (V.11) and RS423 (V.10) standards merely define electrical characteristics. The RS232 (V.28) and V.35 standards also specify their own electrical characteristics. In general, the US standards start with RS or EIA, and the equivalent European standards start with V or X. The characteristics of each interface are summarized in Table 1. Table 1 shows only the most commonly used signal lines. Note that each signal line must conform to only one of four electrical standards, V.10, V.11, V.28 or V.35. RECEIVER S4 C' C' R6 10k R4 20k B B' C R5 20k S3 R3 124Ω S2 A' A LTC1344 ground C' is separate from the signal return. Usually, no cable termination between A' and B' is required for V.10 interfaces. The V.10 receiver configuration for the LTC1343 and LTC1344 is shown in Figure 3. With the introduction of the LTC1343 and LTC1344, a complete softwareselectable serial interface port using an inexpensive DB-25 connector becomes possible. The chips form a serial interface port that supports a wide variety of standards. In V.10 mode, switches S1 and S2 inside the LTC1344 and S3 inside the LTC1343 are turned off. Switch S4 inside the LTC1343 shorts the noninverting receiver input to ground so the B input at the connector can be left floating. The cable termination is then the 30k input impedance to the ground of the LTC1343 V.10 receiver. V.11 (RS422) Interface A typical V.11 balanced interface is shown in Figure 4. A V.11 differential generator with outputs A and B and ground C is connected to a differential receiver with ground C', input A' connected to A and input B' connected to B. The V.11 interface has a differential termination at the receiver end with a minimum value of 100Ω. The termination resistor is optional in the V.11 specification, but for the high speed clock and data lines, the termination is required to prevent reflections from corrupting the data. In V.11 mode, all switches are off except S1 inside the LTC1344, which connects a 103Ω differential termination impedance to the cable, as shown in Figure 5. Table 1. Interface summary Clock and Data Signals Control Signals Test Signals TXD SCTE TXC RXC RXD RTS DTR DSR DCD CTS RI LL RL TM CCITT# (103) (113) (114) (115) (104) (105) (108) (107) (109) (106) (125) (141) (140) (142) RS232 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 EIA-530 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 — V.10 V.10 V.10 EIA-530A V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 V.11 V.11 V.10 V.10 V.10 V.10 RS449 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 V.10 V.10 V.35 V.35 V.35 V.35 V.35 V.35 V.28 — V.28 V.28 V.28 — — — — V.36 V.11 V.11 V.11 V.11 V.11 V.11 — V.11 V.11 V.11 — V.10 V.10 V.10 X.21 V.11 V.11 V.11 V.11 V.11 V.11 — — V.11 — — — — — 16 Linear Technology Magazine • August 1996 DESIGN FEATURES A' BALANCED INTERCONNECTING CABLE GENERATOR A LOAD CABLE TERMINATION R1 51.5Ω S1 100Ω MIN R2 51.5Ω C' C R5 20k R6 10k S3 R3 124Ω S2 B' B R8 6k RECEIVER A' A LTC1343 LTC1344 B' Figure 4. Typical V.11 interface R7 10k R4 20k B RECEIVER S4 C' GND Figure 7. V.28 receiver configuration A' A R1 51.5Ω LTC1344 R8 6k S2 R2 51.5Ω 50Ω R7 10k R4 20k B B' 125Ω 125Ω 50Ω GND B B' C C' A' A R1 51.5Ω BALANCED INTERCONNECTING CABLE LTC1343 LTC1344 R8 6k S1 S2 RECEIVER R7 10k R4 20k B B' S4 C' C' RECEIVER S3 R3 124Ω R2 51.5Ω A' C R5 20k R6 10k LOAD CABLE TERMINATION A 50Ω Figure 8. Typical V.35 interface Figure 5. V.11 receiver configuration GENERATOR RECEIVER 50Ω S4 C' CABLE TERMINATION A' A RECEIVER S3 R3 124Ω BALANCED INTERCONNECTING CABLE GENERATOR R5 20k R6 10k S1 LOAD LTC1343 GND Figure 6. Typical V.28 interface Figure 9. V.35 receiver configuration Table 2. LTC1343/LTC1344 mode selection M2 M1 M0 CTRL/ CLK D1 D2 D3 D4 R1 R2 R3 R4 V.10/RS423 0 0 0 X V.10 V.10 V.10 V.10 V.10 V.10 V.10 V.10 RS530A clock & data 0 0 1 0 V.10 V.11 V.11 V.11 V.11 V.11 V.11 V.10 RS530A control 0 0 1 1 V.10 V.11 V.10 V.11 V.11 V.10 V.11 V.10 Reserved 0 1 0 X V.10 V.11 V.11 V.11 V.11 V.11 V.11 V.10 X.21 0 1 1 X V.10 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.35 clock & data 1 0 0 0 V.28 V.35 V.35 V.35 V.35 V.35 V.35 V.28 V.35 control 1 0 0 1 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 RS530/RS449/V.36 1 0 1 X V.10 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.28/RS232 1 1 0 X V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 No Cable 1 1 1 X Z Z Z Z Z Z Z Z LTC1343 Mode Name Linear Technology Magazine • August 1996 17 DESIGN FEATURES A 51.5Ω LATCH S2 ON LTC1344 S1 ON DCE/ DTE M2 22 23 M1 M0 (DATA) 24 1 51.5Ω CONNECTOR (DATA) B C1 100pF R1, 10k LTC1343 M0 C 17 R2, 10k 20 Figure 10. V.35 driver using the LTC1344 M1 CTRL/CLK 18 R3, 10k 22 M2 LATCH 19 A typical V.28 unbalanced interface is shown in Figure 6. A V.28 singleended generator (output A with ground C) is connected to a single-ended receiver with input A' connected to A and ground C' connected via the signal return ground to C. In V.28 mode, all switches are off except S3 inside the LTC1343, which connects a 6k impedance (R8) to ground in parallel with 20k (R5) plus 10k (R6), for an combined impedance of 5k, as shown in Figure 7. The noninverting input is disconnected inside the LTC1343 receiver and connected to a TTL level reference voltage for a 1.4V receiver trip point. DCE/DTE VCC VCC NC R4, 10k V.28 (RS232) Interface VCC 21 VCC NC CABLE LTC1343 DCE/DTE M2 VCC 20 22 CTRL/CLK M1 LATCH M0 21 19 18 17 (DATA) Figure 11. Mode selection by cable PORT #1 M0 M1 V.35 Interface A typical V.35 balanced interface is shown in Figure 8. A V.35 differential generator with outputs A and B and ground C is connected to a differential receiver with ground C', input A' connected to A and input B' connected to B. The V.35 interface requires T or delta network termination at the receiver end and the generator end. The receiver differential impedance measured at the connector must be 100 ±10Ω, and the impedance between shorted terminals (A' and B') and ground (C') is 150 ±15Ω. In V.35 mode, both switches S1 and S2 inside the LTC1344 are on, connecting the T-network impedance, as shown in Figure 9. Both switches in the LTC1343 are off. The 30k input impedance of the receiver is placed in parallel with the T-network termination, but does not affect the overall input impedance significantly. 18 M2 DCE/DTE CONNECTOR #1 124Ω 21 LATCH PORT #2 M0 M1 M2 DCE/DTE CONTROLLER CONNECTOR #2 V.35 DRIVER LATCH PORT #3 M0 M0 M1 M1 M2 M2 DCE/DTE DCE/DTE LATCH 1 CONNECTOR #3 LTC1344 LATCH 2 LATCH 3 LATCH Figure 12. Mode selection by controller Linear Technology Magazine • August 1996 DESIGN FEATURES SERIAL CONTROLLER LL LTC1343 LTC1344 D1 R4 SERIAL CONTROLLER LL LTC1344 LL LL LTC1343 TXD D2 TXD TXD 103Ω R3 TXD SCTE D3 SCTE SCTE 103Ω R2 SCTE D4 R1 RXD D2 RXD TM R4 TM TM D1 TM 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 0 1 LTC1343 LATCH RXD EC 103Ω LB R3 DCE/DTE RXD CTRL/CLK RXC M2 D3 M1 RXC M0 RXC M0 M1 M2 DCE/DTE LATCH 103Ω M0 M1 M2 DCE/DTE LATCH R2 LATCH RXC EC TXC LB D4 DCE/DTE TXC CTRL/CLK TXC M2 103Ω M1 R1 M0 TXC 0 1 0 1 0 LTC1343 RL RL D1 RTS D2 RTS DTR D3 DTR RL R4 RL RTS R3 RTS DTR R2 DTR D4 R1 D2 CTS RI R4 RI RI D1 RI LATCH CTS EC CTS LB R3 DCE/DTE CTS CTRL/CLK DSR M2 D3 M1 DSR M0 DSR LATCH R2 EC DSR LB DCD DCE/DTE D4 CTRL/CLK DCD M2 DCD M1 R1 M0 DCD 1 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 Figure 13. Normal DTE Loop-back The generator differential impedance must be 50Ω to 150Ω, and the impedance between shorted terminals (A and B) and ground (C) is 150Ω ±15Ω. For the generator termination, switches S1 and S2 are both on and the top side of the center resistor is brought out to a pin so it can be bypassed with an external capacitor to reduce common mode noise, as shown in Figure 10. Linear Technology Magazine • August 1996 Figure 14. Normal DCE loop-back Any mismatch in the driver rise and fall times or skew in driver propagation delays will force current through the center termination resistor to ground, causing a high frequency common mode spike on the A and B terminals. This spike can cause EMI problems that are reduced by capacitor C1, which shunts much of the common mode energy to ground rather than down the cable. LTC1343/LTC1344 Mode Selection The interface protocol is selected using the mode select pins M0, M1, M2 and CTRL/CLK, as summarized in Table 2. The CTRL/CLK pin should be pulled high if the LTC1343 is being used to generate control signals and pulled low if used to generate clock and data signals. 19 DESIGN FEATURES For example, if the port is configured as a V.35 interface, the mode selection pins should be M2 = 1, M1 = 0, M0 = 0. For the control signals, CTRL/CLK = 1 and the drivers and receivers will operate in RS232 (V.28) electrical mode. For the clock and data signals, CTRL/CLK = 0 and the drivers and receivers will operate in V.35 electrical mode, except for the single-ended driver and receiver, which will operate in the RS232 (V.28) electrical mode. The DCE/DTE pin will configure the port for DCE mode when high, and DTE when low. The interface protocol may be selected by simply plugging the appropriate interface cable into the connector. The mode pins are routed to the connector and are left unconnected (1) or wired to ground (0) in the cable, as shown in Figure 11. The pull-up resistors R1–R4 ensure a binary 1 when a pin is left unconnected and also ensure that the two LTC1343s and the LTC1344 enter the no-cable mode when the cable is removed. In the no-cable mode, the LTC1343 power supply current drops to less than 200µA and all LTC1343 driver outputs and LTC1344 resistive terminators are forced into a high impedance state. Note that the data latch pin, LATCH, is shorted to ground for all chips. The interface protocol may also be selected by the serial controller or host microprocessor, as shown in Figure 12. The mode selection pins M0, M1, M2 and DCE/DTE can be shared among multiple interface ports, while each port has a unique data-latch signal that acts as a write enable. When the LATCH pin is low, the buffers on the MO, M1, M2, CTRL/CLK, DCE/DTE, LB and EC pins are transparent. When the LATCH pin is pulled high, the buffers latch the data, and changes on the input pins will no longer affect the chip. The mode selection may also be accomplished by using jumpers to connect the mode pins to ground or VCC. 20 LTC1343 5 DCE/DTE D1 21 16 VCC 39 20 24 R4 26 CTRL/CLK EC Figure 15. Single-ended driver and receiver enable Loop-Back The LTC1343 contains logic for placing the interface into a loop-back configuration for testing. Both DTE and DCE loop-back configurations are supported. Figure 13 shows a complete DTE interface in the loopback configuration and Figure 14 the DCE loop-back configuration. The loop-back configuration is selected by pulling the LB pin low. Enabling the Single-Ended Driver and Receiver When the LTC1343 is being used to generate the control signals (CTRL/ CLK = high) and the EC pin is pulled low, the DCE/DTE pin becomes an enable for driver 1 and receiver 4 so their inputs and outputs can be tied together, as shown in Figure 15. The EC pin has no affect on the configuration when CTRL/CLK is high except to allow the DCE/DTE pin to become an enable. When DCE/DTE is low, the driver 1 output is enabled. The receiver 4 output goes into threestate, and the input presents a 30k load to ground. When DCE/DTE is high, the driver 1 output goes into three-state, and the receiver 4 output is enabled. The receiver 4 input presents a 30k load to ground in all modes except when configured for RS232 operation, when the input impedance is 5k to ground. Multiprotocol Interface with DB-25 or µDB-26 Connectors A multiprotocol serial interface with a standard DB-25 connector EIA-530 pin configuration is shown in Figure 16. [Figures 16–19 follow on pp. 21– 24]. The signal lines must be reversed in the cable when switching between DTE and DCE using the same connector. For example, in DTE mode, the RXD signal is routed to receiver 3, but in DCE mode, the TXD signal is routed to receiver 3. The interface mode is selected by logic outputs from the controller or from jumpers to either VCC or GND on the mode-select pins. The single-ended driver 1 and receiver 4 of the control chip share the RL signal on connector pin 21. With EC low and CTRL/CLK high, the DCE/DTE pin becomes an enable signal. Single-ended receiver 4 can be connected to pin 22 to implement the RI (ring indicate) signal in RS232 mode (see Figure 17). In all other modes, pin 22 carries the DSR(B) signal. A cable selectable multiprotocol interface is shown in Figure 18. Control signals LL, RL and TM are not implemented. The VCC supply and select lines M0 and M1 are brought out to the connector. The mode is selected in the cable by wiring M0 (connector pin 18) and M1 (connector pin 21) and DCE/DTE (connector pin 25) to ground (connector pin 7) or letting them float. If M0, M1 or DCE/ DTE are floating, pull-up resistors R3, R4 and R5 will pull the signals to VCC. The select bit M1 is hard wired to VCC. When the cable is pulled out, the interface goes into the no-cable mode. A cable-selectable multiprotocol interface found in many popular data routers is shown in Figure 19. The entire interface, including the LL signal, can be implemented using the tiny µDB-26 connector. Conclusion The LTC1343 and LTC1344 allow the designer of a multiprotocol serial interface to spend all of his time on the software rather than the hardware. Simply drop the chips down on the board, hook them up to the connector and a serial controller, apply the 5V supply voltage and you’re off and running. In addition, the chip set’s small size and unique termination topology allow many ports to be placed on a board using inexpensive connectors and cables. Linear Technology Magazine • August 1996 DESIGN FEATURES C6 100pF C7 100pF 3 C8 100pF 8 11 12 13 LTC1344 VCC 5V 14 + C3 1µF C1 + 1µF 1 44 2 43 42 4 CHARGE PUMP 3 + C5 1µF 41 8 R1 100k + C11 1µF C9 1µF VCC + C12 1µF 40 GND 23 LB R2 100k LB 7 1 + C10 43 42 1µF 4 CHARGE PUMP DCE TM A RXD A RXD B RXC A RXC B TXC A TXC B RXC A RXC B RXD A RXD B TXC A TXC B SCTE A SCTE B TXD A TXD B TM A LL A SGND SHIELD C13 41 8 + 3.3µF LTC1343 39 D1 38 37 36 35 34 33 D2 D3 D4 R2 32 31 30 29 R3 28 27 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 21 DCE 19 M2 18 M1 17 M0 R1 16 LATCH VCC 44 15 VCC 24 1 14 DTE_CTS/DCE_RTS EC 2 9 DTE_DSR/DCE_DTR DTE LL A 25 10 12 13 DTE_DCD/DCE_DCD 18 17 19 20 22 23 24 1 26 21 DCE 19 M2 18 M1 17 M0 7 DTE_DTR/DCE_DSR 16 15 R3 R2 6 DTE_RTS/DCE_CTS 10 16 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET R1 5 DTE_RL/DCE_RL 9 15 12 17 9 3 16 D4 3 + 7 32 31 30 29 28 27 D3 15 DTE_TM/DCE_LL 6 2 TXD A 14 TXD B 24 SCTE A 11 SCTE B 14 DTE_RXD/DCE_TXD 4 38 37 36 35 34 33 10 12 13 DTE_RXC/DCE_SCTE DB-25 CONNECTOR DCE/ DTE M2 M1 M0 5 D2 9 DTE_TXC/DCE_TXC 2 VEE C4 + 3.3µF 18 7 DTE_SCTE/DEC_RXC 1µF 39 D1 6 DTE_TXD/DCE_RXD + C2 LTC1343 5 DTE_LL/DCE_TM VCC 40 GND 23 LB 21 RL A 4 RTS A 19 RTS B 20 DTR A 23 DTR B 8 DCD A 10 DCD B 6 DSR A 22 DSR B 5 CTS A 13 CTS B RL A CTS A CTS B DSR A DSR B DCD A DCD B DTR A DTR B RTS A RTS B 26 EC 24 DCE/DTE M2 M1 M0 Figure 16. Controller-selectable multiprotocol DTE/DCE port with DB-25 connector Linear Technology Magazine • August 1996 21 DESIGN FEATURES C6 100pF C7 100pF 3 C8 100pF 8 11 12 13 LTC1344 VCC 5V 14 + C3 1µF C1 + 1µF 1 44 2 43 42 4 CHARGE PUMP 3 + C5 1µF D2 D3 9 TXC D4 10 12 13 VCC LL R1 100k + VCC C11 1µF C9 1µF + + C12 1µF VCC 10 12 13 VCC LATCH R2 100k SHIELD (101) + 3.3µF D2 D3 D4 R2 R3 28 27 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 21 DCE 19 M2 18 M1 17 M0 40 GND 23 LB 5 13 6 22 8 10 38 37 36 35 34 33 R1 16 RL 1 SGND (102) 39 D1 32 31 30 29 15 CTX RXD A (104) RXD B RXC A (115) RXC B TXC A (114) TXC B LTC1343 14 DTR TM A (142) C13 41 8 9 DCD 7 1µF 7 DSR 16 15 18 17 19 20 22 23 24 1 VCC + C10 6 CTS 24 43 42 5 RI 10 VCC 44 CHARGE PUMP 9 24 SCTE A (113) 11 SCTE B 2 TXD A (103) 14 TXD B 18 LL A (141) 2 3 7 VCC 1 4 6 3 16 17 9 15 12 26 21 DCE 19 M2 18 M1 17 M0 EC 4 25 16 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 40 GND 23 LB DB-25 FEMA;E CONNECTOR DCE/ DTE M2 M1 M0 38 37 36 35 34 33 R3 R2 15 TXD VEE 39 32 31 30 29 28 27 R1 14 SCTE 2 + 3.3µF 5 D1 7 RXC 1µF LTC1343 6 RXD LB 41 5 TM + C2 C4 8 VCC 20 DTR A (108) 23 DTR B 4 RTS A (105) 19 RTS B 21 RL A (140) 26 EC CTS A (106) CTS B DSR A (107) DSR B/RI A (125) DCD A (109) DCD B RIEN = RS232 24 M2 M1 M0 Figure 17. Controller-selectable multiprotocol DCE port with ring-indicate and DB-25 connector 22 Linear Technology Magazine • August 1996 DESIGN FEATURES C6 100pF C7 100pF 3 C8 100pF 8 12 13 11 LTC1344 VCC 5V 14 + C3 1µF C1 + 1µF 1 44 2 43 42 4 CHARGE PUMP 3 + C5 1µF 41 D4 10 12 13 R3 32 31 30 29 28 27 16 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 26 21 DCE 19 M2 18 M1 17 M0 R1 14 DTE_RXC/DCE_SCTE R2 15 DTE_RXD/DCE_TXD R1 100k + C11 1µF C9 1µF VCC + 40 GND 23 LB + C12 1µF 8 23 24 1 DTE 2 TXD A 14 TXD B 24 SCTE A 11 SCTE B TXC A TXC B RXC A RXC B RXD A RXD B TXC A TXC B SCTE A SCTE B TXD A TXD B SHIELD VCC VCC R3 10k VCC R4 10k VCC R5 10k 25 + 3.3µF 21 18 DCE/DTE M1 M0 39 D1 4 RTS A 19 RTS B 20 DTR A 23 DTR B R2 32 31 30 29 R3 28 27 8 DCD A 10 DCD B 6 DSR A 22 DSR B 5 CTS A 13 CTS B R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 26 21 DCE 19 M2 18 M1 17 M0 40 GND 23 LB DCE RXD A RXD B RXC A RXC B SGND 38 37 36 35 34 33 16 LB 18 17 19 20 22 LTC1343 15 R2 100k 16 15 C13 41 14 VCC 24 1µF 10 12 13 DTE_CTS/ DCE_RTS EC CHARGE PUMP 9 DTE_DSR/DCE_DTR 10 1 + C10 7 DTE_DCD/DCE_DCD 9 7 43 42 6 DTE_DTR/DCE_DSR 7 VCC 44 5 DTE_RTS/DCE_CTS 6 15 12 17 9 3 16 1 3 4 VCC 2 4 DB-25 CONNECTOR DCE/ DTE M2 M1 M0 38 37 36 35 34 33 D3 9 VEE 5 D2 7 DTE_TXC/DCE_TXC 2 + 3.3µF 39 D1 6 DTE_SCTE/DEC_RXC 1µF LTC1343 5 DTE_TXD/DCE_RXD + C2 C4 8 VCC D2 D3 D4 R1 24 EC CTS A CTS B DSR A DSR B DCD A DCD B DTR A DTR B RTS A RTS B VCC CABLE WIRING FOR MODE SELECTION MODE PIN 18 PIN 21 V.35 PIN 7 PIN 7 EIA-530, RS449, NC PIN 7 V.36, X.21 RS232 PIN 7 NC CABLE WIRING FOR DTE/DCE SELECTION MODE PIN 25 DTE PIN 7 DCE NC Figure 18. Cable-selectable multiprotocol DTE/DCE port with DB-25 connector Linear Technology Magazine • August 1996 23 DESIGN FEATURES C6 100pF C7 100pF 3 C8 100pF 8 12 13 11 LTC1344 VCC 5V 14 + C3 1µF C1 1µF + 1 44 2 43 42 4 CHARGE PUMP 3 + C5 1µF 41 D4 10 12 13 R3 32 31 30 29 28 27 16 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 26 21 DCE 19 M2 18 M1 17 M0 R1 14 DTE_RXC/DCE_SCTE R2 15 DTE_RXD/DCE_TXD R1 100k + C11 1µF C9 1µF VCC + 40 GND 23 LB + C12 1µF CHARGE PUMP LB DTE 2 TXD A 14 TXD B 24 SCTE A 11 SCTE B TXC A TXC B RXC A RXC B RXD A RXD B TXC A TXC B SCTE A SCTE B TXD A TXD B SHIELD VCC VCC R3 10k VCC R4 10k VCC R5 10k 25 + 3.3µF 21 18 DCE/DTE M1 M0 39 D1 4 RTS A 19 RTS B 20 DTR A 23 DTR B R2 32 31 30 29 R3 28 27 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 26 21 DCE 19 M2 18 M1 17 M0 8 DCD A 10 DCD B 6 DSR A 22 DSR B 5 CTS A 13 CTS B 26 LL B 40 GND 23 LB DCE RXD A RXD B RXC A RXC B SGND 38 37 36 35 34 33 16 R2 100k 18 17 19 20 22 23 24 1 LTC1343 15 VCC 16 15 C13 8 14 DTE_CTS/DCE_RTS 24 41 10 12 13 DTE_DSR/DCE_DTR EC 1µF 9 DTE_DCD/DCE_DCD 10 1 + C10 7 DTE_DTR/DCE_DSR 9 7 43 42 6 DTE_RTS/DCE_CTS 7 VCC 44 5 DTE_LL/DCE_LL 6 15 12 17 9 3 16 1 3 4 VCC 2 4 µDB-26 CONNECTOR DCE/ DTE M2 M1 M0 38 37 36 35 34 33 D3 9 VEE 5 D2 7 DTE_TXC/DCE_TXC 2 + 3.3µF 39 D1 6 DTE_SCTE/DEC_RXC 1µF LTC1343 5 DTE_TXD/DCE_RXD + C2 C4 8 VCC D2 D3 D4 R1 24 EC CTS A CTS B DSR A DSR B DCD A DCD B DTR A DTR B RTS A RTS B LL B VCC CABLE WIRING FOR MODE SELECTION MODE PIN 18 PIN 21 V.35 PIN 7 PIN 7 EIA-530, RS449, NC PIN 7 V.36, X.21 RS232 PIN 7 NC CABLE WIRING FOR DTE/DCE SELECTION MODE PIN 25 DTE PIN 7 DCE NC Figure 19. Cable-selectable multiprotocol DTE/DCE port with µDB-26 connector 24 Linear Technology Magazine • August 1996 DESIGN IDEAS Li-Ion Battery Charger Does Not Require Precision Resistors by Arie Ravid In constant-voltage mode charging, a Li-Ion cell requires 4.1V ±50mV. This 1.2% tolerance is tight. In a regulation loop where a voltage divider is compared against a reference, the accuracy is achieved by selecting a 0.7% reference and a voltage divider with 0.25% tolerance resistors. Unfortunately, 0.25% precision resistors cost three times as much as 1% resistors and have very long lead times. One solution for moderate volume production involves adding two 1% resistors and two jumpers to the charger circuit, as shown in Figure 1. The jumpers are removed as necessary to bring the constant voltage to the required accuracy of 1.2%. The charger selected for this example is the LT1510 and the number of Li-Ion cells in the battery is three. Select a value for R4 (20k) and calculate the values for resistors R1, R2 and R3 using the equations in Figure 1. K is the relative change required for a circuit with all its tolerances in one direction. For example, in the case of a 0.5% reference and DESIGN IDEAS… Li-Ion Battery Charger Does Not Require Precision Resistors ... 25 Arie Ravid Constant-Voltage Load Box for Battery Simulation ................ 26 Jon Dutra LT1510 Charger with –∆V Termination .................... 27 Arie Ravid Transparent Class-D Amplifiers Featuring the LT1336 ........... 28 Dale Eagar An Ultralow Quiescent Current, 5V Boost Regulator ................ 33 Sam Nork 24 Volt to 14 Volt Converter Provides 15 Amps .................. 34 John Seago The LT1210: High Power Op Amp Yields Higher Voltage and Current .............................................. 36 Dale Eagar LTC1441-Based Micropower Voltage-to-Frequency Converter .............................................. 38 Jim Williams Capacitive Charge Pump Powers 12V VPP from 5V Source ........ 40 Mitchell Lee Bridge Measures Small Capacitance in Presence of Large Strays .................................... 41 two 1% resistors, the total tolerance is 2.5%. In order to bring it back to 1.2%, the percentage change required is 2.5% – 1.2% = 1.3% and K = 0.013. The jumpers J1 or J2 need to be opened based on the following: If VOUT is K/2 below nominal, remove J1. If VOUT is K/2 above nominal, remove J2. The following values were calculated: R1 = 20k, R2 = 324Ω, R3 = 80.6Ω and R4 = 4.99k. The voltage below which J1 should be opened is 12.34V – 1.3%/2 = 12.22V. The voltage above which J2 should be opened is 12.34V + 1.3%/2 = 12.42V. The complete schematic can be seen in Figure 2. Q3 is off when the charger is not powered, preventing current drain from the battery through the voltage divider. R5, a 100k resistor, isolates the OVP pin from any high frequency noise on VIN. The charger in Figure 2 is programmed for 1.3A constant current. Jeff Witt D3 1N5819 C1 D1 0.22µF 1N5819 SW VCC + VIN L1** 33µH R1 OVP R2 – VREF 2.465V J1 + 3-CELL Li-ION R3 + – BOOST VOUT = 12.3V BAT LT1510 CONSTANT VOLTAGE/ CONSTANT CURRENT BATTERY CHARGER J2 – BATTERY GND 1µF VC + R3 = –+ CIN* 10µF LT1510 0.1µF 300Ω 3.83k 1k OVP SENSE BAT + COUT 22µF TANT 3-CELL Li-ION BATTERY J1 R4 R1 = R4 × VOUT – VREF VREF R2 = (R1+R2) × K R5 100k R1 R2 Q3 VN2222 *TOKIN OR MARCON CERAMIC SURFACE MOUNT ** COILTRONICS CTX33-2 J2 R3 R4 × K V 1 – (1 – K) REF VOUT Figure 1. R2, R3, J1 and J2 eliminate the need for precision resistors. Linear Technology Magazine • August 1996 D2 1N914 PROG 16V TO 28V R4 Figure 2. 3-cell Li-Ion charger without precision resistors 25 DESIGN IDEAS Constant-Voltage Load Box for Battery Simulation Linear Technology has developed many new switcher-based battery charger ICs. Testing accuracy, regulation and efficiency in the lab with a battery load is inconvenient because the terminal voltage of a battery constantly changes as it is being charged. If much testing is to be done, a large supply of dead batteries will be needed, since one set of cells can quickly become overcharged. This Design Idea describes an active load circuit that can be used to simulate a battery in any state of charge. The battery simulator provides a constant-voltage load for a battery-charging circuit, independent of applied charging current. The simulator’s impedance is less than 500mΩ at all reasonable input frequencies. Best of all, the simulator can never be overcharged, allowing long-term testing and debugging of a charger system without the possibility of battery damage. by Jon Dutra Circuit Operation The simulator uses an LT1211 high speed, single-supply op amp to drive the base of a high gain PNP transistor-stage active load. Power for the LT1211—a portion of the charging current—is supplied through a diode so the op amp and reference can survive brief periods of zero charging current. The op amp is configured for a DC gain of four, so the voltage on its noninverting input is one fourth of the voltage that the load box is set to. With S1 open, the load-voltage adjust range will be from 10V to 20V, and with S1 closed it will be approximately 3.5V–10V. Low voltage operation could be improved by replacing the top LT1004-2.5 with an LT1004-1.2 and reducing R1, the reference bias resistor, to 1k. The 510Ω and 1.1k resistors are required for high frequency stability; they suppress a 1MHz oscillation. The 1N5400 diode and 4-amp fuse protect the circuit from reverse voltages. Results The battery simulator circuit has been tested “swallowing” currents from 30mA to 3A with the output voltage essentially unchanged. When simulating a battery, the voltage adjust can be increased until the charger thinks the battery is fully charged and reduces the current into the simulator. Conversely, as the voltage is adjusted down, the battery charger may think the battery is becoming discharged and increase the current into the simulator. Figure 2 shows the circuit’s capacity for current absorption at two voltages, 5V and 15V, from 50mA to 3 amps. R1 10k 0.033µF 1N5817 OR BAT-85 + – 5.0V OR 2.5V 1/2 LT1211 100kΩ 10 TURN POT + LT1004-2.5 0.5Ω 5W 30k, 1% 100µF 25V IN+ 15.5 1.1kΩ 5.3 15.4 510Ω + 5.2 15.3 Q1 2N6667 (SEE NOTE) 270µF 25V 2.5V OR 0V 0.033µF LT1004-2.5 4A FUSE VOLTAGE (V) 10k, 1% 1N5400 5.1 15.2 5V 15.1 5 15 15V 4.9 14.9 S1 4.8 14.8 IN– 4.7 14.7 0 0.5 1 1.5 2 CURRENT (A) 2.5 3 S1 CLOSED ≥ 0 TO 10V RANGE S1 OPEN ≥ 10V TO 20V RANGE ALL RESISTORS 5% UNLESS NOTED Q1 DISSIPATES MOST OF THE POWER, MOUNT ON AN ADEQUATE HEAT SINK! Figure 1. Schematic diagram of battery simulator 26 Figure 2. Current absorption capacity of the battery simulator at 5V and 15V Linear Technology Magazine • August 1996 DESIGN IDEAS LT1510 Charger with –∆V Termination by Arie Ravid Any portable equipment that requires fast charge needs proper charge termination. Commonly, a LT1510 constant-voltage, constantcurrent type charger controlled by a microcontroller is used. Sometimes, however, a microcontroller is not available or is not suitable for fastcharge termination. When fast charging NiCd batteries with constant current, the internal battery temperature rises toward the end of the charge. Since the temperature coefficient of NiCd is negative, the temperature rise causes the battery voltage to drop. The drop can be detected and used for termination (called –∆V termination). The circuit in Figure 1 is a solution for a 3-cell (Panasonic P140-SCR) NiCd battery charger with –∆V termination. U1 in Figure 1 is programmed by resistor R2 for a conservative charge current of 0.8A, which is 0.57C. Typi- cal fast-charge current is 1C. (The boldfaced C represents a normalization concept used in the battery industry. A C rate of 1 is equal to the capacity of the cell in ampere-hours, divided by 1 hour. Since the capacity of the P140-SCR is 1.4 ampere-hours, C is 1.4 amperes.) To determine the voltage droop rate, the battery was connected to an LT1510 charger circuit programmed for a 0.8A constant-current. The data was plotted as voltage versus time and the results are shown in Figure 2. The voltage slope is calculated to be –0.6mV/s. After the battery voltage dropped 300mV from the peak of 4.93V (100mV per cell), the charger was disabled. At the heart of the circuit in Figure 1 is U3, a sample-and-hold IC (LF398). For every clock pulse at pin 8, the output of U3 (pin 5) updates to the input level on pin 3. When the battery voltage drops, the input to U3 also drops. If the update step at the output of U3 is sufficiently negative, U2B latches in the high state and Q1 turns on. Q1 terminates the charge by pulling down the LT1510’s VC pin, and thereby disabling it. U2A and the associated passive components smooth, amplify and level shift the battery voltage. The timer (U4) updates the hold capacitor (C8) every fifteen seconds. The timer signal stays high for 7ms, sufficient time for the hold capacitor to be charged to the input level. U2B and the associated parts form a latch that requires a momentary negative voltage at pin 6 to change state. R15 supplies the negative feedback and Q2, R16, R17 and C10 reset the latch on turn-on. U3’s output voltage droops at a rate proportional to the hold capacitor’s internal leakage and the continued on page 32 12V 2 15 VCC1 VCC2 14 13 PROG SW C1 0.22µ L1* 30µ 3 BOOST U1 LT1510 4 GND CR2 1N5819 CR1 1N914 6 VC 12 CR3 1N5819 C3 + 1µ R1 300 R2 6.19k C4 R3 0.1µ 1k 11 GND BAT **1, 7, 8, 9, 10, 16 C2† 10µ + C5 22µ 25V C7 0.1µ R8 100k – C6 0.1µ C12, 0.01µ 16 2 15 4 – 1 5 R20 100k + 3 C9 0.1µ OUTPUT + 6 CLK 150Ω 8 U2B 5 LT1013 R13 10k 12 6 11 7 10 8 9 7 R15 100k R16 100k Q2 2N3904 R17 100k 4 Q1 2N3904 C10 + 22µ – INPUT R10 30.1k 13 LT1029CZ + LOGIC REFERENCE 14 U4 CD45368 5 R11 100k 7 1 3 5VREF 30k LOGIC R18, 100k R19 100k 1 – 8 U2A 3 LT1013 + 4 R14 10k U3 LF398 OFFSET CLK C11 0.22µ N/C R4 10k 2 B1*** R9 30.1k 2 R5 100k R6 100k SENSE R7 10 5VREF HOLD CAPACITOR 6 C8 1µ ECQV1HIOSJL PANASONIC R12 1k R21 10k NOTES: *L1 IS COILTRONICS CTX 33-2 **SOLDER TO GROUND PLANE FOR HEAT DISSIPATION ***B1 IS A NiCd 3 CELL PANASONIC P140-SCR †C2 IS A TOKIN OR MARKON CERAMIC SURFACE MOUNT Figure 1. Schematic diagram: 3-cell NiCd charger with –∆V termination Linear Technology Magazine • August 1996 27 DESIGN IDEAS Transparent Class-D Amplifiers Featuring the LT1336 Introduction + + HEFTY WIRES FROM CAR BATTERY 9V-15V + C1 + + C2 C3 Class-D amplifiers can be simple or complex, depending on what is required by the application. A simple class-D amplifier is the thermostatic switch in an electric heater. The thermostat controls the heater by turning it on or off. The switch is essentially lossless, dissipating practically no power. This class-D amplifier is remarkably efficient, since even the energy lost in the switch, power cord and house wiring contributes to the desired result. The duty factor, and hence the average amount of power delivered to the heater, can assume an infinite number of values. This is true even though a constant amount of heat is delivered when the heater is on. PRi 20T 2x#14 SEC 4T #26 MICROMETALS T150-52 R1 1Ω C4 D3 MUR110 C5 22µF 20V 1200µF, 16V ×4 + – The Electric Heater— a Simple Class-D Amplifier ergy in both directions—input to output and output to input. Class-D amplifiers also have a way of ignoring reactive loads that can be uncanny. A class-D amplifier operating with an AC output will draw very little additional input power when a sizable capacitive or inductive load is placed at its output. This is because the reactive load has AC voltage across it and AC current flowing through it, but the phase angle of the voltage and current is such that no real power is dissipated. The class-D amplifier ends up shuttling power back and forth between its input and its output, doing both with minimal loss. An ideal class-D amplifier can be thought of as having no place to dissipate power, since all of its components are lossless; that is, it contains no resistors. Efficiency in the field of power conversion is like transparency in the field of light transmission. It is no wonder, then, that Class-D amplifiers are often called transparent, since they have no significant power losses. In contrast to class-D amplifiers’ nearly lossless switching, class-A through class-C amplifiers are throttling devices that waste significant energy. Amplifiers of the “lower classes” (A–C) are modeled as rheostats (variable resistors), whereas class-D amplifiers are modeled as variacs (variable transformers). The ideal resistor dissipates power, whereas the ideal transformer does not. Like transformers (variacs), many class-D amplifiers can transfer en- by Dale Eagar 12V D4 MUR110 SEC T1 5 C6 1500pF R2 100k 1 2 8 C7 0.1 Q1 2N3904 R7 1k 6 + – 4 7 U2A LT1215 4 R6 2.4k FB VREF R5 15k 4 C9 0.15 VC VIN 8 + C11 33µF 16V + C12 33µF 16V D2 MBR1060 R4 2.49k R3 51k 7 PRi 36µH 20 30A U1 GTDR LT1243 R16 20Ω 6 D1 1N5819 + C15 C19 1000µF, 63V ×6 R/C C8 1µF 3 + C14 R17 20Ω C13 2200µF 25V 55V, 3.3A + Q3 IRFZ44 Q2 IRFZ44 + R12 0.01Ω 1W ISEN GND 5 R8 1k + 1 U2B LT1215 – R9 1k 3 2 R13 0.01Ω 1W R14 0.01Ω 1W R15 0.01Ω 1W R11 1k C10 220pF R10 100Ω Figure 1. 200W, 12V to 60V front end for automotive applications 28 Linear Technology Magazine • August 1996 DESIGN IDEAS T1 COILTRONICS CTX100-P 12V 55V D3 1N4148 IN TOP OUT C1 1µF IN BOTTOM C2 0.1 R1 6.2k 12V D5 1N4148 R2 2Ω 2 V+ 1 16 10 SW D1 1A 60V IN TOP IN BOTTOM BOOST 13 TGD 12 TGF ISEN TSOU 4 BGD IN TOP 15 S GND 6 Q1 IRFZ44 11 9 Q2 IRFZ44 OUT BGF R6, 10Ω D2 1A 60V IN BOTTOM SW GND R4, 10Ω R5, 10Ω U1 LT1336 3 55V R3, 10Ω 14 V+ 4-Quadrant Class-D Amplifier (SYMBOLIC REPRESENTATION) C3 1µF D4 1N4148 Q3 IRFZ44 Q4 IRFZ44 8 PGND 7 Figure 2. Half-bridge driver subcircuit and symbolic representation Quadrants of Energy Transfer Class-D amplifiers have a property that requires new terminology, a property that generally isn’t considered in lower-class amplifiers. This property, quadrants of energy transfer, describes the output characteristics of the class-D amplifier. The output characteristics are plotted on a imaginary X-Y plot (I’ve yet to see someone actually do one on paper), one axis representing output voltage and the other axis representing output current, with the intersection of the axes representing zero volts and zero amps. A simple switcher that can only provide a positive output current into a positive output voltage can be described as a 1-quadrant device. This 1-quadrant device could be a computer power supply, a battery charger or any supply that delivers a positive voltage into a device that can only consume power. The 2-quadrant converter can be one of two different things: 1) A positive output voltage that can both source and sink current, or 2) A posiLinear Technology Magazine • August 1996 plifier. Figure 2 details the LT1336 driving power MOSFETs and shows the symbolic representation of this subcircuit that will appear in subsequent figures. Table 1 shows the logical states of this half-bridge power driver. tive current that can comply both positive and negative output voltage. Finally, the 4-quadrant converter can both source and sink current into both positive and negitive output voltages. 1-Quadrant Class-D Converter To illustrate the 1-quadrant class-D amplifier, we will focus on the boost mode converter detailed in Figure 1 This circuit removes power from the source (12V automotive battery) and delivers it to the load (some as-yetunknown 55V device) This circuit is classified as “1 quadrant” because it can only regulate output voltage in one polarity (positive) and it can output current in only one polarity (positive). Introducing the LT1336 Half-bridge Driver Taking a side step from our main discussion, we will introduce a component, the half-bridge power am- Class-D amplifiers are commonly used in subwoofer drivers. This is because subwoofers require a great deal of power. A class AB amplifier driving a subwoofer will put about half of its input power into its heat sink. Driving the same subwoofer at the same volume with the same music, a classD amplifier will put about five percent of its input power into the heat sink. The difference is ten to one on the heatsink size and two to one on the input power supply. Figure 3 is the 200W class-D subwoofer driver. This circuit uses the 200W front end developed in Figure 1 as its power source. The circuit in Figure 3 performs as follows: U1a, R1–R4 and C7 implement a 75kHz pseudosawtooth oscillator. U1d is the input amplifier/ filter, with a gain of 6.1 and 200Hz Butterworth lowpass response. U1b and U1c are comparators that compare the sawtooth and the amplified/ filtered input signal to form two complimentary, pulse-width modulated square waves. X1 and X2 are two half-bridge power drivers and M1 is the subwoofer driver. One of the properties of Class-D, 4-quadrant amplification is the ability to transfer power both to and from the load. In our subwoofer driver, this happens when the driver reaches the end of any given excurTable 1. Half-bridge power driver truth table In Top In Bottom Output L L Floating L H Ground H L 55V H H Floating 29 DESIGN IDEAS 12V R1 15k 12V R3 1.8k + 8 U1A LT1365 – R4 15k 10 5 9 6 18" SUBWOOFER DRIVER 1mH, 6.5Ω C8 0.1 R2 15k 12V 55V 4 + U1B LT1365 7 U1C LT1365 1 55V 12V F1 10A M1 – C7 220pF R5 15k 75kHz 3 + 2 C4 0.015 C1 2.2µF R6 1.8k R7 18k – 11 R8 100Ω R9 18k 3 INPUT C3 0.1 C2 0.47 C5 0.022 C6 2.2µF 2 + U1D LT1365 1 – R10 51k R11 10k Figure 3. 200W-powered subwoofer 12V 15k 12V 1.8k + 8 0.1 15k U1A LT1365 – 10 + 9 55V 12V L1 1mH U1B LT1365 – M 220pF 15k 3 2 + U1C LT1365 – 11 1 3 – 12V MOTOR SPEED AND DIRECTION LOAD 12V 55V 4 2 U1D LT1365 1 + POT 1 Figure 4. Class-D motor drive 30 Linear Technology Magazine • August 1996 DESIGN IDEAS + 12V BATTERY + R1 1Ω – + C1 + C2 PRi 20T 2x#14 SEC 4T #26 MICROMETALS T150-52 + C3 C4 D1 MUR110 1200µF, 16V ×4 + C5 22µF 20V 5 6 C6 1.5µF R2 100k 1 2 8 C7 0.1 C9 0.15 R7 1k R6 2.4k VC 20 4 VIN VREF VN2222 C11 33µF 16V + C12 33µF 16V + C13 2200µF 25V 55V + C14 U1 GTDR LT1243 + + C15 C19 6 1000µF, 63V ×6 R/C C8 1µF 3 + 2k 4 FB R5 15k 4 Q1 2N3904 T1 U2A LT1215 – 12V D2 MUR110 7 R4 2.49k R3 51k SEC 8 + ISEN R12 0.01Ω 1W GND 5 R8 1k + 1 U2B LT1215 – R9 1k 3 2 R13 0.01Ω 1W R14 0.01Ω 1W R15 0.01Ω 1W R11 1k C10 220pF R10 200Ω R16 49.9k Figure 5. 200W, 2-quadrant front end for automotive applications sion and the combination of the driver spring and the acoustic spring drive the cone back to center. During this time, energy is transferred from the driver back to the input of the classD amplifier stage. In the case shown in Figure 3, the energy ends up on the 55V bus, where the bus voltage climbs during these periods of “negative energy delivered to the load.” Fortunately, C14–C19 of Figure 1 can store this energy; otherwise the 55V bus would subject to excessive voltage until someplace was found for the energy to go. but when one wants to slow the motor down by turning pot 1 back toward its center, disaster strikes. Rotational energy stored in the inertia of the motor is converted back into electrical energy by the motor and is presented to the output of the class-D amplifier. L1, X1 and X2 do their job by transferring the energy back into the 55V bus. The energy goes into C14–C19 of Figure 1, charging them to some voltage significantly above 55V, and something breaks. The problem here is that the circuit in Figure 1 is only a 1-quadrant class-D amplifier. Managing the Substituting a motor and an inductor Negative Energy Flow Class-D for Motor Drives for the subwoofer in Figure 3 and simplifying the control, we arrive at the circuit shown in Figure 4. Connecting this circuit to the front end shown in Figure 1 and then getting the motor up to speed is no problem, Linear Technology Magazine • August 1996 Sound like a course in management? The negative energy transferred through the class-D amplifier needs a home. One simple home is the 62V power Zener diode strapped across the 55V bus and bolted to a massive heat sink. One could easily imagine the heat sink as the brake shoes heating up as the electric vehicle winds down the mountain road. Another place to put the energy is back into the 12V battery. This will require upgrading the 12V to 55V front-end power converter from 1 quadrant to 2 quadrants. The 2-Quadrant Class-D Converter Converting Figure 1 to two quadrants involves replacing D2 with a switch and activating the switch out of phase with the switch formed by Q2 and Q3. The half-bridge power driver shown in Figure 2 is just such a switch. Refer to Figure 5. The ISENSE signal (U1, pin 3) needs to be offset to accommodate negative current (add R16, Figure 5) The ISENSE signal needs to be scaled for twice the range (–30A to 30A rather 31 DESIGN IDEAS A Trip Over the Great Divide than 0A to 30A); this is done by changing R10. Now we are happily winding down the mountain road, watching the scenery unfold before us. We are happy in knowing that we are recycling the energy released from the descent by charging our batteries, while watching the mountain bikers burn their descent energy off in brake linings. Once again technology wins over sweat and brawn. Climbing the great divide in an electric vehicle requires some planning. Stops to recharge are necessary. Once on top, the whole scheme changes: descending the hill, charging our battery, all goes well until the battery is fully charged; then we have to stop. Further descent would overcharge our battery, boiling out the electrolyte. Not only would this ruin our battery, VIN R1 49.9k R2 95k U1 FIG 5 PIN 8 6 VREF 5.00V Conclusion R3 5M 8 R5 1Ω 200W Class-D has been around for a long time: the venerable electric heater with its bang-bang controller is a remarkably efficient and reliable class-D amplifier. Class-D drives have been used for decades in golf carts, fork lifts, cranes and industry. The advent of the half-bridge driver greatly simplifies the Class-D Amplifier. Here at Linear Technology we have a family of half/full bridge MOSFET drivers. For further information, contact us at the factory or refer to the LT1158, LT1160, LT1162 or LT1336 data sheets. R4 100Ω + U2A LT1215 7 IRFZ40 – 14A 0A 14.3V 14.6V Figure 6. Wolf Creek Pass adapter –∆V Termination, continued from page 27 –dV/dT = VTRIG/(TCLK × GU2A) where: VTRIG is the trigger voltage of U2B, VTRIG = VREF × R12/(R11 + R12) = 5 × 1/101 = 49.5mV VREF = 5V TCLK is the clock period, 15 seconds, GU2A is the gain of the first stage, = R8/(R4 || R5) = 11 The circuit in Figure 1 was built and connected to a system that discharges the battery to 3V after termination, at constant current of 32 5.0 NEGATIVE VOLTAGE SLOPE 4.9 BATTERY VOLTAGE (V) leakage current at pin 6 (10pA typical). This droop is very low and does not affect the operation of the circuit. The minimum negative battery voltage slope required to trigger termination (–dV/dT) is 0.3mV/s. It can be calculated from: in the end we would have no place to put the energy and our class-D amplifier would find some way to fail. We need to stop and drain off some charge, trade batteries with someone climbing the other side or put a power Zener on our battery. Figure 6 details the active Zener circuit. Using the reference in U1 of Figure 5 and the unused half of U2 we are able to make a hysteretic clamp that puts all of the heat into a resistor, R5. This circuit will save the battery from destruction and drop our level of smugness back to that of the mountain bikers. END OF 0.8A CHARGE 4.8 4.7 4.6 4.5 4.4 4.3 4.2 7:30 15:00 22:30 TIME (MIN) 30:00 Figure 2. Voltage-droop rate, 3-cell NiCd battery 0.8A. Once the battery drops to 3V, the system reenables charging, and thus the complete system repeats charge/discharge cycles indefinitely. The duration of 70 charge discharge cycles was recorded. The following is condensed data from the test: 1. Average Charge Time: 2:00:55 Hours 2. Standard Deviation of Charge Time: 5:37 Minutes 3. Average Discharge Time: 1:59:14 Hours 4. Standard Deviation of Discharge Time: 48 Seconds. The ratio of standard deviation of charge time to average charge time proves that the charger has good repeatability. However, the ratio of standard deviation of discharge time to average discharge time shows that the charge level at the time of termination is very consistent because the discharge time at constant current is a better measure of charge level than charge time. A secondary termination method, such as time, battery temperature, or the like, is also recommended. Linear Technology Magazine • August 1996 DESIGN IDEAS An Ultralow Quiescent Current, 5V Boost Regulator Many battery-powered applications require an auxiliary 5V supply to power infrequently used circuitry, such as smart card readers, wireless i.d. tags, or the like. Keeping the 5V supply permanently active is desirable, since this eliminates timing delays and inrush currents due to supply start-up. The downside is that most 5V boost converters consume an unacceptable amount of quiescent current under no-load conditions. This problem is addressed by the SHDN features of the LTC1516 VIN 10µF micropower, charge-pump DC/DC converter. Toggling the SHDN pin of the LTC1516 allows the 5V supply to remain in regulation with a typical no-load input current of less than 5µA. When the 5V output load is enabled, the part can supply up to 50mA of load current. The LTC1516 produces a regulated 5V output from a 2V to 5V input (refer to Figure 1). In normal operation, the part regulates by sensing the output through a resistive divider and enabling a switched-capacitor SHDN + S2A VOUT + S1A C2 + 10µF 0.22µF S2B COMP1 C2 – S1B CLOCK 1 COMP2 CONTROL LOGIC S1C C1 + 0.22µF S2C C1 – CLOCK 2 COMP3 VOS S1D S3 VREF CHARGE PUMP CHARGE PUMP SHOWN IN TRIPLER MODE, DISCHARGE CYCLE Figure 1. LTC1516 simplified block diagram charge pump when the output droops below the trip point of the sense comparator (COMP2). When the output has been boosted above COMP2’s upper trip point, the charge pump is turned off. In shutdown mode, the output load is disconnected from VIN and the quiescent current drops below 1µA. When the output is in regulation, the internal sense resistor draws only 1.5µA (typical) from VOUT. During no-load conditions, this internal load causes a droop rate of only 150mV per second on VOUT with COUT = 10µF. Applying a 5Hz–100Hz, 95%–98% duty-cycle signal to the SHDN pin ensures that the circuit in Figure 2 comes out of shutdown frequently enough to maintain regulation during no-load (or low-load) conditions. Since the part is kept in shutdown mode for the majority of the time, the no-load quiescent current (see Figure 3) is approximately equal to (VOUT × (1.5µA + ILOAD))/(VIN × efficiency). The LTC1516 must be taken out of shutdown mode for a minimum of 200µs to allow the internal sense circuitry to start up and keep the output in regulation. As the VOUT load current increases, the frequency with which the part is taken out of shutdown must also be increased to prevent VOUT from drooping below 4.8V during the OFF phase (see Figure 4). A 100Hz, 98% duty cycle signal continued on page 35 0.22µF 1 VIN = 2V TO 5V 2 + 10µF 3 + 10µF 4 C1+ C1– VIN SHDN LTC1516 VOUT GND C2+ C2 – 0.22µF by Sam Nork 8 7 FROM MPU SHDN PIN WAVEFORMS: 6 5 LOW IQ MODE (5Hz TO 100Hz, 95% TO 98% DUTY CYCLE) VOUT LOAD ENABLE MODE IOUT ≤ 100µA (IOUT = 100µA TO 50mA) VOUT = 5V ±4% Figure 2. Ultralow quiescent current (<5µA) regulated supply Linear Technology Magazine • August 1996 33 DESIGN IDEAS 24 Volt to 14 Volt Converter Provides 15 Amps The LTC1435 is an extremely versatile voltage controller. Most applications take advantage of its ease of design and the high efficiency of its synchronous regulator topology for microprocessor-level output voltages. The LTC1435 can also be used as a conventional buck regulator, with very high efficiency, in circuits requiring hundreds of watts and higher-thanlogic-level output voltages. As a constant-frequency, current mode, step-down switching regulator, it controls external N-channel MOSFETs for very efficient, low noise operation. The current mode architecture provides a tightly controlled output voltage with excellent load and line regulation. Internal slope compensation eliminates subharmonic oscillations. The 1% reference ensures good initial set-point accuracy. The switching frequency can be set between 50kHz and 400kHz, so circuit efficiency, component size and transient response can be properly balanced. The LTC1435 also features both logic-level on/off control and output current soft-start. When the controller is turned off, voltage is removed from the load and quiescent input current drops to a mere 15µA. The LTC1435 is available in the popular 16-pin SO package. by John Seago Combining the LTC1435 with a large geometry power MOSFET and good PCB layout allows large currents to be processed easily and efficiently. With the use of a current sense transformer, output voltages greater than 10V can be implemented. The circuit in Figure 1 shows an LTC1435 configured as a conventional buck regulator using a single N-channel MOSFET to control an output voltage greater than 10V with load current exceeding 15 amps. The efficiency of the breadboard measured 94% with a 24V input, 14V output and 15A of load current. If maximum efficiency is required, adding a sec- D5 1N4148 INPUT 18V TO 28V + C10 1000µF 35V + C11 1000µF 35V T1 R3 10Ω D1 1T 100T C15 100pF D2 1N758 Q1 2N3904 C1 120pF Q3 1 C2, 0.1µF 2 R1, 10k 3 C3, 330pF C4, 47pF 4 5 C5, 100pF 6 R2 11.8k COSC TG RUN/SS ITH SFB BOOST SW U1 LTC1435 VIN INT VCC SGND BG VOSENS 7 SENSE – PGND 8 SENSE + EXT VCC 15 C7, 0.1µF C12 470pF D3 C8, 0.1µF 12 11 Q4 2N3906 R9 0.62Ω R10 100Ω D6 C17 0.001µF Q5 VN2222LL R11 100k L1 10µH 14 13 C16 0.001µF D7 1N751 Q2 2N3906 16 R8 R7 1.2Ω 1K + C9 4.7µF D4 14V AT 15A R6 127k C13 470µF 25V + 10 + C14 470µF 25V GND 9 R4, 100Ω D8 1N4148 C6, 0.001µF R5, 100Ω R12, 100Ω + C18 1µF R14 430Ω R13 2.2k R16 16k Q6 2N3904 C19 0.01µF R15 470Ω C20 0.001µF SPECIAL PARTS C10 = C11 =NICHICON, UPL1V102MHH6 C13 = C14 =NICHICON, UPL1E471MHH6 D1 = D3 = D6 =MOTOROLA, MBRS0540 D4 =MOTOROLA MBR2045 WITH THERMALLOY #7020 HEATSINK Q3 =INTERNAL RECTIFIER, IRL3803 WITH THERMALLOY #6299 HEATSINK U1 =LINEAR TECHNOLOGY, LTC1435CS L1: CORE =MAGNETICS, 55930-AZ WINDING = 8T #14 BIFILAR T1: CORE =MAGNETICS W-41406-TC WINDING = PRI = 1T #18 SEC = 100T #32 Figure 1. 14V, 15A buck regulator 34 Linear Technology Magazine • August 1996 DESIGN IDEAS ond power MOSFET for synchronous switching will improve efficiency by about 1%. This circuit’s 100kHz switching frequency was selected to reduce switching losses so that PCB mounted heat sinks could be used without requiring additional air flow. The switching frequency can be set from 50kHz to 400kHz by selecting an appropriate value for C1. The current sense transformer T1 uses a 1:100 turns ratio to scale down the buck inductor input current and develop the voltage across R9, used by the ±SENSE inputs for regulation. Shortcircuit protection is provided by Q4 and Q5. When the current transformer secondary voltage developed across R8 and R9 is enough to turn on Q4, Q5 temporarily pulls the RUN/SS pin low, turning off the regulator. Output current soft-starts when Q5 releases the RUN/SS pin. This results in frequent attempts to establish output voltage if a short exists, without high current continuously flowing through the power elements. The power elements consist of input capacitors C10 and C11, Current sense transformer T1, buck inductor L1, power MOSFET Q3, commutating diode D4 and output capacitors C13 and C14. Although the wide 3.6V–36V input voltage range and 99% duty cycle operation of the LTC1435 are ideal for A = Q3 SWITCH VOLTAGE 20V/DIV B = L1 CURRENT 10A/DIV 0.0V 0.0A C = T1 PRIMARY CURRENT 10A/DIV 0.0A D = OUTPUT VOLTAGE RIPPLE 14VDC 0.2V/DIV 2µs/DIV Figure 2. Buck regulator circuit waveforms battery/wall adapter input applications, operating above 95% duty cycle causes problems for the current sense transformer. To avoid transformer saturation, the Q6 stage limits duty cycle to approximately 90%. Current through R16 tries to charge C20 to the 3V base voltage of Q6. If the switch cycle terminates at less than a 90% duty cycle, C20 is reset by D8. If the duty cycle exceeds 90%, C20 charges until Q6 turns on, ending the switch cycle. Switch voltage, inductor current, T1 primary current, and output voltage ripple waveforms are shown in Figure 2. These waveforms were measured with a 24V input, 14V output, and 15A load current. When MOS- FET Q3 turns on, the switch voltage (Trace A) goes high, the inductor current (Trace B) increases, as does the T1 primary current (Trace C) and the output ripple voltage (Trace D). When Q3 turns off, the switch voltage goes low, inductor current decreases as its stored energy supplies load current through D4, T1 primary current goes to zero and the output voltage decreases slightly. In addition to its role as a microprocessor voltage controller, the LTC1435 and current sense transformer can be very useful in higher voltage and higher current application where high efficiency and ease-of-design are important. 5V Boost Regulator, continued from page 33 on the SHDN pin ensures proper regulation with load currents as high as 100µA. When load current greater than 100µA is needed, the SHDN pin must be forced low, as in normal operation. The typical no-load supply current for this circuit with VIN = 3V is only 3.2µA. ICC (µA) 4.0 2.0 0.0 2.0 1000 SHDN ON PULSE WIDTH = 200µs COUT = 10µF MAX SHDN OFF TIME (ms) 6.0 100 10 1 3.0 4.0 5.0 1 VIN (V) Figure 3. No-load ICC versus input voltage for Figure 2’s circuit Linear Technology Magazine • August 1996 10 100 1000 IOUT (µA) Authors can be contacted at (408) 432-1900 Figure 4. Maximum SHDN OFF time versus output load current for ultralow IQ operation 35 DESIGN IDEAS The LT1210: High Power Op Amp Yields Higher Voltage and Current by Dale Eagar Introduction 30 The LT1210, a 1 amp current feedback operational amplifier, opens up new frontiers. With 30MHz bandwidth, operation on ±15V supplies, thermal shutdown and 1 amp of output current, this amplifier single handedly tackles many tough applications. But can it handle output voltages higher than ±15V or currents greater than 1 ampere? This Design Idea features a collection of circuits that open the door to high voltage and high current for the LT1210. 25 20 50Ω LOAD GAIN (dB) 15 10 FIGURE 1 CKT +10dBM INPUT 50Ω LOAD 5 0 –5 –10 –15 –20 10K Fast and Sassy— Telescoping Amplifiers 100K 1M FREQUENCY (Hz) input signal. This telescoping arrangement can be cascaded with additional stages to get more than ±30V. This amplifier is stable into capacitive loads, is short-circuit protected and thermally shuts down when overheated. 1k 30V TIP 29 15V 1kΩ 1µF 1k 15V 1 1µF 300Ω 1 LT1210 60Ω 2 + 6 3 1k 4 – 4 – 7 LT1210 7 2 5 5 + 6 3 0.01 0.01 6.2k 1µF 6.2k –15V 60M Figure 2. Gain versus frequency plot of telescoping amplifier Need ±30V? Cascading LT1210’s will get you there. This circuit (Figure 1) will provide the ±30V at ±1A and has 13MHz of full-power bandwidth (see Figure 2). How does it work? The first LT1210 drives the “ground” of the second LT1210 subcircuit, effectively raising and lowering it while the second LT1210 further amplifies the INPUT 10M 15V 1µF TIP 30 1k –30V OUTPUT Extending Power Supply Voltages Another method of getting high voltage from an amplifier is the extendedsupply mode (see “Extending Op Amp Supplies to Get More Voltage”; Linear Technology Volume IV Number 2 (June 1994), pp. 20–22). This involves steering two external regulators with the power supply pins of an op amp to get a high voltage amplifier. Figure 3 shows the LT1210 connected in the extended-supply mode. Placing an amplifier in the extendedsupply mode requires changing the return of the compensation node from the power supply pins to system ground. R9 and C5 are selected for clean step response. The process of relocating the return of the compensation node slows the amplifier down to approximately 1MHz (see Figure 4). Figure 3’s circuit will provide ±1A at ±100V, is stable into capacitive loads and is short-circuit protected. The two external MOSFETs need heat sinking. Figure 1. Telescoping amplifiers 36 Linear Technology Magazine • August 1996 DESIGN IDEAS 100V 100V Boosting Both Current and Voltage 100k 100Ω R8 300Ω 0.01 R7 10k INPUT IRF640 1k 1 P6KE 15A 4 – C5 8pF R9 9.1k + 5 6 0.01 3 15k AV = − ( R8 R9 += R10 ) 220Ω 7 LT1210 2 15V LOAD P6KE 15A 15V 0.01 R10 300Ω R8 R9 − R7 R10 100Ω IRF9640 100k –100V Figure 3. ±100V, ±1A power driver –100V Gateway to the Stars Boosting Output Current The circuit of Figure 3 can be expanded to yield much higher voltages; the first and most obvious way is to use higher voltage MOSFETs. This causes two problems: first, high voltage Pchannel MOSFETs are hard to get; second, and more importantly, at ±1A the power dissipated by the MOSFETs is too high for single packages. The solution is to build telescoping regulators, as shown in Figure 5. This circuit can provide ±1A of current at ±200V and has the additional powerdissipation ability of four MOSFETs. The current booster detailed in Figure 6 illustrates a technique for amplifying the output current capability of an op amp while maintaining speed. Among the many niceties of this topology is the fact that both Q1 and Q2 are normally off and thus consume no quiescent current. Once the load current reaches approximately 100mA, Q1 or Q2 turns on, providing additional drive to the output. This transition is seamless to the outside world and takes advantage of the full speed of Q1 and Q2. This circuit’s small-signal bandwidth and full-power bandwidth are shown in Figure 7. The current-boosted amplifier shown in Figure 6 can be used to replace the amplifiers in Figure 1, yielding ±10A at ±30V. Placing the boosted amplifier in the circuits shown in Figures 3 or 5 will yield peak powers into the kilowatts. Thermal Management When the LT1210 is used with external transistors to increase its output voltage and/or current range an additional benefit can often be realized: system thermal shutdown. Careful analysis of the thermal design of the system can coordinate the overtemperature shutdown of the LT1210 with the junction temperatures of the external transistors. This essentially extends the umbrella of protection of the LT1210’s thermal continued on page 39 200V 0.47µF 250V 10k 1W IRF640 15V 10k 1W IRF640 0.1 15V 220Ω 300Ω 10k 5W INPUT 1k 1 30 25 7 LT1210 2 90Vp-p INTO 50Ω R9 9.1k + C5 8pF ±1A ±200V 4 – 5 LOAD 6 3 0.01 20 300Ω GAIN (dB) 15 15V 10 0.1 100Ω IRF9640 5 10k 1W FIGURE 3 CKT 15V 0 –5 IRF9640 –10 10k 1W –15 –20 10K 0.47µF 250V 100K 1M FREQUENCY (Hz) 10M Figure 4. Gain versus frequency plot of extended-supply amplifier Linear Technology Magazine • August 1996 60M –200V Figure 5. Cascode power amplifier 37 DESIGN IDEAS LTC1441-Based Micropower Voltage-to-Frequency Converter by Jim Williams Figure 1 is a voltage-to-frequency converter. A 0V–5V input produces a 0–10kHz output, with a linearity of 0.02%. Gain drift is 60ppm/°C. Maximum current consumption is only 26µA, 100 times lower than currently available units. To understand the circuit’s operation, assume that C1’s negative input is slightly below its positive input (C2’s output is low). The input voltage causes a positive-going ramp at C1’s input (trace A, Figure 2). C1’s output is high, allowing current flow from Q1’s emitter, through C1’s output stage to the 100pF capacitor. The 2.2µF capacitor provides high frequency bypass, maintaining low impedance at Q1’s emitter. Diode connected Q6 provides a path to ground. The voltage to which the 100pF unit charges is a function of Q1’s emitter potential and Q6’s drop. C1’s CMOS output, purely ohmic, contributes no voltage error. When the ramp at C1’s negative input goes high enough, C1’s output goes low (trace B) and the inverter switches high (trace C). This action pulls current from C1’s negative input capacitor via the Q5 route (trace D). This current removal resets C1’s negative input ramp to a potential slightly below ground. The 50pF capacitor furnishes AC positive feedback (C1’s positive input is trace E) ensuring that C1’s output remains negative long enough for a complete discharge of the 100pF capacitor. The Schottky diode prevents C1’s input from being driven outside its negative common mode limit. When the 50pF unit’s feedback decays, C1 again switches high and the entire cycle repeats. The oscillation frequency depends directly on the input-voltage-derived current. Q1’s emitter voltage must be carefully controlled to get low drift. Q3 and Q4 temperature compensate Q5 and Q6 while Q2 compensates Q1’s VBE. The three LT1004s are the actual voltage reference and the LM334 current source provides 12µA bias to the stack. The current drive provides excellent supply immunity (better than 40ppm/V) and also aids circuit temperature coefficient. It does this by using the LM334’s 0.3%/°C tempco to slightly temperature modulate the voltage drop in the Q2–Q4 trio. This correction’s sign and magnitude directly oppose the –120ppm/°C 100pF polystyrene capacitor’s drift, +V = 6.2 → 12V LM334 INPUT 0–5V 10kHz TRIM 1.2M* 200k 6.04k* + 2.2µF Q8 Q1 – C1 1/2 LTC1441 0.01 LT1004 1.2V x3 + + 0.47 50pF Q2 100k Q3 100Hz TRIM 3M TYP 15k Q5 Q4 Q7 † 100pF 74C14 OUTPUT = HP5082-2810 Q6 10M 2.7M = 1N4148 0.1 Q1, Q2, Q8 = 2N5089 ALL OTHER = 2N2222 † = POLYSTYRENE * = 1% METAL FILM GROUND ALL UNUSED 74C14 INPUTS – C2 1/2 LTC1441 + Figure 1. 0.02% V/F converter requires only 26µA supply current 38 DIVF_01.eps Linear Technology Magazine • August 1996 DESIGN IDEAS A = 50mV/DIV B = 5V/DIV C = 5V/DIV D = 1mA/DIV E = 5V/DIV HORIZ = 20µs/DIV Figure 2. Waveforms for the micropower V/F converter: charge-based feedback provides precision operation with extremely low power consumption. racy permits, draws only small transient currents during its charge and discharge cycles. The 50pF–100k positive feedback combination draws insignificantly small switching currents. Figure 3, a plot of supply current versus operating frequency, reflects the low power design. At zero frequency, comparator quiescent current and the 12µA reference stack bias account for all current drain. There are no other paths for loss. As frequency scales up, the 100pF capacitor’s charge-discharge cycle introduces the 1.1µA/kHz increase shown. A smaller value capacitor would cut power, but effects of stray capacitance and charge imbalance would introduce accuracy errors. Circuit start-up or overdrive can cause the circuit’s AC-coupled feedback to latch. If this occurs, C1’s output goes low; C2, detecting this via the 2.7M–0.1µF lag, goes high. This lifts C1’s positive input and LT1210, continued from page 37 Summary shutdown to cover the external transistors. The thermal shutdown of the LT1210 activates when the junction temperature reaches 150˚C and has about 10˚C hysteresis. The thermal resistance RθJC of the TO-220 package (LT1210CY) is 5˚C/Watt). The LT1210 is a great part; its performance in terms of speed, output current and output voltage is unsurpassed. Its C-Load™ output drive and thermal shutdown allow it to take its place in the real world—no kid gloves are required here. If the generous output specification of the grounds the negative input with Q7, initiating normal circuit action. To calibrate this circuit, apply 50mV and select the indicated resistor at C1’s positive input for a 100Hz output. Complete the calibration by applying 5V and trimming the input potentiometer for a 10kHz output. 35 CURRENT CONSUMPTION (µA) aiding overall circuit stability. Q8’s isolated 100pF drive to the CMOS inverter prevents output loading from influencing Q1’s operating point. This makes circuit accuracy independent of loading. The Q1 emitter-follower delivers charge to the 100pF capacitor efficiently. Both base and collector current end up in the capacitor. The 100pF capacitor, as small as accu- 30 25 20 SLOPE = 1.1µA/kHz 15 10 5 0 0 1 2 3 4 5 6 7 8 9 10 11 12 FREQUENCY (kHz) DIVF_03.eps Figure 3. Current consumption versus frequency for the V/F converter: charge/ discharge cycles account for 1.1µA/kHz current drain increase. LT1210 isn’t big enough for your needs, just add a couple of transistors to dissipate the additional power and you are on your way. Only the worldwide supply of transistors limits the amount of power you could command with one of these parts. 18V 8 0.01 R1 6.2Ω 4AP–P INTO 1Ω 0.033Ω 7 6 Q1, D45VH4 50Ω LOAD 5 3.6k 1 4 4 – 7 LT1210 2 OUT 5 + GAIN (dB) 1.8k IN FIGURE 6 CKT +10dBM INPUT 3 2 6 3 1 0.01 1Ω LOAD Q2, D44VH4 0 0.01 R2 6.2Ω 0.033Ω –1 –2 10K –18V Figure 6. ±10A/1MHz current-boosted power op amp Linear Technology Magazine • August 1996 100K 1M 10M FREQUENCY (Hz) Figure 7. Gain versus frequency response of current-boosted amplifier 39 DESIGN IDEAS Capacitive Charge Pump Powers 12V VPP from 5V Source by Mitchell Lee + 10µF CIN C1+ C1 470nF VCC SHDN OFF ON C1– LTC1263 C2+ C2 470nF C2– 12V AT 60mA VOUT + 10µF COUT VPP FLASH MEMORY For further information on any of the devices mentioned in this issue of Linear Technology, use the reader service card or call the LTC literature service number: –7V OUTPUT (V) VCC = 5V 12V LOAD = 3mA 7 6 1 10 –7V LOAD (mA) Figure 3. Cross regulation with a constant 12V load 40 100 4.75V–5.5V 10µF C1+ VCC SHDN 470nF C1– LTC1263 C2+ 470nF C2– 12V OUTPUT VOUT + 10µF 1µF MBR0520L MBR0520L + –7V OUTPUT 10µF Figure 2. Split supply generator: cross regulation is improved by driving the inverting charge pump from C2+. Figure 1. Programming two flash chips with the LTC1263 charge pump. In shutdown mode, the output is held at 5V. 8 Schemes like this one often suffer from poor cross regulation. Although the inverting output is not directly regulated, the –7V load does affect the 12V output, thereby improving cross regulation (see Figure 3). The regulation with a common load (such as op amps) is shown in Figure 4. 16 VCC = 5V 12 +12V OUTPUT (V) 4.75V-5.5V C1 and C2 in parallel across 5V and ground and then discharging them in series across 5V and the output. In theory, the output could reach 15V, but an internal regulation loop maintains the output at a constant 12V. SHUTDOWN reduces the quiescent current of the LTC1263 to less than 1µA under logic control. In shutdown mode, the output is held at 5V by an internal 500Ω, VCC-to-VOUT switch. Output-voltage fall time is guaranteed to be less than 15ms for the component values shown. Output rise time coming out of shutdown is guaranteed to be less than 800µs. Designing a circuit to generate a split supply from a single 5V source is usually an unpleasant chore; one to be avoided at all costs. If load current requirements are modest, the LTC1263 can generate both 12V and –7V for op amps and biasing needs. Figure 2 shows how. The LTC1263 is connected in the usual way to produce a regulated, 12V output, but a 2 diode, 2-capacitor charge pump is added to the C2+ pin. This pin switches between VCC and VOUT, swinging approximately 7VP–P. The result is an outboard charge pump inverter with a –7V output. + The LTC1263, a regulating charge pump tripler, converts a 5V input to a regulated 12V, 60mA output. No inductors are required; charge pumps operate with capacitors only. Figure 1 shows the LTC1263 configured to provide VPP for two flash memory chips. The “flying” capacitors in the charge pump, C1 and C2, are sized well within the surface mount ceramic range. CIN and COUT, as shown, are surface mount tantalum capacitors, such as Sprague 595D series. In the 10µF capacitance range, tantalum capacitors cost less than ceramic units. The chip operates by charging 8 –7V 1-800-4-LINEAR 4 Ask for the pertinent data sheets and Application Notes. 0 0 20 40 60 COMMON LOAD CURRENT (mA) 80 Figure 4. Output regulation with a common load Linear Technology Magazine • August 1996 DESIGN IDEAS Bridge Measures Small Capacitance in Presence of Large Strays by Jeff Witt Capacitance sensors measure a wide variety of physical quantities, such as position, acceleration, pressure and fluid level. The capacitance changes are often much smaller than stray capacitances, especially if the sensor is remotely placed. I needed to make measurements with a 50pF cryogenic fluid level detector, with only 2pF full-scale change, hooked to several hundred pF of varying cable capacitance. This required a circuit with high stability, sensitivity and noise rejection, but one insensitive to stray capacitance caused by cables and shielding. I also wanted battery operation and analog output for easy interfacing to other instruments. Two traditional circuit types have drawbacks: integrators are sensitive to noise at the comparator and voltageto-frequency converters typically measure stray as well as sensor capacitance. The capacitance bridge presented here measures small transducer capacitance changes, yet rejects noise and cable capacitance. The bridge, shown in Figure 1, is designed around the LTC1043 switched-capacitor building block. The circuit compares a capacitor, CX, of unknown value, with a reference VOUT = VREF CX CREF Balance is achieved by integrating the current from node C using an op amp (LT1413) and a third switch on the LTC1043 for synchronous detection. With CREF = 500pF and VREF = 2.5V, this circuit has a gain of 5mV/ pF, and when measured with a DMM achieves a resolution of 10fF for a dynamic range of 100dB. It also rejects stray capacitance (shown as ghosts in Figure 1) by 100dB. If this rejection is not important, the switching frequency f can be increased to extend the circuit’s bandwidth, which is BW = f 5V VREF 5 + CREF COUT V+ COSC V– 1/2 LT1413 7 16 C1 0.01µF 17 COUT 2.2nF 7 11 – A 1/4 LTC1043 8 CX 1µF With CREF = 50pF, the circuit has a gain of 5V/pF and can resolve 2fF. Supply current is 1mA. The synchronous detection makes this circuit insensitive to external noise sources and in this respect shielding is not terribly important. However, to achieve high resolution and stability, care should be taken to shield the capacitors being measured. I used this circuit for the fluid level detector mentioned above, putting a small trim cap in parallel with CREF to adjust offset and trimming R2 for proper gain. 1/2 LTC1043 4 6 VOUT – VREF ≈ VREF ∆CX (R1 + R2) CREF R2 COUT should be larger than CREF. The circuit operates from a single 5V supply and consumes 800µA. If 5V 100k the capacitances at nodes A and C are kept below 500pF, the LT1078 micropower dual op amp may be used in place of the LT1413, reducing supply current to just 160µA. If the relative capacitance change is small, the circuit can be modified for higher resolution, as shown in Figure 2. A JFET input op amp (LT1462) amplifies the signal before demodulation for good noise performance, and the output of the integrator is attenuated by R1 and R2 to increase the sensitivity of the circuit. If ∆CX << CX, and CREF ≈ CX, then capacitor, CREF. The LTC1043, programmed with C1 to switch at 500Hz, applies a square wave of amplitude VREF to node A, and a square wave of amplitude VOUT and opposite phase to node B. When the bridge is balanced, the AC voltage at node C is zero, and 5V 5 LT1004-2.5 C 2 6 13 3 CREF 12 14 2 + 8 1/2 LT1413 – 1 VOUT 4 B VREF NOTE: SHADED PARTS REPRESENT PARASITIC CAPACITANCES Figure 1. A simple, high performance capacitance bridge Linear Technology Magazine • August 1996 41 CONTINUATIONS VIN 5V 100k VREF 1/2 LTC1043 4 6 5 V+ COSC 16 3 + V– 1/2 LT1413 7 17 1/2 LT1462 10M 2 5V 1/4 LTC1043 VREF 11 – 10k 10k 1 – 7 6 10k 8 CX 1µF + 0.01µF 5 2 100Ω LT1004-2.5 – VREF 5 + 8 1/2 LT1462 7 4 6 VREF 1µF CREF 13 12 5V 14 R1 10.0Ω 1% 8 1 – 1/2 LT1413 + R2 10.0k 1% 4 2 3 100K VREF VOUT Figure 2. A bridge with increased sensitivity and noise performance Bridge circuits are particularly suitable for differential measurements. When CX and CREF are replaced with two sensing capacitors, these circuits measure differential capacitance changes, but reject common mode changes. CMRR for the circuit in Figure 2 exceeds 70dB. In this case, however, the output is linear only for small relative capacitance changes. LTC1433/44, continued from page 14 Power-On Reset Monitor Included An internal regulation monitor provided in the LTC1433 and LTC1434 continuously monitors the output. When the device is out of regulation or in shutdown mode, the POR open drain output pulls low. At start-up, once the output voltage has reached 5% of its final value, an internal timer is started, after which the POR pin is released. The timer counts 216 oscillator cycles, yielding a delay-to-release reset of approximately 300ms in a typical application. Once the output is in regulation, it has to fall by 7.5% before the POR pin is asserted. 42 100 90 EFFICIENCY (%) the internal sense resistance. Figures 6 and 7 show the dropout characteristic at different load currents. VIN = 7V 80 70 VIN = 3.5V 60 50 40 0.001 VOUT = –5.0V COSC = 100pF 0.01 0.10 1.00 LOAD CURRENT (A) Figure 9. Efficiency curve for Figure 8’s positive-to-negative converter Typical Application: Positiveto-Negative Converter Both the LTC1433 and LTC1434 can easily be set up for a negative output voltage. Figure 8 shows the schematic using the LTC1433. The efficiency curve is shown in Figure 9. This circuit is set up so that the output is taken from the device ground. Components that are referenced back to the device ground, Run/SS capacitor, oscillator frequency capacitor and ITH compensation network, are connected to the output instead of to the circuit ground. Conclusion The LTC1433 and LTC1434, with their low dropout, high efficiency and small footprint, are ideal for battery-operated portable equipment applications. In addition, their constant frequency operation makes the devices suited for applications that require the switching regulator to operate at a defined frequency. Linear Technology Magazine • August 1996 DESIGN TOOLS DESIGN TOOLS Applications on Disk Noise Disk — This IBM-PC (or compatible) program allows the user to calculate circuit noise using LTC op amps, determine the best LTC op amp for a low noise application, display the noise data for LTC op amps, calculate resistor noise and calculate noise using specs for any op amp. Available at no charge. SPICE Macromodel Disk — This IBM-PC (or compatible) high density diskette contains the library of LTC op amp SPICE macromodels. The models can be used with any version of SPICE for general analog circuit simulations. The diskette also contains working circuit examples using the models and a demonstration copy of PSPICE™ by MicroSim. Available at no charge. SwitcherCAD — SwitcherCAD is a powerful PC software tool that aids in the design and optimization of switching regulators. The program can cut days off the design cycle by selecting topologies, calculating operating points and specifying component values and manufacturer's part numbers. 144 page manual included. $20.00 SwitcherCAD supports the following parts: LT1070 series: LT1070, LT1071, LT1072, LT1074 and LT1076. LT1082. LT1170 series: LT1170, LT1171, LT1172 and LT1176. It also supports: LT1268, LT1269 and LT1507. LT1270 series: LT1270 and LT1271. LT1371 series: LT1371, LT1372, LT1373, LT1375, LT1376 and LT1377. Micropower SwitcherCAD — MicropowerSCAD is a powerful tool for designing DC/DC converters based on Linear Technology’s micropower switching regulator ICs. Given basic design parameters, MicropowerSCAD selects a circuit topology and offers you a selection of appropriate Linear Technology switching regulator ICs. MicropowerSCAD also performs circuit simulations to select the other components which surround the DC/DC converter. In the case of a battery supply, MicropowerSCAD can perform a battery life simulation. 44 page manual included. $20.00 MicropowerSCAD supports the following LTC micropower DC/DC converters: LT1073, LT1107, LT1108, LT1109, LT1109A, LT1110, LT1111, LT1173, LTC1174, LT1300, LT1301 and LT1303. Technical Books 1990 Linear Databook, Vol I —This 1440 page collection of data sheets covers op amps, voltage regulators, references, comparators, filters, PWMs, data conversion and interface products (bipolar and CMOS), in both commercial and military grades. The catalog features well over 300 devices. $10.00 1992 Linear Databook, Vol II — This 1248 page supplement to the 1990 Linear Databook is a collection of all products introduced in 1991 and 1992. Linear Technology Magazine • August 1996 The catalog contains full data sheets for over 140 devices. The 1992 Linear Databook, Vol II is a companion to the 1990 Linear Databook, which should not be discarded. $10.00 1994 Linear Databook, Vol III —This 1826 page supplement to the 1990 and 1992 Linear Databooks is a collection of all products introduced since 1992. A total of 152 product data sheets are included with updated selection guides. The 1994 Linear Databook Vol III is a companion to the 1990 and 1992 Linear Databooks, which should not be discarded. $10.00 1995 Linear Databook, Vol IV —This 1152 page supplement to the 1990, 1992 and 1994 Linear Databooks is a collection of all products introduced since 1994. A total of 80 product data sheets are included with updated selection guides. The 1995 Linear Databook Vol IV is a companion to the 1990, 1992 and 1994Linear Databooks, which should not be discarded. $10.00 1990 Linear Applications Handbook, Volume I — 928 pages full of application ideas covered in depth by 40 Application Notes and 33 Design Notes. This catalog covers a broad range of “real world” linear circuitry. In addition to detailed, systems-oriented circuits, this handbook contains broad tutorial content together with liberal use of schematics and scope photography. A special feature in this edition includes a 22-page section on SPICE macromodels. $20.00 1993 Linear Applications Handbook, Volume II — Continues the stream of “real world” linear circuitry initiated by the 1990 Handbook. Similar in scope to the 1990 edition, the new book covers Application Notes 40 through 54 and Design Notes 33 through 69. Additionally, references and articles from nonLTC publications that we have found useful are also included. $20.00 Interface Product Handbook — This 424 page handbook features LTC’s complete line of line driver and receiver products for RS232, RS485, RS423, RS422, V.35 and AppleTalk® applications. Linear’s particular expertise in this area involves low power consumption, high numbers of drivers and receivers in one package, mixed RS232 and RS485 devices, 10kV ESD protection of RS232 devices and surface mount packages. Available at no charge Power Solutions Brochure — This 80 page collection of circuits contains real-life solutions for common power supply design problems. There are over 79 circuits, including descriptions, graphs and performance specifications. Topics covered include battery chargers, PCMCIA power management, microprocessor power supplies, portable equipment power supplies, micropower DC/DC, step-up and step-down switching regulators, off-line switching regulators, linear regulators and switched capacitor conversion. Available at no charge. High Speed Amplifier Solutions Brochure — This 72 page collection of circuits contains real-life solutions for problems that require high speed amplifiers. There are 82 circuits including descriptions, graphs and performance specifications. Topics covered include basic amplifiers, video-related applications circuits, instrumentation, DAC and photodiode amplifiers, filters, variable gain, oscillators and current sources and other unusual application circuits. Available at no charge Data Conversion Solutions Brochure — This 52 page collection of data conversion circuits, products and selection guides serves as excellent reference for the data acquisition system designer. Over 60 products are showcased, solving problems in low power, small size and high performance data conversion applications—with performance graphs and specifications. Topics covered include ADCs, DACs, voltage references and analog multiplexers. A complete glossary defines data conversion specifications; a list of selected Application and Design Notes is also included. Available at no charge CD-ROM LinearView — LinearView™ is Linear Technology’s interactive PC-based CD-ROM. LinearView allows you to instantly access thousands of pages of product and applications information, covering Linear Technology’s complete line of high performance analog products, with easy-to-use search tools. The LinearView CD-ROM includes the complete product specifications from Linear Technology’s Databook library (Volumes I–IV) and the complete Applications Handbook collection (Volumes I and II). Our extensive collection of Design Notes and the complete collection of Linear Technology magazine are also included. A powerful search engine built into the LinearView CD-ROM enables you to select parts by various criteria, such as device parameters, keywords or part numbers. All product categories are represented: data conversion, references, amplifiers, power products, filters and interface circuits. Upto-date versions of Linear Technology’s software design tools, SwitcherCAD, FilterCAD, Noise Disk and Spice Macromodel library, are also included. Everything you need to know about Linear Technology’s products and applications is readily accessible via LinearView. Available at no charge. AppleTalk is a registered trademark of Apple Computer, Inc. Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, Linear Technology makes no representation that the circuits described herein will not infringe on existing patent rights. 43 World Headquarters Linear Technology Corporation 1630 McCarthy Boulevard Milpitas, CA 95035-7417 Phone: (408) 432-1900 FAX: (408) 434-0507 U.S. Area Sales Offices NORTHEAST REGION Linear Technology Corporation 3220 Tillman Drive, Suite 120 Bensalem, PA 19020 Phone: (215) 638-9667 FAX: (215) 638-9764 Linear Technology Corporation 266 Lowell St., Suite B-8 Wilmington, MA 01887 Phone: (508) 658-3881 FAX: (508) 658-2701 NORTHWEST REGION Linear Technology Corporation 1900 McCarthy Blvd., Suite 205 Milpitas, CA 95035 Phone: (408) 428-2050 FAX: (408) 432-6331 SOUTHEAST REGION Linear Technology Corporation 17000 Dallas Parkway Suite 219 Dallas, TX 75248 Phone: (214) 733-3071 FAX: (214) 380-5138 Linear Technology Corporation 5510 Six Forks Road Suite 102 Raleigh, NC 27609 Phone: (919) 870-5106 FAX: (919) 870-8831 CENTRAL REGION Linear Technology Corporation Chesapeake Square 229 Mitchell Court, Suite A-25 Addison, IL 60101 Phone: (708) 620-6910 FAX: (708) 620-6977 SOUTHWEST REGION Linear Technology Corporation 21243 Ventura Blvd. Suite 227 Woodland Hills, CA 91364 Phone: (818) 703-0835 FAX: (818) 703-0517 Linear Technology Corporation 15375 Barranca Parkway Suite A-211 Irvine, CA 92718 Phone: (714) 453-4650 FAX: (714) 453-4765 International Sales Offices FRANCE Linear Technology S.A.R.L. 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The Coliseum, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone: 44-1276-677676 FAX: 44-1276-64851 LINEAR TECHNOLOGY CORPORATION 1630 McCarthy Boulevard Milpitas, CA 95035-7417 (408) 432-1900 FAX (408) 434-0507 For Literature Only: 1-800-4-LINEAR 44 © 1996 Linear Technology Corporation/ Printed in U.S.A./34K Linear Technology Magazine • August 1996