The following document contains information on Cypress products.
32-BIT MICROCONTROLLER
FM3 Family
Communication Macro Part
PERIPHERAL MANUAL(MCU SIMULATOR VERSION)
For the information for microcontroller supports, see the following web site.
http://www.spansion.com/support/microcontrollers/
Publication Number FM3_MN706-00043
CONFIDENTIAL
Revision 1.0
Issue Date June 20, 2014
P E R I P H E R A L
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Preface
Thank you for your continued use of Spansion products.
Read this manual and "Data Sheet" thoroughly before using this MCU simulator Model.
This manual explains the FM3 32-bit Microcontroller MCU simulator version(Called "MCU simulator Model"
hereafter).
Purpose of this manual and intended readers
This manual explains the functions and operations of the MCU simulator Model and describes how it is used.
The manual is intended for engineers engaged in the actual development of products using the MCU
simulator Model.
For the descriptions on Analog macro, Timer, and Communication Macro, see the respective separate
peripheral manual.
* This manual explains the configuration and operation of the peripheral functions, but does not cover the
specifics of each device in the series.
Users should refer to the respective data sheets of devices for device-specific details.
Trademark
ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
The company names and brand names herein are the trademarks or registered trademarks of their
respective owners.
Sample programs and development environment
Spansion offers sample programs free of charge for using the peripheral functions of the FM3 family.
Spansion also makes available descriptions of the development environment required for this family. Feel
free to use them to verify the operational specifications and usage of this Spansion microcontroller.
Microcontroller support information:
http://www.spansion.com/support/microcontrollers/
* : Note that the sample programs are subject to change without notice. Since they are offered as a way to
demonstrate standard operations and usage, evaluate them sufficiently before running them on your
system.
Spansion assumes no responsibility for any damage that may occur as a result of using a sample
program.
Overall Organization of This Manual
Peripheral Manual Communication Macro Part has 6 chapters and APPENDIXES as shown below.
CHAPTER 1-1 : Multi-function Serial Interface
CHAPTER 1-2 : UART (Asynchronous Serial Interface)
CHAPTER 1-3 : CSIO (Clock Synchronous Serial Interface)
CHAPTER 1-4 : LIN Interface (Ver.2.1) (LIN Communication Control Interface Ver.2.1)
2
CHAPTER 1-5 : I C Interface
2
CHAPTER 1-6 : I C Auxiliary Noise Filter
CHAPTER 2-1 : USB/Ethernet Clock Generation Block
CHAPTER 2-2 : USB Clock Generation
CHAPTER 2-3 : USB/Ethernet Clock Generation
CHAPTER 3-1 : USB Function
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CHAPTER 3-2 : USB Host
CHAPTER 4 : Ethernet
CHAPTER 5-1 : CAN Prescaler
CHAPTER 5-2 : CAN Controller
CHAPTER 6-1 : HDMI-CEC/Remote Control Reception
CHAPTER 6-2: CEC Reception/Remote Control Reception
CHAPTER 6-3: CEC Transmission
APPENDIXES
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Related Manuals
The manuals related to this MCU simulator Model are listed below. See the manual appropriate to the
applicable conditions.
The contents of these manuals are subject to change without notice. Contact us to check the latest versions
available.
Peripheral Manual
FM3 Family PERIPHERAL MANUAL (this manual)
(Called "PERIPHERAL MANUAL" hereafter)
FM3 Family PERIPHERAL MANUAL Timer Part
(Called "Timer Part" hereafter)
FM3 Family PERIPHERAL MANUAL Analog Macro Part
(Called "Analog Macro Part" hereafter)
FM3 Family PERIPHERAL MANUAL Communication Macro Part
(Called "Communication Macro Part" hereafter)
FM3 Family PERIPHERAL MANUAL Ethernet Part
(Called "Ethernet Part" hereafter)
Data sheet
For details about device-specific, electrical characteristics, package dimensions, ordering information etc.,
see the following document.
32-bit Microcontroller FM3 Family DATA SHEET
* The data sheets for each series are provided.
See the appropriate data sheet for the series that you are using.
CPU Programming manual
For details about ARM Cortex-M3 core, see the following documents that can be obtained from
http://www.arm.com/.
Cortex-M3 Technical Reference Manual
ARMv7-M Architecture Application Level Reference Manual
Flash Programming manual
For details about the functions and operations of the built-in flash memory, see the following document.
FM3 Family FLASH PROGRAMMING MANUAL
* Flash programming manuals for each series are provided.
See the appropriate flash programming manual for the series that you are using.
* The MCU simulator Model does not support Flash Interface Control Registers.
The memory area of the Flash memory is available.
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How to Use This Manual
Finding a function
The following methods can be used to search for the explanation of a desired function in this manual:
Search from the table of the contents
The table of the contents lists the manual contents in the order of description.
Search from the register
The address where each register is located is not described in the text. To verify the address of a
register, see "A. Register Map" in "APPENDIXES".
About the chapters
Basically, this manual explains 1 peripheral function per chapter.
Terminology
This manual uses the following terminology.
Term
Explanation
Word
Indicates access in units of 32 bits.
Half word
Indicates access in units of 16 bits.
Byte
Indicates access in units of 8 bits.
Notations
The notations in bit configuration of the register explanation of this manual are written as follows.
− bit
: bit number
− Field : bit field name
− Attribute : Attributes for read and write of each bit
−
R : Read only
−
W : Write only
−
R/W : Readable/Writable
−
: Undefined
− Initial value : Initial value of the register after reset
−
−
−
0
1
: Initial value is "0"
: Initial value is "1"
X
: Initial value is undefined
The multiple bits are written as follows in this manual.
Example : bit7:0 indicates the bits from bit7 to bit0
The values such as for addresses are written as follows in this manual.
− Hexadecimal number : "0x" is attached in the beginning of a value as a prefix
(example : 0xFFFF)
− Binary number : "0b" is attached in the beginning of a value as a prefix (example: 0b1111)
− Decimal number : Written using numbers only (example : 1000)
The defferences between MCU products and the MCU Simulator Model are written as follows in this
manual.
− A function is not supported by the MCU Simulator Model : Written crossing out sentences or words.
Example : TYPE0 products set the bus right as "DMAC>CPU"
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− A special function of the MCU Simulator Model
: Written by a red letter
Example : Conflicts do not occur in the MCU simulator Model.
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The target products in this manual
In this manual, the products are classified into the following groups and are described as follows.
For the descriptions such as "TYPE0", see the relevant items of the target product in the list below.
Table 1 TYPE0 Product list
Flash memory size
Description in
this manual
TYPE0
512 Kbytes
384 Kbytes
256 Kbytes
MB9BF506N
MB9BF505N
MB9BF504N
128 Kbytes
MB9BF506R
MB9BF505R
MB9BF504R
MB9BF506NA
MB9BF505NA
MB9BF504NA
MB9BF506RA
MB9BF505RA
MB9BF504RA
MB9BF506NB
MB9BF505NB
MB9BF504NB
MB9BF506RB
MB9BF505RB
MB9BF504RB
MB9BF406N
MB9BF405N
MB9BF404N
MB9BF406R
MB9BF405R
MB9BF404R
MB9BF406NA
MB9BF405NA
MB9BF404NA
MB9BF406RA
MB9BF405RA
MB9BF404RA
MB9BF306N
MB9BF305N
MB9BF304N
MB9BF306R
MB9BF305R
MB9BF304R
MB9BF306NA
MB9BF305NA
MB9BF304NA
MB9BF306RA
MB9BF305RA
MB9BF304RA
MB9BF306NB
MB9BF305NB
MB9BF304NB
MB9BF306RB
MB9BF305RB
MB9BF304RB
MB9BF106N
MB9BF105N
MB9BF104N
MB9BF106R
MB9BF105R
MB9BF104R
MB9BF102R
MB9BF106NA
MB9BF105NA
MB9BF104NA
MB9BF102NA
MB9BF106RA
MB9BF105RA
MB9BF104RA
MB9BF102RA
MB9AF105N
MB9AF104N
MB9AF102N
MB9AF105R
MB9AF104R
MB9AF102R
MB9AF105NA
MB9AF104NA
MB9AF102NA
MB9AF105RA
MB9AF104RA
MB9AF102RA
-
-
-
-
MB9BF102N
Table 2 TYPE1 Product list
Flash memory size
Description in this
manual
512 Kbytes
384 Kbytes
256 Kbytes
128 Kbytes
64 Kbytes
MB9AF314L
MB9AF312L
MB9AF311L
MB9AF316M
MB9AF315M
MB9AF314M
MB9AF312M
MB9AF311M
MB9AF316N
MB9AF315N
MB9AF314N
MB9AF312N
MB9AF311N
MB9AF316MA
MB9AF315MA
MB9AF314LA
MB9AF312LA
MB9AF311LA
MB9AF316NA
MB9AF315NA
MB9AF314MA
MB9AF312MA
MB9AF311MA
MB9AF314NA
MB9AF312NA
MB9AF311NA
TYPE1
MB9AF116M
MB9AF115M
MB9AF114L
MB9AF112L
MB9AF111L
MB9AF114M
MB9AF112M
MB9AF111M
MB9AF116N
MB9AF115N
MB9AF114N
MB9AF112N
MB9AF111N
MB9AF116MA
MB9AF115MA
MB9AF114LA
MB9AF112LA
MB9AF111LA
MB9AF116NA
MB9AF115NA
MB9AF114MA
MB9AF112MA
MB9AF111MA
MB9AF114NA
MB9AF112NA
MB9AF111NA
Table 3 TYPE2 Product list
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Flash memory size
Description in this
manual
TYPE2
1 Mbytes
768 Kbytes
512 Kbytes
MB9BFD18S
MB9BFD17S
MB9BFD16S
MB9BFD18T
MB9BFD17T
MB9BFD16T
MB9BF618S
MB9BF617S
MB9BF616S
MB9BF618T
MB9BF617T
MB9BF616T
MB9BF518S
MB9BF517S
MB9BF516S
MB9BF518T
MB9BF517T
MB9BF516T
MB9BF418S
MB9BF417S
MB9BF416S
MB9BF418T
MB9BF417T
MB9BF416T
MB9BF318S
MB9BF317S
MB9BF316S
MB9BF318T
MB9BF317T
MB9BF316T
MB9BF218S
MB9BF217S
MB9BF216S
MB9BF218T
MB9BF217T
MB9BF216T
MB9BF118S
MB9BF117S
MB9BF116S
MB9BF118T
MB9BF117T
MB9BF116T
Table 4 TYPE3 Product list
Flash memory size
Description in
this manual
TYPE3
128 Kbytes
64 Kbytes
MB9AF132K
MB9AF131K
MB9AF132L
MB9AF131L
MB9AF132KA
MB9AF131KA
MB9AF132LA
MB9AF131LA
MB9AF132KB
MB9AF131KB
MB9AF132LB
MB9AF131LB
Table 5 TYPE4 Product list
Flash memory size
Description in
this manual
TYPE4
512 Kbytes
384 Kbytes
256 Kbytes
128 Kbytes
MB9BF516N
MB9BF515N
MB9BF514N
MB9BF512N
MB9BF516R
MB9BF515R
MB9BF514R
MB9BF512R
MB9BF416N
MB9BF415N
MB9BF414N
MB9BF412N
MB9BF416R
MB9BF415R
MB9BF414R
MB9BF412R
MB9BF316N
MB9BF315N
MB9BF314N
MB9BF312N
MB9BF316R
MB9BF315R
MB9BF314R
MB9BF312R
MB9BF116N
MB9BF115N
MB9BF114N
MB9BF112N
MB9BF116R
MB9BF115R
MB9BF114R
MB9BF112R
Table 6 TYPE5 Product list
Flash memory size
Description in this
manual
128 Kbytes
64 Kbytes
MB9AF312K
MB9AF311K
MB9AF112K
MB9AF111K
TYPE5
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Table 7 TYPE6 product list
Flash memory size
Description in
this manual
TYPE6
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256 Kbytes
128 Kbytes
64 Kbytes
MB9AFB44L
MB9AFB42L
MB9AFB41L
MB9AFB44M
MB9AFB42M
MB9AFB41M
MB9AFB44N
MB9AFB42N
MB9AFB41N
MB9AFB44LA
MB9AFB42LA
MB9AFB41LA
MB9AFB44MA
MB9AFB42MA
MB9AFB41MA
MB9AFB44NA
MB9AFB42NA
MB9AFB41NA
MB9AFB44LB
MB9AFB42LB
MB9AFB41LB
MB9AFB44MB
MB9AFB42MB
MB9AFB41MB
MB9AFB44NB
MB9AFB42NB
MB9AFB41NB
MB9AFA44L
MB9AFA42L
MB9AFA41L
MB9AFA44M
MB9AFA42M
MB9AFA41M
MB9AFA44N
MB9AFA42N
MB9AFA41N
MB9AFA44LA
MB9AFA42LA
MB9AFA41LA
MB9AFA44MA
MB9AFA42MA
MB9AFA41MA
MB9AFA44NA
MB9AFA42NA
MB9AFA41NA
MB9AFA44LB
MB9AFA42LB
MB9AFA41LB
MB9AFA44MB
MB9AFA42MB
MB9AFA41MB
MB9AFA44NB
MB9AFA42NB
MB9AFA41NB
MB9AF344L
MB9AF342L
MB9AF341L
MB9AF344M
MB9AF342M
MB9AF341M
MB9AF344N
MB9AF342N
MB9AF341N
MB9AF344LA
MB9AF342LA
MB9AF341LA
MB9AF344MA
MB9AF342MA
MB9AF341MA
MB9AF344NA
MB9AF342NA
MB9AF341NA
MB9AF344LB
MB9AF342LB
MB9AF341LB
MB9AF344MB
MB9AF342MB
MB9AF341MB
MB9AF344NB
MB9AF342NB
MB9AF341NB
MB9AF144L
MB9AF142L
MB9AF141L
MB9AF144M
MB9AF142M
MB9AF141M
MB9AF144N
MB9AF142N
MB9AF141N
MB9AF144LA
MB9AF142LA
MB9AF141LA
MB9AF144MA
MB9AF142MA
MB9AF141MA
MB9AF144NA
MB9AF142NA
MB9AF141NA
MB9AF144LB
MB9AF142LB
MB9AF141LB
MB9AF144MB
MB9AF142MB
MB9AF141MB
MB9AF144NB
MB9AF142NB
MB9AF141NB
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Table 8 TYPE7 product list
Flash memory size
Description in
this manual
128 Kbytes
TYPE7
64 Kbytes
MB9AFA32L
MB9AFA31L
MB9AFA32M
MB9AFA31M
MB9AFA32N
MB9AFA31N
MB9AF132M
MB9AF131M
MB9AF132N
MB9AF131N
MB9AFAA2L
MB9AFAA1L
MB9AFAA2M
MB9AFAA1M
MB9AFAA2N
MB9AFAA1N
MB9AF1A2L
MB9AF1A1L
MB9AF1A2M
MB9AF1A1M
MB9AF1A2N
MB9AF1A1N
Table 9 TYPE8 product list
Flash memory size
Description in
this manual
TYPE8
512 Kbytes
384 Kbytes
256 Kbytes
MB9AF156M
MB9AF155M
MB9AF154M
MB9AF156N
MB9AF155N
MB9AF154N
MB9AF156R
MB9AF155R
MB9AF154R
MB9AF156MA
MB9AF155MA
MB9AF154MA
MB9AF156NA
MB9AF155NA
MB9AF154NA
MB9AF156RA
MB9AF155RA
MB9AF154RA
Table 10
Flash memory size
Description in
this manual
TYPE9
TYPE9 product list
256 Kbytes
128 Kbytes
64 Kbytes
MB9BF524K
MB9BF522K
MB9BF521K
MB9BF524L
MB9BF522L
MB9BF521L
MB9BF524M
MB9BF522M
MB9BF521M
MB9BF324K
MB9BF322K
MB9BF321K
MB9BF324L
MB9BF322L
MB9BF321L
MB9BF324M
MB9BF322M
MB9BF321M
MB9BF124K
MB9BF122K
MB9BF121K
MB9BF124L
MB9BF122L
MB9BF121L
MB9BF124M
MB9BF122M
MB9BF121M
Table 11 TYPE10 product list
Description in
Flash memory size
this manual
64 Kbytes
TYPE10
MB9BF121J
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Table 12 TYPE11 product list
Description in
Flash memory size
this manual
64 Kbytes
MB9AF421K
MB9AF421L
TYPE11
MB9AF121K
MB9AF121L
Table 13 TYPE12 product list
Flash memory size
Description in
this manual
TYPE12
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1.5 Mbytes
1 Mbytes
MB9BF528S
MB9BF528S
MB9BF528T
MB9BF528T
MB9BF428S
MB9BF428S
MB9BF428T
MB9BF428T
MB9BF328S
MB9BF328S
MB9BF328T
MB9BF328T
MB9BF129S
MB9BF128S
MB9BF129T
MB9BF128T
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CONTENTS
CHAPTER 1-1: Multi-function Serial Interface ................................................................... 15
1. Overview of the Multi-function Serial Interface ................................................................. 16
CHAPTER 1-2: UART (Asynchronous Serial Interface) ..................................................... 19
1. Overview of UART (Asynchronous Serial Interface) ........................................................ 20
2. UART Interrupt .................................................................................................................. 21
2.1. Received interrupt and flag set timing........................................................................... 22
2.2. Interrupt and flag set timing when received FIFO is used ............................................ 24
2.3. Transmit interrupt and flag set timing ............................................................................ 26
2.4. Interrupt and flag set timing when transmit FIFO is used ............................................. 27
3. UART Operation ................................................................................................................ 28
4. Dedicated Baud Rate Generator ...................................................................................... 36
4.1. Baud rate settings ......................................................................................................... 37
5. Setting Procedure and Program Flow in Operation Mode 0
(Asynchronous Normal Mode) ....................................................................................... 42
6. Setting Procedure and Program Flow in Operation Mode 1
(Asynchronous Multiprocessor Mode) ........................................................................... 45
7. UART (Asynchronous Serial Interface) Registers ............................................................ 49
7.1. Serial Control Register (SCR) ....................................................................................... 50
7.2. Serial Mode Register (SMR) ......................................................................................... 53
7.3. Serial Status Register (SSR) ......................................................................................... 55
7.4. Extended Communication Control Register (ESCR) .................................................... 58
7.5. Received Data Register/Transmit Data Register (RDR/TDR) ...................................... 60
7.6. Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0) ....................................... 62
7.7. FIFO Control Register 1 (FCR1) ................................................................................... 64
7.8. FIFO Control Register 0 (FCR0) ................................................................................... 67
7.9. FIFO Byte Register (FBYTE) ........................................................................................ 71
CHAPTER 1-3: CSIO (Clock Synchronous Serial Interface) .............................................. 73
CHAPTER 1-4: LIN Interface (Ver. 2.1)
(LIN Communication Control Interface Ver. 2.1)........................................ 75
CHAPTER 1-5: I2C Interface (I2C Communications Control Interface) ............................... 77
CHAPTER 1-6: I2C Auxiliary Noise Filter ........................................................................... 79
CHAPTER 2-1: USB/Ethernet Clock Generation Block...................................................... 81
CHAPTER 2-2: USB Clock Generation ............................................................................. 83
CHAPTER 2-3: USB/Ethernet Clock Generation ............................................................... 85
CHAPTER 3-1: USB Function ........................................................................................... 87
CHAPTER 3-2: USB Host ................................................................................................. 89
CHAPTER 4: Ethernet ....................................................................................................... 91
CHAPTER 5-1: CAN Prescaler.......................................................................................... 93
CHAPTER 5-2: CAN Controller ......................................................................................... 95
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CHAPTER 6-1: HDMI-CEC/Remote Control Reception ..................................................... 97
CHAPTER 6-2: CEC Reception/Remote Reception .......................................................... 99
CHAPTER 6-3: CEC Transmission .................................................................................. 101
APPENDIXES ............................................................................................................... 103
A Register Map ................................................................................................................. 105
1. Register Map .................................................................................................................. 106
B List of Notes .................................................................................................................. 167
1. Notes when high-speed CR is used for the master clock .............................................. 168
C List of Limitations .......................................................................................................... 169
1. List of Limitations for TYPE0 Products........................................................................... 170
2. List of Limitations for TYPE1 Products........................................................................... 173
D Product TYPE List......................................................................................................... 175
1. Product TYPE List .......................................................................................................... 176
MOJOR CHANGES....................................................................................................................... 181
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CHAPTER 1-1: Multi-function Serial Interface
This chapter discribes the overview of the multi-function serial interface.
1. Overview of the Multi-function Serial Interface
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CHAPTER 1-1: Multi-function Serial Interface
1.Overview of the Multi-function Serial Interface
P E R I P H E R A L
M A N U A L
1. Overview of the Multi-function Serial Interface
This multi-function serial interface has the following characteristics.
Interface Mode
The following interface modes are selectable for the multi-function serial interface depending on the operation mode
settings.
UART0 (Asynchronous normal serial interface)
UART1 (Asynchronous multi-processor serial interface)
CSIO (Clock synchronous serial interface) (SPI can be supported)
LIN(LIN bus interface)
I2C (I2C bus interface)
Note:
The MCU simulator model does not support CSIO, LIN, I2C.
<Note>
See explanations of “UART (Asynchronous normal serial interface), “CSIO (Clock synchronous serial interface)”,
“LIN(LIN bus interface)”, and “I2C (I2C bus interface)” chapters for details about each interface.
The MCU simulator model does not support CSIO, LIN, I2C.
Switching the Interface Mode
To communicate through each serial interface, the serial mode register (SMR) shown in Table 1-1 should be used to set
the operation mode before starting the communication.
Table 1-1 Switching Interface Mode
MD2
MD1
MD0
0
0
0
UART0 (Asynchronous normal serial interface)
0
0
1
UART1 (Asynchronous multi-processor serial interface)
0
1
0
CSIO (Clock synchronization serial interface) (SPI can be supported)
The MCU simulator model does not support CSIO.
0
1
1
LIN(LIN bus interface)
The MCU simulator model does not support LIN.
1
0
0
I2C (I2C bus interface)
The MCU simulator model does not support I2C.
Values other than the above
Interface mode
Setting is prohibited.
<Notes>
Transmission and reception cannot be guaranteed when the operation mode is switched while one of the serial
interfaces is still in use for transmission or reception operation.
To switch the current operation mode, issue a programmable clear (SCR:UPCL=1) or disable the I2C (ISMK:EN=0) ,
and switch the operation mode continuously. After the operation mode is set, set each register.
The settings not listed in Table 1-1 are prohibited.
Transmission/Reception FIFO
This function has a 16 × 9 bits transmission FIFO and 16 × 9 bits reception FIFO. The FIFO steps should be converted
to 16 × 9 bits when reading through this text.
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1.Overview of the Multi-function Serial Interface
P E R I P H E R A L
M A N U A L
LIN Sync field Detection: LSYN
If you are to use an ICU in the LIN bus interface mode, use the ICU of the multifunction timer.
For switching an input to an ICU, see the section for Extended Function Pin Setting Register in the chapter "I/O PORT"
in "PERIPHERAL MANUAL".
I2C Auxiliary Noise Filter
If the APB1 bus clock frequency exceeds 40 MHz when using the I2C bus interface, use an auxiliary noise filter. I2C
standard input noise to a maximum of 50 ns is cut off.
For details, see the chapter "I2C Auxiliary Noise Filter".
The I2C auxiliary noise filter is built into only the product with the APB1 bus clock whose maximum frequency is 40
MHz or more.
<Notes>
Since the maximum frequency of the APB1 bus clock varies depending on the product TYPE, refer to the internal
operation clock frequency (FCP1) of the "Data Sheet" of products used.
When the I2C auxiliary noise filter is used, the calculation formula of the reload value that should be set to the Baud
rate generator registers (BGR1, BGR0) is different. See chapter "I2C Auxiliary Noise Filter" for the calculation
formula of reload value when using the I2C auxiliary noise filter.
Extended I2C Bus Control Register (EIBCR)
TYPE6 products and later equip the extended I2C bus control register (EIBCR). This register controls the following
features. For details, see the chapter "I2C Interface (I2C Communication Control Interface)".
Output control of SDA/SCL
Continuity/non-continuity of I2C operation after a bus error occurs
<Note>
Because TYPE0 to TYPE5 products do not equip the EIBCR register, read the following explanation as EIBCR:BEC=0.
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CHAPTER 1-1: Multi-function Serial Interface
1.Overview of the Multi-function Serial Interface
P E R I P H E R A L
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M A N U A L
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
This chapter explains the UART (asynchronous serial interface) function supported in
operation mode 0 and 1 of the multifunction serial interface.
1.
2.
3.
4.
5.
6.
7.
Overview of UART (Asynchronous Serial Interface)
UART Interrupt
UART Operation
Dedicated Baud Rate Generator
Setting Procedure and Program Flow in Operation Mode 0 (Asynchronous Normal Mode)
Setting Procedure and Program Flow in Operation Mode 1 (Asynchronous Multiprocessor Mode)
UART (Asynchronous Serial Interface) Registers
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
1.Overview of UART (Asynchronous Serial Interface)
P E R I P H E R A L
M A N U A L
1. Overview of UART (Asynchronous Serial Interface)
UART (asynchronous serial interface) is a general-purpose serial data communications interface for
asynchronous communications (start/stop synchronization) with external devices. It supports a
bi-directional communications function (normal mode) and a master/slave type communications function
(multi-processor mode: both master and slave modes supported). It also has transmit /received FIFO
installed.
Functions of UART (Asynchronous Serial Interface)
Function
1
Data
Full duplex double buffer (when FIFO is not used)
Transmit /received FIFO (size: max 128 × 9 bits each)*1 (when FIFO is
used)
2
Serial input
Run oversampling three times with the bus clock and determine the value
of received data based on the majority sampling value.
3
Transfer system
4
Baud rate
5
Data length
6
Signaling system
NRZ (Non Return to Zero), inverted NRZ
7
Start bit detection
In synch with the falling edge of the start bit (in the NRZ system)
In synch with the rising edge of the start bit (in the inverted NRZ
system)
8
Received error detection
9
Hardware flow control
10
Interrupt request
11
Master/slave communications
functions
(in multiprocessor mode)
12
FIFO options
Asynchronous
A dedicated baud rate generator (constructed with a 15-bit reload
counter)
The external clock input can be adjusted with the reload counter.
5 to 9 bits (in normal mode)/7 bits or 8 bits (in multiprocessor mode)
Framing error
Overrun error
Parity error*2
CTS/RTS-based automatic transmit /received control
Received interrupt
(upon reception completed, framing error, overrun error or parity
error*2)
Transmit interrupts (transmit data empty, transmit bus idle)
Transmit FIFO interrupt (when transmit FIFO is empty)
DMA(Transmit /Received) transferring support function is available.
One (master)-to-n (slaves) communication is enabled.
(Both master and slave systems are supported.)
Transmit /received FIFO installed (maximum capacity: 128 × 9 bits for
transmit FIFO, 128 bytes × 9 bits for received FIFO) *1
Transmit FIFO or received FIFO can be selected.
Transmit data can be resent.
Received FIFO interrupt timing can be changed via software.
FIFO resetting is supported independently.
*1: The FIFO capacity size varies depending on the product type.
*2: Parity errors are only generated in normal mode.
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
2.UART Interrupt
P E R I P H E R A L
M A N U A L
2. UART Interrupt
UART generates transmit or received interrupts. These interrupt requests can be generated if:
- Received data is set in the Received Data Register (RDR) or a data received error occurs.
- Transmit data is transferred from the Transmit Data Register (TDR) to the transmit shift register and the
data transmission is started.
- The transmit bus is idle (No data transmission occurs).
- Transmit FIFO data is requested.
UART Interrupt
Table 2-1 shows the relationships between the UART interrupt control bits and the interrupt factors.
Table 2-1 UART interrupt control bits and interrupt factors
Interrupt
type
Interrupt
Operation
request
Flag
mode
flag
register
0
1
bit
Interrupt factor
Interrupt
factor
enable bit
Operation to clear
interrupt request flag
Reading from the received data
register (RDR)
A single-byte received
Received of a data
volume matching the
value set for FBYTE.
RDRF
SSR
Received
While the FRIIE bit is
"1" and the received
FIFO contains valid
data, a received idle
state continues for 8
bits or longer period.
ORE
SSR
Overrun error
FRE
SSR
Framing error
PE
SSR
x
Parity error
TDRE
SSR
SCR:RIE
Reading from the Received Data
Register (RDR) until received FIFO
is emptied
Setting the received error flag clear
bit (SSR:REC) to "1"
The Transmit Data
Register is empty
SCR:TIE
Writing to the Transmit Data
Register (TDR) or setting the
transmit FIFO operation enable bit
to "1" when the transmit FIFO
operation enable bit is set to "0" and
valid data are present in transmit
FIFO (re-transmitting data) *1
TBI
SSR
No data transmission
Writing to the Transmit Data
Register (TDR) or setting the
transmit FIFO operation enable bit
SCR:TBIE to "1" when the transmit FIFO
operation enable bit is set to "0" and
valid data are present in transmit
FIFO (re-transmitting data) *1
FDRQ
FCR1
Transmit FIFO is
empty.
The FIFO transmit data request bit
FCR1:FTIE (FCR1:FDRQ) is set to "0" or
transmit FIFO is full.
Transmit
*1: Set the TIE bit to "1" only after the TDRE bit has been set to "0".
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
2.UART Interrupt
P E R I P H E R A L
M A N U A L
2.1. Received interrupt and flag set timing
Data reception can be interrupted by a Received Completion (SSR:RDRF=1) or a Received Error
Occurrence (SSR:PE,ORE,FRE=1).
Received interrupt and flag set timing
Upon detection of the first stop bit, received data are stored in the Received Data Register (RDR). When the data
received is completed (SSR:RDRF=1) or when a data received error occurs (SSR:PE, ORE, FRE=1), each flag is set. If
received interrupts are enabled (SSR:RIE=1) then, a received interrupt occurs.
<Note>
If a received error occurs, data in the Received Data Register (RDR) becomes invalid.
Figure 2-1 RDRF (Received Data Register Full) flag bit set timing
Received
data
ST
D0
D1
D2
D5
D6
D7
SP
ST
RDRF
A received interrupt occurred.
Figure 2-2 FRE (Framing Error) flag bit set timing
Received
data
ST
D0
D1
D2
D5
D6
D7
SP
ST
RDRF
FRE
A received interrupt occurred.
Notes:
- If the first stop bit is "LOW," a framing error occurs.
- The RDRF bit is set to "1" and data can be received even if a framing error has occurred.
However, the received data is invalid.
<Note>
During reception, if the following is detected at the same time as the stop bit sampling point or before the 1 to 2 bus
clocks, the relevant edge becomes invalid, which may disable normal received of the next data. To output frames
continuously, adequate intervals are required between frames.
The falling edge of serial data (When ESCR:INV=0)
The rising edge of serial data (When ESCR:INV=1)
Figure 2-3 ORE (Overrun Error) flag bit set timing
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2.UART Interrupt
P E R I P H E R A L
Received
data
M A N U A L
ST D0 D1 D2 D3 D4 D5 D6 D7 SP ST D0 D1 D2 D3 D4 D5 D6 D7 SP
RDRF
ORE
Note:
If the next data is transferred before the received data is read (RDRF=1), an overrun error occurs.
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
2.UART Interrupt
P E R I P H E R A L
M A N U A L
2.2. Interrupt and flag set timing when received FIFO is used
If the received FIFO is used, an interrupt occurs when the FBYTE data (preset for the FBYTE register) is
received.
Interrupt and flag set timing when received FIFO is used
If the received FIFO is used, an interrupt occurs depending on the value set for the FBYTE register.
When full FBYTE data is received, the received data full flag (SSR:RDRF) of the Serial Status register is set to "1". If
received interrupts are enabled (SCR:RIE) during this time, a received interrupt occurs.
If both of the following conditions are satisfied and if the received idle state continues for more than 8 baud rate
clocks, the receive data full flag (SSR:RDRF) is set to "1".
The received FIFO idle detection enable bit (FCR:FRIIE) is "1".
The number of data sets stored in the received FIFO does not reach the transfer count.
If the RDR data is read during counting of 8 clocks, this counter is reset to "0", and counting for 8 clocks is restarted.
If received FIFO is disabled, this counter is reset to zero (0).If data remains in the received FIFO and if received
FIFO is enabled, the data counting is restarted.
When data is read from the Received Data Register (RDR) until received FIFO is emptied, the received data full flag
(SSR:RDRF) is cleared.
If the valid received data amount is the same as the FIFO capacity and if the next data is received, an overrun error
(SSR:ORE=1) occurs.
Figure 2-4 Received interrupt timing when Received FIFO is used
Received data
ST 1st byte SP
ST 2nd byte SP
FBYTE setting
(with the transfer count)
Reading of FBYTE
(Effective byte count display)
ST 3rd byte SP
ST 4th byte SP
ST 5th byte SP
3
0
1
2
3 2 1
0
1
2
RDRF
Data reading from RDR
An interrupt occurs when the FBYTE (transmit data)
count matches the received data count.
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
2.UART Interrupt
P E R I P H E R A L
M A N U A L
Figure 2-5 ORE (Overrun Error) flag bit set timing
Received data
ST 62nd byte SP
ST 63rd byteSP
FBYTE setting
(with the transfer count)
Reading of FBYTE
(Effective byte count display)
ST 64th byte SP
ST 65th byte SP
ST 66th byte SP
62
62
63
64
RDRF
ORE
An overrun error occurred.
Note:
If the next data set is received when the FBYTE reading is indicating the FIFO capacity,
an overrun error occurs.
This figure shows a case where a 64-byte FIFO capacity is applied.
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
2.UART Interrupt
P E R I P H E R A L
M A N U A L
2.3. Transmit interrupt and flag set timing
A transmit interrupt occurs when transmit data is transferred from the Transmit Data Register (TDR) to
the transmit shift register (SSR:TDRE = 1) and transmission starts and when no transmission is
performed (SSR:TBI = 1).
Transmit interrupt and flag set timing
Transmit data empty flag (SSR:TDRE) set timing
After data has been transferred from the Transmit Data Register (TDR) to the transmit shift register, the next data can be
written in the TDR (SSR:TDRE = 1). If transmit interrupts are enabled (SCR:TIE = 1) during this time, a transmit
interrupt occurs. As the SSR:TDRE bit is read only, the SSR:TDRE bit is cleared to "0" when data is written to the
Transmit Data Register (TDR).
Figure 2-6 Transmit data empty flag (SSR:TDRE) set timing
A transmit interrupt occured.
A transmit interrupt occured.
Transmit data
(Mode 0 or 1)
S T D0
D1
D2
D3 D4 D5 D6
D7 S P
ST D0 D 1 D 2
TDRE
Data writing in TDR
ST : Start bit
Data
bits
ST : Start bit D0 to D7 :D0
to D7
: Data bits
SP :SP
Stop
bit bit
: Stop
Transmit bus idle flag (SSR:TBI) set timing
If the Transmit Data Register is empty (SSR:TDRE=1) and no data is transmitted, the SSR:TBI bit is set to "1". If
transmit bus idle interrupts are enabled (SCR:TBIE = 1) during this time, a transmit interrupt occurs. When transmit data
is written to the Transmit Data Register (TDR), both the SSR:TBI bit and the transmit interrupt request are cleared.
Figure 2-7 Transmit bus idle flag (TBI) set timing
Transmit data
S T D0 D1 D2 D3 D4 D5 D6 D7
SP
S T D0 D1 D2 D3 D4 D5 D6 D7 S P
TBI
TDRE
A transmit interrupt by
the TBI bit occured.
Writing in TDR
ST : Start bitST : Start bit
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to D7
: Data
bits
D0 D0
to D7
: 7Data
bits
SPSP
: Stop
bit bit
: Stop
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2.UART Interrupt
P E R I P H E R A L
M A N U A L
2.4. Interrupt and flag set timing when transmit FIFO is used
When the transmit FIFO is used, an interrupt occurs if the FIFO contains no data.
Transmit interrupt and flag set timing when transmit FIFO is used
If the Transmit FIFO contains no data, the FIFO transmit data request bit (FCR1:FDRQ) is set to "1".
If FIFO transmit interrupts are enabled (FCR1:FTIE=1), a transmit interrupt occurs.
If a transmit interrupt has occurred and you have written the required data in transmit FIFO, clear the interrupt request
by setting the FIFO transmit data request bit (FCR1:FDRQ) to "0".
The FIFO transmit data request bit (FCR1:FDRQ) is set to "0" when transmit FIFO becomes full.
To check to see if transmit FIFO contains any data, read from the FIFO Byte Register (FBYTE).
If FBYTE=0x00, no data exists in the transmit FIFO.
Figure 2-8 Transmit interrupt timing when transmit FIFO is used
ST 1st byte SP
Transmit data
FBYTE
0
1
2
1
ST 2nd byte SP
0
1
ST 3rd byte ST
2
1
SP 4th byte SP
SP 5th byte
0
FDRQ
TDRE
Cleared if
set to "0".
Data writing in transmit
FIFO (TDR)
A transmit interrupt
occurred.*1
Cleared if
set to "0".
A transmit interrupt
occurred.*1
The transmit Data Register is empty.*2
*1) The FDRQ bit is set to "1" as Transmit FIFO is empty.
*2) The TDRE bit is set to “1” as the Transmit Shift Register and the Transmit Buffer Register
contain no data.
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
3.UART Operation
P E R I P H E R A L
M A N U A L
3. UART Operation
UART operates in bi-directional serial asynchronous communications in mode 0 and master/slave
multiprocessor communications in mode 1.
UART operation
Transmit/received data format
Transmit/received data always starts with a start bit, followed by transmit/received of data with the specified data bit
length, and ends with at least one-bit long stop bit.
The BDS bit of the Serial Mode Register (SMR) determines the data transmission direction (LSB first or MSB first).
If parity is used, the parity bit is always placed between the last data bit and the first stop bit.
In operation mode 0 (normal mode), selection is possible to use or not to use parity.
In operation mode 1 (multiprocessor mode), no parity is added, and instead, the AD bit is added.
Figure 3-1 shows the transmit/received data formats for operation mode 0 and 1.
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3.UART Operation
P E R I P H E R A L
M A N U A L
Figure 3-1 Example transmit/received data format (operation mode 0/1)
[Operation mode 0]
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP1 SP2
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP1
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP1 SP2
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP1
ST
D0
D1
D2
D3
D4
D5
D6
SP1 SP2
ST
D0
D1
D2
D3
D4
D5
D6
SP1
ST
D0
D1
D2
D3
D4
D5
D6
P
SP1 SP2
ST
D0
D1
D2
D3
D4
D5
D6
P
SP1
ST
D0
D1
D2
D3
D4
D5
D6
D7
AD
SP1 SP2
ST
D0
D1
D2
D3
D4
D5
D6
D7
AD
SP1
ST
D0
D1
D2
D3
D4
D5
D6
AD SP1 SP2
ST
D0
D1
D2
D3
D4
D5
D6
AD SP1
Without P
Data: 8 bits
With P
Without P
Data: 7 bits
With P
[Operation mode 1]
Data: 8 bits
Data: 7 bits
ST : Start bit
SP : Stop bit
P : Parity bit
AD : Address bit
D : Data bit
<Notes>
The above figure shows formats when the data length is set to 7 or 8 bits. (In operation mode 0, the data length can be
set between 5 and 9 bits.)
If the BDS bit of the Serial Mode Register (SMR) is set to "1" (MSB first), the bits are processed from D7, and then
D6, D5, ... D1, and D0 (P), in that order.
If the data length is set to X bits, the lower X bit of the Transmit/Received Data Register (TDR/RDR) is enabled.
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
3.UART Operation
P E R I P H E R A L
M A N U A L
Data transmission
If the transmit data empty flag bit (TDRE) of the Serial Status Register (SSR) is "1", the transmit data can be written
in the Transmit Data Register (TDR). (When transmit FIFO is enabled, transmit data can be written even if TDRE=0.)
If transmit data is written in the Transmit Data Register (TDR), the transmit data empty flag bit (SSR:TDRE) is set to
"0".
Setting the transmission enable bit of the serial control register (SCR:TXE) to "1" causes transmit data to be loaded to
the transmit shift register, followed by sequential transmission starting with the start bit.
When transmission starts, the transmit data empty flag bit (SSR:TDRE) is set to "1" again. If transmit interrupts are
then enabled (SCR:TIE=1), a transmit interrupt is generated. In the interrupt processing, the next transmit data set can
be written in the Transmit Data Register,
<Notes>
As the transmit data empty flag bit (SSR:TDRE) is initially set to "1", a transmit interrupt occurs as soon as transmit
interrupts are enabled (SCR:TIE).
As the FIFO transmit data request bit (FCR1:FDRQ) is initially set to "1", a transmit interrupt occurs as soon as FIFO
transmit interrupts are enabled (FCR1:FTIE=1).
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
3.UART Operation
P E R I P H E R A L
M A N U A L
Data reception
When reception is enabled (SCR:RXE=1), the interface performs reception.
Upon detection of the start bit, one-frame data reception takes place according to the data format set in the extended
communications control register (ESCR:PEN, P, L2, L1, L0) and serial mode register (SMR:BDS). A start bit is
detected when falling (ESCR:INV=0) is detected after passing the noise filter (with the majority value applied after
sampling serial data input three times with the bus clock) or if rising (ESCR:INV=1) is detected and "LOW" is
detected for the data passing the sampling point.
When one-frame reception is completed, the received data full flag bit (SSR:RDRF) is set to "1". If received
interrupts are then enabled (SCR:RIE=1), a received interrupt is generated.
To read received data, perform reading of the received data after one-frame data received is completed and check the
state of the error flag of the Serial Status Register (SSR). Handle the received error if it is occurring.
Reading of the received data causes the received data full flag bit (SSR:RDRF) to be cleared to "0".
If received FIFO is enabled, the received data full flag bit (SSR:RDRF) is set to "1" when the number of received
frames has reached the value set for received FBYTE.
If all of the following conditions are satisfied and if the received idle state continues for more than 8 baud rate clocks,
the interrupt flag (RDRF) is set to "1".
The received FIFO idle detection enable bit (FRIIE) is "1".
The number of data sets stored in the received FIFO does not reach the transfer count.
If the RDR data is read during counting of 8 clocks, this counter is reset to "0", and counting for 8 clocks is restarted.
If received FIFO is disabled, this counter is reset to zero (0). If data remains in the received FIFO and if received
FIFO is enabled, the data counting is restarted.
If received FIFO is enabled, received FIFO does not store data in which an error has occurred when the error flag of
the Serial Status Register (SSR) is set to "1". Also note that the received data full flag bit (SSR:RDRF) is not set to
"1". (However, the RDRF flag is set to "1" in an overrun error.) What the received FBYTE indicates is the number of
data sets received normally before the error occurred. Unless the error flag of the Serial Status Register (SSR) is
cleared to "0", received FIFO is not enabled.
If received FIFO is enabled, the received data full flag bit (SSR:RDRF) is cleared to "0" when all data in received
FIFO is out.
<Notes>
Data in the Received Data Register (RDR) becomes valid when the received data register full flag bit (SSR:RDRF) is
set to "1" and no received error occurs (SSR:PE, ORE, FRE=0).
Although a noise filter is built in (with the majority value applied after sampling serial data input three times with the
bus clock), wrong data may be received if any noise passes through the filter. As a countermeasures, you can design
the board so as not to allow noise to pass through this filter or perform communications so that noise that has passed
may not cause any problem (by adding check sum of data at the end and resending the data if any error occurs, for
example).
During reception, if the following is detected at the same time as the stop bit sampling point or before the 1 to 2 bus
clocks, the relevant edge becomes invalid, which may disable normal reception of the next data. To output frames
continuously, adequate intervals are required between frames.
The falling edge of serial data (When ESCR:INV=0)
The rising edge of serial data (When ESCR:INV=1)
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3.UART Operation
P E R I P H E R A L
M A N U A L
Clock selection
You can use either an internal or external clock.
To use the external clock, set SMR:EXT to "1". IN this case, the external clock is subject to frequency division by the
baud rate generator.
Start bit detection
In asynchronous mode, the start bit is recognized based on detection of the falling edge of the SIN signal.
For that reason, reception is not started unless the falling edge of the SIN signal is input even if reception is enabled
(SCR:RXE=1).
Upon detection of the start bit's falling edge, the received reload counter of the baud rate generator is reset and
reloaded to start countdown. Thus, sampling always takes place in the middle of data.
Start bit
Data bit
SIN
SIN
(Over-Sampled)
SEDGE
(Internal signal)
Reload
counter reset
Data sampling
Received
sampling clock
A bit time
Stop bit
You can select the bit length to be between one and four.
The received data full flag bit (SSR:RDRF) is set to "1" upon detection of the first stop bit.
Error detection
In operation mode 0, parity, overrun and framing errors can be detected.
In operation mode 1, overrun and framing errors can be detected but parity errors cannot be detected.
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3.UART Operation
P E R I P H E R A L
M A N U A L
Parity bit
The parity bit can only be added in operation mode 0. The parity enable bit (ESCR:PEN) can be used to specify use or
non-use of parity and the parity selection bit (ESCR:P) to set even-number parity or odd-number parity.
Parity cannot be used in operation mode 1.
Figure 3-2 shows transmit/received data when parity is enabled.
Figure 3-2 Operation when parity is enabled
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
Received
data (Mode 0)
During received , a parity error occurs
through even-number parity check.
(ESCR:P=0)
SMR : PE
Transmit data
(Mode 0)
Transmission of even-number parity bits
(ESCR:P=0)
Transmit data
(Mode 0)
Transmission of odd-number parity bits
(ESCR:P=1)
ST : Start bit
SP : Stop bit
With parity (ESCR:PEN = 1), 8-bit long
Note : Parity cannot be used in operation mode 1.
Data signaling system
By setting up the INV bit of the extended communications control register, you can select either the NRZ (Non Return to
Zero) signaling system (ESCR:INV=0) or inverted NRZ signaling system (ESCR:INV=1).
Figure 3-3 shows the NRZ and inverted NRZ signaling systems.
Figure 3-3 NRZ (Non Return to Zero) signaling system and inverted NRZ signaling system
SIN (NRZ)
INV = 0
ST
D0
D1
D2
D3
D4
D5
D6
D7 SP
SIN (Inverted NRZ)
INV = 1
ST
D0
D1
D2
D3
D4
D5
D6
D7 SP
SOT (NRZ)
INV = 0
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
SOT (Inverted NRZ)
INV = 1
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
Data transfer system
As for the data bit transfer method, either LSB first or MSB first can be selected.
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
3.UART Operation
P E R I P H E R A L
M A N U A L
Hardware flow control
When flow control is enabled (ESCR:FLWEN=1), UART performs hardware flow control.
During data transmission
If CTS is "HIGH" after data is transmitted, the next data is not transmitted even if the transmit buffer contains data
(TDRE=0) and the process waits until CTS is set to "LOW". To have transmission wait, input "HIGH" in CTS
before the stop bit transmission is completed. Transmission continues up to the stop bit even if "HIGH" is input in
CTS during transmission.
Figure 3-4 Hardware flow control during data transmission
(SMR:SBL=0, ESCR:ESBL=INV=PEN=L2=L1=L0=0)
Transmit data
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
CTS
TDRE
Data writing in TDR
Transmit in
wait state
During data reception
If FIFO is not used
Upon reception of data one bit before the stop bit, "HIGH" is output to RTS . After received data is read,
"LOW" is output to RTS .
Figure 3-5 Hardware flow control during data reception (with FIFO is unused.)
(SMR:SBL=0, ESCR:ESBL=INV=PEN=L2=L1=L0=0)
Received data
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
RTS
RDRF
Reading from RDR
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
3.UART Operation
P E R I P H E R A L
M A N U A L
If FIFO is used
If SSR:RDRF is not set (the specified number of data sets are not received in received FIFO), RTS outputs
"HIGH" upon reception of data one bit before the stop bit, but RTS outputs "LOW" upon detection of the stop
bit. (For period 1)
If SSR:RDRF is set (the specified number of data sets are received in received FIFO), RTS outputs "HIGH"
upon reception of data one bit before the stop bit. RTS outputs "LOW" after all data is read from received
FIFO. (For period 2)
Figure 3-6 Hardware flow control during data reception (with FIFO used)
(SMR:SBL=0, ESCR:ESBL=INV=PEN=L2=L1=L0=0)
Received data
ST
D0
D6
D7
SP
ST
D0
D6
D7
SP
ST
D0
RTS
RDRF
The entire data is
read from received
FIFO buffer.
Period
1
Period 2
<Notes>
When reception operation is disabled (RXE=0), the RTS signal is fixed to "LOW".
If both conditions below are satisfied when received FIFO is used and if the received idle state continues for more
than 8 baud rate clocks, RDRF is set to "1" but "LOW" is maintained for the RTS signal.
The received FIFO idle detection enable bit (FCR1:FRIIE) is "1".
The preset data amount is not received and some data remains in received FIFO.
Performing programmable resetting (SCR:UPCL=1) clears the RTS signal to "LOW".
June 20, 2014, FM3_MN706-00043-1v0-E
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35
CHAPTER 1-2: UART (Asynchronous Serial Interface)
4.Dedicated Baud Rate Generator
P E R I P H E R A L
M A N U A L
4. Dedicated Baud Rate Generator
As for the UART transmit/received clock source, either of the following can be selected.
- Dedicated baud rate generator (reload counter)
- An external clock input to the baud rate generator (reload counter)
Selecting the UART baud rate
Select one of the following two baud rates.
Baud rate obtained by dividing an internal clock using the dedicated baud rate
generator (reload counter)
This generator provides two internal reload counters, which support transmitting and receiving serial clocks respectively.
To select the baud rate, specify the 15-bit reload value using Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0).
Each reload counter divides an internal clock by the set value.
To set the clock source, select an internal clock (BGR1:EXT=0).
Baud rate obtained by dividing an external clock using the dedicated baud rate
generator (reload counter)
Use an external clock for the clock source of the reload counter.
To select the baud rate, specify the 15-bit reload value using Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0).
Each reload counter divides an external clock by the set value.
To set the clock source, select use of an external clock and the baud rate generator clock (BGR1:EXT=1).
This mode is designed for cases where an oscillator with a divided non-standard frequency is used.
<Notes>
Set the external clock (BGR1:EXT=1) while the reload counter is suspended (BGR1/0=15' h00).
If an external clock is selected (BGR1:EXT=1), its HIGH and LOW signals must have a width at least of two bus
clocks.
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
4.Dedicated Baud Rate Generator
P E R I P H E R A L
M A N U A L
4.1. Baud rate settings
The following explains how to set the baud rate, and also a result of serial clock frequency calculation.
Calculating the baud rate
Two 15-bit reload counters are set using the Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0).
The baud rate is obtained in the following formulas.
(1) Reload value
V = / b - 1
V : Reload value
b : Baud rate
: Bus clock frequency or external clock frequency
(2) Calculation example
To set the 16 MHz bus clock, use the internal clock, and set the 19200 bps baud rate, set the reload value as follows:
Reload value:
V = (16 × 1000000) / 19200 – 1 = 832
Therefore, the baud rate is:
b = (16 × 1000000) / (832 + 1) = 19208 bps
(3) Baud rate error
The baud rate error can be calculated by the following equation.
Error (%) = (Calculated value – Target value) / Target value 100
Example: To set the 20 MHz bus clock and 153600 bps target baud rate:
Reload value
=:(20 × 1000000) /153600-1 = 129
Buad rate (Calculated value) = (20 × 1000000) / (129 + 1) = 153846 (bps)
Error (%)
= (153846 - 153600) / 153600 × 100= 0.16 (%):
B = (16 × 1000000) / (832 + 1) = 19208 bps
<Notes>
If the reload value is set to "0", the reload counter is stopped.
If the reload value is an even number, in the received serial clock, the width of a "LOW" signal is longer than that of a
"HIGH" signal by one bus clock cycle. If the value is odd, the serial clock has the same "HIGH" and "LOW" signal
width.
Set the reload value to 4 or more. Note that data may not be received normally due to the baud rate error and reload
value setting.
For allowable baud rate range, consider the effect by a jitter of the clock input to the macro.
June 20, 2014, FM3_MN706-00043-1v0-E
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37
CHAPTER 1-2: UART (Asynchronous Serial Interface)
4.Dedicated Baud Rate Generator
P E R I P H E R A L
M A N U A L
Reload value and baud rate setting examples for each bus clock frequency
The following shows the reload values and baud rate setting examples.
Table 4-1 Reload values and baud rate setting examples
8 MHz
Baud rate
10 MHz
16 MHz
20 MHz
24 MHz
(bps)
Value
ERR
Value
ERR
Value
ERR
Value
ERR
Value
ERR
4M
-
-
-
-
-
-
4
0
5
0
2.5M
-
-
-
-
-
-
7
0
-
-
2M
-
-
4
0
7
0
9
0
11
0
1M
7
0
9
0
15
0
19
0
23
0
500000
15
0
19
0
31
0
39
0
47
0
460800
-
-
-
-
-
-
-
-
51
0.16
250000
31
0
39
0
63
0
79
0
95
0
230400
-
-
-
-
-
-
86
-0.22
103
0.16
153600
51
0.16
64
0.16
103
0.16
129
0.16
155
0.16
125000
63
0
79
0
127
0
159
0
191
0
115200
-
-
86
-0.22
138
-0.08
173
-0.22
207
0.16
76800
103
0.16
129
0.16
207
0.16
259
0.16
312
-0.16
57600
138
-0.08
173
-0.22
277
-0.08
346
0.06
416
-0.08
38400
207
0.16
259
0.16
416
-0.08
520
-0.03
624
0
28800
277
-0.08
346
<0.01
555
-0.08
693
0.06
832
0.03
19200
416
-0.08
520
-0.03
832
0.03
1041
-0.03
1249
0
10417
767
<0.01
959
<0.01
1535
<0.01
1919
<0.01
2303
<0.01
9600
832
0.04
1041
-0.03
1666
-0.02
2082
0.02
2499
0
7200
1110
<0.01
1388
<0.01
2221
<0.01
2777
<0.01
3332
<0.01
4800
1666
-0.02
2082
0.02
3332
<0.01
4166
<0.01
4999
0
2400
3332
<0.01
4166
<0.01
6666
<0.01
8332
<0.01
9999
0
1200
6666
<0.01
8332
<0.01
13332
<0.01
16666
<0.01
19999
0
600
13332
<0.01
16666
<0.01
26666
<0.01
-
-
-
-
300
26666
<0.01
-
-
-
-
-
-
-
-
Value: BGR1/0 register set value (decimal)
ERR: Baud rate error (%)
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
4.Dedicated Baud Rate Generator
P E R I P H E R A L
M A N U A L
Table 4-2 Reload values and baud rate setting examples (continued)
32MHz
Baud rate
40 MHz
48 MHz
72 MHz
(bps)
Value
ERR
Value
ERR
Value
ERR
Value
ERR
4M
7
0
9
0
11
0
17
0
2.5M
-
-
15
0
-
-
-
-
2M
15
0
19
2
23
0
35
0
1M
31
0
39
0
47
0
71
0
500000
63
0
79
0
95
0
143
0
460800
-
-
86
-0.22
103
0.16
155
0.16
250000
127
0
159
0
191
0
287
0
230400
-
-
173
-0.22
207
0.16
312
-0.16
153600
207
-0.16
259
0.16
312
-0.16
468
-0.05
125000
255
0
319
0
383
0
575
0
115200
277
0.08
346
0.06
416
-0.08
624
0
76800
416
0.08
520
-0.03
624
0
937
-0.05
57600
555
0.08
693
0.06
832
0.04
1249
0
38400
832
-0.04
1041
-0.03
1249
0
1874
0
28800
1110
-0.01
1388
<0.01
1666
-0.02
2499
0
19200
1666
0.02
2082
0.02
2499
0
3749
0
10417
3071
<0.01
3839
<0.01
4607
<0.01
6911
<0.01
9600
3332
-0.01
4166
<0.08
4999
0
7499
0
7200
4443
-0.01
5555
<0.01
6666
<0.01
9999
0
4800
6666
<0.01
8332
<0.01
9999
0.02
14999
0
2400
13332
<-0.01
16666
<0.01
19999
0
29999
0
1200
26666
<0.01
-
-
-
-
-
-
600
-
-
-
-
-
-
-
-
300
-
-
-
-
-
-
-
-
June 20, 2014, FM3_MN706-00043-1v0-E
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
4.Dedicated Baud Rate Generator
P E R I P H E R A L
M A N U A L
Allowable baud rate range for data reception
The following shows the range of baud rate error allowed for the destination to receive data.
Set the received baud rate error by using the following formulas to ensure that the value falls within the allowable range.
Figure 4-1 Allowable baud rate range for data reception
Sampling
UART transfer rate
Start
bit 0
bit1
bit7
Parity
Stop state
FL
Single data frame (11×FL )
Allowable MIN transfer rate
Start
bit0
bit1
bit7
Parity
Stop state
FLmin
Allowable MAX transfer rate
Start
bit0
bit1
bit7
Parity
Stop state
FLmax
As shown in Figure 4-1, after detection of the start bit, the sampling timing of received data is determined by the counter
set in the BGR1/0 register. Data can be received successfully if the bit sequence including the stop bit matches the
sampling timing.
If this applies to a reception of 11 bits, a theoretical explanation can be given in the following.
Assuming that the sampling timing margin is one bus clock (), the minimum allowable transfer rate (FLmin) is
determined as follows:
FLmin = (11bits × (V+1) - (V+1)/2 + 2)/ = (21V + 25)/2 (s)
V: Reload value, : Bus clock
Thus, the maximum baud rate that allows the destination to receive data (BGmax) is determined as follows.
BGmax = 11/FLmin = 22/(21V+25)
V: Reload value, : Bus clock
(bps)
When data is received at the maximum allowable transfer rate (FLmax), the starting point of the received 11th bit is
sampled.
Thus, the maximum allowable transfer rate (FLmax) is determined as follows:
V: Reload value, : Bus clock
10/11 × FLmax = (11bits × (V+1) – (V+1)/2 )/
FLmax = (21/20 × 11 × (V+1)/
Assuming that the sampling timing margin () is two clocks, the maximum allowable transfer rate (FLmax) is
determined as follows:
10/11× FLmax = (11bits × (V+1) – (V+1)/2 –
V: Reload value, : Bus clock
FLmax = (21/20 × 11 × (V+1) – 44/20)/ = (231V + 187)/20 (s) V: Reload value, : Bus clock
Accordingly, the minimum baud rate that allows the destination to receive data (BGmin) is determined as follows:
BGmin=11/FLmax=220/(231V+187)
40
CONFIDENTIAL
(bps)
V: Reload value, : Bus clock
MN706-00043-1v0-E, June 20, 2014
CHAPTER 1-2: UART (Asynchronous Serial Interface)
4.Dedicated Baud Rate Generator
P E R I P H E R A L
M A N U A L
From the above formulas for obtaining the minimum/maximum baud rate, the allowable error between UART and the
destination is obtained as follows.
Reload value (V) Maximum allowable baud rate error Minimum allowable baud rate error
3
0%
0
10
+2.98%
-3.08%
50
+4.37%
-4.40%
100
+4.56%
-4.58%
200
+4.66%
-4.67%
32767
+4.76%
-4.76%
<Note>
Reception accuracy depends on the number of bits per frame, bus clock, and reload value. The higher the bus clock and
frequency division ratio are, the higher the accuracy becomes.
External clock
Writing "1" to the EXT bit of the Baud Rate Generator Register (BGR) causes the baud rate generator to divide the
external clock's frequency.
<Note>
The external clock signal synchronizes with the internal clock on UART. Therefore, an external clock that does not allow
synchronization causes unstable operation.
Functions of reload counter
There are two types of reload counters: The transmission reload counter and the received reload counter, both
functioning as a dedicated baud rate generator. Each reload counter consists of a 15-bit register for the reload value, and
generates transmitting and receiving clocks from the external or internal clock.
Starting counting
When the reload value is written to the Baud Rate Generator Register1, 0 (BGR1 or BGR0), the reload counter starts
counting.
Restarting
The reload counter restarts counting in the following conditions.
Common to transmit and received reload counters
A programmable reset (SCR:UPCL bit)
Received reload counter
Detection of the start bit's falling edge in asynchronous mode
June 20, 2014, FM3_MN706-00043-1v0-E
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41
CHAPTER 1-2: UART (Asynchronous Serial Interface)
5.Setting Procedure and Program Flow in
Operation Mode 0 (Asynchronous Normal Mode)
P E R I P H E R A L
M A N U A L
5. Setting Procedure and Program Flow in
Operation Mode 0 (Asynchronous Normal Mode)
Operation mode 0 enables asynchronous bi-directional serial communications.
CPU-to-CPU connection
Select the bi-directional communication in operation mode 0 (normal mode). Connect two CPUs to each other as shown
in Figure 5-1 and Figure 5-2.
Figure 5-1 A connection example of bi-directional communications in UART operation mode 0 (with flow
control disabled)
SOT
SOT
SIN
SIN
SCK
SCK
CPU_1 (Master)
CPU_2 (Slave)
Figure 5-2 A connection example of bi-directional communications in UART operation mode 0 (with flow
control)
SOT
SOT
SIN
SIN
SCK
SCK
CTS
CTS
RTS
RTS
CPU_1 (Master)
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CONFIDENTIAL
CPU_2 (Slave)
MN706-00043-1v0-E, June 20, 2014
CHAPTER 1-2: UART (Asynchronous Serial Interface)
5.Setting Procedure and Program Flow in
Operation Mode 0 (Asynchronous Normal Mode)
P E R I P H E R A L
M A N U A L
Flowcharts
If FIFO is not used
Figure 5-3 An example of bidirectional communication flowchart (if FIFO is not used)
(Transmit side)
(Received side)
Start
Start
Set to the relevant
operation mode.
(Set to mode 0.)
Set the operation mode.
(So as to have it match
the setting on the
transmit side.)
Set the 1-byte data
in TDR and start
communication.
Send data.
No
RDRF=1
Yes
No
RDRF=1
Yes
Read and process
the received data.
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
Send data.
(ANS)
Read and process
the received data.
Send the 1-byte
data.
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
5.Setting Procedure and Program Flow in
Operation Mode 0 (Asynchronous Normal Mode)
P E R I P H E R A L
M A N U A L
If FIFO is used
Figure 5-4 An example of bidirectional communication flowchart (if FIFO is used)
(Transmit side)
(Received side)
Start
Start
Set the operation
mode.
(Set to mode 0.)
Set the operation
mode.
(Set to mode 0.)
- Enable the transmit/
received FIFO.
- Setting FBYTE
Set N bytes to transmit
FIFO.
- Enable the transmit/
received FIFO.
- Setting FBYTE
Send data.
No
RDRF=1
Yes
Set the FDRQ bit to "0".
Read and process the
FBYTE data.
Send back data.
No
RDRF=1
Set N bytes to transmit
FIFO.
Yes
Read and process the
FBYTE data.
44
CONFIDENTIAL
Set the FDRQ bit to "0".
MN706-00043-1v0-E, June 20, 2014
CHAPTER 1-2: UART (Asynchronous Serial Interface)
6.Setting Procedure and Program Flow in Operation Mode 1 (Asynchronous Multiprocessor Mode)
P E R I P H E R A L
M A N U A L
6. Setting Procedure and Program Flow in Operation Mode 1
(Asynchronous Multiprocessor Mode)
In operation mode 1 (multiprocessor mode), communications by master/slave connections with multiple
CPUs are enabled. Either the master or slave function is available.
CPU-to-CPU connection
In a master/slave type communications, as shown in Figure 6-1, the communications system is configured with two
common communication lines connected to the master CPU and multiple slave CPUs. UART can be used either as a
master or a slave.
Figure 6-1 A connection example for master/slave type communications on UART
SOT
SIN
Master CPU
SOT
SIN
SOT
Slave CPU #0
SIN
Slave CPU #1
Function selection
In master/slave type communications, select the operation mode and data transfer system, as shown in Table 6-1.
Table 6-1 Selection of master/slave type communications functions
Operation mode
Master mode
CPU
Address
transmit
and
reception
Data
transmit
and
reception
Mode 1
(A/D bit
transmit)
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CONFIDENTIAL
Slave mode
CPU
Mode 1
(A/D bit
reception)
Data
Parity
AD=1
+
7 or 8 bits
Address
OFF
AD=0
+
7 or 8 bits
Data
Stop state
bit direction
bit
One bit or
2 bits
LSB or
MSB first
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
6.Setting Procedure and Program Flow in Operation Mode 1 (Asynchronous Multiprocessor Mode)
P E R I P H E R A L
M A N U A L
<Note>
In operation mode 1, operate in word access mode for transmit/received data (TDR/RDR).
Communications procedure
Communications start when the master CPU transmits address data. Address data is a data set whose D8 bit is "1", and
used for selecting a slave CPU to communicate with. Each slave CPU judges the address as programmed, and
communicates with the master CPU if that address matches the assigned address.
Figure 6-2 and Figure 6-3 show flowcharts of master/slave type communications (in multiprocessor mode).
46
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MN706-00043-1v0-E, June 20, 2014
CHAPTER 1-2: UART (Asynchronous Serial Interface)
6.Setting Procedure and Program Flow in Operation Mode 1 (Asynchronous Multiprocessor Mode)
P E R I P H E R A L
M A N U A L
Flowcharts
If FIFO is not used
Figure 6-2 An example flowchart for master/slave type communications (if FIFO buffer is not used)
(Master CPU)
(Slave CPU)
Start
Start
Set the operation mode
(set to mode 1).
Set the operation mode.
(Set to mode 1.)
Set the SIN pin to serial
data input.
Set the SOT pin to serial
data output.
Set the SIN pin to serial
data input.
Set 7 or 8 data bits.
Set 1 or 2 stop bits.
Set 7 or 8 data bits.
Set 1 or 2 stop bits.
Enables transmit/
received operation.
Set the D8 bit to "1".
Received
byte
Enables transmit/
received operation.
D8 bit = 1
Transmits the slave
address.
No
Yes
The slave address
matches.
Set the D8 bit to "0".
No
Yes
Set the SOT pin to serial
data output.
Communicates with a
slave CPU.
Communications
completed?
No
Communicates with
the master CPU.
No
Communications
completed?
Yes
Communicates
with other slave
CPUs.
No
Yes
Yes
Disables transmit/
received operation.
End
June 20, 2014, FM3_MN706-00043-1v0-E
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47
CHAPTER 1-2: UART (Asynchronous Serial Interface)
6.Setting Procedure and Program Flow in Operation Mode 1 (Asynchronous Multiprocessor Mode)
P E R I P H E R A L
M A N U A L
If FIFO is used
Figure 6-3 An example flowchart for master/slave type communications (if FIFO buffer is used)
(Master CPU)
(Slave CPU)
Start
Start
Set the operation mode.
(Set to mode 1.)
Set the operation mode.
(Set to mode 1.)
- Enable the transmit/
received FIFO.
- Setting FBYTE
Enable the transmit/
received FIFO.
Set the AD bit to "1".
Set a slave address to
transmit FIFO and set
the FDRQ bit to "0".
Set FBYTE to "1".
Transmits the slave
address.
RDRF=1
No
Yes
AD = 1 and the
slave address
match.
Set the AD bit to "0".
No
Yes
Set N bytes in transmit
FIFO, and set the FDRQ bit
to "0".
Send data.
Received
FIFO full
Set the D8 bit to "0".
Read and process
the FBYTE data.
RDRF=1
Read and process
the FBYTE data.
48
CONFIDENTIAL
No
Yes
No
Yes
Set FBYTE to "N".
Send data.
Set N bytes in transmit FIFO,
and set the FDRQ bit to "0".
MN706-00043-1v0-E, June 20, 2014
CHAPTER 1-2: UART (Asynchronous Serial Interface)
7.UART (Asynchronous Serial Interface) Registers
P E R I P H E R A L
M A N U A L
7. UART (Asynchronous Serial Interface) Registers
This section provides a list of UART (Asynchronous Serial Interface) registers.
UART (Asynchronous Serial Interface) registers list
Table 7-1 UART (Asynchronous Serial Interface) register list
bit15
UART
FIFO
bit8
bit7
bit0
SCR (Serial Control Register)
SMR (Serial Mode Register)
SSR (Serial Status Register)
ESCR (Extended Communication Control Register)
RDR1/TDR1
(Transmit/Received Data Register 1)
RDR0/TDR0
(Transmit/Received Data Register 0)
BGR1 (Baud Rate Generator Register 1)
BGR0 (Baud Rate Generator Register 0)
FCR1 (FIFO Control Register 1)
FCR0 (FIFO Control Register 0)
FBYTE2 (FIFO2 Byte Register)
FBYTE1 (FIFO1 Byte Register)
Table 7-2 UART (Asynchronous Serial Interface) bit assignment
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SCR/
SMR
UPCL
-
-
RIE
TIE
TBIE
RXE
TXE
MD2
MD1
MD0
-
SBL
BDS
-
SOE
SSR/
ESCR
REC
-
PE
FRE
ORE RDRF TDRE
TBI FLWEN ESBL
INV
PEN
P
L2
L1
L0
D8
(AD)
D7
D6
D5
D4
D3
D2
D1
D0
B8
B7
B6
B5
B4
B3
B2
B1
B0
-
FLST
FLD
FSET
FCL2 FCL1
FE2
FE1
FD7
FD6
FD5
FD4
FD3
FD1
FD0
TDR/
(RDR)
-
BGR1/
BGR0
EXT
B14
B13
FCR1/
FCR0
-
-
-
B12
B11
B10
B9
FLSTE FRIIE FDRQ FTIE FSEL
FBYTE2/
FD15 FD14 FD13 FD12 FD11 FD10
FBYTE1
FD9
FD8
FD2
Operation mode
UART (Asynchronous Serial Interface) operates in two different modes. The Serial Mode Register (SMR) determines
the mode to be enabled, depending on its setting, MD2, MD1 or MD0.
Table 7-3 UART (Asynchronous Serial Interface) operation modes
Operation mode
MD2 MD1 MD0
Type
0
0
0
0
UART0 (asynchronous normal mode)
1
0
0
1
UART1 (asynchronous multiprocessor mode)
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
7.UART (Asynchronous Serial Interface) Registers
P E R I P H E R A L
M A N U A L
7.1. Serial Control Register (SCR)
The Serial Control Register (SCR) can perform transmit/received enable/disable, transmit/received
interrupt enable/disable, transmit bus idle interrupt enable/disable and UART reset operations.
bit
Field
Attribute
Initial
value
15
UPCL
R/W
14
-
13
-
12
RIE
R/W
11
TIE
R/W
10
TBIE
R/W
9
RXE
R/W
8
TXE
R/W
0
-
-
0
0
0
0
0
7
...
(SMR)
0
[bit15] UPCL: Programmable Clear bit
Initializes the UART internal state.
If set to "1",
UART is reset directly (software reset). However, the current register settings are maintained. The transmit or
received state is disconnected immediately.
The baud rate generator reloads the BGR1/0 register value and restarts operation.
All of transmit/received interrupt factors (SSR:PE, FRE, ORE, RDRF, TDRE and TBI) are initialized (to
0b000011).
RTS signal is cleared to "LOW".
If set to "0", it has no effect on operation.
"0" is always read during reading.
bit
Description
At writing
0
No effect on opreration.
1
Programmable clear
At reading
"0" is always read.
<Notes>
Disable an interrupt first, and then execute the programmable clear instruction.
If the FIFO operation is used, disable it (FCR0:FE[2:1]=00) first and then execute Programmable Clear.
[bit14:13] - : Unused bits
These bits' values are undefined when read.
These bits have no effect when written.
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
7.UART (Asynchronous Serial Interface) Registers
P E R I P H E R A L
M A N U A L
[bit12] RIE: Received interrupt enable bit
This bit enables or disables an output of received interrupt request to the CPU.
If the RIE bit and the received data flag bit (SSR:RDRF) are "1", or if any of the error flag bits (SSR:PE, ORE or
FRE) is "1", a received interrupt request is output.
bit
Description
0
Disables the received interrupt.
1
Enables the received interrupt.
[bit11] TIE: Transmit interrupt enable bit
This bit enables or disables an output of Transmit Interrupt Request to the CPU.
If the TIE bit and SSR:TDRE bit are "1", a Transmit Interrupt Request is output.
bit
Description
0
Disables a transmit interrupt.
1
Enables a transmit interrupt.
[bit10] TBIE: Transmit bus idle interrupt enable bit
This bit enables or disables an output of transmit bus idle interrupt request to the CPU.
If the TBIE bit and TBI bit are "1", a transmit bus idle interrupt request is output.
bit
Description
0
Disables the transmit bus idle interrupt.
1
Enables the transmit bus idle interrupt.
[bit9] RXE: Received operation enable bit
Enables or disables UART received operation.
bit
Description
0
Disables data received.
1
Enables data received.
<Notes>
Reception is not started unless the falling edge of the start bit (in NRZ format, when ESCR:INV=0) is input even if
reception is enabled (RXE=1). (In the inverted NRZ format (ESCR:INV=1), reception is not started unless the rising
edge is input).
If data reception is disabled (RXE=0) during the received operation, the current data reception is stopped
immediately.
When the received operation is disabled (RXE=0), the RTS signal is fixed to "LOW".
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
7.UART (Asynchronous Serial Interface) Registers
P E R I P H E R A L
M A N U A L
[bit8] TXE: Transmission operation enable bit
Enables or disables the UART transmission operation.
bit
Description
0
Disables the transmission.
1
Enables the transmission.
<Note>
If data transmission is disabled (TXE=0) during the transmission operation, the current data transmission is stopped
immediately.
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7.UART (Asynchronous Serial Interface) Registers
P E R I P H E R A L
M A N U A L
7.2. Serial Mode Register (SMR)
The Serial Mode Register (SMR) is used to set the operation mode, transfer direction, data length and to
select the stop bit length as well as to enable/disable output of serial data to their pins.
bit
Field
Attribute
Initial
value
15
...
(SCR)
8
7
MD2
R/W
6
MD1
R/W
5
MD0
R/W
4
Reseved
-
3
SBL
R/W
2
BDS
R/W
1
Reserved
-
0
SOE
R/W
0
0
0
-
0
0
-
0
[bit7:5] MD2, MD1, MD0: Operation mode set bit
Set operation mode of the Asynchronous Serial Interface..
* This chapter explains the registers and their operation in operation mode 0 (asynchronous normal mode) and in
operation mode 1 (asynchronous multiprocessor mode).
bit7
bit6
bit5
Description
0
0
0
Operation mode 0 (asynchronous normal mode)
0
0
1
Operation mode 1 (asynchronous multiprocessor mode)
0
1
0
Operation mode 2 (clock sync mode)
0
1
1
Operation mode 3 (LIN communication mode)
1
0
0
Operation mode 4 (I2C mode)
<Notes>
Any bit setting other than above is inhibited.
To switch the current operation mode, issue a programmable clear instruction (SCR:UPCL=1) and switch the
operation mode continuously.
After the operation mode has been switched, set each register correctly.
[bit4] Reserved: Reserved bit
This bit value is undefined when read.
This bit has no effect when written.
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
7.UART (Asynchronous Serial Interface) Registers
P E R I P H E R A L
M A N U A L
[bit3] SBL: Stop bit length select bit
This bit sets a stop bit length (the frame end mark of the transmit data).
bit
Description
ESCR:ESBL=0
1 bit
ESCR:ESBL=1
3 bits
ESCR:ESBL=0
2 bits
ESCR:ESBL=1
4 bits
0
1
<Notes>
In the reception operation, only the first bit of the stop bit data is detected.
Always set this bit when transmission is disabled (SCR:TXE=0).
[bit2] BDS: Transfer direction select bit
Specifies to transmit the least significant bit of the transmit serial data first (LSB first; BDS=0) or the most significant
bit first (MSB first; BDS=1).
bit
Description
0
LSB first (The least significant bit is first transferred.)
1
MSB first (The most significant bit is first transferred.)
<Note>
Set this bit when transmission and reception are disabled (SCR:TXE=SCR:RXE=0).
[bit1] Reserved: Reserved bit
The read value is "0". Be sure to write "0".
[bit0] SOE: Serial data output enable bit
This bit enables or disables a serial data output.
bit
Description
0
Disables a serial data output.
1
Enables a serial data output.
<Note>
If this bit is used as the SOT pin, the GPIO must also be set.
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7.UART (Asynchronous Serial Interface) Registers
P E R I P H E R A L
M A N U A L
7.3. Serial Status Register (SSR)
The Serial Status Register (SSR) is used to check the current transmit/received state, check the
received error flag, and clears the received error flag.
bit
Field
Attribute
Initial
value
15
REC
R/W
14
-
13
PE
R
12
FRE
R
11
ORE
R
10
RDRF
R
9
TDRE
R
8
TBI
R
0
-
0
0
0
0
1
1
7
...
0
(ESCR)
[bit15] REC: Received error flag clear bit
This bit clears the PE, FRE and ORE flags of the Serial Status Register (SSR).
Description
bit
At writing
At reading
0
No effect on operation.
1
Clears the received error flag (PE, FRE, ORE).
"0" is always read.
[bit14] - : Unused bit
This bit value is undefined when read.
This bit has no effect when written.
[bit13] PE: Parity error flag bit (only functions in operation mode 0)
If a parity error occurs during data received with ESCR:PEN=1, this bit is set to "1". This is cleared if the REC bit of
Serial Status Register (SSR) is set to "1".
If the PE bit and SCR:RIE bit are "1", a received interrupt request is output.
If this flag is set, data in the Received Data Register (RDR) is invalid.
If this flag is set when received FIFO is used, the received FIFO enable bit is cleared and the received data is not
stored in received FIFO.
bit
Description
0
No parity error occurred.
1
A parity error occurred.
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
7.UART (Asynchronous Serial Interface) Registers
P E R I P H E R A L
M A N U A L
[bit12] FRE: Framing error flag bit
If a framing error occurs during data reception, this bit is set to "1". This is cleared if the REC bit of Serial Status
Register (SSR) is set to "1".
If the FRE bit and SCR:RIE bit are "1", a received interrupt request is output.
If this flag is set, data in the Received Data Register (RDR) is invalid.
If this flag is set when received FIFO is used, the received FIFO enable bit is cleared and the received data is not
stored in received FIFO.
bit
Description
0
No framing error occurred.
1
A framing error occurred.
[bit11] ORE: Overrun error flag bit
If an overrun occurs during data reception, this bit is set to "1". This is cleared if the REC bit of Serial Status Register
(SSR) is set to "1".
If the ORE and SCR:RIE bits are "1", a received interrupt request is output.
If this flag is set, data in the Received Data Register (RDR) is invalid.
If this flag is set when received FIFO is used, the received FIFO enable bit is cleared and the received data is not
stored in received FIFO.
bit
Description
0
No overrun error occurred.
1
An overrun error occurred.
[bit10] RDRF: Received data full flag bit
This flag shows the state of the Received Data Register (RDR).
When the received data is loaded in the RDR, this bit is set to "1". When data is read from the Received Data Register
(RDR), this bit is cleared to "0".
If the RDRF bit and SCR:RIE bit are "1", a received interrupt request is output.
If the received FIFO is used and if a certain count of data is received by the received FIFO, the RDRF bit is set to "1".
If received FIFO is used, if both of the following conditions are satisfied, and if the Received Idle state continues
more than 8 baud rate clocks, the RDRF bit is set to "1".
The received FIFO idle detection enable bit (FCR1:FRIIE) is "1".
The preset data amount is not received and some data remains in received FIFO.
If the RDR data is read during counting of 8 clocks, this counter is reset to "0", and counting for 8 clocks is restarted.
If the received FIFO is used and if this buffer is emptied, this bit is cleared to "0".
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bit
Description
0
The Received Data Register (RDR) is empty.
1
The Received Data Register (RDR) contains data.
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7.UART (Asynchronous Serial Interface) Registers
P E R I P H E R A L
M A N U A L
[bit9] TDRE: Transmit data empty flag bit
This flag shows the state of Transmit Data Register (TDR).
If transmit data is written in the TDR, this bit is set to "0" to indicate that the TDR contains valid data. When data is
loaded to the transmit shift register and when the transmission is started, this bit is set to "1" to indicate that the TDR
does not have the valid data.
If the TDRE bit and SCR:TIE bit are "1", a transmit interrupt request is output.
When the UPCL bit of the Serial Control Register (SCR) is set to "1", the TDRE bit is set to "1".
For the TDRE bit set/reset timing when transmit FIFO is used, see "2.4 Interrupt and flag set timing when transmit FIFO
is used".
bit
Description
0
The Transmit Data Register (TDR) contains data.
1
The Transmit Data Register is empty.
[bit8] TBI: Transmit bus idle flag
This bit indicates that UART is not transmitting data.
When transmit data is written in the Transmit Data Register (TDR), this bit is set to "0".
If the Transmit Data Register is empty (TDRE=1) and not transmitting data, this bit is set to "1".
When the UPCL bit of the Serial Control Register (SCR) is set to "1", the TBI bit is set to "1".
If this bit is "1" and if the transmit bus idle interrupt is enabled (SCR:TBIE=1), a transmit interrupt request is output.
bit
Description
0
During data transmission
1
No data transmission
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7.UART (Asynchronous Serial Interface) Registers
P E R I P H E R A L
M A N U A L
7.4. Extended Communication Control Register (ESCR)
The Extended Communication Control Register (ESCR) is used to set a transmit/received data length,
enable/disable a parity bit, select a parity bit, invert the serial data format and set stop bit length
selection.
bit
Field
Attribute
Initial
value
15
...
(SSR)
8
7
FLWEN
R/W
6
ESBL
R/W
5
INV
R/W
4
PEN
R/W
3
P
R/W
2
L2
R/W
1
L1
R/W
0
L0
R/W
0
0
0
0
0
0
0
0
[bit7] FLWEN: Flow control enable bit
Selects to enable or disable the hardware flow control operation.
bit
Description
0
Disables hardware flow control.
1
Enables hardware flow control.
<Notes>
Set this bit when data transmission and reception is disabled (SCR:TXE=0, RXE=0).
Set this bit to "1" only when the hardware flow control is desired.
[bit6] ESBL: Extension stop bit length select bit
This bit sets a stop bit length (the frame end mark of the transmit data).
bit
Description
SMR:SBL=0
1 bit
SMR:SBL=1
2 bits
SMR:SBL=0
3 bits
SMR:SBL=1
4 bits
0
1
<Notes>
In the reception operation, only the first bit of the stop bit data is detected.
Always set this bit when transmission is disabled (SCR:TXE=0).
[bit5] INV: Inverted serial data format bit
Selects NRZ or inverted NRZ for the serial data format.
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bit
Description
0
NRZ format
1
Inverted NRZ format
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7.UART (Asynchronous Serial Interface) Registers
P E R I P H E R A L
M A N U A L
[bit4] PEN: Parity enable bit (only functions in operation mode 0)
Sets to add (for transmit) and detect (for reception) a parity bit or not to.
bit
Description
0
Disables parity.
1
Enables parity.
<Note>
In operation mode 1, this bit is internally fixed at "0".
[bit3] P: Parity select bit (only functions in operation mode 0)
When set to enable parity (ESCR:PEN=1, this bit is set to either odd-number parity "1" or even-number parity "0".
bit
Description
0
Even-number parity
1
Odd-number parity
[bit2:0] L2, L1, L0: Data length select bit
These bits set a length of transmit/received data.
- If set to "0b000", the data length is set to eight bits.
- If set to "0b001", the data length is set to five bits.
- If set to "0b010", the data length is set to six bits.
- If set to "0b011", the data length is set to seven bits.
- If set to "0b100", the data length is set to nine bits.
bit2
bit1
bit0
Description
0
0
0
8-bit length
0
0
1
5-bit length
0
1
0
6-bit length
0
1
1
7-bit length
1
0
0
9-bit length
<Notes>
Any setting other than the above is inhibited.
In operation mode 1, set the data length to seven or eight bits. Any other setting is inhibited.
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7.UART (Asynchronous Serial Interface) Registers
P E R I P H E R A L
M A N U A L
7.5. Received Data Register/Transmit Data Register (RDR/TDR)
The Received and Transmit Data Registers are allocated at the same address. This register functions as
the Received Data Register when data is read from it. This register operates as the Transmit Data
Register when data is written in it.
When the FIFO operation is enabled, the RDR/TDR address functions as the FIFO read/write address.
Received Data Register (RDR)
bit
Field
Attribute
Initial
value
15
...
9
8
D8
R
7
D7
R
0
0
6
D6
R
5
D5
R
4
D4
R
3
D3
R
2
D2
R
1
D1
R
0
D0
R
0
0
0
0
0
0
0
The Received Data Register (RDR) is a 9-bit data buffer register for serial data reception.
When serial data signals are sent to the Serial Input pin (SIN), they are converted by a shift register and stored in the
Received Data Register (RDR).
The upper bits are set to "0" according to the data length, as follows.
Data length
D8
D7
D6
D5
D4
D3
D2
D1
D0
9 bits
X
X
X
X
X
X
X
X
X
8 bits
0
X
X
X
X
X
X
X
X
7 bits
0
0
X
X
X
X
X
X
X
6 bits
0
0
0
X
X
X
X
X
X
5 bits
0
0
0
0
X
X
X
X
X
(X represents the received data bit.)
When the received data is stored in the Received Data Register (RDR), the received data full flag bit (SSR:RDRF) is
set to "1". If a received interrupt is enabled (SSR:RIE=1), a received interrupt request is generated.
The Received Data Register (RDR) must be read only when the received data full flag bit (SSR:RDRF) is "1". When
data is read from the Received Data Register (RDR), the received data full flag bit (SSR:RDRF) is cleared to "0"
automatically.
If a received error occurs (when SSR:PE, ORE or FRE is "1"), data in the Received Data Register (RDR) becomes
invalid.
In operation mode 1 (multiprocessor mode), 7-bit or 8-bit long operation takes place and the received AD bit is stored
in the D8 bit.
For 9-bit long data transfer and in operation mode 1, data must be read from RDR by 16-bit data accessing.
<Notes>
If the Received FIFO is used and if the preset amount of data is received in the Received FIFO buffer, SSR:RDRF is
set to "1".
If the received FIFO is used and if this buffer is emptied, the SSR:RDRF bit is cleared to "0".
If a received error occurs when received FIFO is used (SSR:PE, ORE, or FRE is "1"), the received FIFO enable bit is
cleared and the received data is not stored in the received FIFO buffer.
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7.UART (Asynchronous Serial Interface) Registers
P E R I P H E R A L
M A N U A L
Transmit Data Register (TDR)
bit
Field
Attribute
Initial
value
15
...
9
8
D8
W
7
D7
W
6
D6
W
5
D5
W
4
D4
W
3
D3
W
2
D2
W
1
D1
W
0
D0
W
1
1
1
1
1
1
1
1
1
The Transmit Data Register (TDR) is a 9-bit data buffer register for serial data transmission.
If data transmission is enabled (SCR:TXE=1) and if the transmit data is written in the Transmit Data Register (TDR),
the transmit data is transferred to the Transmit Shift Register. The transmit data is then converted into serial data and
sent out from the serial data output pin (SOT).
The upper bits are sequentially made invalid according to the data length as follows.
Data length
D8
D7
D6
D5
D4
D3
D2
D1
D0
9 bits
X
X
X
X
X
X
X
X
X
8 bits
Invalid
X
X
X
X
X
X
X
X
7 bits
Invalid Invalid
X
X
X
X
X
X
X
6 bits
Invalid Invalid Invalid
X
X
X
X
X
X
5 bits
Invalid Invalid Invalid Invalid
X
X
X
X
X
When the transmit data is written in the Transmit Data Register (TDR), the transmit data empty flag (SSR:TDRE) is
cleared to "0".
When the transmit data is transferred to the transmit shift register and data transmission is started, and if transmit
FIFO is disabled or if transmit FIFO is empty, the transmit data empty flag (SSR:TDRE) is set to "1".
If the transmit data empty flag (SSR:TDRE) is "1", transmit data can be written. If a transmit interrupt is enabled, a
transmit interrupt occurs. Perform transmit data write after a transmit interrupt is generated or when the transmit data
empty flag (SSR:TDRE) is "1".
If the transmit data empty flag (SSR:TDRE) is "0" and transmit FIFO is disabled or the transmit FIFO buffer is full,
no transmit data can be written.
In operation mode 1 (multiprocessor mode), 7-bit or 8-bit long operation takes place and the AD bit is sent by writing
to the D8 bit.
For 9-bit long data transfer and in operation mode 1, data must be written in TDR by 16-bit data accessing.
<Notes>
The Transmit Data Register is a write-only register. While the Received Data Register is a read-only register. As the
transmission and received registers are allocated at the same address, the write and read values differ from each other.
Therefore, the INC/DEC instruction and other read-modify-write (RMW) instructions cannot be used.
For the transmit data empty flag (SSR:TDRE) set timing when transmit FIFO is used, see "2.4 Interrupt and flag set
timing when transmit FIFO is used".
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7.UART (Asynchronous Serial Interface) Registers
P E R I P H E R A L
M A N U A L
7.6. Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0)
Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0) are used to set a frequency division ratio of
serial clocks. Also, an external clock can be selected as the clock source of the reload counter.
bit
15 14 13
12
11
10
9
8
Field EXT
(BGR1)
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial
0
0
0
0
0
0
0
0
value
7
6
5
4
3
2
1
0
(BGR0)
R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
The Baud Rate Generator Registers are used to set a frequency division ratio of serial clocks.
The BGR1 register corresponds to the upper bits, and the BGR0 register corresponds to the lower bits. The reload
value to be counted can be written, and the BGR1/BGR0 set value can be read.
When the reload value is written in Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0), the reload counter
starts its counting.
The EXT bit (bit15) specifies to use the clock source of reload counter as the internal clock or the external clock. If
EXT=0 is set, an internal clock is used. If EXT=1 is set, an external clock is used.
[bit15] EXT: External clock select bit
bit
Description
0
Uses the internal clock.
1
Uses an external clock.
[bit14:8] BGR1: Baud Rate Generator Register 1
bit14:8
Description
Write
Writes data in bit8 to 14 of reload counter.
Read
Read the BGR1 set value.
[bit7:0] BGR0: Baud Rate Generator Register 0
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bit7:0
Description
Write
Write data in bit0 to 7 of reload counter.
Read
Read the BGR0 set value.
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P E R I P H E R A L
M A N U A L
<Notes>
Data must be written in the Baud Rate Generator Registers (BGR1 and BGR0) by 16-bit data accessing.
If the current values of Baud Rate Generator Registers (BGR1, BGR0) are changed, the new values are reloaded only
after the counter value has reached "15h00". In order to validate the new set values immediately, change the
BGR1/BGR0 set values and execute the programmable clear (UPCL).
If the reload value is an even number, in the received serial clock, the width of a "LOW" signal is longer than that of a
"HIGH" signal by one bus clock cycle. If the value is an odd number, the width of a LOW signal is the same as that of
a HIGH signal.
Set a value "4" or higher to BGR1/BGR0. Note that data may not be received successfully depending on the baud rate
error and reload value settings.
To change the setting to an external clock (EXT=1) while the Baud Rate Generator is running, write "0" to the Baud
Rate Generators 1 and 0 (BGR1, BGR0), execute Programmable Clear (UPCL) and then set for an external clock
(EXT=1).
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7.UART (Asynchronous Serial Interface) Registers
P E R I P H E R A L
M A N U A L
7.7. FIFO Control Register 1 (FCR1)
The FIFO Control Register (FCR1) is used to set the FIFO test, select the transmit or received FIFO,
enable the transmit FIFO interrupt, and control the interrupt flag.
bit
Field
Attribute
Initial
value
15
14
Reserved
-
13
12
FLSTE
R/W
11
FRIIE
R/W
10
FDRQ
R/W
9
FTIE
R/W
8
FSEL
R/W
0
0
1
0
0
7
...
0
(FCR0)
[bit15:13] Reserved bits
The read value is "0". Be sure to write "0".
[bit12] FLSTE: Re-transmission data lost detect enable bit
This bit enables the FIFO re-transmission data lost flag (FLST) detection.
If set to "0", the FLST bit detection is disabled.
If set to "1", the FLST bit detection is enabled.
bit
Description
0
Disables the Data Lost detection.
1
Enables the Data Lost detection.
<Note>
If you wish to set this bit to "1", set the FSET bit to "1" first, and then set this bit to "1".
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M A N U A L
[bit11] FRIIE: Received FIFO idle detection enable bit
This bit sets to detect the received idle state if the received FIFO contains valid data and if it continues more than 8-bit
hours. If the received interrupt is enabled (SCR:RIE=1), a received interrupt is generated when the received idle state is
detected.
If set to "0", a detection of received idle state is disabled.
If set to "1", a detection of received idle state is enabled.
bit
Description
0
Disables the received FIFO idle detection.
1
Enables the received FIFO idle detection.
<Note>
In case of using Received FIFO, set this bit to "1".
[bit10] FDRQ: Transmit FIFO data request bit
This bit requests for the transmit FIFO data.
If this bit is "1", the transmit data is being requested. At this time, if a transmit FIFO interrupt is enabled (FTIE=1), a
transmit FIFO interrupt request is output.
The FDRQ bit is set when:
The FBYTE (for transmission) is "0" (Transmit FIFO is empty).
The FDRQ bit is reset when:
This bit is set to "0".
Transmit FIFO is filled with data.
bit
Description
0
Does not request for the transmit FIFO data.
1
Requests for the transmit FIFO data.
<Notes>
"0" written when transmit FIFO is enabled is valid.
If the FBYTE (for transmission) is "0", this bit cannot be set to "0".
If this bit is set to "1", it has no effect on the operation.
If a read-modify-write instruction is issued, "1" is read.
[bit9] FTIE: Transmit FIFO interrupt enable bit
This bit enables a transmit FIFO interrupt. If this bit is set to "1", an interrupt occurs when the FDRQ bit is set to "1".
bit
Description
0
Disables the transmit FIFO interrupt.
1
Enables the transmit FIFO interrupt.
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[bit8] FSEL: FIFO select bit
This bit selects the transmit or received FIFO.
If set to "0", the transmit FIFO is assigned to FIFO1, and the received FIFO is assigned to FIFO2.
If set to "1", the transmit FIFO is assigned to FIFO2, and the received FIFO is assigned to FIFO1.
bit
Description
0
Transmit FIFO:FIFO1; Received FIFO:FIFO2
1
Transmit FIFO:FIFO2; Received FIFO:FIFO1
<Notes>
This bit is not cleared by the FIFO Reset (FCR0:FCL[2:1]=11).
To change this bit state, first disable the FIFO operation (FCR0:FE[2:1]=00).
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7.UART (Asynchronous Serial Interface) Registers
P E R I P H E R A L
M A N U A L
7.8. FIFO Control Register 0 (FCR0)
The FIFO Control Register 0 (FCR0) is used to enable/disable the FIFO operation, reset FIFO, save the
read pointer, and set the data re-transmission.
bit
Field
Attribute
Initial
value
15
...
8
(FCR1)
7
-
6
FLST
R
5
FLD
R/W
4
FSET
R/W
3
FCL2
R/W
2
FCL1
R/W
1
FE2
R/W
0
FE1
R/W
0
0
0
0
0
0
0
0
[bit7] - : Unused bit
When read, always "0" is read.
When written, always set this bit to "0".
[bit6] FLST: FIFO re- transmit data lost flag bit
This bit shows that the re- transmit data of transmit FIFO has been lost.
The FLST bit is set when:
Data is written (overwritten) in the FIFO buffer when the FLSTE bit of FIFO Control Register 1 (FCR1) is "1" and
the write pointer for transmit FIFO matches the read pointer which has been saved by the FSET bit.
The FLST bit is reset when:
FIFO is reset (FCL bit is set to "1").
The FSET bit is set to "1".
If this bit is set to "1", the data identified by the read pointer (saved by the FSET bit) is overwritten. Therefore, the FLD
bit cannot set the data re-transmission even if an error has occurred. If this bit is set to "1" and if you wish to re-transmit
data, first reset FIFO. Then, write data in the FIFO buffer again.
bit
Description
0
No Data Lost has occurred.
1
Data Lost has occurred.
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M A N U A L
[bit5] FLD: FIFO pointer reload bit
This bit reloads the data, being saved in transmit FIFO by the FSET bit, to the reload pointer. This bit can be used to
re-transmit data after a communication error or others have occurred.
When the re-transmission setting has finished, this bit is set to "0".
bit
Description
0
Not reloaded
1
Reloaded
<Notes>
If this bit is "1", data is being reloaded in the read pointer. Therefore, data writing except for FIFO reset is disabled.
When FIFO is enabled or when data is being transmitted, this bit cannot be set to "1".
After you have set the TIE bit and TBIE bit to "0", set this bit to "1". After you have enabled transmit FIFO, set the
SCR:TIE bit and SCR:TBIE bit to "1".
[bit4] FSET: FIFO pointer save bit
This bit saves the transmit FIFO read pointer.
If the read pointer value is saved before being transmitted and if the FLST bit is "0", the data can be re-transmitted even
if a communication error or others have occurred.
If set to "1", the current read pointer value is saved.
If set to "0", it has no effect.
bit
Description
At writing
0
Not saved
1
FIFO2 is reset.
At reading
"0" is always read.
<Note>
This bit can be set to "1" only when the transmission byte count (FBYTE) is "0".
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M A N U A L
[bit3] FCL2: FIFO2 reset bit
This bit resets the FIFO2 value.
If this bit is set to "1", the FIFO2 internal state is initialized.
Only the FCR1:FLST bit is initialized, and the other bits of FCR1/FCR0 registers are kept.
bit
Description
At writing
0
No effect on operation.
1
FIFO2 is reset.
At reading
"0" is always read.
<Notes>
Disable the transmit and reception first, and then reset FIFO2.
Set the transmit FIFO interrupt enable bit to "0" before the execution.
The valid data count of the FBYTE2 register is set to "0".
[bit2] FCL1: FIFO1 reset bit
This bit resets the FIFO1 state.
If this bit is set to "1", the FIFO1 internal state is initialized.
Only the FCR1:FLST bit is initialized, and the other bits of FCR1/FCR0 registers are kept.
bit
Description
At writing
0
No effect on operation.
1
FIFO1 is reset.
At reading
"0" is always read.
<Notes>
Disable the transmit and reception first, and then reset FIFO1.
Set the transmit FIFO interrupt enable bit to "0" before the execution.
The valid data count of the FBYTE1 register is set to "0".
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7.UART (Asynchronous Serial Interface) Registers
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[bit1] FE2: FIFO2 operation enable bit
This bit enables or disables the FIFO2 operation.
To use the FIFO2 operation, set this bit to "1".
If FIFO2 is set as transmit FIFO (FCR1:FSEL=1) and if data exists in FIFO2 when this bit is set to "1", the data
transmission starts immediately when the UART is enabled to transmit data (SCR:TXE=1). During this time, set both
SCR:TIE bit and SCR:TBIE bit to "0". Then, set this bit to "1" and set both SCR:TIE bit and SCR:TBIE bit to "1".
If received FIFO is selected by the FSEL bit and if a received error has occurred, this bit is cleared to "0". This bit
cannot be set to "1" until the received error is cleared.
If FIFO2 is used as transmit FIFO, this bit must be set to "1" or "0" when the transmit buffer is empty
(SSR:TDRE=1).
If FIFO2 is used as received FIFO, this bit must be set to "0" when the received buffer is empty (SSR:RDRF=0) and
no valid data exists in received FIFO (FBYTE2=0) after reception is disabled (SCR:RXE=0).
If FIFO2 is used as received FIFO, this bit must be set to "1" when the received buffer is empty (SSR:RDRF=0) after
reception is disabled (SCR:RXE=0).
The FIFO2 state is held even if the FIFO2 operation is disabled.
bit
Description
0
Disables the FIFO2 operation.
1
Enables the FIFO2 operation.
[bit0] FE1: FIFO1 operation enable bit
This bit enables or disables the FIFO1 operation.
To use the FIFO1 operation, set this bit to "1".
When the FIFO1 is set as transmit FIFO (FCR1:FSEL=0) and if data exists in FIFO1 when this bit is set to "1", the
data transmission starts immediately when the UART is set to enable data transmission (SCR:TXE=1). During this
time, set both SCR:TIE bit and SCR:TBIE bit to "0". Then, set this bit to "1" and set both TIE bit and SCR:TBIE bit
to "1".
If received FIFO is selected by the FSEL bit and if a received error has occurred, this bit is cleared to "0". This bit
cannot be set to "1" until the received error is cleared.
If FIFO1 is used as transmit FIFO, this bit must be set to "1" or "0" when the transmit buffer is empty
(SSR:TDRE=1).
If FIFO1 is used as received FIFO, this bit must be set to "0" when the received buffer is empty (SSR:RDRF=0) and
no valid data exists in received FIFO (FBYTE2=0) after reception is disabled (SCR:RXE=0).
If FIFO1 is used as received FIFO, this bit must be set to "1" when the received buffer is empty (SSR:RDRF=0) after
reception is disabled (SCR:RXE=0).
The FIFO1 state is held even if the FIFO1 operation is disabled.
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bit
Description
0
Disables the FIFO1 operation.
1
Enables the FIFO1 operation.
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
7.UART (Asynchronous Serial Interface) Registers
P E R I P H E R A L
M A N U A L
7.9. FIFO Byte Register (FBYTE)
The FIFO Byte Register (FBYTE) indicates the effective data count in the FIFO buffer. Also, this register
can be used to generate a received interrupt when certain number of data sets are received in the
received FIFO.
bit
15 14 13
12
11
10
9
8
Field
(FBYTE2)
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial
0
0
0
0
0
0
0
0
value
7
6
5
4
3
2
1
0
(FBYTE1)
R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
The FBYTE register indicates the effective data count of data written from or received in FIFO. The following shows the
settings of the FCR1:FSEL bit.
Table 7-4 Display of data count
FSEL
FIFO selection
Data count display
0
FIFO2: Received FIFO, FIFO1:Transmit FIFO
FIFO2:FBYTE2, FIFO1:FBYTE1
1
FIFO2: Transmit FIFO, FIFO1:Received FIFO
FIFO2:FBYTE2, FIFO1:FBYTE1
The initial value of data transfer count is "0x08" for the FBYTE register.
Set a data count to flag a received interrupt for the FBYTE register of received FIFO. If this specified transfer count
matches the FBYTE register display, the receive data full flag bit (RDRF) is set to "1".
If both conditions below are satisfied and if the received idle state continues for more than 8 baud rate clocks, the
receive data full flag bit (RDRF) is set to "1".
The received FIFO idle detection enable bit (FRIIE) is "1".
The number of data sets stored in the received FIFO does not reach the transfer count.
If the RDR data is read during counting of 8 clocks, this counter is reset to "0", and counting for 8 clocks is restarted.
If received FIFO is disabled, this counter is reset to zero (0). If data remains in the received FIFO and if received
FIFO is enabled, the data counting is restarted.
[bit15:8] FBYTE2: FIFO2 data count display bits
[bit7:0] FBYTE1: FIFO1 data count display bits
At writing
Sets the transfer data count.
At reading
Reads the effective count of data.
Read (Effective data count)
During transmit: The number of data sets already written in the FIFO buffer but not transmitted yet
During reception: The number of data sets reception in FIFO
Write (Transfer data count)
During transmit: Set "0x00".
During reception: Set the data count to generate a received interrupt.
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CHAPTER 1-2: UART (Asynchronous Serial Interface)
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M A N U A L
<Notes>
Set "0x00" in the FBYTE register of transmit FIFO.
Set a data value equal to or greater than "1" in the FBYTE register of received FIFO.
This state can be changed only after the data reception has been disabled.
A read-modify-write instruction cannot be used for this register.
Any setting exceeding the FIFO capacity is inhibited.
Even the number of effective data in FIFO is the equal to FBYTE setting value, SSR:RDRF is not set to 1, if MCU
simulator model meets the following conditions.
Except case when FBYTE value are more than 2.
・In case that FBYTE is 1.
・In case that the number of effective data in FIFO is 1(equal to FBYTE setting value).
・When when multi-function serial interface macro writes reception data in reception FIFO, the reading of data is
carried out from reception FIFO. But, in one of the the following cases, flag indicating the status of data
reception (full or not full) (SSR:RDRF) is set in "1".
・When the received next data.
・In case that the idle status of data reception is detected (more than 8 bit clocks), if FIFO data reception idle status
is enabled (FRIIE=1).
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CHAPTER 1-3: CSIO (Clock Synchronous Serial
Interface)
This chapter explains the Clock Synchronous Serial interface (CSIO) function that is
supported in Operation mode 2.
The MCU simulator model does not support CSIO.
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CHAPTER 1-3: CSIO (Clock Synchronous Serial Interface)
P E R I P H E R A L
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CHAPTER 1-4: LIN Interface (Ver.2.1) (LIN
Communication Control Interface Ver.2.1)
This chapter explains the LIN communication function, a part of multifunction serial
interface functions and supported in Operation mode 3.
The MCU simulator model does not support LIN.
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CHAPTER 1-4: LIN Interface (Ver.2.1) (LIN Communication Control Interface Ver.2.1)
P E R I P H E R A L
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CHAPTER 1-5: I2C Interface (I2C Communication
Control Interface)
This chapter explains the I2C function supported in operation mode 4 of the
multifunction serial interface.
The MCU simulator model does not support I2C .
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CHAPTER 1-5: I2C Interface (I2C Communication Control Interface)
P E R I P H E R A L
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CHAPTER 1-6: I2C Auxiliary Noise Filter
This chapter explains the I2C auxiliary noise filter.
The MCU simulator model does not support I2C auxiliary noise filter.
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CHAPTER 1-6: I2C Auxiliary Noise Filter
P E R I P H E R A L
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CHAPTER 2-1: USB/Ethernet Clock Generation Block
This chapter explains the USB/Ethernet clock generation.
The MCU simulator model does not support USB/Ethernet clock generation.
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CHAPTER 2-1: USB/Ethernet Clock Generation Block
P E R I P H E R A L
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CHAPTER 2-2: USB Clock Generation
This chapter explains the USB clock generation.
The MCU simulator model does not support USB clock generation.
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CHAPTER 2-2: USB Clock Generation
P E R I P H E R A L
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CHAPTER 2-3: USB/Ethernet Clock Generation
This chapter explains the USB/Ethernet clock generation.
The MCU simulator model does not support USB/Ethernet clock generation.
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CHAPTER 2-3: USB/Ethernet Clock Generation
P E R I P H E R A L
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CHAPTER 3-1: USB Function
This chapter explains the USB function.
The MCU simulator model does not support USB function.
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CHAPTER 3-1: USB Function
P E R I P H E R A L
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CHAPTER 3-2: USB Host
This chapter explains the functions and operations of the USB host.
The MCU simulator model does not support USB host.
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CHAPTER 3-2: USB Host
P E R I P H E R A L
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CHAPTER 4: Ethernet
For the Ethernet, refer to the “Ethernet Part”.
The MCU simulator model does not support Ethernet.
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CHAPTER 4: Ethernet
P E R I P H E R A L
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CHAPTER 5-1: CAN Prescaler
This chapter explains the CAN prescaler.
The MCU simulator model does not support CAN prescaler.
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CHAPTER 5-1: CAN Prescaler
P E R I P H E R A L
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CHAPTER 5-2: CAN Controller
This chapter explains CAN.
The MCU simulator model does not support CAN Controller.
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CHAPTER 5-2: CAN Controller
P E R I P H E R A L
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CHAPTER 6-1: HDMI-CEC/Remote Control Reception
HDMI-CEC/remote control reception is explained as follows.
The MCU simulator model does not support HDMI-CEC/Remote Control Reception.
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CHAPTER 6-1: HDMI-CEC/Remote Control Reception
P E R I P H E R A L
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CHAPTER 6-2: CEC Reception/Remote Reception
Functions and operations of CEC reception/remote reception are explained as
follows.
The MCU simulator model does not support CEC Reception/Remote Reception.
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CHAPTER 6-2: CEC Reception/Remote Reception
P E R I P H E R A L
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CHAPTER 6-3: CEC Transmission
Functions and operations of CEC (Consumer Electronics Control) transmission are
as follows.
The MCU simulator model does not support CEC transmission.
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CHAPTER 6-3: CEC Transmission
P E R I P H E R A L
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APPENDIXES
This section shows the register map, list of notes, limitations, and product TYPE list.
A.
B.
C.
D.
Register Map
List of Notes
List of Limitations
Product TYPE List
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APPENDIXES
P E R I P H E R A L
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A. Register Map
This section shows the register map.
1. Register Map
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A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
1. Register Map
Register map is shown on the table every module/function.
[How to read the each table]
Module/function name and its base address
Clock/Reset
Base_Address : 0x4001_0000
Base_Address
+ Address
Register
+3
+2
+1
0x000
-
-
-
0x004
-
-
-
STB_CTL[B,H,W]
00000000 00000000 -------- ---0--00
RST_STR[B,H,W]
-------0 00000-01
0x008
0x00C
-
- : Reserved area
* : Test register area
+0
SCM_CTL[B,H,W]
00000-0SCM_STR[B,H,W]
00000-0-
Initial value after reset
"1"
:
"0"
:
"X"
:
"-"
:
Initial value is "1"
Initial value is "0"
Initial value is undefined
Reserved bit
Register name
Access unit
(B : byte, H : half word, W : word)
Rightmost register address (For word-length access, the "+0" column of the
register is the LSB of the data.)
Notes:
The register table is represented in the little-endian.
When performing a data access, the addresses should be as below according to the access size.
Word access
: Address should be multiples of 4 (least significant 2 bits should be "0x00")
Half word access : Address should be multiples of 2 (least significant bit should be "0x0")
Byte access
: Do not access the test register area.
Do not access the area that is not written in the register table.
The respective meanings of *1 to *8 in the register map are as follows:
*1 : Initial value for TYPE0.
*2 : Initial value for TYPE1 to TYPE7.
*3 : Initial value for TYPE0, TYPE3, and TYPE7.
*4 : Initial value for TYPE1, TYPE2, TYPE4, and TYPE5.
*5 : Initial value for TYPE6, TYPE8, and TYPE9.
*6 : Initial value for TYPE3 and TYPE7.
*7 : Initial value for TYPE6 and TYPE8.
*8 : Initial value for TYPE9 to TYPE12.
Flash I/F
106
CONFIDENTIAL
Base_Address : 0x4000_0000
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
The MCU simulator model does not support Flash I/F registers.
Products other than TYPE6, and TYPE8 to TYPE12
Register
Base_Address
+ Address
+3
+2
0x000
FASZR[B,H,W]
0x004
FRWTR[B,H,W]
0x008
FSTR[B,H,W]
0x00C
*
0x010
FSYNDN[B,H,W]
0x014
FBFCR[B,H,W]
0x018 - 0x0FC
-
-
0x100
0x104 - 0xFFC
+1
+0
-
-
-
-
CRTRMM[B,H,W]
-
-
TYPE6, and TYPE8 to TYPE11 products
Register
Base_Address
+ Address
+3
+2
+1
+0
0x000
-
-
-
-
-
-
-
-
-
-
0x004
FRWTR[B,H,W]
0x008
FSTR[B,H,W]
0x00C - 0x01C
-
-
0x020
FICR[B,H,W]
0x024
FISR[B,H,W]
0x028
FICLR[B,H,W]
0x02C - 0x0FC
-
-
0x100
0x104 - 0xFFC
CRTRMM[B,H,W]
-
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
-
107
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
TYPE12 products
Register
Base_Address
+ Address
+3
+2
+1
+0
0x000
-
-
-
-
-
-
-
-
-
-
-
-
0x004
FRWTR[B,H,W]
0x008
FSTR[B,H,W]
0x00C - 0x01C
-
-
0x020
FICR[B,H,W]
0x024
FISR[B,H,W]
0x028
FICLR[B,H,W]
0x02C - 0x084
-
-
0x088
0x08C - 0x0FC
FSTR1[B,H,W]
-
-
0x100
0x104 - 0xFFC
CRTRMM[B,H,W]
-
-
Note:
For details of Flash I/F registers, see "FLASH PROGRAMMING MANUAL" of the product used.
108
CONFIDENTIAL
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
Unique ID
M A N U A L
Base_Address : 0x4000_0200
The MCU simulator model does not support Unique ID registers.
Register
Base_Address
+ Address
0x000
+3
+2
+1
+0
UIDR0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXX----
0x004
UIDR1 [W]
-------- -------- ---XXXXX XXXXXXXX
0x008 –
0xDFC
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
109
A.Register Map
1.Register Map
P E R I P H E R A L
Clock/Reset
M A N U A L
Base_Address : 0x4001_0000
Register
Base_Address
+ Address
+3
+2
+1
0x000
-
-
-
0x004
-
-
-
+0
SCM_CTL[W]
00000-0SCM_STR[W]
00000-0-
STB_CTL[W]
0x008
00000000 00000000 -------- ---0-000
RST_STR[W]
0x00C
-
-------0 00000-01
0x010
-
-
-
0x014
-
-
-
0x018
-
-
-
0x01C
-
-
-
0x020
-
-
-
0x024 - 0x027
-
-
-
0x028
-
-
-
0x02C - 0x02F
-
-
-
0x030
-
-
-
0x034
-
-
-
0x038
-
-
-
0x03C
-
-
-
0x040
-
-
110
CONFIDENTIAL
BSC_PSR[W]
-----000
APBC0_PSR[W]
------00
APBC1_PSR[W]
1--0--00
APBC2_PSR[W]
1--0--00
SWC_PSR[W]
X-----00
TTC_PSR[W]
------00
CSW_TMR[W]
-0000000
PSW_TMR[W]
---0-000
PLL_CTL1[W]
00000000
PLL_CTL2[W]
---00000
CSV_CTL[W]
-111--00 ------11
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
+2
+1
0x044
-
-
-
0x048
-
-
0x04C
-
-
0x050
-
-
0x054
-
-
-
0x058
-
-
-
*
0x05C - 0x05F
-
-
-
-
0x060
-
-
-
0x064
-
-
-
0x068
-
-
-
0x06C 0xFFC
-
-
-
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
+0
CSV_STR[W]
------00
FCSWH_CTL[W]
11111111 11111111
FCSWL_CTL[W]
00000000 00000000
FCSWD_CTL[W]
00000000 00000000
DBWDT_CTL[W]
0-0-----
INT_ENR[W]
--0--000
INT_STR[W]
--0--000
INT_CLR[W]
--0--000
-
111
A.Register Map
1.Register Map
P E R I P H E R A L
HW WDT
Base_Address : 0x4001_1000
Register
Base_Address
+ Address
M A N U A L
+3
+2
+1
+0
WDG_LDR[W]
0x000
00000000 00000000 11111111 11111111
WDG_VLR[W]
0x004
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WDG_CTL[W]
0x008
-
-
-
------11
-
XXXXXXXX
WDG_ICL[W]
0x00C
-
WDG_RIS[W]
0x010
0x014 - 0xBFC
-
-
-
-------0
-
-
-
-
WDG_LCK[W]
0xC00
0xC04 0xFFC
SW WDT
00000000 00000000 00000000 00000001
-
-
-
+1
+0
Base_Address : 0x4001_2000
Register
Base_Address
+ Address
-
+3
+2
WdogLoad[W]
0x000
11111111 11111111 11111111 11111111
WdogValue[W]
0x004
11111111 11111111 11111111 11111111
WdogControl[W]
0x008
-
-
-
------00
WdogIntClr[W]
0x00C
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WdogRIS[W]
0x010
0x014 - 0xBFC
-
-
-
-------0
-
-
-
-
WdogLock[W]
0xC00
0xC04 0xFFC
112
CONFIDENTIAL
00000000 00000000 00000000 00000000
-
-
-
-
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
Dual_Timer
Base_Address : 0x4001_5000
Register
Base_Address
+ Address
+3
+2
+0
00000000 00000000 00000000 00000000
Timer1Value[W]
0x004
11111111 11111111 11111111 11111111
Timer1Control[W]
0x008
-------- -------- -------- 00100000
Timer1IntClr[W]
0x00C
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Timer1RIS[W]
0x010
-------- -------- -------- -------0
Timer1MIS[W]
0x014
-------- -------- -------- -------0
Timer1BGLoad[W]
0x018
00000000 00000000 00000000 00000000
Timer2Load[W]
0x020
00000000 00000000 00000000 00000000
Timer2Value[W]
0x024
11111111 11111111 11111111 11111111
Timer2Control[W]
0x028
-------- -------- -------- 00100000
Timer2IntClr[W]
0x02C
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Timer2RIS[W]
0x030
-------- -------- -------- -------0
Timer2MIS[W]
0x034
-------- -------- -------- -------0
Timer2BGLoad[W]
0x038
00000000 00000000 00000000 00000000
-
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
+1
Timer1Load[W]
0x000
0x040 - 0xFFC
M A N U A L
-
-
-
113
A.Register Map
1.Register Map
P E R I P H E R A L
MFT unit0
MFT unit1
MFT unit2
Base_Address : 0x4002_0000
Base_Address : 0x4002_1000
Base_Address : 0x4002_2000
Register
Base_Address
+ Address
+3
+2
0x000
-
-
0x004
-
-
0x008
-
-
0x00C
-
-
0x010
-
-
0x014
-
-
0x018
-
-
0x01C
-
-
0x020
-
-
0x024
-
-
0x028
-
-
0x02C
-
-
0x030
-
-
0x034
-
-
0x038
-
-
0x03C
-
-
0x040
-
-
114
CONFIDENTIAL
M A N U A L
+1
+0
OCCP0[H,W]
00000000 00000000
OCCP1[H,W]
00000000 00000000
OCCP2[H,W]
00000000 00000000
OCCP3[H,W]
00000000 00000000
OCCP4[H,W]
00000000 00000000
OCCP5[H,W]
00000000 00000000
OCSB10[B,H,W]
OCSA10[B,H,W]
-110--00
00001100
OCSB32[B,H,W]
OCSA32[B,H,W]
-110--00
00001100
OCSB54[B,H,W]
OCSA54[B,H,W]
-110--00
00001100
OCSC[B,H,W]
-
--000000
TCCP0[H,W]
11111111 11111111
TCDT0[H,W]
00000000 00000000
TCSA0[B,H,W]
000---00 01000000
TCSB0[B,H,W]
-------- -----000
TCCP1[H,W]
11111111 11111111
TCDT1[H,W]
00000000 00000000
TCSA1[B,H,W]
000---00 01000000
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+2
0x044
-
-
0x048
-
-
0x04C
-
-
0x050
-
-
0x054
-
-
0x058
-
-
0x05C
-
-
0x060
-
-
0x064
-
-
0x068
-
-
0x06C
-
-
0x070
-
-
0x074
-
-
0x078
-
-
0x07C
-
-
0x080
-
-
0x084
-
-
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
M A N U A L
+1
+0
TCSB1[B,H,W]
-------- -----000
TCCP2[H,W]
11111111 11111111
TCDT2[H,W]
00000000 00000000
TCSA2[B,H,W]
000---00 01000000
TCSB2[B,H,W]
-------- -----000
OCFS32[B,H,W]
OCFS10[B,H,W]
00000000
00000000
OCFS54[B,H,W]
-
00000000
ICFS32[B,H,W]
ICFS10[B,H,W]
00000000
00000000
-
ICCP0[H,W]
XXXXXXXX XXXXXXXX
ICCP1[H,W]
XXXXXXXX XXXXXXXX
ICCP2[H,W]
XXXXXXXX XXXXXXXX
ICCP3[H,W]
XXXXXXXX XXXXXXXX
ICSB10[B,H,W]
ICSA10[B,H,W]
------00
00000000
ICSB32[B,H,W]
ICSA32[B,H,W]
------00
00000000
WFTM10[H,W]
00000000 00000000
WFTM32[H,W]
00000000 00000000
115
A.Register Map
1.Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+2
0x088
-
-
0x08C
-
-
0x090
-
-
0x094
-
-
0x098
-
-
0x09C
-
-
0x0A0
-
-
0x0A4
-
-
0x0A8
-
-
0x0AC
-
-
0x0B0
-
-
0x0B4
-
-
0x0B8
-
-
0x0BC
-
-
0x0C0
-
-
0x0C4 - 0x0FC
-
-
116
CONFIDENTIAL
M A N U A L
+1
+0
WFTM54[H,W]
00000000 00000000
WFSA10[H,W]
---00000 000000
WFSA32[H,W]
---00000 000000
WFSA54[H,W]
---00000 000000
WFIR[H,W]
00000000 0000--00
NZCL[H,W]
-------- ---00000
ACCP0[H,W]
00000000 00000000
ACCPDN0[H,W]
00000000 00000000
ACCP1[H,W]
00000000 00000000
ACCPDN1[H,W]
00000000 00000000
ACCP2[H,W]
00000000 00000000
ACCPDN2[H,W]
00000000 00000000
-
ACSB[B,H,W]
-000-111
ACSA[B,H,W]
--000000 --000000
ATSA[H,W]
--000000 --000000
-
-
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
PPG
Base_Address : 0x4002_4000
The MCU simulator model does not support IGBT register.
Register
Base_Address
+ Address
+3
+2
0x000
-
-
0x004
-
-
0x008
-
-
+1
TTCR0 [B,H,W]
11110000
-
+0
*
COMP0 [B,H,W]
00000000
0x00C
-
-
0x010
-
-
0x014
-
-
-
0x018 - 0x01C
-
-
-
0x020
-
-
0x024
-
-
0x028
-
-
0x02C
-
-
0x030
-
-
0x034
-
-
-
0x038 - 0x03C
-
-
-
0x040
-
-
0x044
-
-
0x048
-
-
0x04C
-
-
0x050
-
-
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
COMP4 [B,H,W]
00000000
TTCR1 [B,H,W]
11110000
COMP1 [B,H,W]
00000000
COMP5 [B,H,W]
00000000
TTCR2 [B,H,W]
11110000
COMP8 [B,H,W]
00000000
COMP12 [B,H,W]
00000000
COMP2 [B,H,W]
00000000
COMP6 [B,H,W]
00000000
*
COMP3 [B,H,W]
00000000
COMP7 [B,H,W]
00000000
*
COMP10 [B,H,W]
00000000
-
117
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
+2
+1
0x054
-
-
-
0x58 - 0x0FC
-
-
-
0x100
-
-
0x104
-
-
0x108 - 0x13C
-
-
0x140
-
-
0x144
-
-
0x148 - 0x1FC
-
-
0x200
-
-
0x204
0x208
0x20C
0x210
0x214
-
-
-
-
-
+0
COMP14 [B,H,W]
00000000
TRG [B,H,W]
00000000 00000000
REVC [B,H,W]
00000000 00000000
-
TRG1 [B,H,W]
-------- 00000000
REVC1 [B,H,W]
-------- 00000000
-
-
PPGC0 [B,H,W]
PPGC1 [B,H,W]
00000000
00000000
PPGC2 [B,H,W]
PPGC3 [B,H,W]
00000000
00000000
PRLH0 [B,H,W]
PRLL0 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH1 [B,H,W]
PRLL1 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH2 [B,H,W]
PRLL2 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH3 [B,H,W]
PRLL3 [B,H,W]
XXXXXXXX
XXXXXXXX
-
-
-
-
GATEC0 [B,H,W]
0x218
-
-
--00---00
0x21C - 0x23C
-
-
0x240
-
-
0x244
0x248
118
CONFIDENTIAL
-
-
-
-
PPGC4 [B,H,W]
PPGC5 [B,H,W]
00000000
00000000
PPGC6 [B,H,W]
PPGC7 [B,H,W]
00000000
00000000
PRLH4 [B,H,W]
PRLL4 [B.H.W]
XXXXXXXX
XXXXXXXX
-
-
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+2
0x24C
-
-
0x250
0x254
M A N U A L
-
-
+1
+0
PRLH5 [B,H,W]
PRLL5 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH6 [B,H,W]
PRLL6 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH7 [B,H,W]
PRLL7 [B,H,W]
XXXXXXXX
XXXXXXXX
-
GATEC4 [B,H,W]
0x258
-
-
------00
0x25C - 0x27C
-
-
0x280
-
-
0x284
0x288
0x28C
0x290
0x294
-
-
-
-
-
-
-
PPGC8 [B,H,W]
PPGC9 [B,H,W]
00000000
00000000
PPGC10 [B,H,W]
PPGC11 [B,H,W]
00000000
00000000
PRLH8 [B,H,W]
PRLL8 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH9 [B,H,W]
PRLL9 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH10 [B,H,W]
PRLL10 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH11 [B,H,W]
PRLL11 [B,H,W]
XXXXXXXX
XXXXXXXX
-
-
-
-
GATEC8 [B,H,W]
0x298
-
-
--00--00
0x29C 0x2BC
-
-
0x2C0
-
-
0x2C4
0x2C8
0x2CC
-
-
-
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
-
-
PPGC12 [B,H,W]
PPGC13 [B,H,W]
00000000
00000000
PPGC14 [B,H,W]
PPGC15 [B,H,W]
00000000
00000000
PRLH12 [B,H,W]
PRLL12 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH13 [B,H,W]
PRLL13 [B,H,W]
XXXXXXXX
XXXXXXXX
-
-
-
119
A.Register Map
1.Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+2
0x2D0
-
-
0x2D4
M A N U A L
-
+1
+0
PRLH14 [B,H,W]
PRLL14 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH15 [B,H,W]
PRLL15 [B,H,W]
XXXXXXXX
XXXXXXXX
GATEC12 [B,H,W]
0x2D8
-
-
------00
0x2DC 0x2FC
-
-
0x300
-
-
0x304
0x308
0x30C
0x310
0x314
-
-
-
-
-
-
-
PPGC16 [B,H,W]
PPGC17 [B,H,W]
00000000
00000000
PPGC18 [B,H,W]
PPGC19 [B,H,W]
00000000
00000000
PRLH16 [B,H,W]
PRLL16 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH17 [B,H,W]
PRLL17 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH18 [B,H,W]
PRLL18 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH19 [B,H,W]
PRLL19 [B,H,W]
XXXXXXXX
XXXXXXXX
-
-
-
-
GATEC16[B,H,W]
0x318
-
-
--00---00
0x31C - 0x33C
-
-
0x340
-
-
0x344
0x348
0x34C
0x350
120
CONFIDENTIAL
-
-
-
-
-
-
PPGC20 [B,H,W]
PPGC21 [B,H,W]
00000000
00000000
PPGC22 [B,H,W]
PPGC23 [B,H,W]
00000000
00000000
PRLH20 [B,H,W]
PRLL20 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH21 [B,H,W]
PRLL21 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH22 [B,H,W]
PRLL22 [B,H,W]
XXXXXXXX
XXXXXXXX
-
-
-
-
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
+2
0x354
-
-
+1
+0
PRLH23 [B,H,W]
PRLL23 [B,H,W]
XXXXXXXX
XXXXXXXX
GATEC20 [B,H,W]
0x358
-
-
------00
0x35C - 0x37C
-
-
-
0x380
-
-
-
IGBTC [B,H,W]
00000000
0x384 - 0xFFC
-
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
-
-
-
121
A.Register Map
1.Register Map
P E R I P H E R A L
Base Timer ch.0
Base Timer ch.1
Base Timer ch.2
Base Timer ch.3
Base Timer ch.4
Base Timer ch.5
Base Timer ch.6
Base Timer ch.7
Base Timer ch.8
Base Timer ch.9
Base Timer ch.10
Base Timer ch.11
Base Timer ch.12
Base Timer ch.13
Base Timer ch.14
Base Timer ch.15
Base Address : 0x4002_5000
Base Address : 0x4002_5040
Base Address : 0x4002_5080
Base Address : 0x4002_50C0
Base Address : 0x4002_5200
Base Address : 0x4002_5240
Base Address : 0x4002_5280
Base Address : 0x4002_52C0
Base Address : 0x4002_5400
Base Address : 0x4002_5440
Base Address : 0x4002_5480
Base Address : 0x4002_54C0
Base Address : 0x4002_5600
Base Address : 0x4002_5640
Base Address : 0x4002_5680
Base Address : 0x4002_56C0
Register
Base_Address
+ Address
+3
+2
0x000
-
-
0x004
-
-
0x008
-
-
0x00C
-
-
0x010
-
-
0x014 - 0x03C
-
-
122
CONFIDENTIAL
M A N U A L
+1
+0
PCSR/PRLL [H,W]
XXXXXXXX XXXXXXXX
PDUT/PRLH/DTBF [H,W]
XXXXXXXX XXXXXXXX
TMR [H,W]
00000000 00000000
TMCR [B,H,W]
-0000000 00000000
TMCR2 [B,H,W]
STC [B,H,W]
-------0
0000-000
-
-
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
IO Selector for ch.0-ch.3 (Base Timer)
M A N U A L
Base Address : 0x4002_5100
Register
Base_Address
+ Address
+3
+2
+1
+0
0x000
-
-
BTSEL0123 [B,H,W]
00000000
-
0x004 - 0x0FC
-
-
-
-
IO Selector for ch.4-ch.7(Base Timer)
Base Address : 0x4002_5300
Register
Base_Address
+ Address
+3
+2
+1
+0
0x000
-
-
BTSEL4567 [B,H,W]
00000000
-
0x004 - 0x0FC
-
-
-
-
IO Selector for ch.8-ch.11(Base Timer)
Base Address : 0x4002_5500
Register
Base_Address
+ Address
+3
+2
+1
+0
0x000
-
-
BTSEL89AB [B,H,W]
00000000
-
0x004 - 0x0FC
-
-
-
-
IO Selector for ch.12-ch.15(Base Timer)
Base Address : 0x4002_5700
Register
Base_Address
+ Address
+3
+2
+1
+0
0x000
-
-
BTSELCDEF
[B,H,W]
00000000
-
0x004 - 0x0FC
-
-
-
-
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
123
A.Register Map
1.Register Map
P E R I P H E R A L
Software-based Simulation Startup (Base Timer)
M A N U A L
Base Address : 0x4002_5F00
Register
Base_Address
+ Address
+3
+2
+1
+0
0x000 - 0x0FB
-
-
-
-
0x0FC
-
-
BTSSSR [B,H,W]
XXXXXXXX XXXXXXXX
QPRC ch.0
QPRC ch.1
QPRC ch.2
Base Address : 0x4002_6000
Base Address : 0x4002_6040
Base Address : 0x4002_6080
Register
Base_Address
+ Address
+3
+2
0x0000
-
-
0x0004
-
-
0x0008
-
-
0x000C
-
-
0x0010
-
-
0x0014
-
-
0x0018
-
-
0x001C
-
-
0x0020 0x0038
-
-
0x003C
124
CONFIDENTIAL
+1
+0
QPCR [H,W]
00000000 00000000
QRCR [H,W]
00000000 00000000
QPCCR [H,W]
00000000 00000000
QPRCR [H,W]
00000000 00000000
QMPR [H,W]
11111111 11111111
QICRH [B,H,W]
QICRL [B,H,W]
--000000
00000000
QCRH [B,H,W]
QCRL [B,H,W]
00000000
00000000
QECR [B,H,W]
-------- -----000
-
-
QPCRR [B,H,W]
QRCRR [B,H,W]
00000000 00000000
00000000 00000000
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
12-bit A/DC unit0
12-bit A/DC unit1
12-bit A/DC unit2
M A N U A L
Base_Address : 0x4002_7000
Base_Address : 0x4002_7100
Base_Address : 0x4002_7200
TYPE0 to TYPE2, TYPE4, and TYPE5 products
Register
Base_Address
+ Address
+3
+2
0x000
-
-
0x004
-
-
0x008
-
-
+0
ADCR[B,H,W]
ADSR[B,H,W]
000-0000
00---000
-
*
SCCR[B,H,W]
SFNS[B,H,W]
1000-000
----0000
SCFD[B,H,W]
0x00C
XXXXXXXX XXXX---- ---1--XX ---XXXXX
0x010
-
-
0x014
-
-
0x018
-
-
SCIS3[B,H,W]
SCIS2[B,H,W]
00000000
00000000
SCIS1[B,H,W]
SCIS0[B,H,W]
00000000
00000000
PCCR[B,H,W]
PFNS[B,H,W]
1000-000
--XX--00
PCFD[B,H,W]
0x01C
0x020
+1
XXXXXXXX XXXX---- ---1-XXX ---XXXXX
-
CMPD[B,H,W]
0x024
-
-
00000000 00------
CMPCR[B,H,W]
00000000
ADSS2[B,H,W]
00000000
00000000
ADSS1[B,H,W]
ADSS0[B,H,W]
00000000
00000000
ADST0[B,H,W]
ADST1[B,H,W]
00010000
00010000
-
-
0x02C
-
-
0x030
-
-
0x034
-
-
0x038
-
-
0x03C
-
-
-
0x040 - 0x0FC
-
-
-
CONFIDENTIAL
00000000
ADSS3[B,H,W]
0x028
June 20, 2014, FM3_MN706-00043-1v0-E
PCIS[B,H,W]
-
ADCT[B,H,W]
00000111
SCTSL[B,H,W]
PRTSL[B,H,W]
----0000
----0000
ADCEN[B,H,W]
--00--00
-
125
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
TYPE3, and TYPE6 to TYPE12 products
Register
Base_Address
+ Address
+3
+2
0x000
-
-
0x004
-
-
0x008
-
-
+0
ADCR[B,H,W]
ADSR[B,H,W]
000-0000
00---000
-
*
SCCR[B,H,W]
SFNS[B,H,W]
1000-000
----0000
SCFD[B,H,W]
0x00C
XXXXXXXX XXXX---- ---1--XX ---XXXXX
0x010
-
-
0x014
-
-
0x018
-
-
SCIS3[B,H,W]
SCIS2[B,H,W]
00000000
00000000
SCIS1[B,H,W]
SCIS0[B,H,W]
00000000
00000000
PCCR[B,H,W]
PFNS[B,H,W]
10000000
--XX--00
PCFD[B,H,W]
0x01C
0x020
+1
XXXXXXXX XXXX---- ---1-XXX ---XXXXX
-
CMPD[B,H,W]
0x024
PCIS[B,H,W]
-
00000000
CMPCR[B,H,W]
-
00000000 00------
0x028
-
-
0x02C
-
-
00000000
ADSS3[B,H,W]
ADSS2[B,H,W]
00000000
00000000
ADSS1[B,H,W]
ADSS0[B,H,W]
00000000
00000000
ADST0[B,H,W]
ADST1[B,H,W]
00010000
00010000
0x030
-
-
0x034
-
-
-
0x038
-
-
SCTSL[B,H,W]
----0000
0x03C
-
-
0x040 - 0x0FC
-
-
126
CONFIDENTIAL
ADCT[B,H,W]
00000111
PRTSL[B,H,W]
----0000
ADCEN[B,H,W]
11111111 ------00
-
-
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
10-bit D/AC
Base_Address : 0x4002_8000
The MCU simulator model does not support 10-bit D/AC. It is Reserved area. In the MCU simulator
model, read and write access in 10-bit D/AC area are supported.
Base_Address
+ Address
Register
+3
0x00
-
0x04
-
0x08 - 0xFC
-
+2
0x00 0xFC
+3
+2
+1
+0
-
-
-
-
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
+0
DADR0[B,H,W]
------XX XXXXXXXX
DADR1[B,H,W]
------XX XXXXXXXX
-
Register
Base_Address
+ Address
+1
DACR0[B,H,W]
-------0
DACR1[B,H,W]
-------0
-
127
A.Register Map
1.Register Map
P E R I P H E R A L
CR Trim
M A N U A L
Base_Address : 0x4002_E000
Register
Base_Address
+ Address
+3
+2
+1
0x000
-
-
-
+0
MCR_PSR [B,H,W]
------01
MCR_FTRM[B,H,W]
------01 10000000 *3
0x004
-
-
------01 10001110 *6
-------- 01111111 *4
------10 00000000 *5
0x008
-
-
MCR_TTRM
[B,H,W]
-
--011111
MCR_RLR[W]
0x00C
0x010 - 0x0FC
EXTI
00000000 00000000 00000000 00000001
-
-
-
+1
+0
Base_Address : 0x4003_0000
Register
Base_Address
+ Address
-
+3
+2
ENIR[B,H,W]
0x000
00000000 00000000 00000000 00000000
EIRR[B,H,W]
0x004
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EICL[B,H,W]
0x008
11111111 11111111 11111111 11111111
ELVR[R/W]
0x00C
00000000 00000000 00000000 00000000
ELVR1[R/W]
0x010
00000000 00000000 00000000 00000000
NMIRR[B,H,W]
0x014
-
-
0x018
-
-
0x01C
-
-
-
-
0x020 - 0x0FC
-
-
-
-
128
CONFIDENTIAL
-------- -------0
NMICL[B,H,W]
-------- -------1
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
INT-Req. READ
M A N U A L
Base_Address : 0x4003_1000
Products other than TYPE3/TYPE7
Register
Base_Address
+ Address
+3
+2
00000000 00000000 00000000 00000000
0x004
0x00C
*
ODDPKS[B]
---00000
-
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
+0
DRQSEL[B,H,W]
0x000
0x008
+1
-
-
*
-
-
IRQCMODE[B,H,W]
-------0
EXC02MON[B,H,W]
-------- -------- -------- ------00
IRQ00MON[B,H,W]
-------- -------- -------- -------0
IRQ01MON[B,H,W]
-------- -------- -------- -------0
IRQ02MON[B,H,W]
-------- -------- -------- -------0
IRQ03MON[B,H,W]
-------- -------- ----0000 00000000
IRQ04MON[B,H,W]
-------- -------- -------- 00000000
IRQ05MON[B,H,W]
-------- 00000000 00000000 00000000
IRQ06MON[B,H,W]
-------- ----0000 00000000 00000000
IRQ07MON[B,H,W]
-------- -------- -------- ------00
IRQ08MON[B,H,W]
-------- -------- -------- ----0000
IRQ09MON[B,H,W]
-------- -------- -------- ------00
IRQ10MON[B,H,W]
-------- -------- -------- ----0000
IRQ11MON[B,H,W]
-------- -------- -------- ------00
129
A.Register Map
1.Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
0x044
0x048
0x04C
0x050
0x054
0x058
M A N U A L
+3
+2
+1
+0
IRQ12MON[B,H,W]
-------- -------- -------- ----0000
IRQ13MON[B,H,W]
-------- -------- -------- ------00
IRQ14MON[B,H,W]
-------- -------- -------- ----0000
IRQ15MON[B,H,W]
-------- -------- -------- ------00
IRQ16MON[B,H,W]
-------- -------- -------- ----0000
IRQ17MON[B,H,W]
-------- -------- -------- ------00
IRQ18MON[B,H,W]
0x05C
-------- -------- -------- ----0000
0x060
0x064
0x068
0x06C
0x070
0x074
0x078
0x07C
0x080
0x084
130
CONFIDENTIAL
IRQ19MON[B,H,W]
-------- -------- -------- ------00
IRQ20MON[B,H,W]
-------- -------- -------- ----0000
IRQ21MON[B,H,W]
-------- -------- -------- ------00
IRQ22MON[B,H,W]
-------- -------- -------- ----0000
IRQ23MON[B,H,W]
-------- -------- -------0 00000000
IRQ24MON[B,H,W]
-------- -------- -------- --000000
IRQ25MON[B,H,W]
-------- -------- -------- ----0000
IRQ26MON[B,H,W]
-------- -------- -------- ----0000
IRQ27MON[B,H,W]
-------- -------- -------- ---00000
IRQ28MON[B,H,W]
-------- ------00 00000000 00000000
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
0x088
0x08C
0x090
0x094
0x098
0x09C
0x0A0
0x0A4
0x0A8
0x0AC
0x0B0
0x0B4
0x0B8
0x0BC
0x0C0
0x0C4
0x0C8
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
M A N U A L
+2
+1
+0
IRQ29MON[B,H,W]
-------- -------- ----0000 00000000
IRQ30MON[B,H,W]
-------- ------00 00000000 00000000
IRQ31MON[B,H,W]
-------- -------- 00000000 00000000
IRQ32MON[B,H,W]
-------- -------- -------- ----0000
IRQ33MON[B,H,W]
-------- -------- -------- -----000
IRQ34MON[B,H,W]
-------- -------- -------- ---00000
IRQ35MON[B,H,W]
-------- -------- -------- --000000
IRQ36MON[B,H,W]
-------- -------- -------- --000000
IRQ37MON[B,H,W]
-------- -------- -------- -0000000
IRQ38MON[B,H,W]
-------- -------- -------- -------0
IRQ39MON[B,H,W]
-------- -------- -------- -------0
IRQ40MON[B,H,W]
-------- -------- -------- -------0
IRQ41MON[B,H,W]
-------- -------- -------- -------0
IRQ42MON[B,H,W]
-------- -------- -------- -------0
IRQ43MON[B,H,W]
-------- -------- -------- -------0
IRQ44MON[B,H,W]
-------- -------- -------- -------0
IRQ45MON[B,H,W]
-------- -------- -------- -------0
131
A.Register Map
1.Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+2
+1
+0
IRQ46MON[B,H,W]
0x0CC
-------- -------- 00000000 00000000
IRQ47MON[B,H,W]
0x0D0
0x0D4 0x1FC
M A N U A L
-------- -------- ----0--- --------
-
-
-
DRQSEL1[B,H,W]
0x200
-------- -------- -------- ---00000
DQESEL[B,H,W]
0x204
00000000 00000000 00000000 00000000
0x208
*
ODDPKS[B]
0x20C
-
-
*
---00000
RCINTSEL3[B,H,W] RCINTSEL2[B,H,W] RCINTSEL1[B,H,W] RCINTSEL0[B,H,W]
0x210
---00000
---00000
---00000
---00000
RCINTSEL7[B,H,W] RCINTSEL6[B,H,W] RCINTSEL5[B,H,W] RCINTSEL4[B,H,W]
0x214
0x218 - 0xFFC
---00000
---00000
---00000
---00000
-
-
-
-
+1
+0
-
-
TYPE3/TYPE7 products
Register
Base_Address
+ Address
+3
+2
0x000
*
0x004
*
0x008
*
0x00C
0x010
0x014
0x018
0x01C
0x020
132
CONFIDENTIAL
-
EXC02MON[B,H,W]
-------- -------- -------- ------00
IRQ00MON[B,H,W]
-------- -------- -------- -------0
IRQ01MON[B,H,W]
-------- -------- -------- -------0
IRQ02MON[B,H,W]
-------- -------- -------- -------0
IRQ03MON[B,H,W]
-------- -------- -------- ----0000
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
M A N U A L
+3
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
0x048
0x04C
0x050
0x054
0x058
0x05C
+2
+1
+0
IRQ04MON[B,H,W]
-------- -------- -------- -0000000
IRQ05MON[B,H,W]
-------- -------- -------- 0------IRQ06MON[B,H,W]
-------- -------- -------- -------0
IRQ07MON[B,H,W]
-------- -------- -------- ------00
IRQ08MON[B,H,W]
-------- -------- -------- -------0
IRQ09MON[B,H,W]
-------- -------- -------- ------00
IRQ10MON[B,H,W]
-------- -------- -------- -------0
IRQ11MON[B,H,W]
-------- -------- -------- ------00
IRQ12MON[B,H,W]
-------- -------- -------- -------0
IRQ13MON[B,H,W]
-------- -------- -------- ------00
IRQ14MON[B,H,W]
-------- -------- -------- -------0
IRQ15MON[B,H,W]
-------- -------- -------- ------00
IRQ16MON[B,H,W]
-------- -------- -------- -------0
IRQ17MON[B,H,W]
-------- -------- -------- ------00
IRQ18MON[B,H,W]
-------- -------- -------- -------0
IRQ19MON[B,H,W]
0x060
-------- -------- -------- ------00
0x064
0x068
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
IRQ20MON[B,H,W]
-------- -------- -------- ------0
IRQ21MON[B,H,W]
-------- -------- -------- ------00
133
A.Register Map
1.Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
0x06C
0x070
0x074
0x078
0x07C
0x080
0x084
0x088
0x08C
0x090
134
CONFIDENTIAL
M A N U A L
+3
+2
+1
+0
IRQ22MON[B,H,W]
-------- -------- -------- -----000
IRQ23MON[B,H,W]
-------- -------- -------- --0--000
IRQ24MON[B,H,W]
-------- -------- -------- ----0000
IRQ25MON[B,H,W]
-------- -------- -------- --000000
IRQ26MON[B,H,W]
-------- -------- -------- ----0000
IRQ27MON[B,H,W]
-------- -------- -------- --000000
IRQ28MON[B,H,W]
-------- -------- 00000000 00000000
IRQ29MON[B,H,W]
-------- -------- -------- ---0---IRQ30MON[B,H,W]
-------- -------- -------- --0----IRQ31MON[B,H,W]
-------- -------- -------- -0------
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
LCDC Base_Address : 0x4003_2000
The MCU simulator model does not support LCDC. It is Reserved area. In the MCU simulator model,
read and write access in LCDC area are supported.
Base_Address
+ Address
0x00
Register
+3
-
0x04
0x08
0x0C
0x10
0x14
-
0x18
LCDRAM03[B,H,W]
00000000
LCDRAM07[B,H,W]
00000000
LCDRAM11[B,H,W]
00000000
LCDRAM15[B,H,W]
00000000
LCDRAM19[B,H,W]
00000000
LCDRAM23[B,H,W]
00000000
LCDRAM27[B,H,W]
00000000
LCDRAM31[B,H,W]
00000000
LCDRAM35[B,H,W]
00000000
LCDRAM39[B,H,W]
00000000
-
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
0x40
0x44 - 0xFC
+2
0x00 0xFC
+3
+2
+1
+0
-
-
-
-
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
+0
Register
Base_Address
+ Address
+1
LCDCC3[B,H,W]
LCDCC2[B,H,W]
LCDCC1[B,H,W]
0011111--010100
-00000-LCDC_PSR[B,H,W]
-------- -0000000 00000000 00000000
LCDC_COMEN[B,H,W]
-------- -------- -------- 00000000
LCDC_SEGEN1[B,H,W]
00000000 00000000 00000000 00000000
LCDC_SEGEN2[B,H,W]
-------- -------- -------- 00000000
LCDC_BLINK[B,H,W]
00000000 00000000
LCDRAM02[B,H,W] LCDRAM01[B,H,W] LCDRAM00[B,H,W]
00000000
00000000
00000000
LCDRAM06[B,H,W] LCDRAM05[B,H,W] LCDRAM04[B,H,W]
00000000
00000000
00000000
LCDRAM10[B,H,W] LCDRAM09[B,H,W] LCDRAM08[B,H,W]
00000000
00000000
00000000
LCDRAM14[B,H,W] LCDRAM13[B,H,W] LCDRAM12[B,H,W]
00000000
00000000
00000000
LCDRAM18[B,H,W] LCDRAM17[B,H,W] LCDRAM16[B,H,W]
00000000
00000000
00000000
LCDRAM22[B,H,W] LCDRAM21[B,H,W] LCDRAM20[B,H,W]
00000000
00000000
00000000
LCDRAM26[B,H,W] LCDRAM25[B,H,W] LCDRAM24[B,H,W]
00000000
00000000
00000000
LCDRAM30[B,H,W] LCDRAM29[B,H,W] LCDRAM28[B,H,W]
00000000
00000000
00000000
LCDRAM34[B,H,W] LCDRAM33[B,H,W] LCDRAM32[B,H,W]
00000000
00000000
00000000
LCDRAM38[B,H,W] LCDRAM37[B,H,W] LCDRAM36[B,H,W]
00000000
00000000
00000000
-
135
A.Register Map
1.Register Map
P E R I P H E R A L
GPIO
M A N U A L
Base_Address : 0x4003_3000
Register read and write are supported for PZR register.
Register
Base_Address
+ Address
+3
PFR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PFR2[B,H,W]
0x008
---- ---- ---- ---- 0000 0000 0000 0000
PFR3[B,H,W]
0x00C
---- ---- ---- ---- 0000 0000 0000 0000
PFR4[B,H,W]
0x010
---- ---- ---- ---- 0000 0000 0000 0000
PFR5[B,H,W]
0x014
---- ---- ---- ---- 0000 0000 0000 0000
PFR6[B,H,W]
0x018
---- ---- ---- ---- 0000 0000 0000 0000
PFR7[B,H,W]
0x01C
---- ---- ---- ---- 0000 0000 0000 0000
PFR8[B,H,W]
0x020
---- ---- ---- ---- 0000 0000 0000 0000
PFR9[B,H,W]
0x024
---- ---- ---- ---- 0000 0000 0000 0000
PFRA[B,H,W]
0x028
---- ---- ---- ---- 0000 0000 0000 0000
PFRB[B,H,W]
0x02C
---- ---- ---- ---- 0000 0000 0000 0000
PFRC[B,H,W]
0x030
---- ---- ---- ---- 0000 0000 0000 0000
PFRD[B,H,W]
0x034
---- ---- ---- ---- 0000 0000 0000 0000
PFRE[B,H,W]
0x038
---- ---- ---- ---- 0000 0000 0000 0000
PFRF[B,H,W]
0x03C
CONFIDENTIAL
+0
---- ---- ---- ---- 0000 0000 0001 1111
0x004
136
+1
PFR0[B,H,W]
0x000
0x040 - 0x0FC
+2
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
0x100
0x104
0x108
0x10C
0x110
0x114
0x118
0x11C
0x120
0x124
0x128
0x12C
0x130
0x134
0x138
0x13C
0x140 - 0x1FC
0x200
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
M A N U A L
+2
+1
+0
PCR0[B,H,W]
---- ---- ---- ---- 0000 0000 0001 1111
PCR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PCR2[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PCR3[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PCR4[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PCR5[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PCR6[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PCR7[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PCRB[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PCR9[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PCRA[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PCRB[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PCRC[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PCRD[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PCRE[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PCRF[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
DDR0[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
137
A.Register Map
1.Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
---- ---- ---- ---- 0000 0000 0000 0000
DDR3[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
DDR4[B,H,W]
0x210
---- ---- ---- ---- 0000 0000 0000 0000
DDR5[B,H,W]
0x214
---- ---- ---- ---- 0000 0000 0000 0000
DDR6[B,H,W]
0x218
---- ---- ---- ---- 0000 0000 0000 0000
DDR7[B,H,W]
0x21C
---- ---- ---- ---- 0000 0000 0000 0000
DDR8[B,H,W]
0x220
---- ---- ---- ---- 0000 0000 0000 0000
DDR9[B,H,W]
0x224
---- ---- ---- ---- 0000 0000 0000 0000
DDRA[B,H,W]
0x228
---- ---- ---- ---- 0000 0000 0000 0000
DDRB[B,H,W]
0x22C
---- ---- ---- ---- 0000 0000 0000 0000
DDRC[B,H,W]
0x230
---- ---- ---- ---- 0000 0000 0000 0000
DDRD[B,H,W]
0x234
---- ---- ---- ---- 0000 0000 0000 0000
DDRE[B,H,W]
0x238
---- ---- ---- ---- 0000 0000 0000 0000
DDRF[B,H,W]
0x23C
138
CONFIDENTIAL
+0
DDR2[B,H,W]
0x20C
0x304
+1
---- ---- ---- ---- 0000 0000 0000 0000
0x208
0x300
+2
DDR1[B,H,W]
0x204
0x240 - 0x2FC
M A N U A L
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
PDIR0[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDIR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+1
+0
---- ---- ---- ---- 0000 0000 0000 0000
PDIR3[B,H,W]
0x30C
---- ---- ---- ---- 0000 0000 0000 0000
PDIR4[B,H,W]
0x310
---- ---- ---- ---- 0000 0000 0000 0000
PDIR5[B,H,W]
0x314
---- ---- ---- ---- 0000 0000 0000 0000
PDIR6[B,H,W]
0x318
---- ---- ---- ---- 0000 0000 0000 0000
PDIR7[B,H,W]
0x31C
---- ---- ---- ---- 0000 0000 0000 0000
PDIR8[B,H,W]
0x320
---- ---- ---- ---- 0000 0000 0000 0000
PDIR9[B,H,W]
0x324
---- ---- ---- ---- 0000 0000 0000 0000
PDIRA[B,H,W]
0x328
---- ---- ---- ---- 0000 0000 0000 0000
PDIRB[B,H,W]
0x32C
---- ---- ---- ---- 0000 0000 0000 0000
PDIRC[B,H,W]
0x330
---- ---- ---- ---- 0000 0000 0000 0000
PDIRD[B,H,W]
0x334
---- ---- ---- ---- 0000 0000 0000 0000
PDIRE[B,H,W]
0x338
---- ---- ---- ---- 0000 0000 0000 0000
PDIRF[B,H,W]
0x33C
---- ---- ---- ---- 0000 0000 0000 0000
-
0x400
0x404
0x408
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
+2
PDIR2[B,H,W]
0x308
0x340 - 0x3FC
M A N U A L
-
-
-
PDOR0[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDOR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDOR2[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
139
A.Register Map
1.Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+1
+0
---- ---- ---- ---- 0000 0000 0000 0000
PDOR4[B,H,W]
0x410
---- ---- ---- ---- 0000 0000 0000 0000
PDOR5[B,H,W]
0x414
---- ---- ---- ---- 0000 0000 0000 0000
PDOR6[B,H,W]
0x418
---- ---- ---- ---- 0000 0000 0000 0000
PDOR7[B,H,W]
0x41C
---- ---- ---- ---- 0000 0000 0000 0000
PDOR8[B,H,W]
0x420
---- ---- ---- ---- 0000 0000 0000 0000
PDOR9[B,H,W]
0x424
---- ---- ---- ---- 0000 0000 0000 0000
PDORA[B,H,W]
0x428
---- ---- ---- ---- 0000 0000 0000 0000
PDORB[B,H,W]
0x42C
---- ---- ---- ---- 0000 0000 0000 0000
PDORC[B,H,W]
0x430
---- ---- ---- ---- 0000 0000 0000 0000
PDORD[B,H,W]
0x434
---- ---- ---- ---- 0000 0000 0000 0000
PDORE[B,H,W]
0x438
---- ---- ---- ---- 0000 0000 0000 0000
PDORF[B,H,W]
0x43C
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
ADE[B,H,W]
0x500
0x504 - 0x57C
+2
PDOR3[B,H,W]
0x40C
0x440 - 0x4FC
M A N U A L
1111 1111 1111 1111 1111 1111 1111 1111
-
-
-
-
SPSR[B,H,W]
0x580
---- ---- ---- ---- ---- ---- ---0 ---1 *1
---- ---- ---- ---- ---- ---- ---0 0101 *2
0x584 - 0x5FC
0x600
0x604
140
CONFIDENTIAL
-
-
-
-
EPFR00[B,H,W]
---- --00 ---- --11 --0- --0- 0000 --00
EPFR01[B,H,W]
0000 0000 0000 0000 ---0 0000 0000 0000
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+1
+0
0000 0000 0000 0000 ---0 0000 0000 0000
EPFR03[B,H,W]
0x60C
0000 0000 0000 0000 ---0 0000 0000 0000
EPFR04[B,H,W]
0x610
--00 0000 --00 00-- --00 0000 -000 00-EPFR05[B,H,W]
0x614
--00 0000 --00 00-- --00 0000 --00 00-EPFR06[B,H,W]
0x618
0000 0000 0000 0000 0000 0000 0000 0000
EPFR07[B,H,W]
0x61C
---- 0000 0000 0000 0000 0000 0000 ---EPFR08[B,H,W]
0x620
---- 0000 0000 0000 0000 0000 0000 0000
EPFR09[B,H,W]
0x624
0000 0000 0000 0000 0000 0000 0000 0000
EPFR10[B,H,W]
0x628
0000 0000 0000 0000 0000 0000 0000 0000
EPFR11[B,H,W]
0x62C
---- --00 0000 0000 0000 0000 0000 0000
EPFR12[B,H,W]
0x630
--00 0000 --00 00-- --00 0000 --00 00-EPFR13[B,H,W]
0x634
--00 0000 --00 00-- --00 0000 --00 00-EPFR14[B,H,W]
0x638
0000 0000 0000 0000 0000 0000 0000 0000
EPFR15[B,H,W]
0x63C
0000 0000 0000 0000 0000 0000 0000 0000
EPFR16[B,H,W]
0x640
---- 0000 0000 0000 0000 0000 0000 ---EPFR17[B,H,W]
0x644
---- 0000 0000 0000 0000 0000 0000 ---EPFR18[B,H,W]
0x648
---- ---- ---- ---- ---- ---- ---- 0000
-
0x700
0x704
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
+2
EPFR02[B,H,W]
0x608
0x64C - 0x6FC
M A N U A L
-
-
-
PZR0[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR1[B,H,W]
141
A.Register Map
1.Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
M A N U A L
+3
+2
+1
+0
---- ---- ---- ---- 0000 0000 0000 0000
142
CONFIDENTIAL
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+2
+1
---- ---- ---- ---- 0000 0000 0000 0000
PZR3[B,H,W]
0x70C
---- ---- ---- ---- 0000 0000 0000 0000
PZR4[B,H,W]
0x710
---- ---- ---- ---- 0000 0000 0000 0000
PZR5[B,H,W]
0x714
---- ---- ---- ---- 0000 0000 0000 0000
PZR6[B,H,W]
0x718
---- ---- ---- ---- 0000 0000 0000 0000
PZR7[B,H,W]
0x71C
---- ---- ---- ---- 0000 0000 0000 0000
PZR8[B,H,W]
0x720
---- ---- ---- ---- 0000 0000 0000 0000
PZR9[B,H,W]
0x724
---- ---- ---- ---- 0000 0000 0000 0000
PZRA[B,H,W]
0x728
---- ---- ---- ---- 0000 0000 0000 0000
PZRB[B,H,W]
0x72C
---- ---- ---- ---- 0000 0000 0000 0000
PZRC[B,H,W]
0x730
---- ---- ---- ---- 0000 0000 0000 0000
PZRD[B,H,W]
0x734
---- ---- ---- ---- 0000 0000 0000 0000
PZRE[B,H,W]
0x738
---- ---- ---- ---- 0000 0000 0000 0000
PZRF[B,H,W]
0x73C
---- ---- ---- ---- 0000 0000 0000 0000
-
-
0x800
*
0x804
*
0x808 - 0xFFC
-
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
+0
PZR2[B,H,W]
0x708
0x740 - 0x7FC
M A N U A L
-
-
-
-
-
143
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
HDMI-CEC/Remote Control Receiver ch.0 Base_Address : 0x4003_4000
HDMI-CEC/Remote Control Receiver ch.1 Base_Address : 0x4003_4100
The MCU simulator model does not support HDMI-CEC/Remote Control Receiver. It is Reserved area.
In the MCU simulator model, read and write access in HDMI-CEC/Remote Control Receiver area are
supported.
Base_Address
+ Address
Register
+3
+2
+1
0x00
-
-
-
0x04
-
-
-
0x08
-
-
-
0x0C
-
-
-
0x10 - 0x3F
-
-
0x40
-
-
0x44
-
-
0x48
-
-
0x4C
-
-
0x50
-
-
0x54
-
-
0x58
-
-
0x5C
-
-
0x60
-
-
0x64
-
-
0x68 - 0xFC
-
-
0x00 0xFC
144
CONFIDENTIAL
RCCR[B,H,W]
0---0000
RCSHW[B,H,W]
00000000
RCDBHW[B,H,W]
00000000
RCADR1[B,H,W]
RCADR2[B,H,W]
---00000
---00000
RCDTHH[B,H,W]
RCDTHL[B,H,W]
00000000
00000000
RCDTLH[B,H,W]
RCDTLL[B,H,W]
00000000
00000000
RCCKD[H,W]
---00000 00000000
RCRC[B,H,W]
RCRHW[B,H,W]
---0---0
00000000
RCLE[B,H,W]
00000-00
RCLELW[B,H,W]
RCLESW[B,H,W]
00000000
00000000
-
Register
Base_Address
+ Address
+0
TXCTRL[B,H,W]
--0000-0
TXDATA[B,H,W]
00000000
TXSTS[B,H,W]
--00---0
SFREE[B,H,W]
----0000
RCST[B,H,W]
00000000
RCDAHW[B,H,W]
00000000
+3
+2
+1
+0
-
-
-
-
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
LVD
M A N U A L
Base_Address : 0x4003_5000
TYPE0/TYPE1/TYPE2/TYPE4/TYPE5 products
Register
Base_Address
+ Address
+3
+2
+1
0x000
-
-
-
0x004
-
-
-
0x008
-
-
-
+0
LVD_CTL [B,H,W]
010000-LVD_STR [B,H,W]
0------LVD_CLR [B,H,W]
1-------
LVD_RLR[W]
0x00C
00000000 00000000 00000000 00000001
LVD_STR2
0x010
-
-
0-------
0x014 - 0xFFC
-
-
-
-
+1
+0
TYPE3, and TYPE6 to TYPE12 products
Register
Base_Address
+ Address
+3
+2
LVD_CTL[B, H, W]
1-0001-- 0-00000- *6
100001-- 000100-- *7
100001-- 000011-- *8
0x000
-
-
0x004
-
-
-
0x008
-
-
-
LVD_STR[B,H,W]
0------LVD_CLR[B,H,W]
1-------
LVD_RLR[W]
0x00C
00000000 00000000 00000000 00000001
LVD_STR2
0x010
-
-
01------
0x014 - 0x7FC
-
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
-
-
-
145
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
DS_Mode
Base_Address : 0x4003_5100
The MCU simulator model does not support DS_Mode. It is Reserved area. In the MCU simulator model,
read and write access in DS_Mode area are supported.
Register
Base_Address
+ Address
+3
+2
+1
0x000
-
-
-
0x004
-
-
-
0x008 - 0x6FC
-
-
-
0x700
-
-
-
0x704
-
-
-
0x708
-
-
0x70C
-
-
0x710
-
-
-
0x714
-
-
-
0x718 - 0x7FC
-
-
-
-
BUR04[B,H,W]
BUR03[B,H,W]
BUR02[B,H,W]
BUR01[B,H,W]
00000000
00000000
00000000
00000000
BUR08[B,H,W]
BUR07[B,H,W]
BUR06[B,H,W]
BUR05[B,H,W]
00000000
00000000
00000000
00000000
BUR012[B,H,W]
BUR11[B,H,W]
BUR10[B,H,W]
BUR09[B,H,W]
00000000
00000000
00000000
00000000
BUR16[B,H,W]
BUR15[B,H,W]
BUR14[B,H,W]
BUR13[B,H,W]
00000000
00000000
00000000
00000000
-
-
-
-
0x800
0x804
0x808
0x80C
0x810 - 0xEFC
+0
REG_CTL[B,H,W]
-------0
RCK_CTL[B,H,W]
------01
PMD_CTL[B,H,W]
-------0
WRFSR[B,H,W]
------00
WIFSR[B,H,W]
------00 00000000
WIER[B,H,W]
------00 00000-00
WILVR[B,H,W]
-----000
DSRAMR[B,H,W]
------00
Register
Base_Address
+ Address
+3
+2
+1
+0
0x000 - 0xFFC
-
-
-
-
146
CONFIDENTIAL
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
USB Clock
M A N U A L
Base_Address : 0x4003_6000
The MCU simulator model does not support USB Clock. It is Reserved area. In the MCU simulator model, read and write
access in USB Clock area are supported.
Products other than TYPE2
Register
Base_Address
+ Address
+3
+2
+1
0x000
-
-
-
0x004
-
-
-
0x008
-
-
-
0x00C
-
-
-
+0
UCCR[B,H,W]
------00
UPCR1[B,H,W]
------00
UPCR2[B,H,W]
-----000
UPCR3[B,H,W]
---00000
UPCR4[B,H,W]
0x010
-
-
-
---10111 *1
-0111011 *2
0x014
-
-
-
0x018
-
-
-
0x01C
-
-
-
0x020
-
-
-
0x024
-
-
-
0x028 - 0x02C
-
-
-
0x030
-
-
-
UP_STR[B,H,W]
-------0
UPINT_ENR[B,H,W]
-------0
UPINT_CLR[B,H,W]
-------0
UPINT_STR[B,H,W]
-------0
UPCR5[B,H,W]
----0100
USBEN[B,H,W]
-------0
0x034 - 0x0FC
-
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
-
-
-
147
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
TYPE2 products
Register
Base_Address
+ Address
+3
+2
+1
0x000
-
-
-
0x004
-
-
-
0x008
-
-
-
0x00C
-
-
-
0x010
-
-
-
0x014
-
-
-
0x018
-
-
-
0x01C
-
-
-
0x020
-
-
-
0x024
-
-
-
0x028
-
-
-
0x02C
-
-
-
0x030
-
-
-
0x034
-
-
-
+0
UCCR[B,H,W]
-0000000
UPCR1[B,H,W]
------00
UPCR2[B,H,W]
-----000
UPCR3[B,H,W]
---00000
UPCR4[B,H,W]
-0111011
UP_STR[B,H,W]
-------0
UPINT_ENR[B,H,W]
-------0
UPINT_CLR[B,H,W]
-------0
UPINT_STR[B,H,W]
-------0
UPCR5[B,H,W]
----0100
UPCR6[B,H,W]
----0010
UPCR7[B,H,W]
-------0
USBEN[B,H,W]
-------0
USBEN1[B,H,W]
-------0
0x038 - 0x0FC
-
-
0x000 0x0FC
148
CONFIDENTIAL
-
Register
Base_Address
+ Address
-
+3
+2
+1
+0
-
-
-
-
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
CAN_Prescaler
Base_Address : 0x4003_7000
The MCU simulator model does not support CAN_Prescaler.. It is Reserved area. In the MCU simulator
model, read and write access in CAN_Prescaler. area are supported.
Register
Base_Address
+ Address
+3
+2
+1
0x000
-
-
-
0x004 - 0xFFC
-
-
-
-
0x0000 0x0FFC
----1011
+3
+2
+1
+0
-
-
-
-
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
CANPRE[B,H,W]
Register
Base_Address
+ Address
+0
149
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
MFS
Products other than TYPE8/TYPE12
MFS ch.0
MFS ch.1
MFS ch.2
MFS ch.3
MFS ch.4
MFS ch.5
MFS ch.6
MFS ch.7
Base_Address : 0x4003_8000
Base_Address : 0x4003_8100
Base_Address : 0x4003_8200
Base_Address : 0x4003_8300
Base_Address : 0x4003_8400
Base_Address : 0x4003_8500
Base_Address : 0x4003_8600
Base_Address : 0x4003_8700
Register
Base_Address
+ Address
+3
+2
0x000
-
-
0x004
-
-
0x008
-
-
0x00C
-
-
0x010
-
-
0x014
-
-
0x018
-
-
0x1C
0x020 - 0x0FC
150
CONFIDENTIAL
-
-
+1
+0
SCR/ IBCR[B,H,W]
SMR[B,H,W]
0--00000
000000-0
SSR[B,H,W]
ESCR/ IBSR[B,H,W]
0-000011
00000000
RDR/TDR[H,W]
-------0 00000000
BGR1[B,H,W]
BGR0[B,H,W]
00000000
00000000
ISMK[B,H,W]
ISBA[B,H,W]
--------
--------
FCR1[B,H,W]
FCR0[B,H,W]
---00100
-0000000
FBYTE2[B,H,W]
00000000
FBYTE1[B,H,W]
00000000
EIBCR[B, H, W]
--001100
-
-
-
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
MFS Noise Filter Control Base_Address : 0x4003_8800
Register
Base_Address
+ Address
+3
+2
0x000
-
-
0x004 - 0x0FC
-
-
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
+1
+0
I2CDNF[B,H,W]
00000000
-
-
151
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
TYPE8/TYPE12 products
MFS ch.0
MFS ch.1
MFS ch.2
MFS ch.3
MFS ch.4
MFS ch.5
MFS ch.6
MFS ch.7
MFS ch.8
MFS ch.9
MFS ch.10
MFS ch.11
MFS ch.12
MFS ch.13
MFS ch.14
MFS ch.15
Base_Address : 0x4003_8000
Base_Address : 0x4003_8100
Base_Address : 0x4003_8200
Base_Address : 0x4003_8300
Base_Address : 0x4003_8400
Base_Address : 0x4003_8500
Base_Address : 0x4003_8600
Base_Address : 0x4003_8700
Base_Address : 0x4003_8800
Base_Address : 0x4003_8900
Base_Address : 0x4003_8A00
Base_Address : 0x4003_8B00
Base_Address : 0x4003_8C00
Base_Address : 0x4003_8D00
Base_Address : 0x4003_8E00
Base_Address : 0x4003_8F00
Register
Base_Address
+ Address
+3
+2
0x000
-
-
0x004
-
-
0x008
-
-
0x00C
-
-
0x010
-
-
0x014
-
-
0x018
-
-
0x1C
0x020 - 0x0FC
152
CONFIDENTIAL
-
-
+1
+0
SCR/ IBCR[B,H,W]
SMR[B,H,W]
0--00000
000000-0
SSR[B,H,W]
ESCR/ IBSR[B,H,W]
0-000011
00000000
RDR/TDR[H,W]
-------0 00000000
BGR1[B,H,W]
BGR0[B,H,W]
00000000
00000000
ISMK[B,H,W]
ISBA[B,H,W]
--------
--------
FCR1[B,H,W]
FCR0[B,H,W]
---00100
-0000000
FBYTE2[B,H,W]
00000000
FBYTE1[B,H,W]
00000000
EIBCR[B, H, W
--001000
-
-
-
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
CRC
M A N U A L
Base_Address : 0x4003_9000
Register
Base_Address
+ Address
+3
+2
+1
0x000
-
-
-
CRCCR[B,H,W]
-0000000
CRCINIT[B,H,W]
0x004
11111111 11111111 11111111 11111111
CRCIN[B,H,W]
0x008
00000000 00000000 00000000 00000000
CRCR[B,H,W]
0x00C
Watch Counter
+0
11111111 11111111 11111111 11111111
Base_Address : 0x4003_A000
Register
Base_Address
+ Address
+3
+2
+1
+0
0x000
-
WCCR[B,H,W]
WCRL[B,H,W]
WCRD[B,H,W]
00--0000
--000000
--000000
0x004 - 0x00C
-
-
-
-
0x010
-
-
0x014
-
-
-
0x018 - 0xFFC
-
-
-
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
CLK_SEL[B,H,W]
-----000 -------0
CLK_EN[B,H,W]
------00
-
153
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
RTC
Base_Address : 0x4003_B000
The MCU simulator model does not support RTC. It is Reserved area. In the MCU simulator model, read
and write access in RTC area are supported.
TYPE3/TYPE4/TYPE5 products
Base_Address
+ Address
Register
+3
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
WTDR[B,H,W]
--000000
+0
WTSR[B,H,W]
-0000000
-0000000
WTYR[B,H,W]
WTMOR[B,H,W]
WTDW[B,H,W]
00000000
---00000
-----000
ALDR[B,H,W]
ALHR[B,H,W]
ALMIR[B,H,W]
--000000
--000000
-0000000
ALYR[B,H,W]
ALMOR[B,H,W]
-
-
0x020
-
0x024
-
0x028
-
0x02C - 0xFFC
-
CONFIDENTIAL
+1
WTCR1[B,H,W]
00000000 00000000 ---00000 -00000-0
WTCR2[B,H,W]
-------- -------- -----000 -------0
WTBR[B,H,W]
-------- 00000000 00000000 00000000
WTHR[B,H,W]
WTMIR[B,H,W]
--000000
0x01C
154
+2
00000000
---00000
WTTR[B,H,W]
-------- ------00 00000000 00000000
WTCLKM[B,H,W]
------00
WTCALEN[B,H,W]
-------0
WTDIVEN[B,H,W]
------00
-
-
WTCLKS [B,H,W]
-------0
WTCAL [B,H,W]
-0000000
WTDIV [B,H,W]
----0000
-
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
TYPE6 to TYPE12 products
Base_Address
+ Address
Register
+3
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
WTDR[B,H,W]
--000000
+2
-0000000
WTYR[B,H,W]
WTMOR[B,H,W]
WTDW[B,H,W]
00000000
---00000
-----000
ALDR[B,H,W]
ALHR[B,H,W]
ALMIR[B,H,W]
--000000
--000000
-0000000
ALYR[B,H,W]
ALMOR[B,H,W]
-
-
-
0x024
-
0x028
-
0x02C
-
0x030
-
0x034 - 0xFFC
-
Register
+3
+2
+1
+0
-
-
-
-
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
-
00000000
---00000
WTTR[B,H,W]
-------- ------00 00000000 00000000
WTCLKM[B,H,W]
WTCLKS [B,H,W]
------00
-------0
WTCALEN[B,H,W]
WTCAL [B,H,W]
-------0
------00 00000000
WTDIVEN[B,H,W]
WTDIV [B,H,W]
------00
----0000
WTCALPRD [B,H,W]
--010011
WTCOSEL [B,H,W]
-------0
-
Base_Address
0xFFC
WTSR[B,H,W]
-0000000
0x020
0x000 -
+0
--000000
0x01C
+ Address
+1
WTCR1[B,H,W]
00000000 00000000 ---00000 -00000-0
WTCR2[B,H,W]
-------- -------- -----000 -------0
WTBR[B,H,W]
-------- 00000000 00000000 00000000
WTHR[B,H,W]
WTMIR[B,H,W]
155
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
EXT-Bus I/F
Base_Address : 0x4003_F000
The MCU simulator model does not support EXT-Bus I/F. It is Reserved area. In the MCU simulator
model, read and write access in EXT-Bus I/F area are supported.
Register
Base_Address
+ Address
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
0x0040
156
CONFIDENTIAL
+3
+2
+1
+0
MODE0[W]
-------- -------- --000-00 00000000
MODE1[W]
-------- -------- --000-00 00000000
MODE2[W]
-------- -------- --000-00 00000000
MODE3[W]
-------- -------- --000-00 00000000
MODE4[W]
-------- -------- --000-00 00000001
MODE5[W]
-------- -------- --000-00 00000000
MODE6[W]
-------- -------- --000-00 00000000
MODE7[W]
-------- -------- --000-00 00000000
TIM0[W]
00000101 01011111 11110000 00001111
TIM1[W]
00000101 01011111 11110000 00001111
TIM2[W]
00000101 01011111 11110000 00001111
TIM3[W]
00000101 01011111 11110000 00001111
TIM4[W]
00000101 01011111 11110000 00001111
TIM5[W]
00000101 01011111 11110000 00001111
TIM6[W]
00000101 01011111 11110000 00001111
TIM7[W]
00000101 01011111 11110000 00001111
AREA0[W]
-------- -0001111 -------- 00000000
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
0x0044
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
M A N U A L
+2
+1
+0
AREA1[W]
-------- -0001111 -------- 00010000
157
A.Register Map
1.Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
-------- -0001111 -------- 00110000
AREA4[W]
-------- -0001111 -------- 01000000
AREA5[W]
0x0054
-------- -0001111 -------- 01010000
AREA6[W]
0x0058
-------- -0001111 -------- 01100000
AREA7[W]
0x005C
-------- -0001111 -------- 01110000
ATIM0[W]
0x0060
-------- -------- ----0100 01011111
ATIM1[W]
0x0064
-------- -------- ----0100 01011111
ATIM2[W]
0x0068
-------- -------- ----0100 01011111
ATIM3[W]
0x006C
-------- -------- ----0100 01011111
ATIM4[W]
0x0070
-------- -------- ----0100 01011111
ATIM5[W]
0x0074
-------- -------- ----0100 01011111
ATIM6[W]
0x0078
-------- -------- ----0100 01011111
ATIM7[W]
0x007C
-------- -------- ----0100 01011111
-
CONFIDENTIAL
-
-
-
DCLKR[W]
0x0300
158
+0
AREA3[W]
0x0050
0x03FC
+1
-------- -0001111 -------- 00100000
0x004C
0x0304 -
+2
AREA2[W]
0x0048
0x0080 0x02FC
M A N U A L
-------- -------- -------- ---00001
-
-
-
-
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
0x0000 0x03FC
+3
+2
+1
+0
-
-
-
-
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
M A N U A L
159
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
USB ch.0
Base_Address : 0x4004_0000
USB ch.1
Base_Address : 0x4005_0000
The MCU simulator model does not support USB. It is Reserved area. In the MCU simulator model, read
and write access in USB area are supported.
Register
Base_Address
+ Address
+3
+2
0x2100
-
-
0x2104
-
-
0x2108
-
-
0x210C
-
-
0x2110
-
-
0x2114
-
-
0x2118
-
-
0x211C
-
-
0x2120
-
-
0x2124
-
-
0x2128
-
-
0x212C
-
-
0x2130
-
-
0x2134
-
-
0x2138
-
-
0x213C
-
-
160
CONFIDENTIAL
+1
+0
HCNT1[B,H,W]
HCNT0[B,H,W]
-----001
00000000
HERR[B,H,W]
HIRQ[B,H,W]
00000011
0-000000
HFCOMP[B,H,W]
HSTATE[B,H,W]
00000000
--010010
HRTIMER(1/0)[B,H,W]
00000000 00000000
HADR[B,H,W]
HRTIMER(2)[B,H,W]
-0000000
-----00
HEOF(1/0)[B,H,W]
--000000 00000000
HFRAME(1/0)[B,H,W]
-----000 00000000
-
HTOKEN [B,H,W]
00000000
UDCC[B,H,W]
-------- 10100-00
EP0C[H,W]
------0- -1000000
EP1C[H,W]
01100001 00000000
EP2C[H,W]
0110000- -1000000
EP3C[H,W]
0110000- -1000000
EP4C[H,W]
0110000- -1000000
EP5C[H,W]
0110000- -1000000
TMSP[H,W]
-----000 00000000
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+2
0x2140
-
-
0x2144
-
-
0x2148
-
-
0x214C
-
-
0x2150
-
-
0x2154
-
-
0x2158
-
-
0x215C
-
-
0x2160
-
-
0x2164
-
-
0x2168
-
-
0x216C
-
-
0x2170
-
-
0x2174
-
-
0x2178 0x217C
-
-
0x2100 0x217C
+0
UDCIE[B,H,W]
UDCS[B,H,W]
--000000
--000000
EP0IS[H,W]
10---1-- -------EP0OS[H,W]
100--00- -XXXXXXX
EP1S[H,W]
100-000X XXXXXXXX
EP2S[H,W]
100-000- -XXXXXXX
EP3S[H,W]
100-000- -XXXXXXX
EP4S[H,W]
100-000- -XXXXXXX
EP5S[H,W]
100-000- -XXXXXXX
EP0DTH [B,H,W]
EP0DTL [B,H,W]
XXXXXXXX
XXXXXXXX
EP1DTH [B,H,W]
EP1DTL [B,H,W]
XXXXXXXX
XXXXXXXX
EP2DTH [B,H,W]
EP2DTL [B,H,W]
XXXXXXXX
XXXXXXXX
EP3DTH [B,H,W]
EP3DTL [B,H,W]
XXXXXXXX
XXXXXXXX
EP4DTH [B,H,W]
EP4DTL [B,H,W]
XXXXXXXX
XXXXXXXX
EP5DTH [B,H,W]
EP5DTL [B,H,W]
XXXXXXXX
XXXXXXXX
-
-
+3
+2
+1
+0
-
-
-
-
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
+1
Register
Base_Address
+ Address
M A N U A L
161
A.Register Map
1.Register Map
P E R I P H E R A L
DMAC
Base_Address : 0x4006_0000
Register
Base_Address
+ Address
0x0000
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
0x0040
0x0044
0x0048
0x004C
0x0050
162
CONFIDENTIAL
M A N U A L
+3
+2
+1
+0
DMACR[B,H,W]
00-00000 -------- -------- -------DMACA0[B,H,W]
00000000 0---0000 00000000 00000000
DMACB0[B,H,W]
--000000 00000000 00000000 -------0
DMACSA0[B,H,W]
00000000 00000000 00000000 00000000
DMACDA0[B,H,W]
00000000 00000000 00000000 00000000
DMACA1[B,H,W]
00000000 0---0000 00000000 00000000
DMACB1[B,H,W]
--000000 00000000 00000000 -------0
DMACSA1[B,H,W]
00000000 00000000 00000000 00000000
DMACDA1[B,H,W]
00000000 00000000 00000000 00000000
DMACA2[B,H,W]
00000000 0---0000 00000000 00000000
DMACB2[B,H,W]
--000000 00000000 00000000 -------0
DMACSA2[B,H,W]
00000000 00000000 00000000 00000000
DMACDA2[B,H,W]
00000000 00000000 00000000 00000000
DMACA3[B,H,W]
00000000 0---0000 00000000 00000000
DMACB3[B,H,W]
--000000 00000000 00000000 -------0
DMACSA3[B,H,W]
00000000 00000000 00000000 00000000
DMACDA3[B,H,W]
00000000 00000000 00000000 00000000
DMACA4[B,H,W]
00000000 0---0000 00000000 00000000
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
+0
--000000 00000000 00000000 -------0
DMACSA4[B,H,W]
0x0058
00000000 00000000 00000000 00000000
DMACDA4[B,H,W]
0x005C
00000000 00000000 00000000 00000000
DMACA5[B,H,W]
0x0060
00000000 0---0000 00000000 00000000
DMACB5[B,H,W]
0x0064
--000000 00000000 00000000 -------0
DMACSA5[B,H,W]
0x0068
00000000 00000000 00000000 00000000
DMACDA5[B,H,W]
0x006C
00000000 00000000 00000000 00000000
DMACA6[B,H,W]
0x0070
00000000 0---0000 00000000 00000000
DMACB6[B,H,W]
0x0074
--000000 00000000 00000000 -------0
DMACSA6[B,H,W]
0x0078
00000000 00000000 00000000 00000000
DMACDA6[B,H,W]
0x007C
00000000 00000000 00000000 00000000
DMACA7[B,H,W]
0x0080
00000000 0---0000 00000000 00000000
DMACB7[B,H,W]
0x0084
--000000 00000000 00000000 -------0
DMACSA7[B,H,W]
0x0088
00000000 00000000 00000000 00000000
DMACDA7[B,H,W]
0x008C
00000000 00000000 00000000 00000000
-
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
+1
DMACB4[B,H,W]
0x0054
0x0090 0x00FC
+2
-
-
-
163
A.Register Map
1.Register Map
P E R I P H E R A L
M A N U A L
CAN ch.0
Base_Address : 0x4006_2000
CAN ch.1
Base_Address : 0x4006_3000
The MCU simulator model does not support CAN. It is Reserved area. In the MCU simulator model, read
and write access in CAN area are supported.
Register
Base_Address
+ Address
+3
0x0000
0x0004
0x0008
+2
+1
+0
STATR[B,H,W]
CTRLR[B,H,W]
-------- 00000000
-------- 000-0001
BTR[B,H,W]
ERRCNT[B,H,W]
-0100011 00000001
00000000 00000000
TESTR[B,H,W]
INTR[B,H,W]
-------- X00000--
00000000 00000000
BRPER[B,H,W]
0x000C
-
-------- ----0000
0x0010
0x0014
0x0018
IF1CMSK[B,H,W]
IF1CREQ[B,H,W]
-------- 00000000
0------- 00000001
IF1MSK2[B,H,W]
IF1MSK1[B,H,W]
11-11111 11111111
11111111 11111111
IF1ARB2[B,H,W]
IF1ARB1[B,H,W]
00000000 00000000
00000000 00000000
IF1MCTR[B,H,W]
0x001C
-
00000000 0---0000
0x0020
0x0024
0x0028 0x002F
0x0034
0x0040
0x0044
164
CONFIDENTIAL
IF1DTA1[B,H,W]
00000000 00000000
00000000 00000000
IF1DTB2[B,H,W]
IF1DTB1[B,H,W]
00000000 00000000
00000000 00000000
-
0x0030
0x0038 0x003C
IF1DTA2[B,H,W]
-
-
-
IF1DTA1[B,H,W]
IF1DTA2[B,H,W]
00000000 00000000
00000000 00000000
IF1DTB1[B,H,W]
IF1DTB2[B,H,W]
00000000 00000000
00000000 00000000
-
-
-
-
IF2CMSK[B,H,W]
IF2CREQ[B,H,W]
-------- 00000000
0------- 00000001
IF2MSK2[B,H,W]
IF2MSK1[B,H,W]
11-11111 11111111
11111111 11111111
MN706-00043-1v0-E, June 20, 2014
A.Register Map
1.Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
0x0048
0x004C
0x0054
0x0064
+1
+0
IF2ARB2[B,H,W]
IF2ARB1[B,H,W]
00000000 00000000
00000000 00000000
IF2MCTR[B,H,W]
-
00000000 0---0000
IF2DTA2[B,H,W]
IF2DTA1[B,H,W]
00000000 00000000
00000000 00000000
IF2DTB2[B,H,W]
IF2DTB1[B,H,W]
00000000 00000000
00000000 00000000
-
0x0060
0x0068 0x007C
+2
-
0x0050
0x0058 0x005C
M A N U A L
-
-
-
IF2DTA1[B,H,W]
IF2DTA2[B,H,W]
00000000 00000000
00000000 00000000
IF2DTB1[B,H,W]
IF2DTB2[B,H,W]
00000000 00000000
00000000 00000000
-
-
-
-
TREQR2[B,H,W]
TREQR1[B,H,W]
00000000 00000000
00000000 00000000
0x0080
0x0084 –
0x008F
-
0x0090
0x0094 0x009F
0x00B4 0x0FFC
00000000 00000000
00000000 00000000
-
0x0000 0x0FFC
INTPND1[B,H,W]
00000000 00000000
00000000 00000000
-
-
-
MSGVAL2[B,H,W]
MSGVAL1[B,H,W]
00000000 00000000
00000000 00000000
-
-
-
-
Register
+3
+2
+1
+0
-
-
-
-
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
-
INTPND2[B,H,W]
Base_Address
+ Address
NEWDT1[B,H,W]
-
0x00B0
-
NEWDT2[B,H,W]
-
0x00A0
0x00A4 0x00AF
-
165
A.Register Map
1.Register Map
P E R I P H E R A L
Ether-MAC ch.0
Ether-MAC ch.1
M A N U A L
Base_Address : 0x4006_4000
Base_Address : 0x4006_7000
The MCU simulator model does not support Ether-MAC. It is Reserved area. In the MCU simulator model, read and write
access in Ether-MAC area are supported.
Note:
For the register details of Ether-MAC block, refer to the "Ethernet Part".
Ether-Control
Base_Address : 0x4006_6000
The MCU simulator model does not support Ether-Control. It is Reserved area. In the MCU simulator model, read and write
access in Ether-Control area are supported.
Note:
For the register details of Ether-Control block, refer to the "Ethernet Part".
WorkFlash_IF
Base_Address : 0x200E_0000
The MCU simulator model does not support WorkFlash_IF registers.
Register
Base_Address
+ Address
+3
+2
0x000
WFASZR[B,H,W]
0x004
WFRWTR[B,H,W]
0x008
WFSTR[B,H,W]
0x00C - 0xFFF
-
-
+1
+0
-
-
Note:
For the register details of Workflash IF block, refer to the "FLASH PROGRAMMING MANUAL" of the product used.
166
CONFIDENTIAL
MN706-00043-1v0-E, June 20, 2014
B. List of Notes
This section explains notes for each function.
1. Notes when high-speed CR is used for the master clock
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
167
B. List of Notes
1.Notes when high-speed CR is used for the master clock
P E R I P H E R A L
M A N U A L
1. Notes when high-speed CR is used for the master clock
This section explains notes when the high-speed CR is used for the master clock.
The frequency of the high-speed CR varies depending on the temperature and/or the power supply voltage.
The following table shows notes on each function macro when the high-speed CR is used for the master clock.
Furthermore, pay attention to notes when the high-speed CR is used as an input clock of the PLL and the master clock is
selected for PLL.
Notes on Each Macro
Macro
Function/mode
Base Clock
HCLK/FCLK
Timer
Multi-function Timer
Base Timer
Watch Timer
Dual Timer
Watch Dog Timer
Quadrature
Sampling Time
Compare Tim
A/D Converter
USB
Ethernet-MAC
CAN
Multi Function
Serial Interface
UART
CSIO
I2C
LIN
Debug Interface
Serial Wire
Flash Memory
Serial Write
External Bus
Interface
Clock Output
168
CONFIDENTIAL
Notes
The maximum frequency of the high-speed CR
shall not exceed the upper limit of the internal
operation clock frequency specified in the "Data
Sheet" of the product used.
The frequency variation of the high-speed CR
should be considered for the timer count value of
each macro.
Considering the frequency variation of the
high-speed CR, the sampling time and the compare
time of the A/D converter shall satisfy the
specification specified in the "Data Sheet" of the
product used.
As the frequency accuracy does not meet the
required specification, these macros cannot be used
when the high-speed CR is used for the master
clock.
Even if the frequency of the high-speed CR is the
minimum or the maximum value, the baud rate
error should be considered.
The baud rate error shall not exceed the limit.
The frequency variation of the high-speed CR
should be considered for the communication of
each macro.
As the required frequency accuracy cannot be met,
this function cannot be used as master.
As slave, this function can be used.
As a slave, the specified baud rate has more error at
the maximum/minimum frequency of high-speed
clock. So, if the error limit of the baud rate is
exceeded, this function cannot be used.
As the frequency variation of the high-speed CR,
the SWV(Serial Wire View) may not be used.
The serial write cannot be supported for TYPE0,
TYPE1, TYPE2, and TYPE4 products
When the serial write is required, the clock should
be supplied to the X0/X1pins.
When the external bus clock output is used, the
frequency variation of the high-speed CR should be
considered for devices to be connected.
MN706-00043-1v0-E, June 20, 2014
C. List of Limitations
This section shows the differences between series.
1. List of Limitations for TYPE0 Products
2. List of Limitations for TYPE1 Products
June 20, 2014, FM3_MN706-00043-1v0-E
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C. List of Limitations
1.List of Limitations for TYPE0 Products
P E R I P H E R A L
M A N U A L
1. List of Limitations for TYPE0 Products
This section shows the differences in the MB9A100A Series, MB9B500A/400A/300A/100A Series,
MB9A100 Series and MB9B500/400/300/100 Series in a table.
The "Items" in the table are as written in this manual.
Item
Timer Part 1.6.7
Hardware Watchdog
Timer Load Register
(WDG_LDR)
Details
Following restrictions should be added to the <Notes> of "6.7. Hardware
Watchdog Timer Load Register".
If a value is written to WDG_LDR again during the reloading period of
the Hardware watchdog timer * (low-speed CR 4 cycle period after
reloading the counter), the writing operation is ignored.
Read the software of the appropriate register to check whether the writing
value have been reflected to WDG_LDR properly.
* The condition of counter reloading
1. Clearing watchdog timer (Writing a value to WDG_ICL register)
2. Writing a value to WDG_LDR register
Timer Part 1.6.9
Hardware Watchdog
Timer Control Register
(WDG_CTL)
Following restrictions should be added to the <Notes> of "6.9. Hardware
Watchdog Timer Control Register".
After writing "0" to the INTEN (watchdog counter enable) bit of the
WDG_CTL register, if "1" is written again within 2 cycles of the low-speed CR
(50KHz to 150KHz), operation may resume without reloading the count value
from WDG_LDR.
When setting the INTEN bit to "1" again after setting it to "0", always ensure a
period of 2 clock cycles of the low-speed CR before setting. Alternatively, clear
the timer using the WDG_ICL register immediately after writing "1" to INTEN
to execute a reload.
Timer Part 3-2
Watch Counter
Following restrictions should be added to "CHAPTER 3-2: Watch Counter".
*These restrictions are only for MB9A100 Series and MB9B500/400/300/100
Series.
In Sub timer mode or Low speed CR timer mode, when the watch counter with
sub crystal oscillator is used, the count value would be delayed from the actual
time at the returning from an interrupt, by lengthening the interval of the low
speed CR×35 cycles (Typ 350s) watch counter.
In Sub sleep mode or Low speed CR sleep mode, the counter value is not
delayed.
Analog Macro Part
1-3.5.13
Sampling Time
Selection Register
(ADSS)
170
CONFIDENTIAL
Following restrictions should be added to "5.13. Sampling Time Selection
Register".
In this series, the sampling time set in the Sampling Time Setup Register
(ADST1) cannot be used.
Enable the sampling time set in the Sampling Time Setup Register (ADST0)
only.
Always write "0" to each bit of the Sampling Time Selection Register (ADSS0
to ADSS3).
MN706-00043-1v0-E, June 20, 2014
C. List of Limitations
1.List of Limitations for TYPE0 Products
P E R I P H E R A L
Item
M A N U A L
Details
Communication Macro
Part
1-2.7.9
1-3.5.9
1-4.6.9
1-5.5.12
FIFO Byte Register
(FBYTE)
Following notes should be added to
"7.9. FIFO Byte Register (FBYTE)" in chapter 1-2,
"5.9. FIFO Byte Register (FBYTE)" in chapter 1-3,
"6.9. FIFO Byte Register (FBYTE)" in chapter 1-4,
"5.12. FIFO Byte Register (FBYTE)" in chapter 1-5.
Communication Macro
Part 3-1.2
End-point
configuration of the
USB function
Following notes should be added to " End-point configuration of USB
function".
USB function does not support ISO (isochronous transfer).
Only Comb1 of setting combinations is valid.
Communication Macro
Part 3-1.3.6
DMA transfer function
Following restrictions should be added to " Automatic data size transfer
mode".
If all the following conditions are met, the receive data full flag
(SSR:RDRF) is not set to "1" despite the valid data of the number of
FBYTE settings in the receive FIFO. If the setting value of FBYTE is "2"
or more, this operation is not applied.
The setting value of FBYTE is "1".
Both the number of valid data of receive FIFO and the number of
FBYTE settings are "1".
The data in receive FIFO is read at the same time when the
multi-function serial interface macro receives the data and the
received data is written to receive FIFO.
However, in case that one of the followings occurs later, the receive
data full flag (SSR:RDRF) is set to "1".
Next data is received.
The receive time idle of 8-bit time or more is detected when the
receive FIFO idle is enabled (FCR:FRIIE=1).
In this series, if the IN direction Automatic data size transfer mode is used in
the Short packet transfer, packet transfer may not start even after DMA transfer
is finished.
In addition, it is prohibited to set USB as both the transfer source and transfer
destination.
[Workaround]
Transfer data using CPU.
Communication Macro
Part 3-1.3.7
NULL transfer function
Communication Macro
Part 3-1.5.3
EP1 to 5 Status Registers
(EP1C to EP5C)
The following description should be added as the NULL transfer mode
restriction.
In this series, NULL transfer may not start after DMA transfer, even in the
NULL transfer mode. Use this mode under the setting of EP1C to EP5C:NULE
= "0".
[Workaround]
To perform the NULL transfer, firstly set DMAE = "0" and clear the DRQ bit
without writing the buffer data.
See Notes of [bit10] DRQ bit in "23-1.5.9 EP1 to 5 Status Registers (EP1S to
EP5S)".
June 20, 2014, FM3_MN706-00043-1v0-E
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171
C. List of Limitations
1.List of Limitations for TYPE0 Products
P E R I P H E R A L
Item
M A N U A L
Details
Communication Macro
Part 3-1.5.3
EP1 to EP5 Control
Register
(EP1C to EP5C)
[bit 14:13] TYPE: The following end-point transfer types are supported.
TYPE
Operation mode
00
Setting is prohibited
01
Setting is prohibited
10
Bulk transfer
11
Interrupt transfer
Communication Macro
Part 3-1.5.10
EP0 to EP5 Data Registers
(EP0DTH to EP5DTH/
EP0DTL to EP5DTL)
Following restrictions should be added to "5.10. EP0 to EP5 Data Registers".
In this series, an indefinite data is read if serial read access to the above register
is performed on the AHB bus.
[Workaround]
Please make the software to prevent the serial read. In the programming using
C language, unintended serial read access on AHB bus may occur because of
the optimization by the compiler option etc. Please refer to " Reference 1" for
the workaround.
172
CONFIDENTIAL
MN706-00043-1v0-E, June 20, 2014
C. List of Limitations
2.List of Limitations for TYPE1 Products
P E R I P H E R A L
M A N U A L
2. List of Limitations for TYPE1 Products
This section shows the differences in the MB9A002 Series, MB9A310 Series, MB9A110 Series, in a
table.
The "Items" in the table are as written in this manual.
Item
Communication Macro
Part 1-2.7.9
1-3.5.9
1-4.6.9
1-5.5.12
FIFO Byte Register
(FBYTE)
Details
Following notes should be added to
"7.9. FIFO Byte Register (FBYTE)" in chapter 1-2,
"5.9. FIFO Byte Register (FBYTE)" in chapter 1-3,
"6.9. FIFO Byte Register (FBYTE)" in chapter 1-4,
"5.12. FIFO Byte Register (FBYTE)" in chapter 1-5.
If all the following conditions are met, the receive data full flag
(SSR:RDRF) is not set to "1" despite the valid data of number of FBYTE
settings in the receive FIFO. If the setting value of FBYTE is "2" or more,
this operation is not applied.
The setting value of FBYTE is "1".
Both the number of valid data of receive FIFO and the number of
FBYTE settings are "1"
The data in receive FIFO is read at the same time when the
multi-function serial interface macro receives the data and the
received data is written to receive FIFO.
However, in case that one of the followings occurs later, the receive
data full flag (SSR:RDRF) is set to "1".
Next data is received.
The receive time idle of 8-bit time or more is detected when the
receive FIFO idle is enabled (FCR:FRIIE=1).
June 20, 2014, FM3_MN706-00043-1v0-E
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173
C. List of Limitations
2.List of Limitations for TYPE1 Products
P E R I P H E R A L
M A N U A L
Reference 1
Example:
If the following C source codes are compiled, serial read access may occur because of the optimization by
the compiler option etc.
void do_ep0o(void)
{
int i;
int length;
unsigned int b0,b1,b2,b3;
b0 = (unsigned int)IO_EP0DT;
b1 = (unsigned int)IO_EP0DT;
b2 = (unsigned int)IO_EP0DT;
b3 = (unsigned int)IO_EP0DT;
buffer[0] = (unsigned short)b0;
buffer[1] = (unsigned short)b1;
buffer[2] = (unsigned short)b2;
buffer[3] = (unsigned short)b3;
}
The following is a workaround. (Execute processing in the following order)
void do_ep0o(void)
{
int i;
int length;
volatile int b0;
b0 = (unsigned int)IO_EP0DT;
buffer[0] = (unsigned short)b0;
b0 = (unsigned int)IO_EP0DT;
buffer[1] = (unsigned short)b0;
b0 = (unsigned int)IO_EP0DT;
buffer[2] = (unsigned short)b0;
b0 = (unsigned int)IO_EP0DT;
buffer[3] = (unsigned short)b0;
}
174
CONFIDENTIAL
MN706-00043-1v0-E, June 20, 2014
D. Product TYPE List
This section describes product TYPE.
0. Product TYPE List
June 20, 2014, FM3_MN706-00043-1v0-E
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D. Product TYPE List
1.Product TYPE List
P E R I P H E R A L
M A N U A L
1. Product TYPE List
In this manual, the products are classified into the following groups and are described as follows.
For the descriptions such as "TYPE0", see the relevant items of the target product in the list below.
Table 1 TYPE0 product list
Description in
this manual
512K bytes
TYPE0
Flash memory size
384K bytes
256K bytes
MB9BF506N
MB9BF506R
MB9BF506NA
MB9BF506RA
MB9BF506NB
MB9BF506RB
MB9BF505N
MB9BF505R
MB9BF505NA
MB9BF505RA
MB9BF505NB
MB9BF505RB
MB9BF504N
MB9BF504R
MB9BF504NA
MB9BF504RA
MB9BF504NB
MB9BF504RB
-
MB9BF406N
MB9BF406R
MB9BF406NA
MB9BF406RA
MB9BF405N
MB9BF405R
MB9BF405NA
MB9BF405RA
MB9BF404N
MB9BF404R
MB9BF404NA
MB9BF404RA
-
MB9BF306N
MB9BF306R
MB9BF306NA
MB9BF306RA
MB9BF306NB
MB9BF306RB
MB9BF305N
MB9BF305R
MB9BF305NA
MB9BF305RA
MB9BF305NB
MB9BF305RB
MB9BF304N
MB9BF304R
MB9BF304NA
MB9BF304RA
MB9BF304NB
MB9BF304RB
-
MB9BF106N
MB9BF106R
MB9BF106NA
MB9BF106RA
MB9BF105N
MB9BF105R
MB9BF105NA
MB9BF105RA
MB9BF104N
MB9BF104R
MB9BF104NA
MB9BF104RA
MB9BF102N
MB9BF102R
MB9BF102NA
MB9BF102RA
-
MB9AF105N
MB9AF105R
MB9AF105NA
MB9AF105RA
MB9AF104N
MB9AF104R
MB9AF104NA
MB9AF104RA
MB9AF102N
MB9AF102R
MB9AF102NA
MB9AF102RA
Table 2 TYPE1 product list
Description
in this
512K bytes
manual
Flash memory size
384K bytes
TYPE1
176
CONFIDENTIAL
128K bytes
MB9AF316M
MB9AF316N
MB9AF316MA
MB9AF316NA
MB9AF315M
MB9AF315N
MB9AF315MA
MB9AF315NA
MB9AF116M
MB9AF116N
MB9AF116MA
MB9AF116NA
MB9AF115M
MB9AF115N
MB9AF115MA
MB9AF115NA
256K bytes
128K bytes
64K bytes
MB9AF314L
MB9AF314M
MB9AF314N
MB9AF314LA
MB9AF314MA
MB9AF314NA
MB9AF114L
MB9AF114M
MB9AF114N
MB9AF114LA
MB9AF114MA
MB9AF114NA
MB9AF312L
MB9AF312M
MB9AF312N
MB9AF312LA
MB9AF312MA
MB9AF312NA
MB9AF112L
MB9AF112M
MB9AF112N
MB9AF112LA
MB9AF112MA
MB9AF112NA
MB9AF311L
MB9AF311M
MB9AF311N
MB9AF311LA
MB9AF311MA
MB9AF311NA
MB9AF111L
MB9AF111M
MB9AF111N
MB9AF111LA
MB9AF111MA
MB9AF111NA
MN706-00043-1v0-E, June 20, 2014
D. Product TYPE List
1.Product TYPE List
P E R I P H E R A L
Table 3 TYPE2 product list
Description in
this manual
1M byte
TYPE2
Flash memory size
768K bytes
512K bytes
MB9BFD18S
MB9BFD18T
MB9BFD17S
MB9BFD17T
MB9BFD16S
MB9BFD16T
MB9BF618S
MB9BF618T
MB9BF617S
MB9BF617T
MB9BF616S
MB9BF616T
MB9BF518S
MB9BF518T
MB9BF517S
MB9BF517T
MB9BF516S
MB9BF516T
MB9BF418S
MB9BF418T
MB9BF417S
MB9BF417T
MB9BF416S
MB9BF416T
MB9BF318S
MB9BF318T
MB9BF317S
MB9BF317T
MB9BF316S
MB9BF316T
MB9BF218S
MB9BF218T
MB9BF217S
MB9BF217T
MB9BF216S
MB9BF216T
MB9BF118S
MB9BF118T
MB9BF117S
MB9BF117T
MB9BF116S
MB9BF116T
Table 4 TYPE3 product list
Description in
this manual
TYPE3
Flash memory size
128K bytes
64K bytes
MB9AF132K
MB9AF132L
MB9AF131K
MB9AF131L
MB9AF132KA
MB9AF132LA
MB9AF131KA
MB9AF131LA
MB9AF132KB
MB9AF132LB
MB9AF131KB
MB9AF131LB
Table 5 TYPE4 product list
Description in
this manual
512K bytes
TYPE4
Flash memory size
384K bytes
256K bytes
128K bytes
MB9BF516N
MB9BF516R
MB9BF515N
MB9BF515R
MB9BF514N
MB9BF514R
MB9BF512N
MB9BF512R
MB9BF416N
MB9BF416R
MB9BF415N
MB9BF415R
MB9BF414N
MB9BF414R
MB9BF412N
MB9BF412R
MB9BF316N
MB9BF316R
MB9BF315N
MB9BF315R
MB9BF314N
MB9BF314R
MB9BF312N
MB9BF312R
MB9BF116N
MB9BF116R
MB9BF115N
MB9BF115R
MB9BF114N
MB9BF114R
MB9BF112N
MB9BF112R
Table 6 TYPE5 product list
Description in
this manual
TYPE5
Flash memory size
128 Kbytes
64 Kbytes
MB9AF312K
MB9AF311K
MB9AF112K
MB9AF111K
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
M A N U A L
177
D. Product TYPE List
1.Product TYPE List
P E R I P H E R A L
Table 7 TYPE6 product list
Description in
this manual
256 Kbytes
MB9AFB44L
TYPE6
MB9AFB44M
MB9AFB44N
MB9AFB44LA
MB9AFB44MA
MB9AFB44NA
MB9AFB42LA
MB9AFB42MA
MB9AFB42NA
64 Kbytes
MB9AFB41L
MB9AFB41M
MB9AFB41N
MB9AFB41LA
MB9AFB41MA
MB9AFB41NA
MB9AFB44LB
MB9AFB44MB
MB9AFB44NB
MB9AFB42LB
MB9AFB42MB
MB9AFB42NB
MB9AFB41LB
MB9AFB41MB
MB9AFB41NB
MB9AFA44L
MB9AFA44M
MB9AFA44N
MB9AFA44LA
MB9AFA44MA
MB9AFA44NA
MB9AFA42L
MB9AFA42M
MB9AFA42N
MB9AFA42LA
MB9AFA42MA
MB9AFA42NA
MB9AFA41L
MB9AFA41M
MB9AFA41N
MB9AFA41LA
MB9AFA41MA
MB9AFA41NA
MB9AFA44LB
MB9AFA44MB
MB9AFA44NB
MB9AFA42LB
MB9AFA42MB
MB9AFA42NB
MB9AFA41LB
MB9AFA41MB
MB9AFA41NB
MB9AF344L
MB9AF344M
MB9AF344N
MB9AF344LA
MB9AF344MA
MB9AF344NA
MB9AF342L
MB9AF342M
MB9AF342N
MB9AF342LA
MB9AF342MA
MB9AF342NA
MB9AF341L
MB9AF341M
MB9AF341N
MB9AF341LA
MB9AF341MA
MB9AF341NA
MB9AF344LB
MB9AF344MB
MB9AF344NB
MB9AF342LB
MB9AF342MB
MB9AF342NB
MB9AF341LB
MB9AF341MB
MB9AF341NB
MB9AF144L
MB9AF144M
MB9AF144N
MB9AF144LA
MB9AF144MA
MB9AF144NA
MB9AF142L
MB9AF142M
MB9AF142N
MB9AF142LA
MB9AF142MA
MB9AF142NA
MB9AF141L
MB9AF141M
MB9AF141N
MB9AF141LA
MB9AF141MA
MB9AF141NA
MB9AF144LB
MB9AF144MB
MB9AF144NB
MB9AF142LB
MB9AF142MB
MB9AF142NB
MB9AF141LB
MB9AF141MB
MB9AF141NB
Table 8 TYPE7 product list
Description in
this manual
TYPE7
178
CONFIDENTIAL
Flash memory size
128 Kbytes
M A N U A L
MB9AFB42L
MB9AFB42M
MB9AFB42N
Flash memory size
128 Kbytes
64 Kbytes
MB9AFA32L
MB9AFA32M
MB9AFA32N
MB9AF132M
MB9AF132N
MB9AFA31L
MB9AFA31M
MB9AFA31N
MB9AF131M
MB9AF131N
MB9AFAA2L
MB9AFAA2M
MB9AFAA2N
MB9AF1A2L
MB9AF1A2M
MB9AF1A2N
MB9AFAA1L
MB9AFAA1M
MB9AFAA1N
MB9AF1A1L
MB9AF1A1M
MB9AF1A1N
MN706-00043-1v0-E, June 20, 2014
D. Product TYPE List
1.Product TYPE List
P E R I P H E R A L
Table 9 TYPE8 product list
Description in
this manual
512 Kbytes
TYPE8
MB9AF156M
MB9AF156N
MB9AF156R
MB9AF156MA
MB9AF156NA
MB9AF156RA
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
M A N U A L
Flash memory size
384 Kbytes
256 Kbytes
MB9AF155M
MB9AF155N
MB9AF155R
MB9AF155MA
MB9AF155NA
MB9AF155RA
MB9AF154M
MB9AF154N
MB9AF154R
MB9AF154MA
MB9AF154NA
MB9AF154RA
179
D. Product TYPE List
1.Product TYPE List
P E R I P H E R A L
Table 10 TYPE9 product list
Description in
this manual
256 Kbytes
TYPE9
MB9BF524K
MB9BF524L
MB9BF524M
MB9BF324K
MB9BF324L
MB9BF324M
MB9BF124K
MB9BF124L
MB9BF124M
Flash memory size
128 Kbytes
64 Kbytes
MB9BF522K
MB9BF522L
MB9BF522M
MB9BF322K
MB9BF322L
MB9BF322M
MB9BF122K
MB9BF122L
MB9BF122M
MB9BF521K
MB9BF521L
MB9BF521M
MB9BF321K
MB9BF321L
MB9BF321M
MB9BF121K
MB9BF121L
MB9BF121M
Table 11 TYPE10 product list
Description in
this manual
TYPE10
Flash memory size
64 Kbytes
MB9BF121J
Table 12 TYPE11 product list
Description in
this manual
Flash memory size
64 Kbytes
TYPE11
MB9AF421K
MB9AF421L
MB9AF121K
MB9AF121L
Table 13 TYPE12 product list
Description in
this manual
1.5 Mbytes
TYPE12
180
CONFIDENTIAL
M A N U A L
Flash memory size
1 Mbytes
MB9BF529S
MB9BF529T
MB9BF528S
MB9BF528T
MB9BF429S
MB9BF429T
MB9BF428S
MB9BF428T
MB9BF329S
MB9BF329T
MB9BF328S
MB9BF328T
MB9BF129S
MB9BF129T
MB9BF128S
MB9BF128T
MN706-00043-1v0-E, June 20, 2014
P E R I P H E R A L
M A N U A L
MAJOR CHANGES
Page
Section
Revision 1.0
-
-
June 20, 2014, FM3_MN706-00043-1v0-E
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Change Results
Initial release
181
P E R I P H E R A L
182
CONFIDENTIAL
M A N U A L
MN706-00043-1v0-E, June 20, 2014
P E R I P H E R A L
M A N U A L
MN706-00043-1v0-E
Spansion Controller Manual
32-BIT MICROCONTROLLER
FM3 Family
Communication Part
PERIPHERAL MANUAL (MCU SIMULATOR VERSION)
June 2014 Rev. 1.0
Published:
Edited:
Spansion Inc.
Marketing Communications Dept.
June 20, 2014, FM3_MN706-00043-1v0-E
CONFIDENTIAL
183
P E R I P H E R A L
M A N U A L
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed,
developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high
safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical
damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport
control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is
intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third
party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices
have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety
design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and
other abnormal operating conditions. If any products described in this document represent goods or technologies subject to
certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration
Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be
required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion
product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without
notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy,
completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other
warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the
information in this document.
Copyright © 2014 Spansion. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM, ORNANDTM
and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries.
Other names used are for informational purposes only and may be trademarks of their respective owners.
184
CONFIDENTIAL
MN706-00043-1v0-E, June 20, 2014