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FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
CM71-10132-3E
32-BIT MICROCONTROLLER
FR60Lite
MB91345 Series
HARDWARE MANUAL
32-BIT MICROCONTROLLER
FR60Lite
MB91345 Series
HARDWARE MANUAL
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system
development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU SEMICONDUCTOR LIMITED
PREFACE
■ Purpose of This Document and Intended Reader
The MB91345 series is a microcontroller that has a 32-bit high performance RISC CPU as well as built-in I/
O resources and bus control mechanisms for embedded controller that requires high-performance and highspeed CPU processing. In order to support the extensive address space to which the 32-bit CPU accesses, it is
based on the external bus access, however, the MB91345 series has built-in RAM (for data) to increase the
speed at which the CPU executes instructions.
MB91345 series has the optimum specifications for the built-in applications that require a high-performance
CPU processing power, such as digital home appliances or AV equipments control.
MB91345 series is a FR family designed for higher-speed processing by integrating peripheral functions to a
compact package for the single chip.
This manual is intended for engineers who will develop products using the MB91345 series and describes the
functions and operations of the MB91345 series. Read this manual thoroughly.
For more information on instructions, see the "Instructions Manual".
Note: FR, which is an abbreviation of FUJITSU RISC controller, is a product of Fujitsu Semiconductor
Limited.
■ Trademarks
The company names and brand names herein are the trademarks or registered trademarks of their respective
owners.
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■ Organization of This Document
This manual contains the following 22 chapters and appendix.
CHAPTER 1 Overview
The FR families are lines of standard single-chip microcontrollers each based on a 32-bit highperformance RISC CPU, incorporating a variety of I/O resources and bus control features for embedded
control applications which require high performance/high-speed CPU processing.
CHAPTER 2 Handling of Device
This chapter describes precautions about handling of the MB91345 series.
CHAPTER 3 CPU and Control Section
In this chapter, basic matters such as architecture, specifications and instructions are explained for
knowing the function of FR family.
CHAPTER 4 I/O Port
This chapter describes the overview, the register configuration, and the function of I/O port.
CHAPTER 5 DMA Controller (DMAC)
This chapter describes an overview, the configuration and functions of registers, and operation of the
DMA controller (DMAC).
CHAPTER 6 Interrupt Controller
This chapter describes an overview, the configuration and functions of registers, and operation of the
interrupt controller.
CHAPTER 7 External Interrupt Controller
This chapter describes an overview, the configuration and functions of registers, and operation of the
external interrupt controller.
CHAPTER 8 REALOS-Related Hardware
REALOS-related hardware is used by real-time operating systems. Therefore, if REALOS is used, it
cannot be used in a user program.
CHAPTER 9 16-bit Reload Timer
This chapter describes register configuration and feature of 16-bit reload timer and its timer operation.
CHAPTER 10 16-bit Compare Timer
This chapter describes the overview, the configuration and functions of registers, and operation of the 16bit compare timer.
CHAPTER 11 32-bit Compare Timer
This chapter describes the overview, the configuration and functions of registers, and operation of the 32bit compare timer.
CHAPTER 12 16-bit PWC
This chapter describes the overview, the configuration and functions of registers, and operations of the
16-bit PWC.
CHAPTER 13 PPG Timer
This chapter describes the overview, the configuration and functions of registers, and operation of the
PPG timer.
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CHAPTER 14 Up/Down Counter
This chapter explains the overview, the configuration and functions of registers, and operations of the 8/
16-bit up/down counter.
CHAPTER 15 Serial Interface
This chapter describes the overview, the configuration and functions of registers, and operations of serial
interface.
CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
This chapter describes a UART function of the multi function serial interface functions, which is
supported on operation mode 2.
CHAPTER 17 I2C Interface
I2C interface, which is supported by the operation mode 4, among the multi function interfaces is
described.
CHAPTER 18 A/D Converter
This chapter describes an overview of the A/D converter, configuration/function of the register, and its
operation.
CHAPTER 19 Flash Memory
This chapter describes an overview of flash memory, configuration/function of the register, and its
operation. This product has an internal flash memory with a capacity of 512 Kbytes/IM, and the flash
memory enables mass erase of all the sectors, erase in sector units and writing from the CPU.
CHAPTER 20 Wild Register
This chapter describes functions and operations of the wild register.
CHAPTER 21 Arithmetic Macro for the Minimum, Maximum and Absolute Values
This chapter describes the overview, the configuration and functions of registers, and the operation of the
arithmetic macro for MIN/MAX/ABS.
CHAPTER 22 Serial Writing Connection
This chapter explains an example of a serial writing connection using the flash microcontroller
programmer (manufactured by Yokogawa Digital Computer Corporation).
APPENDIX
This section contains detailed information which is not included in the main text but required for
programming, such as the I/O map, interrupt vectors, pin status in the CPU state, and notes and
instruction lists that may be needed when using the little endian field.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU
SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you
develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such
use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of
the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's
intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any
infringement of the intellectual property rights or other rights of third parties which would result from the use of information
contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages
arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright© 2006-2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved.
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CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
CHAPTER 2
2.1
Overview ...................................................................................................... 1
Overview ............................................................................................................................................. 2
Block Diagram .................................................................................................................................... 5
External Dimensions ........................................................................................................................... 6
Pin Assignments ................................................................................................................................. 7
Pin Function List ................................................................................................................................. 8
I/O Circuit Type ................................................................................................................................. 18
Handling of Device .................................................................................... 23
Precautions on Handling of Device ................................................................................................... 24
CHAPTER 3
CPU and Control Section ......................................................................... 31
3.1
Memory Space ..................................................................................................................................
3.2
Internal Architecture ..........................................................................................................................
3.3
Overview of the Instructions .............................................................................................................
3.4
Special Registers ..............................................................................................................................
3.4.1
Program Status Register (PS) .....................................................................................................
3.5
General Registers .............................................................................................................................
3.6
Data Structure ...................................................................................................................................
3.7
Word Alignment ................................................................................................................................
3.8
Memory Map .....................................................................................................................................
3.9
Branch Instruction .............................................................................................................................
3.9.1
Operation of Branch Instruction with a Delay Slot .......................................................................
3.9.2
Operation of Branch Instruction without a Delay Slot ..................................................................
3.10 EIT (Exception, Interrupt, Trap) ........................................................................................................
3.10.1 Interrupt Level of EIT ...................................................................................................................
3.10.2 Interrupt Control Register (ICR) ...................................................................................................
3.10.3 System Stack Pointer (SSP) ........................................................................................................
3.10.4 Table Base Register (TBR) .........................................................................................................
3.10.5 Multi EIT Processing ....................................................................................................................
3.10.6 Operation of EIT ..........................................................................................................................
3.11 Operation Modes ..............................................................................................................................
3.12 Reset (Initialization of the Device) ....................................................................................................
3.12.1 Reset Level ..................................................................................................................................
3.12.2 Reset Factor ................................................................................................................................
3.12.3 Reset Sequence ..........................................................................................................................
3.12.4 Oscillation Stabilization Waiting Time ..........................................................................................
3.12.5 Reset Operation Mode ................................................................................................................
3.13 Clock Generation Control .................................................................................................................
3.13.1 PLL Control ..................................................................................................................................
3.13.2 Oscillation Stabilization Waiting/PLL Lock Waiting Time .............................................................
3.13.3 Clock Distribution .........................................................................................................................
3.13.4 Clock Dividing ..............................................................................................................................
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32
33
36
38
42
47
48
49
50
52
53
55
56
57
59
61
62
66
68
72
75
76
77
79
80
82
84
85
87
88
89
3.13.5 Block Diagram of Clock Generation Control Section ................................................................... 90
3.13.6 Registers of the Clock Generation Control Section ..................................................................... 91
3.13.7 Peripheral Circuits Provided for Clock Control Section ............................................................. 111
3.13.8 Smooth Activation and Stop of the Clock .................................................................................. 114
3.14 Device Status Control ..................................................................................................................... 119
3.14.1 Device Status and Various Transitions ...................................................................................... 121
3.14.2 Low Power Consumption Modes ............................................................................................... 124
CHAPTER 4
4.1
4.2
4.3
4.4
4.5
Overview of I/O Port .......................................................................................................................
Port Data Register (PDR0 to PDRE) ..............................................................................................
Data Direction Register (DDR0 to DDRE) ......................................................................................
Port Function Register (PFR0 to PFRE)/Extended Port Function Register
(EPFR0 to EPFRE) .........................................................................................................................
Pull-up Control Register (PCR0 to PCRE) ......................................................................................
CHAPTER 5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
I/O Port ..................................................................................................... 129
194
197
198
200
201
External Interrupt Controller .................................................................. 207
7.1
Overview of External Interrupt Controller ........................................................................................
7.2
External Interrupt Controller Registers ...........................................................................................
7.2.1
Enable Interrupts Register (ENIR0 to ENIR2) ...........................................................................
7.2.2
External Interrupt Factor Register (EIRR0 to EIRR2) ................................................................
7.2.3
External Interrupt Request Level Setting Register (ELVR0 to ELVR2) .....................................
7.3
Operation of External Interrupt Controller .......................................................................................
CHAPTER 8
158
161
176
178
179
181
190
192
Interrupt Controller ................................................................................. 193
6.1
Overview of Interrupt Controller ......................................................................................................
6.2
Interrupt Controller Register ...........................................................................................................
6.2.1
Interrupt Control Register (ICR) .................................................................................................
6.2.2
Hold Request Cancel Request Register (HRCL) .......................................................................
6.3
Operation of Interrupt Controller .....................................................................................................
CHAPTER 7
136
156
DMA Controller (DMAC) ......................................................................... 157
Overview of DMA Controller (DMAC) .............................................................................................
DMA Controller (DMAC) Register ...................................................................................................
Operation of DMA Controller ..........................................................................................................
Setting Transfer Request ................................................................................................................
Transfer Sequence .........................................................................................................................
General Aspects of DMA Transfer ..................................................................................................
Operation Flowchart .......................................................................................................................
Data Path ........................................................................................................................................
CHAPTER 6
130
134
135
208
209
210
211
212
214
REALOS-Related Hardware ................................................................... 217
8.1
Delayed Interrupt Module ...............................................................................................................
8.1.1
Overview of delayed interrupt module .......................................................................................
8.1.2
Register of Delayed Interrupt Module ........................................................................................
8.1.3
Operation of Delayed Interrupt Module .....................................................................................
8.2
Bit Search Module ..........................................................................................................................
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218
219
220
221
222
8.2.1
8.2.2
8.2.3
Overview of Bit Search Module ................................................................................................. 223
Register of Bit Search Module ................................................................................................... 224
Operation of Bit Search Module ................................................................................................ 226
CHAPTER 9
16-bit Reload Timer ................................................................................. 229
9.1
Overview of 16-bit Reload Timer ....................................................................................................
9.2
Register of 16-bit Reload Timer ......................................................................................................
9.2.1
Control Status Register (TMCSR) .............................................................................................
9.2.2
16-bit Timer Register (TMR) ......................................................................................................
9.2.3
16-bit Reload Register (TMRLR) ...............................................................................................
9.3
Operation of 16-bit Reload Timer ...................................................................................................
230
231
232
235
236
237
CHAPTER 10 16-bit Compare Timer ............................................................................. 241
10.1 Overview of 16-bit Compare Timer .................................................................................................
10.2 Block Diagram of 16-bit Compare Timer ........................................................................................
10.3 Compare Timer Registers ...............................................................................................................
10.3.1 Compare Clear Register (CPCLRB/CPCLR) .............................................................................
10.3.2 Timer Data Register (TCDTH/TCDTL) ......................................................................................
10.3.3 Timer Status Control Register (TCCSH/TCCSL) .......................................................................
10.3.4 Output Compare Register (OCCPH0 to OCCPH3/OCCPL0 to OCCPL3) .................................
10.3.5 Compare Control Register (OCSH0 to OCSH3/OCSL0 to OCSL3) ..........................................
10.3.6 Input Capture Data Register (IPCPH0 to IPCPH3/IPCPL0 to IPCPL3) .....................................
10.3.7 Input Capture Status Control Register (ICSH01, ICSL01/ICSH23, ICSL23) ............................
10.4 Interrupt by the Compare Timer ......................................................................................................
10.5 Compare Timer Operation ..............................................................................................................
10.5.1 Operation of the 16-bit Free-run Timer ......................................................................................
10.5.2 Operation of the 16-bit Output Compare ...................................................................................
10.5.3 Operation of the 16-bit Input Capture ........................................................................................
10.6 Notes on Using the Compare Timer ...............................................................................................
10.7 Program Example of the Compare Timer .......................................................................................
242
243
247
251
252
253
257
258
262
263
270
272
273
276
279
281
282
CHAPTER 11 32-bit Compare Timer ............................................................................. 287
11.1 Overview of 32-bit Compare Timer .................................................................................................
11.2 Block Diagram of 32-bit Compare Timer ........................................................................................
11.3 Compare Timer Registers ...............................................................................................................
11.3.1 Compare Clear Register (CPCLRB/CPCLR) .............................................................................
11.3.2 Timer Data Register (TCDT) .....................................................................................................
11.3.3 Timer Status Control Register of High-order Byte (TCCSH) .....................................................
11.3.4 Timer Status Control Register of Low-order Byte (TCCSL) .......................................................
11.3.5 Output Compare Register (OCCP4 to OCCP7) ........................................................................
11.3.6 Compare Control Register of High-order-side (OCSH45, OCSH67) .........................................
11.3.7 Compare Control Register of Low-order Byte (OCSL45, OCSL67) ..........................................
11.3.8 Input Capture Data Register (IPCP4 to IPCP7) .........................................................................
11.3.9 Input Capture Status Control (ICS67, ICS45) ............................................................................
11.4 Interrupt by the Compare Timer ......................................................................................................
11.5 Compare Timer Operation ..............................................................................................................
11.5.1 Operation of the 32-bit Free-run Timer ......................................................................................
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288
289
293
296
297
298
300
302
303
305
307
308
312
314
315
11.5.2 Operation of the 32-bit Output Compare ...................................................................................
11.5.3 Operation of the 32-bit Input Capture ........................................................................................
11.6 Notes on Using the Compare Timer ...............................................................................................
11.7 Program Example of the Compare Timer .......................................................................................
318
321
323
324
CHAPTER 12 16-bit PWC ............................................................................................... 329
12.1 Overview of the 16-bit PWC ...........................................................................................................
12.2 Register of the 16-bit PWC .............................................................................................................
12.2.1 PWC Control Status Register (PWCSR0) .................................................................................
12.2.2 PWC Data Buffer Register (PWCR0) ........................................................................................
12.2.3 Division Ratio Control Register (PDIVR0) .................................................................................
12.3 Operation of the 16-bit PWC ...........................................................................................................
12.4 Notes on Using in the 16-bit PWC ..................................................................................................
330
332
333
338
339
340
350
CHAPTER 13 PPG Timer ................................................................................................ 353
13.1
13.2
13.3
13.4
13.5
Overview of PPG Timer ..................................................................................................................
Block Diagrams of PPG Timer ........................................................................................................
PPG Timer Registers ......................................................................................................................
Operation Descriptions about PPG Timer ......................................................................................
Timing Generator to PPG Timer .....................................................................................................
354
358
362
369
378
CHAPTER 14 Up/Down Counter .................................................................................... 387
14.1 Overview of Up/Down Counter .......................................................................................................
14.2 Up/Down Counter Registers ...........................................................................................................
14.2.1 Up/Down Count Register (UDCR0 to UDCR3) ..........................................................................
14.2.2 Reload Compare Register (RCR) ..............................................................................................
14.2.3 Counter Status Register (CSR) .................................................................................................
14.2.4 Counter Control Register (CCR) ................................................................................................
14.3 Operations of Up/Down Counter .....................................................................................................
388
391
392
393
394
396
400
CHAPTER 15 Serial Interface ........................................................................................ 409
15.1 Overview of Serial Interface ............................................................................................................
15.2 Function of UART (Asynchronous Serial Interface) ........................................................................
15.3 Registers of UART (Asynchronous Serial Interface) ......................................................................
15.3.1 Serial Control Register (SCR0 to SCRA) ..................................................................................
15.3.2 Serial Mode Register (SMR0 to SMRA) ....................................................................................
15.3.3 Serial Status Register (SSR0 to SSRA) ....................................................................................
15.3.4 Extended Communication Control Register (ESCR0 to ESCRA) ..............................................
15.3.5 Receive Data Register (RDR0 to RDRA), Transmit Data Register (TDR0 to TDRA) ................
15.3.6 Baud Rate Generator Registers 0/1 (BGR00 to BGRA0, BGR01 to BGRA1) ...........................
15.3.7 FIFO Control Register 1 (FCR01, FCR11) ................................................................................
15.3.8 FIFO Control Register 0 (FCR00, FCR10) ................................................................................
15.3.9 FIFO Byte Register (FBYTE01, FBYTE02, FBYTE11, FBYTE12) ............................................
15.4 UART Interrupt ................................................................................................................................
15.4.1 Reception Interrupt Generation and Flag Set Timing ................................................................
15.4.2 Timing when the interrupt occurs and the flag
should be set during the use of the reception FIFO ..................................................................
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410
412
413
414
416
418
421
423
426
428
430
433
435
437
438
15.4.3
15.4.4
Transmit Interrupt Generation and Flag Set Timing ..................................................................
Timing when the Interrupt Occurs and the Flag Should be Set during the
Use of the Transmit FIFO ..........................................................................................................
15.5 Operation of UART .........................................................................................................................
15.6 Dedicated Baud Rate Generator ....................................................................................................
15.6.1 Baud Rate Setting .....................................................................................................................
15.7 Setting Procedure and Program Flow of Operation Mode 0 (In Asynchronous Normal Mode) ......
15.8 Setting Procedure and Program Flow of Operation Mode 1
(In Asynchronous Multiprocessor Mode) ........................................................................................
15.9 Notes on UART Mode .....................................................................................................................
440
441
442
447
448
452
454
458
CHAPTER 16 CSIO (Clock Synchronous Serial Interface) ......................................... 459
16.1 Overview of CSIO (Clock Synchronous Serial Interface) ...............................................................
16.2 CSIO (Clock Synchronous Serial Interface) Registers ...................................................................
16.2.1 Serial Control Register (SCR0 to SCRA) ..................................................................................
16.2.2 Serial Mode Register (SMR0 to SMRA) ....................................................................................
16.2.3 Serial Status Register (SSR0 to SSRA) ....................................................................................
16.2.4 Extended Communication Control Register (ESCR0 to ESCRA) ..............................................
16.2.5 Receive Data Register (RDR0 to RDRA), Transmit Data Register (TDR0 to TDRA) ................
16.2.6 Baud Rate Generator Registers 0/1 (BGR00 to BGRA0/BGR01 to BGRA1) ............................
16.2.7 FIFO Control Register 1 (FCR01, FCR11) ................................................................................
16.2.8 FIFO Control Register 0 (FCR00, FCR10) ................................................................................
16.2.9 FIFO Byte Register (FBYTE01, FBYTE02, FBYTE11, FBYTE12) ............................................
16.3 CSIO (Clock Synchronous Serial Interface) Interrupts ...................................................................
16.3.1 Reception Interrupt Generation and Flag Set Timing ................................................................
16.3.2 Timing when the Interrupt Occurs and the Flag Should be Set during the
Use of the Reception FIFO ........................................................................................................
16.3.3 Transmit Interrupt Generation and Flag Set Timing ..................................................................
16.3.4 Timing when the Interrupt Occurs and the Flag
Should be Set during the Use of the Transmit FIFO .................................................................
16.4 Operation of CSIO (Clock Synchronous Serial Interface) ...............................................................
16.5 Dedicated Baud Rate Generator ....................................................................................................
16.5.1 Baud Rate Setting .....................................................................................................................
16.6 Setting Procedure and Program Flow of CSIO (Clock Synchronous Serial Interface) ...................
16.7 Notes on CSIO Mode ......................................................................................................................
460
461
462
464
467
469
471
474
476
478
481
483
484
486
488
489
490
502
503
506
508
CHAPTER 17 I2C Interface ............................................................................................. 509
17.1 Overview of I2C Interface ................................................................................................................
17.2 I2C Interface Register .....................................................................................................................
17.2.1 I2C Bus Control Register (IBCR) ...............................................................................................
17.2.2 Serial Mode Register (SMR0 to SMRA) ....................................................................................
17.2.3 I2C Bus Status Register (IBSR) .................................................................................................
17.2.4 Serial Status Register (SSR0 to SSRA) ....................................................................................
17.2.5 Receive Data Register (RDR0 to RDRA), Transmit Data Register (TDR0 to TDRA) ................
17.2.6 7-bit Slave Address Mask Register (ISMK0 to ISMKA) .............................................................
17.2.7 7-bit Slave Address Register (ISBA) .........................................................................................
17.2.8 Baud Rate Generator Register 1/Baud Rate Generator Register 0
(BGR00 to BGRA0/BGR01 to BGRA1) .....................................................................................
ix
510
511
512
517
519
523
525
527
529
530
17.2.9 FIFO Control Register 1 (FCR01, FCR11) ................................................................................
17.2.10 FIFO Control Register 0 (FCR00, FCR10) ................................................................................
17.2.11 FIFO Byte Register (FBYTE01, FBYTE02, FBYTE11, FBYTE12) ............................................
17.3 I2C Interface Interruption ................................................................................................................
17.3.1 Operation of I2C Interface Communication ................................................................................
17.3.2 Master Mode ..............................................................................................................................
17.3.3 Slave Mode ................................................................................................................................
17.3.4 Bus Error ...................................................................................................................................
17.4 Dedicated Baud Rate Generator ....................................................................................................
17.4.1 Example of I2C Flowcharts ........................................................................................................
17.5 Notes on I2C Mode .........................................................................................................................
531
533
537
539
541
542
561
565
566
568
582
CHAPTER 18 A/D Converter .......................................................................................... 585
18.1 Overview of A/D Converter .............................................................................................................
18.2 Block Diagram of A/D Converter .....................................................................................................
18.3 Registers of A/D Converter .............................................................................................................
18.3.1 Analog Input Enable Register (ADERH) ....................................................................................
18.3.2 A/D Control Status Register (ADCS) .........................................................................................
18.3.3 Data Register (ADCR) ...............................................................................................................
18.3.4 Mirror Data Register (ADCR0M, ADCR1M) ...............................................................................
18.3.5 A/D Conversion Time Setting Register (ADCT) .........................................................................
18.3.6 A/D Start/End Channels Setting Registers (ADSCH, ADECH) .................................................
18.3.7 Trigger Control Register (ADTGS) ............................................................................................
18.4 Operation of A/D Converter ............................................................................................................
586
587
588
589
590
594
595
596
598
601
602
CHAPTER 19 FLASH MEMORY ..................................................................................... 605
19.1 Outline of Flash Memory .................................................................................................................
19.2 Flash Memory Registers .................................................................................................................
19.2.1 Flash Control Status Register (FLCR) .......................................................................................
19.2.2 Wait Register (FLWC) ...............................................................................................................
19.3 Flash Memory Access Modes .........................................................................................................
19.4 Automatic Algorithm of Flash Memory ............................................................................................
19.5 Execution Status of the Automatic Algorithm ..................................................................................
19.6 Data Writing to and Erasing from Flash Memory ............................................................................
19.6.1 Read/Reset Status ....................................................................................................................
19.6.2 Data Writing ...............................................................................................................................
19.6.3 Erasing Data (Chip Erase) .........................................................................................................
19.6.4 Erasing Data (Sector Erase) ......................................................................................................
19.6.5 Temporary Sector Erase Stop ...................................................................................................
19.6.6 Sector Erase Restart .................................................................................................................
19.7 Restrictions on Data Polling Flag (DQ7) and How to Avoid Erroneous Judgment .........................
19.8 Notes on Flash Memory Programming ...........................................................................................
606
610
611
613
614
616
620
624
625
626
628
629
631
632
633
636
CHAPTER 20 Wild Register ........................................................................................... 637
20.1 Wild Register Function .................................................................................................................... 638
20.1.1 Description of Registers for Wild Register Function .................................................................. 639
x
CHAPTER 21 Arithmetic Macro for the Minimum, Maximum
and Absolute Values ............................................................................... 643
21.1
21.2
21.3
21.4
Overview of Arithmetic Macro for MIN/MAX/ABS ...........................................................................
Register Configuration of Arithmetic Macro for MIN/MAX/ABS ......................................................
Operation Description of Arithmetic Macro for MIN/MAX/ABS .......................................................
Caution of Arithmetic Macro for MIN/MAX/ABS ..............................................................................
644
645
648
650
CHAPTER 22 Serial Writing Connection ...................................................................... 651
22.1
22.2
22.3
22.4
22.5
Basic Configuration of the Serial Writing ........................................................................................
Pins Used for Fujitsu-Standard Serial Onboard Writing .................................................................
Sample Connection of Serial Writing ..............................................................................................
System Configuration of Flash Microcontroller Programmer ..........................................................
Caution of Serial Writing .................................................................................................................
652
653
654
655
656
APPENDIX ......................................................................................................................... 657
APPENDIX A I/O Map ................................................................................................................................ 658
APPENDIX B Vector Table ......................................................................................................................... 672
APPENDIX C Pin Status List ...................................................................................................................... 675
INDEX................................................................................................................................... 679
xi
xii
Major changes in this edition
The vertical lines marked in the left side of the page show the changes.
Page
Section
Changes (For details, refer to main body.)
CHAPTER 5 DMA
191 Controller (DMAC)
Corrected "Figure 5.7-2 Operation Flowchart (Burst Transfer)".
5.7 Operation Flowchart
CHAPTER 8 REALOSRelated Hardware
224,
8.2 Bit Search Module
Corrected Figure 8.2-3, Figure 8.2-4, Figure 8.2-5, and Figure 8.2-6.
225
8.2.2 Register of Bit
Search Module
CHAPTER 9 16-bit
Reload Timer
237
9.3 Operation of 16-bit
Reload Timer
Corrected Figure 9.3-1.
238, 9.3 Operation of 16-bit
239 Reload Timer
Corrected Figure 9.3-4 and Figure 9.3-5.
CHAPTER 10 16-bit
Compare Timer
10.5 Compare Timer
276
Operation
10.5.2 Operation of the
16-bit Output Compare
Corrected "■ Operation of the 16-bit Output Compare (Inversion Mode)".
282
10.7 Program Example
of the Compare Timer
CHAPTER 13 PPG
355, Timer
356 13.1 Overview of PPG
Timer
362
13.3 PPG Timer
Registers
13.5 Timing Generator
to PPG Timer
384 ■ Overview of the
Timing Generator
Operation
391 CHAPTER 14 Up/
Down Counter
396 14.2 Up/Down Counter
Registers
409
CHAPTER 15 Serial
Interface
Corrected the main text in "● Details of processing".
(62.5ms  62.5ns)
Corrected Figure 13.1-2, Figure 13.1-3, and Figure 13.1-4.
Corrected "■ PPGCn Register (PPGn Operation Mode Control Register) n = 0 to F".
Corrected Figure 13.3-1.
Corrected "Figure 13.5-5 Timing for Operating/Stopping the 8-bit Counter".
(MONITER  MONI)
Corrected Figure 14.2-1.
Corrected Figure 14.2-5.
Added "15.9 Notes on UART Mode".
xiii
Page
Section
424
15.3 Registers of UART
(Asynchronous Serial
428 Interface)
Changes (For details, refer to main body.)
Corrected Figure 15.3-7.
Corrected Figure 15.3-9.
Initial value in Figure 15.3-9 was changed to 00-0000000000000B.
447
15.6 Dedicated Baud
Rate Generator
Corrected "Notes:".
(1500H  0000H)
15.9 Notes on UART
Mode
Added an item.
458
CHAPTER 16 CSIO
(Clock Synchronous
Serial Interface)
491
16.4 Operation of CSIO
(Clock Synchronous
Serial Interface)
508
16.7 Notes on CSIO
Mode
According to the errata notes, attachment 2 was added as 15.9.
Corrected "● Timing chart for Normal Transfer (I)" and others.
(SOUT  SOT)
Added an item.
Added "16.7 Notes on CSIO Mode".
2
509 CHAPTER 17 I C
Interface
Added "17.1 Overview of I2C Interface".
17.2 I2C Interface
Register
512 17.2.1
I2C Bus Control
Register (IBCR)
Corrected Figure 17.2-2.
17.2.6
7-bit Slave Address
528
Mask Register (ISMK0
to ISMKA)
Corrected Table 17.2-6.
17.2.7
529 7-bit Slave Address
Register (ISBA)
Corrected Figure 17.2-9.
531 17.2.9
FIFO Control Register 1
532 (FCR01, FCR11)
568
17.4 Dedicated Baud
to
Rate Generator
581
Corrected Figure 17.2-11.
CR01  FCR01
Corrected the title of Table 17.2-8.
Corrected Figure 17.4-1 to Figure 17.4-12
582 17.5 Notes on I2C Mode Added an item in "17.5 Notes on I2C Mode".
xiv
Page
Section
CHAPTER 18 A/D
Converter
18.1 Overview of A/D
586
Converter
■ Features of the A/D
Converter
588
18.3 Registers of A/D
Converter
590
"channel" was changed to "unit".
Corrected Figure 18.3-1.
Corrected "■ A/D Control Status Register (ADCS0, ADCS1)".
18.3.2 A/D Control
592 Status Register (ADCS)
598 18.3.6
A/D Start/End Channels
Setting Registers
599 (ADSCH, ADECH)
603, 18.4 Operation of A/D
604 Converter
605
Changes (For details, refer to main body.)
CHAPTER 19 FLASH
MEMORY
Corrected the term.
(A/D  A/D conversion)
Corrected "Summary" and "■ A/D Start/End Channel Setting Registers (ADSCH,
ADECH)".
Corrected the terms.
(UNIT)(Reserved)
"■ Setting Example of the Compare/Sampling time" was replaced by master copy.
Replaced by the latest version of CM71-00512-2.
606
Deleted "TM" in "*: Automatic algorithm: embedded algorithmTM".
19.1 Outline of Flash
608 Memory
Corrected Figure 19.1-2.
609
Corrected Figure 19.1-3.
611
19.2.1 Flash Control
Status Register (FLCR)
Corrected Figure 19.2-2.
629
19.6.4 Erasing Data
(Sector Erase)
Corrected "❍ How to Specify Sectors".
(erase code (30H)  erase code (3030H))
636
19.8 Notes on Flash
Memory Programming
Added an item.
637
CHAPTER 20 Wild
to
Register
642
Totally revised from "19.6 Wild Register" of the second edition.
CHAPTER 21
643 Arithmetic Macro for
to the Minimum,
650 Maximum and Absolute
Values
Corrected Chapter number.
(CHAPTER 20  CHAPTER 21)
651
CHAPTER 22 Serial
to
Writing Connection
656
Corrected Chapter number.
(CHAPTER 21  CHAPTER 22)
xv
Page
Section
662 APPENDIX
663 APPENDIX A I/O Map
Changes (For details, refer to main body.)
Corrected "Attached Table A-1 I/O Map".
Corrected "Attached Table A-1 I/O Map".
xvi
CHAPTER 1
Overview
The FR families are lines of standard single-chip
microcontrollers each based on a 32-bit highperformance RISC CPU, incorporating a variety of I/O
resources and bus control features for embedded
control applications which require high performance/
high-speed CPU processing.
1.1 Overview
1.2 Block Diagram
1.3 External Dimensions
1.4 Pin Assignments
1.5 Pin Function List
1.6 I/O Circuit Type
CM71-10132-3E
FUJITSU SEMICONDUCTOR LIMITED
1
CHAPTER 1 Overview
1.1 Overview
1.1
MB91345 Series
Overview
This section shows the features of MB91345 series.
■ Features
• 32-bit RISC, load/store architecture, and 5-stage pipeline
• Maximum operating frequency: 50 MHz [when PLL used at original oscillation of 12.5 MHz]
• 16-bit fixed length instruction (basic instruction); 1 instruction/cycle
• Memory-to-memory transfer instruction, bit manipulation instruction, barrel shift instruction, etc.
Instructions suiting for embedded applications.
• Function entry/exit instruction, multi-load/store instruction of register contents
Instructions supporting high-level languages
• Register interlock function
Facilitating description in assembler language
• Built-in multiplier/supported at instruction level
- Signed 32-bit multiplication: 5 cycles
- Signed 16-bit multiplication: 3 cycles
• Interrupt (PC and PS saved): 6 cycles, 16 priority levels
• Harvard architecture enabling concurrent program access and data access
• Instruction compatibility with other products of FR family
■ Internal Memory
Table 1.1-1 Internal Memory
Flash memory
D-bus RAM
F-bus RAM
MB91F345B
512 Kbytes
24 Kbytes
8 Kbytes
MB91F346B
1 Mbyte
24 Kbytes
8 Kbytes
■ DMAC (DMA Controller)
• Up to 5 channels can operate simultaneously
• Two transfer factors (internal peripheral and software)
• Addressing mode: 20-/24-bit full-address specification (increase, decrease, and fixed)
• Various transfer modes (burst transfer, step transfer, and block transfer)
• Selectable transfer data sizes of 8, 16, and 32 bits
■ Bit Search Module (REALOS is Used)
The position of the first change "1" / "0" is searched from MSB in 1 word.
■ Reload Timer: 3 channels (Including 1 channel for REALOS)
• 16-bit timer
• Any of 2-/8-/32-divided frequency can be selected for the internal clock.
2
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 1 Overview
1.1 Overview
MB91345 Series
■ Multi Function Serial Interface: Up to 11 channels
• Full duplex double buffer
• 2 channels out of 11 channels with 16-byte FIFO
• Any of asynchronous (Start-Stop synchronous) communication, clock synchronous communication, I2C
normal mode (Max 100 Kbps), and I2C high-speed mode (Max 400 Kbps) can be selected for
transmission mode.
• With parity and without parity
• Baud rate generator for each channel
• A full range of error detection functions is provided. (Parity, frame, and overrun)
• External clocks used as transfer clocks
• ch.0, ch.1, ch.2, and ch.10 is tolerant of 5V.
• SPI supported
■ Interrupt Controller: External Interrupts Up to 24 channels
• Interrupts from internal peripherals.
• Software-programmable priority levels (16 levels)
• Used as Wake up at stop
■ A/D Converter: 8 channels + 8 channels 2 unit
• 10-bit resolution
• Sequential conversion
Conversion time: min. 1.2 s (at 16 MHz)
• Conversion mode (one-shot conversion and scan conversion)
• Trigger (software and external)
■ PPG Timer: Up to 16 channels (at 8 bits)
• 8/16-bit PPG timer: 8 bits  16 channels or 16 bits  8 channels
• Any of 1-/4-/16-/64-divided frequency can be selected for the internal clock.
■ PWC Timer: 1 channel
16-bit up counter 1 channel (1 input)
■ Input Capture and Output Compare: Up to 8 channels (ch.0 to ch.3; 16-bit ICU, OCU,
ch.4 to ch.7; 32-bit ICU, OCU)
• 16-bit free-run counter  1 channel + 16-bit input capture  4 channels + 16-bit output compare  4
channels
• 32-bit free-run counter  1 channel + 32-bit input capture  4 channels + 32-bit output compare  4
channels
■ Other Interval Timer and Counter
• 8-/16-bit up down counter:
8-bit  4 channels or 16-bit  2 channels
• 16-bit time-base timer/watchdog timer
• MIN/MAX/ABS arithmetic functions
Performance of MIN, MAX and ABS arithmetical operations, and cumulative addition of the results
CM71-10132-3E
FUJITSU SEMICONDUCTOR LIMITED
3
CHAPTER 1 Overview
1.1 Overview
MB91345 Series
■ I/O Port: Max 71 ports
■ Other Features
• Oscillation circuit for clock source and PLL multiplier
• INIT Reset pin
• Watchdog timer and software resets
• Stop mode and sleep mode supported as low-power-consumption mode
• Gear function
• Built-in time-base timer
• Memory patch function
• Package: TQFP-100
• CMOS technology (0.18 m)
• Power supply voltage: 3.3 V ± 0.3 V (single power supply)
4
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 1 Overview
1.2 Block Diagram
MB91345 Series
1.2
Block Diagram
This section shows the block diagram of MB91345 series.
■ Block Diagram
Figure 1.2-1 Block Diagram
FR CPU
Core
32
Absolute value
operation macro
32
Bit search
RAM 24Kbytes
(data)
Bus
Converter
Flash 512K/1Mbytes
RAM 8Kbytes
X0 ,X1
MD2 to MD0
INIT
32
32
16
Adapter
Clock
control
PORT I/F
16
Interrupt
controller
INT23 to INT0
SIN10 to SIN0
SOT10 to SOT0
SCK10 to SCK0
AN7 to AN0
ADTRG0,
ADTRG0-2
AVRH ,AVCC
AVSS/AVRL
ADTRG1,
ADTRG1-2
AN15 to AN8
AIN3 to AIN0,
BIN3 to BIN0,
ZIN3 to ZIN0
PPGF to PPG0
CM71-10132-3E
DMAC
5 channels
16-bit Reload timer
3 channels
External interrupt
24 channels
PORT
TOT2 to TOT0,
TOT0-2, TOT1-2,
TOT2-2
TIN2 to TIN0
16-bit Free-run timer
FRCK0
11 channels
16-bit Input capture
4 channels
IC3 to IC0
10-bit A/D
8 channels x 1 unit
16-bit Output compare
4 channels
RT3 to RT0
10-bit A/D
8 channels x 1 unit
32-bit Free-run timer
FRCK1
8/16-bit up down
2 channels
32-bit Input capture
4 channels
IC7 to IC4
32-bit Output compare
4 channels
RT7 to RT4
UART (including 2channels
with internal FIFO)
8/16-bit PPG
16 channels
FUJITSU SEMICONDUCTOR LIMITED
5
CHAPTER 1 Overview
1.3 External Dimensions
1.3
MB91345 Series
External Dimensions
This section shows the external dimensions drawing of MB91345 series.
■ TQFP 100-pin
Figure 1.3-1 External Dimensions
100-pin plastic TQFP
(FPT-100P-M18)
100-pin plastic TQFP
(FPT-100P-M18)
Lead pitch
0.40 mm
Package width ×
package length
12.0 × 12.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.20 mm MAX
Weight
0.40g
Code(Reference)
P-TFQFP100-12 × 12-0.40
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
* 12.00±0.10(.472±.004)SQ
75
0.145±0.055
(.006±.002)
51
76
50
0.08(.003)
Details of "A" part
1.10±0.10
(.043±.004)
INDEX
0°~8°
26
100
0.10±0.05
(.004±.002)
(Stand off)
"A"
0.25(.010)
LEAD No.
1
0.40(.016)
C
0.60±0.15
(.024±.006)
25
0.18±0.05
(.007±.002)
0.07(.002)
M
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F100029S-c-3-6
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
6
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 1 Overview
1.4 Pin Assignments
MB91345 Series
1.4
Pin Assignments
This section shows the pin assignments drawing of MB91345 series.
■ TQFP 100-pin
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VCC
P23/SIN1
P22/SCK0/SCL0
P21/SOT0/SDA0
P20/SIN0
P17/ADTRG0
P16/SCK7/SCL7/ADTRG1
P15/SOT7/SDA7/TOT2
P14/SIN7/TIN2
P13/SCK6/SCL6/TOT1
P12/SOT6/SDA6/TIN1
P11/SIN6/TOT0
P10/SCK5/SCL5/TIN0
P07/SOT5/SDA5/INT15
P06/SIN5/INT14
P05/SCK4/SCL4/INT13
P04/SOT4/SDA4/INT12
P03/SIN4/INT11
P02/SCK3/SCL3/INT10
P01/SOT3/SDA3/INT9
P00/SIN3/INT8
P63/RT3
P62/RT2/ADTRG1-2
P61/RT1/PWC0/ADTRG0-2
VCC
Figure 1.4-1 TQFP 100-pin
VSS
C
P24/SOT1/SDA1
P25/SCK1/SCL1
P26/SIN2
P27/SOT2/SDA2
P30/SCK2/SCL2
P31/AIN0/TOT0-2
P32/BIN0/TOT1-2
P33/ZIN0/TOT2-2
P34/AIN2
P35/BIN2/IC4
P36/ZIN2/IC5
P37/FRCK1
P40/PPG9/INT16
P41/PPGB/INT17
P42/PPGD/INT18
P43/PPGF/INT19
P44/IC0/INT20
P45/IC1/INT21/SIN10
P46/IC2/INT22/SOT10/SDA10
P47/IC3/INT23/SCK10/SCL10
VSS
X1
X0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Top View
TOP View
(TQFP-100)
MB91420 Series
(LQFP-100)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
57
53
52
51
VSS
P60/RT0
P57/RT7
P56/RT6
P55/RT5
P54/RT4
P53/PPG7
P52/PPG5
P51/PPG3
P50/PPG1
MD2
MD1
MD0
INIT
TRST
IBREAK
ICS2
ICS1
ICS0
ICD3
ICD2
ICD1
ICD0
ICLK
VCC
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
PC2/IC7/SCK9/SCL9
PC1/IC6/SOT9/SDA9
PC0/FRCK0/SIN9
PE7/AN15/INT7/SCK8/SCL8
PE6/AN14/INT6/SOT8/SDA8
PE5/AN13/INT5/SIN8
PE4/AN12/INT4/PPGE
PE3/AN11/INT3/PPGC
PE2/AN10/INT2/PPGA
PE1/AN9/INT1/PPG8
PE0/AN8/INT0/PPG6
AVSS
AVRL
AVRH
AVCC
PD7/AN7/PPG4
PD6/AN6/PPG2
PD5/AN5/ZIN3/PPG0
PD4/AN4/BIN3
PD3/AN3/AIN3
PD2/AN2/ZIN1
PD1/AN1/BIN1
PD0/AN0/AIN1
VCC
Note: TOTx and TOTx-2 have same function. Also ADTRGx and ADTRGx-2 have
same function. Use either of the two depending on the combined resource.
CM71-10132-3E
FUJITSU SEMICONDUCTOR LIMITED
7
CHAPTER 1 Overview
1.5 Pin Function List
1.5
MB91345 Series
Pin Function List
This section shows the pin function list.
■ Pin Function List
Table 1.5-1 Pin Function List (1 / 9)
Pin No.
Pin name
Circuit
type
1
VSS
-
Power supply pin (0V)
2
C
-
Power stabilization capacitance pin
P24
3
SOT1
General-purpose I/O port
B
P25
SCK1
General-purpose I/O port. Enabled in single-chip mode.
B
P26
6
General-purpose I/O port. Enabled in single-chip mode.
B
SIN2
UART2 serial data input pin
P27
General-purpose I/O port. Enabled in single-chip mode.
SOT2
B
P30
SCK2
General-purpose I/O port. Enabled in single-chip mode.
B
P31
AIN0
General-purpose I/O port. Enabled in single-chip mode.
B
TOT0-2
BIN0
General-purpose I/O port. Enabled in single-chip mode.
B
TOT1-2
ZIN0
TOT2-2
8
Up down counter input pin
Reload timer output pin
P33
10
Up down counter input pin
Reload timer output pin
P32
9
UART2 clock I/O pin
I2C2 clock I/O pin.
SCL2
8
UART2 serial data output pin
I2C2 data I/O pin.
SDA2
7
UART1 clock I/O pin
I2C1 clock I/O pin.
SCL1
5
UART1 serial data output pin
I2C1 data I/O pin.
SDA1
4
Function
General-purpose I/O port. Enabled in single-chip mode.
B
Up down counter input pin
Reload timer output pin
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 1 Overview
1.5 Pin Function List
MB91345 Series
Table 1.5-1 Pin Function List (2 / 9)
Pin No.
Pin name
Circuit
type
P34
11
General-purpose I/O port. Enabled in single-chip mode.
B
AIN2
Up down counter input pin
P35
12
13
BIN2
General-purpose I/O port. Enabled in single-chip mode.
B
Input capture ICU 4 data sample input pin
P36
General-purpose I/O port. Enabled in single-chip mode.
ZIN2
B
General-purpose I/O port. Enabled in single-chip mode.
B
FRCK1
16-bit free-run timer input pin
P40
PPG9
General-purpose I/O port
B
INT16
PPGB
General-purpose I/O port
B
INT17
General-purpose I/O port
B
INT18
PPGF
General-purpose I/O port
B
INT19
IC0
General-purpose I/O port
B
INT20
Input capture ICU0 data sample input pin
External interrupt request 20 input pin
P45
General-purpose I/O port
IC1
20
PPG output pin
External interrupt request 19 input pin
P44
19
PPG output pin
External interrupt request 18 input pin
P43
18
PPG output pin
Input pin of external interrupt request 17
P42
PPGD
PPG output pin
Input pin of External interrupt request 16
P41
17
Up down counter input pin
Input capture ICU 5 data sample input pin
P37
14
16
Up down counter input pin
IC4
IC5
15
Function
Input capture ICU1 data sample input pin
B
INT21
External interrupt request 21 input pin
SIN10
UART10 serial data input pin
CM71-10132-3E
FUJITSU SEMICONDUCTOR LIMITED
9
CHAPTER 1 Overview
1.5 Pin Function List
MB91345 Series
Table 1.5-1 Pin Function List (3 / 9)
Pin No.
21
22
Pin name
Circuit
type
P46
General-purpose I/O port
IC2
Input capture ICU2 data sample input pin
INT22
B
External interrupt request 22 input pin
SOT10
UART10 serial data output pin
SDA10
I2C10 data I/O pin.
P47
General-purpose I/O port
IC3
Input capture ICU3 data sample input pin
INT23
B
External interrupt request 10 input pin
SCK10
UART10 clock I/O pin
SCL10
I2C10 clock I/O pin.
23
VSS
-
Power supply pin (0V)
24
X1
A
Main clock I/O
25
X0
A
Main clock input
26
VCC
-
Power supply pin (3.3V)
PD0
27
28
29
30
31
AN0
General-purpose I/O port
E
A/D converter analog input pin
AIN1
Up down counter input pin
PD1
General-purpose I/O port
AN1
E
A/D converter analog input pin
BIN1
Up down counter input pin
PD2
General-purpose I/O port
AN2
E
A/D converter analog input pin
ZIN1
Up down counter input pin
PD3
General-purpose I/O port
AN3
E
A/D converter analog input pin
AIN3
Up down counter input pin
PD4
General-purpose I/O port
AN4
BIN3
10
Function
E
A/D converter analog input pin
Up down counter input pin
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 1 Overview
1.5 Pin Function List
MB91345 Series
Table 1.5-1 Pin Function List (4 / 9)
Pin No.
Pin name
Circuit
type
PD5
General-purpose I/O port
AN5
32
33
34
Function
A/D converter analog input pin
E
ZIN3
Up down counter input pin
PPG0
PPG output pin
PD6
General-purpose I/O port
AN6
E
A/D converter analog input pin
PPG2
PPG output pin
PD7
General-purpose I/O port
AN7
E
PPG4
A/D converter analog input pin
PPG output pin
35
AVCC
-
Analog power supply input pin
36
AVRH
-
A/D converter standard voltage input pin
Be sure to turn on/off this power supply when potential of AVRH or more is
applied to AVCC.
37
AVRL
-
A/D converter standard low voltage input pin
38
AVSS
-
Analog VSS input pin
PE0
General-purpose I/O port
AN8
39
A/D converter analog input pin
E
INT0
External interrupt request 0 input pin
PPG6
PPG output pin
PE1
General-purpose I/O port
AN9
40
A/D converter analog input pin
E
INT1
External interrupt request 1 input pin
PPG8
PPG output pin
PE2
General-purpose I/O port
AN10
41
A/D converter analog input pin
E
INT2
External interrupt request 2 input pin
PPGA
PPG output pin
PE3
General-purpose I/O port
AN11
42
A/D converter analog input pin
E
INT3
External interrupt request 3 input pin
PPGC
PPG output pin
CM71-10132-3E
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CHAPTER 1 Overview
1.5 Pin Function List
MB91345 Series
Table 1.5-1 Pin Function List (5 / 9)
Pin No.
Pin name
Circuit
type
PE4
General-purpose I/O port
AN12
43
A/D converter analog input pin
E
INT4
External interrupt request 4 input pin
PPGE
PPG output pin
PE5
General-purpose I/O port
AN13
44
A/D converter analog input pin
E
INT5
External interrupt request 5 input pin
SIN8
UART8 serial data input pin
PE6
General-purpose I/O port
AN14
45
INT6
A/D converter analog input pin
E
UART8 serial data output pin
SDA8
I2C8 data I/O pin.
General-purpose I/O port
AN15
INT7
A/D converter analog input pin
E
UART8 clock I/O pin
SCL8
I2C8 clock I/O pin.
FRCK0
General-purpose I/O port
C
UART9 serial data input pin
PC1
General-purpose I/O port
SOT9
Input capture ICU6 data sample input pin
C
PC2
General-purpose I/O port
IC7
SCK9
Input capture ICU7 data sample input pin
C
UART9 clock I/O pin
I2C9 clock I/O pin.
SCL9
12
UART9 serial data output pin
I2C9 data I/O pin.
SDA9
49
16-bit free-run timer input pin
SIN9
IC6
48
External interrupt request 7 input pin
SCK8
PC0
47
External interrupt request 6 input pin
SOT8
PE7
46
Function
50
VSS
-
Power supply pin (0V)
51
VCC
-
Power supply pin (3.3V)
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CM71-10132-3E
CHAPTER 1 Overview
1.5 Pin Function List
MB91345 Series
Table 1.5-1 Pin Function List (6 / 9)
Pin No.
Pin name
Circuit
type
52
ICLK
H
Development tool clock pin
53
ICD0
K
Development tool data pin
54
ICD1
K
Development tool data pin
55
ICD2
K
Development tool data pin
56
ICD3
K
Development tool data pin
57
ICS0
J
Development tool status pin
58
ICS1
J
Development tool status pin
59
ICS2
J
Development tool status pin
60
IBREAK
I
Development tool break pin
61
TRST
G
Development tool reset pin
62
INIT
G
Reset pin
63
MD0
F
Operation mode designation input pin. Directly connect this pin to VCC or VSS.
64
MD1
F
Operation mode designation input pin. Directly connect this pin to VCC or VSS.
65
MD2
F
Operation mode designation input pin. Directly connect this pin to VCC or VSS.
P50
66
Function
General-purpose I/O port
C
PPG1
PPG output pin
P51
67
General-purpose I/O port
C
PPG3
PPG output pin
P52
68
General-purpose I/O port
C
PPG5
PPG output pin
P53
69
General-purpose I/O port
C
PPG7
PPG output pin
P54
70
General-purpose I/O port
C
RT4
Output compare OCU4 waveform output pin
P55
71
General-purpose I/O port
C
RT5
Output compare OCU5 waveform output pin
P56
72
General-purpose I/O port
D
RT6
Output compare OCU6 waveform output pin
P57
73
General-purpose I/O port
D
RT7
Output compare OCU7 waveform output pin
P60
74
General-purpose I/O port
C
RT0
CM71-10132-3E
Output compare OCU0 waveform output pin
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CHAPTER 1 Overview
1.5 Pin Function List
MB91345 Series
Table 1.5-1 Pin Function List (7 / 9)
Pin No.
Pin name
Circuit
type
75
VSS
-
Power supply pin (0V)
76
VCC
-
Power supply pin (3.3V)
P61
General-purpose I/O port
RT1
77
Output compare OCU1 waveform output pin
C
PWC0
PWC input pin
ADTRG0-2
A/D converter trigger input pin
P62
78
RT2
General-purpose I/O port
C
ADTRG1-2
General-purpose I/O port
C
RT3
Output compare OCU3 waveform output pin
P00
General-purpose I/O port
SIN3
C
INT8
General-purpose I/O port
SOT3
81
UART3 serial data output pin
C
SDA3
I2C3 data I/O pin.
INT9
External interrupt request 9 input pin
P02
General-purpose I/O port
SCK3
82
UART3 clock I/O pin
C
SCL3
I2C3 clock I/O pin.
INT10
External interrupt request 10 input pin
P03
SIN4
General-purpose I/O port
C
INT11
General-purpose I/O port
SOT4
84
UART4 serial data input pin
External interrupt request 11 input pin
P04
14
UART3 serial data input pin
External interrupt request 8 input pin
P01
83
Output compare OCU2 waveform output pin
A/D converter trigger input pin
P63
79
80
Function
UART4 serial data output pin
C
SDA4
I2C4 data I/O pin.
INT12
External interrupt request 12 input pin
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 1 Overview
1.5 Pin Function List
MB91345 Series
Table 1.5-1 Pin Function List (8 / 9)
Pin No.
Pin name
Circuit
type
P05
General-purpose I/O port
SCK4
85
UART4 clock I/O pin
C
SCL4
I2C4 clock I/O pin.
INT13
External interrupt request 13 input pin
P06
86
SIN5
General-purpose I/O port
C
INT14
General-purpose I/O port
SOT5
87
UART5 serial data output pin
C
SDA5
I2C5 data I/O pin.
INT15
External interrupt request 15 input pin
P10
General-purpose I/O port
SCK5
88
UART5 clock I/O pin
C
SCL5
I2C5 clock I/O pin.
TIN0
Reload timer 0 event input pin
P11
SIN6
General-purpose I/O port
C
UART6 serial data input pin
TOT0
Reload timer 0 output pin
P12
General-purpose I/O port
SOT6
90
UART6 serial data output pin
C
SDA6
I2C6 data I/O pin.
TIN1
Reload timer 1 event input pin
P13
General-purpose I/O port
SCK6
91
92
UART5 serial data input pin
External interrupt request 14 input pin
P07
89
Function
UART6 clock I/O pin
C
SCL6
I2C6 clock I/O pin.
TOT1
Reload timer 1 output pin
P14
General-purpose I/O port
SIN7
TIN2
CM71-10132-3E
C
UART7 serial data input pin
Reload timer 2 event input pin
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CHAPTER 1 Overview
1.5 Pin Function List
MB91345 Series
Table 1.5-1 Pin Function List (9 / 9)
Pin No.
Pin name
Circuit
type
P15
General-purpose I/O port
SOT7
93
UART7 serial data output pin
C
SDA7
I2C7 data I/O pin.
TOT2
Reload timer 2 output pin
P16
General-purpose I/O port
SCK7
94
UART7 clock I/O pin
C
SCL7
ADTRG1
General-purpose I/O port
C
ADTRG0
A/D converter trigger input pin
P20
96
General-purpose I/O port
C
SIN0
UART0 serial data input pin
P21
General-purpose I/O port
SOT0
C
P22
SCK0
General-purpose I/O port
C
P23
General-purpose I/O port
C
SIN1
100
16
UART0 clock I/O pin
I2C0 clock I/O pin.
SCL0
99
UART0 serial data output pin
I2C0 data I/O pin.
SDA0
98
I2C7 clock I/O pin.
A/D converter trigger input pin
P17
95
97
Function
VCC
UART1 serial data input pin
-
Power supply pin (3.3V)
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 1 Overview
1.5 Pin Function List
MB91345 Series
Table 1.5-2 I/O Pin Number
Package pin number
Pin name
TQFP100
CM71-10132-3E
X1
24
X0
25
INIT
62
P00 to P07
80 to 87
P10 to P17
88 to 95
P20 to P23
96 to 99
P24 to P27
3 to 6
P30 to P37
7 to 14
P40 to P47
15 to 22
P50 to P57
66 to 73
P60
74
P61 to P63
77 to 79
PC0 to PC2
47 to 49
PD0 to PD7
27 to 34
PE0 to PE7
39 to 46
AVCC
35
AVRH
36
AVRL
37
AVSS
38
MD0 to MD2
63 to 65
VCC
26, 51, 76, 100
VSS
1, 23, 50, 75
C
2
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CHAPTER 1 Overview
1.6 I/O Circuit Type
1.6
MB91345 Series
I/O Circuit Type
This section shows the I/O circuit type.
■ I/O Circuit Type
Table 1.6-1 I/O Circuit Type (1 / 4)
Classification
Circuit type
Remarks
X1
Clock input
A
Oscillation circuit
Internal resistor: approx. 1M.
X0
STANDBY CONTROL
B
P-ch
Open drain control
N-ch
Digital output
• CMOS level output
IOH = 4 mA
• With open drain output control
• CMOS level hysteresis input
VIH = 0.7  VCC
• Standby control provided
• Tolerant: 5V
Digital input
STANDBY CONTROL
P-ch
C
P-ch
Open drain control
N-ch
Digital output
• CMOS level output
IOH = 4 mA
• With open drain output control
• CMOS level hysteresis input
VIH = 0.8  VCC
• Standby control provided
• With pull-up resistance (33 k)
Digital input
STANDBY CONTROL
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CM71-10132-3E
CHAPTER 1 Overview
1.6 I/O Circuit Type
MB91345 Series
Table 1.6-1 I/O Circuit Type (2 / 4)
Classification
Circuit type
D
Remarks
P-ch
Digital output
N-ch
Digital output
• CMOS level output
IOH = 4 mA
• CMOS level hysteresis input
VIH = 0.8  VCC
Standby control provided
Without pull-up resistance
Digital input
STANDBY CONTROL
P-ch
P-ch
Open drain control
N-ch
Digital output
E
• CMOS level output
IOH = 4 mA
• With open drain output control
• CMOS level hysteresis input
VIH = 0.8  VCC
Standby control provided
• With analog input switch
• With pull-up resistance (33 k)
Analog input
CONTROL
Digital input
STANDBY CONTROL
• CMOS level input
• Standby control not provided
P-ch
F
N-ch
Digital input
CM71-10132-3E
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 1 Overview
1.6 I/O Circuit Type
MB91345 Series
Table 1.6-1 I/O Circuit Type (3 / 4)
Classification
Circuit type
Remarks
• CMOS hysteresis input
• With pull-up resistance
P-ch
G
P-ch
N-ch
Digital input
CMOS level output
P-ch
Digital output
N-ch
Digital output
H
• CMOS hysteresis input
• With pull-down resistance
• Standby control not provided
P-ch
I
N-ch
N-ch
Digital input
J
P-ch
Digital output
N-ch
Digital output
• CMOS level output
• CMOS level hysteresis input
• Standby control not provided
Digital input
20
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 1 Overview
1.6 I/O Circuit Type
MB91345 Series
Table 1.6-1 I/O Circuit Type (4 / 4)
Classification
Circuit type
P-ch
Digital output
N-ch
Digital output
K
N-ch
Remarks
•
•
•
•
CMOS level output
CMOS level hysteresis input
Standby control not provided
With pull-down resistance
Digital input
CM71-10132-3E
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CHAPTER 1 Overview
1.6 I/O Circuit Type
22
MB91345 Series
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 2
Handling of Device
This chapter describes precautions about handling of
the MB91345 series.
2.1 Precautions on Handling of Device
CM71-10132-3E
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CHAPTER 2 Handling of Device
2.1 Precautions on Handling of Device
2.1
MB91345 Series
Precautions on Handling of Device
This section explains how to prevent latch-up, how to design pin processing, how to
handle the circuit, and notes on input at power on.
■ To Prevent Latch-up
The latch-up phenomenon may occur in CMOS IC if a voltage higher than VCC or lower than VSS is
applied to the input pin or output pin, or if a voltage exceeding the rated voltage is applied between VCC
pin and VSS pin. If the latch-up phenomenon occurs, the power supply current can increase rapidly, leading
to thermal damage of elements. Thus, sufficient care must be taken to ensure that the maximum voltage
rating is not exceeded when using the device.
■ Handling of Unused Input Pin
If an unused input pin is left open, a malfunction may occur. Thus, perform pull-up or pull-down
processing.
■ Handling of Power Pin
If there are multiple VCC pins and VSS pins, potential to be the same is connected inside the device at the
designing device, in order to prevent malfunctioning such as latch-up. Be sure to connect all of them to the
power supply and ground externally for reducing unnecessary radiation, preventing malfunctioning of the
strobe signal due to the rising ground level, and obeying the total output current standard. In addition,
consideration should be given to connecting VCC pin/VSS pin of this device with as low an impecance as
possible from the current supply source. Also, we recommend connecting a ceramic capacitor of about 0.1
µF between VCC pin and VSS pin near this device as a bypass capacitor.
■ Handling of Crystal Oscillator Circuit
Noise in the vicinity of the X0 and X1 pins may cause a malfunction in the device. Design the printed
circuit board so that X0 pin, X1 pin, the crystal oscillator (or ceramic oscillator), and the bypass capacitor
are as close to the ground as possible. It is strongly recommended to design the printed circuit board
artwork so that the X0/X1 pins are surrounded by ground plane, because stable operation can be expected
with such an artwork. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal
and this device.
■ Handling of Mode Pins (MD0 to MD2)
These pins should be connected directly to VCC pin or VSS pin. To prevent the device from being
erroneously switched to test mode due to noise, design the printed circuit board such that the pattern length
between the mode pins and VCC pin or VSS pin is as short as possible to ensure that they are connected at
a low impedance.
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FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 2 Handling of Device
2.1 Precautions on Handling of Device
MB91345 Series
■ About Operation at Power-on
Be sure to execute setting initialized reset (INIT) with INIT pin immediately after power-on.
Also, in order to provide the oscillation stabilization wait time of the oscillator circuit and the stabilization
wait time of regulator immediately after power-on, the "L" level input to the INIT pin should be maintained
for the wait time required by the oscillator circuit to stabilize. (For INIT via the INIT pin, the oscillation
stabilization wait time setting is initialized to the minimum value.)
■ About Oscillation Input at Power On
When turning the power on, be sure that clock input is maintained until the device is released from the
oscillation stabilization wait state.
■ Note at Power On/Off
When the power is turned on, the output pin may be indeterminate until the internal power supply
stabilizes.
■ About Clocks
● Note when using external clock
In principle, when using external clock, supply a clock to the X0 pin and an opposite-phase clock signal to
the X1 pin simultaneously. However, the STOP mode (oscillation stop mode) must not be used in this case,
because the X1 pin stops with the "H" output in the STOP mode. When operating at 12.5 MHz or less, the
device can be used with the clock signal supplied only to the X0 pin.
The following Figure 2.1-1 and Figure 2.1-2, are two examples of how to use the external clock.
Figure 2.1-1 Example of Using an External Clock (Normal Case)
X0
X1
MB91345 series
[The STOP mode (oscillation stop mode) cannot be used.]
Figure 2.1-2 Example of Using an External Clock (Possible Only If 12.5 MHz or Below)
X0
OPEN
X1
MB91345 series
Note:
The X1 pin must be designed to have a delay within 15 ns, at 10 MHz, from the signal to the X0 pin.
CM71-10132-3E
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 2 Handling of Device
2.1 Precautions on Handling of Device
MB91345 Series
■ About C Pin
MB91345 series has a built-in regulator. A bus condenser of 4.7 µF or above should be connected to the C
pin for the regulator.
C
4.7 µF
VSS
■ About AVCC Pin
MB91345 series has a built-in A/D converter. A condenser of approximately 0.1 µF should be inserted
between the AVCC pin and AVSS pin.
AVCC
0.1 µF
AVSS
■ Handling of NC Pin and OPEN Pin
The NC and OPEN pins should always be open.
■ Note when not Using Emulator
If evaluation MCU on user system is executed without emulator, the input pins on evaluation MCU
connected to the emulator interface on the user system should be handled, as described in the following
table. Note that the switch circuit or other function may be required on user system when designing the
MCU.
Table 2.1-1 Pin Processing for Emulator Interface
Name of evaluation
MCU pin
TRST
Connect to the reset output circuit on user system.
INIT
Connect to the reset output circuit on user system.
Others
26
Pin processing
Should be open.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 2 Handling of Device
2.1 Precautions on Handling of Device
MB91345 Series
■ Handling of Emulator Pin (ICLK)
To control the reflected wave, ICLK pin for the emulator connection of this product should connect the
dumping resistance (About 56).
The resistance value is different depending on the substrate layout, so it should set to the proper value using
the substrate.
Figure 2.1-3 Connection Example of MB2198-01 Emulator
ICLK
MB91345 series
MB2198-10
emulator cable
MB2198-01
emulator
■ Restrictions
● Common in the series
• Clock control block
Take the oscillation stabilization wait time during "L" input to INIT.
• Bit search module
The data register for detecting 0 (BSD0), data register for detecting 1 (BSD1), and data register for
detecting a change point (BSDC) are only word-accessible.
• I/O port
Ports are accessed only in bytes.
• Low power consumption mode
- To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit8 in
TBCR, or time-base counter control register) and be sure to use the following sequence:
(ldi
#value_of_standby, r0)
(ldi
#_STCR, r12)
stb
r0, @r12
// set STOP/SLEEP bit
ldub
@r12, r0
// Must read STCR
ldub
@r12, r0
// after reading, go into standby mode
nop
// Must insert NOP *5
nop
nop
nop
nop
- When the monitor debugger is used, please ensure that:
CM71-10132-3E
•
Setting a break point within the instructions array shown above.
•
Performed a single-stepping for the instructions array shown above.
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 2 Handling of Device
2.1 Precautions on Handling of Device
MB91345 Series
• Notes on the PS register
As the PS register is processed by some instructions in advance, exception handling below may cause
the interrupt handling routine to break when the debugger is used or the display contents of flags in the
PS register to be updated. As the device is designed to carry out reprocessing correctly upon returning
from such an EIT event, it performs operations before and after the EIT as specified in either case.
1. When the instruction followed by a DIV0U/DIV0S instruction results in acceptance of a user
interrupt or NMI, step execution, or a break at a data event or emulator menu, the following
operations may be performed:
(1) The D0 and D1 flags are updated in advance.
(2) An EIT handling routine (user interrupt, NMI, or emulator) is executed.
(3) Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags
are updated to the same values as shown in (1).
2. If the OR CCR/ST ILM/MOV Ri, PS instructions are executed to enable interruptions when a user
interrupt or NMI trigger even has occurred, the following operations are performed.
(1) The PS register is updated in advance.
(2) An EIT handling routine (user interrupt, NMI, or emulator) is executed.
(3) Upon returning from the EIT, the instructions shonw above are executed and the PS register is
updated to the same value as shown in (1).
• About watchdog timer
MB91345 series has a built-in function called "watchdog timer". This function monitors a program to
perform the reset defer operation within a certain period of time. The watchdog timer resets the CPU if
the program runs out of controls and the reset defer operation is not executed. Thus, once enabled, the
watchdog timer will be up and running until it resets the CPU. However, with one exception, the
watchdog timer automatically defers a reset timing under the condition in which the CPU stops program
execution. Refer to "3.13.7 Peripheral Circuits Provided for Clock Control Section" for the exceptional
condition. If the system runs out of control and develops the above condition, a watchdog reset may not
be generated. In that case, please reset (INIT) from external INIT pin.
• Note on using the A/D converter
MB91345 series has a built-in A/D converter. The AVCC should not be supplied with higher voltage
than VCC.
• About software reset of synchronous mode
When using software reset of the synchronous mode, fill it with the following two conditions before
setting "0" to the SRST bit of STCR (standby control register) .
- Set the interrupt enable flag (I-Flag) to interrupt disable (I-Flag=0).
- NMI is not used.
● Unique to the evaluation chip
• Single-stepping of the RETI instruction
If an interrupt occurs frequently during single stepping, only the relevant processing routine is executed
repeatedly after single-stepping RETI. This will prevent the main routine and low-interrupt-level
programs from being executed. Do not single-step the RETI instruction for escape. Also, when the
debugging of the relevant interrupt routine becomes unnecessary, perform debugging with that interrupt
disabled.
• About operand break
Do not apply a data event break to access to the area containing the address of a stack pointer.
28
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 2 Handling of Device
2.1 Precautions on Handling of Device
MB91345 Series
• Execution in an unused area of Flash memory
Accidentally executing an instruction in an unused area of Flash memory (with data placed at FFFFH)
will prevent breaks from being accepted. To avoid this, the code event address mask function of the
debugger should be used to cause a break when accessing an instruction in an unused area.
• Interrupt handler for NMI request (tool)
To prevent the device from malfunctioning in case the factor flag to be set only in response to a break
request from the ICE is set accidentally, for example, by a noise to the DSU pin while the ICE is not
connected, add the following program to the interrupt handler. ICE can be used without problems when
this program is added.
Location to add the program:
Next interrupt handler
Interrupt factors: NMI request (tool)
Interrupt number: 13 (decimal), 0D (hexadecimal)
Offset: 3C8H
Address when TBR is the default: 000FFFC8H
Program to be added
STM (R0, R1)
LDI #0B00H, R0 ; 0B00H is the address of DSU break factor register
LDI #0, R1
STB R1, @R0 ; Clear the break factor register
LDM (R0, R1)
RETI
CM71-10132-3E
FUJITSU SEMICONDUCTOR LIMITED
29
CHAPTER 2 Handling of Device
2.1 Precautions on Handling of Device
30
FUJITSU SEMICONDUCTOR LIMITED
MB91345 Series
CM71-10132-3E
CHAPTER 3
CPU and Control Section
In this chapter, basic matters such as architecture,
specifications and instructions are explained for
knowing the function of FR family.
3.1 Memory Space
3.2 Internal Architecture
3.3 Overview of the Instructions
3.4 Special Registers
3.5 General Registers
3.6 Data Structure
3.7 Word Alignment
3.8 Memory Map
3.9 Branch Instruction
3.10 EIT (Exception, Interrupt, Trap)
3.11 Operation Modes
3.12 Reset (Initialization of the Device)
3.13 Clock Generation Control
3.14 Device Status Control
CM71-10132-3E
FUJITSU SEMICONDUCTOR LIMITED
31
CHAPTER 3 CPU and Control Section
3.1 Memory Space
3.1
MB91345 Series
Memory Space
The logical address space of FR family is 4G bytes (232 addresses) and CPU accesses
to it linearly.
■ Direct Addressing Area
The following area of the address space is used for I/O.
This area is called direct addressing area and you can directly specify the address of operand in the
instructions. As shown below, the direct addressing area differs by the size of the data to be accessed.
 byte data access
: 000H to 0FFH
 half word data access
: 000H to 1FFH
 word data access
: 000H to 3FFH
■ Memory Map
Figure 3.1-1 Memory Space
Single chip mode
0000 0000H
I/O
Direct addressing area
0000 0400H
da
I/O
Refer to I/O map
0001 0000H
Access prohibited
000 3 E000H
0004 0000H
000 4 6000H
000 5 0000H
Built-in
RAM 8Kbytes
(Data/instruction)
Built-in
RAM 24Kbytes
(Data)
Access prohibited
000 8 0000H
Built-in Flash*
512Kbytes
0010 0000H
0020_0000H
Access prohibited
FFFF FFFFH
*: The built-in flash area of MB91F346B is 1 Mbyte by 00080000H to 0017FFFFH
32
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 3 CPU and Control Section
3.2 Internal Architecture
MB91345 Series
3.2
Internal Architecture
FR family CPU is high performance core adopting RISC architecture and implementing
high-level function instructions for embedded applications.
■ Features of Internal Architecture
• Adopting RISC architecture
Basic instructions: One instruction per cycle
• 32-bit architecture
General purpose register: 32 bits × 16
• 4 Gbytes linear memory space
• On chip multiplier
- 32 bits × 32-bit multiplication: 5 cycles
- 16 bits × 16-bit multiplication: 3 cycles
• Enhanced interruption function
- High speed response: 6 cycles
- Multiple interruption support
- Level mask function: 16 levels
• Enhanced I/O operation instruction
- Memory-memory transfer instructions
- Bit processing instructions
• High code efficiency
Basic instruction word length: 16 bits
• Low power consumption
Sleep mode/stop mode
• Gear function
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CHAPTER 3 CPU and Control Section
3.2 Internal Architecture
MB91345 Series
■ Structure of Internal Architecture
The CPU of FR family adopts Harvard architecture structure which instruction bus and data bus are
independent. The 32-bit 16-bit bus converter is connected to 32-bit bus (F-bus), and realizes interface
between CPU and peripheral resources. Harvard Princeton bus converter is connected to both I-bus
and D-bus, and realizes interface between CPU and bus controller.
Figure 3.2-1 shows the structure of internal architecture.
Figure 3.2-1 Structure of Internal Architecture
FRex
D-bus
CPU
I-bus
32
I address
Harvard
32
External address
24
I data
D address
Princeton
bus
converter
32
Data
D data
RAM
External data
16
32
32-bit
Address
32
16-bit
Data
32
bus converter
16
R-bus
Peripheral resources
34
F-bus
Internal I/O
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Bus controller
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CHAPTER 3 CPU and Control Section
3.2 Internal Architecture
MB91345 Series
● CPU
The CPU is the one which compactly implements FR architecture of 32-bit RISC.
Five-stage instruction pipeline system is adopted for executing one instruction per cycle. The pipeline
consists of the stages shown below.
• Instruction Fetch (IF)
: Output instruction address and fetch instruction.
• Instruction Decode (ID) : Decode the fetched instruction. Read out register too.
• Execution (EX)
: Execute operation.
• Memory Access (MA)
: Load or store access to the memory.
• Write Back (WB)
: Write the operation results (or loaded memory data) to the register.
Figure 3.2-2 shows the configuration of instruction pipeline.
Figure 3.2-2 Instruction Pipeline
CLK
Instruction 1
WB
Instruction 2
MA
WB
Instruction 3
EX
MA
WB
Instruction 4
ID
EX
MA
WB
Instruction 5
IF
ID
EX
MA
WB
IF
ID
EX
MA
Instruction 6
WB
Instructions are not executed in random order. That means if instruction A enters in the pipeline before
instruction B, instruction A surely reaches write back stage before instruction B does.
Basically instruction is executed at the speed of one instruction per cycle. But multiple cycles are required
for the execution of load store instruction with memory wait, branch instruction without a delay slot and
multi cycle instruction. Execution speed slows down too in case the instructions’ supply is late.
● 32-bit 16-bit bus converter
The converter interfaces between F-bus accessed with 32-bit width and R-bus accessed with 16-bit width
and realizes data access from CPU to built-in peripheral circuits.
When there is a 32-bit width access from CPU to R-bus, the converter transforms it into two 16-bit width
accesses and accesses to R-bus. There is a restriction on access width in some built-in peripheral circuits.
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CHAPTER 3 CPU and Control Section
3.3 Overview of the Instructions
3.3
MB91345 Series
Overview of the Instructions
This section explains an overview of the instructions for FR family.
■ Overview of the Instructions
Adding to general RISC instruction system, FR family supports logical operation and bit handling
optimized for embedded applications and direct addressing instructions. As each instruction is 16-bit length
(some instructions are 32 or 48 bits), it has good memory usage efficiency.
The instruction set is categorized into the groups shown below.
• Arithmetic operation
• Load and store
• Branch
• Logical operation and bit handling
• Direct addressing
• Others
For the list of instruction set, refer to the "Appendix E Instruction List".
● Arithmetic Operation
In the arithmetic operation, there are standard arithmetic operation instruction (addition, subtraction,
comparing) and shift instruction (logical shift, arithmetic operation shift). In the addition instruction and
subtraction instruction, carried operation used for multi word length operation and operation that does not
change flag value which is useful for address calculation are possible.
Furthermore, there are 32-bit × 32-bit, 16-bit × 16-bit multiplication instruction and 32-bit / 32-bit step
division instruction. It also provides instantaneous transfer instruction which instantaneously sets value in
the register and inter-register transfer instruction.
All arithmetic operation instructions operate using general registers and multiply & divide register in the
CPU.
● Load and Store
Load and store are the instructions for reading and writing to external memory. They are also used for
reading and writing to peripheral circuits (I/O) on the chip.
Load and store have three kinds of access length as byte, half word and word. Adding to general register
indirect memory addressing, register indirect with displacement and register indirect with increment/
decrement memory addressing are also possible for some instructions.
● Branch
Branch group has the instructions of branch, call, interrupts and return.
There are branch instructions with a delay slot and branch instructions without a delay slot, and they are
optimized for their use. Details of the branch instructions are explained in the "3.9 Branch Instruction".
● Logical Operation and Bit Handling
Logical operation instructions can execute logical operation of AND, OR, EOR between general registers
or between general registers and memory (and I/O). And bit handling instructions can directly handle the
contents of memory (and I/O). Memory addressing is general register indirect addressing.
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CHAPTER 3 CPU and Control Section
3.3 Overview of the Instructions
● Direct Addressing
Direct addressing instructions are used for accessing between I/O and general registers or between I/O and
memory. Fast and high efficiency access can be accomplished by directly designating the I/O address in the
instructions rather than register indirect. Register indirect memory addressing with register increment/
decrement is possible for some instructions.
● Others
They are instructions for flag setting in the program status register (PS), stack operation, sign/zero
expansion and others. Function entrance/exit for high level language and register multi load/store
instructions are also provided.
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CHAPTER 3 CPU and Control Section
3.4 Special Registers
3.4
MB91345 Series
Special Registers
These registers are used for special purpose. Program counter (PC), program status
(PS), table base register (TBR), return pointer (RP), system stack pointer (SSP), user
stack pointer (USP) and multiply & divide register (MDH/MDL) are provided.
■ List of Special Registers
Each register consists of 32 bits.
Figure 3.4-1 shows the list of special registers.
Figure 3.4-1 List of Special Registers

ILM

SCR
CCR
Program counter
(PC)
Program status
(PS)
Table base register
(TBR)
Return pointer
(RP)
System stack pointer
(SSP)
User stack pointer
(USP)
Multiply & Divide register
(MDH)
(MDL)
■ Program Counter (PC)
The function of the program counter (PC) is described here. The program counter (PC) consists of 32 bits.
Figure 3.4-2 shows bit configuration of the program counter (PC).
Figure 3.4-2 Bit Configuration of the Program Counter (PC)
bit31
bit0
Initial value
XXXXXXXXH
The program counter indicates the executing instruction address. When updating PC with instruction
execution, bit0 is set to "0". Bit0 becomes "1", only when odd number address is specified as a branch
destination address.
Although in that case, bit0 is invalid and the instruction should be placed in the address that is multiple of
two.
Initial value by reset is indeterminate.
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CHAPTER 3 CPU and Control Section
3.4 Special Registers
MB91345 Series
■ Table Base Register (TBR)
The function of the table base register (TBR) is explained.
The table base register (TBR) consists of 32 bits.
Figure 3.4-3 shows the bit configuration of the table base register (TBR).
Figure 3.4-3 Bit Configuration of the Table Base Register (TBR)
bit31
bit0
Initial value
000FFC00H
The table base register holds the first address of the vector table which is used for EIT processing.
The initial value set by reset is "000FFC00H".
■ Return Pointer (RP)
The function of return pointer (RP) is explained.
The return pointer (RP) consists of 32 bits.
Figure 3.4-4 shows the bit configuration of the return pointer (RP).
Figure 3.4-4 Bit Configuration of the Return Pointer (RP)
bit31
bit0
Initial value
XXXXXXXXH
The return pointer holds the return address from subroutine.
The value of PC is transferred to this RP when CALL instruction is executed.
The contents of the RP is transferred to PC when RET instruction is executed.
The initial value set by reset is indeterminate.
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CHAPTER 3 CPU and Control Section
3.4 Special Registers
MB91345 Series
■ System Stack Pointer (SSP)
The function of the system stack pointer (SSP) is explained.
The system stack pointer (SSP) consists of 32 bits.
Figure 3.4-5 shows the bit configuration of the system stack pointer (SSP).
Figure 3.4-5 Bit Configuration of the System Stack Pointer (SSP)
bit31
bit0
Initial value
00000000H
SSP is a system stack pointer.
When S flag is "0", it works as R15.
SSP can be explicitly specified. It is also used as stack pointer which specifies the stack for saving PS and
PC when EIT occurs.
The initial value by reset is "00000000H".
■ User Stack Pointer (USP)
The function of the user stack pointer (USP) is explained.
The user stack pointer (USP) consists of 32 bits.
Figure 3.4-6 shows the bit configuration of the user stack pointer (USP).
Figure 3.4-6 Bit Configuration of the User Stack Pointer (USP)
bit31
bit0
Initial value
XXXXXXXXH
USP is a user stack pointer.
When S flag is "1", it works as R15.
USP can be explicitly specified.
The initial value set by reset is indeterminate.
It cannot be used in RETI instruction.
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CHAPTER 3 CPU and Control Section
3.4 Special Registers
MB91345 Series
■ Multiply & Divide Register (MDH/MDL)
The function of the Multiply & Divide register (MDH/MDL) is explained.
The Multiply & Divide register (MDH/MDL) consists of 32 bits.
Figure 3.4-7 shows bit configuration of the Multiply & Divide register (MDH/MDL).
Figure 3.4-7 Multiply & Divide Register (MDH/MDL)
bit31
bit0
MDH
MDL
Multiply & Divide register is used for multiplication and division operation and it consists of MDH and
MDL. Each consists of 32-bit length.
The initial value set by reset is indeterminate.
● Function at multiplication execution
In case of 32-bit × 32-bit multiplication, 64 bits executed results are stored in the Multiply & Divide
register arranged as shown below.
• MDH: upper 32 bits
• MDL: lower 32 bits
In case of 16-bit × 16-bit multiplication, executed results are stored in the Multiply & Divide register
arranged as shown below.
• MDH: indeterminate
• MDL: 32-bit results
● Function at division execution
When calculation starts, dividend is stored in MDL.
When division is done by execution of the instruction DIV0S/DIV0U, DIV1, DIV2, DIV3, DIV4S, the
results are stored in MDL and MDH as shown below.
• MDH: remainder
• MDL: quotient
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CHAPTER 3 CPU and Control Section
3.4 Special Registers
3.4.1
MB91345 Series
Program Status Register (PS)
Program Status Register (PS) is a register to hold program status and it is separated
into three parts of ILM, SCR and CCR. All undefined bits are reserved bits. When it is
read, "0" is always read out. Write is prohibited.
■ Program Status Register (PS)
● Program status register (PS)
The program status register (PS) consists of condition code register (CCR), system condition code register
(SCR) and interrupt level mask register (ILM).
Figure 3.4-8 shows register structure of the program status register.
Figure 3.4-8 Structure of the Program Status Register (PS)
bit31
bit20
bit16
bit10 bit8 bit7
ILM
SCR
bit0
CCR
● Condition code register (CCR)
Figure 3.4-9 shows the structure of the condition code register (CCR).
Figure 3.4-9 Structure of the Condition Code Register (CCR)
42
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value


S
I
N
Z
V
C
--00XXXXB
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3.4 Special Registers
MB91345 Series
The function of each bit is explained below.
[bit5] S: Stack flag
This bit specifies the stack pointer used as R15.
Table 3.4-1 shows the function of stack flag (S).
Table 3.4-1 Function of the Stack Flag (S)
S
Function
0
System stack pointer (SSP) is used as R15.
When EIT occurs, the flag becomes "0" automatically.
(But the value saved in the stack is the value before it is cleared.)
1
User stack pointer (USP) is used as R15.
This bit is cleared to "0" by reset.
Set "0" when RETI instruction is executed.
[bit4] I: Interrupt enable flag
This bit controls enable/disable of user interrupt request.
Table 3.4-2 shows the function of interrupt enable flag (I).
Table 3.4-2 Function of the Interrupt Enable Flag (I)
I
Function
0
Disable user interrupt.
When INT instruction is executed, it is cleared to "0".
(But the value saved in the stack is the value before it is cleared.)
1
Enable user interrupt.
Masking process of user interrupt request is controlled by the value held in ILM.
This bit is cleared to "0" by reset.
[bit3] N: Negative flag
This bit indicates the sign of integer expressed in two’s complement of executed results.
Table 3.4-3 shows the function of negative flag (N).
Table 3.4-3 Function of the Negative Flag (N)
N
Function
0
Indicates the executed result was positive value.
1
Indicates the executed result was negative value.
Initial state of this bit by reset is indeterminate.
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CHAPTER 3 CPU and Control Section
3.4 Special Registers
MB91345 Series
[bit2] Z: Zero flag
This bit indicates whether the executed result was "0" or not.
Table 3.4-4 shows the function of zero flag (Z).
Table 3.4-4 Function of the Zero Flag (Z)
Z
Function
0
Indicates that executed result was a value other than "0".
1
Indicates that executed result was "0".
Initial state of this bit by reset is indeterminate.
[bit1] V: Overflow flag
Assuming the operand used in the execution as an integer expressed in two’s complement, this bit
indicates whether overflow occurred or not in the executed results.
Table 3.4-5 shows the function of overflow flag (V).
Table 3.4-5 Function of the Overflow Flag (V)
V
Function
0
Shows overflow didn’t occur in the executed results.
1
Shows overflow occurred in the executed results.
Initial state of this bit by reset is indeterminate.
[bit0] C: Carry flag
This bit indicates whether carry or borrow from the MSB was occurred or not in the execution.
Table 3.4-6 shows the function of carry flag (C).
Table 3.4-6 Function of the Carry Flag (C)
C
Function
0
Shows neither carry nor borrow occurred.
1
Shows either carry or borrow occurred.
Initial state of this bit by reset is indeterminate.
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CHAPTER 3 CPU and Control Section
3.4 Special Registers
MB91345 Series
● System condition code register (SCR)
Figure 3.4-10 shows the structure of the system condition code register (SCR).
Figure 3.4-10 Structure of the System Condition Code Register (SCR)
bit10
bit9
bit8
Initial value
D1
D0
T
XX0B
The function of each bit for the system condition code register (SCR) is explained below.
[bit10, bit9] D1, D0: Flag for step division
These bits hold intermediate data during step division execution.
Do not change these bits during division execution.
In case other processing is done during step division execution, restarting of step division is assured by
save/restore of the value in the program status register (PS).
Initial state of this bit by reset is indeterminate.
These bits are set by DIV0S instruction execution referring dividend and divisor.
These bits are forcibly cleared by DIV0U instruction execution.
• DIV0S/DIV0U instructions and simultaneous acceptance of user interrupt and NMI
Do not execute a process in the EIT processing routine, expecting D0/D1 bit of PS register before
EIT branch.
• In case execution is halted by break or step just before DIV0S/DIV0U instructions, there is a case
that D0/D1 bits of PS register does not show correct values. But the executed result after resume is
correct.
[bit8] T: Step trace trap flag
This bit specifies whether enable or not step trace trap.
Table 3.4-7 shows the function of step trace trap flag (T).
Table 3.4-7 Function of the Step Trace Trap Flag (T)
T
Function
0
Step Trace Trap is ineffective
1
Step Trace Trap is effective
In case of this, both NMI for user and user interrupt are disabled.
This bit is initialized to "0" by reset.
The emulator uses the function of the step trace trap. When the emulator is using it, it cannot be used in
the user program.
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CHAPTER 3 CPU and Control Section
3.4 Special Registers
MB91345 Series
● Interrupt level mask register (ILM)
Figure 3.4-11 shows the structure of the interrupt level mask register (ILM).
Figure 3.4-11 Structure of the Interrupt Level Mask Register (ILM)
bit20
bit19
bit18
bit17
bit16
Initial value
ILM4
ILM3
ILM2
ILM1
ILM0
01111B
The interrupt level mask register (ILM) holds the value of interrupt level mask and the value held by the
ILM is used for level mask.
Among interrupt requests taken into CPU, only in case corresponding interrupt level is higher than the level
given by ILM, that interrupt request is accepted.
The strongest level value is 0 (00000B) and the weakest value is 31 (11111B).
There is a limitation that can be set by the program.
In case the original value is 16 to 31, the value that can be set as new value is 16 to 31. If an instruction to
set 0 to 15 is executed, then the value (specified value +16) is transferred.
In case the original value is 0 to 15, any value of 0 to 31 can be set.
This register is initialized to 15 (01111B) by reset.
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CHAPTER 3 CPU and Control Section
3.5 General Registers
MB91345 Series
3.5
General Registers
Registers R0-R15 are general registers. These registers are used as an accumulator and
a pointer for memory access in various operations.
■ General Register
Figure 3.5-1 shows the structure of the general registers.
Figure 3.5-1 Structure of the General Registers
32 bits
Initial value
R0
XXXX XXXX
H
H
R1
R12
R13
R14
AC
FP
XXXX XXXX
R15
SP
0000 0000
H
The registers R0-R15 are general registers. These registers are used as an accumulator and a pointer for
memory access in various operations. Among 16 registers, the registers shown below are assumed to be
used for special purposes, and some instructions are enhanced.
• R13: Virtual accumulator (AC)
• R14: Frame pointer (FP)
• R15: Stack pointer (SP)
Initial values of R0-R14 by reset are indeterminate. R15 becomes "00000000H" (value of SSP).
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CHAPTER 3 CPU and Control Section
3.6 Data Structure
3.6
MB91345 Series
Data Structure
In FR family, there are two kinds of data allocation as shown below.
• Bit ordering
• Byte ordering
■ Bit Ordering
FR family adopts little endian for bit ordering.
Figure 3.6-1 shows bit configuration of bit ordering.
Figure 3.6-1 Bit Configuration of the Bit Ordering
bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSB
LSB
■ Byte Ordering
FR family adopts big endian for byte ordering.
Figure 3.6-2 shows the structure of byte ordering.
Figure 3.6-2 Structure of Byte Ordering
Memory
MSB
bit31
bit23
bit15
bit7
LSB
bit0
10101010 11001100 11111111 00010001
bit
7
n Address
bit
0
10101010
(n+1) Address 11001100
(n+2) Address 11111111
(n+3) Address 00010001
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CHAPTER 3 CPU and Control Section
3.7 Word Alignment
MB91345 Series
3.7
Word Alignment
As instructions or data access by byte, allocated address is different depending on the
instruction length and data width.
■ Program Access
Program of FR family is necessary to be allocated in the address that is multiple of two.
The bit0 of the program counter (PC) is set to "0" when PC is updated with execution of instructions.
"1" is set only when odd number address is specified as a branch destination address.
Even in that case, bit0 is invalid and the instructions have to be allocated in the address that is multiple of
two.
There is no odd number exception.
■ Data Access
In FR family, when data access is performed, forcible alignment is done to the address depending on its
width as shown below.
• Word access
: Address is multiple of "4". (The least two significant bits are forcibly set to "00".)
• Half word access
: Address is multiple of "2". (The least significant bit is forcibly set to "0".)
• Byte access
: --
In word data access and half word data access, some bits are forcibly set to "0" for executed result of
effective address. For example, in case of addressing mode of @(R13,Ri), the register before addition (even
though the least significant bit is "1") is used for calculation as it is, and lower bit of addition result is
masked. This means the register before addition is not masked.
[Example] LD@(R13,R2),R0
R13
00002222H
R2
00000003H
+)
Addition result
Address terminal
CM71-10132-3E
00002225H
The least two significant bits are forcibly masked
00002224H
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CHAPTER 3 CPU and Control Section
3.8 Memory Map
3.8
MB91345 Series
Memory Map
Memory map of FR family is shown.
■ Memory Map
The Memory address space is 32 bits linear.
Figure 3.8-1 shows the memory map.
Figure 3.8-1 Memory Map
0000 0000H
Byte data
0000 0100H
Half word data
Direct addressing area
0000 0200H
Word data
0000 0400H
000F FC00H
Vector table
000F FFFFH
Initial area
FFFF FFFFH
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CHAPTER 3 CPU and Control Section
3.8 Memory Map
MB91345 Series
■ Memory Map of Single-chip Mode
Figure 3.8-2 Memory Map of Single-chip Mode
Single-chip mode
0000 0000H
I/O
Direct-addressing area
0000 0400H
da
I/O
0001 0000H
See the I/O map.
Access
prohibited
0003 E000H
0004 0000H
0004 6000H
0005 0000H
8 Kbytes
Internal RAM
(Data/Instruction)
24 Kbytes
Internal RAM
(Data)
Access
prohibited
0008 0000H
512 Kbytes*
Internal Flash
0010 0000H
0020_0000H
Access
prohibited
FFFF FFFFH
*: The built-in flash memory area of MB91F346B is 1 Mbyte by 00080000H to 0017FFFFH
● Direct addressing area
In the address space, the areas shown below are the area for I/O. This area can directly specify operand
address in the instructions by direct addressing.
The size of address area which can specify direct address is different depending on the data length.
• Byte data (8 bits)
: 000H to 0FFH
• Half word data (16 bits)
: 000H to 1FFH
• Word data (32 bits)
: 000H to 3FFH
● Vector table initial area
The area "000FFC00H" to "000FFFFFH" is the initial area of EIT vector table.
The vector table which is used at EIT processing can be allocated in any address by rewriting TBR, but it is
allocated in this address by reset initialization.
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CHAPTER 3 CPU and Control Section
3.9 Branch Instruction
3.9
MB91345 Series
Branch Instruction
FR family can specify operation with a delay slot and operation without a delay slot to
branch instruction.
■ Branch Instruction with a Delay Slot
The instructions expressed as shown below accomplish branch operation with a delay slot.
52
JMP:D @Ri
CALL:D label12
CALL:D @Ri
RET:D
BRA:D label9
BNO:D label9
BEQ:D label9
BNE:D label9
BC:D
label9
BNC:D label9
BN:D
BP:D
BV:D
label9
BNV:D label9
BLT:D label9
BGE:D label9
BLE:D label9
BGT:D label9
BLS:D label9
BHI:D label9
label9
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CHAPTER 3 CPU and Control Section
3.9 Branch Instruction
MB91345 Series
3.9.1 Operation of Branch Instruction with a Delay Slot
In the operation with a delay slot, before executing the instruction of branch
destination, it executes the instruction which is located just after (called "a delay slot")
the branch instruction, and then it branches to the branch destination.
■ Operation of Branch Instruction with a Delay Slot
As instruction with a delay slot is executed before branch operation, apparent execution speed becomes one
cycle. On the other hand, when effective instruction cannot be put into a delay slot, NOP instruction has to
be placed.
[Example]
;
Instruction line
ADD
R1, R2 ;
BRA:D
LABEL
MOV
R2, R3 ; A delay slot …… Executed before branch.
; Branch destination

LABEL : ST
R3, @R4 ; Branch destination
In case of conditional branch instruction, the instruction located in the delay slot is executed regardless of
the condition is met or not.
In the delay branch instructions, though the execution order of some instruction appears to be inverted, it is
only for updating operation of PC, and other operations (such as updating and referring of registers) are
executed in the order described.
Example is shown below.
● JMP:D @Ri / CALL:D @Ri instruction
The Ri referred by JMP:D @Ri / CALL:D @Ri instruction is not affected even if the instruction in a delay
slot updates the Ri.
[Example]
LDI:32
#Label, R0
JMP:D
@R0
LDI:8
#0,
; Branch to Label
R0
; Does not affect on the branch destination address.

● RET:D instruction
RP referred by RET:D instruction is not affected even if the instruction in a delay slot updates RP.
[Example]
; Branch to the address indicated by RP which was set
RET:D
; before.
MOV
R8,
RP
; Does not affect on return operation.

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CHAPTER 3 CPU and Control Section
3.9 Branch Instruction
MB91345 Series
● Bcc:D rel instruction
The flag referred by Bcc:D rel instruction is not affected by a delay slot instruction.
[Example]
R0
; Flag change
ADD
#1,
BC:D
Overflow
; Branch by the execution result of above instruction
ANDCCR
#0
; This flag update is not referred by the above branch
; instruction

● CALL:D instruction
When RP is referred by the instruction in a delay slot of CALL:D instruction, the contents updated by
CALL:D instruction is read out.
[Example]
CALL:D
Label
MOV
RP,
; Update RP and branch
R0
; RP of execution result for above CALL:D is transferred.

■ Restrictions on Branch Instructions with a Delay Slot
● Instructions that can be located in a delay slot
Only the instructions that satisfy the condition shown below can be executed in a delay slot.
• 1 cycle instruction
• Not branch instruction
• The instruction that does not affect on the operation even when the order is changed.
"One cycle instruction" is the instruction, either "1", "a", "b", "c" or "d" is described in the cycle column
of the instruction list.
● Step trace trap
Step trace trap does not occur between the execution of branch instruction with a delay slot and the delay
slot.
● Interrupt/NMI
Interrupt/NMI is not accepted between the execution of branch instruction with a delay slot and the delay
slot.
● Undefined instruction exception
In case undefined instruction exists in a delay slot, undefined instruction exception does not occur. In this
situation, undefined instruction works as NOP instruction.
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CHAPTER 3 CPU and Control Section
3.9 Branch Instruction
MB91345 Series
3.9.2
Operation of Branch Instruction without a Delay Slot
In the operation of branch instruction without a delay slot, it is adamantly executed in
the order of the instructions. The instruction just next to it is never executed before
branch.
■ Branch Instruction without a Delay Slot
The instructions expressed as shown below do the operation of branch instruction without a delay slot.
JMP @Ri
CALL label12
CALL @Ri
RET
BRA label9
BNO
label9
BEQ
label9
BNE label9
BC
label9
BNC
label9
BN
label9
BP
BV
label9
BNV
label9
BLT
label9
BGE label9
BLE label9
BGT
label9
BLS
label9
BHI label9
label9
■ Operation of Branch Instruction without a Delay Slot
In the operation of branch instruction without a delay slot, it is adamantly executed in the order of the
instructions. The instruction just next to it is never executed before branch.
[Example]
;
List of commands
ADD
R1, R2 ;
BRA
LABEL
MOV
R2, R3 ; Not executed
; Branch instruction (without a delay slot)

LABEL:
ST
R3, @R4 ; Branch destination
The number of execution cycle for branch instruction without a delay slot is 2 cycles when it branches and
1 cycle when it does not branch.
Compared to the branch instruction with a delay slot in which NOP is explicitly written as it is not possible
to place adequate instructions in it, instruction code efficiency can be improved.
By selecting the operation with a delay slot in case that effective instruction can be placed in a delay slot
and in other case by selecting the operation without a delay slot, you can accomplish both execution speed
and code efficiency.
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CHAPTER 3 CPU and Control Section
3.10 EIT (Exception, Interrupt, Trap)
3.10
MB91345 Series
EIT (Exception, Interrupt, Trap)
EIT is the generic term of Exception, Interrupt and Trap and when events occur during
the relevant program execution, it executes other program by interrupting the execution
of the program.
■ EIT (Exception, Interrupt, Trap)
Exception: The exception is the event that occurs relating to the executing context. Execution restarts from
the instruction that arouses the exception.
Interrupt: The interrupt is the event that occurs irrelevantly with the executing context. The factors of
event are hardware.
Trap:
Trap is the event that occurs relating to the executing context. There are instructions like a
system call that are specified by the program. Execution restarts from the next instruction of the
instruction that arouses the trap.
■ Feature
• Interrupt supports multi interrupts
• Interrupt has level mask function (User can use 15 levels.)
• Trap instruction (INT)
• EIT for emulator activation (hardware /software)
■ EIT Factors
Followings are EIT factors.
• Reset
• User interrupt (internal resource, external resource)
• NMI
• Delayed interrupt
• Undefined instruction exception
• Trap instruction (INT)
• Trap instruction (INTE)
• Step trace trap
• Co-processor non existence trap
• Co-processor error trap
■ Return from EIT
RETI instruction is used for returning from EIT.
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CHAPTER 3 CPU and Control Section
3.10 EIT (Exception, Interrupt, Trap)
MB91345 Series
3.10.1
Interrupt Level of EIT
The interrupt levels are 0 to 31, and controlled with 5 bits.
■ Interrupt Level of EIT
Table 3.10-1 shows the EIT interrupt level.
Table 3.10-1 Interrupt Level of EIT
Level
Interrupt cause
Binary
Decimal
00000


00011
0


3
(System reserved)


(System reserved)
00100
4
INTE command
Step trace trap
00101


01110
5


14
(System reserved)


(System reserved)
01111
15
NMI (for user)
10000
10001


11110
11111
16
17


30
31
Interrupt
Interrupt


Interrupt
—
Note
In case the original value of ILM is between 16
and 31, the value in this range cannot be set to
ILM by the program.
When setting ILM, user interrupt is disabled.
When setting ICR, interrupt is disabled.
The levels 16 to 31 are operable.
Undefined instruction exception, co-processor non existence trap, co-processor error trap and INT
instruction are not affected by the interrupt level. And they do not change the ILM.
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CHAPTER 3 CPU and Control Section
3.10 EIT (Exception, Interrupt, Trap)
MB91345 Series
■ I Flag
This flag specifies interrupt enable/disable. The bit4 of CCR in the program status register (PS) is assigned
for it.
Table 3.10-2 shows the function of I flag.
Table 3.10-2 Function of I Flag
I
Function
0
Interrupt disabled
This is cleared to "0" when INT instruction is executed.
But the value saved to stack is the value before cleared.
1
Interrupt enabled
The processing of interrupt request mask is controlled by the value held by ILM.
■ Interrupt Level Mask Register (ILM)
This is the program status register (PS) (bit20 to bit16) that holds interrupt level mask value.
In the interrupt request input to CPU, the interrupt request is accepted only in case that the relevant
interrupt level is stronger than the level indicated by interrupt level mask register (ILM).
The strongest level value is 0 (00000B) and the weakest is 31 (11111B).
There is a limitation in the value to be set by the program. In case the original value is between 16 and 31,
the value between 16 and 31 can be set as a new value. If the instruction of setting the values 0 to 15 is
executed, the value (specified value +16) is transferred.
In case the original value is between 0 and 15, any value between 0 and 31 can be set.
Note:
For setting, use the instruction ST ILM.
■ Level Mask for Interrupt/NMI
When NMI and interrupt request occur, the interrupt level of interrupt factor (see Table 3.10-1) is
compared with the level mask value held in the ILM. And it is masked when the following condition is met
and the request is not accepted.
Interrupt level of interrupt factor Level mask value
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CHAPTER 3 CPU and Control Section
3.10 EIT (Exception, Interrupt, Trap)
MB91345 Series
3.10.2
Interrupt Control Register (ICR)
The interrupt control register (ICR) is a register set in the interrupt controller and sets
the level for each request of interrupt. The ICR is prepared corresponding to each
interrupt request input. The ICR is mapped in the I/O space and it is accessed through a
bus by CPU.
■ Bit Configuration of the Interrupt Control Register (ICR)
Figure 3.10-1 shows the bit configuration of the interrupt control register (ICR).
Figure 3.10-1 Bit Configuration of the Interrupt Control Register (ICR)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000440H
to
00046FH



ICR4
ICR3
ICR2
ICR1
ICR0
---11111B



R
R/W
R/W
R/W
R/W
R/W : Readable/writable
R : Read only
The function of each bit for the interrupt control register (ICR) is shown below.
[bit4] ICR4
This bit is always "1".
[bit3 to bit0] ICR3 to ICR0
These bits are the lower four bits of interrupt level for corresponding interrupt factor. Reading and
writing are enabled.
The ICR can set the value in the range of 16 to 31 with bit4.
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CHAPTER 3 CPU and Control Section
3.10 EIT (Exception, Interrupt, Trap)
MB91345 Series
■ Mapping of the Interrupt Control Register (ICR)
Table 3.10-3 shows the relation between interrupt factors, the interrupt control register and the interrupt
vector.
Table 3.10-3 Interrupt Factors, Interrupt Control Register and Interrupt Vector
Corresponding interrupt vector
Interrupt
factor
Interrupt control register
Number
Address
Hexadecimal
Decimal
IRQ00
ICR00
00000440H
10H
16
TBR + 3BCH
IRQ01
ICR01
00000441H
11H
17
TBR + 3B8H
IRQ02
ICR02
00000442H
12H
18
TBR + 3B4H












IRQ45
ICR45
0000046DH
3DH
61
TBR + 308H
IRQ46
ICR46
0000046EH
3EH
62
TBR + 304H
IRQ47
ICR47
0000046FH
3FH
63
TBR + 300H
TBR initial value: "000F FC00H"
Refer to "CHAPTER 6 Interrupt Controller" for details.
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CHAPTER 3 CPU and Control Section
3.10 EIT (Exception, Interrupt, Trap)
MB91345 Series
3.10.3
System Stack Pointer (SSP)
The System Stack Pointer (SSP) is used for EIT acceptance and used as a pointer that
indicates the stack for data save/restore during return operation.
■ System Stack Pointer (SSP)
The system stack pointer (SSP) consists of 32 bits.
Figure 3.10-2 shows bit configuration of the system stack pointer (SSP).
Figure 3.10-2 Bit Configuration of the System Stack Pointer (SSP)
bit31
bit0
Initial value
00000000H
When processing EIT, 8 is subtracted from the contents, and when resuming the operation from EIT by the
execution of RETI instruction "8" is added.
By reset, the initial value of SSP is "00000000H".
The SSP works as a general register R15 when S flag in the CCR is "0".
■ Interrupt Stack
In the area indicated by SSP, the value of PC and PS are saved/restored. After interruption, PC is stored in
the address indicated by the SSP and PS is stored in the address (SSP+4).
Figure 3.10-3 shows the interrupt stack.
Figure 3.10-3 Interrupt Stack
[Example]
SSP
[Before interrupt]
80000000H
[After interrupt]
SSP
7FFFFFF8H
Memory
80000000H
7FFFFFFCH
7FFFFFF8H
CM71-10132-3E
80000000H
7FFFFFFCH
7FFFFFF8H
FUJITSU SEMICONDUCTOR LIMITED
PS
PC
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CHAPTER 3 CPU and Control Section
3.10 EIT (Exception, Interrupt, Trap)
3.10.4
MB91345 Series
Table Base Register (TBR)
Table base register (TBR) is a register that indicates the head address of the vector
table for EIT.
■ Table Base Register (TBR)
The table base register (TBR) consists of 32 bits.
Figure 3.10-4 shows bit configuration of the table base register (TBR).
Figure 3.10-4 Bit Configuration of the Table Base Register (TBR)
bit31
bit0
Initial value
000FFC00H
The address that predetermined offset value for TBR and EIT factors is added becomes the vector address.
By reset, the initial value of TBR is "000FFC00H".
■ EIT Vector Table
The 1 Kbyte area from the address which is indicated by TBR becomes the vector area for EIT.
The size per vector is four bytes and the relation between vector number and vector address is expressed
below.
vctadr = TBR + vctofs
= TBR + (3FCH - 4 vct)
vctadr : Vector address
vctofs : Vector offset
vct
: Vector number
The lower two bits of the added results are always treated as "00B".
The area "000FFC00H" to "000FFFFFH" is the initial area of the vector table by reset.
Special function is assigned to some of the vectors.
Table 3.10-4 shows the vector table on the architecture.
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3.10 EIT (Exception, Interrupt, Trap)
MB91345 Series
Table 3.10-4 Vector Table (1 / 3)
Interrupt Factor
Interrupt
Number
Interrupt
Level
Offset
TBR Default
Address
Reset *1
0
00

3FCH
000FFFFCH
Mode vector *1
1
01

3F8H
000FFFF8H
System reserved
2
02

3F4H
000FFFF4H
System reserved
3
03

3F0H
000FFFF0H
System reserved
4
04

3ECH
000FFFECH
System reserved
5
05

3E8H
000FFFE8H
System reserved
6
06

3E4H
000FFFE4H
Co-processor non existence trap
7
07

3E0H
000FFFE0H
Co-processor error trap
8
08

3DCH
000FFFDCH
INTE instruction
9
09

3D8H
000FFFD8H
System reserved
10
0A

3D4H
000FFFD4H
System reserved
11
0B

3D0H
000FFFD0H
Step trace trap
12
0C

3CCH
000FFFCCH
NMI request (tool)
13
0D

3C8H
000FFFC8H
Undefined instruction exception
14
0E

3C4H
000FFFC4H
NMI request
15
0F
15(FH) fixed
3C0H
000FFFC0H
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
Reload timer 0
24
18
ICR08
39CH
000FFF9CH
Reload timer 1
25
19
ICR09
398H
000FFF98H
Reload timer 2
26
1A
ICR10
394H
000FFF94H
Maskable factor *2
27
1B
ICR11
390H
000FFF90H
Maskable factor *2
28
1C
ICR12
38CH
000FFF8CH
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CHAPTER 3 CPU and Control Section
3.10 EIT (Exception, Interrupt, Trap)
MB91345 Series
Table 3.10-4 Vector Table (2 / 3)
Interrupt Factor
64
Interrupt
Number
Interrupt
Level
Offset
TBR Default
Address
Maskable factor *2
29
1D
ICR13
388H
000FFF88H
Maskable factor *2
30
1E
ICR14
384H
000FFF84H
Maskable factor *2
31
1F
ICR15
380H
000FFF80H
Maskable factor *2
32
20
ICR16
37CH
000FFF7CH
Maskable factor *2
33
21
ICR17
378H
000FFF78H
Maskable factor *2
34
22
ICR18
374H
000FFF74H
Maskable factor *2
35
23
ICR19
370H
000FFF70H
Maskable factor *2
36
24
ICR20
36CH
000FFF6CH
Maskable factor *2
37
25
ICR21
368H
000FFF68H
Maskable factor *2
38
26
ICR22
364H
000FFF64H
Maskable factor *2
39
27
ICR23
360H
000FFF60H
Maskable factor *2
40
28
ICR24
35CH
000FFF5CH
Maskable factor *2
41
29
ICR25
358H
000FFF58H
Maskable factor *2
42
2A
ICR26
354H
000FFF54H
Maskable factor *2
43
2B
ICR27
350H
000FFF50H
Maskable factor *2
44
2C
ICR28
34CH
000FFF4CH
Maskable factor *2
45
2D
ICR29
348H
000FFF48H
Maskable factor *2
46
2E
ICR30
344H
000FFF44H
Time-base timer overflow
47
2F
ICR31
340H
000FFF40H
Maskable factor *2
48
30
ICR32
33CH
000FFF3CH
Maskable factor *2
49
31
ICR33
338H
000FFF38H
Maskable factor *2
50
32
ICR34
334H
000FFF34H
Maskable factor *2
51
33
ICR35
330H
000FFF30H
Maskable factor *2
52
34
ICR36
32CH
000FFF2CH
Maskable factor *2
53
35
ICR37
328H
000FFF28H
Maskable factor *2
54
36
ICR38
324H
000FFF24H
Maskable factor *2
55
37
ICR39
320H
000FFF20H
Maskable factor *2
56
38
ICR40
31CH
000FFF1CH
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CM71-10132-3E
CHAPTER 3 CPU and Control Section
3.10 EIT (Exception, Interrupt, Trap)
MB91345 Series
Table 3.10-4 Vector Table (3 / 3)
Interrupt Factor
Interrupt
Number
Interrupt
Level
Offset
TBR Default
Address
Maskable factor *2
57
39
ICR41
318H
000FFF18H
Maskable factor *2
58
3A
ICR42
314H
000FFF14H
Maskable factor *2
59
3B
ICR43
310H
000FFF10H
Maskable factor *2
60
3C
ICR44
30CH
000FFF0CH
Maskable factor *2
61
3D
ICR45
308H
000FFF08H
Maskable factor *2
62
3E
ICR46
304H
000FFF04H
Delayed interrupt factor bit
63
3F
ICR47
300H
000FFF00H
System reserved (use in REALOS)
64
40

2FCH
000FFEFCH
System reserved (use in REALOS)
65
41

2F8H
000FFEF8H
System reserved
66
42

2F4H
000FFEF4H
System reserved
67
43

2F0H
000FFEF0H
System reserved
68
44

2ECH
000FFEECH
System reserved
69
45

2E8H
000FFEE8H
System reserved
70
46

2E4H
000FFEE4H
System reserved
71
47

2E0H
000FFEE0H
System reserved
72
48

2DCH
000FFEDCH
System reserved
73
49

2D8H
000FFED8H
System reserved
74
4A

2D4H
000FFED4H
System reserved
75
4B

2D0H
000FFED0H
System reserved
76
4C

2CCH
000FFECCH
System reserved
77
4D

2C8H
000FFEC8H
System reserved
78
4E

2C4H
000FFEC4H
System reserved
79
4F

2C0H
000FFEC0H
Use in INT instruction
80
to
255
50
to
FF

2BCH
to
000H
000FFEBCH
to
000FFC00H
*1: Although the value of TBR is changed, reset vector and mode vector use the fixed address "000FFFFCH"
and "000FFFF8H".
*2: The maskable factors are defined for each product. Refer to "APPENDIX B Vector Table" for the vector
table of MB91345 series.
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CHAPTER 3 CPU and Control Section
3.10 EIT (Exception, Interrupt, Trap)
3.10.5
MB91345 Series
Multi EIT Processing
In case plural EIT factors occur simultaneously, the CPU repeats the operation, such as
selecting one EIT and accepting it, and after executing the EIT sequence, detecting the
EIT factors again. During EIT factors detection, when there is not any acceptable EIT
factor, the handler instruction of EIT factor which was accepted at the last is executed.
Therefore, when plural EIT factors occur simultaneously, the execution order of handler
for each factor is decided by the two factors shown below.
• Priority of acceptance for EIT factors
• How to mask other factors when accepting the one
■ Priority of EIT Factor Acceptance
The priority of acceptance for EIT factors is the order for selecting the factor of executing EIT sequence,
such as saving PS and PC and updating PC and (when it is necessary) doing mask processing.
The handler of factor accepted at first is not necessarily executed at first.
Table 3.10-5 shows the priority of EIT factor acceptance and mask for other factors.
Table 3.10-5 Priority of EIT Factor Acceptance and Mask for Other Factors
Priority of
acceptance
Factor
Mask for other factors
1
Reset
Other factors are discarded.
2
Undefined instruction exception
Cancel
3
INT instruction
I flag=0
4
Co-processor non existence trap
Co-processor error trap
5
User interrupt
ILM=Level of the factor accepted
6
NMI (for user)
ILM=15
7
(INTE instruction)
ILM=4 *
8
NMI (for emulator)
ILM=4
9
Step trace trap
ILM=4
10
INTE instruction
ILM=4
—
* : Only when INTE instruction and NMI for emulator occur simultaneously, the priority
becomes "6".
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CHAPTER 3 CPU and Control Section
3.10 EIT (Exception, Interrupt, Trap)
MB91345 Series
By considering the mask processing for other factors after accepting the EIT factors, the execution order of
each handler for EIT factor which occurred simultaneously becomes as shown below.
Table 3.10-6 shows the execution order of each handler for EIT factor.
Table 3.10-6 Execution Order of Each Handler for EIT Factor
Execution order of
handler
Factor
1
Reset *1
2
Undefined instruction exception
3
Step trace trap *2
4
INTE instruction *2
5
NMI (for user)
6
INT instruction
7
User interrupt
8
Co-processor non existence trap, co-processor error trap
* 1: Other factors are discarded.
* 2: When INTE instruction is executed by step, only EIT of step trace trap occurs. The
factor caused by INTE is neglected.
Figure 3.10-5 shows an example of the multi EIT processing.
Figure 3.10-5 Multi EIT Processing
Main routine
Handler of NMI
Handler of
INT instruction
Priority
(1) Execute first
(High) NMI occurrence
(Low) INT instruction execution
(2) Execute next
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CHAPTER 3 CPU and Control Section
3.10 EIT (Exception, Interrupt, Trap)
3.10.6
MB91345 Series
Operation of EIT
The operation of EIT is explained.
■ Operation of EIT
In the explanation below, "PC" of transferred source means the instruction address that detected each EIT
factor. And "next instruction address" means, the instruction that detected EIT is as shown below.
• In case LDI is 32: PC+6
• In case LDI is 20 and COPOP, COPLD, COPST, COPSV: PC+4
• In case other instruction: PC+2
■ Operation of User Interrupt/NMI
When an interrupt request of user interrupt or NMI for user occurs, enable or disable of request acceptance
is judged in the order shown below.
[Judging enable or disable for interrupt request acceptance]
1) Comparing the interrupt levels of request that occurred simultaneously, the one holding the strongest
level (the least number) is selected.
As the level used for comparing, for maskable interrupt the value held in the corresponding ICR is used,
and for NMI the predetermined constant is used.
2) When plural interrupt requests of same level occur simultaneously, the interrupt request that has the
youngest interrupt number is selected.
3) In case "interrupt level  level mask value", interrupt request is masked and not accepted. In case
"interrupt level < level mask value", goes to 4).
4) In case the selected interrupt request is maskable interrupt, if I flag is "0", then the interrupt request is
masked and not accepted. If I flag is "1", then goes to 5). In case the selected interrupt request is NMI,
regardless of the value for I flag, goes to 5).
5) When the above conditions are met, interrupt request is accepted at the interval of the instruction
processing.
In case the user interrupt/NMI request is accepted when EIT request is detected, using the interrupt number
corresponding to the accepted interrupt request, the CPU operates as shown below. ( ) indicates the address
that register specifies.
[Operation]
1) (TBR + vector offset of accepted interrupt request)  TMP
2) SSP - 4
 SSP
3) PS
 (SSP)
4) SSP - 4
 SSP
5) Address of next instruction
 (SSP)
6) Interrupt level of accepted request
 ILM
7) "0"
 S flag
8) TMP
 PC
After finishing the interrupt sequence, before executing the head instruction of the handler, new EIT
detection is done. If acceptable EIT has occurred at this point of time, the CPU makes the transition to EIT
processing sequence.
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CHAPTER 3 CPU and Control Section
3.10 EIT (Exception, Interrupt, Trap)
MB91345 Series
During user interrupt or NMI factor is occurring, if each of the instruction OR CCR, ST ILM and MOV Ri,
PS is executed to enable the interrupt, there is a case that the above instruction is executed twice before and
after the interrupt handler. But there is no problem in the operation since it just sets the same value twice in
the register of the CPU.
In the EIT processing routine, do not execute the processing expecting the contents of PS register before
EIT branch.
■ Operation of INT Instruction
INT #u8 instruction operates as shown below.
It branches to the interrupt handler of vector specified by u8.
[Operation]
1) (TBR+3FCH - 4u8)
 TMP
2) SSP- 4
 SSP
3) PS
 (SSP)
4) SSP- 4
 SSP
5) PC+2
 (SSP)
6) "0"
 I flag
7) "0"
 S flag
8) TMP
 PC
■ Operation of INTE Instruction
INTE instruction operates as shown below.
It branches to the interrupt handler of vector number #9.
[Operation]
1) (TBR+3D8H)
 TMP
2) SSP- 4
 SSP
3) PS
 (SSP)
4) SSP- 4
 SSP
5) PC+2
 (SSP)
6) "00100B"
 ILM
7) "0"
 S flag
8) TMP
 PC
In the INTE instruction and processing routine of step trace trap, do not use INTE instruction.
Also, EIT does not occur by INTE during the execution of the step.
■ Operation of Step Trace Trap
If the step trace function is enabled by setting T flag at the SCR in the PS, trap occurs every one instruction
execution and breaks. The detecting conditions of step trace trap are shown below.
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3.10 EIT (Exception, Interrupt, Trap)
MB91345 Series
[Detecting conditions of step trace trap]
• T flag=1
• Not a branch instruction with delay
• When a processing routine excepting INTE instruction or step trace trap is executing.
When the above conditions are met, it breaks at the interval of the instruction operations.
[Operation]
1) (TBR+3CCH)
 TMP
2) SSP- 4
 SSP
3) PS
 (SSP)
4) SSP- 4
 SSP
5) Address of the next instruction  (SSP)
6) "00100B"
 ILM
7) "0"
 S flag
8) TMP
 PC
When the step trace trap is enabled by setting T flag, NMI for user and user interrupt enter into the
prohibited state. And EIT by INTE instruction does not occur.
In the FR family, trap occurs from the instruction next to the one that T flag was set.
■ Operation of Undefined Instruction Exception
Undefined instruction exception occurs when it detects undefined instruction during instruction decoding.
The detecting conditions of undefined instruction exception are shown below.
• When decoding the instruction, it detects as undefined instruction.
• It is located outside of the delay slot. (It is not just after the branch instruction with delay.)
When the above conditions are met, undefined instruction exception occurs and breaks.
[Operation]
1) (TBR+3C4H)
 TMP
2) SSP- 4
 SSP
3) PS
 (SSP)
4) SSP- 4
 SSP
5) PC
 (SSP)
6) "0"
 S flag
7) TMP
 PC
The one to be saved into as PC is the address of the instruction itself that detected the undefined instruction
exception.
■ Co-processor Non Existence Trap
Co-processor non existence trap occurs when co-processor instruction that uses uninstalled co-processor is
executed.
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3.10 EIT (Exception, Interrupt, Trap)
MB91345 Series
[Operation]
1) (TBR+3E0H)
 TMP
2) SSP- 4
 SSP
3) PS
 (SSP)
4) SSP- 4
 SSP
5) Address of next instruction
 (SSP)
6) "0"
 S flag
7) TMP
 PC
■ Co-processor Error Trap
In case an error occurs during a co-processor is used, and when the next co-processor instruction that
handles the co-processor is executed, a co-processor error trap occurs.
[Operation]
1) (TBR+3DCH)
 TMP
2) SSP- 4
 SSP
3) PS
 (SSP)
4) SSP- 4
 SSP
5) Address of next instruction
 (SSP)
6) "0"
 S flag
7) TMP
 PC
■ Operation of RETI Instruction
RETI instruction is the instruction to return from EIT processing routine.
[Operation]
1) (R15)
 PC
2) R15+4
 R15
3) (R15)
 PS
4) R15+4
 R15
RETI instruction should be executed in the state which S flag is "0".
■ Caution for a Delay Slot
A delay slot of branch instruction has restrictions regarding EIT.
Refer to "3.9 Branch Instruction".
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CHAPTER 3 CPU and Control Section
3.11 Operation Modes
3.11
MB91345 Series
Operation Modes
There are bus mode and access mode for the operation modes. Each mode is
explained.
■ Operation Mode
Bus mode
Access mode
Single chip
32-bit bus width
16-bit bus width
8-bit bus width
● Bus mode
The bus mode is the mode that specifies with the mode setting pins (MD2, MD1, MD0) and the contents of
ROMA bit in the mode data.
● Access mode
The access mode is the mode that controls external data bus width, and it specifies with WTH1, WTH0 bits
in the mode register.
■ Bus Mode
● Bus mode 0 (Single chip mode)
In this mode, internal I/O, D-bus RAM, F-bus RAM and F-bus ROM are valid and the access to other area
is invalid.
External pin does the function of peripheral or general purpose port. It does not work as a bus pin.
■ Mode Setting
In the FR family, operation mode is set by the mode setting pins (MD2, MD1, MD0) and the mode register
(MODR).
● Mode pins
They are three pins of MD2, MD1 and MD0, and specify the contents of the mode vector fetch.
Table 3.11-1 explains about the mode setting.
Table 3.11-1 Mode Setting
Mode pins
MD2 MD1 MD0
Mode name
Reset vector Access area
000B
Internal ROM mode vector
Internal
Remarks
Note:
In the FR family, external mode vector fetch by multiplex bus is not supported.
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MB91345 Series
● Mode register (MODR)
The data that are written in the mode register by mode vector fetch is called mode data. For mode vector
fetch, refer to "3.12.3 Reset Sequence".
After the mode register (MODR) is set, it operates in the operation mode set by this register.
The mode register is set by all reset factors. And it is not written in by the user program.
Reference:
Nothing exists in the address (0000 07FFH) of the mode register of conventional FR family.
In the emulator mode, rewriting is possible. In this case, use data transfer instruction of 8-bit length.
It cannot be written by 16/32-bit length transfer instruction.
The details of the mode register are shown below.
[Details of the mode register]
Figure 3.11-1 Bit Configuration of Mode Register (MODR)
MODR
0007FCH
bit7
bit6
bit5
bit4
bit3
0
0
0
0
0
W
W
W
W
W
bit2
bit1
bit0
ROMA WTH1 WTH0
W
W
Initial value
XXXXXXXXB
W
Operation mode setting bits
W: Write only
[bit7 to bit3] Reserved bits
Make sure to set "00000B".
The operation is not assured if the value other than "00000B" is set.
[bit2] ROMA (Internal ROM enable bit)
Make sure to set "1".
Table 3.11-2 ROMA (Internal ROM Enable Bit)
ROMA
Function
0
-
1
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Remarks
Setting is prohibited
Internal ROM mode
Embedded F-bus RAM and F-bus ROM become valid.
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3.11 Operation Modes
MB91345 Series
[bit1, bit0] WTH1, WTH0 (Bus width specifying bits)
Make sure to set "11B".
Table 3.11-3 WTH1, WTH0 (Bus Width Specifying Bits)
WTH1
WTH0
Function
Remarks
0
0
-
Setting is prohibited
0
1
-
Setting is prohibited
1
0
-
Setting is prohibited
1
1
Single chip mode
Single chip mode
Note:
Mode data to be set to the mode vector must be placed in "000FFFF8H" as byte data. Since big
endian is used for byte endian in the FR family, mode data should be placed in the most significant
byte, from bit31 to bit24 as shown in the diagram below.
bit
24
23
16
15
8
7
0
Wrong
000FFFF8H
XXXXXXXX
XXXXXXXX
XXXXXXXX
Mode Data
Correct
000FFFF8H
Mode Data
XXXXXXXX
XXXXXXXX
XXXXXXXX
000FFFFCH
74
31
Reset Vector
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CHAPTER 3 CPU and Control Section
3.12 Reset (Initialization of the Device)
MB91345 Series
3.12
Reset (Initialization of the Device)
In this section, reset which is the initialization of the FR family devices is explained.
■ Reset (Initialization of the Device)
When reset factor occurs, the device halts all programs and hardware operations and initializes the state.
This state is called a reset state.
Disappearing of reset factors makes the device start programs and hardware operations from the initial
state. MB91345 series of operation from the reset state to the starting of operations is called a reset
sequence.
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3.12 Reset (Initialization of the Device)
3.12.1
MB91345 Series
Reset Level
The reset operations of the FR family device are divided into two kinds of level and each
occurring factors and initialization contents are different respectively.
■ Setting Initialization Reset (INIT)
The highest level reset that initializes all settings is called setting initialization reset (INIT).
The main settings that are initialized by setting initialization reset (INIT) are as shown below.
● Settings initialized by setting initialization reset (INIT)
• Operation mode of the device (settings of the bus mode and the access mode)
• All settings regarding the internal clock (clock source selection, PLL control, division ratio setting)
• All settings of other pin state
• All settings that are initialized by operation initialization reset (RST)
For details, refer to the explanation of each function.
Note:
Be sure to do the setting initialization reset by INIT pin after power on.
■ Operation Initialization Reset (RST)
Normal level reset that initializes the program operation is called operation initialization reset (RST).
At setting initialization reset (INIT), operation initialization reset (RST) is also occurred simultaneously.
The main settings that are initialized by operation initialization reset (RST) are as shown below.
● Settings initialized by operation initialization reset (RST)
• Program operations
• CPU and internal buses
• Register setting values of the peripheral circuits
• I/O port settings
• Operation mode of the devices (settings of the bus mode and the access mode)
For details, refer to the explanation of each function.
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MB91345 Series
3.12.2
Reset Factor
Various reset occurring factors and occurring reset levels of the FR family devices are
explained.
The reset factors that occurred in the past can be known by reading out the RSRR
(Reset Factor Register). The details of register and flag in each explanation are
explained in "3.13.5 Block Diagram of Clock Generation Control Section" and "3.13.6
Registers of the Clock Generation Control Section".
■ INIT Pin Input (Setting Initialization Reset Pin)
INIT pin of external pin works as a setting initialization reset pin.
While "L" level is input to this pin, the setting initialization reset (INIT) request occurs.
By inputting "H" level to this pin, the setting initialization reset (INIT) request is released.
When INIT occurs by the request of this pin, bit15 (INIT bit) in the RSRR (reset factor register) is set.
The setting initialization reset (INIT) by the request of this pin is the strongest in all reset factors, and it
takes priority over all input/operation/state.
Make sure to do setting initialization reset (INIT) on INIT pin just after power on.
And, to assure the oscillation stabilization waiting time for oscillation circuit and the stabilization waiting
time for the regulator just after power on, hold "L" level input on INIT pin during the waiting time for
stabilization that the oscillation circuits requires.
For INIT by the INIT pin, the initial setting of the stabilization waiting time for oscillation is set to
minimum value.
• Generation trigger
: "L" level input on the external INIT pin
• Release trigger
: "H" level input on the external INIT pin
• Generation level
: Setting initialization reset (INIT)
• Corresponding flag : bit15 (INIT)
■ Software Reset (STCR:SRST Bit Writing)
When "0" is written in the bit4 (SRST bit) of the standby control register (STCR), a software reset request
occurs. The software reset request is an operation initialization reset (RST) request.
When the request is accepted and an operation initialization reset (RST) occurs, then the software reset
request is released.
In case the operation initialization reset (RST) occurred by the software reset request, then bit11 (SRST bit)
of RSRR (reset factor register) is set.
In case the bit9 (SYNCR bit) in the time-base counter control register (TBCR) is set (the synchronous reset
mode), the operation initialization reset (RST) by the software reset request does not occur until all bus
access stops.
Therefore, depending on the situation of bus use, there is a case that it takes a long time until the operation
initialization reset (RST) occurs.
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MB91345 Series
• Generation trigger
: Writing "0" into the bit4 (SRST bit) of standby control register (STCR)
• Release trigger
: Generation of operation initialization reset (RST)
• Generation level
: Operation initialization reset (RST)
• Corresponding flag : bit11 (SRST)
■ Watchdog Reset
When writing into the watchdog timer control register (RSRR), the watchdog timer is activated. After that,
if A5H/5AH writing is not done into the watchdog reset generation postpone register (WPR) in a period set
by the bit9 and bit8 (WT1, WT0 bits) in RSRR, a watchdog reset request is generated.
The watchdog reset request is a setting initialization reset (INIT) request. When the request is accepted and
if setting initialization reset (INIT) generates or operation initialization reset (RST) generates, the watchdog
reset request is cancelled.
When setting initialization reset (INIT) generates by watchdog reset request, the bit13 (WDOG bit) in the
reset factor register (RSRR) is set.
In addition, in case setting initialization reset (INIT) generates by watchdog reset request, oscillation
stabilization waiting time setting is not initialized.
• Generation trigger
: Passing the set period of watchdog timer
• Release trigger
: Generation of setting initialization reset (INIT) or operation initialization reset (RST)
• Generation level
: Setting initialization reset (INIT)
• Corresponding flag : bit13 (WDOG)
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3.12 Reset (Initialization of the Device)
MB91345 Series
3.12.3
Reset Sequence
The device starts execution of reset sequence by disappearing of reset trigger.
The operation content of reset sequence is different for each reset level.
In this section, the operation contents of reset sequence for each reset level are
explained.
■ Setting Initialization Reset (INIT) Cancellation Sequence
When setting initialization reset (INIT) request is cancelled, the device executes the operations shown
below in sequence.
1) Cancellation of setting initialization reset (INIT), transition to oscillation stabilization waiting state
2) During the oscillation stabilization waiting time (set by bit3, bit2 (OS1, OS0 bits of STCR)), holds the
state of operation initialization reset (RST), stops the internal clock.
3) State of operation initialization reset (RST), stars the internal clock operation.
4) Cancellation of operation initialization reset (RST), transition to the state of normal operation
5) From the address 000FFFF8H, reads the mode vector.
6) To MODR (mode register) in the address 000007FDH, writes the mode vector.
7) From the address 000FFFFCH, reads reset vector.
8) To program counter (PC), writes reset vector.
9) From the address indicated by the program counter (PC), starts program operation.
■ Operation Initialization Reset (RST) Cancellation Sequence
This reset is generated by software reset.
When operation initialization reset (RST) request is cancelled, the device executes the operations shown
below in sequence.
1) Cancellation of operation initialization reset (RST), transition to the state of normal operation
2) From the address 000FFFF8H, reads the mode vector.
3) To MODR (mode register) in the address 000007FDH, writes the mode vector.
4) From the address 000FFFFCH, reads the reset vector.
5) To program counter (PC), writes the reset vector.
6) From the address indicated by the program counter (PC), starts the program operation.
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3.12 Reset (Initialization of the Device)
3.12.4
MB91345 Series
Oscillation Stabilization Waiting Time
When the device returned from the state that source oscillation of the device was
halting or the state that such a possibility existed, it automatically moves to oscillation
stabilization waiting state. By this function, it makes not to use the oscillator output that
is not stable after starting oscillation.
During oscillation stabilization waiting time, clock supply to internal and external is
halted, and only internal time-base counter operates and waits for passing of
stabilization waiting time which was set in the standby control register (STCR).
In this section, oscillation stabilization waiting operation is explained.
■ Generation Trigger of Oscillation Stabilization Waiting
Generation trigger of oscillation stabilization waiting is shown below.
● When setting initialization reset (INIT) is cancelled
It moves to the state of oscillation stabilization waiting just after setting initialization reset (INIT) was
cancelled by some triggers.
After passing oscillation stabilization waiting time, it moves to the state of operation initialization reset
(RST).
● When returning from the stop mode
Just after the stop mode was cancelled, it moves to the state of oscillation stabilization waiting. But, in case
it was cancelled by the setting initialization reset (INIT) request, it moves to the state of setting
initialization reset (INIT), and after the setting initialization reset (INIT) is cancelled, it moves to the state
of oscillation stabilization waiting.
After passing oscillation stabilization waiting time, it moves to the state corresponding to the factors that
cancelled the stop mode.
• When returning by the occurrence of valid external interrupt request input (includes NMI):
It moves to the normal operation state.
• When returning by the setting initialization reset (INIT) request:
It moves to the state of the setting initialization reset (INIT)
• When returning by the operation initialization reset (RST) request:
It moves to the state of the operation initialization reset (RST)
● When returning from the abnormal state occurrence at selecting PLL
In case any abnormality* occurs in PLL control during the PLL is operating as a source clock, it
automatically moves to oscillation stabilization waiting time to secure PLL lock time.
After passing oscillation stabilization waiting time, it moves to the normal operation state.
*: Occurrence of the change in the frequency multiplication coefficient while PLL is being used, and PLL
operation enable bit is garbled, etc.
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3.12 Reset (Initialization of the Device)
MB91345 Series
■ Selection of the Oscillation Stabilization Waiting Time
The oscillation stabilization waiting time is counted by the embedded time-base counter.
When the oscillation stabilization waiting generation trigger occurs and it moves to the state of oscillation
stabilization waiting, once the embedded time-base counter is initialized and then starts clocking of the
oscillation stabilization waiting time.
By the bit3 and bit2 (OS1, OS0 bits) of the standby control register (STCR), the oscillation stabilization
waiting time can be set by selecting from the four kinds of the waiting time. Once the setting is selected, it
is not initialized except setting initialization reset (INIT) by external INIT pin. By other resets such as
watchdog reset/setting initialization reset (INIT) by low voltage detection standby and the operation
initialization reset (RST), the oscillation stabilization waiting time which was set before reset occurred is
held.
The four kinds of setting parameters for selecting the oscillation stabilization waiting time are assumed to
be used as shown below.
• OS1, OS0=00B : No oscillation stabilization waiting time (the case that PLL does not stop oscillator
by stop mode)
• OS1, OS0=01B : PLL lock waiting time (the case that oscillator is not stopped by external clock input
or stop mode)
• OS1, OS0=10B : Oscillation stabilization waiting time (medium) (the case that uses oscillator element
which stabilizes fast, such as ceramic resonator)
• OS1, OS0=11B : Oscillation stabilization waiting time (long) (the case that uses conventional crystal
oscillator element)
In addition, just after power on, be sure to do setting initialization reset (INIT) by INIT pin.
And just after power on, to assure the oscillation stabilization waiting time of the oscillator circuits and the
stabilization waiting time of regulator, hold "L" level input on INIT pin during the stabilization waiting
time which is required by the oscillation circuits. (In case INIT by INIT pin, the setting of the oscillation
stabilization waiting time is initialized to minimum value.)
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3.12 Reset (Initialization of the Device)
3.12.5
MB91345 Series
Reset Operation Mode
In the operation initialization reset (RST), there are two modes, the normal
(asynchronous) reset mode and the synchronous reset mode, and either of two modes
can be set by the bit9 (SYNCR bit) in the time-base counter control register (TBCR). This
mode setting is initialized only by the setting initialization reset (INIT). The setting
initialization reset (INIT) always does reset operation asynchronously.
Operation of each mode is explained in this section.
■ Normal Reset Operation
The operation that instantaneously moves to the state of operation initialization reset (RST) when the
operation initialization reset (RST) request occurs is called the normal reset operation.
In this mode, when reset (RST) request is accepted, it instantaneously moves to the reset (RST) state
regardless of the operation state for internal bus access.
In this mode, the results cannot be assured for the bus access which was being done at the time moving to
each state. But it is possible to surely accept those requests.
When the bit9 (SYNCR bit) in the time-base counter control register (TBCR) is "0", it becomes the normal
reset mode. The initial value after occurring of the setting initialization reset (INIT) becomes the normal
reset mode.
■ Synchronous Reset Operation
In case the operation initialization reset (RST) request occurs, the operation that moves to the operation
initialization reset (RST) state after all bus access stopped is called the synchronous reset operation.
In this mode, moving to the reset (RST) state is not done during internal bus access is being done despite
the reset (RST) request is accepted.
When the above request is accepted, then the sleep request is issued to the internal bus. When each bus
halts operation and moves to the sleep state, then it moves to the operation initialization reset (RST) state.
In this mode, as all bus access is halting at the time of moving to each state, the results of all bus access are
assured.
But in case that bus access does not halt by some reason, each request cannot be accepted during that
period. Even in the case like this, the setting initialization reset (INIT) becomes valid instantaneously.
The following cases are listed as the causes that bus access does not halt.
• The case that bus cancellation request (BRQ) is being continued to input to the external expanded bus
interface, and the bus cancellation acknowledge (BGRNT) is valid, and in case that new bus access
request is occurring from the internal bus.
• The case that ready request (RDY) is being continued to input to the external expanded bus interface,
and in case the bus wait is valid.
In the next case, it takes long time to move, though it moves to each state for the last time.
• The case that SDRAM interface is activated, and self refresh at sleep is set (it does not perform status
transition until self refresh mode setting is finished).
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Reference:
• Refer to the restrictions on bit9: SYNCR bit in the time-base counter control register (TBCR) for
the use of the synchronous reset mode.
• Transfer of the DMA controller will be stopped on receiving each request, so transition to each
status does not need to be delayed.
• The synchronous reset mode will start when bit9: SYNCR bit in the time-base counter control
register (TBCR) is "1".
• The initial value after the setting initialization reset (lNIT) has occurred returns to the normal reset
mode.
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CHAPTER 3 CPU and Control Section
3.13 Clock Generation Control
3.13
MB91345 Series
Clock Generation Control
In this section, clock generation and its control are explained.
■ Clock Generation Control
The internal operation clock of the FR family device is generated as shown below.
• Selection of the source clock
: Selects the source of the clock supply.
• Generation of the base clock
: Generates the basic clock by dividing the source clock by two or by
oscillating PLL.
• Generation of each internal clock : Divides the base clock, and generates three kinds of operation
clocks that are supplied to each part.
 indicates the base clock generated by dividing the source clock by 2 or by oscillating PLL. Therefore, the
system base clock is a clock generated when the base clock above occurs.
Generation and control of each clock are explained below. Refer to "3.13.5 Block Diagram of Clock
Generation Control Section", "3.13.6 Registers of the Clock Generation Control Section" for details of the
registers and the flags in each explanation.
■ Source Clock
● Autodyne oscillation mode (X0/X1 pin input)
This is the mode that makes source oscillation that is generated in the internal oscillation circuit by
connecting an oscillator element on the external oscillation pin as the source clock.
All clock supply source is the FR family device itself.
Main clock:
Generates from X0/X1 pin input, and it is assumed to be used as a high speed clock.
The main clock is multiplied by using the controllable embedded main PLL.
The internal base clock is generated by selecting the source clock shown below.
• Main clock divided by two
• Main clock multiplied by main PLL
Selection control of the source clock is done by setting of the clock source control register (CLKR).
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3.13 Clock Generation Control
MB91345 Series
3.13.1
PLL Control
For each PLL oscillation circuits corresponding to the main source clock, it is possible
to control operation (oscillation) enable/disable and the setting of multiplier ratio
independently. Each control is done by setting the clock source control register (CLKR).
The content of each control is explained below.
■ PLL Operation Enabling
Enable/disable of the main PLL oscillation is done by setting the bit10 (PLL1EN bit) of the clock source
control register (CLKR).
● PLL operation control
Both bits are initialized to "0" after setting initialization reset (INIT), and PLL oscillation operation stays in
halt. During halt, PLL output cannot be selected as a source clock.
When the program operation starts, in the first place, set the frequency multiplication coefficient of PLL for
the clock source, and after enabling operation, switch the source clock after passing the lock waiting time
of PLL. In this case, during the lock waiting time of the PLL, the time-base timer interrupt can be used.
During the PLL output is selected as the source clock, that PLL operation cannot be stopped (writing into
the register becomes invalid). In case to stop the PLL to move to the stop mode, once reselect the main
clock divided by two as a source clock, then stop the PLL.
In addition, in case that it is specified as oscillation stops in the stop mode by setting the bit0 (OSCD1 bit)
of the standby control register (STCR), as the corresponding PLL automatically stops when it moves to the
stop mode, it is not necessary to set to stop operation again. After that when returning from the stop mode,
PLL automatically starts oscillation operation. In case that it is specified as the oscillation does not stop in
stop mode, the PLL does not stop automatically. In this case, if it is necessary, set the operation stop before
moving to the stop mode.
■ PLL Frequency Multiplication Coefficient
The frequency multiplication coefficient of the main PLL is set by bit14 to bit12 (PLL1S2, PLL1S1,
PLL1S0 bits) of the clock source control register (CLKR).
After the setting initialization reset (INIT), bit14 to bit12 (PLL1S2, PLL1S1, PLL1S0 bits) are initialized to
"0".
● Setting of the PLL frequency multiplication coefficient
When changing the setting of PLL frequency multiplication coefficient from the initial value in the
autodyne oscillation mode, it should be set after the program operation starts, and before or at the same
time of enabling the PLL operation. After the frequency multiplication coefficient is changed, switch the
source clock after passing lock waiting time. In this case, in the PLL lock waiting time, the time-base timer
interrupt can be used.
When changing the PLL frequency multiplication coefficient in operation, once switch the source clock to
the one that is not relevant PLL, and then change it. After changing the frequency multiplication
coefficient, switch the source clock after passing the lock waiting time as described above.
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Though setting of the PLL frequency multiplication coefficient can be changed while the PLL is being
used, in this case, after rewriting the frequency multiplication coefficient, it automatically moves to the
state of oscillation stabilization waiting, the program operation stops until passing the set oscillation
stabilization waiting time.
In case the clock source is changed to other than PLL, the program operation does not stop.
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3.13.2
Oscillation Stabilization Waiting/PLL Lock Waiting Time
In case the clock selected as the source clock is not in stable state, the oscillation
stabilization waiting time is required. (Refer to "3.12.4 Oscillation Stabilization Waiting
Time")
For the PLL, lock waiting time is required until the output becomes stable at the set
frequency after the operation started.
In this section, waiting times for several cases are explained.
● Waiting time after power on
After power on, in the first place, the oscillation stabilization waiting time for the oscillation circuit for
main clock is required.
As the setting of the oscillation stabilization waiting time is initialized to the minimum value by the INIT
pin input (setting initialization reset pin), this oscillation stabilization waiting time is assured by the input
time of "L" level on INIT pin input.
In this state, as both PLL are not enabled to operate, the lock waiting time is not need to be considered.
● Waiting time after setting initialization
When the setting initialization reset (INIT) is cancelled, it moves to the state of oscillation stabilization
waiting. In that state, the specified oscillation stabilization waiting time is internally generated. At the
beginning of the state for oscillation stabilization waiting after INIT pin input, as the setting value is
initialized to the minimum value, soon this state finishes, and it moves to the state of operation initialization
reset (RST).
After the program operation started, at the time of cancellation in case the setting initialization reset (INIT)
occurred by the causes other than INIT pin input, the oscillation stabilization waiting time that was set by
the program is internally generated.
In these state, as both PLL are not enabled to operate, the lock waiting time is not need to be considered.
● Waiting time after changing of the PLL frequency multiplication coefficient
After the program operation starts, when the frequency multiplication coefficient setting of the PLL in
operation is changed, the program operation halts temporarily and moves to the state of oscillation
stabilization waiting (lock waiting), and after passing the specified oscillation stabilization waiting (lock
waiting) time, it returns to the program operation.
The time-base counter is once initialized by this operation.
● Waiting time after returning to the stop mode
After the program operation starts, at the time of cancellation in case it moved to the stop mode, the time
period of oscillation stabilization waiting time set by the program is internally generated. In case the setting
was to stop the oscillation circuit for main clock in the stop mode, between the oscillation stabilization
waiting time of the oscillation circuit and lock waiting time of main PLL, the longer time becomes
necessary. Before moving to the stop mode, set its oscillation stabilization waiting time in advance.
In case setting is not to stop the oscillation circuit for the main clock in the stop mode, the PLL does not
stop automatically. Unless stopping the PLL, the oscillation stabilization waiting time is not necessary.
Before moving to the stop mode, the oscillation stabilization waiting time should be set to the minimum
value in advance.
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3.13.3
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Clock Distribution
The operation clocks for each function are generated based on the base clock
generated from the source clock. There are four kinds of internal operation clock and
the dividing ratio can be set independently for each of them.
In this section, each internal operation clock is explained.
■ CPU Clock (CLKB)
This is the clock that is used for the CPU, the internal memory and the internal bus.
The circuits that use this clock are as shown below.
• CPU
• Embedded RAM
• Bit search module
• I-bus, D-bus, X-bus, F-bus
• DMA controller
• DSU (development tool interface circuit)
As the upper limit of the operable frequency is 50 MHz, do not set a combination of the frequency
multiplication coefficient and the dividing ratio that makes the frequency exceeding this limit.
■ Peripheral Clock (CLKP)
This is the clock used for the peripheral circuits and the peripheral bus.
The circuits that use this clock are as shown below.
• Peripheral bus
• Clock control section (bus interface section only)
• Interrupt controller
• Peripheral I/O port
• I/O port bus
• External interrupt input
• UART
• 16-bit timer
• A/D converter
• PPG
As the upper limit of the operable frequency is 25 MHz, do not set a combination of the frequency
multiplication coefficient and the dividing ratio that makes the frequency exceeding this limit.
Note:
The processing power of the CPU also depends on the wait register (FLWC) setting. Make sure that
the setting of this register is optimized before use. Refer to "19.2.2 Wait Register (FLWC)".
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Clock Dividing
For the internal operation clock, the dividing ratio from the base clock can be set
independently. The optimum operation frequency can be set for each circuit by this
function.
■ Clock Dividing
The dividing ratio is set by the base clock dividing setting register 0 (DIVR0) and the base clock dividing
setting register 1 (DIVR1). Each register has four bits of setting bits corresponding to each clock, and for
its clock, (register set value +1) becomes the dividing ratio to the base clock. Regardless the dividing ratio
setting is odd number, the duty always becomes 50 %.
When the setting value is changed, the changed dividing ratio becomes valid from the rising edge of the
next clock after setting.
The setting of dividing ratio is not initialized by the occurrence of the operation initialization reset (RST),
and the setting is held as the one before reset occurred. It is initialized only by the occurrence of the setting
initialization reset (INIT).
In the initial state, as all dividing ratio become one, except peripheral clock (CLKP), be sure to set the
dividing ratio before changing the source clock to fast one.
For each clock, the upper limit of the operable frequency is defined. Be cautious that in case the setting
which exceeds the upper limit frequency is done by the combination of the source clock selection, the
frequency multiplication coefficient setting of the PLL and the dividing ratio setting, the operation is not
assured. Especially be careful not to mistake the order with setting of source clock selection change.
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3.13.5
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Block Diagram of Clock Generation Control Section
In this section, the block diagram of the clock generation control section is shown.
■ Block Diagram
Figure 3.13-1 shows the block diagram of the clock generation control section.
For details of the register in Figure 3.13-1, refer to "3.13.6 Registers of the Clock Generation Control
Section".
Figure 3.13-1 Block Diagram of Clock Generation Control Section
Peripheral stop control register
R-bus
[ Clock generation section ]
DIVR0,DIVR1 register
CPU clock dividing
CPU clock
X0
X1
Oscillation
circuit
External bus clock dividing
X1A
Oscillation
circuit
Selector
External bus clock
CLKR register
PLL
Main oscillation
1/2
X0A
Each peripheral clock
Selector
Main oscillation
stabilization
waiting timer
(for selecting sub)
Selector
Peripheral
stop control
Each peripheral clock dividing
Stop control
Selector
Sub oscillation
Watch timer
[ Stop/sleep control section ]
Internal interrupt
STCR Register
Stop state
State
transition
control
circuits
Internal reset
Sleep state
Reset generation
F/F
Reset generation
F/F
Internal reset (RST)
Internal reset (INIT)
[ Reset factor circuits ]
INIT pin
RSRR register
[ Watchdog control section ]
Watchdog F/F
WPR register
Time-base counter
Counter clock
CTBR register
Selector
TBCR register
Overflow detecting F/F
Time-base timer
interrupt request
Interrupt enable
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3.13.6
Registers of the Clock Generation Control Section
In this section, the function of the registers used in the clock generation control section
is explained.
■ Reset Factor Register/Watchdog Timer Control Register (RSRR)
Figure 3.13-2 shows the bit configuration of the reset factor register/watchdog timer control register
(RSRR).
Figure 3.13-2 Bit Configuration of Reset Factor Register/Watchdog Timer Control Register (RSRR)
Address: 00000480H
R/W:
R:
:
X:
bit15
bit14
bit13
bit12
bit11
bit10
bit9
INIT

WDOG

SRST

WT1
R
R
R
R
R
R
R/W
bit8
Initial value
WT0 10000000B (INIT pin)
-0-XX-00B (INIT)
R/W XXX--X00 (RST)
B
Readable/writable
Read only
Initialized by the factor
Not initialized
This register holds reset causes which occurred just before, and accomplishes the setting of the period for
the watchdog timer and its activation control. When reading this register, the held reset causes is cleared
after reading out. In case plural resets occur until reading out, the reset factor flags are accumulated and
plural flags are set.
When writing into this register, the watchdog timer is activated. After that, the watchdog timer continues to
operate until reset (RST) occurs.
The function of each bit in the reset factor register/watchdog timer control register (RSRR) is explained
below.
[bit15] INIT (INITialize reset occurred)
This bit indicates whether there was an occurrence of reset (INIT) by INIT pin input.
Table 3.13-1 shows the function of INIT.
Table 3.13-1 INIT Function
INIT
Function
0
INIT did not occur by INIT pin input.
1
INIT occurred by INIT pin input.
• It is initialized to "0" just after reading.
• Reading is possible, and writing does not affect to the bit value.
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[bit14]  (Reserved bit)
This bit is a reserved bit.
[bit13] WDOG (WatchDOG reset occurred)
This bit indicates whether there was an occurrence of reset (INIT) by the watchdog timer. Table 3.13-2
shows the function of WDOG.
Table 3.13-2 WDOG Function
WDOG
Function
0
INIT by watchdog timer did not occur.
1
INIT by watchdog timer occurred.
• It is initialized to "0" just after reset (INIT) by the INIT pin input or reading.
• Reading is possible, and writing does not affect to the bit value.
[bit12] (Reserved bit)
This bit is a reserved bit.
[bit11] SRST (Software ReSeT occurred)
This bit indicates whether there was an occurrence of reset (RST) by SRST bit writing (software reset)
of standby control register (STCR).
Table 3.13-3 shows the function of SRST.
Table 3.13-3 SRST Function
SRST
Function
0
RST by software reset did not occur.
1
RST by software reset occurred.
• It is initialized to "0" just after reset (INIT) by the INIT pin input or reading.
• Reading is possible, and writing does not affect to the bit value.
[bit10] (Reserved bit)
This bit is a reserved bit.
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[bit9, bit8] WT1, WT0 (Watchdog interval Time select)
These bits set the time period of the watchdog timer.
By the value written into these bits, the time period of the watchdog timer is selected from the four
kinds shown in Table 3.13-4.
Table 3.13-4 shows the time period of the watchdog timer.
Table 3.13-4 Time Period of Watchdog Timer
The minimum required intervals of
writing to WPR to deter the
occurrence of the watchdog reset
The time from the last 5AH writing into
WPR till the occurrence of the
watchdog reset
WT1
WT0
0
0
×216
0
1
×218
×218 to ×219
1
0
×220
×220 to ×221
1
1
×222
×222 to ×223
(Initial value)
×216 to ×217
 : Time period of the system base clock.
• These bits are initialized to "00B" by reset (RST).
• These bits are readable and writing is valid only once after reset (RST). The writing after that is
invalid.
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■ Standby Control Register (STCR)
Figure 3.13-3 shows the bit configuration of the standby control register (STCR).
Figure 3.13-3 Bit Configuration of the Standby Control Register (STCR)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
OSCD1 00110011 (INIT pin)
HIZ SRST OS1 OS0

B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W 00111111B (HST)*
*
: Only in case it is done at the same time of initialization by the INIT pin, in other 0011XX11B (INIT)
cases, it is same as the one at INIT.
00X1XXXXB (RST)
R/W : Readable/writable
Address: 00000481H STOP SLEEP
The standby control register (STCR) controls the operation mode of the device.
It does moving to two standby modes of stop and sleep, pin and oscillation stop control in the stop mode,
setting of oscillation stabilization waiting time and issuing of software reset.
Note:
In case being able to go into the standby mode, use synchronous standby mode (set by the bit8
SYNCS bit of the time-base counter control register TBCR) and be sure to use the following
sequence.
(LDI
#value_of_standby, R0) ; value_of_standby is the write data to STCR
(LDI
#_STCR, R12)
; _STCR is the address (481H) of STCR
STB
R0,@R12
; Write into the standby control register (STCR)
LDUB
@R12, R0
; STCR read for synchronous standby
LDUB
@R12, R0
NOP
; Once again, dummy read STCR
; NOP × 5 for timing adjustment
NOP
NOP
NOP
NOP
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The function of each bit in the standby control register (STCR) is explained.
[bit7] STOP (STOP mode)
This bit specifies to move to the stop mode. In case "1" is written both in the bit6 (SLEEP bit) and in
this bit, this bit (STOP) takes priority and moves to the stop mode.
Table 3.13-5 shows the function of STOP.
Table 3.13-5 STOP Function
STOP
Function
0
Does not move to stop mode. (Initial value)
1
Moves to stop mode.
• It is initialized to "0" by reset (RST) and the stop returning factor.
• Read and write are possible.
[bit6] SLEEP (SLEEP mode)
This bit specifies to move to the sleep mode. In case "1" is written both in the bit7 (STOP bit) and in
this bit, the bit7 (STOP bit) has a priority and moves to the stop mode.
Table 3.13-6 shows the function of SLEEP.
Table 3.13-6 SLEEP Function
SLEEP
Function
0
Does not move to sleep mode. (Initial value)
1
Moves to sleep mode.
• It is initialized to "0" by reset (RST) and the sleep returning factor.
• Read and write are possible.
[bit5] HIZ (HIZ mode)
This bit controls the pin state in the stop mode.
Table 3.13-7 shows the function of HIZ.
Table 3.13-7 HIZ Function
HIZ
Function
0
Holds the pin state before it moved to stop mode.
1
Makes the pin output to high impedance in stop mode. (Initial value)
• It is initialized to "0" by reset (INIT)
• Read and write are possible.
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[bit4] SRST (Software ReSeT)
This bit specifies issuing of the software reset (RST).
Table 3.13-8 shows the function of SRST.
Table 3.13-8 SRST Function
SRST
Function
0
Issues a software reset.
1
Does not issue a software reset. (Initial value)
• It is initialized to "1" by reset (RST).
• Read and write are possible. The read out value is always "1".
Reference:
Refer to the restrictions on bit9:SYNCR bit in the time-base counter control register (TBCR) for the
use of the synchronous reset mode.
[bit3, bit2] OS1, OS0 (Oscillation Stabilization time select)
These bits specify the oscillation stabilization waiting time after reset (INIT) and returning to the stop
mode, etc.
By the value written in these bits, the oscillation stabilization waiting time is selected from the four kinds
shown in the Table 3.13-9. Table 3.13-9 shows the setting of the oscillation stabilization waiting time.
Table 3.13-9 Setting of the Oscillation Stabilization Waiting Time
Oscillation stabilization waiting
time
In case the source oscillation is
12.5 MHz
OS1
OS0
0
0
×21 (Initial value)
0
1
×211
327.68 s
1
0
×216
10.49 ms
1
1
×222
671.09 ms
0.32 s
 : Period of the system base clock, in this case double period of the source oscillation input.
• These are initialized to "00B" by reset (INIT) due to the INIT pin input.
• Read and write are possible.
[bit1]  (Reserved bit)
• It is initialized to "1" by reset (INIT).
• Write "1" when writing.
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[bit0] OSCD1 (OSCillation Disable mode for XIN1)
This bit controls oscillation stop in stop mode for main oscillation input (XIN1).
Table 3.13-10 shows the function of OSCD1.
Table 3.13-10 OSCD1 Function
OSCD1
Function
0
Main oscillation does not stop in stop mode.
1
Main oscillation stops in stop mode. (Initial value)
• It is initialized to "1" by reset (INIT).
• Read and write are possible.
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■ Time-Base Counter Control Register (TBCR)
Figure 3.13-4 shows the bit configuration of the time-base counter control register (TBCR).
Figure 3.13-4 Bit Configuration of the Time-Base Counter Control Register (TBCR)
bit15
Address: 00000482H
bit14
TBIF
TBIE
R/W
R/W
bit13
bit12
bit11
TBC2 TBC1 TBC0
R/W
R/W
R/W
bit10
bit9
bit8
Initial value
SYNCR SYNCS 00XXXX00B (INIT)

R/W
R/W
R/W 00XXXXXXB (RST)
R/W: Readable/writable
The time-base counter control register (TBCR) is the register that controls time-base timer interrupt, etc.
Not only it enables the time-base timer interrupts and selects the interrupt interval time, but also it sets
option functions of the reset operation.
The function of each bit in the time-base counter control register (TBCR) is explained.
[bit15] TBIF (Time-Base timer Interrupt Flag)
This bit is a time-base timer interrupt flag. It shows that the time-base counter has passed the specified
interval time (set by the TBC2 to TBC0 bits of bit13 to bit11).
Time-base timer interrupt request occurs when this bit becomes "1" in case interrupt occurrence is
enabled (TBIE=1) by the bit14 (TBIE bit).
Table 3.13-11 shows the function of time-base timer interrupt flag (TBIF).
Table 3.13-11 Time-Base Timer Interrupt Flag (TBIF) Function
TBIF
Function
Clear factor
"0" is written by instruction.
Set factor
Passing the specified interval time (detection of falling edge for the timebase counter output).
• It is initialized to "0" by reset (RST).
• Read and write are possible. But only "0" can be written, and if "1" is written, bit value does not
change. And in case of reading by the read modify write (RMW) instruction series, the read out
value always becomes "1".
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[bit14] TBIE (Time-Base timer Interrupt Enable)
This bit is a time-base timer interrupt request output enable bit.
It controls the interrupt request output caused by passing of interval time for the time-base counter.
When this bit is "1" and when bit15 (TBIF bit) becomes "1", then time-base timer interrupt request
occurs.
Table 3.13-12 shows the function of the time-base timer interrupt request output enabling bit (TBIE).
Table 3.13-12 Time-Base Timer Interrupt Request Output Enabling Bit (TBIE) Function
TBIE
Function
0
Time-base timer interrupt request output disabled (Initial value)
1
Time-base timer interrupt request output enabled
• It is initialized to "0" by reset (RST).
• Read and write are possible.
[bit13 to bit11] TBC2, TBC1, TBC0 (Time-Basetimer Counting time select)
These bits set the interval time of the time-base counter used by the time-base timer.
By the value written in these bits, select the interval time from the eight kinds shown in the Table 3.13-13.
Table 3.13-13 shows setting of the interval time.
Table 3.13-13 Setting of the Interval Time
TBC2
TBC1
TBC0
Timer interval time
When the source oscillation is 12.5 MHz
and PLL is multiplied by four
0
0
0
×211
40.96 s
0
0
1
×212
81.92 s
0
1
0
×213
163.84 s
0
1
1
×222
83.9 ms
1
0
0
×223
167.8 ms
1
0
1
×224
335.5 ms
1
1
0
×225
671.1 ms
1
1
1
×226
1342.2 ms
 : Time period of the system base clock.
• Initial value is indeterminate. Before enable interrupt, be sure to set the value.
• Read and write are possible.
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[bit10]  (Reserved bit)
This bit is a reserved bit. Read out value is indeterminate, and writing does not affect the operation.
[bit9] SYNCR (SYNChronous Reset enable)
This bit is a synchronous reset operation enable bit.
When the operation initialization reset (RST) request occurs, it selects whether to do the normal reset
operation that does reset (RST) instantaneously or to do the synchronous reset operation that does the
operation initialization reset (RST) after all bus access finish.
Table 3.13-14 shows the function of the synchronous reset operation enable bit (SYNCR).
Table 3.13-14 Synchronous Reset Operation Enable Bit (SYNCR) Function
SYNCR
Function
0
Normal reset operation (Initial value)
1
Synchronous reset operation
• It is initialized to "0" by reset (INIT).
• Read and write are possible.
Note:
When using software reset of the synchronous mode, be sure to satisfy the following two conditions
before setting "0" to the SRST bit of STCR (standby control register) .
• Set the interrupt enable flag (I-Flag) to interrupt disable (I-Flag=0).
• NMI is not used.
[bit8] SYNCS (SYNChronous Standby enable)
This bit is a synchronous standby operation enable bit.
Be sure to set "1" when the standby mode (the sleep mode or the stop mode) is used.
Table 3.13-15 shows the function of the synchronous standby operation enable bit (SYNCS).
Table 3.13-15 Synchronous Standby Operation Enable Bit (SYNCS) Function
SYNCS
Function
0
Normal standby operation (Initial value)
1
Synchronous standby operation
• It is initialized to "0" by reset (INIT).
• Read and write are possible.
Note:
On transition to the standby mode, be sure to set "1" as the synchronous standby operation.
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■ Time-Base Counter Clear Register (CTBR)
Figure 3.13-5 shows the bit configuration of time-base counter clear register (CTBR).
Figure 3.13-5 Bit Configuration of the Time-Base Counter Clear Register (CTBR)
bit7
Address: 00000483H
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
XXXXXXXXB (INIT)
XXXXXXXXB (RST)
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
W: Write only
The time-base counter clear register (CTBR) is used for initializing of the time-base counter.
When "A5H" and "5AH" are written consecutively in this register, all bits of the time-base counter are
cleared to "0" just after "5AH" is written. There is not a restriction for the time intervals of "A5H" writing
and "5AH" writing, but if the data other than "5AH" is written after "A5H" writing, then clear operation is
not done even if "5AH" is written unless "A5H" is written again.
The read out value of this register is indeterminate.
Note:
When clear the time-base counter using this register, the oscillation stabilization waiting time, the
watchdog timer time period, and the time period of the time-base timer change temporarily.
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■ Clock Source Control Register (CLKR)
Figure 3.13-6 shows the bit configuration of the clock source control register (CLKR).
Figure 3.13-6 Bit Configuration of the Clock Source Control Register (CLKR)
bit15

Address: 00000484H
bit14
bit13
bit12
bit11

PLL1S2 PLL1S1 PLL1S0
R/W
R/W
R/W
R/W
R/W
bit10
bit9
bit8
Initial value
PLL1EN CLKS1 CLKS0 00000000B (INIT)
R/W
R/W
R/W
XXXXXXXXB (RST)
R/W: Readable/writable
The clock source control register (CLKR) is the register that selects clock source for the system base clock
and controls PLL. By this register, the clock source is selected from the two kinds. And it enables PLL
operation and controls selection of frequency multiplication coefficient.
The function of the each bit in the clock source control register (CLKR) is explained below.
[bit15]  (Reserved bit)
This bit is a reserved bit.
[bit14 to bit12] PLL1S2, PLL1S1, PLL1S0 (PLL1 ratio Select 2-0)
These bits are the bits used for selecting the PLL frequency multiplication coefficient. From the eight
kinds in Table 3.13-16, select the PLL frequency multiplication coefficient.
These bits disable rewriting during the main PLL is selected for the clock source.
Table 3.13-16 shows setting of the PLL frequency multiplication coefficient.
Table 3.13-16 Setting of the PLL Frequency Multiplication Coefficient
PLL1S2
PLL1S1
PLL1S0
0
0
0
0
0
1
0
1
0
Main PLL frequency
multiplication coefficient
×1
When the source oscillation is 12.5 MHz
(equal)
Setting is prohibited
×2
(multiplied by 2)
Setting is prohibited
0
×3
(multiplied by 3)
 =26.7 ns (37.5 MHz)
1
1
×4
(multiplied by 4)
 =20.0 ns (50.0 MHz)
1
0
0
×5
(multiplied by 5)
Setting is prohibited
1
0
1
×6
(multiplied by 6)
Setting is prohibited
1
1
0
×7
(multiplied by 7)
Setting is prohibited
1
1
1
×8
(multiplied by 8)
Setting is prohibited
 : Time period of system base clock.
• These bits are initialized to "000B" by reset (INIT).
• Read and write are possible.
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Note:
As the upper limit of the operable frequency is 50 MHz, set them not to over this limit.
[bit11]  (Reserved bit)
This bit is a reserved bit.
[bit10] PLL1EN (PLL1 ENable)
This bit is an operation enable bit of the main PLL.
Rewriting of this bit is prohibited when the PLL is selected for the clock source.
In addition, when this bit is "0", selecting the main PLL for the clock source is prohibited (by setting
CLKS1, CLKS0 bits of bit9, bit8).
When bit0 (OSCD1 bit) of STCR is "1", and in the stop mode, the PLL stops even when this bit is "1".
After returning from the stop mode, it returns to operation enable.
Table 3.13-17 shows the function of the operation enable bit (PLL1EN) for the main PLL.
Table 3.13-17 Main PLL Operation Enable Bit (PLL1EN) Function
PLL1EN
Function
0
Main PLL stop (Initial value)
1
Main PLL operation enabled
• It is initialized to "0" by reset (INIT).
• Read and write are possible.
[bit9, bit8] CLKS1, CLKS0 (CLocK source Select)
These bits set the clock source used for FR core.
By the values written in these bits, select the clock source from the two kinds shown in the Table 3.1318.
Table 3.13-18 shows the setting of the clock source.
Table 3.13-18 Setting of the Clock Source
CM71-10132-3E
CLKS1
CLKS0
Setting of the clock source
0
0
Divided by two of the source oscillation input from X0/X1 (Initial value)
0
1
Divided by two of the source oscillation input from X0/X1
1
0
Main PLL
1
1
Setting is prohibited
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Table 3.13-19 shows unchangeable combination and changeable combination of CLKS1, CLKS0 bits.
Table 3.13-19 Unchangeable Combination and Changeable Combination of CLKS1,
CLKS0 Bits
Unchangeable combination
Changeable combination
"00B""11B"
"00B""01B" or "10B"
"01B""10B"
"01B""11B" or "00B"
"10B""01B" or "11B"
"10B""00B"
"11B""00B" or "10B"
"11B""01B"
• It is initialized to "00B" by reset (INIT).
• Read and write are possible.
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■ Watchdog Reset Generation Postponement Register (WPR)
Figure 3.13-7 shows the bit configuration of the watchdog reset generation postponement register (WPR).
Figure 3.13-7 Bit Configuration of the Watchdog Reset Generation Postponement Register (WPR)
Address: 00000485H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
XXXXXXXXB (INIT)
XXXXXXXXB (RST)
W: Write only
The watchdog reset generation postponement register (WPR) is the register that postpones generation of the
watchdog reset. When writing "A5H", "5AH" into this register consecutively, just after writing "5AH", it
clears the FF for the watchdog timer detection and postpones the generation of the watchdog reset. There is
no restriction for the time intervals between "A5H" writing and "5AH" writing. But if the data other than
"5AH" is written after "A5H" writing, clear operation is not done unless "A5H" is written again, even
though "5AH" is written. In addition, if writing of both data is not done in the time period shown in Table
3.13-20, the watchdog reset occurs.
By the state of bit9 (WT1), bit8 (WT0) of the reset factor/watchdog timer control register (RSRR), it
changes as shown in the Table 3.13-20.
Table 3.13-20 shows the setting of watchdog reset occurrence.
Table 3.13-20 Setting of Watchdog Reset Occurrence
WT1
WT0
The minimum writing intervals to WPR,
required for suppressing the watchdog reset
occurrence of RSRR
The time from the last "5AH" writing to WPR till
the occurrence of the watchdog reset
0
0
×216 (Initial value)
×216 to ×217
0
1
×218
×218 to ×219
1
0
×220
×220 to ×221
1
1
×222
×222 to ×223
 : Time period of the system base clock. WT1 and WT0 are bit9 and bit8 of RSRR and setting of the time period for the
watchdog timer.
As it clears automatically, during the time when CPU is not operating such as stop, sleep, DMA transfer, if
these conditions occur, the watchdog reset is automatically postponed.
The read out value of this register is indeterminate.
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■ Base Clock Dividing Setting Register (DIVR0)
Figure 3.13-8 shows the bit configuration of the base clock dividing setting register 0 (DIVR0).
Figure 3.13-8 Bit Configuration of the Base Clock Dividing Setting Register 0 (DIVR0)
Address: 00000486H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
B3
R/W
B2
R/W
B1
R/W
B0
R/W
P3
R/W
P2
R/W
P1
R/W
bit8
Initial value
P0 00000011B (INIT)
R/W XXXXXXXXB (RST)
R/W: Readable/writable
The base clock dividing setting register 0 (DIVR0) is the register that controls the dividing ratio of each
internal clock to the base clock. This register sets the clock (CLKB) of CPU and internal bus and the
dividing ratio of the peripheral circuits and peripheral bus clock (CLKP).
The upper limit of operable frequency is defined for each clock. Be cautious, that if setting is done as it
exceeds the upper limit frequency, by the combination of source clock selection, PLL frequency
multiplication coefficient setting, and dividing ratio setting, the operation is not assured. Be cautious not to
reverse the order with setting of the source clock selection change.
When there is a change of the setting for this register, the changed dividing ratio becomes valid from the
next clock rate after setting.
[bit15 to bit12] B3, B2, B1, B0 (clkB divide select 3-0)
These bits are the bits for setting of the clock dividing ratio for CPU clock (CLKB). It sets the clock
dividing ratio of clock (CLKB) for CPU, internal memory and internal bus.
By the value written in these bits, select the dividing ratio (clock frequency) of the clock for the CPU
and the internal bus to the base clock, from the 16 kinds shown in the Table 3.13-21.
Note:
As the upper limit of operable frequency is 50 MHz, set the dividing ratio not to exceed this
frequency limit.
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Table 3.13-21 shows the setting of the clock dividing ratio (CPU clock).
Table 3.13-21 Setting of the Clock Dividing Ratio (CPU Clock)
Clock dividing ratio
Clock frequency: Source oscillation 12.5 MHz
and PLL multiplication by four
B3
B2
B1
B0
0
0
0
0

50.0 MHz (Initial value)
0
0
0
1
×2 (divided by two)
25.0 MHz
0
0
1
0
×3 (divided by three)
16.7 MHz
0
0
1
1
×4 (divided by four)
12.5 MHz
0
1
0
0
×5 (divided by five)
10.0 MHz
0
1
0
1
×6 (divided by six)
8.3 MHz
0
1
1
0
×7 (divided by seven)
7.1 MHz
0
1
1
1
×8 (divided by eight)
6.25 MHz






1
1
1
1
×16 (divided by sixteen)
3.125 MHz
 : Time period of the system base clock.
• These bits are initialized to "0000B" by reset (INIT).
• Read and write are possible.
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[bit11 to bit8] P3, P2, P1, P0 (clkP divide select 3-0)
These bits are the bits for setting the clock dividing ratio of the peripheral clock (CLKP). It sets the
clock dividing ratio of the peripheral circuits and the peripheral bus clock (CLKP).
By the value written in these bits, select the dividing ratio (clock frequency) of the peripheral circuits
and the peripheral bus clock to the base clock, from the 16 kinds shown in Table 3.13-22.
Table 3.13-22 shows the setting of the clock dividing ratio (CPU clock).
Table 3.13-22 Setting of the Clock Dividing Ratio (CPU Clock)
Clock dividing ratio
Clock frequency: Source oscillation 12.5 MHz
and PLL multiplication by four
P3
P2
P1
P0
0
0
0
0

50.0 MHz
0
0
0
1
×2 (divided by two)
25.0 MHz
0
0
1
0
×3 (divided by three)
16.7 MHz
0
0
1
1
×4 (divided by four)
12.5 MHz (Initial value)
0
1
0
0
×5 (divided by five)
10.0 MHz
0
1
0
1
×6 (divided by six)
8.3 MHz
0
1
1
0
×7 (divided by seven)
7.1 MHz
0
1
1
1
×8 (divided by eight)
6.25 MHz






1
1
1
1
×16 (divided by sixteen)
3.125 MHz
 : Time period of the system base clock.
• These bits are initialized to "0011B" by reset (INIT).
• Read and write are possible.
Note:
As the upper limit of operable frequency is 25 MHz, set the dividing ratio not to exceed this
frequency.
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■ Base Clock Dividing Setting Register 1 (DIVR1)
Figure 3.13-9 shows the bit configuration of the base clock dividing setting register 1 (DIVR1)
Figure 3.13-9 Bit Configuration of the Base Clock Dividing Setting Register 1 (DIVR1)
Address: 00000487H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
T3
T2
T1
T0




R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B (INIT)
XXXXXXXX
B (RST)
R/W
R/W: Readable/writable
The base clock dividing setting register 1 (DIVR1) is the register that controls the dividing ratio of each
internal clock to the base clock. This register sets the dividing ratio of the clock (CLKT) for external
expanded bus interface. The upper limit of the operable frequency is defined for each clock. Be cautious,
that if setting is done as it exceeds the upper limit frequency, by the combination of the source clock
selection, PLL frequency multiplication coefficient setting, and dividing ratio setting, the operation is not
assured.
Be cautious not to reverse the order with setting of source clock selection change.
When there is a change of the setting for this register, the changed dividing ratio becomes valid from the
next clock rate after setting.
[bit7 to bit4] T3, T2, T1, T0 (clkT divide select 3-0)
These bits are the bits for setting the clock dividing ratio of the external bus clock (CLKT). These bits
set the clock dividing ratio of the clock (CLKT) for the external extended bus interface. By the value
written in these bits, select the dividing ratio (clock frequency) of the clock for the external extended
bus interface to the base clock, from the 16 kinds shown in the Table 3.13-23.
Table 3.13-23 shows the setting of the clock dividing ratio (external bus clock).
Table 3.13-23 Setting of the Clock Dividing Ratio (External Bus Clock)
Clock dividing ratio
Clock frequency: Source oscillation 12.5 MHz
and PLL multiplication by four
T3
T2
T1
T0
0
0
0
0

50.0 MHz (initial value)
0
0
0
1
×2 (divided by two)
25.0 MHz
0
0
1
0
×3 (divided by three)
16.7 MHz
0
0
1
1
×4 (divided by four)
12.5 MHz
0
1
0
0
×5 (divided by five)
10.0 MHz
0
1
0
1
×6 (divided by six)
8.3 MHz
0
1
1
0
×7 (divided by seven)
7.1 MHz
0
1
1
1
×8 (divided by eight)
6.25 MHz






1
1
1
1
×16 (divided by sixteen)
3.125 MHz
: Time period of the system base clock.
• Read and write are possible.
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[bit3 to bit0]  (Reserved bits)
These are reserved bits.
Note:
As the upper limit of the operable frequency is 50 MHz, set the dividing ratio not to over this
frequency.
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3.13.7
Peripheral Circuits Provided for Clock Control Section
In this section, the function of the peripheral circuits that the clock control section has
is explained.
■ Time-Base Counter
In the clock control section, there is the time-base counter of 26-bit length, and it works by the system base
clock.
The time-base counter is used for measuring of the oscillation stabilization waiting time, and it is also used
for the purposes shown below. (For the details of the oscillation stabilization waiting time, refer to "3.12.4
Oscillation Stabilization Waiting Time".)
• Watchdog timer
This is the watchdog timer for detection of the system hang-up and measures using the bit output of the
time-base counter.
• Time-base timer
Using the time-base counter output, it generates interval interrupt.
These functions are explained below.
● Watchdog timer
The watchdog timer is the timer for hang-up detection using the output of the time-base counter. When the
generation postponement operation of the watchdog reset is not done in the specified the interval, caused by
hang-up of the program, the setting initialization reset (INIT) request is generated as the watchdog reset.
[Activation and setting of the time period for the watchdog timer]
The watchdog timer is activated by the first writing operation into the reset factor register/watchdog
timer control register (RSRR) after reset (RST).
In this time, the interval time of the watchdog timer is set by the bit9 and bit8 (WT1, WT0 bits). For
setting of the interval time, only the time that is set by this first writing is valid, and all the writings
after it is neglected.
[Generation postponement of the watchdog reset]
Once the watchdog timer is activated, it is necessary to write the data "A5H", "5AH" orderly into the
watchdog reset generation postponement register (WPR) by the program periodically.
The flag for the watchdog reset generation is initialized by this operation.
[Generation of the watchdog reset]
The flag for the watchdog reset generation is set by the falling edge of the time-base counter output of
the specified interval. If the flag is set at the time of the second falling edge detection, the setting
initialization reset (INIT) request is generated as the watchdog reset.
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[Stop of the watchdog timer]
Once the watchdog timer is activated, it cannot be stopped until the operation initialization reset (RST)
is generated.
In the following states that generate the operation initialization reset (RST), the watchdog timer stops
and it does not work until it is activated by the program again.
• Operation initialization reset (RST) state
• Setting initialization reset (INIT) state
• Oscillation stabilization waiting reset (RST) state
[Temporary stop of the watchdog timer (postponement of automatic generation)]
When the program operation of the CPU is in stop, the watchdog timer initializes the watchdog reset
generation flag once and postpones the generation of the watchdog reset. Specifically, the program
operation stops are the following operations.
• Sleep state
• Stop state
• Oscillation stabilization waiting RUN state
• In process of break when emulator debugger or monitor debugger is used
• Period between INTE instruction execution and RETI instruction execution
• Step trace trap (break for each instruction by the T flag of PS register=1)
• In process of data access to the instruction cache control register (ISIZE, ICHCR) or to the cache
memory in RAM mode
In addition, when the time-base counter is cleared, the flag for the watchdog reset generation is also
initialized at the same time, and the watchdog reset generation is postponed.
And if the above states occur by the system hang-up, there is a possibility that the watchdog reset does
not generate. In that case, do reset (INIT) from the external INIT pin.
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■ Time-Base Timer
The time-base timer is the timer for interval interrupt generation, using the time-base counter output. It is
suitable for the time measuring of relatively long time till "base clock × 227" cycles as maximum, such as
the PLL lock waiting time or the oscillation stabilization waiting time of the sub clock.
When it detects the falling edge of output for the time-base counter corresponding to the specified interval,
it generates the time-base timer interrupt request.
[Activation of the time-base timer and setting of the interval]
The time-base timer sets the interval time by the bit13 to bit11 (TBC2, TBC1, TBC0 bits) of the timebase counter control register (TBCR). As the falling edge of the output for the time-base counter
corresponding to the specified interval is always being detected, after setting of the interval time, clear
the bit15 (TBIF bit) in the first place, set "1" in the bit14 (TBIE bit), and then enable the interrupt
request output.
When changing the interval time, set "0" in the bit14 (TBIE bit) in advance to disable the interrupt
request output.
As the time-base counter is doing count operation constantly without being affected by these settings,
clear the time-base counter before enabling the interrupt to get accurate interval interrupt time. If it is
not cleared, there is a case that the interrupt request occurs just after enabling the interrupt.
[Clear the time-base counter by the program]
When the data "A5H", "5AH" are written orderly in the time-base counter clear register (CTBR), all the
bits of the time-base counter are cleared to "0" right after writing "5AH". Although there is not any
restriction for the time between "A5H" writing and "5AH" writing when data other than "5AH" is written
after "A5H" writing, clear operation is not done even if "5AH" is written unless "A5H" is written again.
By clearing this time-base counter, the flag for the watchdog reset generation is also initialized at the
same time, and the generation of the watchdog reset is postponed once.
[Clear the time-base counter by the device state]
When the device state changes as shown below, all the bits of the time-base counter are cleared to "0"
simultaneously.
• Stop state
• Setting initialization reset (INIT) state
Especially, in case of the stop state, as the time-base counter is used for measuring the oscillation
stabilization waiting time, there is a case that the interval interrupts of the time-base timer occurs
unexpectedly. Therefore before setting the stop mode, disable the time-base timer interrupt and do not
use the time-base timer.
For other states, as operation initialization reset (RST) occurs, the time-base timer interrupt is
automatically disabled.
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3.13.8
MB91345 Series
Smooth Activation and Stop of the Clock
The method for suppressing the internal voltage effect or voltage surge is explained.
■ Smooth Activation and Stop of the Clock
For suppressing the internal voltage effect or voltage surge, the internal voltage fluctuation is significantly
suppressed by connecting bypass capacitor of around 4.7 µF on the C pin. In addition, when changing all
clocks (CPU and internal bus clock (CLKB), the external bus clock (CLKT), the peripheral circuits and the
peripheral bus clock (CLKP)), switch from low frequency to the target frequency step by step and do not
switch it abruptly.
When returning to the operation of low frequency, also do it step by step and do activation and shutdown of
the clock as shown below.
When switching from the high frequency operation to the low frequency operation, do it as the same way.
● Activation
1) Enable PLL operation (Set "1" in the PLL1EN bit of the clock source control register (CLKR).)
2) Oscillation stabilization waiting time
3) Divide CLKB, CLKT and CLKP by 16. (Set DIVR0, DIVR1 registers.)
4) Set the PLL frequency multiplication coefficient and switch X0 to PLL side. (Set the clock source
control register (CLKR).)
5) Decrease the dividing ratio of CLKB, CLKT, CLKP step by step. Waiting loop is inserted between
dividing steps.
● Shut down
1) Divide CLKB, CLKT, CLKP step by step (The number of step depends on the setting of the frequency.)
to the maximum dividing coefficient, and insert waiting loop between dividing steps.
(Set the registers DIVR0, DIVR1.)
2) Switch from the PLL to the source oscillation of X0/X1. (Set the clock source control register (CLKR).)
3) Disable the PLL. (Set "0" in the PLL1EN bit of the to the clock source control register (CLKR).)
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■ Program Example for Smooth Activation and Stop of the Clock
● Activation procedure
#macro wait_loop loop_number
#local _wait64_loop
ldi
#loop_number,r0
_wait64_loop:
add
#-1,r0
bne
_wait64_loop
#endm
smooth_up_start3:
ldi #_DIVR0,r1
// Dividing register for CLKB and CLKP
ldi #_DIVR1,r2
// Dividing register for CLKT
ldi #_CLKR,r3
// CLKR register
ldi #0xff,r4
ldi #0x11,r5
ldi #0x33,r6
ldi #0x77,r7
ldi #0x01,r8
ldi #0x34,r12
ldi #0x36,r13
nop
nop
nop
// PLL  X0 PLL operation is enabled
stb r12,@r3
//Divides CLKB, CLKT, CLKP by 16
stb
r4,@r1
// CLKB, CLKP dividing by 16
stb
r4,@r2
// CLKT dividing by 16
wait_loop 4
// Switches X0 to PLL side.
stb r13,@r3
wait_loop 4
//Decreases the dividing ratio of CLKB, CLKP step by step.
// CLKB, CLKP dividing by 16  dividing by 8
stb r7,@r1
wait_loop 8
// CLKB, CLKP dividing by 8  dividing by 4
stb r6,@r1
wait_loop 8
// CLKB, CLKP dividing by 4  dividing by 2
stb r5,@r1
wait_loop 16
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stb r8,@r1
MB91345 Series
// CLKB dividing by 2  no dividing, CLKP dividing by 2 
// dividing by 2
wait_loop 16
//Decreases the dividing ratio of CLKT step by step.
stb r7,@r2
// CLKT dividing by 16  dividing by 8
wait_loop 8
stb r6,@r2
// CLKT dividing by 8  dividing by 4
wait_loop 8
stb r5,@r2
// CLKT dividing by 4 dividing by 2
wait_loop 16
stb r8,@r2
// CLKT no dividing
wait_loop 16
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● Shut down procedure
#macro wait_loop loop_number
#local _wait64_loop
ldi
#loop_number,r0
_wait64_loop:
add
#-1,r0
bne
_wait64_loop
#endm
smooth_down_start3:
ldi
#_DIVR0,r1
// Dividing register for CLKB and CLKP
ldi #_DIVR1,r2
// Dividing register for CLKT
ldi #_CLKR,r3
// CLKR register
ldi #0x11,r5
ldi #0x3f,r6
ldi #0xff,r8
ldi #0x04,r9
ldi #0x33,r10
ldi #0xff,r12
ldi #0x00,r13
ldi #0x1f,r14
nop
nop
nop
//Increases the dividing ratio of CLKT step by step.
// CLKT no dividingdividing by 2
stb r14,@r2
wait_loop 16
// CLKT dividing by 2dividing by 4
stb r6,@r2
wait_loop 8
// CLKT dividing by 4dividing by 16
stb r8,@r2
wait_loop 4
//Increases the dividing ratio of CLKB, CLKP step by step.
// CLKB no dividingdividing by 2, CLKP dividing by 2
// dividing by 2
stb r5,@r1
wait_loop 16
stb r10,@r1
// CLKB, CLKP dividing by 2dividing by 4
wait_loop 8
stb r12,@r1
// CLKB, CLKP dividing by 4dividing by 16
wait_loop 4
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//Decreases the multiplication coefficient of the PLL step by step.
stb r9,@r3
// Switches from the PLL to the source oscillation of X0/X1
stb r13,@r3
// PLL off
nop
nop
nop
ret
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CHAPTER 3 CPU and Control Section
3.14 Device Status Control
MB91345 Series
3.14
Device Status Control
In this section, various kind of status and its control, and low power consumption mode
of the FR family are explained.
■ Device Status
The operation statuses of the FR family are shown below.
The details of these are explained in the "3.14.1 Device Status and Various Transitions".
• RUN status (Normal operation)
• Sleep status
• Stop status
• Oscillation stabilization waiting RUN status
• Oscillation stabilization waiting reset (RST) status
• Operation initialization reset (RST) status
• Setting initialization reset (INIT) status
■ Low Power Consumption Modes
There are two low power consumption modes shown below.
The details of these are explained in the "3.14.2 Low Power Consumption Modes".
• Sleep mode
• Stop mode
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■ Device Status and Various Transitions
Transition of the device status in MB91345 series is shown below.
Figure 3.14-1 Transition of Device Status in MB91345 Series
1
2
3
4
5
6
7
8
9
10
11
INIT pin=0 (INIT)
INIT pin=1 (INIT cancellation)
End of oscillation stabilization waiting
Reset (RST) cancellation
Software reset (RST)
Sleep (instruction writing)
Stop (instruction writing)
Interrupt
External interrupt that does not require the clock
Watchdog reset (INIT)
Stop (instruction writing) without oscillation stop
Strongest
Power on
1
Weakest
Order of priority for the transition request
Setting initialization reset (INIT)
End of oscillation stabilization waiting
Operation initialization reset (RST)
Interrupt request
Stop
Sleep
Setting initialization
(INIT)
2
1
Stop
(without oscillation stop)
1
Stop
(with oscillation stop)
9
1
Oscillation stabilization
waiting RUN
11
Main oscillation
stabilization waiting reset
9
1
3
7
Program reset
(RST)
3
5
1
6
Sleep
RUN
1
4
10
1
8
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3.14 Device Status Control
MB91345 Series
3.14.1
Device Status and Various Transitions
In this section, operation status of the device and the transitions between various
operation statuses are explained.
■ RUN Status (Normal Operation)
This status is the program execution status. All internal clocks are supplied and all circuits are in the
operable status.
But only for the 16-bit peripheral (peripheral) bus, only the bus clock is halting during it is not accessed.
In this status, the request of various transitions is accepted, but in case the synchronous reset mode is
selected, the status transition operation for some requests is different from that of the normal reset mode.
For details, refer to "■ Synchronous reset operation" in "3.12.5 Reset Operation Mode".
■ Sleep Status
This status is the state that the program is halting. Transition to this status is made by the program
operation.
This is the status that only the program execution of the CPU stops, and the peripheral circuits are operable.
Various embedded memory and the internal bus are under the stop status unless the DMA controller
requests.
• By the occurrence of valid interrupt request, this status is cancelled and moves to the RUN state (normal
operation).
• By the occurrence of setting initialization reset (INIT) request, it moves to the status of the setting
initialization reset (INIT).
• By the occurrence of operation initialization reset (RST) request, it moves to the status of operation
initialization reset (RST).
■ Stop Status
This status is the state that the device is halting. Transition to this status is made by the program operation.
All the internal circuits stop. All internal clocks stop, and the oscillation circuits and the PLL can be
stopped by the setting. Before moving to the stop status, be sure to set PLL1EN=0. In addition, by the
setting, it is possible to make the external pins in high impedance uniformly (except some pins).
• By the occurrence of specific (which doses not require the clock) valid interrupt request, it moves to the
status of oscillation stabilization waiting RUN.
• By the occurrence of the setting initialization reset (INIT) request, it moves to the state of the setting
initialization reset (INIT).
• By the occurrence of operation initialization reset (RST) request, it moves to the oscillation stabilization
waiting reset (RST).
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■ Oscillation Stabilization Waiting RUN Status
This status is the state that the device is halting. Transition to this status is made after returning from the
stop status.
All internal circuits except the clock generation control section (the time-base counter and the device status
control section) stop. All internal clocks stop, but the oscillation circuit and the PLL which operation was
enabled are operating.
• The high impedance control of the external pin in the stop status and other status is cancelled.
• By the time elapse of the specified oscillation stabilization waiting time, it moves to the RUN status
(normal operation).
• By the occurrence of the setting initialization reset (INIT) request, it moves to the setting initialization
reset (INIT) status.
• By the occurrence of the operation initialization reset (RST) request, it moves to the oscillation
stabilization waiting reset (RST) status.
■ Oscillation Stabilization Waiting Reset (RST) Status
This status is the state that the device is halting. Transition to this status is made after returning from the
stop status or the setting initialization reset (INIT) status. All internal circuits except the clock generation
control section (the time-base counter and the device status control section) stop. All internal clocks stop,
but the oscillation circuit and the PLL which operation was enabled are operating.
• The high impedance control of the external pin in the stop status and other status is cancelled.
• It outputs the operation initialization reset (RST) to the internal circuits.
• By the time elapse of the specified oscillation stabilization waiting time, it moves to the oscillation
stabilization waiting reset (RST) status.
• By the occurrence of the setting initialization reset (INIT) request, it moves to the setting initialization
reset (INIT) status.
■ Operation Initialization Reset (RST) Status
This status is the state that the program is initialized. Transition to this status is made by the acceptance of
the operation initialization reset (RST) request or by the ending of oscillation stabilization waiting reset
(RST) status.
Program execution of the CPU stops and the program counter is initialized. The peripheral circuits except
some of them are initialized. All internal clocks and the oscillation circuit, and the PLL which operation
was enabled are operating.
• Operation initialization reset (RST) is output to the internal circuits.
• By the cancellation of the operation initialization reset (RST) request, transition to the RUN status
(normal operation) is made, and the operation initialization reset sequence is executed. In case after
returning from the setting initialization reset (INIT) status, the setting initialization reset sequence is
executed.
• By the occurrence of the setting initialization reset (INIT) request, it moves to the setting initialization
reset (INIT) status.
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■ Setting Initialization Reset (INIT) Status
This status is the state that all settings are initialized. Transition to this status is made by the setting
initialization reset (INIT) request.
Program execution of the CPU stops and the program counter is initialized. All peripheral circuits are
initialized. The oscillation circuits run, but the PLL operation stops. All internal clocks stop during "L"
level input is supplied on the external INIT pin, but it runs other than that case.
• It outputs the setting initialization reset (INIT) and the operation initialization reset (RST) to the internal
circuits.
• By the cancellation of the setting initialization reset (INIT) request, this status is cancelled, and
transition to the oscillation stabilization waiting reset (RST) status is made. After that, going through the
operation initialization reset (RST) status, the setting initialization reset sequence is executed.
■ Order of the Priority for Various Status Transition Requests
In every status, various status transition requests follow the order of the priority shown below. But some of
the requests occur in the special status, those are valid only in that status.
[Strongest] Setting initialization reset (INIT) request

Ending of the oscillation stabilization waiting time (Only occurs in the oscillation
stabilization waiting reset status and the oscillation stabilization waiting RUN status.)

Operation initialization reset (RST) request

Valid interrupt request (Only occurs in RUN, sleep, and stop status.)

Stop mode request (register writing) (Only occurs in RUN status.)
[Weakest] Sleep mode request (register writing) (Only occurs in RUN status.)
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3.14.2
MB91345 Series
Low Power Consumption Modes
In the status of the FR family devices, various low power consumption modes and the
way of their use are explained.
■ Low Power Consumption Modes
Low power consumption modes of the FR family are shown below.
• Sleep mode : By writing in the register, it moves the device to the sleep status.
• Stop mode : By writing in the register, it moves the device to the stop status.
For each mode, explanation is shown below.
■ Sleep Mode
When "1" is written in the bit6 (SLEEP bit) of the standby control register (STCR), it comes into the sleep
mode and it moves to the sleep status. After this, the sleep status is held until the factor of returning from
the sleep status occurs.
In case "1" is written both in the bit7 (STOP bit) and in this bit of the standby control register (STCR), the
bit7 (STOP bit) has a priority and it moves to the stop status.
For sleep status, refer to "■ Sleep status" in "3.14.1 Device Status and Various Transitions" too.
[Transition to the sleep mode]
In case moving into the sleep mode, use the synchronous standby mode (set by the bit8:SYNCS bit of
the TBCR), then the following sequence must be used.
(LDI #value_of_sleep,R0) ; value_of_sleep is write data to STCR
(LDI #_STCR,R12)
; _STCR is the address (481H) of STCR
STB
; Writes into standby control register (STCR)
R0,@R12
LDUB @R12,R0
; STCR read for synchronous standby
LDUB @R12,R0
; Dummy read STCR again
NOP
; NOP × 5 for timing adjustment
NOP
NOP
NOP
NOP
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● Circuits that stop in the sleep status
• Program execution of the CPU
• Bit search module (It operates when DMA transfer occurs.)
• Various embedded memory (It operates when DMA transfer occurs.)
• Internal bus (It operates when DMA transfer occurs.)
● Circuits that do not stop in the sleep status
• Oscillator circuit
• Operation enabled PLL
• Clock generation control section
• Interrupt controller
• Peripheral circuits
• DMA controller
● Returning factors from sleep status
• Occurrence of valid interrupt request
When an interrupt request occurs in case the setting of the ICR register is not "11111B", the sleep mode
is cancelled, and moves to the RUN status (normal operation). In case the setting of the ICR register is
"11111B", the sleep mode is not cancelled even if an interrupt request occurs,
• Occurrence of the setting initialization reset (INIT) request
When the setting initialization reset (INIT) request occurs, it moves to the setting initialization reset
(INIT) status unconditionally.
• Occurrence of the operation initialization reset (RST) request
When the operation initialization reset (RST) request occurs, it moves to the operation initialization
reset (RST) status unconditionally.
For the order of priority for various factors, refer to "■ Order of priority of various status transition
requests" in "3.14.1 Device Status and Various Transitions".
● Synchronous standby operation
In case "1" is set in the bit8 (SYNCS bit) of the time-base counter control register (TBCR), the
synchronous standby operation is enabled. In this case, it does not move to the sleep status only by writing
into sleep bit.
It moves to the sleep status after reading the STCR register.
For using the sleep mode, the sequence in [Transition to the sleep mode] must be used.
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■ Stop Mode
When "1" is written in the bit7 (STOP bit) of the standby control register (STCR), it comes into the stop
mode and it moves to the stop status. After that, the stop status is held until the returning cause from the
stop status occurs.
When "1" is written to both bit6 (SLEEP bit) and this bit of the standby control register (STCR), the bit7
(STOP bit) has a priority and moves to the stop status.
For the stop status, also refer to "■ Stop status" in "3.14.1 Device Status and Various Transitions".
[Transition to the stop mode]
In case moving into the stop mode, use the synchronous standby mode (set by the bit8:SYNCS bit of
the TBCR), then the following sequence must be used.
(LDI #value_of_stop,R0)
; value_of_stop is write data to STCR
(LDI #_STCR,R12)
; _STCR is the address (481H) of STCR
STB
; Writes into standby control register (STCR)
R0,@R12
LDUB @R12,R0
; STCR read for synchronous standby
LDUB @R12,R0
; Dummy read STCR again
NOP
; NOP × 5 for timing adjustment
NOP
NOP
NOP
NOP
● Circuits that stop in the stop status
• Oscillator circuits that are set to stop
In case "1" is set in the bit0 (OSCD1 bit) of the standby control register (STCR), it makes the oscillator
circuit in the stop status, which is for the main clock, into the state of stop.
• PLL which is disabled the operation or connected to the oscillator circuit that is set to stop.
In case "1" is set in the bit0 (OSCD1 bit) of the standby control register (STCR) and even if "1" is set in
the bit10 (PLL1EN bit) of the clock source control register (CLKR), it makes the PLL in the stop status,
which is for the main clock, into the state of stop.
• All the internal circuits except "Circuits that do not stop in the stop status" shown below.
● Circuits that do not stop in the stop status
• Oscillator circuit that is not set to stop
When "0" is set in the bit0 (OSCD1 bit) of the standby control register (STCR), the oscillator circuit in
the stop status, which is for the main clock, does not stop.
• PLL which is enabled the operation and connected to the oscillator circuit that is not set to stop.
When "0" is set in the bit0 (OSCD1 bit) of the standby control register (STCR), and when "1" is set in
the bit10 (PLL1EN bit) of the clock source control register (CLKR), the PLL in the stop status, which is
for the main clock, does not stop.
● High impedance control of pin in the stop status
• When "1" is set in the bit5 (HIZ bit) of the standby control register (STCR), it makes the pin output in
the stop status to the high impedance status. For the pins which are subject to this control, refer to
"APPENDIX C Pin Status List".
• When "0" is set in the bit5 (HIZ bit) of the standby control register (STCR), the pin output in the stop
status holds the value before transition to the stop status. For details, refer to "APPENDIX C Pin Status
List".
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● Returning factors from the stop status
• Occurrence of the specific (not requires the clock) valid interrupt request
The external interrupt input pins (INT0 to INT7 pins) are valid. In case the setting of the ICR register is
not "11111B" and when an interrupt request occurs, the stop mode is cancelled and it moves to the RUN
status (normal operation). In case the setting of the ICR register is "11111B" and when an interrupt
request occurs, the stop mode is not cancelled.
• Occurrence of the setting initialization reset (INIT) request
When the setting initialization reset (INIT) request occurs, it unconditionally moves to the setting
initialization reset (INIT) status.
For the order of the priority for various factors, refer to "■ Order of the priority of various status transition
requests" in "3.14.1 Device Status and Various Transitions".
● Clock source selection in the stop mode
In case the autodyne oscillation mode, before selecting the stop mode, set the source clock as the main
clock dividing by two in advance. For details, refer to "3.13 Clock Generation Control", especially "3.13.1
PLL Control".
In addition, for setting of the dividing ratio, the restrictions are same as for the normal operation.
● Synchronous standby operation
When "1" is set in the bit8 (SYNCS bit) of the time-base counter control register (TBCR), synchronous
standby operation is enabled. In this case, it does not move to the sleep status by only writing in the SLEEP
bit.
After that, it moves to the sleep status by reading the STCR register.
When using the sleep mode, the sequence in the [Transition to the sleep mode] must be used.
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MB91345 Series
CM71-10132-3E
CHAPTER 4
I/O Port
This chapter describes the overview, the register
configuration, and the function of I/O port.
4.1 Overview of I/O Port
4.2 Port Data Register (PDR0 to PDRE)
4.3 Data Direction Register (DDR0 to DDRE)
4.4 Port Function Register (PFR0 to PFRE)/ Extended Port Function
Register (EPFR0 to EPFRE)
4.5 Pull-up Control Register (PCR0 to PCRE)
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4.1 Overview of I/O Port
4.1
MB91345 Series
Overview of I/O Port
In MB91345 series, when the peripheral corresponding to each pin is set not to use
these pins as input/output, these pins can be used as I/O ports.
■ Basic Block Diagram of Port
The I/O port consists of the following registers.
• Port data register (PDR)
• Data direction register (DDR)
• Port function register (PFR)
• Extension port function register (EPFR)
• Pull-up control register (PCR)
The basic port configuration is given in the Figure 4.1-2.
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4.1 Overview of I/O Port
MB91345 Series
Figure 4.1-1 Block diagram of I/O port
R-bus
CMOS
Schmitt
Stop Hi-Z
Peripheral input
0
Reading from PDR
1
33kΩ
*
PCR
Peripheral output
Output
Peripheral output
1
Pull-up
control
0
Output
driver
Pin
MUX
PDR
DDR
PFR
Port
direction
control
EPFR
*: The port where pull-up can be controlled is P07 to P00, P17 to P10, P55 to P50, P63 to P60,
PC2 to PC0, PD7 to PD0, and PE7 to PE0.
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4.1 Overview of I/O Port
MB91345 Series
Figure 4.1-2 Block diagram of analog input I/O port.
R-bus
Analog input*1
*1
ADER
Stop Hi-Z
Peripheral input
CMOS
Schmitt
0
Reading from PDR
1
33kΩ
*2
PCR
1
Pull-up
control
Peripheral output
Output
Peripheral output
MUX
0
Output
driver
Pin
PDR
DDR
PFR
Port
direction
control
EPFR
*1: Dual usable port for analog input is PD7 to PD0 and PE7 to PE0.
*2: The port where pull-up can be controlled is P07 to P00, P17 to P10, P55 to P50, P63 to P60,
PC2 to PC0, PD7 to PD0, and PE7 to PE0.
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4.1 Overview of I/O Port
MB91345 Series
■ General Specification of Port
• Each port has the port data register (PDR) and it stores the output data. PDR registers are not initialized
even after resetting.
• Each port has the port direction register (DDR) and it switches the port I/O direction. All ports are
turned to input after resetting. (DDR=00H)
- Port input mode (PFR=0 & EPFR=0 & DDR=0)
PDR read
: The level of the corresponding external pin is read.
PDR write
: A setting value is written to PDR.
- Port output mode (PFR=0 & EPFR=0 & DDR=1)
PDR read
: The PDR value is read.
PDR write
: A setting value is written to PDR and the value is output to the corresponding
external pin.
- Peripheral output mode (Settings other than PFR=0 & EPFR=0)
PDR read
: The peripheral output value is read when DDR=0.
The PDR value is read when DDR=1.
PDR write
: A setting value is written to PDR.
- Regardless of the port state, the setting value of the register is read when a read modify write (RMW)
command to PDR.
- The peripheral input is always connected to the pin except in special circumstances. Use port input
mode to input to peripheral under normal conditions.
• The pull-up control register can be set pull-up of 33 k.
(P07 to P00, P17 to P10, P55 to P50, P63 to P60, PC2 to PC0, PD7 to PD0, PE7 to PE0)
• All ports have the port function register (PFR) and additionally some have the extended port function
register (EPFR). They mainly control the output of the peripheral.
• Inputs are fixed to "0" in STOP mode. However, when the corresponding interruptions are valid (input
pin selection by ENIR bit setting and PFR, EPFR, DDR), external interrupting inputs are not fixed and
inputs to pins can be used as interruptions.
• A bidirectional signal of the peripheral (I2C function SOT and SCK of UART) is valid for PFR. For
switching the bidirectional signal, see the corresponding peripheral chapter.
• For the analog input multiplexed port, analog input becomes available if you set to the port input and then
set the corresponding bit in the ADER. The initial value of the ADER is set to the analog input. If you
want to use the function other than the analog input, cleat the corresponding bits in the ADER register.
Note:
There is no register switched between general-purpose port input and peripheral input.
The value input via an external pin is always passed to the general-purpose port and peripheral
circuit.
Even with the DDR output setting, the value output to the outside is always propagated to the
general-purpose port peripheral circuit.
For use as a peripheral input, DDR input and enable each peripheral’s input signal.
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4.2 Port Data Register (PDR0 to PDRE)
4.2
MB91345 Series
Port Data Register (PDR0 to PDRE)
This section describes function and configuration of the port data register (PDR0 to
PDRE).
Each port has the port data register (PDR0 to PDRE) and it stores the output data. PDR registers are not
initialized even after resetting.
■ Configuration of the Port Data Register (PDR0 to PDRE)
The configuration of Port Data Register (PDR0 to PDRE) is shown in Figure 4.2-1.
Figure 4.2-1 Bit Configuration of Port Data Register (PDR0 to PDRE)
Address
bit7
bit6
000000H PDR07 PDR06
000001H PDR17 PDR16
000002H PDR27 PDR26
000003H PDR37 PDR36
000004H PDR47 PDR46
000005H PDR57 PDR56
000006H


00000CH


00000DH PDRD7 PDRD6
00000EH PDRE7 PDRE6
R/W
R/W
R/W: Readable/writable
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDRC
PDRD
PDRE
bit5
PDR05
PDR15
PDR25
PDR35
PDR45
PDR55


PDRD5
PDRE5
R/W
bit4
PDR04
PDR14
PDR24
PDR34
PDR44
PDR54


PDRD4
PDRE4
R/W
bit3
PDR03
PDR13
PDR23
PDR33
PDR43
PDR53
PDR63

PDRD3
PDRE3
R/W
bit2
PDR02
PDR12
PDR22
PDR32
PDR42
PDR52
PDR62
PDRC2
PDRD2
PDRE2
R/W
bit1
PDR01
PDR11
PDR21
PDR31
PDR41
PDR51
PDR61
PDRC1
PDRD1
PDRE1
R/W
bit0
PDR00
PDR10
PDR20
PDR30
PDR40
PDR50
PDR60
PDRC0
PDRD0
PDRE0
R/W
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
----XXXXB
-----XXXB
XXXXXXXXB
XXXXXXXXB
PDR0 to PDR6 and PDRC to PDRE are I/O data registers of the I/O port.
The corresponding DDR0 to DDR6 and DDRC to DDRE control I/O.
Regardless of the port state, the setting value of the register is read when a read modify write (RMW)
command to PDR.
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4.3 Data Direction Register (DDR0 to DDRE)
MB91345 Series
4.3
Data Direction Register (DDR0 to DDRE)
This section describes function and configuration of the data direction register.
■ Configuration of the Data Direction Register (DDR0 to DDRE)
The configuration of Data Direction Register (DDR0 to DDRE) is shown in Figure 4.3-1.
Figure 4.3-1 Bit Configuration of Data Direction Register (DDR0 to DDRE)
bit7
DDR07
DDR17
DDR27
DDR37
DDR47
DDR57


DDRD7
DDRE7
R/W
R/W: Readable/writable
DDR0
DDR1
DDR2
DDR3
DDR4
DDR5
DDR6
DDRC
DDRD
DDRE
Address
000400H
000401H
000402H
000403H
000404H
000405H
000406H
00040CH
00040DH
00040EH
bit6
DDR06
DDR16
DDR26
DDR36
DDR46
DDR56


DDRD6
DDRE6
R/W
bit5
DDR05
DDR15
DDR25
DDR35
DDR45
DDR55


DDRD5
DDRE5
R/W
bit4
DDR04
DDR14
DDR24
DDR34
DDR44
DDR54


DDRD4
DDRE4
R/W
bit3
DDR03
DDR13
DDR23
DDR33
DDR43
DDR53
DDR63

DDRD3
DDRE3
R/W
bit2
DDR02
DDR12
DDR22
DDR32
DDR42
DDR52
DDR62
DDRC2
DDRD2
DDRE2
R/W
bit1
DDR01
DDR11
DDR21
DDR31
DDR41
DDR51
DDR61
DDRC1
DDRD1
DDRE1
R/W
bit0
DDR00
DDR10
DDR20
DDR30
DDR40
DDR50
DDR60
DDRC0
DDRD0
DDRE0
R/W
Initial value
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
----0000B
-----000B
00000000B
00000000B
Each port has the port direction register (DDR) and it switches the port I/O direction. All ports are turned to
input after resetting. (DDR=00H)
- Port input mode (PFR=0 & EPFR=0 & DDR=0)
PDR read: The level of the corresponding external pin is read.
PDR write: A setting value is written to PDR.
- Port output mode (PFR=0 & EPFR=0 & DDR=1)
PDR read: The PDR value is read.
PDR write: A setting value is written to PDR and the value is output to the corresponding external
pin.
- Peripheral output mode (PFR=1)
PDR read: The corresponding peripheral output value is read.
PDR write: A setting value is written to PDR.
- The peripheral input is always connected to the pin except in special circumstances. Use port input
mode to input to peripheral under normal conditions.
CM71-10132-3E
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CHAPTER 4 I/O Port
4.4 Port Function Register (PFR0 to PFRE)/ Extended Port
Function Register (EPFR0 to EPFRE)
4.4
MB91345 Series
Port Function Register (PFR0 to PFRE)/
Extended Port Function Register (EPFR0 to EPFRE)
This section describes function of the port function register (PFR0 to PFRE) and
Extended port function register (EPFR0 to EPFRE).
■ Port 0
Port 0 is controlled by PFR0 and EPFR0.
Port 0 is used as UART3/UART4/UART5. For selectable input signals, select the input pin on the
corresponding resources.
Figure 4.4-1 Bit Configuration of Port 0
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000420H PFR07 PFR06 PFR05 PFR04 PFR03 PFR02 PFR01 PFR00 00000000B
000520H EPFR07 EPFR06 EPFR05 EPFR04 EPFR03 EPFR02 EPFR01 EPFR00 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
PFR0
EPFR0
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CM71-10132-3E
CHAPTER 4 I/O Port
4.4 Port Function Register (PFR0 to PFRE)/ Extended Port Function
Register (EPFR0 to EPFRE)
MB91345 Series
Table 4.4-1 Bit Function Registers of Port 0
Bit
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CM71-10132-3E
PFR
EPFR
Function
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SOT5 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SCK4 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SOT4 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SCK3 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SOT3 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Setting inhibited
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CHAPTER 4 I/O Port
4.4 Port Function Register (PFR0 to PFRE)/ Extended Port
Function Register (EPFR0 to EPFRE)
MB91345 Series
■ Port 1
Port 1 is controlled by PFR1 and EPFR1.
Port 1 is used as UART5/UART6/UART7, load timer 1 or A/D converter. For selectable input signals,
select the input pin on the corresponding resources.
Figure 4.4-2 Bit Configuration of Port 1
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000421H PFR17 PFR16 PFR15 PFR14 PFR13 PFR12 PFR11 PFR10 00000000B
000521H EPFR17 EPFR16 EPFR15 EPFR14 EPFR13 EPFR12 EPFR11 EPFR10 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
PFR1
EPFR1
138
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CM71-10132-3E
CHAPTER 4 I/O Port
4.4 Port Function Register (PFR0 to PFRE)/ Extended Port Function
Register (EPFR0 to EPFRE)
MB91345 Series
Table 4.4-2 Bit Function Registers of Port 1
Bit
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CM71-10132-3E
PFR
EPFR
Function
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SCK7 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SOT7 output
1
1
Reload timer 2 TOT2 output
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SCK6 output
1
1
Reload timer 1 TOT1 output
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SOT6 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Reload timer 0 TOT0 output
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SCK5 output
1
1
Setting inhibited
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CHAPTER 4 I/O Port
4.4 Port Function Register (PFR0 to PFRE)/ Extended Port
Function Register (EPFR0 to EPFRE)
MB91345 Series
■ Port 2
Port 2 is controlled by PFR2 and EPFR2.
Port 2 is used as UART0/UART1/UART2. For selectable input signals, select the input pin on the
corresponding resources.
Figure 4.4-3 Bit Configuration of Port 2
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000422H PFR27 PFR26 PFR25 PFR24 PFR23 PFR22 PFR21 PFR20 00000000B
000522H EPFR27 EPFR26 EPFR25 EPFR24 EPFR23 EPFR22 EPFR21 EPFR20 11111111B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
PFR2
EPFR2
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CM71-10132-3E
CHAPTER 4 I/O Port
4.4 Port Function Register (PFR0 to PFRE)/ Extended Port Function
Register (EPFR0 to EPFRE)
MB91345 Series
Table 4.4-3 Bit Function Registers of Port 2
Bit
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CM71-10132-3E
PFR
EPFR
Function
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SOT2 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SCK1 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SOT1 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SCK0 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SOT0 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Setting inhibited
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CHAPTER 4 I/O Port
4.4 Port Function Register (PFR0 to PFRE)/ Extended Port
Function Register (EPFR0 to EPFRE)
MB91345 Series
■ Port 3
Port 3 is controlled by PFR3 and EPFR3.
Port 3 is used as the free-run timer, UART2, the up/down counter 0/2, reload timer 0/1/2, or input capture
4/5. For selectable input signals, select the input pin on the corresponding resources.
Figure 4.4-4 Bit Configuration of Port 3
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000423H PFR37 PFR36 PFR35 PFR34 PFR33 PFR32 PFR31 PFR30 00000000B
000523H EPFR37 EPFR36 EPFR35 EPFR34 EPFR33 EPFR32 EPFR31 EPFR30 11111111B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
PFR3
EPFR3
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CM71-10132-3E
CHAPTER 4 I/O Port
4.4 Port Function Register (PFR0 to PFRE)/ Extended Port Function
Register (EPFR0 to EPFRE)
MB91345 Series
Table 4.4-4 Bit Function Registers of Port 3
Bit
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CM71-10132-3E
PFR
EPFR
Function
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Reload timer TOT2-2 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Reload timer TOT1-2 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Reload timer TOT0-2 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SCK2 output
1
1
Setting inhibited
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CHAPTER 4 I/O Port
4.4 Port Function Register (PFR0 to PFRE)/ Extended Port
Function Register (EPFR0 to EPFRE)
MB91345 Series
■ Port 4
Port 4 is controlled by PFR4 and EPFR4.
Port 4 is used as the external interruption, PPG9/PPGB/PPGD/PPGF, or input capture 0/1/2/3. For
selectable input signals, select the input pin on the corresponding resources.
Figure 4.4-5 Bit Configuration of Port 4
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000424H PFR47 PFR46 PFR45 PFR44 PFR43 PFR42 PFR41 PFR40 00000000B
000524H EPFR47 EPFR46 EPFR45 EPFR44 EPFR43 EPFR42 EPFR41 EPFR40 11111111B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
PFR4
EPFR4
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CM71-10132-3E
CHAPTER 4 I/O Port
4.4 Port Function Register (PFR0 to PFRE)/ Extended Port Function
Register (EPFR0 to EPFRE)
MB91345 Series
Table 4.4-5 Bit Function Registers of Port 4
Bit
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CM71-10132-3E
PFR
EPFR
Function
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SCK10 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SOT10 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
PPGF output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
PPGD output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
PPGB output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
PPG9 output
1
1
Setting inhibited
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CHAPTER 4 I/O Port
4.4 Port Function Register (PFR0 to PFRE)/ Extended Port
Function Register (EPFR0 to EPFRE)
MB91345 Series
■ Port 5
Port 5 is controlled by PFR5 and EPFR5.
Port 5 is used as PPG1/PPG3/PPG5/PPG7 or output compare. For selectable input signals, select the input
pin on the corresponding resources.
Figure 4.4-6 Bit Configuration of Port 5
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000425H PFR57 PFR56 PFR55 PFR54 PFR53 PFR52 PFR51 PFR50 00000000B
000525H EPFR57 EPFR56 EPFR55 EPFR54 EPFR53 EPFR52 EPFR51 EPFR50 11111111B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
PFR5
EPFR5
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CM71-10132-3E
CHAPTER 4 I/O Port
4.4 Port Function Register (PFR0 to PFRE)/ Extended Port Function
Register (EPFR0 to EPFRE)
MB91345 Series
Table 4.4-6 Bit Function Registers of Port 5
Bit
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CM71-10132-3E
PFR
EPFR
Function
0
0
General-purpose port
0
1
Setting inhibited
1
0
OCU OUT7 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
OCU OUT6 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
OCU OUT5 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
OCU OUT4 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
PPG7 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
PPG5 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
PPG3 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
PPG1 output
1
1
Setting inhibited
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CHAPTER 4 I/O Port
4.4 Port Function Register (PFR0 to PFRE)/ Extended Port
Function Register (EPFR0 to EPFRE)
MB91345 Series
■ Port 6
Port 6 is controlled by PFR6 and EPFR6.
Port 6 is used as ADC0/ADC1 or output compare. For selectable input signals, select the input pin on the
corresponding resources.
Figure 4.4-7 Bit Configuration of Port 6
PFR6
EPFR6
Address
000426H
000526H
bit7


R/W
bit6


R/W
bit5


R/W
bit4


R/W
bit3
bit2
bit1
bit0
Initial value
PFR63 PFR62 PFR61 PFR60 ----0000B
EPFR63 EPFR62 EPFR61 EPFR60 ----1000B
R/W
R/W
R/W
R/W
R/W: Readable/writable
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CM71-10132-3E
CHAPTER 4 I/O Port
4.4 Port Function Register (PFR0 to PFRE)/ Extended Port Function
Register (EPFR0 to EPFRE)
MB91345 Series
Table 4.4-7 Bit Function Registers of Port 6
Bit
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CM71-10132-3E
PFR
EPFR
Function
0
0
Invalid
0
1
Invalid
1
0
Invalid
1
1
Invalid
0
0
Invalid
0
1
Invalid
1
0
Invalid
1
1
Invalid
0
0
Invalid
0
1
Invalid
1
0
Invalid
1
1
Invalid
0
0
Invalid
0
1
Invalid
1
0
Invalid
1
1
Invalid
0
0
General-purpose port
0
1
Setting inhibited
1
0
OCU OUT3 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
OCU OUT2 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
OCU OUT1 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
OCU OUT0 output
1
1
Setting inhibited
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CHAPTER 4 I/O Port
4.4 Port Function Register (PFR0 to PFRE)/ Extended Port
Function Register (EPFR0 to EPFRE)
MB91345 Series
■ Port C
Port C is controlled by PFRC and EPFRC.
Figure 4.4-8 Bit Configuration of Port C
Address
PFRC 00042CH
EPFRC 00052CH
bit7


R/W
R/W: Readable/writable
150
bit6


R/W
bit5


R/W
bit4


R/W
bit3


R/W
bit2
bit1
bit0
Initial value
PFRC2 PFRC1 PFRC0 -----000B
EPFRC2 EPFRC1 EPFRC0 -----000B
R/W
R/W
R/W
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 4 I/O Port
4.4 Port Function Register (PFR0 to PFRE)/ Extended Port Function
Register (EPFR0 to EPFRE)
MB91345 Series
Table 4.4-8 Bit Function Registers of Port C
Bit
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CM71-10132-3E
PFR
EPFR
Function
0
0
Invalid
0
1
Invalid
1
0
Invalid
1
1
Invalid
0
0
Invalid
0
1
Invalid
1
0
Invalid
1
1
Invalid
0
0
Invalid
0
1
Invalid
1
0
Invalid
1
1
Invalid
0
0
Invalid
0
1
Invalid
1
0
Invalid
1
1
Invalid
0
0
Invalid
0
1
Invalid
1
0
Invalid
1
1
Invalid
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SCK9 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SOT9 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Setting inhibited
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CHAPTER 4 I/O Port
4.4 Port Function Register (PFR0 to PFRE)/ Extended Port
Function Register (EPFR0 to EPFRE)
MB91345 Series
■ Port D
Port D is controlled by PFRD and EPFRD. This port serves also as the analog input for the up/down
counter 1/2/3, PPG0/PPG2/PPG3, and A/D converter. The analog input is controlled by the ADERH
register. The analog input becomes available if you set to the port input and then set the corresponding bit
in the ADERH. The initial value of the ADERH is set to the analog input. If you want to use the function
other than the analog input, cleat the corresponding bits in the ADERH register.
Figure 4.4-9 Bit Configuration of Port D
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00042DH PFRD7 PFRD6 PFRD5 PFRD4 PFRD3 PFRD2 PFRD1 PFRD0 00000000B
00052DH EPFRD7 EPFRD6 EPFRD5 EPFRD4 EPFRD3 EPFRD2 EPFRD1 EPFRD0 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
PFRD
EPFRD
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CM71-10132-3E
CHAPTER 4 I/O Port
4.4 Port Function Register (PFR0 to PFRE)/ Extended Port Function
Register (EPFR0 to EPFRE)
MB91345 Series
Table 4.4-9 Bit Function Registers of Port D
Bit
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CM71-10132-3E
PFR
EPFR
Function
0
0
General-purpose port
0
1
Setting inhibited
1
0
PPG PPG4 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
PPG PPG2 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
PPG PPG0 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Setting inhibited
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CHAPTER 4 I/O Port
4.4 Port Function Register (PFR0 to PFRE)/ Extended Port
Function Register (EPFR0 to EPFRE)
MB91345 Series
■ Port E
Port E is controlled by PFRE and EPFRE.
Port E is used as PPG6/PPG8/PPGA/PPGC/PPGE, UART8, and A/D converter analog input. The analog
input is controlled by the ADERH register. The analog input becomes available if you set to the port input
and then set the corresponding bit in the ADERH. The initial value of the ADERH is set to the analog
input. If you want to use the function other than the analog input, cleat the corresponding bits in the
ADERH register.
Figure 4.4-10 Bit Configuration of Port E
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00042EH PFRE7 PFRE6 PFRE5 PFRE4 PFRE3 PFRE2 PFRE1 PFRE0 00000000B
00052EH EPFRE7 EPFRE6 EPFRE5 EPFRE4 EPFRE3 EPFRE2 EPFRE1 EPFRE0 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
PFRE
EPFRE
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CHAPTER 4 I/O Port
4.4 Port Function Register (PFR0 to PFRE)/ Extended Port Function
Register (EPFR0 to EPFRE)
MB91345 Series
Table 4.4-10 Bit Function Registers of Port E
Bit
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CM71-10132-3E
PFR
EPFR
Function
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SCK8 I/O
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
UART SOT8 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
Setting inhibited
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
PPG PPGE output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
PPG PPGC output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
PPG PPGA output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
PPG PPG8 output
1
1
Setting inhibited
0
0
General-purpose port
0
1
Setting inhibited
1
0
PPG PPG6 output
1
1
Setting inhibited
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CHAPTER 4 I/O Port
4.5 Pull-up Control Register (PCR0 to PCRE)
4.5
MB91345 Series
Pull-up Control Register (PCR0 to PCRE)
Pins have the function to add the pull-up of 33 k. This function can be controlled by
software for each bit.
■ Pull-up Control
Pull-up function uses the port pull-up control register (PCR) to control the pull-up.
The pull-up of the pin is turned invalid automatically when:
• The port is output.
• STOP mode Hi-Z is selected.
■ Port Pull-up Control Register
Table 4.5-1 shows the setting of the port pull-up control register. A setting value for each bit is valid only
when the corresponding PCR is set.
Pull-up control can be done with ports P07 to P00, P17 to P10, P55 to P50, P63 to P60, PC2 to PC0, PD7 to
PD0, and PE7 to PE0. There are bits corresponding to these ports.
Table 4.5-1 Setting of the port pull-up control register
Port pull-up control register
Bit
PCRxy
0 (initial value)
1
No pull-up
Pull-up
Figure 4.5-1 Port Pull-up Control Register
Address
000500H
000501H
000505H
000506H
00050CH
00050DH
00050EH
bit7
PCR07
PCR0
PCR1
PCR17
PCR5

PCR6

PCRC

PCRD
PCRD7
PCRE
PCRE7
R/W
R/W: Readable/writable
156
bit6
PCR06
PCR16



PCRD6
PCRE6
R/W
bit5
PCR05
PCR15
PCR55


PCRD5
PCRE5
R/W
bit4
PCR04
PCR14
PCR54


PCRD4
PCRE4
R/W
bit3
PCR03
PCR13
PCR53
PCR63

PCRD3
PCRE3
R/W
bit2
PCR02
PCR12
PCR52
PCR62
PCRC2
PCRD2
PCRE2
R/W
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bit1
PCR01
PCR11
PCR51
PCR61
PCRC1
PCRD1
PCRE1
R/W
bit0
PCR00
PCR10
PCR50
PCR60
PCRC0
PCRD0
PCRE0
R/W
Initial value
00000000B
00000000B
--000000B
----0000B
-----000B
00000000B
00000000B
Initial value
CM71-10132-3E
CHAPTER 5
DMA Controller
(DMAC)
This chapter describes an overview, the configuration
and functions of registers, and operation of the DMA
controller (DMAC).
5.1 Overview of DMA Controller (DMAC)
5.2 DMA Controller (DMAC) Register
5.3 Operation of DMA Controller
5.4 Setting Transfer Request
5.5 Transfer Sequence
5.6 General Aspects of DMA Transfer
5.7 Operation Flowchart
5.8 Data Path
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CHAPTER 5 DMA Controller (DMAC)
5.1 Overview of DMA Controller (DMAC)
5.1
MB91345 Series
Overview of DMA Controller (DMAC)
DMAC module implements a DMA (Direct Memory Access) transfer on FR family
devices.
DMA transfers by control of this module allows various data transfer operations to be
executed at high speed with bypassing the CPU and increases the system performance.
■ Hardware Configuration
The DMAC module mainly consists of the following components:
• Independent DMA channel  5 channels
• 5-channel independent access control circuit
• 20-bit address registers (Reload specifying permitted: ch.0 to ch.3)
• 24-bit address registers (Reload specifying permitted: ch.4)
• 16-bit transfer count registers (Reload specifying permitted: one per channel)
• 4-bit block count registers (one per channel)
• Two-cycle transfer
■ Main Functions
Data transfer using DMAC module mainly consists of the following functions.
Independent data transfer can be performed over multiple channels (5 channels)
• Priority (ch.0 > ch.1 > ch.2 > ch.3 > ch.4)
• The priority can be rotated between ch.0 and ch.1.
• DMAC trigger
- Internal peripheral request
- Software request (register write)
• Transfer mode
- Burst transfer/step transfer/block transfer
- Addressing mode with a 20-bit (24-bit) address setting (increment/decrement/fixed)
(Increment/decrement width of address is fixed at ±1, 2, or 4)
- Data types: byte/halfword/word length
- Selectable single shot/reload
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5.1 Overview of DMA Controller (DMAC)
MB91345 Series
■ DMA Controller (DMAC) Register List
Figure 5.1-1 DMA Controller (DMAC) Register List
bit31
ch.0 control/status register A
DMACA0 00000200H
ch.0 control/status register B
DMACB0 00000204H
ch.1 control/status register A
DMACA1 00000208H
ch.1 control/status register B
DMACB1 0000020CH
ch.2 control/status register A
DMACA2 00000210H
ch.2 control/status register B
DMACB2 00000214H
ch.3 control/status register A
DMACA3 00000218H
ch.3 control/status register B
DMACB3 0000021CH
ch.4 control/status register A
DMACA4 00000220H
ch.4 control/status register B
DMACB4 00000224H
All-channel control register
DMACR
bit0
00000240H
ch.0 transfer source address setting register
DMASA0 00001000H
ch.0 transfer destination address setting register
DMADA0 00001004H
ch.1 transfer source address setting register
DMASA1 00001008H
ch.1transfer destination address setting register
DMADA1 0000100CH
ch.2 transfer source address setting register
DMASA2 00001010H
ch.2 transfer destination address setting register
DMADA2 00001014H
ch.3 transfer source address setting register
DMASA3 00001018H
ch.3 transfer destination address setting register
DMADA3 0000101CH
ch.4 transfer source address setting register
DMASA4 00001020H
ch.4 transfer destination address setting register
DMADA4 00001024H
bit31
bit20
bit31
bit24 bit23
bit19
bit0
bit0
: Unused bit
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CHAPTER 5 DMA Controller (DMAC)
5.1 Overview of DMA Controller (DMAC)
MB91345 Series
■ Block Diagram of DMA Controller (DMAC)
Figure 5.1-2 Block Diagram of DMA Controller (DMAC)
Counter
DMA transfer request
to bus controller
DMA trigger
selection circuit
&
Control the
request receiving
Selector
Write back
Buffer
DTC 2-step register
Input peripheral start request/stop
DTCR
Counter
DSS2 to DSS0
Buffer
To interrupt controller
IRQ4 to IRQ0
Clear peripheral interrupt
MCLREQ
ERIR,EDIR
Selector
Control
read/write
Read
Write
Priority circuit
BLK register
TYPE.MOD,WS
X-bus
Bus control block
Selector
Selector
Address
DMASA 2-step register
SADM, SASZ7 to SASZ0
SADR
DMADA 2-step register
DADM, DASZ7 to DASZ0
DADR
Write back
Counter buffer
Access
Counter buffer
DMA control
Address counter
To bus
controller
Bus control block
Status transition
circuit
Write back
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CHAPTER 5 DMA Controller (DMAC)
5.2 DMA Controller (DMAC) Register
MB91345 Series
5.2
DMA Controller (DMAC) Register
This section describes the configuration and functions of registers used for the DMA
controller (DMAC).
■ Note on Setting Register
When DMA controller is set, some bits need to be set while DMA is stopped. If they are set while DMA is
operating (transferring), normal operation is not guaranteed.
The "*" marked bits affect operations if they are set during a DMA transfer. Rewrite these bits when the
DMA transfer is stopped (disabled or halted).
If they are set while the DMA transfer is disabled (DMACR:DMAE=0 or DMACA:DENB=0), they
become effective after the DMA transfer is enabled.
If they are set while the DMA transfer is halted (DMACR:DMAH3 to DMAH0  0000B or
DMACA:PAUS=0), they become effective after the halt has been canceled.
■ DMAC - ch.0, ch.1, ch.2, ch.3, ch.4 Control/Status Register A
● [DMACA0 to DMACA4]
These registers control operations of each DMAC channel, and are provided independently for each
channel.
The function of each bit is as follows.
Figure 5.2-1 DMAC - ch.0, ch.1, ch.2, ch.3, ch.4 Control/Status Register A
bit31 bit30 bit29 bit28 bit27 bit26 bit25 bit24 bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16
DENB PAUS STRG

IS4 to IS0
BLK3 to BLK0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DTC15 to DTC0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
(Initial value: 00000000_00000000_00000000_00000000B)
R/W: Readable/writable
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5.2 DMA Controller (DMAC) Register
MB91345 Series
[bit31] DENB (Dma ENaBle): DMA operation enable bit
This bit enables or disables a DMA transfer for each transfer channel.
The activated channel starts a DMA transfer when a transfer request is generated and received.
All transfer requests for disabled channels are ignored.
When the transfer on an activated channel reaches the specified count, this bit is set to "0" and transfer
stops.
The transfer can be forced to stop by writing "0" to this bit. Be sure to stop a transfer forcibly ("0"
write) only after pausing DMA by using the PAUS bit [DMACA:bit30]. If the transfer is forced to stop
without pausing DMA, DMA can stop but the transferred data is not guaranteed. Check whether DMA
is stopped using DSS2 to DSS0 bits (DMACB:bit18 to bit16).
Table 5.2-1 DMA Operation Enable Bit
DENB
Function
0
Disable DMA operation on the corresponding channel (initial value)
1
Enable DMA operation on the corresponding channel
• If a stop request is accepted at reset: Initialized to "0".
• This bit is readable and writable.
• If the bit15:DMAE bit of DMAC all-channel control register (DMACR) disables the operation on all
channels, "1" written to this bit has no effect and the stopped state is remained. Also, if this bit
enables the operation that has been disabled by the bit15, this bit is set to "0" and the transfer is
stopped (forced stop).
[bit30] PAUS (PAUSe): Pause instruction
This bit controls pausing a DMA transfer on the corresponding channel. Once this bit has been set, the
DMA transfer is not performed until this bit cleared. (DSS bits are set to "1XXB" during DMA stopped)
If started after this bit set, the DMA transfer remains pausing.
New transfer requests are accepted while this bit is set but the transfer does not start until the bit is
cleared. (See "■ Transfer Request Acceptance and Transfer")
Table 5.2-2 Pause Instruction
PAUS
Function
0
Enable DMA operation on the corresponding channel (initial value)
1
Pause DMA operation on the corresponding channel
• When reset: Initialized to "0".
• This bit is readable and writable.
[bit29] STRG (Software TRiGger): Transfer request
This bit generates a DMA transfer request on the corresponding channel. If "1" is written to this bit, a
transfer request is generated when writing to the register is completed and the transfer on the
corresponding channel starts.
However, if the corresponding channel has not been activated, operations on this bit have no effect.
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5.2 DMA Controller (DMAC) Register
MB91345 Series
Note:
When the activation by writing to the DMAE bit occurs concurrently with the transfer request
generated by this bit, the transfer request is enabled and the transfer starts. When the transfer
request occurs concurrently with writing "1" to the PAUS bit, the transfer request is enabled
but the DMA transfer does not start until the PAUS bit is reset to "0".
Table 5.2-3 Transfer Request
STRG
Function
0
Disabled
1
DMA activation request
• When reset: Initialized to "0".
• The read value is always "0".
• Only a write value "1" is valid. "0" does not affect the operation.
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5.2 DMA Controller (DMAC) Register
MB91345 Series
[bit28 to bit24] IS4 to IS0 (Input Select)*: Transfer trigger selection
These bits select the transfer request trigger as follows. Note that the software transfer request by STRG
bit function is always valid regardless of the settings for these bits.
Table 5.2-4 Transfer Trigger Selection
IS
Function
00000B
Software transfer request only
00001B

01111B
Disabled Setting
10000B
UART0 (reception completed)
10001B
UART1 (reception completed)
10010B
UART2 (reception completed)
10011B
UART0 (transmission completed)
10100B
UART1 (transmission completed)
10101B
UART2 (transmission completed)
10110B
Disabled Setting
10111B
Disabled Setting
11000B
Reload timer ch.0
11001B
Reload timer ch.1
11010B
Reload timer ch.2
11011B
Disabled Setting
11100B
Disabled Setting
11101B
Disabled Setting
11110B
A/D Converter0
11111B
A/D Converter1
Transfer stop request
None
Yes
None
• When reset: Initialized to "00000B".
• These bits are readable and writable.
Note:
When an interrupt from a peripheral function is set as a DMA activation (IS=1XXXXB), disable the
interrupt for the selected function by using the ICR register.
Also, if the software transfer request is used to activate a DMA transfer when a DMA activation by an
interrupt from a peripheral function is enabled, the factors for the appropriate peripheral are cleared
after the transfer is completed. Since this may clear a proper transfer request, do not use the
software transfer request to start DMA when a DMA activation by an interrupt from a peripheral is
enabled.
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5.2 DMA Controller (DMAC) Register
MB91345 Series
[bit23 to bit20] (Reserved): Unused bits
• The read value is fixed to "0000B". Writing is disabled.
[bit19 to bit16] BLK3 to BLK0 (BLocK size): Block size setting
These bits specify the size of block transfer on the corresponding channel. The value set in these bits
specifies the number of words for each transfer unit (or, more exactly, the number of times that the data
range is set). Set these bits to "01H" (size 1) if the block transfer will not be performed.
Table 5.2-5 Block Size Setting
BLK
XXXXB
Function
Block size of the corresponding channel
• When reset: Initialized to "0000B".
• These bits are readable and writable.
• If "0" is specified for all bits, the block size is set to 16 words.
• The read value is always the block size (reload value).
[bit15 to bit0] DTC (Dma Terminal Count register)*: Transfer count register
This register stores the transfer count. Each register has 16-bit length.
Each register has its own reload register. If the register is used for a channel that is enabled to reload the
transfer count register, the initial value is automatically written back to this register when the transfer is
completed.
Table 5.2-6 Transfer Count Register
DTC
XXXXH
Function
Transfer count for the corresponding channel
When a DMA transfer is started, the data in this register is stored into the counter buffer of the
dedicated DMA transfer count counter and the counter is decremented by 1 (subtraction) on a transfer
basis. When the DMA transfer is completed, the contents of the counter buffer are written back to this
register and then DMA ends. Thus, the transfer count value during DMA operation cannot be read.
• When reset: Initialized to "00000000_00000000B".
• These bits are readable and writable. Halfword length or word length must be used for DTC access.
• The read value is the count value. The reload value cannot be read.
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5.2 DMA Controller (DMAC) Register
MB91345 Series
■ DMAC - ch.0, ch.1, ch.2, ch.3, ch.4 Control/Status Register B
● [DMACB0 to DMACB4]
These registers control the operation of each DMAC channel, and are provided independently for each
channel.
The function of each bit is as follows.
Figure 5.2-2 DMAC - ch.0, ch.1, ch.2, ch.3, ch.4
Control/Status Register B
bit31 bit30 bit29 bit28 bit27 bit26 bit25 bit24 bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16
TYPE1,TYPE0 MOD1,MOD0
WS1,WS0 SADM DADM DTCR SADR DADR ERIE EDIE
DSS2 to DSS0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
bit7
bit6
bit5
SASZ7 to SASZ0
bit4
bit3
bit2
bit1
bit0
DASZ7 to DASZ0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
(Initial value: 00000000_00000000_00000000_00000000B)
R/W: Readable/writable
[bit31, bit30] TYPE1, TYPE0 (TYPE)*: Transfer type setting
These bits set the operation type of the corresponding channels as follows.
Two-cycle transfer mode:
This mode sets the transfer source address (DMASA) and transfer
destination address (DMADA), and performs the specified number of
transfer for read and write operations.
Table 5.2-7 Transfer Type Setting
TYPE
Function
00B
Two-cycle transfer (initial value)
01B
Setting disabled
10B
Setting disabled
11B
Setting disabled
• When reset: Initialized to "00B".
• These bits are readable and writable.
• Be sure to set to "00B".
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5.2 DMA Controller (DMAC) Register
MB91345 Series
[bit29, bit28] MOD1, MOD0 (MODe)*: Transfer mode setting
These bits set the operation mode of the corresponding channels as follows.
Table 5.2-8 Transfer Mode Setting
MOD
Function
00B
Block/step transfer mode (initial value)
01B
Burst transfer mode
10B
Setting disabled
11B
Setting disabled
• When reset: Initialized to "00B".
• These bits are readable and writable.
[bit27, bit26] WS1, WS0 (Word Size): Transfer data width selection
These bits are used to select the transfer data width on the corresponding channel. The specified number
of transfer operations are performed in the data width set in these registers.
Table 5.2-9 Transfer Data Width Selection
WS
Function
00B
Transfer in byte (initial value)
01B
Transfer in halfword
10B
Transfer in word
11B
Setting disabled
• When reset: Initialized to "00B".
• These bits are readable and writable.
[bit25] SADM (Source-ADdr. count-Mode select)*: Transfer source address count mode setting
This bit specifies the processing of the transfer source address on the corresponding channel for each
transfer.
An address is incremented/decremented on a transfer basis according to the specified transfer source
address count width (SASZ). When transfer is completed, the address for the next access is written to
the corresponding address register (DMASA).
Therefore, the transfer source address register is not updated until the DMA transfer is completed.
To fix the address, set "0" or "1" to this bit, and set "0" to the address count width (SASZ, DASZ).
Table 5.2-10 Transfer Source Address Count Mode Setting
SADM
CM71-10132-3E
Function
0
Increase transfer source addresses (initial value)
1
Decrease transfer source addresses
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5.2 DMA Controller (DMAC) Register
MB91345 Series
• When reset: Initialized to "0".
• This bit is readable and writable.
[bit24] DADM (Destination-ADdr. Count-Mode select)*: Transfer destination address count mode
setting
This bit specifies the processing of the transfer destination address on the corresponding channel for
each transfer.
An address is incremented/decremented on a transfer basis according to the specified transfer
destination address count width (DASZ). When transfer is completed, the address for the next access is
written to the corresponding address register (DMADA).
Therefore, the transfer destination address register is not updated until the DMA transfer is completed.
To fix the address, set "0" or "1" to this bit, and set "0" to the address count width (SASZ, DASZ).
Table 5.2-11 Transfer Destination Address Count Mode Setting
DADM
Function
0
Increase transfer destination addresses (initial value)
1
Decrease transfer destination addresses
• When rest: Initialized to "0".
• This bit is readable and writable.
[bit23] DTCR (DTC-reg. Reload)*: Transfer count register reload setting
This bit controls a reload function of the transfer count register on the corresponding channel.
If this bit enables the reload operation, the value of the count register is reset to its initial value after
transfer is completed, and DMAC halts and waits for the transfer request (an activation request by
STRG or IS setting). If this bit is "1", the DENB bit is not cleared.
The transfer is forced to stop by setting of DENB=0 or DMAE=0.
Disabling reload operation of the counter results in a single shot transfer operation, which stops when
the transfer is completed even if reload is specified in the address register. In this case, the DENB bit is
cleared.
Table 5.2-12 Transfer Count Register Reload Setting
DTCR
Function
0
Disable transfer count register reloading (initial value)
1
Enable transfer count register reloading
• When reset: Initialized to "0".
• This bit is readable and writable.
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5.2 DMA Controller (DMAC) Register
MB91345 Series
[bit22] SADR (Source-ADdr.-reg. Reload)*: Transfer source address register reload setting
This bit controls a reload function of the transfer source address register on the corresponding channel.
If this bit enables the reload operation, the value of the transfer source address register is reset to the
initial value after transfer is completed.
Disabling reload operation of the counter results in a single shot transfer operation, which stops when
the transfer is completed even if reload is specified in the address register. In this case, the operation
stops with the value of the address register which the initial value is reloaded to.
If this bit enables the reload operation, the value of the address register when the transfer is completed
is set to the next access address after the last address. (If the address increment is enabled, this will be
set to the incremented address).
Table 5.2-13 Transfer Source Address Register Reload Setting
SADR
Function
0
Disable transfer source address register reloading (initial value)
1
Enable transfer source address register reloading
• When reset: Initialized to "0".
• This bit is readable and writable.
[bit21] DADR (Dest.-ADdr.-reg. Reload)*: Transfer destination address register reload setting
This bit controls a reload function of the transfer destination address register on the corresponding
channel.
If this bit enables the reload operation, the value of the transfer destination address register is reset to
the initial value after transfer is completed.
The details of other functions are the same as those described for bit22:SADR.
Table 5.2-14 Transfer Destination Address Register Reload Setting
DADR
Function
0
Disable transfer destination address register reloading (initial value)
1
Enable transfer destination address register reloading
• When reset: Initialized to "0".
• This bit is readable and writable.
[bit20] ERIE (ERror Interrupt Enable)*: Error interrupt output enable
This bit controls an interrupt generation at a termination when an error occurs. The details of the
generated error is indicated by DSS2 to DSS0. Note that the interrupt is generated not by every
termination trigger but by a specific one (Refer to DSS2 to DSS0 bits).
Table 5.2-15 Error Interrupt Output Enable
ERIE
Function
0
Disable error interrupt request output (initial value)
1
Enable error interrupt request output
• When reset: Initialized to "0".
• This bit is readable and writable.
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5.2 DMA Controller (DMAC) Register
MB91345 Series
[bit19] EDIE (EnD Interrupt Enable)*: End interrupt output enable
This bit controls an interrupt generation at a normal end.
Table 5.2-16 End Interrupt Output Enable
EDIE
Function
0
Disable end interrupt request output (initial value)
1
Enable end interrupt request output
• When reset: Initialized to "0".
• This bit is readable and writable.
[bit18 to bit16] DSS2 to DSS0 (Dma Stop Status)*: Transfer stop factor indication
These bits indicate a code (end code) of 3 bits that indicates the stop/end factor of DMA transfer on the
corresponding channel. The descriptions of end codes are as follows.
Table 5.2-17 Transfer Stop Factor Indication (DSS2)
DSS2
Function
Interrupt generation
0
Initial value
None
1
DMA halting (DMAH, PAUS bit, interrupt, etc.)
None
Table 5.2-18 Transfer Stop Factor Indication (DSS1, DSS0)
DSS1, DSS0
Function
Interrupt generation
00B
Initial value
None
01B

None
10B
Transfer stop request
Error
11B
Normal end
End
The transfer stop request is set only when a request from a peripheral circuit is used.
Note:
The "Interrupt generation" column indicates the possible type of interrupt request.
• When reset: Initialized to "000B".
• These bits are cleared when "000B" is written.
• These bits are readable and writable. However, only "000B" written to these bits is valid.
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5.2 DMA Controller (DMAC) Register
MB91345 Series
[bit15 to bit8] SASZ7 to SASZ0 (Source Addr count SiZe)*: Transfer source address count size setting
These bits specify the increment or decrement width of the transfer source address (DMASA) on the
corresponding channel for each transfer. The value set for these bits indicates the address increment or
decrement width for each transfer unit. The address increment or decrement width depends on the
transfer source address count mode setting (SADM).
Table 5.2-19 Transfer Source Address Count Size Setting
SASZ7 to SASZ0
Function
00H
Address fixed
01H
Transfer in byte
02H
Transfer in halfword
04H
Transfer in word
Other than above
Setting disabled
• When reset: Initialized to "00000000B".
• These bits are readable and writable.
• If setting other than the address fixed, set the same transfer unit as that for transfer data width (WS).
[bit7 to bit0] DASZ7 to DASZ0 (Des Addr count SiZe)*: Transfer destination address count size setting
These bits specify the increment or decrement width of the transfer destination address (DMADA) on
the corresponding channel for each transfer. The value set for these bits indicates the address increment
or decrement width for each transfer unit. The address increment or decrement width depends on the
transfer destination address count mode setting (DADM).
Table 5.2-20 Transfer Destination Address Count Size Setting
DASZ7 to DASZ0
Function
00H
Address fixed
01H
Transfer in byte
02H
Transfer in halfword
04H
Transfer in word
Other than above
Setting disabled
• When reset: Initialized to "00000000B".
• These bits are readable and writable.
• If setting other than the address fixed, set the same transfer unit as that for transfer data width (WS).
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CHAPTER 5 DMA Controller (DMAC)
5.2 DMA Controller (DMAC) Register
MB91345 Series
■ DMAC - ch.0, ch.1, ch.2, ch.3, ch.4 Transfer Source/Destination Address Setting
Register
● [DMASA0 to DMASA4/DMADA0 to DMADA4]
These registers control the operation of each DMAC channel, and are provided independently for each
channel. The function of each bit is as follows.
• ch.0 to ch.3
Figure 5.2-3 DMAC - ch.0, ch.1, ch.2, ch.3 Transfer Source/Destination Address Setting Register
(ch.0 to ch.3)
bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DMASA0 to DMASA3[19:16]
bit
15
14
13
11
11
10
9
8
7
6
5
4
3
2
1
0
DMASA0 to DMASA3[15:0]
(Initial value: 00000000_00000000_00000000_00000000B)
bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DMADA0 to
DMADA3[19:16]
bit
15
14
13
11
11
10
9
8
7
6
5
4
3
2
1
0
DMASA0 to DMASA3[15:0]
(Initial value: 00000000_00000000_00000000_00000000B)
• ch.4
Figure 5.2-4 DMAC - ch.4 Transfer Source/Destination Address Setting Register (ch.4)
bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
2
1
0
DMASA4[23:16]
bit
15
14
13
11
11
10
9
8
7
6
5
4
3
DMASA4[15:0]
(Initial value: 00000000_00000000_00000000_00000000B)
bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
2
1
0
DMADA4[23:16]
bit
15
14
13
11
11
10
9
8
7
6
5
4
3
DMADA4[15:0]
(Initial value: 00000000_00000000_00000000_00000000B)
These registers store the transfer source/destination address. The channels from 0 to 3 have 20-bit length,
ch.4 has 24-bit length.
[bit31 to bit0] DMASA (DMA Source Addr)*: Transfer source address setting
These bits set the transfer source address.
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5.2 DMA Controller (DMAC) Register
MB91345 Series
[bit31 to bit0] DMADA (DMA Destination Addr)*: Transfer destination address setting
These bits set the transfer destination address.
When a DMA transfer is started, the data in these registers is stored into the counter buffer of the
dedicated DMA address counter and the address count is updated on a transfer basis. When the DMA
transfer is completed, the contents of the counter buffer are written back to these registers and then the
DMA ends. Thus, the address counter value during the DMA operation cannot be read.
Each register has its own reload register. If the register is used for a channel that is enabled to reload the
transfer source/transfer destination address register, the initial value is automatically written back to
these registers when the transfer is completed. At this time, other address register is not affected.
• When rest: Initialized to "00000000_00000000_00000000_00000000B".
• These bits are readable and writable. Be sure to access these registers with 32-bit data.
• During transfer, the read value is the address value before the transfer. After transfer, the read value
is the next access address value. The reload value cannot be read. Therefore, the transfer address
cannot be read in real time.
• Set "0" to higher bits which do not exist.
Note:
Do not set any of the DMACs' registers using this register. DMA transfer to registers in the DMAC is
not allowed.
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CHAPTER 5 DMA Controller (DMAC)
5.2 DMA Controller (DMAC) Register
MB91345 Series
■ DMAC - ch.0, ch.1, ch.2, ch.3, ch.4
DMAC All-channel Control Register
● [DMACR]
This register controls the operations of all five DMA channels. Be sure to access this register using byte
length.
The functions of each bit are as follows.
Figure 5.2-5 DMAC - ch.0, ch.1, ch.2, ch.3, ch.4
bit
bit
31
30
29
28
27
26
25
DMAE


PM01
15
14
13
11
11
10
9







24
DMAC All-channel Control Register
23
22
21
20
19
18
17
16








8
7
6
5
4
3
2
1
0









DMAH3 to DMAH0
(Initial value: 0XX00000_XXXXXXXX_XXXXXXXX_XXXXXXXXB)
[bit31] DMAE (DMA Enable): DMA operation enable
This bit controls operations of all DMA channels.
When this bit disables DMA operation, the transfer operation on all channels is disabled regardless of
the operation status or the start/stop settings for each channel. Also, the channel in transferring cancels
the requests and stops the transfer at a block boundary. Any start operation on each channel in the
disabled status is invalid.
When this bit enables DMA operation, the start/stop operations are allowed for each channel. Using this
bit to enable DMA operation does not perform activations on each channel.
The transfer can be forced to stop by writing "0" to this bit. Be sure to stop a transfer forcibly (0 write)
only after pausing DMA by using the DMAH3 to DMAH0 bits (DMACR:bit27 to bit24). If the transfer
is forced to stop without pausing DMA, DMA stops but the transferred data cannot be guaranteed.
Check whether DMA is stopped using DSS2 to DSS0 bits (DMACB:bit18 to bit16]).
Table 5.2-21 DMA Operation Enable
DMAE
Function
0
Disable DMA operation on all channels (initial value)
1
Enable DMA operation on all channels
• When rest: Initialized to "0".
• This bit is readable and writable.
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5.2 DMA Controller (DMAC) Register
MB91345 Series
[bit28] PM01 (Priority Mode ch.0,1 robin): Channel priority rotation
This bit is set to change the priority between ch.0 and ch.1 on a transfer basis.
Table 5.2-22 Channel Priority Rotation
PM01
Function
0
Priority fixed (ch.0 > ch.1) (initial value)
1
Priority rotated (ch.1 > ch.0)
• When reset: Initialized to "0".
• This bit is readable and writable.
[bit27 to bit24] DMAH (DMA Halt): DMA halt
These bits control a halt of all DMA channels. Once these bits have been set, DMA transfers on all
channels are not performed until these bits are cleared.
Started after these bits set, DNA transfers on all channels remain pausing.
Any transfer requests generated on a channel for which DMA transfer is enabled (DENB=1) are valid
while these bits are set. And the transfer starts when the bits are cleared.
Table 5.2-23 DMA Halt
DMAH
Function
0000B
Enable DMA operation on all channels (initial value)
Others
Halt DMA operation on all channels
• When reset: Initialized to "0".
• These bits are readable and writable.
[bit30, bit29, bit23 to bit0] (Reserved): Unused bits
The read value is indeterminate.
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CHAPTER 5 DMA Controller (DMAC)
5.3 Operation of DMA Controller
5.3
MB91345 Series
Operation of DMA Controller
This section explains the operation of the DMA controller.
■ Main Operation
• Functions can be set independently for each transfer channel.
• Once enabled, each channel does not start transfer operation until a specified transfer request is
detected.
• On detecting the transfer request, DMAC outputs DMA transfer request to the bus controller and
starts transfer on receiving bus access rights from the bus controller.
• The transfer is performed in sequence according to the independent mode settings for each channel.
■ Transfer Mode
Each DMA channel operates a transfer according to the transfer mode set in the MOD1, MOD0 bits of
its DMACB register.
● Block/step transfer
DMA transfers only one block transfer unit per transfer request, then stops a transfer request to the
bus controller until the next transfer request is received.
Block transfer unit: specified block size (DMACA:BLK3 to BLK0)
● Burst transfer
The transfer is repeated for a specified transfer count, in a transfer request.
Specified transfer count: block size  transfer count (DMACA:BLK3 to BLK0  DMACA:DTC15
to DTC0)
■ Transfer Type
● Two-cycle transfer (normal transfer)
The DMA controller performs a set of read operation and write operation as a unit.
The DMAC reads data from the address in the transfer source register, and then write it into the
transfer destination register.
■ Transfer Address
The following types of addressing are available and can be set independently for each channel transfer
source and destination.
● Specifying the address for two-cycle transfer
The value read from the registers (DMASA and DMADA) in which the address has been preset is
used as the address for access.
After receiving a transfer request, DMA stores the addresses from those registers into temporary
storage buffers and then start the transfer.
On each transfer (access), the next access address is generated by using the address counter (can be
based on increment/decrement/fixed) and restored into the temporary storage buffer. The contents of
this temporary storage buffer are written back to the registers (DMASA and DMADA) when each
transfer block unit is completed.
Since the values in the address registers (DMASA and DMADA) are only updated on a transfer
block unit basis, the address cannot be determined in real time during transfer.
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5.3 Operation of DMA Controller
MB91345 Series
■ Transfer Count and Transfer End
● Transfer count
The transfer count register is decremented (1) after each block transfer is completed. When the
transfer count register reaches "0", indicating that the specified number of transfer has been
completed, DMAC displays the end code and stops or restarts.
The value in the transfer count register is only updated on a transfer block basis like that in the
address register.
When the transfer count register reload is disabled, the transfer ends. If the reload is enabled,
DMAC initialize the register value and waits for transfer (DMACB:DTCR).
● Transfer end
Transfer can be ended by the following factors. A factor is indicated as an end code at the transfer
end. (DMACB:DSS2 to DSS0)
• End of the specified transfer count (DMACA:BLK3 to BLK0  DMACA:DTC15 to DTC0) 
Normal end
• Generation of transfer stop request from peripheral circuit  Error
• Reset triggered  Reset
The transfer stop factor (DSS) can be indicated and the transfer end/error interrupt can be generated
corresponding to each end factor.
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CHAPTER 5 DMA Controller (DMAC)
5.4 Setting Transfer Request
5.4
MB91345 Series
Setting Transfer Request
There are two types of transfer requests to activate DMA transfer as follows. The
software request can be used at any time regardless of other request settings.
■ Built-in Peripheral Request
A transfer request is generated by an interrupt from a built-in peripheral circuit.
The interrupt from a peripheral circuit to generate a transfer request is set for each channel.
(DMACA:IS4 to IS0=1XXXXB)
Note:
Since an interrupt request used for a transfer request is taken as an interrupt request for CPU,
disable the interrupts in the interrupt controller. (ICR register)
■ Software Request
A transfer request is generated by writing to the trigger bit in the register. (DMACA:STRG)
This is independent of the transfer request mentioned above, and is always available.
If a software request is triggered simultaneously with the activation (transfer enable), DMAC
immediately outputs the DMA transfer request to the bus controller and starts the transfer.
Note:
If the software request is set to a channel that has been set the built-in peripheral request, perform
the DMAC clear factors on the appropriate peripherals after the transfer is completed. As this may
clear a proper transfer request, do not use the software request in this case.
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CHAPTER 5 DMA Controller (DMAC)
5.5 Transfer Sequence
MB91345 Series
5.5
Transfer Sequence
The transfer type and mode which determines, for example, the operation sequence
after DMA transfer started can be set independently for each channel. (setting on
DMACB:TYPE1, TYPE0, MOD1, MOD0)
■ Transfer Sequence Selection
The following sequences can be selected with register settings.
• Burst two-cycle transfer
• Block/step two-cycle transfer
■ Burst Two-cycle Transfer
DMAC repeats a transfer for a transfer factor as many times as the specified transfer count. In a two-cycle
transfer, the transfer source/destination address can be specified as 20-bit address for ch.0 to ch.3 and as
24-bit address for ch.4.
A transfer factor can be a peripheral transfer request or a software transfer request.
● Characteristics of burst transfer
• Each time a transfer request is received, transfer continues until the transfer count register reaches
"0".
Transfer count is the block size  the transfer count. (DMACA:BLK3 to BLK0  DMACA:DTC15
to DTC0)
• If another request is generated during transfer, the request is ignored.
• When the reloading of the transfer count register is enabled, the next transfer request is accepted
after transfer is completed.
• If a transfer request from another channel with a higher priority is received during transfer, the
DMAC changes these channels at the boundary of the block transfer units and does not restart the
transfer until the request on the channel with the higher priority is cleared.
Figure 5.5-1 Example of Burst Transfer for a Peripheral Transfer Request, Block Number = 1,
Transfer Count = 4
Peripheral
transfer request
Bus operation
CPU
SA
DA
SA
DA
SA
DA
SA
Transfer count
DA
CPU
1
Transfer end
(internal)
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CHAPTER 5 DMA Controller (DMAC)
5.5 Transfer Sequence
MB91345 Series
■ Step/Block Transfer Two-cycle Transfer
In a step/block transfer (transfer for a specified number of blocks in each transfer request), the transfer
source/destination address can be specified as 20-bit address for ch.0 to ch.3 and as 24-bit address for ch.4.
● Step transfer
The step transfer sequence is used if the block size is set to "1".
● Characteristics of step transfer
• Each time a transfer request is received, one transfer is performed. And then the transfer request is
cleared and the transfer stopped. (The DMA transfer request to the bus controller is canceled).
• If another request is generated during transfer, the request is ignored.
• If a transfer request from another channel with a higher priority is received during transfer, after the
transfer is stopped, the DMAC changes these channels and starts the next transfer. The priority in the
step transfer is valid only if transfer requests is generated simultaneously.
● Block transfer
The block transfer sequence is used if the block size is set to a value other than "1".
● Features of block transfer
The operation is the same as that for step transfer except that one transfer unit consists of multiple counts of
transfer cycle (number of block).
Figure 5.5-2 Example of Block Transfer for a Peripheral Transfer Request, Block Number = 2,
Transfer Count = 2
Peripheral
transfer request
Bus operation
CPU
SA
DA
SA
DA
CPU
Number of blocks
SA
DA
SA
DA
1
Transfer count
Transfer end
(internal)
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CHAPTER 5 DMA Controller (DMAC)
5.6 General Aspects of DMA Transfer
MB91345 Series
5.6
General Aspects of DMA Transfer
This section explains the general aspects of the DMA transfer.
■ Block Size
• A transfer unit of transfer data is a set of data that is set in the block size setting register ( data width).
• Since the size of data transferred in each transfer cycle is fixed at the value specified by data width, a
transfer unit consists of the number for transfer cycles for the block size setting value.
• During transfer, if a transfer request with a higher priority is received or if a transfer halt request is
generated, a block transfer stops only at a boundary of the transfer units. This can protect a data block
from splitting and pausing, but may cause the degradation in response time if the block size is large.
• The transfer is stopped only if the reset is triggered, but the transferred data is not guaranteed.
■ Reload Operation
In this module, the following three reload functions can be set for each channel.
• Transfer count register reload function
When the specified number of transfers completes, DMAC resets the transfer count register to its initial
value and waits for the next trigger.
This setting is used to repeat the entire transfer sequence.
If reload is not specified, the count register remains at "0" after the specified number of transfers is
completed and no further transfers are performed.
• Transfer source address register reload function
When the specified number of transfers is completed, DMAC resets the transfer source address register
to its initial value.
This setting is used to repeat the transfer from a fixed area in the transfer source register address area.
If the reload is not specified, the transfer source address register value is set to the next transfer address
after the specified number of transfers is completed. This setting is used when the address area is not
fixed.
• Transfer destination address register reload function
When the specified number of transfers is completed, DMAC resets the transfer destination address
register to its initial value.
This setting is used to repeat the transfer to a fixed area in the transfer destination address area.
If the reload is not specified, the transfer source address register value is set to the next transfer address
after the specified number of transfers is completed. This setting is used when the address area is not
fixed.
If only the reload function of the transfer source/destination register is enabled, the restart after the
specified number of transfers is completed is not performed. Only the values of each address register are
set.
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CHAPTER 5 DMA Controller (DMAC)
5.6 General Aspects of DMA Transfer
MB91345 Series
Notes:
Special examples of operating mode and the reload operation
• If you want to halt a transfer after it is completed and to restart where another input is detected,
do not specify reload.
• In burst, block, or step transfer mode, transfer halts after the reload if the transfer is completed,
and no further transfer is performed until a new transfer request input is detected.
■ Addressing Mode
The transfer destination/source address for each transfer channel is specified independently.
The following procedure is used to set the registers. Set the registers according to the transfer sequence.
● Address register setting
In two-cycle transfer mode, set the transfer source address in the transfer source address setting register
(DMASA) and set the transfer destination address in the transfer destination address setting register
(DMADA).
● Features of address register setting
The channels from 0 to 3 have 20-bit length, ch.4 has 24-bit length.
● Functions of address register
• The registers are read at the time of each access and transferred to the address bus.
• At the same time, the address counter is used to calculate the address for the next access and the address
register is updated with the calculated address.
• Either increment or decrement is selected for the address calculation of each channel, transfer
destination and transfer source. The increment or decrement width of address varies with the value of
address count size setting register. (DMACB:SASZ, DASZ7 to DASZ0)
• If the reload function is not enabled, the address calculated on the last address remains in the address
register after the transfer is completed.
• If the reload function is enabled, the initial value of the address is reloaded.
Notes:
• Even if an overflow or underflow occurs as a result of the 20-bit or 24-bit length full address
calculation, the transfer on that channel continues. Set each channel so that no overflow and
underflow is generated.
• Do not set the addresses of registers in the DMAC in the address registers.
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5.6 General Aspects of DMA Transfer
MB91345 Series
■ Data Type
The data length (data width) transferred in each transfer can be selected from the following.
• byte
• halfword
• word
Since the word boundary specification is also complied in DMA transfer, different low-order bits are
ignored if an address with a different data length is specified for the transfer destination/source address.
• word:
The actual access address has 4-byte length starting with "00B" as the lower 2 bits.
• halfword:
The actual access address has 2-byte length starting with "0" as the lower 1 bit.
• byte:
The actual access address and the address setting match.
If the lower bits in the transfer source address and the transfer destination address are different, the
addresses as set are output on the internal address bus. However, each transfer target on the bus is accessed
after the addresses has been corrected according to the above rules.
■ Transfer Count Control
The transfer count is specified within the range of the maximum 16-bit length (1 to 65536). The transfer
count value is set in the transfer count register (DMACA:DTC).
The register value is stored into a temporary storage buffer when a transfer starts, and is decremented by
the transfer count counter. When the counter value reached to "0", the DMAC detects that the specified
number of transfers is completed, and then stops the transfer on the channel or waits for the next trigger (if
reload is enabled).
● Characteristics of transfer count registers
• Each register has 16-bit length.
• Each register has its own reload register.
• If activated when the register value is "0", transfer is performed 65536 times.
● Reload operation
• The reload operation can be used only if reloading is enabled in a register that allows reloading.
• When transfer is activated, the initial value of the count register is saved in the reload register.
• If the transfer count counter counts down to "0", the transfer end is reported. And the initial value is
read from the reload register and written to the count register.
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CHAPTER 5 DMA Controller (DMAC)
5.6 General Aspects of DMA Transfer
MB91345 Series
■ CPU Control
When a DMA transfer request is accepted, DMA issues a transfer request to the bus controller.
The bus controller passes the right to use the internal bus to DMA at a break in bus operation and DMA
transfer starts.
● DMA transfer and interrupt
• During a DMA transfer, interrupts are generally not accepted until the transfer is completed.
• If a DMA transfer request occurs during interrupt processing, the transfer request is accepted and
interrupt processing is stopped until the transfer is completed.
• As an exception, if a NMI request or an interrupt request with a higher level than the hold suppress level
set by the interrupt controller is generated, DMAC temporarily cancels the transfer request for the bus
controller at a transfer unit boundary (one block) and pauses the transfer until the interrupt request is
cleared. The transfer request is retained internally during this time. After the interrupt request has been
cleared, DMAC issues a transfer request to the bus controller to acquire the right to use the bus and then
starts the DMA transfer again.
● DMA suppression
• On the FR family, DMAC interrupts a DMA transfer to branch to the relevant interrupt routine when an
interrupt factor with a higher priority is generated during DMA transfer. This feature is valid as long as
any interrupt requests exist. However, if interrupt factors are cleared, the suppression feature no longer
works and the DMA transfer is restarted in the interrupt processing routine. Thus, if you want to
suppress restart of a DMA transfer after clearing interrupt factors in the interrupt factor processing
routine at a level that interrupts a DMA transfer, use the DMA suppress function. The DMA suppress
function can be activated by writing any value other than "0" to the DMAH3 to DMAH0 bits of the
DMA all-channel control register and can be stopped by writing "0" to these bits.
• This function is primarily used in the interrupt processing routines. Before clearing the interrupt factor
in the interrupt processing routine, this function increments the value in the DMA suppress register by 1.
This prevents any subsequent DMA transfer. After handling the interrupt processing, this function
decrements the value of DMAH3 to DMAH0 bits by 1 before returning. In case of multiple interrupts,
the DMA transfer continues to be suppressed since the values of the DMAH3 to DMAH0 bits are not
"0" yet. Otherwise, the values of DMAH3 to DMAH0 bits become "0" and then the DMA requests are
enabled immediately.
Notes:
• Since the register has only 4 bits, this function cannot be used for multiple interrupts exceeding 15
levels.
• Be sure to make the DMA tasks at least 15 levels higher priority than other interrupt levels.
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5.6 General Aspects of DMA Transfer
MB91345 Series
■ Operation Start
Starting of a DMA transfer is controlled independently for each channel, but before the transfer starts, the
operation of all channels must be enabled.
● Enabling operation on all channels
Before activating on each DMAC channel, operation on all channels must be enabled the DMA operation
enable bit (DMACR:DMAE). All start settings and transfer requests generated before operation is enabled
are invalid.
● Starting transfer
The transfer operation can be started by the operation enable bit in the control register for each channel. If a
transfer request to the activated channel is accepted, the DMA transfer operation is started in the specified
mode.
● Starting during halts
If a halt occurs before starting with channel-by-channel or all-channel control, the halt state is maintained
even though the transfer operation is started. If generated during that time, transfer requests are accepted
and retained. When the halt is released, a transfer is started.
■ Transfer Request Acceptance and Transfer
• Sampling for transfer request set for each channel starts after the activation.
• If peripheral interrupt activation is selected, DMAC continues the transfer until all transfer requests are
cleared. When they are cleared, DMAC stops the transfer in one transfer unit (peripheral interrupt
activation).
Since the peripheral interrupt is handled as a level detection, use the interrupt clear by DMA to handle
the interrupts.
• Transfer requests are always accepted while requests from other channel are accepted and transfer is
performed. The channel to be used for transfer is determined for each transfer unit according to the
priority.
■ Peripheral Interrupt Clear by DMA
• The DMA has a function that clears peripheral interrupts. This function works when peripheral interrupt
is selected as the DMA trigger (when IS4 to IS0=1XXXXB).
• The peripheral interrupt clear is performed for the trigger that has been set. That is, only the peripheral
functions set on IS4 to IS0 are cleared.
● Timing for interrupt clear generation
The timing for the generation depends on the transfer mode (See section "5.7 Operation Flowchart").
[Block/step transfer]
If the block transfer is selected, a clear signal is generated per one block (step) transfer.
[Burst transfer]
If the burst transfer is selected, a clear signal is generated when the specified transfer count is
completed.
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CHAPTER 5 DMA Controller (DMAC)
5.6 General Aspects of DMA Transfer
MB91345 Series
■ Halt
DMA halts in the following cases.
● Halt setting by writing to the control register (set for each channel individually or for all channels
together)
If the halt is set with halt bits, a transfer on the corresponding channel is stopped until the halt cancellation
is set again. You can check the DSS bit for the halt condition.
The transfer is restarted when the halt is canceled.
● NMI/hold suppress level interrupt processing
If an NMI request or an interrupt request with a higher level than the hold suppress level is generated,
DMAC halts all transferring channels at a boundary of the transfer units, and opens a bus rights to give a
higher priority to NMI/interrupt processing. Transfer requests accepted during NMI/interrupt processing
are retained and waits for the completion of the NMI processing.
The channels retaining requests restart transfers after the NMI/interrupt processing is completed.
■ Operation End/Stop
The end of DMA transfer can be controlled independently for each channel. It is also possible to disable the
operation for all channels.
● Transfer end
If the reload is disabled, the DMAC stops a transfer, displays "Normal end" as the end code, and disables
any further transfer request when the transfer count register becomes "0" (clear DMACA:DENB bit).
If the reload is enabled, the DMAC reloads an initial value, displays "Normal end" as the end code, and
waits for a transfer request again when the transfer count register becomes "0" (not clear DMACA: DENB
bit).
● Disabling operation on all channels
If the operations on all channels are disabled with the DMA operation enable bit DMAE, all DMAC
operations, including operations on active channels, are stopped. After that, even if the DMA operations on
all channels are enabled again, no transfer is performed unless each channel is restarted independently. In
this case, no interrupt is generated.
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CHAPTER 5 DMA Controller (DMAC)
5.6 General Aspects of DMA Transfer
MB91345 Series
■ Stop Due to Error
In addition to normal end after the specified number of transfers is completed, a transfer may be stopped
due to various error or be stopped forcibly.
● Generation of transfer stop request from peripheral circuit
Depending on the peripheral circuit that outputs a transfer request, a transfer stop request may be generated
when an error is detected (Example: reception/transmission error on peripherals in a communication
system).
When received such a transfer stop request, the DMAC displays "Transfer stop request" as the end code
and stops the transfer on the corresponding channel.
Notes:
• For the availability of the transfer stop request from peripheral circuits, see the description of the
transfer trigger selection bits [bit28 to bit24] (IS4 to IS0) in the DMACA register.
• For details of the conditions under which a transfer stop request is generated, see the
specifications for each peripheral circuit.
■ DMAC Interrupt Control
The following interrupts can be output for each DMAC channel independently of peripheral interrupts that
can be transfer requests.
• Transfer end interrupt: Generated only when operations end normally
• Error interrupt:
Transfer stop request from peripheral circuits (error due to a peripheral)
These interrupts are outputs according to the meaning of the end code.
Interrupt request can be cleared by writing "000B" to DSS2 to DSS0 (end code) on DMACS.
Be sure to clear the end code by writing "000B" before restarting.
If the reload is enabled, the transfer is automatically restarted. At this point, however, the end code is not
cleared and is retained until a new end code is written when the next transfer is completed.
Since only one end factor can be displayed in the end code, the result of setting priorities is displayed if
multiple factors are generated simultaneously. The interrupt generated at this time conforms to the
displayed end code.
The following shows the priority for displaying end codes (in order of decreasing priority).
• Reset
• Clear by writing "000B"
• Peripheral stop request
• Normal end
• Channel selection and control
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CHAPTER 5 DMA Controller (DMAC)
5.6 General Aspects of DMA Transfer
MB91345 Series
■ DMA Transfer in Sleep Mode
• The DMAC can also operate in sleep mode.
• For the operation in sleep mode, note the following.
- Since the CPU stops, the DMAC register cannot be rewritten. Complete settings before putting it into
sleep mode.
- Since the sleep mode is cancelled by an interrupt, interrupts must be disabled by the interrupt
controller if a peripheral interrupt is selected as the DMAC trigger.
Similarly, if you do not want to cancel the sleep mode by the DMAC end interrupt, disable the interrupts.
■ Channel Selection and Control
Up to 5 channels can be set as transfer channels at one time. In general, the functions can be set
independently on each channel.
● Priority for channels
Since a DMA transfer is possible only on one channel, the priority must be set for channels.
The priority setting has two modes: fixed and rotation. These modes can be selected for each channel group
(described later).
(1) Fixed mode
The priority is fixed by channel number in ascending order.
(ch.0 > ch.1 > ch.2 > ch.3 > ch.4)
If a transfer request with a higher priority is received during transfer, the transfer channel is switched to
the channel with the higher priority when transfer for one transfer unit (the number set in the block size
setting register  data width) is completed.
When the higher priority transfer is completed, transfer on the previous channel is restarted.
Figure 5.6-1 Timing Chart for Fixed Mode
ch.0 transfer request
ch.1 transfer request
Bus operation
Transfer channel
CPU
SA
DA
ch.1
SA
DA
ch.0
SA
DA
ch.0
SA
DA
CPU
ch.1
ch.0 transfer end
ch.1 transfer end
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CHAPTER 5 DMA Controller (DMAC)
5.6 General Aspects of DMA Transfer
MB91345 Series
(2) Rotation mode (between ch.0 and ch.1 only)
When operation is enabled, the initial states are set as the same priority as (1). However, the priority for
the channel is switched when a transfer is completed. Thus, if more than one transfer request is output
at the same time, the channel is switched by a transfer unit.
This mode is effective when continuous/burst transfer is set.
Figure 5.6-2 Timing Chart for Rotation Mode
ch.0 transfer request
ch.1 transfer request
Bus operation
CPU
SA
Transfer channel
DA
ch.1
SA
DA
SA
ch.0
DA
SA
ch.1
DA
CPU
ch.0
ch.0 transfer end
ch.1 transfer end
● Channel group
Set the priority selection as shown in the following table.
Table 5.6-1 Channel Group
CM71-10132-3E
Mode
Priority
Remarks
Fixed
ch.0 > ch.1

Rotation
ch.0 > ch.1

ch.0 < ch.1
The initial state is the order as shown in the upper row.
The order is reversed if transfer with that state is
completed.
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CHAPTER 5 DMA Controller (DMAC)
5.7 Operation Flowchart
5.7
MB91345 Series
Operation Flowchart
This section shows the flowcharts for the block transfer and burst transfer.
■ Block Transfer
Figure 5.7-1 Operation Flowchart (Block Transfer)
Stop DMA
DENB→0
DENB=1
Reload enabled
Wait for
activation request
Activation request
Load the initial address,
transfer count, block count
Calculate the address for
transfer source address access
Calculate the address for
transfer destination address access
Block count − 1
BLK=0
Transfer count − 1
Only when the peripheral interrupt trigger is selected
Write back the address,
transfer count, block count
Clear the interrupt
Interrupt clear generation
DTC=0
DMA transfer end
DMA interrupt generation
Block Transfer
•
•
•
•
•
190
Can be activated by any trigger (option).
Can access any area.
Can set the block count.
Generates an interrupt clear when the block count is completed.
Generates a DMA interrupt when the specified transfer count is completed.
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CHAPTER 5 DMA Controller (DMAC)
5.7 Operation Flowchart
MB91345 Series
■ Burst Transfer
Figure 5.7-2 Operation Flowchart (Burst Transfer)
Stop DMA
DENB→0
DENB=1
Wait for
activation request
Reload enabled
Load the initial address,
transfer count, block count
Calculate the address for
transfer source address access
Calculate the address for
transfer destination address access
BLK=0
DTC=0
Write back the address,
transfer count, block count
Only when the peripheral interrupt trigger is selected
Clear the interrupt
DMA transfer end
Interrupt clear generation
DMA interrupt generation
Burst Transfer
•
•
•
•
Can be activated by any trigger (option).
Can access any area.
Can set the block count.
Clears interrupt and generates a DMA interrupt when the specified transfer count is completed.
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CHAPTER 5 DMA Controller (DMAC)
5.8 Data Path
5.8
MB91345 Series
Data Path
This section shows the data flow in two-cycle transfer.
■ Data Flow in Two-cycle Transfer
Two transfer examples are illustrated below (other sets are omitted).
Figure 5.8-1 Data Flow in Two-cycle Transfer
Transfer: Internal I/O area => Internal RAM area
DMAC
DMAC
Write cycle
Read cycle
I-bus
CPU
CPU
I-bus
Bus controller
D-bus
Data buffer
Bus controller
D-bus
F-bus
RAM
F-bus
I/O
RAM
I/O
Transfer: Internal RAM area => Internal I/O area
DMAC
DMAC
Write cycle
Read cycle
I-bus
CPU
CPU
I-bus
Bus controller
D-bus
Data buffer
Bus controller
D-bus
Data buffer
F-bus
F-bus
RAM
192
I/O
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RAM
I/O
CM71-10132-3E
CHAPTER 6
Interrupt Controller
This chapter describes an overview, the configuration
and functions of registers, and operation of the interrupt
controller.
6.1 Overview of Interrupt Controller
6.2 Interrupt Controller Register
6.3 Operation of Interrupt Controller
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CHAPTER 6 Interrupt Controller
6.1 Overview of Interrupt Controller
6.1
MB91345 Series
Overview of Interrupt Controller
The interrupt controller controls interrupt acceptance and arbitration processing.
■ Hardware Configuration of Interrupt Controller
The interrupt controller consists of the following components:
• ICR register
• Interrupt priority decision circuit
• Interrupt level and interrupt number (vector) generator
• HOLD request cancel request generator
■ Major Functions of Interrupt Controller
The interrupt controller has the following major functions:
• NMI request/interrupt request detection
• Deciding priority (using a level or number)
• Transferring of prioritizing interrupt level based on the decision result (to the CPU)
• Transferring of prioritizing interrupt number based on the decision result (to the CPU)
• Instruction for return from stop mode due to the generation of an interrupt with an NMI/ interrupt level
other than "11111B" (to CPU)
• Generating a HOLD request cancel request for the bus master
Note:
NMI is not supported in MB91345 series.
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CHAPTER 6 Interrupt Controller
6.1 Overview of Interrupt Controller
MB91345 Series
■ List of Interrupt Controller Register
Figure 6.1-1 shows the list of the interrupt controller register.
Figure 6.1-1 List of Interrupt Controller Register
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Address:
00000440H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR00
Address:
00000441H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR01
Address:
00000442H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR02
Address:
00000443H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR03
Address:
00000444H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR04
Address:
00000445H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR05
Address:
00000446H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR06
Address:
00000447H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR07
Address:
00000448H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR08
Address:
00000449H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR09
Address:
0000044AH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR10
Address:
0000044BH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR11
Address:
0000044CH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR12
Address:
0000044DH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR13
Address:
0000044EH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR14
Address:
0000044FH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR15
Address:
00000440H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR16
Address:
00000451H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR17
Address:
00000452H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR18
Address:
00000453H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR19
Address:
00000454H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR20
Address:
00000455H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR21
Address:
00000456H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR22
Address:
00000457H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR23
Address:
00000458H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR24
Address:
00000459H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR25
Address:
0000045AH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR26
Address:
0000045BH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR27
Address:
0000045CH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR28
Address:
0000045DH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR29
Address:
0000045EH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR30
Address:
0000045FH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR31
Address:
00000460H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR32
Address:
00000461H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR33
Address:
00000462H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR34
Address:
00000463H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR35
Address:
00000464H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR36
Address:
00000465H
-
-
-
ICR4
R
ICR3
R/W
ICR2
R/W
ICR1
R/W
ICR0
R/W
ICR37
(Continued)
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CHAPTER 6 Interrupt Controller
6.1 Overview of Interrupt Controller
MB91345 Series
(Continued)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Address:
00000466H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR38
Address:
00000467H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR39
Address:
00000468H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR40
Address:
00000469H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR41
Address:
0000046AH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR42
Address:
0000046BH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR43
Address:
0000046CH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR44
Address:
0000046DH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR45
Address:
0000046EH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR46
Address:
0000046FH
-
-
-
ICR4
R
ICR3
R/W
ICR2
R/W
ICR1
R/W
ICR0
R/W
ICR47
Address:
00000045H MHALTI
R/W
-
-
LVL4
R
LVL3
R/W
LVL2
R/W
LVL1
R/W
LVL0
R/W
HRCL
■ Block Diagram of Interrupt Controller
Figure 6.1-2 shows the block diagram of interrupt controller.
Figure 6.1-2 Block Diagram of Interrupt Controller.
UNMI
WAKEUP (LEVEL ≠ 11111B: “1”)
Priority decision
5
LEVEL4 to LEVEL0
NMI
processing
LEVEL,
VECTOR
generation
LEVEL decision
RI47
(DLYIRQ)
ICR00
·········
·········
RI00
VECTOR
decision
HLDREQ
cancel
request
6
MHALTI
VCT5 to VCT0
ICR47
R-bus
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CHAPTER 6 Interrupt Controller
6.2 Interrupt Controller Register
MB91345 Series
6.2
Interrupt Controller Register
This section describes the configuration and functions of the interrupt controller
register.
■ Details of Interrupt Controller Register
The interrupt controller uses the following two types of registers:
• Interrupt Control Register (ICR)
• Hold Request Cancel Request Register (HRCL)
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CHAPTER 6 Interrupt Controller
6.2 Interrupt Controller Register
6.2.1
MB91345 Series
Interrupt Control Register (ICR)
An interrupt control register (ICR) is provided for each of the interrupt input and sets the
interrupt level of the corresponding interrupt request.
■ Bit Configuration of Interrupt Control Register (ICR)
The bit configuration of the interrupt control register (ICR) is shown below.
Figure 6.2-1 Bit Configuration of Interrupt Control Register (ICR)
ICR
Address
000440H to
00046FH
R/W:
R:
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value



ICR4
ICR3
ICR2
ICR1
ICR0
---11111B
R
R/W
R/W
R/W
R/W
Readable/writable
Read only
[bit7 to bit5] -: Reserved
These are reserved bits.
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6.2 Interrupt Controller Register
MB91345 Series
[bit4 to bit0] ICR4 to ICR0
These bits, which are the interruption level set bits, specify the interrupt level of the corresponding
interrupt request.
If the interrupt level set in this register is higher than the level mask value set in the ILM register in the
CPU, an interrupt request is masked on the CPU side.
The register is initialized to "11111B" at reset.
Table 6.2-1 shows the correspondence between possible interruption level set bits and interrupt levels.
Table 6.2-1 Correspondence between Possible Interruption Level Set Bits and Interrupt
Levels
ICR4*
ICR3
ICR2
ICR1
ICR0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Interrupt level
0
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved for system
NMI
Highest level available
(High)
(Low)
Interrupts disabled
* : ICR4 is always "1"; "0" cannot be written to this bit.
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CHAPTER 6 Interrupt Controller
6.2 Interrupt Controller Register
6.2.2
MB91345 Series
Hold Request Cancel Request Register (HRCL)
HRCL is an interrupt level setting register for generating a hold request cancel request.
■ Bit Configuration of Hold Request Cancel Request Register (HRCL)
The bit configuration of the hold request cancel request register (HRCL) is shown below.
Figure 6.2-2 Bit Configuration of Hold Request Cancel Request Register (HRCL)
HRCL
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000045H
MHALTI


LVL4
LVL3
LVL2
LVL1
LVL0
0--11111B
R
R/W
R/W
R/W
R/W
R/W:
R:
R/W
Readable/writable
Read only
[[bit7] MHALTI
MHALTI is a bit to suppress the DMA transfer by an NMI request. This bit is set to "1" by the NMI
request, and cleared by writing "0" to this bit. Clear this bit at the end of the NMI routine in the same
way as with an ordinary interrupt routine.
Note:
NMI is not supported in MB91345 series.
[bit6, bit5] Reserved
These are reserved bits.
[bit4 to bit0] LVL4 to LVL0
These bits are used to set the interrupt level used to issue a hold request cancel request to the bus
master.
If an interrupt request with a higher level than the level set in this register is generated, a hold request
cancel request is issued to the bus master.
LVL4 bit is always "1" and cannot be set to "0".
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CHAPTER 6 Interrupt Controller
6.3 Operation of Interrupt Controller
MB91345 Series
6.3
Operation of Interrupt Controller
This section describes the operation of the interrupt controller.
■ Priority Decision
This module selects the interrupt factor with the highest priority from the interrupt factors generated at the
same time and outputs the interrupt level and interrupt number of the selected interrupt factor to the CPU.
The criteria for evaluating the priorities of interrupt factors are as follows:
1) NMI
2) Factor that meets the following conditions:
- Factor with an interrupt level value other than 31 (31 disables interrupts)
- Factor with the smallest interrupt level value
- Factor with the smallest interrupt number among above
If no interrupt factor is selected according to the above criteria, the interrupt controller outputs 31 (11111B)
as the interrupt level, where the interrupt number is indeterminate.
"APPENDIX B Vector Table" shows the relationship between interrupt factors, interrupt numbers, and
interrupt levels.
Note:
NMI is not supported in MB91345 series.
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CHAPTER 6 Interrupt Controller
6.3 Operation of Interrupt Controller
MB91345 Series
■ NMI (Non Maskable Interrupt)
NMI has the highest priority among the interrupt factors handled by this module. Thus, NMI is selected
whenever it is generated at the same time as other interrupt factors.
● NMI generation
When an NMI is generated, the following information is reported to the CPU:
Interrupt level: 15 (01111B)
Interrupt number: 15 (0001111B)
● NMI detection
NMI is set and detected by the external interrupt/NMI module. This module only generates an interrupt
level, interrupt number, and MHALTI in response to an NMI request.
● Suppressing DMA transfer by NMI request
When the NMI request is generated, the MHALTI bit in the HRCL register is set to "1", the DMA transfer
is suppressed. To cancel the suppression of the DMA transfer, clear the MHALTI bit to "0" at the end of
the NMI routine.
Note:
NMI is not supported in MB91345 series.
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CHAPTER 6 Interrupt Controller
6.3 Operation of Interrupt Controller
MB91345 Series
■ Hold Request Cancel Request (HRLC)
When Interrupt with a high-priority is processed during CPU hold (during DMA transfer), the device that
has generated the hold request must cancel the request. Set the HRCL register at the interrupt level as the
reference level for generating the hold request cancel request.
● Criteria for generation
If an interrupt factor with a higher interrupt level than that set in the HRCL register is generated, a hold
request cancel request is generated.
Interrupt level set of the HRCL register  Interrupt level after priority evaluation
Cancel request is generated
Interrupt level set of the HRCL register  Interrupt level after priority evaluation
No cancel request
The cancel request remains in effect until the interrupt factor generating that request is cleared, and
accordingly no DMA transfer is executed. Therefore, be sure to clear the relevant interrupt factor.
When an NMI is used, the MHALTI bit in the HRCL register is "1" and thus the cancel request is in effect.
● Allowed level
HRCL register accepts a value from "10000B" to "11111B" like the ICR register.
If the HRCL register is set to "11111B", a cancel request is generated for every level of interrupt. If it is set
to "10000B", a cancel request is generated for NMI only.
Table 6.3-1 shows the settings of interrupt level at which a hold request cancel request is generated.
Table 6.3-1 Settings of Interrupt Level at which Hold Request Cancel Request is generated
HRCL register
Interrupt level at which a hold request cancel request is generated
16
NMI only
17
NMI, Interrupt level 16
18
NMI, Interrupt levels 16 and 17
~
~
31
NMI, Interrupt levels 16 to 30 [initial value]
After reset, DMA transfer is suppressed for any level of interrupt. Since DMA transfer is not executed with
an interrupt generated, set the HRCL register to an appropriate value.
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CHAPTER 6 Interrupt Controller
6.3 Operation of Interrupt Controller
MB91345 Series
■ Returning from Standby Mode (Sleep/Stop)
This module provides the function to return from stop mode when an interrupt request occurs. If any
interrupt request (with an interrupt level other than 11111B), including an NMI, is generated from a
peripheral resource, this module issues a request to the clock control unit to return from stop mode.
Since the priority evaluation circuit restarts the operation after the clock supply recovers after returning
from the stop mode, the CPU continues to execute instructions until a priority evaluation result is obtained.
Even after returning from the sleep state, this module operates in the same way.
Also, the registers in this module are accessible even in sleep mode.
Notes:
• NMI request can perform a return from the stop mode, too. However, set an NMI so that valid
input can be detected in the stop state.
• Provide an interrupt level of "11111B" in the corresponding peripheral control register for an
interrupt factor that you do not want to cause a return from stop or sleep.
• NMI is not supported in MB91345 series. (5) Clearing an interrupt factor Some restrictions apply
to the use of an instruction to clear an interrupt factor and the RETI instruction in an interrupt
routine. For more information, see the section "CHAPTER 3 CPU and Control Section".
■ Example of Using Hold Request Cancel Request Function (HRCR)
To execute a high-priority process during DMA transfer, the CPU must request the DMA controller to
cancel the hold request for releasing itself from the hold status. In this example, an interrupt is used to
cancel a hold request to the DMA controller, or to give priority to the CPU.
● Control register
• Hold request cancel level (HRCL) register: This module:
If an interrupt with a higher level than that set in this register is generated, a hold request cancel request
to the DMA controller is generated. This register is used to set that reference level.
• Interrupt control register (ICR): This module:
A higher level than that in the HRCL register is set in the ICR register corresponding to the interrupt
factor to be used.
● Hardware configuration
Figure 6.3-1 shows the flow of the hold request signals.
Figure 6.3-1 Flow of Hold Request Signals
This module
IRQ
Bus access request
MHALTI
I-UNIT
DHREQ
DMA
B-UNIT
CPU
(ICR)
(HRCL)
204
DHREQ: D-bus hold request
DHACK: D-bus hold acknowledge
IRQ :
Interrupt request
MHALTI: Hold request cancel request
DHACK
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CHAPTER 6 Interrupt Controller
6.3 Operation of Interrupt Controller
MB91345 Series
● Sequence
Figure 6.3-2 shows an interrupt level that is higher than the one set in the HRCL register.
Figure 6.3-2 Interrupt Level that is Higher than the One Set in the HRCL Register
RUN
Bus hold
CPU
Interrupt processing
(1)
(2)
Bus hold
(DMA transfer)
Example of interrupt routine
Bus access request
(1) Interrupt factor clear
DHREQ
~
DHACK
(2) RETI
IRQ
LEVEL
MHALTI
If an interrupt request is generated and the interrupt level becomes higher than that set in the HRCL
register, MHALTI becomes active to the DMA controller. Then the DMA controller cancels the access
request, allowing the CPU to return from the hold status for servicing the interrupt.
Figure 6.3-3 shows interrupt levels for multiple interrupts.
Figure 6.3-3 Interrupt Levels for Multiple Interrupts
RUN
Bus hold
CPU
Interrupt I
Interrupt
processing II
(3)
(4)
Interrupt
processing I
(1)
(2)
Bus hold
(DMA transfer)
Bus access request
DHREQ
DHACK
IRQ1
IRQ2
LEVEL
MHALTI
[Example of interrupt routine]
(1), (3) Interrupt factor clear
~
(2), (4) RETI
In the above example, an interrupt with a higher priority is generated during execution of the interrupt
routine I.
DHREQ remains low when an interrupt with a higher level than that set in HRCL register has been
generated.
Note:
Pay attention to the relationship between the interrupt levels set in the HRCL registers and ICR.
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6.3 Operation of Interrupt Controller
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CHAPTER 7
External Interrupt Controller
This chapter describes an overview, the configuration
and functions of registers, and operation of the external
interrupt controller.
7.1 Overview of External Interrupt Controller
7.2 External Interrupt Controller Registers
7.3 Operation of External Interrupt Controller
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CHAPTER 7 External Interrupt Controller
7.1 Overview of External Interrupt Controller
7.1
MB91345 Series
Overview of External Interrupt Controller
The external interrupt controller is a block that controls external interrupt requests input to
INT Pins.
The following four types of levels can be selected as the level of a request to be detected.
• "H" level
• "L" level
• Rising edge
• Falling edge
These levels can be used to return from STOP.
■ List of External Interrupt Controller Register
Following figure shows the list of the external interrupt controller register.
Figure 7.1-1 List of External Interrupt Controller Register
Address
000040H
0000C0H
0000C4H
bit31
bit24 bit23
EIRR0
EIRR1
EIRR2
bit16 bit15
ENIR0
ENIR1
ENIR2
bit8 bit7
bit0
ELVR0
ELVR1
ELVR2
■ Block Diagram of External Interrupt Controller
Figure 7.1-2 shows a block diagram of the external interrupt controller.
Figure 7.1-2 Block Diagram of External Interrupt Controller
R-bus
8
24
8
16
208
Enable interrupt register
Gate
Factor F/F
Edge detection circuit
24
INT0 to INT23
Interrupt factor register
Request level setting register
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CHAPTER 7 External Interrupt Controller
7.2 External Interrupt Controller Registers
MB91345 Series
7.2
External Interrupt Controller Registers
This section describes the configuration and functions of the external interrupt
controller register.
■ Details of External Interrupt Controller Registers
The external interrupt controller has the following three types of registers:
• Enable Interrupts Register (ENIR0 to ENIR2)
• External Interrupt Factor Register (EIRR0 to EIRR2)
• External Interrupt Request Level Setting Register (ELVR0 to ELVR2)
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CHAPTER 7 External Interrupt Controller
7.2 External Interrupt Controller Registers
7.2.1
MB91345 Series
Enable Interrupts Register (ENIR0 to ENIR2)
ENIR controls masking of external interrupt request output.
■ Bit Configuration of Enable Interrupts Register (ENIR0 to ENIR2)
Following figure shows the bit configuration of the enable interrupts register.
Figure 7.2-1 Bit Configuration of Enable Interrupts Register (ENIR0 to ENIR2)
ENIR0
Address
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
Initial value
000041H
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
Initial value
0000C1H
EN15
EN14
EN13
EN12
EN11
EN10
EN9
EN8
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
Initial value
0000C5H
EN23
EN22
EN21
EN20
EN19
EN18
EN17
EN16
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ENIR1
ENIR2
R/W:
Readable/writable
Output for an interrupt request is enabled based on the bit in this register to which "1" has been written
(INT0 enable is controlled by EN0), after which the interrupt request is output to the interrupt controller.
The pin corresponding to the bit to which "0" is written retains the interrupt factor but does not generate a
request to the interrupt controller.
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7.2 External Interrupt Controller Registers
MB91345 Series
7.2.2
External Interrupt Factor Register (EIRR0 to EIRR2)
EIRR is a register that indicates a corresponding external interrupt request exists when
reading, and that clears a content of the flip-flop showing this request when writing.
■ Bit Configuration of External Interrupt Factor Register (EIRR0 to EIRR2)
Following figure shows the bit configuration of the external interrupt factor register.
Figure 7.2-2 Bit Configuration of External Interrupt Factor Register (EIRR0 to EIRR2)
EIRR0
Address
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Initial value
000040H
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Initial value
0000C0H
ER15
ER14
ER13
ER12
ER11
ER10
ER9
ER8
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Initial value
0000C4H
ER23
ER22
ER21
ER20
ER19
ER18
ER17
ER16
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EIRR1
EIRR2
R/W:
Readable/writable
When the EIRR register is read, Operation depends on the value that is read.
If the value is "1", there is an external interrupt request at the pin corresponding to the bit.
Write "0" to this register to clear the request flip-flop of the corresponding bit.
Writing "1" to this register is invalid.
"1" is read in a read operation of the read-modify-write (RMW) instruction.
Depending on a pin state, the external interrupt factor register can be "1" even if "0" is written to the
corresponding bit of the enable external interrupt register.
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CHAPTER 7 External Interrupt Controller
7.2 External Interrupt Controller Registers
7.2.3
MB91345 Series
External Interrupt Request Level Setting Register
(ELVR0 to ELVR2)
ELVR is a register to select request detection.
■ Bit Configuration of External Interrupt Request Level Setting Register (ELVR0 to
ELVR2)
Following figure shows the bit configuration of the external interrupt request level setting register.
Figure 7.2-3 Bit Configuration of External Interrupt Request Level Setting Register (ELVR0 to ELVR2)
ELVR0
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000042H
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000043H
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000C2H
LB15
LA15
LB14
LA14
LB13
LA13
LB12
LA12
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
0000C3H
LB11
LA11
LB10
LA10
LB9
LA9
LB8
LA8
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000C6H
LB23
LA23
LB22
LA22
LB21
LA21
LB20
LA220
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
0000C7H
LB19
LA19
LB18
LA18
LB17
LA17
LB16
LA16
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ELVR1
ELVR2
R/W:
Readable/writable
Two bits are assigned to each of external interrupt channels, and the settings are as shown below.
When each bit of the EIRR is cleared while the level is in the request input level, an appropriate bit is set
again as long as the input is at active level.
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7.2 External Interrupt Controller Registers
MB91345 Series
Note:
Changing the external interrupt request level may cause an interrupt source internally. After
changing the external interrupt request level, therefore, clear the external interrupt source register
(EIRR). Before writing to clear the external interrupt source register, read external interrupt request
level register once.
Table 7.2-1 shows assignments of ELVR.
Table 7.2-1 Assignment of ELVR
LBx LAx
Operation
00
"L" level with a request [Initial value]
01
"H" level with a request
10
Rising edge with a request
11
Falling edge with a request
Note:
Any request level can be set for returning from STOP.
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CHAPTER 7 External Interrupt Controller
7.3 Operation of External Interrupt Controller
7.3
MB91345 Series
Operation of External Interrupt Controller
This section describes the operation of the external interrupt controller.
■ Operation of External Interrupt
If, after a request level and an enable register are defined, a request defined in the ELVR register is input to
the corresponding pin, this module generates an interrupt request signal to the interrupt controller. For
simultaneous interrupt requests from the resources, the interrupt controller determines the interrupt request
with the highest priority and generates an interrupt for it.
Figure 7.3-1 shows the external interrupt operation.
Figure 7.3-1 External Interrupt Operation.
External interrupt
ELVR
Resource
request
ICR yy
EIRR
ENIR
CPU
Interrupt controller
IL
CMP
ICR xx
CMP
ILM
Factor
■ Operation Procedure for an External Interrupt
Set up a register located inside the external interrupt controller as follows.
1. Set the general-purpose I/O port served dual use as external interrupt input pin as the input port.
2. Disable the target bit in the enable interrupts register (ENIR).
3. Set the target bit in the Eexternal interrupt request level setting register (ELVR).
4. Read the Eexternal interrupt request level setting register (ELVR).
5. Clear the target bit in the enable interrupts register (ENIR).
6. Enable the target bit in the enable interrupts register (ENIR).
However, simultaneous writing of 16-bit data is allowed for step 5. and 6.
Before setting a register in this module, you must disable the enable register. In addition, before enabling
the enable register, you must clear the factor register. This procedure is required to prevent an interrupt
factor from generating by mistake while a register is being set or an interrupt is enabled.
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7.3 Operation of External Interrupt Controller
MB91345 Series
■ External Interrupt Request Level
If the request level is an edge request, a pulse width of at least three machine cycles (peripheral clock
machine cycles) is required to detect an edge.
If the request level is a level setting, a pulse width of at least 3 machine cycles is required. As long as the
interrupt input pin retains the active level, the interrupt to the interrupt controller has kept occurring even if
you clear the factor register.
The factor register must be cleared to cancel a request to the interrupt controller.
Figure 7.3-2 shows clearing the factor retaining circuit when a level is set.
Figure 7.3-2 Clearing the Factor Retaining Circuit when a Level is Set
Interrupt input
Level detection
Factor F/F
(Factor retaining circuit)
Enable gate
Interrupt controller
Retaining the factor unless it is cleared
Figure 7.3-3 shows the interrupt factor and interrupt request to the interrupt controller when interrupts are
enabled.
Figure 7.3-3 Interrupt Factor and Interrupt Request to Interrupt Controller when Interrupts are Enabled
"H" level
Interrupt input
Interrupt request to
interrupt controller
CM71-10132-3E
Becomes inactive when the factor F/F is cleared
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7.3 Operation of External Interrupt Controller
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CHAPTER 8
REALOS-Related Hardware
REALOS-related hardware is used by real-time operating
systems. Therefore, if REALOS is used, it cannot be
used in a user program.
8.1 Delayed Interrupt Module
8.2 Bit Search Module
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CHAPTER 8 REALOS-Related Hardware
8.1 Delayed Interrupt Module
8.1
MB91345 Series
Delayed Interrupt Module
This section describes an overview of delayed interrupt module, configuration/feature
of a register, and its operations.
■ Overview of Delayed Interrupt Module
Delayed interrupt module is a module used to generate an interrupt for task switch.
This module allows the software to generate or cancel interrupt requests for the CPU.
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CHAPTER 8 REALOS-Related Hardware
8.1 Delayed Interrupt Module
MB91345 Series
8.1.1
Overview of delayed interrupt module
This section describes register list, description, and operations of delayed interrupt
module.
■ Register List of Delayed Interrupt Module
The figure below shows register list of delayed interrupt module.
Figure 8.1-1 Register list of delayed interrupt module
DICR
Address
00000044H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value







DLYI
00000000B
R/W
R/W:
Readable/writable
■ Block Diagram of Delayed Interrupt Module
Figure 8.1-2 shows block diagram of the delayed interrupt module.
Figure 8.1-2 Block Diagram of Delayed Interrupt Module
R-bus
Interrupt request
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CHAPTER 8 REALOS-Related Hardware
8.1 Delayed Interrupt Module
8.1.2
MB91345 Series
Register of Delayed Interrupt Module
This section describes register configuration and features of the delayed interrupt
module.
■ Delayed Interrupt Module Register (DICR)
DICR is a register used to control a delayed interrupt.
The figure below shows a bit configuration of the delayed interrupt module register (DICR).
Figure 8.1-3 Bit Configuration of Delayed Interrupt Module Register (DICR)
DICR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value







DLYI
00000000B
000044H
R/W
R/W:
Readable/writable
[bit0] DLYI
This bit is used to control whether to generate or cancel the appropriate interrupt trigger.
DLYI
220
Description
0
Cancels a delayed interrupt trigger. No request. [Initial value]
1
Generates a delayed interrupt trigger.
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8.1.3
CHAPTER 8 REALOS-Related Hardware
8.1 Delayed Interrupt Module
Operation of Delayed Interrupt Module
Delayed interrupt is used to generate an interrupt to switch multiple tasks. This feature
allows the software to generate or cancel interrupt requests for the CPU.
■ Interrupt No.
Delayed interrupt is assigned to an interrupt trigger corresponding to the largest interrupt No.
MB91345 series assigns a delayed interrupt to interrupt No. 63 (3FH).
■ DLYI Bit of DICR
If this bit is written as "1", a delayed interrupt trigger is generated. If this bit is written as "0", a delayed
interrupt trigger is canceled.
This bit is the same as interrupt trigger flags used for general interrupt. This bit must be cleared within the
interrupt routine. At the same time, ensure to switch tasks.
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CHAPTER 8 REALOS-Related Hardware
8.2 Bit Search Module
8.2
MB91345 Series
Bit Search Module
This section describes an overview of bit search module, configuration/feature of a
register, and its operations.
■ Overview of Bit Search Module
Bit search module searches the data written in input registers for "0", "1" or a change point in order to
return a detected bit position.
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CHAPTER 8 REALOS-Related Hardware
8.2 Bit Search Module
MB91345 Series
8.2.1
Overview of Bit Search Module
This section describes a register configuration and features of the bit search module.
■ Register List of Bit Search Module
The figure below shows register list of bit search module.
Figure 8.2-1 Register List of Bit Search Module
bit31
bit0
Address: 000003F0H
BSD0
Data register for detecting 0
Address: 000003F4H
BSD1
Data register for detecting 1
Address: 000003F8H
BSDC
Data register for detecting a change point
Address: 000003FCH
BSRR
Detection result register
■ Block Diagram of Bit Search Module
Figure 8.2-2 shows block diagram of the bit search module.
Figure 8.2-2 Block Diagram of Bit Search Module
D-bus
Input latch
Address decoder
Detecting mode
1 detection data coding
Bit search circuit
Search results
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CHAPTER 8 REALOS-Related Hardware
8.2 Bit Search Module
8.2.2
MB91345 Series
Register of Bit Search Module
This section describes a register configuration and features of the bit search module.
■ Data Register for Detecting 0 (BSD0)
This data register detects "0" from values written.
The figure below shows a register configuration of the data register for detecting 0 (BSD0).
Figure 8.2-3 Configuration of Data Register for Detecting 0 (BSD0)
Address:
bit31
bit0
000003F0H
Attribute
Initial value
:Write only
:XXXXXXXXH
Initial value by the reset procedure is indeterminate. The read value is indeterminate.
Use 32-bit length data transfer command for data transfer. (Do not use 8-bit and 16-bit length data transfer
commands.)
■ Data Register for Detecting 1 (BSD1)
The figure below shows a register configuration of the data register for detecting 1 (BSD1).
Figure 8.2-4 Configuration of Data Register for Detecting 1 (BSD1)
Address:
bit31
bit0
000003F4H
Attribute
Initial value
:Readable/writable
:XXXXXXXXH
Use 32-bit length data transfer command for data transfer. (Do not use 8-bit and 16-bit length data transfer
commands.)
• When it writes : This data register detects "1" from values written.
• When it reads : Save data for internal state of bit search module is read.
This is used to save or restore the previous state when interrupt handlers use the bit search module.
If data is written into the data register for detecting 0 or for detecting a change point, it can be saved or
restored since only the data register for detecting "1" is operated.
Initial value by the reset procedure is indeterminate.
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8.2 Bit Search Module
MB91345 Series
■ Data Register for Detecting a Change Point (BSDC)
This data register detects a change point from values written.
The figure below shows a register configuration of the data register for detecting a change point (BSDC).
Figure 8.2-5 Configuration of Data Register for Detecting a Change Point (BSDC)
Address:
bit31
bit0
000003F8H
Attribute
Initial value
:Write only
:XXXXXXXXH
Initial value by the reset procedure is indeterminate.
The read value is indeterminate.
Use 32-bit length data transfer command for data transfer. (Do not use 8-bit and 16-bit length data transfer
commands.)
■ Detection Result Register (BSRR)
This data register reads detection results for detecting 0, for detecting 1 and for detecting a change point.
Detection results which will be read are determined by the most recently written data register.
The figure below shows a register configuration of the detection result register (BSRR).
Figure 8.2-6 Configuration of Detection Result Register (BSRR)
Address:
bit31
bit0
000003FCH
Attribute
Initial value
CM71-10132-3E
:Read only
:XXXXXXXXH
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CHAPTER 8 REALOS-Related Hardware
8.2 Bit Search Module
8.2.3
MB91345 Series
Operation of Bit Search Module
This section describes the operation of bit search module.
■ For Detecting 0
It scans data written into the data register for detecting 0 from MSB to LSB and returns the position where
the first "0" is detected.
Detection result is obtained by reading the detection result register. Table 8.2-1 shows the relationship
between detected position and returned value.
When there is no "0" (i.e. the value of FFFFFFFFH), the value of 32 will be returned for search results.
[Execution example]
Written data
Read value (decimal)
11111111111111111111000000000000B (FFFFF000H)

20
11111000010010011110000010101010B (F849E0AAH)

5
10000000000000101010101010101010B (8002AAAAH)

1
11111111111111111111111111111111B (FFFFFFFFH)

32
■ For Detecting 1
It scans data written into the data register for detecting 1 from MSB to LSB and returns the position where
the first "1" is detected.
Detection result is obtained by reading the detection result register. Table 8.2-1 shows the relationship
between detected position and returned value.
When there is no "1" (i.e. the value of 00000000H), the value of 32 will be returned for search results.
[Execution example]
Written data
226
Read value (decimal)
00100000000000000000000000000000B (20000000H)

2
00000001001000110100010101100111B (01234567H)

7
00000000000000111111111111111111B (0003FFFFH)

14
00000000000000000000000000000001B (00000001H)

31
00000000000000000000000000000000B (00000000H)

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CHAPTER 8 REALOS-Related Hardware
8.2 Bit Search Module
MB91345 Series
■ For Detecting a Change Point
It scans data written into the data register for detecting a change point from bit30 to LSB and compares it
with the value of MSB.
It returns the position where the value different from MSB is detected first. Detection result is obtained by
reading the detection result register.
Table 8.2-1 shows the relationship between detected position and returned value.
When there is no change point, the value of 32 will be returned. For detecting a change point, "0" will
never be returned for search results.
[Execution example]
Written data
Read value (decimal)
00100000000000000000000000000000B (20000000H)

2
00000001001000110100010101100111B (01234567H)

7
00000000000000111111111111111111B (0003FFFFH)

14
00000000000000000000000000000001B (00000001H)

31
00000000000000000000000000000000B (00000000H)

32
11111111111111111111000000000000B (FFFFF000H)

20
11111000010010011110000010101010B (F849E0AAH)

5
10000000000000101010101010101010B (8002AAAAH)

1
11111111111111111111111111111111B (FFFFFFFFH)

32
Table 8.2-1 shows bit position and returned value (decimal).
Table 8.2-1 Bit Position and Returned Value (Decimal)
CM71-10132-3E
Detected bit
position
Returned
value
Detected bit
position
Returned
value
Detected bit
position
Returned
value
Detected bit
position
Returned
value
31
0
23
8
15
16
7
24
30
1
22
9
14
17
6
25
29
2
21
10
13
18
5
26
28
3
20
11
12
19
4
27
27
4
19
12
11
20
3
28
26
5
18
13
10
21
2
29
25
6
17
14
9
22
1
30
24
7
16
15
8
23
0
31
N/A
32
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CHAPTER 8 REALOS-Related Hardware
8.2 Bit Search Module
MB91345 Series
■ Save and Restoration Procedures
If internal state of bit search module is required to save or to restore, in case that bit search module is used
during the interrupt handlers, follow the procedures below.
(1) Read the data register for detecting 1 and store it. (= Save)
(2) Use a bit search module.
(3) Write the data which was saved in step (1) into the data register for detecting 1 (= Return).
This procedure allows you to obtain the data written into bit search module before step (1), if detection
result register is read next time.
If most recently written data register is the data register for detecting 0 or the data register for detecting a
change point, it can be restored correctly using above procedure.
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CHAPTER 9
16-bit Reload Timer
This chapter describes register configuration and
feature of 16-bit reload timer and its timer operation.
9.1 Overview of 16-bit Reload Timer
9.2 Register of 16-bit Reload Timer
9.3 Operation of 16-bit Reload Timer
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CHAPTER 9 16-bit Reload Timer
9.1 Overview of 16-bit Reload Timer
9.1
MB91345 Series
Overview of 16-bit Reload Timer
16-bit reload timer is composed of the 16-bit down counter, the 16-bit reload register,
the internal count, the prescaler for generating clock and the control register.
■ Overview of 16-bit Reload Timer
16-bit reload timer is composed of the 16-bit down counter, the 16-bit reload register, the internal count,
the prescaler for creating clock and the control register.
For the clock source, you can select three types of internal clocks (the peripheral clock divided by 2, by 8,
or by 32) or external events.
■ Block Diagram of 16-bit Reload Timer
Figure 9.1-1 shows block diagram of the 16-bit reload timer.
Figure 9.1-1 Block Diagram of the 16-bit Reload Timer.
16-bit reload register
(TMRLR)
Reload
R-bus
16-bit down counter
(TMR)
RELD
UF
OUTL
OUT
CTL
Count
enabled
INTE
UF
IRQ
CNTE
TRG
Clock
selector
CSL1
CSL0
EXCK
External timer
output
IN CTL
TOE0 to TOE3
Prescaler
Prescaler
cleared
CSL1
CSL0
External
trigger
selection
Bits in PFRK
External trigger input
φ
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CHAPTER 9 16-bit Reload Timer
9.2 Register of 16-bit Reload Timer
MB91345 Series
9.2
Register of 16-bit Reload Timer
This section describes register configuration and feature used by the 16-bit reload
timer.
■ Register List of 16-bit Reload Timer
Figure 9.2-1 Register List of 16-bit Reload Timer
TMCSR (high byte)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value




CSL1
CSL0
MOD2
MOD1
----0000B




R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
MOD0

OUTL
RELD
INTE
UF
CNTE
TRG
00000000B
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
TMCSR (low byte)
TMR
bit15
bit0
Initial value
XXXXH
R
TMRLR
bit15
bit0
Initial value
XXXXH
W
R/W: Readable/writable
R:
Read only
W:
Write only
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CHAPTER 9 16-bit Reload Timer
9.2 Register of 16-bit Reload Timer
9.2.1
MB91345 Series
Control Status Register (TMCSR)
Control status register (TMCSR) is used to control the operation mode and an interrupt
of the 16-bit reload timer.
■ Bit Configuration of the Control Status Register (TMCSR)
Figure 9.2-2 Bit Configuration of the Control Status Register (TMCSR)
TMCSR (high byte)
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value




CSL1
CSL0
MOD2
MOD1
----0000B




R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value

OUTL
RELD
INTE
UF
CNTE
TRG
00000000B
R
R/W
R/W
R/W
R/W
R/W
R/W
ch.0 00004EH
ch.1 000056H
ch.2 00005EH
TMCSR (low byte)
Address
ch.0 00004FH MOD0
ch.1 000057H R/W
ch.2 00005FH
R/W: Readable/writable
R:
Read only
[bit15 to bit12] Reserved: Reserved bits
These are reserved bits.
The read value is always "0000B".
[bit11, bit10] CSL1, CSL0: Count source selection bits
These are count source selection bits. Count source is used to select internal clocks and external events.
The following count sources are available for selection.
Count source
(: Peripheral clock)
 = 25 MHz
CSL1
CSL0
0
0
Internal clock
/21 [Initial value]
80 ns
0
1
Internal clock
/23
320 ns
1
0
Internal clock
/25
1.28 µs
1
1
External events

If external events are set as count source, count effective edge is set by MOD1 and MOD0 bits.
Minimum pulse width required for the external clock is 2  T (T: peripheral clock cycle).
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CHAPTER 9 16-bit Reload Timer
9.2 Register of 16-bit Reload Timer
MB91345 Series
[bit9 to bit7] MOD2, MOD1, MOD0: Mode bits
These bits are used to select the operation mode. Different functions will be set whether "Internal clock"
or "external clock" is selected for the count source.
• When it is a internal clock mode: Reload trigger is set.
• When it is a external clock mode: Count effective edge is set.
Set "0" always for MOD2.
[Setting reload trigger when internal clock is selected]
If the internal clock is selected for the count source when effective edge is input based on the setting of
MOD2 through MOD0 bits, the data of reload register is loaded and count operation is carried on.
MOD2
MOD1
MOD0
Effective edge
0
0
0
Software trigger [Initial value]
0
0
1
External triggers (Rising edge)
0
1
0
External triggers (Falling edge)
0
1
1
External triggers (Both edges)
1
X
X
Setting disabled.
[Setting effective edge when external clock is selected]
If the external clock event is set for the count source when effective edge is input based on the setting of
MOD2 through MOD0 bits, events will be counted.
MOD2
MOD1
MOD0
Effective edge
X
0
0
- [Initial value]
X
0
1
External triggers (Rising edge)
X
1
0
External triggers (Falling edge)
X
1
1
External triggers (Both edges)
When the external event is set, reload is generated by underflow and software trigger.
[bit6] Reserved: Reserved bit
This is reserved bit.
The read value is always "0".
[bit5] OUTL: Output level
This bit is used to set the external timer output level. Output level is inverted whether this bit is "0" or
"1".
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CHAPTER 9 16-bit Reload Timer
9.2 Register of 16-bit Reload Timer
MB91345 Series
[bit4] RELD: Reload enable bit
This is a reload enable bit. When "1" is set to this bit, it will be in the reload mode. When the counter
value underflows from "0000H" to "FFFFH", the data of reload register is loaded to the counter and
count operation is carried on.
When "0" is set to this bit, it will be in the one-shot mode. When the counter value underflows from
"0000H" to "FFFFH", the count operation is stopped.
PFRxy*
OUTL
RELD
Output waveform
0
X
X
Disables output. [Initial value]
1
0
0
"H" rectangular wave during the counting.
1
1
0
"L" rectangular wave during the counting.
1
0
1
"L" toggle output when the count is started.
1
1
1
"H" toggle output when the count is started.
*: PFRxy represents the PFR register value corresponding to the pin.
[bit3] INTE: Interrupt enable bit
This is an interrupt request enable bit. When "1" is set to this bit and UF bit becomes "1", interrupt
request is generated. When "0" is set to this bit, no interrupt request is generated.
[bit2] UF: Underflow interrupt flag
This is a timer interrupt request flag. When the counter value underflows from "0000H" to "FFFFH",
this bit is set to "1". When "0" is written to this bit, it is cleared.
If this bit is written as "1", it will be useless.
When Read/Modify/Write commands are used for reading, read value will be "1".
[bit1] CNTE: Count enable bit
This is a count enable bit of a timer. If this bit is written as "1", it will be in the status waiting for startup
trigger. If this bit is written as "0", the count operation is stopped.
[bit0] TRG: Trigger bit
This is a software trigger bit. If this bit is written as "1", software trigger occurs and the data of reload
register is loaded into the counter and count operation is started.
If this bit is written as "0", it will be useless. The read value is always "0".
Trigger input using this register will be enabled only if CNTE is "1". If CNTE is "0", it does not affect
the operation.
Note:
To rewrite a bit except UF, CNTE, or TRG bit, ensure to rewrite it when CNTE is "0".
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CHAPTER 9 16-bit Reload Timer
9.2 Register of 16-bit Reload Timer
MB91345 Series
9.2.2
16-bit Timer Register (TMR)
16-bit timer register (TMR) is used to read the count value of 16-bit timer.
■ Bit Configuration of the 16-bit Timer Register (TMR)
Figure 9.2-3 Bit Configuration of the 16-bit Timer Register (TMR)
TMR
Address
ch.0 00004AH
ch.1 000052H
ch.2 00005AH
bit15
bit0
Initial value
XXXXH
R
R: Read only
This register allows reading the count value of 16-bit timer. Initial value is indeterminate. Make sure to use
16-bit data transfer commands to read this register.
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CHAPTER 9 16-bit Reload Timer
9.2 Register of 16-bit Reload Timer
9.2.3
MB91345 Series
16-bit Reload Register (TMRLR)
16-bit reload register (TMRLR) is used to hold the initial value of the counter.
■ Bit Configuration of the 16-bit Reload Register (TMRLR)
Figure 9.2-4 Bit Configuration of the 16-bit Reload Register (TMRLR)
TMRLR
Address
ch.0 000048H
ch.1 000050H
ch.2 000058H
bit15
bit0
Initial value
XXXXH
W
W: Write only
This register is used to hold the initial value of the counter. Initial value is indeterminate. Make sure to use
16-bit data transfer commands to read this register.
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CHAPTER 9 16-bit Reload Timer
9.3 Operation of 16-bit Reload Timer
MB91345 Series
9.3
Operation of 16-bit Reload Timer
This section describes the following operations of the 16-bit reload timer.
• Internal clock operations
• Underflow operations
• Output pin functions
■ Internal Clock Operations
If the timer is operated using division clock of internal clock, you can select peripheral clock divided by 2,
by 8, or by 32 for the count source.
To start the count operation along with count enable, write "1" into both of CNTE bit and TRG bit in the
control status register.
Trigger input by TRG bit is always enabled when the timer is activated (when CNTE is "1") regardless of
the operation mode.
For the time between the counter start trigger is input and the data of reload register is loaded into the
counter, time of T is required (Peripheral clock machine cycle)
Figure 9.3-1 Counter Activation and Operation.
Count clock
Counter
Reload data
-1
-1
-1
Data load
CNTE bit
TRG bit
T
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CHAPTER 9 16-bit Reload Timer
9.3 Operation of 16-bit Reload Timer
MB91345 Series
■ Underflow Operations
Underflow is regarded as the time when the counter value changes from "0000H" to "FFFFH". Therefore,
the [Reload register setting value + 1] count generates underflow.
When underflow is generated and RELD bit in control status register is "1", the data of reload register is
loaded into the counter and count operation is carried on. When RELD bit is "0", the counter stops at the
"FFFFH".
[RELD=1]
Figure 9.3-2 Underflow operations
Count clock
Counter
0000H
Reload data
-1
-1
-1
Data load
Underflow set
[RELD=0]
Figure 9.3-3 Underflow operations
Count clock
Counter
0000H
FFFFH
Underflow set
■ Output Pin Functions
TOT output pin plays a role of the toggle output inverted by underflow when it is in reload mode, and plays
a role of the pulse output that indicates that counting is in progress when it is in one-shot mode. Output
polarity can be set using the OUTL bit of the register. When OUTL is "0", initial value of the toggle output
is "0" and the one-shot pulse output outputs "1" during the counting. When OUTL is "1", output waveform
is inverted.
Figure 9.3-4 Output Pin Functions [RELD=1, OUTL=0]
Count is started
Underflow
TOT0 to TOT2
CNTE
It is inverted when
OUTL is “1”.
General
port
Activation trigger
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CHAPTER 9 16-bit Reload Timer
9.3 Operation of 16-bit Reload Timer
MB91345 Series
Figure 9.3-5 Output Pin Functions [RELD=0, OUTL=0]
Count is started.
Underflow
It is inverted
when OUTL
is “1”
TOT0 to TOT2
CNTE
General
port
Activation trigger
Status waiting for the activation trigger
■ Operation Status of the Counter
Counter status is determined by CNTE bit in the control status register and the WAIT signal of the internal
signal. Available status for setting is the stop status when CNTE is "0" and WAIT is "1" (STOP status), the
status waiting for startup trigger when CNTE is "1" and WAIT is "1" (WAIT status), and the running status
when CNTE is "1" and WAIT is "0" (RUN status).
Figure 9.3-6 Status Transition of the Counter
Status transition caused by hardware
Reset
Status transition caused by register accesses
STOP
CNTE=0,WAIT=1
The counter holds the value
when it is stopped.
Right after the reset, it is
indeterminate.
CNTE=1
TRG=0
WAIT
CNTE=1
TRG=1
CNTE=1,WAIT=1
RUN
The counter holds the value
when it is stopped.
Right after the reset, it is
indeterminate until the load.
RELD·UF
TRG=1
LOAD
CNTE=1,WAIT=0
Counter is running.
TRG=1
CNTE=1,WAIT=0
RELD·UF
The data of reload register
is loaded into the counter.
End of the load
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CHAPTER 9 16-bit Reload Timer
9.3 Operation of 16-bit Reload Timer
MB91345 Series
■ Caution
• Internal prescaler is enabled for running when bit1 (Timer enable: CNTE) of the control status register
is set to "1" and the trigger (software trigger or external trigger) occurs.
• If the timing of setting the interrupt request flag and the timing of clear overlap, setting the flag has
priority and the clear operation is disabled
• If writing the data into 16-bit timer reload register and the timing of reload overlap, old data is loaded
into the counter and new data will be loaded into the counter at the next reload timing.
• In 16-bit timer register, if the load timing and the count timing overlap, the load (reload) operation has
priority.
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CHAPTER 10
16-bit Compare Timer
This chapter describes the overview, the configuration
and functions of registers, and operation of the 16-bit
compare timer.
10.1 Overview of 16-bit Compare Timer
10.2 Block Diagram of 16-bit Compare Timer
10.3 Compare Timer Registers
10.4 Interrupt by the Compare Timer
10.5 Compare Timer Operation
10.6 Notes on Using the Compare Timer
10.7 Program Example of the Compare Timer
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CHAPTER 10 16-bit Compare Timer
10.1 Overview of 16-bit Compare Timer
10.1
MB91345 Series
Overview of 16-bit Compare Timer
The compare timer consists of one 16-bit free-run timer, four 16-bit output compares,
and four 16-bit input captures.
■ Configuration of the Compare Timer
● 16-bit free-run timer ( 1)
• The 16-bit free-run timer consists of a 16-bit up counter, a control register, a 16-bit compare clear
register, and a prescaler.
• Nine types of counter operation clock settings can be selected (, /2, /4, /8, /16, /32, /64, /128,
and /256; : Peripheral clock).
• A compare clear interrupt is generated when the compare clear register and the 16-bit free-run timer are
compared and judged to be a match.
• When a reset, a software clear, or a compare match with the compare clear register occurs, the counter
value is reset to "0000H".
• The output value of this counter can be used as a clock count for the output compare and input capture.
● 16-bit output compare ( 4)
• The 16-bit output compare consists of four 16-bit compare registers, a compare output latch, and a
compare control register.
When the value of the 16-bit free-run timer matches with the compare register, an interrupt is generated
and the output level is inverted.
• These four compare registers can be operated independently. The output pins and interrupt flags
correspond to the compare registers respectively.
• You can pair the two compare registers to control the output pin. The output pin is inverted by using two
compare registers together.
• The initial value of each output pin can be specified.
• An interrupt is generated when the output compare register matches with the 16-bit free-run timer.
● 16-bit input capture ( 4)
• The input capture consists of four independent external input pins, and capture registers and capture
control registers corresponding to the pins. When the edge of an input signal is detected at the external
pin, the value of the 16-bit free-run timer can be stored in the capture register, and an interrupt is
generated simultaneously.
• For the external input signal, three types of trigger edges (rising edge, falling edge, and both edges) can
be selected.
• These four input captures can be operated independently.
• An interrupt is generated when a valid edge from the external input is detected.
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CHAPTER 10 16-bit Compare Timer
10.2 Block Diagram of 16-bit Compare Timer
MB91345 Series
10.2
Block Diagram of 16-bit Compare Timer
This section shows the block diagram of the compare timer.
■ Block Diagram of the Compare Timer
Figure 10.2-1 Block Diagram of the Compare Timer
→ Output compare 0
Interrupt
Interrupt
Interrupt
Interrupt
→ Output compare 1
→ Output compare 2
→ Output compare 3
16-bit
output compare
RT0 to RT3
Data transfer
from buffer
RT0 to RT3
Counter
value
→ Zero detection 0
Internal data bus
Interrupt
Interrupt
→ Compare clear 0
16-bit
free-run timer
EXCK
Counter
value
Interrupt
Interrupt
Interrupt
Interrupt
FRCK0
Input capture 0
Input capture 1
Input capture 2
Input capture 3
16-bit
input capture
IC0 to IC3
CM71-10132-3E
IC0 to IC3
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CHAPTER 10 16-bit Compare Timer
10.2 Block Diagram of 16-bit Compare Timer
MB91345 Series
■ Block Diagram of the 16-bit Free-run Timer
Figure 10.2-2 Block Diagram of the 16-bit Free-run Timer
φ
STOP
STOP
SCLR
CLK2
CLK1
CLK0
Prescaler
CLR
STOP
16-bit free-run timer
CK
To input capture and
output compare
Transfer
16-bit compare
clear register
Internal data bus
Compare circuit
Interrupt
ICLE
244
Compare clear match
(to output compare)
ICLF
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CM71-10132-3E
CHAPTER 10 16-bit Compare Timer
10.2 Block Diagram of 16-bit Compare Timer
MB91345 Series
■ Block Diagram of the 16-bit Output Compare
Figure 10.2-3 Block Diagram of the 16-bit Output Compare
Count value from free-run timer
Compare register 0, 2
Internal data bus
Compare circuit
Compare register 1, 3
Compare circuit
IOP1
IOP0
IOE1
IOE0
Interrupt
Interrupt
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CHAPTER 10 16-bit Compare Timer
10.2 Block Diagram of 16-bit Compare Timer
MB91345 Series
■ Block Diagram of the 16-bit Input Capture
Figure 10.2-4 Block Diagram of the 16-bit Input Capture
Count value from free-run timer
Capture register 0
Edge detection
ICP0
ICE0
EG01
EG00
IC0
IEI0
Interrupt 0
Internal data bus
Capture register 1
Edge detection
ICP1
ICE1
EG11
EG10
IC1
IEI1
Interrupt 1
Capture register 2
Edge detection
ICP2
ICE2
EG21
EG20
IC2
IEI2
Interrupt 2
Capture register 3
Edge detection
ICP3
ICE3
EG31
EG30
IC3
IEI3
Interrupt 3
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CHAPTER 10 16-bit Compare Timer
10.3 Compare Timer Registers
MB91345 Series
10.3
Compare Timer Registers
This section describes the registers used for the compare timer.
■ Registers of the 16-bit Free-run Timer
Figure 10.3-1 Registers of the 16-bit Free-run Timer
Compare clear buffer register, compare clear register (High order)
CPCLRBH/CPCLRH
Address
bit15
bit14
bit13
bit2
bit11
bit10
bit9
bit8
Initial value
0000D0H
CL15
CL14
CL13
CL12
CL11
CL10
CL09
CL08
11111111B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Compare clear buffer register, compare clear register (Low order)
CPCLRBL/CPCLRL
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000D1H
CL07
CL06
CL05
CL04
CL03
CL02
CL01
CL00
11111111B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Timer data register (High order)
TCDTH
Address
bit15
bit14
bit13
bit2
bit11
bit10
bit9
bit8
Initial value
0000D2H
T15
T14
T13
T12
T11
T10
T09
T08
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Timer data register (Low order)
TCDTL
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000D3H
T07
T06
T05
T04
T03
T02
T01
T00
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
(Continued)
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CHAPTER 10 16-bit Compare Timer
10.3 Compare Timer Registers
MB91345 Series
(Continued)
Timer status control register (High order)
TCCSH
Address
bit15
bit14
bit13
bit2
bit11
bit10
bit9
bit8
Initial value
0000D4H
ECKE





ICLR
ICRE
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Timer status control register (Low order)
TCCSL
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000D5H

STOP

SCLR
CLK3
CLK2
CLK1
CLK0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
248
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CHAPTER 10 16-bit Compare Timer
10.3 Compare Timer Registers
MB91345 Series
■ Registers of the 16-bit Output Compare
Figure 10.3-2 Registers of the 16-bit Output Compare
Output compare buffer register, output compare register (High order)
OCCPBH0 to 3/OCCPH0 to 3
Address
0000E8H
0000EAH
0000ECH
0000EEH
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
XXXXXXXXB
OP15
OP14
OP13
OP12
OP11
OP10
OP09
OP08
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit1
bit0
Initial value
XXXXXXXXB
Output compare buffer register, output compare register (Low order)
OCCPBL0 to 3/OCCPL0 to 3
Address
0000E9H
0000EBH
0000EDH
0000EFH
bit7
bit6
bit5
bit4
bit3
bit2
OP07
OP06
OP05
OP04
OP03
OP02
OP01
OP00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Compare control register 1, 3 (High order)
OCSH01, OCSH23
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
0000F0H
0000F2H



CMOD


OTD1
OTD0
11101100B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Compare control register 0, 2 (Low order)
OCSL01, OCSL23
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000F1H
0000F2H
IOP1
IOP0
IOE1
IOE0


CST1
CST0
00001100B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
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CHAPTER 10 16-bit Compare Timer
10.3 Compare Timer Registers
MB91345 Series
■ Registers of the 16-bit Input Capture
Figure 10.3-3 Registers of the 16-bit Input Capture
Input capture data register (High order)
IPCPH0 to IPCPH3
Address
0000DCH
0000DEH
0000E0H
0000E2H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
XXXXXXXXB
CP15
CP14
CP13
CP12
CP11
CP10
CP09
CP08
R
R
R
R
R
R
R
R
Input capture data register (Low order)
IPCPL0 to IPCPL3
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000DDH
0000DFH
0000E1H
0000E3H
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
XXXXXXXXB
R
R
R
R
R
R
R
R
Input capture status control register (ch.2, ch.3) (High order)
ICSH23
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
0000E6H






IEI3
IEI2
XXXXXX00B






R
R
Input capture status control register (ch.0, ch.1) (High order)
ICSH01
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
0000E4H






IEI3
IEI2
XXXXXX00B






R
R
Input capture status control register (ch.2, ch.3)
ICSL23
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000E7H
ICP3
ICP2
ICE3
ICE2
EG31
EG30
EG21
EG20
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Input capture status control register (ch.0, ch.1)
ICSL01
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000E5H
ICP1
ICP0
ICE1
ICE0
EG11
EG10
EG01
EG00
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
R:
Read only
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CHAPTER 10 16-bit Compare Timer
10.3 Compare Timer Registers
MB91345 Series
10.3.1
Compare Clear Register (CPCLRB/CPCLR)
The compare clear register (CPCLRB/CPCLR) is a 16-bit register which is used for the
comparison with the free-run timer.
■ Compare Clear Register (CPCLRB/CPCLR)
Figure 10.3-4 Compare Clear Register (CPCLRB/CPCLR)
Compare clear register (High order)
CPCLRBH/CPCLRH
Address
bit15
bit14
bit13
bit2
bit11
bit10
bit9
bit8
Initial value
0000D0H
CL15
CL14
CL13
CL12
CL11
CL10
CL09
CL08
11111111B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Compare clear register (Low order)
CPCLRBL/CPCLRL
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000D1H
CL07
CL06
CL05
CL04
CL03
CL02
CL01
CL00
11111111B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
The compare clear register is used to be compared with the count value of the 16-bit free-run timer. When
this register matches with the count value of the 16-bit free-run timer, the 16-bit free-run timer is reset to
"0000H". To access to this register, use a half-word or word access instruction.
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CHAPTER 10 16-bit Compare Timer
10.3 Compare Timer Registers
10.3.2
MB91345 Series
Timer Data Register (TCDTH/TCDTL)
The timer data register (TCDTH/TCDTL) is used to read the count value of the 16-bit
free-run timer.
■ Timer Data Register (TCDTH/TCDTL)
Figure 10.3-5 Timer Data Register (TCDTH/TCDTL)
Timer data register (High order)
TCDTH
Address
bit15
bit14
bit13
bit2
bit11
bit10
bit9
bit8
Initial value
0000D2H
T15
T14
T13
T12
T11
T10
T09
T08
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Timer data register (Low order)
TCDTL
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000D3H
T07
T06
T05
T04
T03
T02
T01
T00
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
The timer data register is used to read the count value of the 16-bit free-run timer. When a reset occurs, the
count value is immediately cleared to "0000H". The timer value can be specified by writing a value into this
register. The value, however, must be written while the timer has stopped (STOP (bit6) in the low-order
byte of the timer status control register (TCCSL) = 1). To access to the timer data register, use a half-word
or word access instruction.
The 16-bit free-run timer is initialized as soon as one of the following factors occurs:
• Reset
• Clear bit (SCLR: bit4) of the timer status control register (TCCSL) = 1
• The compare clear register matches with the timer count value.
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CHAPTER 10 16-bit Compare Timer
10.3 Compare Timer Registers
MB91345 Series
10.3.3
Timer Status Control Register (TCCSH/TCCSL)
The timer status control register (TCCSH/TCCSL) is a 16-bit register which is used to
control the operation of the 16-bit free-run timer.
■ Timer Status Control Register, High-order Byte (TCCSH)
Figure 10.3-6 Timer Status Control Register, High-order Byte (TCCSH)
Timer status control register (higher order)
TCCSH
Address
bit15
0000D4H
ECKE
R/W
bit14
R/W
bit13
R/W
bit12
R/W
bit11
bit10
R/W
bit9
bit8
ICLR
ICRE
R/W
R/W
R/W
ICRE
Compare clear interrupt request permission bit
0
Disable interrupt requests.
1
Enable interrupt requests.
Compare clear interrupt flag bit
ICLR
Read
Write
0
Compare clear does not match.
This bit is cleared.
1
Compare clear matches.
This bit is not affected.
bit14 to bit10
ECKE
R/W : Readable/writable
: Reserved
: Initial value
CM71-10132-3E
Initial value: 00000000B
Reserved
0
Initial value
1
Setting disabled
Clock selection bit
0
Internal clock
1
External clock
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CHAPTER 10 16-bit Compare Timer
10.3 Compare Timer Registers
MB91345 Series
Table 10.3-1 Timer Status Control Register, High-order Byte (TCCSH)
Bit name
bit15
ECKE:
Clock selection
bit
bit14 to bit10 Reserved
254
bit9
ICLR:
Compare clear
interrupt flag bit
bit8
ICRE:
Compare clear
interrupt request
permission bit
Function
• This bit is used to select either of the internal clock or external clock to be
used as the count clock of the 16-bit free-run timer.
• When this bit is set to "0":
The internal clock is selected. To select the count clock frequency, you
also need to select the clock frequency selection bits (CLK3 to CLK0: bit3
to bit0) of the TCCSL register.
• When this bit is set to "1":
The external clock is selected. The external clock is input through the
FRCK0 pin. Consequently, you must enable the external clock input by
writing "0" into bit7 of the port direction register (DDR 1).
Note:
The count clock is changed as soon as this bit is set. Consequently, this bit
must be changed while the output compare and input capture have stopped.
These bits must be set to "0".
• When the compare clear value matches with the 16-bit free-run timer
value, this bit is set to "1".
• When this bit is set to "0": This bit is cleared.
• When this bit is set to "1": This bit is not affected.
• In read-modify-write (RMW) instruction operation, the read value is
always "1".
Note:
This bit is set to "1" when an interrupt specified with the interrupt mask
selection bit is generated.
When no interrupt is generated, this bit is not set to "1".
When this bit and the compare clear interrupt flag bit (ICLR: bit9) are set to
"1", an interrupt request to the CPU is generated.
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CHAPTER 10 16-bit Compare Timer
10.3 Compare Timer Registers
MB91345 Series
■ Timer Status Control Register, Low-order Byte (TCCSL)
Figure 10.3-7 Timer Status Control Register, Low-order Byte (TCCSL)
Timer status control register (low order)
TCCSL
bit7
bit6
bit5
Address:
STOP
0000D5H
R/W
R/W
R/W
bit4
bit3
bit2
bit1
bit0
SCLR
CLK3
CLK2
CLK1
CLK0
R/W
R/W
R/W
R/W
R/W
Initial value: 01000000B
Clock frequency selection bits
CLK3
CLK2
CLK1
CLK0
0
0
0
0
31.25ns
62.5ns
125ns
0.25µs
1µs
0
0
0
1
62.5ns
125ns
0.25µs
0.5µs
2µs
0
0
1
0
125ns
0.25µs
0.5µs
1µs
4µs
0
0
1
1
0.25µs
0.5µs
1µs
2µs
8µs
0
1
0
0
0.5µs
1µs
2µs
4µs
16µs
0
1
0
1
1µs
2µs
4µs
8µs
32µs
0
1
1
0
2µs
4µs
8µs
16µs
64µs
0
1
1
1
4µs
8µs
16µs
32µs
128µs
1
0
0
0
8µs
16µs
32µs
64µs
256µs
Count
clock
Other settings disabled
SCLR
0
1
R/W : Readable/writable
: Reserved
: Initial value
CM71-10132-3E
Timer clear bit
Read
Write
Read value is always "0".
The counter is not initialized.
The counter is initialized to "0000H".
bit5
Reserved
0
Initial value
1
Setting disabled
STOP
Timer permission bit
0
Enable (Start) counting.
1
Disable (Stop) counting.
bit7
Reserved
0
Initial value
1
Setting disabled
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CHAPTER 10 16-bit Compare Timer
10.3 Compare Timer Registers
MB91345 Series
Table 10.3-2 Timer Status Control Register, Low-order Byte (TCCSL)
Bit name
256
Function
bit7
Reserved
This bit must be set to "0".
bit6
• This bit is used to start/stop the count of the 16-bit free-run timer.
• When this bit is set to "0":
The count of the 16-bit free-run timer starts.
STOP:
• When this bit is set to "1":
Timer permission
The count of the 16-bit free-run timer stops.
bit
Note:
When the 16-bit free-run timer stops, the operation of the output compare
also stops.
bit5
Reserved
This bit must be set to "0".
bit4
SCLR:
Timer clear bit
• This bit is used to initialize the 16-bit free-run timer to "0000H".
• When this bit is set to "1":
The 16-bit free-run timer is initialized to "0000H" at the next count clock.
• The read value is always "0".
Note:
Even when "1" is written to this bit, a 0 detection interrupt is not generated.
If this bit is set to "1" and then "0" is written to this bit before the next
count clock, the timer is not cleared.
bit3
to
bit0
CLK3 to CLK0:
Clock frequency
selection bits
• These bits are used to select the count clock frequency of the 16-bit freerun timer.
• The count clock is changed as soon as these bits are set. Consequently,
these bits must be changed while the output compare and input capture
have stopped.
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CHAPTER 10 16-bit Compare Timer
10.3 Compare Timer Registers
MB91345 Series
10.3.4
Output Compare Register (OCCPH0 to OCCPH3/OCCPL0
to OCCPL3)
The output compare register (OCCPH0 to OCCPH3/OCCPL0 to OCCPL3) is a register
used for the comparison with the free-run timer.
■ Output Compare Register (OCCPH0 to OCCPH3/OCCPL0 to OCCPL3)
Figure 10.3-8 Output Compare Register (OCCPH0 to OCCPH3/OCCPL0 to OCCPL3)
Output compare register (High order)
OCCPH0 to OCCPH3
Address
bit15
bit14
bit13
bit2
bit11
bit10
bit9
bit8
Initial value
0000E8H
0000EAH
0000ECH
0000EEH
OP15
OP14
OP13
OP12
OP11
OP10
OP09
OP08
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output compare register (Low order)
OCCPL0 to OCCPL3
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000E9H
0000EBH
0000EDH
0000EFH
OP07
OP06
OP05
OP04
OP03
OP02
OP01
OP00
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
The output compare register is a 16-bit register used to be compared with the count value of the 16-bit freerun timer. Before enabling the timer operation, set a value to the output compare register (OCCPH/
OCCPL).
When the value of the output compare register matches with the count value of the 16-bit free-run timer, a
compare signal is generated, and the compare match interrupt flag bit (IOP1, IOP0 (bit7, bit6) in the loworder byte of the compare control register (OCSL0, OCSL2) is set.
To access to this register, use a half-word or word access instruction.
The free-run timer described above concerns the operating status of the free-run timer selected by the
output compare.
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CHAPTER 10 16-bit Compare Timer
10.3 Compare Timer Registers
10.3.5
MB91345 Series
Compare Control Register (OCSH0 to OCSH3/OCSL0 to
OCSL3)
The compare control register is used to control the output level, output permission,
output level inversion mode, compare operation permission, compare match interrupt
permission, and compare match interrupt flag of RT0 to RT3.
■ Compare Control Register, High-order Byte (OCSH1, OCSH3)
Figure 10.3-9 Compare Control Register, High-order Byte (OCSH1, OCSH3)
Compare control register (High order)
OCSH1, OCSH3
bit14
bit15
bit13
Address
0000F0H
0000F2H
R/W
R/W
bit12
bit11
R/W
R/W
OTD0
0
1
OTD1
0
1
R/W : Readable/writable
: Reserved
: Initial value
258
bit10
CMOD
R/W
bit9
bit8
OTD1
OTD0
R/W
R/W
Initial value: 11101100B
Output level bit
Read
Write
Current output value of RT0, RT2
"0" is output from RT0, RT2
.
"1" is output from RT0, RT2
.
Output level bit
Read
Write
Current output value of RT1, RT3
"0" is output from RT1, RT3
.
"1" is output from RT1,RT3
bit10
Reserved
0
Initial value
1
Setting disabled
bit11
Reserved
0
Initial value
1
Setting disabled
CMOD
Output level inversion mode bit
0
RT0, RT2 : The level is inverted as sonn as the match with
compare registers 0, 2 occurs.
RT1, RT3 : The level is inverted as sonn as the match with
compare registers 1, 3 occurs.
1
RT0, RT2 : The level is inverted as sonn as the match with
compare registers 0, 2 occurs.
RT1, RT3 : The level is inverted as sonn as the match with
compare registers (0 or 1) and (2 or 3) occurs.
bit13
Reserved
0
Setting disabled
1
Initial value
bit14
Reserved
0
Setting disabled
1
Initial value
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CM71-10132-3E
CHAPTER 10 16-bit Compare Timer
10.3 Compare Timer Registers
MB91345 Series
Table 10.3-3 Compare Control Register, High-order Byte (OCSH1, OCSH3)
Bit name
bit15
Unused bit
bit14,
bit13
Reserved bits
bit12
bit11,
bit10
Reserved bits
bit8
• The read value is indeterminate.
• Writing to this bit does not affect the operation.
This bit must be set to "1".
CMOD:
Output level
inversion mode
bit
bit9
Function
• This bit is used to switch the pin output level inversion mode as soon as a
match occurs while the pin output is enabled (OTE 1 = 1 or OTE 0 = 1).
• When this bit is set to "0":
And when the compare mode control register (OCMOD) (MOD1x) = 0,
- RT0, RT2: The level is inverted as soon as the 16-bit free-run timer
matches with compare registers 0, 2.
- RT1, RT3: The level is inverted as soon as the 16-bit free-run timer
matches with the compare registers 1, 3.
• When this bit is set to "1":
And when the compare mode control register (OCMOD) (MOD1x) = 0,
- RT0, RT2: The level is inverted as soon as the 16-bit free-run timer
matches with compare registers 0, 2.
- RT1, RT3: The level is inverted as soon as the 16-bit free-run timer
matches with the compare registers (0 or 1) and (2 or 3).
If the compare registers 0, 2 and 1, 3 have the same value, the operation is the
same as the case where only one compare register is used.
This bit must be set to "0".
OTD 1:
Output level bit
• This bit is used to change the pin output level of output compare
1, 3 (RT1, RT3).
• The initial value of the compare pin output is "0".
• Be sure to stop the compare operation before writing a value. The read
value of this bit indicates the output compare value for RT1, RT3.
OTD 0:
Output level bit
• This bit is used to change the pin output level of output compare
0, 2 (RT0, RT2).
• The initial value of the compare pin output is "0".
• Be sure to stop the compare operation before writing a value. The read
value of this bit indicates the output compare value for RT0, RT2.
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CHAPTER 10 16-bit Compare Timer
10.3 Compare Timer Registers
MB91345 Series
■ Compare Control Register, Low-order Byte (OCSL0, OCSL2)
Figure 10.3-10 Compare Control Register, Low-order Byte (OCSL0, OCSL2)
Compare control register (low order)
OCSL0, OCSL2
bit6
bit5
bit7
Address:
0000F1H
IOP1
IOP0
IOE1
0000F3H
R/W
R/W
R/W
bit4
bit3
R/W
R/W
CST0
bit0
CST0
R/W
R/W
Initial value:00001100B
Compare operation permission bit
Disable the compare operation of compare registers 0, 2.
1
Enable the compare operation of compare registers 0, 2.
Compare operation permission bit
0
Disable the compare operation of compare registers 1, 3.
1
Enable the compare operation of compare registers 1, 3.
bit2
Reserved
0
Setting disabled
1
Initial value
bit3
Reserved
0
Setting disabled
1
Initial value
IOE0
Compare match interrupt permission bit
0
Disable the compare match interrupt of compare registers 0, 2.
1
Enable the compare match interrupt of compare registers 0, 2.
IOE1
Compare match interrupt permission bit
0
Disable the compare match interrupt of compare registers 1, 3.
1
Enable the compare match interrupt of compare registers 1, 3.
IOP0
0
1
IOP1
0
260
R/W
bit1
CST1
0
CST1
R/W : Readable/writable
: Reserved
: Initial value
bit2
IOE0
1
Compare match interrupt flag bit
Read
Write
The compare match interrupt of
This bit is cleared.
compare registers 0, 2 does not occur.
The compare match interrupt of
This bit is not affected.
compare registers 0, 2 occurs.
Compare match interrupt flag bit
Read
The compare match interrupt of
compare registers 3 does not occur.
The compare match interrupt of
compare registers 3 occurs.
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Write
This bit is cleared.
This bit is not affected.
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10.3 Compare Timer Registers
MB91345 Series
Table 10.3-4 Compare Control Register, Low-order Byte (OCSL0, OCSL2)
Bit name
Function
IOP1:
Compare match
interrupt flag bit
• This bit is an interrupt flag which indicates that compare registers 1, 3
match with the value of the 16-bit free-run timer.
• This bit is set to "1" when the values of the compare registers match with
the value of the 16-bit free-run timer.
• If this bit is set while the compare match interrupt permission bit (IOE1:
bit5) is enabled, an output compare interrupt occurs.
• When this bit is set to "0": This bit is cleared.
• When this bit is set to "1": This bit is not affected.
• In read-modify-write (RMW) instruction, the read value is always "1".
bit6
IOP0:
Compare match
interrupt flag bit
• This bit is an interrupt flag which indicates that compare registers 0, 2
match with the value of the 16-bit free-run timer.
• This bit is set to "1" when the values of the compare registers match with
the value of the 16-bit free-run timer.
• If this bit is set while the compare match interrupt permission bit (IOE0:
bit4) is enabled, an output compare interrupt occurs.
• When this bit is set to "0": This bit is cleared.
• When this bit is set to "1": This bit is not affected.
• In read-modify-write (RMW) instruction, the read value is always "1".
bit5
IOE1:
Compare match
interrupt
permission bit
• This bit is used to enable the output compare interrupt of compare registers
1, 3.
• If the compare match interrupt flag bit (IOP1: bit7) is set while "1" is
written in this bit, an output compare interrupt occurs.
bit4
IOE0:
Compare match
interrupt
permission bit
• This bit is used to enable the output compare interrupt of compare registers
0, 2.
• If the compare match interrupt flag bit (IOP0: bit6) is set while "1" is
written in this bit, an output compare interrupt occurs.
bit3,
bit2
Reserved bits
bit7
bit1
bit0
This bit must be set to "0".
CST1:
Compare
operation
permission bit
• This bit is used to enable the compare operation between the 16-bit freerun timer and compare registers 1, 3.
• Be sure to write values into compare registers 1, 3 and the timer data
register (TCDT) before enabling the compare operation.
Note:
Since the output compare is synchronized with the 16-bit free-run timer
clock, stopping the 16-bit free-run timer also stops the compare operation.
CST0:
Compare
operation
permission bit
• This bit is used to enable the compare operation between the 16-bit freerun timer and compare registers 0, 2.
• Be sure to write values into compare register 0, 2 and the timer data
register (TCDT) before enabling the compare operation.
Note:
Since the output compare is synchronized with the 16-bit free-run timer
clock, stopping the 16-bit free-run timer also stops the 0 detection and
compare operation.
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10.3.6
MB91345 Series
Input Capture Data Register (IPCPH0 to IPCPH3/IPCPL0
to IPCPL3)
The input capture data register is used to retain the count value of the free-run timer
when a valid edge of the input waveform is detected.
■ Input Capture Data Register (IPCPH0 to IPCPH3/IPCPL0 to IPCPL3)
Figure 10.3-11 Input Capture Data Register (IPCPH0 to IPCPH3/IPCPL0 to IPCPL3)
Input capture data register (High order)
IPCPH0 to IPCPH3
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
0000DCH
0000DEH
0000E0H
0000E2H
CP15
CP14
CP13
CP12
CP11
CP10
CP09
CP08
XXXXXXXXB
R
R
R
R
R
R
R
R
Input capture data register (Low order)
IPCPL0 to IPCPL3
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000DDH
0000DFH
0000E1H
0000E3H
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
XXXXXXXXB
R
R
R
R
R
R
R
R
R: Read only
This register is used to store the value of the free-run timer when a valid edge of the corresponding external
pin input waveform is detected. (To access to this register, use a half-word or word access instruction. Data
cannot be written to this register.)
The free-run timer described above concerns the operating status of the free-run timer selected by the input
capture.
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10.3.7
Input Capture Status Control Register (ICSH01, ICSL01/
ICSH23, ICSL23)
The input capture status control/PPG output control register (ICSH01, ICSL01/ICSH23,
ICSL23) is used to control the edge selection, interrupt request permission, and
interrupt request flag. It is also used to indicate a valid edge detected by input capture 2
and 3.
■ Input Capture Status Control Register (ch.2, ch.3) (ICSH23)
Figure 10.3-12 Input Capture Status Control Register (ch.2, ch.3) (ICSH23)
ICSH23
Address:
0000E6H
Input Capture Status Control Register(High order)
bit15
bit14
bit13
bit12
IEI2
0
1
IEI3
0
1
bit11
bit10
bit9
bit8
IEI3
IEI2
R/W
R/W
Initial value: XXXXXX00B
Effective edge instruction bit (input capture2)
Falling edge are detected
Rising edge are detected
Effective edge instruction bit (input capture3)
Falling edge are detected
Rising edge are detected
R/W : Readable/writable
: Undefined
: Initial value
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Table 10.3-5 Input Capture Status Control Register (ch.2, ch.3) , (ICSH23)
Bit name
bit15
to
bit10
bit9
bit8
264
Function
• The read value is indeterminate.
• Writing to these bits has no effect on operation.
Undefined bits
IEI3:
Effective edge
instruction bit
(input capture3)
• This bit is the effective edge instruction bit for the input capture3 that indicates a rising
edge or falling edge has been detected.
• When a falling edge is detected, "0" is written to this bit.
• When a rising edge is detected, "1" is written to this bit.
• This is a read-only bit.
Note:
When EG31, EG30: bit3, bit2 in the input capture status control register lower (ICSL23) are
"00B", the read value doesn't have any meaning.
IEI2:
Effective edge
instruction bit
(input capture2)
• This bit is the effective edge instruction bit for the input capture2 that indicates a rising
edge or falling edge has been detected.
• When a falling edge is detected, "0" is written to this bit.
• When a rising edge is detected, "1" is written to this bit.
• This is a read-only bit.
Note:
When EG21, EG20: bit1, bit0 in the input capture status control register lower (ICSL23)
are "00B", the read value doesn't have any meaning.
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10.3 Compare Timer Registers
MB91345 Series
■ Input Capture Status Control Register (ch.0, ch.1) (ICSH01)
Figure 10.3-13 Input Capture Status Control Register (ch.0, ch.1) (ICSH01)
Input Capture Status Control Register(High order)
bit31
bit30
bit29
bit28
bit27
ICSH01
Address: 0000E4H
IEI2
0
1
IEI3
0
1
bit26
bit25
bit24
IEI1
IEI0
R/W
R/W
Initial value: XXXXXX00B
Effective edge instruction bit (input capture2)
Falling edge are detected
Rising edge are detected
Effective edge instruction bit (input capture3)
Falling edge are detected
Rising edge are detected
R/W : Readable/writable
: Undefined
: Initial value
Table 10.3-6 Input Capture Status Control Register (ch.0, ch.1) , (ICSH01)
Bit name
bit15
to
bit10
bit9
bit8
Function
• The read value is indeterminate.
• Writing to these bits has no effect on operation.
Undefined bits
IEI1:
Effective edge
instruction bit
(input capture1)
• This bit is the effective edge instruction bit for the input capture1 that indicates a rising edge
or falling edge has been detected.
• When a falling edge is detected, "0" is written to this bit.
• When a rising edge is detected, "1" is written to this bit.
• This is a read-only bit.
Note:
When EG11, EG10: bit3, bit2 in the input capture status control register lower (ICSL01) are
"00B", the read value doesn't have any meaning.
IEI0:
Effective edge
instruction bit
(input capture0)
• This bit is the effective edge instruction bit for the input capture0 that indicates a rising edge
or falling edge has been detected.
• When a falling edge is detected, "0" is written to this bit.
• When a rising edge is detected, "1" is written to this bit.
• This is a read-only bit.
Note:
When EG01, EG00: bit1, bit0 in the input capture status control register lower (ICSL01) are
"00B", the read value doesn't have any meaning.
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■ Input Capture Status Control Register (ch.2, ch.3), (ICSL23)
Figure 10.3-14 Input Capture Status Control Register (ch.2, ch.3), (ICSL23)
Input capture status control register (Low order)
ICSL23
Address: 0000E7H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ICP3
ICP2
ICE3
ICE2
EG31
EG30
EG21
EG20
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EG21 EG20
Initial value: 00000000B
Edge selection bits (Input capture 2)
0
0
0
1
No edges are detected. (Stop)
Rising edges are detected.
1
0
Falling edges are detected.
1
1
Both edges are detected.
EG31 EG30
Edge selection bits (Input capture 3)
0
0
0
1
No edges are detected. (Stop)
Rising edges are detected.
1
0
Falling edges are detected.
1
1
Both edges are detected.
ICE2
Interrupt request permission bit (Input capture 2)
0
Disable interrupt requests.
1
Enable interrupt requests.
ICE3
Interrupt request permission bit (Input capture 3)
0
Disable interrupt requests.
1
Enable interrupt requests.
ICP2
Interrupt request flag bit (Input capture 2)
Read
Write
0
Valid edge is not detected.
This bit is cleared.
1
Valid edge is detected.
This bit is not affected.
ICP3
Interrupt request flag bit (Input capture 3)
Read
Write
0
Valid edge is not detected.
This bit is cleared.
1
Valid edge is detected.
This bit is not affected.
R/W : Readable/writable
: Initial value
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Table 10.3-7 Input Capture Status Control Register (ch.2, ch.3), (ICSL23)
Bit name
Function
ICP3:
Interrupt request
flag bit
(Input capture 3)
• This bit is used as an interrupt request flag for input capture 3.
• This bit is set to "1" as soon as a valid edge is detected at the external input
pin.
• If a valid edge is detected while the interrupt request permission bit (ICE3:
bit5) is set, an interrupt can be generated immediately.
• When this bit is set to "0": This bit is cleared.
• When this bit is set to "1": This bit is not affected.
• In read-modify-write (RMW) instruction, the read value is always "1".
bit6
ICP2:
Interrupt request
flag bit
(Input capture 2)
• This bit is used as an interrupt request flag for input capture 2.
• This bit is set to "1" as soon as a valid edge is detected at the external input
pin.
• If a valid edge is detected while the interrupt request permission bit (ICE2:
bit4) is set, an interrupt can be generated immediately.
• When this bit is set to "0": This bit is cleared.
• When this bit is set to "1": This bit is not affected.
• In read-modify-write (RMW) instruction, the read value is always "1".
bit5
ICE3:
Interrupt request
permission bit
(Input capture 3)
bit4
ICE2:
Interrupt request
permission bit
(Input capture 2)
bit3,
bit2
EG31, EG30:
Edge selection
bits
(Input capture 3)
• These bits are used to specify the polarity of valid edges from the external
input of input capture 3.
• These bits are also used to enable the operation of input capture 3.
bit1,
bit0
EG21, EG20:
Edge selection
bits
(Input capture 2)
• These bits are used to specify the polarity of valid edges from the external
input of input capture 2.
• These bits are also used to enable the operation of input capture 2.
bit7
CM71-10132-3E
• This bit is used to enable an input capture interrupt request for input
capture 3.
• If the interrupt request flag bit (ICP3: bit7) is set while "1" is set to this bit,
an interrupt for input capture 3 is generated.
• This bit is used to enable an input capture interrupt request for input
capture 2.
• If the interrupt request flag bit (ICP2: bit6) is set while "1" is set to this bit,
an interrupt for input capture 2 is generated.
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MB91345 Series
■ Input Capture Status Control Register (ch.0, ch.1), (ICSL01)
Figure 10.3-15 Input Capture Status Control Register (ch.0, ch.1), ( ICSL01)
ICSL01
Address:
0000E5H
Input capture status control register (Low order)
bit7
bit6
bit5
bit4
ICP1
ICP0
ICE1
R/W
R/W
R/W
bit3
bit2
bit1
bit0
ICE0
EG11
EG10
EG01
EG00
R/W
R/W
R/W
R/W
R/W
EG01 EG00
Initial value:
00000000B
Edge selection bits (Input capture 0)
0
0
No edges are detected. (Stop)
0
1
Rising edges are detected.
1
0
Falling edges are detected.
1
1
Both edges are detected.
EG11 EG10
Edge selection bits (Input capture 1)
0
0
0
1
No edges are detected. (Stop)
Rising edges are detected.
1
0
Falling edges are detected.
1
1
Both edges are detected.
ICE0
Interrupt request permission bit (Input capture 0)
0
Disable interrupt requests.
1
Enable interrupt requests.
ICE1
Interrupt request permission bit (Input capture 1)
0
Disable interrupt requests.
1
Enable interrupt requests.
ICP0
Interrupt request flag bit (Input capture 0)
Read
Write
0
Valid edge is not detected.
This bit is cleared.
1
Valid edge is detected.
This bit is not affected.
ICP1
Interrupt request flag bit (Input capture 1)
Read
Write
0
Valid edge is not detected.
This bit is cleared.
1
Valid edge is detected.
This bit is not affected.
R/W : Readable/writable
: Initial value
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Table 10.3-8 Input Capture Status Control Register (ch.0, ch.1), (ICSL01)
Bit name
Function
ICP1:
Interrupt request
flag bit
(Input capture 1)
• This bit is used as an interrupt request flag for input capture 1.
• This bit is set to "1" as soon as a valid edge is detected at the external input
pin.
• If a valid edge is detected while the interrupt permission bit (ICE1: bit5) is
set, an interrupt is generated immediately.
• When this bit is set to "0": This bit is cleared.
• When this bit is set to "1": This bit is not affected.
• In read-modify-write (RMW) instruction, the read value is always "1".
bit6
ICP0:
Interrupt request
flag bit
(Input capture 0)
• This bit is used as an interrupt request flag for input capture 0.
• This bit is set to "1" as soon as a valid edge is detected at the external input
pin.
• If a valid edge is detected while the interrupt permission bit (ICE0: bit4) is
set, an interrupt is generated immediately.
• When this bit is set to "0": This bit is cleared.
• When this bit is set to "1": This bit is not affected.
• In read-modify-write (RMW) instruction, the read value is always "1".
bit5
ICE1:
Interrupt request
permission bit
(Input capture 1)
bit4
ICE0:
Interrupt request
permission bit
(Input capture 0)
bit3,
bit2
EG11, EG10:
Edge selection
bits
(Input capture 1)
• These bits are used to specify the polarity of valid edges from the external
input of input capture 1.
• These bits are also used to enable the operation of input capture 1.
bit1,
bit0
EG01, EG00:
Edge selection
bits
(Input capture 0)
• These bits are used to specify the polarity of valid edges from the external
input of input capture 0.
• These bits are also used to enable the operation of input capture 0.
bit7
CM71-10132-3E
• This bit is used to enable an input capture interrupt request for input
capture 1.
• If the interrupt request flag bit (ICP1: bit7) is set while "1" is set to this bit,
an interrupt for input capture 1 is generated.
• This bit is used to enable an input capture interrupt request for input
capture 0.
• If the interrupt request flag bit (ICP0: bit6) is set while "1" is set to this bit,
an interrupt for input capture 0 is generated.
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10.4 Interrupt by the Compare Timer
10.4
MB91345 Series
Interrupt by the Compare Timer
The compare timer can generate interrupts for the 16-bit free-run timer, the 16-bit output
compare, and the 16-bit input capture respectively.
■ Interrupt for the 16-bit Free-run Timer
Table 10.4-1 shows the interrupt control bits and interrupt factor for the 16-bit free-run timer.
Table 10.4-1 Interrupt Control Bits and Interrupt Factor for the 16-bit Free-run Timer
Compare clear of 16-bit free-run timer
Interrupt request flag bit
ICLR (bit9) in the high-order byte of the timer status register (TCCSH)
Interrupt request permission bit
ICRE (bit8) in the high-order byte of the timer status register (TCCSH)
Interrupt factor
The value of the 16-bit free-run timer matches with the compare clear register
(CPCLRB/CPCLR).
When the value of the 16-bit free-run timer matches with the compare clear register (CPCLRB/CPCLR),
ICLR (bit9) of the timer status register (TCCSH) is set to "1". If an interrupt request is enabled in this status
(ICRE (bit8) of TCCSH register = 1), an interrupt request is output to the interrupt controller.
■ Interrupt for the 16-bit Output Compare
Table 10.4-2 shows the interrupt control bits and interrupt factor for the 16-bit output compare.
Table 10.4-2 Interrupt Control Bits and Interrupt Factor for the 16-bit Output Compares 0 to 3
16-bit output compares 0, 1
16-bit output compares 2, 3
Interrupt request flag bit
IOP1, IOP0 (bit7, bit6) in the loworder byte of the compare control
register (OCS01)
IOP1, IOP0 (bit7, bit6) in the low-order
byte of the compare control register
(OCS23)
Interrupt request permission bit
IOE1, IOE0 (bit5, bit4) in the loworder byte of the compare control
register (OCS01)
IOE1, IOE0 (bit5, bit4) in the low-order
byte of the compare control register
(OCS23)
Interrupt factor
The value of the 16-bit free-run timer
matches with the output compare
register (OCCP0, OCCP1)
The value of the 16-bit free-run timer
matches with the output compare register
(OCCP2, OCCP3)
When the value of the 16-bit free-run timer matches with the output compare register (OCCP0 to OCCP3),
IOP1, IOP0 (bit7, bit6) in the low-order byte of the compare control register (OCS01, OCS23) are set to "1".
If an interrupt request is enabled in this status (IOE1, IOE0 (bit5, bit4) of OCS01, OCS23 registers = 11B),
an interrupt request is output to the interrupt controller.
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10.4 Interrupt by the Compare Timer
MB91345 Series
■ Interrupt for the 16-bit Input Capture
Table 10.4-3 shows the interrupt control bits and interrupt factor for the 16-bit input capture.
Table 10.4-3 Interrupt control bits and interrupt factor for the 16-bit input captures 0 to 3
16-bit input captures 0, 1
16-bit input captures 2, 3
Interrupt request flag bit
ICP1, ICP0 (bit7, bit6) in the low-order
byte of the input capture status control
register (ICSL01)
ICP3, ICP2 (bit7, bit6) in the low-order
byte of the input capture status control
register (ICSL23)
Interrupt request permission bit
ICE1, ICE0 (bit5, bit4) in the low-order
byte of the input capture status control
register (ICSL01)
IOE3, IOE2 (bit5, bit4) in the low-order
byte of the input capture status control
register (ICSL23)
Interrupt factor
A valid edge is detected at pins IC0, IC1 A valid edge is detected at pins IC2, IC3
As for the 16-bit input capture, when a valid edge is detected at pins IC0 to IC3, ICP3, ICP2, ICP1, ICP0
(bit7, bit6 for all cases) of the input capture status control register (ICSL01, ICSL23) are set to "11B". If an
interrupt request is enabled in this status (ICE3, ICE2, ICE1, ICE0 (bit5, bit4 for all cases) of ICSL01 and
ICSL23 registers = 11B), an interrupt request is output to the interrupt controller.
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10.5 Compare Timer Operation
10.5
MB91345 Series
Compare Timer Operation
This section describes the operation of the compare timer.
■ Compare Timer Operation
● 16-bit free-run timer
When count operation is enabled, the 16-bit free-run timer starts counting up from the value specified in the
timer data register (TCDT). The count value is used as reference time for the 16-bit output compare and 16bit input capture.
● 16-bit output compare
The 16-bit output compare is used to compare "the value set in the specified output compare register" with
"the value of the 16-bit free-run timer". When match is detected, an interrupt flag is set and the output level
is inverted.
● 16-bit input capture
The 16-bit input capture is used to detect a valid edge being specified.
When a valid edge is detected, an interrupt flag is set, and the value of the 16-bit free-run timer is captured
and stored in the input capture data register.
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10.5 Compare Timer Operation
MB91345 Series
10.5.1
Operation of the 16-bit Free-run Timer
The compare timer has one unit of a 16-bit free-run timer. After a reset is completed, the
16-bit free-run timer starts counting up from the value specified in the timer data
register (TCDT). The count value is used as reference time for the 16-bit output compare
and 16-bit input capture.
■ Clearing the Timer
The count value of the 16-bit free-run timer is cleared at one of the following events:
• When the match with the compare clear register is detected by the up-count mode (MODE (bit5) of the
TCCSL register = 0).
• When "1" is written in SCLR (bit4) of the TCCSL register during operation.
• When "0000H" is written in the TCDT register while operation is stopped.
• When the timer is reset.
When the timer is reset, the counter is cleared immediately. When a software clear occurs or when the
match with the compare clear register is detected, the counter is cleared in synchronization with the count
timing.
Figure 10.5-1 Timing of clearing the 16-bit free-run timer
φ
Compare clear
N
Register value
Compare match
Count value
N
0000H
■ Counting Up
The 16-bit free-run timer is an up counter.
The counter starts counting up from the value of the predefined timer data register (TCDT) and continue
counting until the count value matches with the value of the compare clear register (CPCLRB/CPCLR).
The counter is cleared to "0000H" and starts counting up again.
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MB91345 Series
■ Compare Clear Register
The compare clear register (CPCLRB/CPCLR) writes data to be compared.
Figure 10.5-2 Writing data of compare clear register
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Start of timer operation
Compare clear match
Reset
Compare clear
register
BFFFH
7FFFH
FFFFH
■ Timer Interrupt
The 16-bit free-run timer can generate a compare clear interrupt.
A compare clear interrupt is generated when the timer value matches with the value of the compare clear
register (COCLRB/COCLR).
Figure 10.5-3 Generating Compare Clear Interrupt
Count value
N-1
N
0
1
Compare clear interrupt
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10.5 Compare Timer Operation
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■ Selected External Count Clock
The 16-bit free-run timer is incremented based on the input clock (internal or external clock). When an
external clock is selected, the external clock mode is selected (ECKE (bit15) of the TCCSH register = 1). If
the initial value of the external input is "1", the 16-bit free-run timer starts counting up at a rising edge.
After that, it counts up at both edges. If the initial value of the external input is "0", the timer starts counting
up at a falling edge. After that, it counts up at both edges.
Figure 10.5-4 Count Timing of the 16-bit Free-run Timer
External clock input
TCCSH: ECKE bit
Count clock
Count value
N
N+1
N+2
Note:
The external clock input is counted at both edges of the external clock.
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10.5 Compare Timer Operation
10.5.2
MB91345 Series
Operation of the 16-bit Output Compare
The output compare is used to compare the value set in the specified compare clear
register with the value of the 16-bit free-run timer. When match is detected, an interrupt
flag is set and the output level is inverted.
■ Operation of the 16-bit Output Compare (Inversion Mode)
● The compare operation can be executed at each channel (CMOD (bit12) in the high-order byte of the
compare control register (OCSH1, OCSH3) = 0).
Figure 10.5-5 Example of Output Waveform if Compare Registers 0 and 1 are Used Independently
when the Output Initial Value is "0"
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Reset
Compare
register 0
Compare
register 1
Time
BFFFH
7FFFH
RT0
RT1
Interrupt by
compare 0
Interrupt by
compare 1
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10.5 Compare Timer Operation
MB91345 Series
● The output level can be changed by using a pair of compare registers (CMOD (bit12) in the high-order
byte of the compare control register (OCS01, OCS23) = 1).
Figure 10.5-6 Example of Output Waveform if Compare Registers 0 and 1 are Used as a Pair
when the Output Initial Value is "0"
Count value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare
register 0
Compare
register 1
BFFFH
7FFFH
Corresponds to
compare 0
Corresponds to
compare 0 and 1
RT0
RT1
Interrupt by
compare 0
Interrupt by
compare 1
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10.5 Compare Timer Operation
MB91345 Series
■ Timing of the 16-bit Output Compare Operation
If the value of the free-run timer matches with the value of the compare register, the output compare
generates a compare match signal, inverts the output, and generates an interrupt. When a compare match
occurs, the output is inverted in synchronization with the count timing of the counter.
Figure 10.5-7 Interrupt Timing of the Compare Register
N+1
N
Count value
N
Compare register
Compare match
Interrupt
Figure 10.5-8 Timing of Changes in the Pin Output
Count value
Compare register
N
N+1
N
N+1
N
Compare match signal
Pin output
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10.5 Compare Timer Operation
MB91345 Series
10.5.3
Operation of the 16-bit Input Capture
The input capture is used to detect a valid edge being specified. When a valid edge is
detected, an interrupt flag is set and the value of the 16-bit free-run timer is loaded to
the capture register.
■ Operation of the 16-bit Input Capture
Figure 10.5-9 Timing Example of Input Capture
Count value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
IC0
IC1
IC example
Capture
register 0
Capture
register 1
Capture register
example
Indeterminate
3FFFH
Indeterminate
Indeterminate
7FFFH
BFFFH
3FFFH
Interrupt by
capture 0
Interrupt by
capture 1
Interrupt by
capture example
Capture 0: Rising edge
Capture 1: Falling edge
Capture example: Both edges
CM71-10132-3E
Another generation of an interrupt
by a valid edge
Interrupt clear by software.
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10.5 Compare Timer Operation
MB91345 Series
■ Input Timing of the 16-bit Input Capture
Figure 10.5-10 Timing Example of the 16-bit Input Capture for Input Signals
Machine clock φ
Count value
Input
N
N+1
Valid edge
Capture input
Capture signal
Capture register
N+1
Interrupt
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CHAPTER 10 16-bit Compare Timer
10.6 Notes on Using the Compare Timer
MB91345 Series
10.6
Notes on Using the Compare Timer
This section describes the notes on using the components of the compare timer.
■ Notes on Using the 16-bit Free-run Timer
● Notes on setting by program
• When a reset or a software clear is executed (SCLR (bit4) of the TCCSL register = 1), the timer value is
reset to "0000H".
• If the count is started when the compare and count values match, a compare clear flag is not set.
● Notes on interrupt
When "1" is set to the ICLR (bit9) in the high-order byte of the timer status control register (TCCSH), and
then an interrupt request is enabled (ICRE (bit8) of the TCCSH register = 1), the control cannot return from
the interrupt processing. Note that ICLR (bit9) must be cleared.
■ Notes on Using the 16-bit Output Compare
Notes on interrupt
When "11B" is set to IOP1, IOP0 (bit7, bit6) in the low-order byte of the compare control register (OCSL0,
OCSL2), and then an interrupt request is enabled (IOE1, IOE0 (bit6, bit5) of the OCSL register = 11B), the
control cannot return from the interrupt processing. Note that IOP1, IOP0 bits must be cleared.
■ Notes on Using the 16-bit Input Capture
Notes on interrupt
• When "1" is set to ICP3, ICP2, ICP1, ICP0 (bit7, bit6 for all cases) in the low-order byte of the input
capture status control register (ICSL01, ICSL23), and then an interrupt request is enabled (ICE3, ICE2,
ICE1, ICE0 (bit5, bit4 for all cases) of the ICSL01, ICSL23 registers = 11B), the control cannot return
from the interrupt processing. Note that ICP3, ICP2, ICP1, ICP0 (bit7, bit6 for all cases) must be
cleared.
• If the input capture pin (IC) level is switched during the period between when the ICP3, ICP2, ICP1,
ICP0 bits are set and when the interrupt routine has been processed, the valid edge designation bits of
ICP3, ICP2, ICP1, ICP0 (IEI3, IEI2 (bit9, bit8) of the ICSH23 register, IEI1, IEI0 (bit9, bit8) of the
ICSH01 register) indicate the latest detected edge.
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10.7 Program Example of the Compare Timer
10.7
MB91345 Series
Program Example of the Compare Timer
This section shows the program example of the components of the compare timer.
■ Program Example of the 16-bit Free-run Timer
● Details of processing
• When the 16-bit free-run timer counts 4 ms, it generates a compare clear interrupt.
• This timer is used to regenerate the compare clear timer in the up-count mode.
• The setting of 16 MHz is for the peripheral clock, and 62.5 ns is for the count clock.
● Coding example
ICR32
.EQU 000460H
; Compare clear interrupt control register of
; the 16-bit free-run timer
TCCSH
.EQU 0000A8H
CPCLRBH .EQU 0000A4H
; Timer control status register
; Compare clear buffer register
;--------------- Main program ------------------------------ORG
C0000H
:
; Assume that the stack pointer (SP) has been
START:
;
; already initialized.
ANDCCR #0EFH
; Disable interrupts.
LDI
#ICR32,r0
LDI
#00H,r1
STB
r1,@r0
LDI
#CPCLRBH,r0 ; Specify a value in the compare clear buffer register
LDI
#0FA00H,r1 ; to generate a compare clear interrupt at 4 ms
STH
r1,@r0
LDI
#TCCSH,r3 ; Set the up/down-count mode,
LDI
#0110H,r1 ; set the 62.5 ns count clock,
STH
r1,@r3
; Interrupt level: 16 (Highest)
; when the 16-bit free-run timer is in the up-count mode.
; enable a compare clear interrupt,
; clear the compare clear interrupt flag bit,
; disable the interrupt mask,
; clear the timer, and enable the operation.
LOOP
STILM #14H
; Set ILM in PS to level 20.
ORCCR #10H
; Enable interrupts.
LDI
#00H,r0
; Endless loop
LDI
#01H,r1
BRA
LOOP
;
;--------------- Interrupt program ------------------------------282
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10.7 Program Example of the Compare Timer
MB91345 Series
WARI
LDI
#0100H,r1
; Clear the interrupt request flag.
ANDH r1,@r3
;
:
;
User processing
;
:
; Return from the interrupt processing.
RETI
;--------------- Vector setting -----------------------------------VECT
.ORG
FFFF8H
; Set the interrupt routine.
.DATA.W
WARI
.ORG
FFFF8H
.DATA.W
0x07000000 ; Set the single chip mode.
.DATA.W
START
; Set the reset vector.
.END
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10.7 Program Example of the Compare Timer
MB91345 Series
■ Program Example of the 16-bit Output Compare
● Details of processing
• When the count value of the 16-bit free-run timer matches with the value of the output compare, an
output compare match is generated.
• This program is used when the 16-bit free-run timer is in the up/down-count mode.
• The setting of 16 MHz is for the peripheral clock, and 62.5 ns is for the count clock of the 16-bit freerun timer 0.
● Coding example
ICR44
EQU
00046CH
; Output compare 0/1 interrupt register
TCCSH
EQU
0000A8H
; Timer control status register
CPCLRBH EQU
0000A4H
; Compare clear buffer register
OCCPBH0 EQU
000090H
; Output compare buffer register 0
OCCPBH1 EQU
000092H
; Output compare buffer register 1
OCSH1
00009CH
; Compare control register
EQU
;--------------- Main program --------------------------------------------START:
;
; Assume that the stack pointer (SP) has been
:
; already initialized.
ANDCCR #0EFH
284
; Disable interrupts.
LDI
#ICR44,r0
LDI
#00H,r1
STB
r1,@r0
LDI
#CPCLRBH,r0 ; Set it to the compare clear buffer register
LDI
#0FFFFH,r1
STH
r1,@r0
LDI
#OCCPBH0,r0 ; Set output compare register 0.
LDI
#0BFFFH,r1
STH
r1,@r0
LDI
#OCCPBH1,r0 ; Set output compare register 1.
LDI
#07FFFH,r1
STH
r1,@r0
LDI
#OCSH1,r3
; Enable the output compare output.
LDI
#6C33H,r2
; Enable compare match interrupts 0/1.
STH
r2,@r3
; Clear the interrupt flag bit.
LDI
#TCCSH,r0
; Set the up/down-count mode,
LDI
#0010H,r1
; clear the timer, and enable the operation.
STH
r1,@r0
; Interrupt level: 16 (Highest)
; of the 16-bit free-run timer.
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10.7 Program Example of the Compare Timer
MB91345 Series
LOOP
STILM #14H
; set ILM in PS to level 20.
ORCCR #10H
; Enable interrupts.
LDI
#00H,r0
; Endless loop
LDI
#01H,r1
BRA
LOOP
;
;--------------- Interrupt program -------------------------------WARI:
; Clear the interrupt register flag.
ANDH r2,@r3
;
:
;
User processing
;
:
; Return from the interrupt processing.
RETI
;--------------- Vector setting ------------------------------------VECT
.ORG
FFFF8H
; Set the interrupt routine.
.DATA.W
WARI
.ORG
FFFF8H
.DATA.W
0x07000000 ; Set the single chip mode.
.DATA.W
START
; Set the reset vector.
.END
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10.7 Program Example of the Compare Timer
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CHAPTER 11
32-bit Compare Timer
This chapter describes the overview, the configuration
and functions of registers, and operation of the 32-bit
compare timer.
11.1 Overview of 32-bit Compare Timer
11.2 Block Diagram of 32-bit Compare Timer
11.3 Compare Timer Registers
11.4 Interrupt by the Compare Timer
11.5 Compare Timer Operation
11.6 Notes on Using the Compare Timer
11.7 Program Example of the Compare Timer
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CHAPTER 11 32-bit Compare Timer
11.1 Overview of 32-bit Compare Timer
11.1
MB91345 Series
Overview of 32-bit Compare Timer
The 32-bit compare timer consists of one 32-bit free-run timer, four 32-bit output
compares, and four 32-bit input captures.
■ Configuration of the Compare Timer
● 32-bit free-run timer ( 1)
• The 32-bit free-run timer consists of a 32-bit up counter, a control register, a 32-bit compare clear
register, and a prescaler.
• Nine types of counter operation clock settings can be selected (, /2, /4, /8, /16, /32, /64, /128,
/256; : Peripheral clock).
• A compare clear interrupt is generated when the compare clear register and the 32-bit free-run timer are
compared and judged to be a match.
• When a reset, a software clear, or a compare match with the compare clear register occurs, the counter
value is reset to "0000 0000H".
• The output value of this counter can be used as a reference count for the output compare and input
capture.
● 32-bit output compare ( 4)
• The 32-bit output compare consists of four 32-bit compare registers, a compare output latch, and a
compare control register. When the value of the 32-bit free-run timer matches with the compare register,
an interrupt is generated and the output level is inverted.
• These four compare registers can be operated independently. The output pins and interrupt flags
correspond to the compare registers respectively.
• You can pair two compare registers to control the output pin. The output pin is inverted by using two
compare registers together.
• The initial value of each output pin can be specified.
• An interrupt is generated when the output compare register matches with the 32-bit free-run timer.
● 32-bit input capture ( 4)
• The input capture consists of four independent external input pins, and capture registers and capture
control registers corresponding to the pins. When the edge of an input signal is detected at the external
pin, the value of the 32-bit free-run timer can be stored in the capture register, and an interrupt is
generated simultaneously.
• For the external input signal, three types of trigger edges (rising edge, falling edge, and both edges) can
be selected.
• These four input captures can be operated independently.
• An interrupt is generated when a valid edge from the external input is detected.
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11.2 Block Diagram of 32-bit Compare Timer
MB91345 Series
11.2
Block Diagram of 32-bit Compare Timer
This section shows the block diagram of the compare timer.
■ Block Diagram of the Compare Timer
Figure 11.2-1 Block Diagram of the Compare Timer
Interrupt
Interrupt
Interrupt
Interrupt
→
→
→
→
Output compare 4
Output compare 5
Output compare 6
Output compare 7
32-bit output compare
Data transfer
from buffer
RT4 to RT7
Counter
value
RT4 to RT7
Internal data bus
Interrupt → Zero detection 0
Interrupt → Compare clear 0
32-bit free-run timer
EXCK
Counter
value
Interrupt
Interrupt
Interrupt
Interrupt
FRCK1
Input capture 4
Input capture 5
Input capture 6
Input capture 7
32-bit input capture
IC4 to IC7
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CHAPTER 11 32-bit Compare Timer
11.2 Block Diagram of 32-bit Compare Timer
MB91345 Series
■ Block Diagram of the 32-bit Free-run Timer
Figure 11.2-2 Block Diagram of the 32-bit Free-run Timer
STOP
SCLR
CLK2
CLK1
CLK0
Prescaler
External clock input
STOP
CLR
Select circuit
STOP
32-bit free-run timer
CK
To input capture and
output compare
Transfer
Compare circuit
Internal data bus
32-bit compare
clear register
Interrupt
ICLE
290
ICLF
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CHAPTER 11 32-bit Compare Timer
11.2 Block Diagram of 32-bit Compare Timer
MB91345 Series
■ Block Diagram of the 32-bit Output Compare
Figure 11.2-3 Block Diagram of the 32-bit Output Compare
Count value from free-run timer
Compare registers 4, 6
Internal data bus
Compare circuit
IOP1
IOP0
IOE1
IOE0
Interrupt 6
Compare registers 5, 7
Interrupt 7
Compare circuit
IOP1
IOP0
IOE1
IOE0
Interrupt 4
Interrupt 5
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CHAPTER 11 32-bit Compare Timer
11.2 Block Diagram of 32-bit Compare Timer
MB91345 Series
■ Block Diagram of the 32-bit Input Capture
Figure 11.2-4 Block Diagram of the 32-bit Input Capture
Count value from free-run timer
Capture register 4
Edge detection
ICP4
ICE4
EG41
IC4
EG40
Interrupt 4
Edge detection
Internal data bus
Capture register 5
ICP5
ICE5
EG51
IC5
EG50
Interrupt 5
Capture register 6
Edge detection
ICP6
ICE6
EG61
IC6
EG60
Interrupt 6
Edge detection
Capture register 7
ICP7
ICE7
EG71
IC7
EG70
Interrupt 7
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CHAPTER 11 32-bit Compare Timer
11.3 Compare Timer Registers
MB91345 Series
11.3
Compare Timer Registers
This section describes the registers used for the compare timer.
■ Registers of the 32-bit Free-run Timer
Figure 11.3-1 Registers of the 32-bit Free-run Timer
Compare clear register
CPCLRB/CPCLR
Address
bit31
bit30
bit29
bit2
bit1
bit0
Initial value
000150H
CL31
CL30
CL29
CL02
CL01
CL00
FFFFFFFFH
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit31
bit30
bit29
bit2
bit1
bit0
Initial value
000154H
T31
T30
T29
T02
T01
T00
00000000H
R/W
R/W
R/W
R/W
R/W
R/W
Timer data register
TCDTH/TCDTL
Timer status control register (High order)
TCCSH
Address
bit15
bit14
bit13
bit2
bit11
bit10
bit9
bit8
Initial value
000158H
ECKE





ICLR
ICRE
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Timer status control register (Low order)
TCCSL
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000159H

STOP

SCLR
CLK3
CLK2
CLK1
CLK0
01000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
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11.3 Compare Timer Registers
MB91345 Series
■ Registers of the 32-bit Output Compare
Figure 11.3-2 Registers of the 32-bit Output Compare
Output compare register
OCCP4 to OCCP7
Address
bit31
bit30
bit29
bit2
bit1
bit0
Initial value
000170H
000174H
000178H
00017CH
CP31
CP30
CP29
CP02
CP01
CP00
XXXXXXXXH
R/W
R/W
R/W
R/W
R/W
R/W
Compare control register 5, 7 (High order)
OCSH45, OCSH67
Address
bit15
bit14
bit13
bit2
bit11
bit10
bit9
bit8
Initial value
000180H
000182H



CMOD


OTD1
OTD0
11101100B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Compare control register 4, 6 (Low order)
OCSL45, OCSL67
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000181H
000183H
IOP1
IOP0
IOE1
IOE0


CST1
CST0
00001100B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
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11.3 Compare Timer Registers
MB91345 Series
■ Registers of the 32-bit Input Capture
Figure 11.3-3 Registers of the 32-bit Input Capture
Input capture data register
IPCP4 to IPCP7
Address
bit31
bit30
bit29
bit2
bit1
bit0
Initial value
00015CH
000160H
000164H
000168H
CP31
CP30
CP29
CP02
CP01
CP00
XXXXXXXXH
R
R
R
R
R
R
Input capture status control register (ch.6, ch.7)
ICS67
Address
bit15
bit14
bit13
bit2
bit11
bit10
bit9
bit8
Initial value
00016FH
ICP7
ICP6
ICE7
ICE6
EG71
EG70
EG61
EG60
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Input capture status control register (ch.4, ch.5)
ICS45
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00016DH
ICP5
ICP4
ICE5
ICE4
EG51
EG50
EG41
EG40
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W:
R:
Readable/writable
Read only
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CHAPTER 11 32-bit Compare Timer
11.3 Compare Timer Registers
11.3.1
MB91345 Series
Compare Clear Register (CPCLRB/CPCLR)
The compare clear register (CPCLRB/CPCLR) is a 32-bit register which is used for the
comparison with the free-run timer.
■ Compare Clear Register (CPCLRB/CPCLR)
Figure 11.3-4 Compare Clear Register (CPCLRB/CPCLR)
Compare clear register
CPCLRB/CPCLR
Address
bit31
bit30
bit29
bit2
bit1
bit0
Initial value
000150H
CL31
CL30
CL29
CL02
CL01
CL00
FFFFFFFFH
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
The compare clear register is used to be compared with the count value of the 32-bit free-run timer. When
the count value of this register matches with the count value of the 32-bit free-run timer, the free-run timer
is reset to "00000000H", and when the value specified with this register matches with the counter value, an
interrupt occurs. The value, however, must be written while the timer has stopped (STOP (bit6) in the loworder byte of the timer status control register (TCCSL) = 1). To access to this register, use a word access
instruction.
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11.3 Compare Timer Registers
MB91345 Series
11.3.2
Timer Data Register (TCDT)
The timer data register (TCDT) is used to read the count value of the 32-bit free-run
timer.
■ Timer Data Register (TCDT)
Figure 11.3-5 Timer Data Register (TCDT)
Timer data register
TCDT
Address
bit31
bit30
bit29
bit2
bit1
bit0
Initial value
000154H
T31
T30
T29
T02
T01
T00
00000000H
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
The timer data register is used to read the count value of the 32-bit free-run timer. When a reset occurs, the
count value is immediately cleared to "00000000H". The timer value can be specified by writing a value
into this register. The value, however, must be written while the timer has stopped (STOP (bit6) in the loworder byte of the timer status control register (TCCSL) = 1). To access to the timer data register, use a word
access instruction.
The 32-bit free-run timer is initialized as soon as one of the following factors occurs:
• Reset
• Clear bit (SCLR:bit4) of the timer status control register (TCCSL) = 1.
• The compare clear register matches with the timer count value.
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CHAPTER 11 32-bit Compare Timer
11.3 Compare Timer Registers
11.3.3
MB91345 Series
Timer Status Control Register of High-order Byte
(TCCSH)
The timer status control register (TCCSH) is a 8-bit register which is used to control the
operation of the 32-bit free-run timer.
■ Timer Status Control Register, High-order Byte (TCCSH)
Figure 11.3-6 Timer Status Control Register, High-order Byte (TCCSH)
Timer status control register (High order)
TCCSH
Address
bit15
bit14
bit13
bit12
bit11
bit10
000158H
ECKE
−
−
−
−
−
R/W
R/W
R/W
R/W
R/W
R/W
bit9
bit8
Initial value
ICLR
ICRE
00000000B
R/W
ICRE
R/W
Compare clear interrupt request permission bit
0
Disable interrupt requests.
1
Enable interrupt requests.
Compare clear interrupt flag bit
ICLR
Read
Write
0
Compare clear does not match.
This bit is cleared.
1
Compare clear matches.
This bit is not affected.
bit14 to bit10
Reserved
0
Initial value
1
Setting disabled
ECKE
Clock selection bit
0
Internal clock
1
External clock
R/W : Readable/writable
: Initial value
298
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CHAPTER 11 32-bit Compare Timer
11.3 Compare Timer Registers
MB91345 Series
Table 11.3-1 Timer Status Control Register, High-order Byte (TCCSH)
Bit name
bit15
ECKE:
Clock selection bit
bit14 to bit10 Reserved
bit9
ICLR:
Compare clear
interrupt flag bit
bit8
ICRE:
Compare clear
interrupt request
permission bit
CM71-10132-3E
Function
• This bit is used to select either of the internal clock or external clock to be used as
the count clock of the 32-bit free-run timer.
• When this bit is set to "0":
The internal clock is selected. To select the count clock frequency, you also need
to select the clock frequency selection bits (CLK3 to CLK0: bit3 to bit0) of the
TCCSL register.
• When this bit is set to "1":
The external clock is selected. The external clock is input through the FRCK1 pin.
Consequently, you must enable the external clock input by writing "0" into bit7 of
the port direction register (DDR3). When the external clock is selected with this
bit, the clock count operates at both edges.
Note:
The count clock is changed as soon as this bit is set. Consequently, this bit must be
changed while the output compare and input capture have stopped.
These bits must be set to "0".
• When the compare clear value matches with the 32-bit free-run timer value, this bit
is set to "1".
• When this bit is set to "0": This bit is cleared.
• When this bit is set to "1": This bit is not affected.
• In read-modify-write (RMW) instruction, the read value is always "1".
When this bit and the compare clear interrupt flag bit (ICLR:bit9) are set to "1", an
interrupt request to the CPU is generated.
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11.3 Compare Timer Registers
11.3.4
MB91345 Series
Timer Status Control Register of Low-order Byte (TCCSL)
The timer status control register (TCCSL) is a 8-bit register which is used to control the
operation of the 32-bit free-run timer.
■ Timer Status Control Register, Low-order Byte (TCCSL)
Figure 11.3-7 Timer Status Control Register, Low-order Byte (TCCSL)
Timer status control register (low order)
TCCSL
bit7
bit6
bit5
Address:
STOP
000159H
bit4
bit3
bit2
bit1
bit0
Initial value
SCLR
CLK3
CLK2
CLK1
CLK0
01000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock frequency selection bits
CLK3
CLK2
CLK1
CLK0 Count
clock
0
0
0
0
31.25ns
0
0
0
1
0
0
1
0
0
0
1
1
0.25µs
0
1
0
0
0.5µs
0
1
0
1
1µs
2µs
4µs
8µs
32µs
0
1
1
0
2µs
4µs
8 µs
16µs
64µs
0
1
1
1
4µs
8 µs
16µs
32µs
128µs
1
0
0
0
8 µs
16µs
32µs
64µs
256µs
-
-
-
-
-
Other settings disabled
SCLR
0
1
300
125ns
62.5ns
125ns
0.25µs
0.5µs
2µs
125ns
0.25µs
0.5µs
1µs
4µ s
0.5µs
1µs
2µs
8µs
1µs
2µs
4µs
16µs
-
0.25µs
1µ s
Timer clear bit
Read
Always read "0".
Write
The counter is not initialized.
The counter is initialized to "00000000H".
bit5
Reserved
0
Initial value
1
R/W : Readable/writable
: Initial value
62.5ns
Setting disabled
STOP
Timer permission bit
0
Enable (Start) counting.
1
Disable (Stop) counting.
bit7
Reserved
0
Initial value
1
Setting disabled
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CHAPTER 11 32-bit Compare Timer
11.3 Compare Timer Registers
MB91345 Series
Table 11.3-2 Timer Status Control Register, Low-order Byte (TCCSL)
Bit name
bit7
Function
Reserved
This bit must be set to "0".
bit6
STOP:
Timer permission bit
• This bit is used to start/stop the count of the 32-bit free-run timer.
• When this bit is set to "0":
The count of the 32-bit free-run timer starts.
• When this bit is set to "1":
The count of the 32-bit free-run timer stops.
Note:
When the 32-bit free-run timer stops, the operation of the output compare also
stops.
bit5
Reserved
This bit must be set to "0".
bit4
• This bit is used to initialize the 32-bit free-run timer to "0000H".
• When this bit is set to "1":
The 32-bit free-run timer is initialized to "00000000H" at the next count clock. At
this instant, the prescaler inside the macro is also cleared.
SCLR: Timer clear bit
• The read value is always "0".
Note:
After "1" is set to this bit, the timer is cleared at the next timing of the internal
clock.
bit3
to
bit0
CLK3 to CLK0:
Clock frequency
selection bits
CM71-10132-3E
• These bits are used to select the count clock frequency of the 32-bit free-run timer.
• The count clock is changed as soon as these bits are set. Consequently, these bits
must be changed while the output compare and input capture have stopped.
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11.3 Compare Timer Registers
11.3.5
MB91345 Series
Output Compare Register (OCCP4 to OCCP7)
The output compare register (OCCP) is a register used for the comparison with the freerun timer.
■ Output Compare Register (OCCP4 to OCCP7)
Figure 11.3-8 Output Compare Register (OCCP4 to OCCP7)
Output compare register
OCCP4 to OCCP7
Address
bit31
bit30
bit29
bit2
bit1
bit0
Initial value
000170H
000174H
000178H
00017CH
CP31
CP30
CP29
CP02
CP01
CP00
XXXXXXXXH
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
The output compare register is a 32-bit register used to be compared with the count value of the 32-bit freerun timer. Before enabling the timer operation, set a value to the output compare register (OCCPH/
OCCPL). The compare value will be reflected after the write instruction is completed. Therefore, if the
compare value is changed during operation and the new compare value is greater than the old compare
value, two interrupts may occur during one free-run count. To avoid the problem, use the compare interrupt
processing of the free-run timer to rewrite the value of the output compare register.
When the value of the output compare register matches with the count value of the 32-bit free-run timer, a
compare signal is generated, and the output compare interrupt flag bits (IOP1, IOP0 (bit7, bit6) in the loworder byte of the compare control register (OCSL4, OCSL6)) are set.
To access to this register, use a word access instruction.
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CHAPTER 11 32-bit Compare Timer
11.3 Compare Timer Registers
MB91345 Series
11.3.6
Compare Control Register of High-order-side
(OCSH45, OCSH67)
The compare control register is used to control the output level and output level
inversion mode of RT4 to RT7.
■ Compare Control Register, High-order Byte (OCSH45, OCSH67)
Figure 11.3-9 Compare Control Register, High-order Byte (OCSH45, OCSH67)
Compare control register (High order)
OCS67
Address
bit15
bit14
bit13
000180H
000182H
-
R/W
R/W
bit12
bit11
bit10
bit9
bit8
Initial value
CMOD
-
-
OTD1
OTD0
11101100B
R/W
R/W
R/W
R/W
R/W
OTD0
0
1
OTD1
0
1
Current output value of RT4, RT6
"1" is output from RT4, RT6
Output level bit
Read
Write
Current output value of RT5, RT7
"0" is output from RT5, RT7
.
"1" is output from RT5, RT7
.
Reserved
0
Initial value
1
Setting disabled
bit11
Reserved
0
Initial value
1
Setting disabled
0
1
CM71-10132-3E
Write
"0" is output from RT4, RT6
bit10
CMOD
R/W : Readable/writable
: Undefined
: Initial value
Output level bit
Read
Output level inversion mode bit
RT4, RT6 : The level is inverted as soon as the match with
compare registers 4, 6 occurs.
RT5, RT7 : The level is inverted as soon as the match with
compare registers 5, 7 occurs.
RT4, RT6 : The level is inverted as soon as the match with
compare registers 4, 6 occurs.
RT5, RT7 : The level is inverted as soon as the match with
compare registers (4 or 5) and (6 or 7) occurs.
bit13
Reserved
0
Setting disabled
1
Initial value
bit14
Reserved
0
Setting disabled
1
Initial value
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11.3 Compare Timer Registers
MB91345 Series
Table 11.3-3 Compare Control Register, High-order Byte (OCSH45, OCSH67)
Bit name
bit15
Undefined bit
bit14, bit13 Reserved
bit12
CMOD:
Output level
inversion mode bit
bit11, bit10 Reserved
304
Function
• The read value is indeterminate.
• Writing to this bit does not affect the operation.
This bit must be set to "1".
• This bit is used to switch the pin output level inversion mode as soon as a match
occurs while the pin output is enabled (OTE1 = 1 or OTE0 = 1).
• When this bit is set to "0":
- RT4, RT6: The level is inverted as soon as the 32-bit free-run timer matches
with compare registers 4, 6.
- RT5, RT7: The level is inverted as soon as the 32-bit free-run timer matches
with compare registers 5, 7.
• When this bit is set to "1":
- RT4, RT6: The level is inverted as soon as the 32-bit free-run timer matches
with compare registers 4, 6.
- RT5, RT7: The level is inverted as soon as the 32-bit free-run timer matches
with the compare registers (4 or 5) and (6 or 7).
If the compare registers 4, 6 and 5, 7 have the same value, the operation is the same as
the case where one compare register is used.
This bit must be set to "0".
bit9
OTD1:
Output level bit
• This bit is used to change the pin output level of output compares 5, 7 (RT5, RT7).
• The initial value of the compare pin output is "0".
• Be sure to stop the compare operation before writing a value. The read value of this
bit indicates the output compare value for RT5, RT7.
bit8
OTD0:
Output level bit
• This bit is used to change the pin output level of output compares 4, 6 (RT4, RT6).
• The initial value of the compare pin output is "0".
• Be sure to stop the compare operation before writing a value. The read value of this
bit indicates the output compare value for RT4, RT6.
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CHAPTER 11 32-bit Compare Timer
11.3 Compare Timer Registers
MB91345 Series
11.3.7
Compare Control Register of Low-order Byte
(OCSL45, OCSL67)
The compare control register is used to control the compare operation permission,
compare match interrupt permission, and compare match interrupt flag.
■ Compare Control Register, Low-order Byte (OCSL45, OCSL67)
Figure 11.3-10 Compare Control Register, Low-order Byte (OCSL45, OCSL67)
Compare control register (low order)
OCS45
bit7
bit6
bit5
Address :
IOP1
IOP0
IOE1
000181H
000183H
R/W
R/W
R/W
bit4
bit3
bit2
bit1
bit0
Initial value
IOE0
-
-
CST1
CST0
00001100B
R/W
R/W
R/W
R/W
R/W
CST0
Compare operation permission bit
0
Disable the compare operation of compare registers 4, 6.
1
Enable the compare operation of compare registers 4, 6.
CST1
Compare operation permission bit
0
Disable the compare operation of compare registers 5, 7.
1
Enable the compare operation of compare registers 5, 7.
bit2
Reserved
0
Setting disabled
1
Initial value
bit3
Setting disabled
1
Initial value
IOE0
Disable the compare match interrupt of compare registers 4, 6.
1
Enable the compare match interrupt of compare registers 4, 6.
Compare match interrupt permission bit
0
Disable the compare match interrupt of compare registers 5, 7.
1
Enable the compare match interrupt of compare registers 5, 7.
IOP0
Compare match interrupt flag bit
Read
Write
0
The compare match interrupt of
compare registers 4, 6 does not occur.
This bit is cleared.
1
The compare match interrupt of
compare registers 4, 6 occurs.
IOP1
CM71-10132-3E
Compare match interrupt permission bit
0
IOE1
R/W : Readable/writable
: Initial value
Reserved
0
This bit is not affected.
Compare match interrupt flag bit
Read
Write
0
The compare match interrupt of
compare registers 5, 7 does not occur.
This bit is cleared.
1
The compare match interrupt of
compare registers 5, 7 occurs.
This bit is not affected.
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11.3 Compare Timer Registers
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Table 11.3-4 Compare Control Register, Low-order Byte (OCSL45, OCSL67)
Bit name
IOP1:
Compare match
interrupt flag bit
• This bit is an interrupt flag which indicates that compare registers 5, 7 match with
the value of the 32-bit free-run timer.
• This bit is set to "1" when the values of the compare registers match with the
value of the 32-bit free-run timer.
• If this bit is set while the compare match interrupt permission bit (IOE1:bit5) is
enabled, an output compare interrupt occurs.
• When this bit is set to "0": This bit is cleared.
• When this bit is set to "1": This bit is not affected.
• In read-modify-write (RMW) instruction, the read value is always "1".
bit6
IOP0:
Compare match
interrupt flag bit
• This bit is an interrupt flag which indicates that compare registers 4, 6 match with
the value of the 32-bit free-run timer.
• This bit is set to "1" when the values of the compare registers match with the
value of the 32-bit free-run timer.
• If this bit is set while the compare match interrupt permission bit (IOE0:bit4) is
enabled, an output compare interrupt occurs.
• When this bit is set to "0": This bit is cleared.
• When this bit is set to "1": This bit is not affected.
• In read-modify-write (RMW) instruction, the read value is always "1".
bit5
IOE1:
• This bit is used to enable the output compare interrupt of compare registers 5, 7.
Compare match
• If the compare match interrupt flag bit (IOP1:bit7) is set while "1" is written in
interrupt permission bit
this bit, an output compare interrupt occurs.
bit4
IOE0:
• This bit is used to enable the output compare interrupt of compare registers 4, 6.
Compare match
• If the compare match interrupt flag bit (IOP0:bit6) is set while "1" is written in
interrupt permission bit
this bit, an output compare interrupt occurs.
bit3
Reserved
This bit must be set to "0".
bit2
Reserved
This bit must be set to "0".
bit1
CST1:
Compare operation
permission bit
This bit is used to enable the compare operation between the 32-bit free-run timer
and compare registers 5, 7.
Note:
Since the output compare is synchronized with the 32-bit free-run timer clock,
stopping the 32-bit free-run timer also stops the compare operation.
CST0:
Compare operation
permission bit
This bit is used to enable the compare operation between the 32-bit free-run timer
and compare registers 4, 6.
Note:
Since the output compare is synchronized with the 32-bit free-run timer clock,
stopping the 32-bit free-run timer also stops the zero detection and compare operation.
bit7
bit0
306
Function
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CHAPTER 11 32-bit Compare Timer
11.3 Compare Timer Registers
MB91345 Series
11.3.8
Input Capture Data Register (IPCP4 to IPCP7)
The input capture data register is used to retain the count value of the free-run timer
when a valid edge of the input waveform is detected.
■ Input Capture Data Register (IPCP4 to IPCP7)
Figure 11.3-11 Input Capture Data Register (IPCP4 to IPCP7)
Input capture data register
IPCP4 to IPCP7
Address
bit31
bit30
bit29
bit2
bit1
bit0
Initial value
00015CH
000160H
000164H
000168H
CP31
CP30
CP29
CP02
CP01
CP00
XXXXXXXXH
R
R
R
R
R
R
R: Read only
This register is used to store the value of the free-run timer when a valid edge of the corresponding external
pin input waveform is detected. (To access to this register, use a word access instruction. Data cannot be
written to this register.)
The free-run timer described above concerns the operating status of the free-run timer selected by the input
capture.
CM71-10132-3E
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11.3 Compare Timer Registers
11.3.9
MB91345 Series
Input Capture Status Control (ICS67, ICS45)
The input capture status control/PPG output control register (ICS67, ICS45) is used to
control the edge selection, interrupt request permission, and interrupt request flag. It is
also used to indicate a valid edge detected by input capture 4 to 7.
■ Input Capture Status Control Register (ch.6, ch.7), (ICS67)
Figure 11.3-12 Input Capture Status Control Register (ch.6, ch.7), (ICS67)
Input capture status control register
ICS67
Address:
00016FH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ICP7
ICP6
ICE7
ICE6
EG71
EG70
EG61
EG60
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EG61 EG60
Edge selection bits (Input capture 6)
0
0
No edges are detected. (Stop)
0
1
Rising edges are detected.
1
0
Falling edges are detected.
1
1
Both edges are detected.
EG71 EG70
Edge selection bits (Input capture 7)
0
0
No edges are detected. (Stop)
0
1
Rising edges are detected.
1
0
Falling edges are detected.
1
1
Both edges are detected.
ICE6
Interrupt request permission bit (Input capture 6)
0
Disable interrupt requests.
1
Enable interrupt requests.
ICE7
Interrupt request permission bit (Input capture 7)
0
Disable interrupt requests.
1
Enable interrupt requests.
ICP6
Interrupt request flag bit (Input capture 6)
Read
Write
0
Valid edge is not detected.
This bit is cleared.
1
Valid edge is detected.
ICP7
This bit is not affected.
Interrupt request flag bit (Input capture 7)
Read
Write
0
Valid edge is not detected.
This bit is cleared.
1
Valid edge is detected.
This bit is not affected.
R/W : Readable/writable
: Initial value
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CHAPTER 11 32-bit Compare Timer
11.3 Compare Timer Registers
MB91345 Series
Table 11.3-5 Input Capture Status Control Register (ch.6, ch.7), (ICS67)
Bit name
Function
bit7
• This bit is used as an interrupt request flag for input capture 7.
• This bit is set to "1" as soon as a valid edge is detected at the external input pin.
ICP7:
• If a valid edge is detected while the interrupt request permission bit (ICE7:bit5) is
Interrupt request flag bit
set, an interrupt can be generated immediately.
(Input capture 7)
• When this bit is set to "0": This bit is cleared.
• When this bit is set to "1": This bit is not affected.
• In read-modify-write (RMW) instruction, the read value is always "1".
bit6
• This bit is used as an interrupt request flag for input capture 6.
• This bit is set to "1" as soon as a valid edge is detected at the external input pin.
ICP6:
• If a valid edge is detected while the interrupt request permission bit (ICE6:bit4) is
Interrupt request flag bit
set, an interrupt can be generated immediately.
(Input capture 6)
• When this bit is set to "0": This bit is cleared.
• When this bit is set to "1": This bit is not affected.
• In read-modify-write (RMW) instruction, the read value is always "1".
bit5
ICE7:
Interrupt request
permission bit
(Input capture 7)
bit4
ICE6:
Interrupt request
permission bit
(Input capture 6)
bit3,
bit2
EG70, EG71:
Edge selection bits
(Input capture 7)
• These bits are used to specify the polarity of valid edges from the external input
of input capture 7.
• These bits are also used to enable the operation of input capture 7.
bit1,
bit0
EG60, EG61:
Edge selection bits
(Input capture 6)
• These bits are used to specify the polarity of valid edges from the external input
of input capture 6.
• These bits are also used to enable the operation of input capture 6.
CM71-10132-3E
• This bit is used to enable an input capture interrupt request for input capture 7.
• If the interrupt request flag bit (ICP7:bit7) is set while "1" is set to this bit, an
interrupt for input capture 7 is generated.
• This bit is used to enable an input capture interrupt request for input capture 6.
• If the interrupt request flag bit (ICP6:bit6) is set while "1" is set to this bit, an
interrupt for input capture 6 is generated.
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CHAPTER 11 32-bit Compare Timer
11.3 Compare Timer Registers
MB91345 Series
■ Input Capture Status Control Register (ch.4, ch.5), (ICS45)
Figure 11.3-13 Input Capture Status Control Register (ch.4, ch.5), (ICS45)
Input capture status control register
bit7
bit6
bit5
ICS45
Address:
ICP5
ICP4
ICE5
00016DH
R/W
R/W
R/W
bit4
bit3
bit2
bit1
bit0
Initial value
ICE4
EG51
EG50
EG41
EG40
00000000B
R/W
R/W
R/W
R/W
R/W
EG41 EG40
Edge selection bits (Input capture 4)
0
0
No edges are detected. (Stop)
0
1
Rising edges are detected.
1
0
Falling edges are detected.
1
1
Both edges are detected.
EG51 EG50
Edge selection bits (Input capture 5)
0
0
No edges are detected. (Stop)
0
1
Rising edges are detected.
1
0
Falling edges are detected.
1
1
Both edges are detected.
ICE4
Interrupt request permission bit (Input capture 4)
0
Disable interrupt requests.
1
Enable interrupt requests.
ICE5
Interrupt request permission bit (Input capture 5)
0
Disable interrupt requests.
1
Enable interrupt requests.
ICP4
Interrupt request flag bit (Input capture 4)
Read
Write
0
Valid edge is not detected.
This bit is cleared.
1
Valid edge is detected.
ICP5
This bit is not affected.
Interrupt request flag bit (Input capture 5)
Read
Write
0
Valid edge is not detected.
This bit is cleared.
1
Valid edge is detected.
This bit is not affected.
R/W : Readable/writable
: Initial value
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11.3 Compare Timer Registers
MB91345 Series
Table 11.3-6 Input Capture Status Control Register (ch.4, ch.5), (ICS 45)
Bit name
Function
ICP5:
Interrupt request flag
bit (Input capture 5)
• This bit is used as an interrupt request flag for input capture 5.
• This bit is set to "1" as soon as a valid edge is detected at the external input pin.
• If a valid edge is detected while the interrupt request permission bit (ICE5:bit5) is
set, an interrupt is generated immediately.
• When this bit is set to "0": This bit is cleared.
• When this bit is set to "1": This bit is not affected.
• In read-modify-write (RMW) instruction, the read value is always "1".
bit6
ICP4:
Interrupt request flag
bit (Input capture 4)
• This bit is used as an interrupt request flag for input capture 4.
• This bit is set to "1" as soon as a valid edge is detected at the external input pin.
• If a valid edge is detected while the interrupt request permission bit (ICE4:bit4) is
set, an interrupt is generated immediately.
• When this bit is set to "0": This bit is cleared.
• When this bit is set to "1": This bit is not affected.
• In read-modify-write (RMW) instruction, the read value is always "1".
bit5
ICE5:
Interrupt request
permission bit
(Input capture 5)
bit4
ICE4:
Interrupt request
permission bit
(Input capture 4)
bit3,
bit2
EG50, EG51:
Edge selection bits
(Input capture 5)
• These bits are used to specify the polarity of valid edges from the external input of
input capture 5.
• These bits are also used to enable the operation of input capture 5.
bit1,
bit0
EG40, EG41:
Edge selection bits
(Input capture 4)
• These bits are used to specify the polarity of valid edges from the external input of
input capture 4.
• These bits are also used to enable the operation of input capture 4.
bit7
CM71-10132-3E
• This bit is used to enable an input capture interrupt request for input capture 5.
• If the interrupt request flag bit (ICP5:bit7) is set while "1" is set to this bit, an
interrupt for input capture 5 is generated.
• This bit is used to enable an input capture interrupt request for input capture 4.
• If the interrupt request flag bit (ICP4:bit6) is set while "1" is set to this bit, an
interrupt for input capture 4 is generated.
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CHAPTER 11 32-bit Compare Timer
11.4 Interrupt by the Compare Timer
11.4
MB91345 Series
Interrupt by the Compare Timer
The compare timer can generate interrupts for the 32-bit free-run timer, the 32-bit output
compare, and the 32-bit input capture respectively.
■ Interrupt for the 32-bit Free-run Timer
Table 11.4-1 shows the interrupt control bits and interrupt factor for the 32-bit free-run timer.
Table 11.4-1 Interrupt Control Bits and Interrupt Factor for the 32-bit Free-run Timer
Compare clear of 32-bit free-run timer
Interrupt request flag bit
ICLR (bit9) in the high-order byte of the timer status register (TCCSH)
Interrupt request permission bit
ICRE (bit8) in the high-order byte of the timer status register (TCCSH)
Interrupt factor
The value of the 32-bit free-run timer matches with the compare clear register
(CPCLRB/CPCLR).
When the value of the 32-bit free-run timer matches with the compare clear register (CPCLRB/CPCLR),
ICLR (bit9) of the timer status register (TCCSH) is set to "1". If an interrupt request is enabled in this status
(ICRE (bit8) of TCCSH register = 1), an interrupt request is output to the interrupt controller.
■ Interrupt for the 32-bit Output Compare
Table 11.4-2 shows the interrupt control bits and interrupt factor for the 32-bit output compare.
Table 11.4-2 Interrupt Control Bits and Interrupt Factor for the 32-bit Output Compares 4 to 7
32-bit output compares 4, 5
32-bit output compares 6, 7
Interrupt request flag bit
IOP1, IOP0 (bit7, bit6) in the low-order byte IOP1, IOP0 (bit7, bit6) in the low-order byte
of the compare control register (OCSL4)
of the compare control register (OCSL6)
Interrupt request permission bit
IOE1, IOE0 (bit5, bit4) in the low-order byte IOE1, IOE0 (bit5, bit4) in the low-order byte
of the compare control register (OCSL4)
of the compare control register (OCSL6)
Interrupt factor
The value of the 32-bit free-run timer
matches with the output compare register
(OCCPH/L 4, 5).
The value of the 32-bit free-run timer
matches with the output compare register
(OCCPH/L 6, 7).
When the value of the 32-bit free-run timer matches with the output compare register (OCCPH/L 4 to 7),
IOP1, IOP0 (bit7, bit6) in the low-order byte of the compare control register (OCSL4, OCSL6) are set to
"11B". If an interrupt request is enabled in this status (IOE1, IOE0 (bit5, bit4) of OCSL4, OCSL6 registers =
11B), an interrupt request is output to the interrupt controller.
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11.4 Interrupt by the Compare Timer
MB91345 Series
■ Interrupt for the 32-bit Input Capture
Table 11.4-3 interrupt control bits and interrupt factor for the 32-bit input capture.
Table 11.4-3 Interrupt Control Bits and Interrupt Factor for the 32-bit Input Captures 4 to 7
32-bit input captures 4, 5
Interrupt request flag bit
32-bit input captures 6, 7
ICP4, ICP5 (bit7, bit6) in the low-order byte ICP7, ICP6 (bit7, bit6) in the low-order byte
of the input capture status control register
of the input capture status control register
(ICS45)
(ICS67)
ICE4, ICE5 (bit5, bit4) in the low-order byte ICE7, ICE6 (bit5, bit4) in the low-order byte
Interrupt request permission bit of the input capture status control register
of the input capture status control register
(ICS45)
(ICS67)
Interrupt factor
A valid edge is detected at the IC4, IC5 pins A valid edge is detected at the IC6, IC7 pins
As for the 32-bit input capture, when a valid edge is detected at the IC4 to IC7 pins, ICP7, ICP6, ICP5,
ICP4 (bit7, bit6 for all cases) of the input capture status control register (ICS45, ICS67) are set to "11B". If
an interrupt request is enabled in this status (ICE7, ICE6, ICE5, ICE4 (bit5, bit4 for all cases) of ICS45,
ICS67 registers = 11B), an interrupt request is output to the interrupt controller.
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CHAPTER 11 32-bit Compare Timer
11.5 Compare Timer Operation
11.5
MB91345 Series
Compare Timer Operation
This section describes the operation of the compare timer.
■ Compare Timer Operation
● 32-bit free-run timer
When count operation is enabled, the 32-bit free-run timer starts counting up from the value specified in the
timer data register (TCDT). The count value is used as reference time for the 32-bit output compare and 32bit input capture.
● 32-bit output compare
The 32-bit output compare is used to compare "the value set in the specified output compare register" with
"the value of the 32-bit free-run timer". When a match is detected, an interrupt flag is set and the output
level is inverted.
● 32-bit input capture
The 32-bit input capture is used to detect a valid edge being specified.
When a valid edge is detected, an interrupt flag is set, and the value of the 32-bit free-run timer is captured
and stored in the input capture data register.
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11.5 Compare Timer Operation
MB91345 Series
11.5.1
Operation of the 32-bit Free-run Timer
The compare timer has one unit of a 32-bit free-run timer. After a reset is completed, the
32-bit free-run timer starts counting up from the value specified in the timer data
register (TCDT). The count value is used as reference time for the 32-bit output compare
and 32-bit input capture.
■ Clearing the Timer
The count value of the 32-bit free-run timer is cleared at one of the following events:
• When the match with the compare clear register is detected
• When "1" is written in SCLR (bit4) of the TCCSL register during operation
• When "00000000H" is written in the TCDT register while operation is stopped
• When the timer is reset
When the timer is reset, the counter is cleared immediately. When the match with the compare clear
register is detected, the counter is cleared in synchronization with the count timing.
Figure 11.5-1 Timing of clearing the 32-bit free-run timer
φ
Compare clear
Register value
N
Compare match
Count value
N
0000H
■ Counting Up
The 32-bit free-run timer is an up counter.
The counter starts counting up from the value of the predefined timer data register (TCDT) and continues
counting up until the count value matches with the value of the compare clear register (CPCLRB/CPCLR).
Then the counter is cleared to "0000H" and starts counting up again.
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CHAPTER 11 32-bit Compare Timer
11.5 Compare Timer Operation
MB91345 Series
■ Compare Clear Register
The compare clear register (CPCLRB/CPCLR) writes data to be compared.
Figure 11.5-2 Writing data of compare clear register
Count value
FFFFFFFFH
BFFFFFFFH
7FFFFFFFH
3FFFFFFFH
Time
00000000 H
Start of timer operation
Compare clear match
Reset
Compare clear
register
BFFFH
7FFFH
FFFFH
■ Timer Interrupt
The 32-bit free-run timer can generate a compare clear interrupt.
A compare clear interrupt is generated when the timer value matches with the value of the compare clear
register (CPCLRB/CPCLR).
Figure 11.5-3 Compare clear interrupt
Count value
N-1
N
0
1
Compare clear interrupt
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11.5 Compare Timer Operation
MB91345 Series
■ Selected External Count Clock
The 32-bit free-run timer is incremented based on the input clock (internal or external clock). When the
external clock is selected, the external clock mode is selected (ECKE (bit15) of the TCCSH register = 1). If
the initial value of the external input is "1", the 32-bit free-run timer starts counting up at a rising edge.
After that, it counts up at both edges. If the initial value of the external input is "0", the timer starts counting
up at a falling edge. After that, it counts up at both edges.
Figure 11.5-4 Count Timing of the 32-bit Free-run Timer
External clock input
TCCSH: ECKE bit
Count clock
Count value
N
N+1
N+2
Note:
The external clock input is counted at both edges of the external clock.
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CHAPTER 11 32-bit Compare Timer
11.5 Compare Timer Operation
11.5.2
MB91345 Series
Operation of the 32-bit Output Compare
The output compare is used to compare "the value set in the specified compare clear
register" with "the value of the 32-bit free-run timer". When a match is detected, an
interrupt flag is set and the output level is inverted.
■ Operation of the 32-bit Output Compare
● The compare operation can be executed at each channel (CMOD (bit12) in the high-order byte of the
compare control register (OCS45, OCS67) = 0).
Figure 11.5-5 Example of Output Waveform if Compare Registers 4 and 5 are Used Independently
when the Output Initial Value is "0"
Count value
FFFFFFFFH
BFFFFFFFH
7FFFFFFFH
3FFFFFFFH
00000000 H
Time
Reset
Compare
register 4
BFFFH
Compare
register 5
7FFFH
RT4
RT5
Interrupt by
compare 4
Interrupt by
compare 5
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11.5 Compare Timer Operation
MB91345 Series
● The output level can be changed by using a pair of compare registers (CMOD (bit12) in the high-order
byte of the compare control register (OCS45, OCS67) = 1).
Figure 11.5-6 Example of Output Waveform if Compare Registers 4 and 5 are Used as a Pair
when the Output Initial Value is "0"
Count value
FFFFFFFFH
BFFFFFFFH
7FFFFFFFH
3FFFFFFFH
00000000 H
Time
Reset
Compare
register 4
BFFFH
Compare
register 5
7FFFH
Corresponds to
compare 4
Corresponds to
compare 4 and 5
RT4
RT5
Interrupt by
compare 4
Interrupt by
compare 5
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CHAPTER 11 32-bit Compare Timer
11.5 Compare Timer Operation
MB91345 Series
■ Timing of the 32-bit Output Compare Operation
If the value of the free-run timer matches with the value of the compare register, the output compare
generates a compare match signal, inverts the output, and generates an interrupt. When a compare match
occurs, the output is inverted in synchronization with the count timing of the counter.
Figure 11.5-7 Interrupt Timing of the Compare Register
Machine clock φ
N
N+1
Count value
N
Compare register
Compare match
Interrupt
Figure 11.5-8 Timing of Changes in the Pin Output
Machine clock φ
Count value
Compare register
N+1
N
N+1
N
N
Compare match signal
Pin output
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CHAPTER 11 32-bit Compare Timer
11.5 Compare Timer Operation
MB91345 Series
11.5.3
Operation of the 32-bit Input Capture
The input capture is used to detect a valid edge being specified. When a valid edge is
detected, an interrupt flag is set and the value of the 32-bit free-run timer is loaded to
the capture register.
■ Operation of the 32-bit Input Capture
Figure 11.5-9 Timing Example of Input Capture
Count value
FFFFFFFFH
BFFFFFFFH
7FFFFFFFH
3FFFFFFFH
00000000 H
Time
Reset
IC4
IC5
IC example
Capture
register 4
Capture
register 5
Capture
register
example
Indeterminate
3FFFH
Indeterminate
Indeterminate
7FFFH
BFFFH
3FFFH
Interrupt by
capture 4
Interrupt by
capture 5
Interrupt by
capture example
Another generation of an interrupt by a valid edge
Interrupt clear by software.
Capture 4: Rising edge
Capture 5: Falling edge
Capture example: Both edges
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11.5 Compare Timer Operation
MB91345 Series
■ Input Timing of the 32-bit Input Capture
Figure 11.5-10 Timing Example of the 32-bit Input Capture for Input Signals
Machine clock φ
Count value
Input
N
N+1
Valid edge
Capture input
Capture signal
Capture register
N+1
Interrupt
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CHAPTER 11 32-bit Compare Timer
11.6 Notes on Using the Compare Timer
MB91345 Series
11.6
Notes on Using the Compare Timer
This section describes the notes on using the components of the compare timer.
■ Notes on Using the 32-bit Free-run Timer
● Notes on setting by program
When a reset or a software clear is executed (SCLR (bit4) of the TCCSL register = 1), the timer value is
reset to "00000000H".
● Notes on interrupt
When "1" is set to the ICLR (bit9) in the high-order byte of the timer status control register (TCCSH), and
then an interrupt request is enabled (ICRE (bit8) of the TCCSH register = 1), the control cannot return from
the interrupt processing. Note that ICLR (bit9) must be cleared.
■ Notes on Using the 32-bit Output Compare
Notes on interrupt
When "11B" is set to IOP1, IOP0 (bit7, bit6) in the low-order byte of the compare control register (OCSL4,
OCSL6), and then an interrupt request is enabled (IOE1, IOE0 (bit6, bit5) of the OCSL register = 11B), the
control cannot return from the interrupt processing. Be sure to clear IOP0, IOP1 bits.
■ Notes on Using the 32-bit Input Capture
Notes on interrupt
When "1" is set to ICP7, ICP6, ICP5, ICP4 (bit7, bit6 for all cases) in the low-order byte of the input
capture status control register (ICSL45, ICSL67), and then an interrupt request is enabled (ICE7, ICE6,
ICE5, ICE4 (bit5, bit4 for all cases) of the ICSL45, ICSL67 registers = 11B), the control cannot return from
the interrupt processing. Be sure to clear ICP7, ICP6, ICP5, ICP4 (bit7, bit6 for all cases).
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CHAPTER 11 32-bit Compare Timer
11.7 Program Example of the Compare Timer
11.7
MB91345 Series
Program Example of the Compare Timer
This section shows the program example of the components of the compare timer.
■ Program Example of the 32-bit Free-run Timer
● Details of processing
• When the 32-bit free-run timer counts 4 ms, it generates a compare clear interrupt.
• This timer is used to regenerate the compare clear timer in the up-count mode.
• The setting of 16 MHz is for the peripheral clock, and that of 62.5 ns is for the count clock.
● Coding example
ICR32
.EQU 000460H
; Compare clear interrupt control register of
; the 32-bit free-run timer
TCCSH
.EQU 0000A8H
CPCLRBH .EQU 0000A4H
; Timer control status register
; Compare clear buffer register
;--------------- Main program -------------------------------ORG
C0000H
START:
;
; Assume that the stack pointer (SP) has been
:
; already initialized.
ANDCCR #0EFH
; Disable interrupts.
LDI
#ICR32,r0
LDI
#00H,r1
STB
r1,@r0
LDI
#CPCLRBH,r0 ; Specify a value in the compare clear buffer register
LDI
#0FA00H,r1
; to generate a compare clear interrupt at 4 ms
STH
r1,@r0
; when the 32-bit free-run timer is in the up-count mode.
LDI
#TCCSH,r3
; Set the up/down-count mode,
LDI
#0110H,r1
; set the 62.5 ns count clock,
STH
r1,@r3
; enable a compare clear interrupt,
; Interrupt level 16 (Highest)
; clear the compare clear interrupt flag bit,
; disable the interrupt mask,
; clear the timer, and enable the operation.
LOOP
324
STILM #14H
; Set ILM in PS to level 20.
ORCCR #10H
; Enable interrupts.
LDI
#00H,r0
; Endless loop
LDI
#01H,r1
BRA
LOOP ;
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11.7 Program Example of the Compare Timer
MB91345 Series
;--------------- Interrupt program -------------------------------WARI
LDI
#0100H,r1
; Clear the interrupt request flag.
ANDH r1,@r3
;
:
;
User processing
;
:
; Return from the interrupt processing.
RETI
;--------------- Vector setting ------------------------------------VECT
.ORG
.DATA.W
.ORG
FFFF8H
WARI
; Set the interrupt routine.
FFFF8H
.DATA.W
0x07000000 ; Set the single chip mode.
.DATA.W
START
; Set the reset vector.
.END
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CHAPTER 11 32-bit Compare Timer
11.7 Program Example of the Compare Timer
MB91345 Series
■ Program Example of the 32-bit Output Compare
● Details of processing
• When the count value of the 32-bit free-run timer matches with the value of the output compare, an
output compare match is generated.
• This program is used when the 32-bit free-run timer is in the up/down-count mode.
• The setting of 16 MHz is for the peripheral clock, and that of 62.5 ns is for the count clock of the 32-bit
free-run timer 0.
● Coding example
ICR44
EQU
00046CH
; Output compare 0/1 interrupt register
TCCSH
EQU
0000A8H
; Timer control status register
CPCLRBH EQU
0000A4H
; Compare clear buffer register
OCCPBH0 EQU
000090H
; Output compare buffer register 0
OCCPBH1 EQU
000092H
; Output compare buffer register 1
OCSH1
00009CH
; Compare control register
EQU
;--------------- Main program -------------------------------START:
;
; Assume that the stack pointer (SP) has been
:
; already initialized.
ANDCCR #0EFH
326
; Disable interrupts.
LDI
#ICR44,r0
LDI
#00H,r1
STB
r1,@r0
LDI
#CPCLRBH,r0 ; Set it to the compare clear buffer register
LDI
#0FFFFH,r1
STH
r1,@r0
LDI
#OCCPBH0,r0 ; Set output compare register 0.
LDI
#0BFFFH,r1
STH
r1,@r0
LDI
#OCCPBH1,r0 ; Set output compare register 1.
LDI
#07FFFH,r1
STH
r1,@r0
LDI
#OCSH1,r3
; Enable the output compare output.
LDI
#6C33H,r2
; Enable compare match interrupts 0/1.
STH
r2,@r3
; Clear the interrupt flag bit.
LDI
#TCCSH,r0
; Set the up/down-count mode,
LDI
#0010H,r1
; clear the timer, and enable the operation.
; Interrupt level 16 (Highest)
; of the 32-bit free-run timer.
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CHAPTER 11 32-bit Compare Timer
11.7 Program Example of the Compare Timer
MB91345 Series
STH
LOOP
r1,@r0
STILM #14H
; Set ILM in PS to level 20.
ORCCR #10H
; Enable interrupts.
LDI
#00H,r0
; Endless loop
LDI
#01H,r1
BRA
LOOP
;
;--------------- Interrupt program -------------------------------WARI:
; Clear the interrupt register flag.
ANDH r2,@r3
;
:
;
User processing
;
:
; Return from the interrupt processing.
RETI
;--------------- Vector setting ------------------------------------VECT
.ORG
.DATA.W
.ORG
FFFF8H
WARI
; Set the interrupt routine.
FFFF8H
.DATA.W
0x07000000 ; Set the single chip mode.
.DATA.W
START
; Set the reset vector.
.END
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11.7 Program Example of the Compare Timer
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CHAPTER 12
16-bit PWC
This chapter describes the overview, the configuration
and functions of registers, and operations of the 16-bit
PWC.
12.1 Overview of the 16-bit PWC
12.2 Register of the 16-bit PWC
12.3 Operation of the 16-bit PWC
12.4 Notes on Using in the 16-bit PWC
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CHAPTER 12 16-bit PWC
12.1 Overview of the 16-bit PWC
12.1
MB91345 Series
Overview of the 16-bit PWC
16-bit PWC is composed of 16-bit up counter, input pulse divider, division ratio control
register, measurement input pin and control register. It allows pulse-width measurement
of input signals.
■ Overview of the 16-bit PWC
16-bit PWC measures the time between any given events of pulse inputs from the outside. Reference
internal clock can be selected from among the following three types.
• Peripheral clock divided by 4, 16, 32.
Measurement mode can be selected from among the following six types.
• "H" pulse width ( through )
• "L" pulse width ( through )
• Rising cycle ( through )
• Falling cycle ( through )
• Measurement between edges ( or  through  or )
• Measurement of input pulse division cycle [2n divisions (n = 1, 2, 3, 4, 5, 6, 7, 8)]
In addition, the 16-bit PWC has the following features.
• 16-bit PWC can generate interrupt requests at the termination of the measurement.
• 16-bit PWC can select one-time measurement or continuous measurement.
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12.1 Overview of the 16-bit PWC
MB91345 Series
■ Block Diagram of the 16-bit PWC
Figure 12.1-1 Block diagram of the 16-bit PWC
PWCR0 is read.
ERR
Error is detected.
16
/
/
16
PWCR0
Internal clock
(Peripheral clock divided by 4)
/ 16
Writing is enabled.
Reload
Data is transferred.
/ 16
R-bus
16-bit up counter
Overflow
Cleared
Clock
22
Counting is
permitted.
23
CKS1/
CKS0
Control circuit
Control bit is
outputted.
Flag is set.
Start edge
is selected.
Measurement
start edge
Termination
edge is
selected.
Divider is cleared.
Division
On/Off
Input wave
comparator
Edge is
detected.
Measurement
termination edge
Interrupt request at the termination
of the measurement
Clock
divider
PIS1/PIS0
ERR
CKS1/CKS0
PWC
8-bit
divider
Interrupt request for overflow
15
/
PWCSR
Division ratio
is selected.
2
/
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PDIVR
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CHAPTER 12 16-bit PWC
12.2 Register of the 16-bit PWC
12.2
MB91345 Series
Register of the 16-bit PWC
This section describes the register of the 16-bit PWC.
■ Register List of the 16-bit PWC
Figure 12.2-1 Register list of the 16-bit PWC
PWCSR high order
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
0000F8H
STRT
STOP
EDIR
EDIE
OVIR
OVIE
ERR
R/W
R
R/W
R/W
R/W
R


00000000B
R/W
PWCSR low order
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000F9H
CKS1
CKS0
PIS1
PIS0
SC
MOD2
MOD1
MOD0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit14
bit13
bit12
bit11
bit10
bit9
bit8
PWCR high order
Address
0000FAH
bit15
PWC15 PWC14 PWC13 PWC12 PWC11 PWC10 PWC09 PWC08
R
R
R
R
R
R
R
R
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00000000B
PWCR low order
Address
0000FBH
PWC07 PWC06 PWC05 PWC04 PWC03 PWC02 PWC01 PWC00
Initial value
00000000B
R
R
R
R
R
R
R
R
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000FDH










DIV2
DIV1
DIV0
XXXXX000B
R/W
R/W
R/W
PDIVR
R/W:
R:
:
332
Readable/writable
Read only
Reserved bit
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CHAPTER 12 16-bit PWC
12.2 Register of the 16-bit PWC
MB91345 Series
12.2.1
PWC Control Status Register (PWCSR0)
This register is used to control the operation of PWC and to display the status.
■ PWC Control Status Register (PWCSR0)
PWCSR0 high order
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
0000F8H
STRT
STOP
EDIR
EDIE
OVIR
OVIE
ERR
R/W
R
R/W
R/W
R/W
R


00000000B
R/W
PWCSR0 low order
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000F9H
CKS1
CKS0
PIS1
PIS0
SC
MOD2
MOD1
MOD0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W:
R:
:
Readable/writable
Read only
Reserved bit
[bit15] STRT: Counter start bit
[bit14] STOP: Counter stop bit
These bits are used to start, restart and stop the 16-bit up counter. When it is read, counter’s operation
status is displayed. The following tables show bit functions.
(1) Functions during the writing (Control of the operation)
STRT
STOP
Functions of operation control
0
0
No function/No effect on operation
0
1
Starts/Restarts the counter. (Enable counting)
Note: Clear bit command is enabled.
1
0
Forcedly stops the operation of counter (Disable counting).
Note: Clear bit command is enabled.
1
1
No function/No effect on operation
(2) Functions during the reading (Display of the operation status)
STRT
STOP
Display of the operation status
0
0
Counting is stopped.
[Initial value]
(The counter is not activated or measurement is terminated.)
1
1
Counting is running. (Under a measurement)
• When reset, it is initialized to "00B".
• Read/Write is enabled. Depending on the writing and reading, functions will be different as
mentioned above.
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12.2 Register of the 16-bit PWC
MB91345 Series
• When Read/Modify/Write (RMW) commands are used for the reading, the read value will be "11B"
regardless of its operation.
• To write STRT/STOP bits for starting/stopping the counter, bit processing command (e.g. Bit clear
command) can be used for the corresponding bits. However, to read the operation status, bit
processing command cannot be used. (When it is read, note that "Counting is running". is always
displayed.)
[bit13] EDIR: Interrupt request flag at the termination of the measurement
This bit is a flag used to indicate that measurement is terminated when it is in the pulse-width
measurement mode. If this bit is set when the interrupt request at the termination of the measurement is
permitted (bit12: EDIE=1), the interrupt request at the termination of the measurement is generated.
Setting trigger
This bit is set when the pulse-width measurement is terminated (Measurement
results are stored into the PWCR0). [Initial value]
Clearing trigger
This bit is cleared when the PWCR0 (measurement results) is read.
• When reset, it is initialized to "0".
• Only Read is enabled. Writing does not affect the bit value.
[bit12] EDIE: Interrupt request permission bit at the termination of the measurement
This bit controls the interrupt request at the termination of the measurement as follows, when it is in the
pulse-width measurement mode.
0
Disables the interrupt request output at the termination of the measurement.
[Initial value] (Even if EDIR is set, the interrupt is not generated.)
1
Enables the interrupt request output at the termination of the measurement.
(If EDIR is set, the interrupt is generated.)
• When reset, it is initialized to "0".
• Read/Write is enabled.
[bit11] OVIR: Interrupt request flag for the counter overflow
This flag is used to indicate that 16-bit up counter overflows from "FFFFH" to "0000H" in all modes. If
this bit is set when the interrupt request flag for the counter overflow is enabled (bit10: OVIE=1), the
interrupt request flag for the counter overflow is generated.
Setting trigger
This bit is set when the counter overflow occurs.
(When the counter overflows from FFFFH to 0000H.)
Clearing trigger
This bit is cleared when "0" is written.
• When reset, it is initialized to "0".
• Read/Write is enabled. For writing, only "0" can be used. Even if writing "1", it does not affect the bit
value.
• When Read/Modify/Write commands are used, read value will be "1" regardless of its bit value.
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12.2 Register of the 16-bit PWC
MB91345 Series
[bit10] OVIE: Interrupt request permission bit for the counter overflow
This bit controls the interrupt request for the counter overflow as follows.
0
Disables the interrupt request output for the overflow.
(Even if OVIR is set, the interrupt is not generated.)
1
Enables the interrupt request output for the overflow.
(If OVIR is set, the interrupt is generated.)
[Initial value]
• When reset, it is initialized to "0".
• Read/Write is enabled.
[bit9] ERR: Error flag
This flag is used to indicate that next measurement is terminated before the measurement results in the
PWCR0 are read when it is in the continuous pulse-width measurement mode. In this case, the PWCR0
value is updated to a new measurement result. The last measurement result is deleted. Measurement is
continued regardless of this bit value.
Setting trigger
This bit is set when unread measurement result is deleted by the next result.
Clearing trigger
This bit is cleared when the PWCR0 (measurement results) is read.
• When reset, it is initialized to "0".
• Only Read is enabled. Writing does not affect the bit value.
[bit8] (Reserved)
This bit is a reserved bit. The read value is "0".
Write "0" always.
[bit7, bit6] CKS1, CKS0: Clock selection bits
These bits are used to select internal counting as follows.
CKS1
CKS0
Count clock selection
0
0
Peripheral clock divided by 4
0
1
Peripheral clock divided by 16
1
0
Peripheral clock divided by 32
1
1
Setting disabled.
[Initial value]
• When reset, it is initialized to "00B".
• Read/Write is enabled. Do not set "11B".
Note:
After the counter is started, rewriting is disabled. Make sure to write these bits before the counter
starts or after the counter stops.
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12.2 Register of the 16-bit PWC
MB91345 Series
[bit5, bit4] PIS1, PIS0: Pulse-width measurement input pin selection bits
Write "00B" always for these bits.
These bits are used to select the pulse-width measurement input pin.
PIS1
PIS0
Input clock selection
0
0
(Selects PWC0 pin.)
0
1
Selects to compare two inputs (Rising edges are compared).
It is disabled in this product.
1
0
Selects to compare two inputs (Falling edges are compared).
It is disabled in this product.
1
1
Setting disabled.
[Initial value]
• When reset, it is initialized to "00B".
• Read/Write is enabled. Do not set "11B".
These bits are enabled for only PWC0. (PWC0/PWC1 is used for the input.) For more information, see
"■ Details of operation for the pulse-width measurement" in the section "12.3 Operation of the 16-bit
PWC".
Note:
Since this product is equipped with PWC 1 channel, the width measurement function to compare two
inputs cannot be used.
After the counter is started, rewriting is disabled. Make sure to write these bits before the counter
starts or after the counter stops.
[bit3] SC: Measurement mode (one-time/continuous) selection bit
This bit is used to select the measurement mode as follows.
SC
When it is in the pulse-width
measurement mode
Measurement mode selection
0
One-time measurement mode
[Initial value]
It is stopped when one-time measurement
is terminated.
1
Continuous measurement mode
Continuous measurement: buffer register
is enabled.
• When reset, it is initialized to "0".
• Read/Write is enabled.
Note:
After the counter is started, rewriting is disabled. Make sure to write this bit before the counter starts
or after the counter stops.
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12.2 Register of the 16-bit PWC
MB91345 Series
[bit2, bit1, bit0] MOD2, MOD1, MOD0: Operation mode/Measurement edge selection bits
These bits are used to select edges which carry out the operation mode and width measurement as
follows.
MOD2 MOD1 MOD0
Operation mode/Measurement edge selection
0
0
0
Pulse-width measurement mode between all edges ( or  through  or ).
[Initial value]
0
0
1
Division cycle measurement mode (Input divider is enabled.)
0
1
0
Cycle measurement mode between rising edges ( through )
0
1
1
"H" pulse-width measurement mode ( through )
1
0
0
"L" pulse-width measurement mode ( through )
1
0
1
Cycle measurement mode between falling edges ( through )
1
1
0
1
1
1
Setting disabled.
• When reset, it is initialized to "000B".
• Read/Write is enabled.
Note:
After the counter is started, rewriting is disabled. Make sure to write these bits before the counter
starts or after the counter stops.
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12.2 Register of the 16-bit PWC
12.2.2
MB91345 Series
PWC Data Buffer Register (PWCR0)
This register is a buffer used to retain the measurement results.
■ PWC Data Buffer Register (PWCR0)
PWCR0 high order
Address
0000FAH
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
PWC15 PWC14 PWC13 PWC12 PWC11 PWC10 PWC09 PWC08
R
R
R
R
R
R
R
R
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00000000B
PWCR0 low order
Address
0000FBH
PWC07 PWC06 PWC05 PWC04 PWC03 PWC02 PWC01 PWC00
R
R:
R
R
R
R
R
R
Initial value
00000000B
R
Read only
If it is in continuous measurement mode (PWCSR0 bit3: SC=1), this buffer register retains last
measurement results. In this case, only Read is enabled. Writing does not affect any register value.
If it is in one-time measurement mode (PWCSR0 bit3: SC=0), this register directly accesses the up counter.
In this case, only Read is enabled. Writing does not affect any register value. Reading is always enabled as
needed. Read value will be the counted value during the counting. After the measurement is terminated,
measurement results will be stored.
• When reset, it is initialized to "0000H".
• Only Read is enabled.
Note:
To access to this register, make sure to use a half-word or a word transfer command.
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12.2 Register of the 16-bit PWC
MB91345 Series
12.2.3
Division Ratio Control Register (PDIVR0)
Division ratio control register is used to control the counted value of the 16-bit free-run
timer.
■ Division Ratio Control Register (PDIVR0)
PDIVR0
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0000FDH










DIV2
DIV1
DIV0
XXXXX000B
R/W
R/W
R/W
R/W:
Readable/writable
This register is used when it is in the division cycle measurement mode (PWCSR0 bit2, bit1, bit0: MOD2,
MOD1, MOD0=001B). When it is in any other mode, this register is useless.
When it is in the division cycle measurement mode, this register measures single cycle width by dividing
the pulse inputted in measurement pins according to the division ratio set by this register. The division ratio
is selected as follows.
DIV2
DIV1
DIV0
Division ratio selection
0
0
0
0
0
1
22=4 divisions
0
1
0
23=8 divisions
0
1
1
24=16 divisions
1
0
0
25=32 divisions
1
0
1
26=64 divisions
1
1
0
27=128 divisions
1
1
1
28=256 divisions
21=2 divisions
[Initial value]
• When reset, it is initialized to "000B".
• Read/Write is enabled.
Note:
After the counter is started, rewriting is disabled. Make sure to write these bits before the counter
starts or after the counter stops.
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12.3 Operation of the 16-bit PWC
12.3
MB91345 Series
Operation of the 16-bit PWC
16-bit PWC is equipped with the measurement input pins and the 8-bit input divisions.
PWC provides the pulse-width measurement function which can select three types of
count clocks. This section describes basic functions and operations of the pulse-width
measurement function.
■ Pulse-width Measurement Function
This function measures times and cycles between any given events of the input pulse using the counter.
Once it is started, the counting is not carried out until the specified measurement start edge is inputted. Counting
up starts when the counter which detects the start edge is cleared to "0000H". Counting stops when stop edge is
detected. Counted values between these counting are stored into the register as the pulse-width.
Upon the termination of measurement and overflow occurrence, this function allows interrupt request to
generate.
Upon the termination of the measurement, the following operations are provided depending on its measurement
mode.
• One-time measurement mode: It stops the operation.
• Continuous measurement mode: It transfers the counter value into the buffer register and then stops the
counting until the measurement start edge is inputted again.
(Solid line = counted value)
PWC input .
Measured pulse
counted value
FFFFH
Counting is cleared.
0000H
Measurement
is started.
Counting
is started.
Counting
is stopped.
Time
EDIR flag is set. (Measurement is terminated.)
Operation of pulse-width measurement (One-time measurement mode/"H" width measurement)
(Solid line = counted value)
PWC input .
Measured pulse
counted value
Overflow
FFFFH
Data is transferred
to the PWCR0.
Data is transferred to the PWCR0.
Counting is cleared.
Counting is cleared.
0000H
Measurement
is started.
Counting
is started.
Counting
is stopped.
Counting
is started.
OVIR flag is set.
EDIR flag is set. (Measurement is terminated.)
Counting
is stopped.
Time
EDIR flag is set.
Operation of pulse-width measurement (Continuous measurement mode/"H" width measurement)
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12.3 Operation of the 16-bit PWC
MB91345 Series
■ Count Clock Selection
Count clock of the counter can be selected from among the three types of internal clock sources using the
setting of bit7, bit6: CKS1, CKS0 of the PWCSR0 register.
The following count clocks are available for selection.
Table 12.3-1 Count Clock Selection
PWCSR0
Internal count clocks available for selection
CKS1, CKS0
00B
Peripheral clock divided by 4
01B
Peripheral clock divided by 16
10B
Peripheral clock divided by 32
[Initial value]
For the initial value by reset, peripheral clock divided by 4 will be selected.
Note:
To select a count clock, make sure to do it before the counter starts.
■ Operation Mode Selection
To select the operation mode and measurement mode, use the setting of PWCSR0.
• To set an operation mode: PWCSR0 bit2 to bit0: MOD2, MOD1, MOD0
(Pulse-width measurement modes are selected and measurement edges are determined.)
• To set a measurement mode: PWCSR0 bit3: SC
(One-time measurement or continuous measurement will be selected.)
The following table shows the operation mode list with the combination of mode setting bits.
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12.3 Operation of the 16-bit PWC
MB91345 Series
Table 12.3-2 Operation Mode List with Combination of Mode Setting Bits
Operation mode
SC
MOD2 MOD1 MOD0
 or  through  or 
Measurement between all
edges
One-time measurement: Buffer is disabled.
0
0
0
0
Continuous measurement: Buffer is enabled.
1
0
0
0
Division cycle
measurement (1 division
through 256 divisions)
One-time measurement: Buffer is disabled.
0
0
0
1
Continuous measurement: Buffer is enabled.
1
0
0
1
 through  :
Cycle measurement
between rising edges
One-time measurement: Buffer is disabled.
0
0
1
0
Continuous measurement: Buffer is enabled.
1
0
1
0
One-time measurement: Buffer is disabled.
0
0
1
1
Continuous measurement: Buffer is enabled.
1
0
1
1
 through :
"L" pulse-width
measurement
One-time measurement: Buffer is disabled.
0
1
0
0
Continuous measurement: Buffer is enabled.
1
1
0
0
 through :
Cycle measurement
between falling edges
One-time measurement: Buffer is disabled.
0
1
0
1
Continuous measurement: Buffer is enabled.
1
1
0
1
0
1
1
0
1
1
1
0
0
1
1
1
1
1
1
1
Pulse-width
measurement  through :
"H" pulse-width
measurement
Setting disabled.
For the initial value by reset, measurement between all edges (one-time measurement mode) will be
selected.
Note:
To select a start mode, make sure to do it before the counter starts.
■ Start and Stop of Pulse-width Measurement
To start, restart and forcedly stop each operation, use bit15, bit14: STRT, STOP of the PWCSR0.
Pulse-width measurement has different functions depending on the STRT bit which is used to start/restart
the pulse-width measurement and STOP bit which is used to forcedly stop the pulse-width measurement.
When "0" is written into each bit, it functions. In this case, the values written to both bits are exclusively
each other. Otherwise, it does not function. To write the value using the commands other than bit operating
commands (byte size or more), make sure to write the following combinations.
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12.3 Operation of the 16-bit PWC
MB91345 Series
Table 12.3-3 Start and Stop of Pulse-width Measurement
Function
STRT
STOP
Start and restart of the pulse-width measurement
0
1
Forced stop of the pulse-width measurement
1
0
If you use a bit operating command (bit clearing command), your hardware will automatically write the
value using the combinations mentioned above so that you do not need to pay any attention.
• Operation upon the start of the pulse-width measurement mode
Counting will not be carried out until the measurement start edge is inputted. Upon the detection of the
measurement start edge, 16-bit up counter is cleared to "0000H" to start the counting.
• About the restart
- Activating the counting (to write "0" into STRT bit) during the operation after the start of pulse-width
measurement is called the "restart". If this restart is activated, the following operation will be carried
out.
- When it is in the status waiting for measurement start edge, it does not affect the operation. During
the measurement, it stops the counting and it will be in the status waiting for measurement start edge
again. In this case, if the detection of measurement termination edge and restart occur at the same
time, measurement termination flag (EDIR) is set. When it is in the continuous measurement mode,
measurement results are transferred to the PWCR0.
• About the stop
- When it is in the one-time measurement mode, counter overflow or termination of the measurement
will automatically stop the counting so that you do not need to pay attention. When it is in other
modes or if you want to stop it before it is stopped automatically, you need to forcedly stop it.
- If PWC1 edge selected to compare two inputs is not placed before the forced stop, the first
measurement result right after the restart will be incorrect. Forced stop shall be inputted after the
PWC1 edge is inputted.
Note:
Since this product is equipped with PWC 1 channel, the width measurement function to compare two
inputs cannot be used.
• To verify the operation status
As mentioned above, STRT and STOP bits play a role as a bit to display the operation status when it is
read. Displayed values show the following details.
Table 12.3-4 Operation Status Display of STRT Bit and STOP Bit
CM71-10132-3E
STRT
STOP
Operation status
0
0
Counting is stopped. (Except for the status waiting for measurement start edge.)
The counter is not activated or measurement is terminated.
1
1
Counting is running or it is in the status waiting for measurement start edge.
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12.3 Operation of the 16-bit PWC
MB91345 Series
Note:
If you read either STRT bit or STOP bit, the read value will be the same value. Since the read value
will be always "11B" when Read/Modify/Write (RMW) commands (e.g. bit processing commands) are
used for reading this bit, do not use these commands for the reading.
■ Clearing the Counter
16-bit up counter is cleared to "0000H" in the following cases.
• When reset
• In the case to start the counting by detecting the measurement start edge when it is in pulse-width
measurement mode.
■ Details of Operation for the Pulse-width Measurement
One-time measurement and continuous measurement
• Pulse-width measurement has one-time measurement mode and continuous measurement mode. Each
mode is selected by SC bit of the PWCSR0 (See "■ Operation mode selection" in this section). The
differences between these modes are as follows.
- One-time measurement mode:
When the first measurement termination edge is inputted, the counting of the counter is stopped and then
measurement termination flag (EDIR) of the PWCSR0 is set. Subsequent measurement will not be carried
out. However, if the restart is activated at the same time, it is in the status waiting for the measurement start.
- Continuous measurement mode:
When the measurement termination edge is inputted, the counting of the counter is stopped and then
measurement termination flag (EDIR) of the PWCSR0 is set. The counting is stopped until the
measurement start edge is inputted again. Upon the input of the measurement start edge again, the counter is
cleared to "0000H" and then the measurement is started. Upon the termination of the measurement,
measurement results of the counter are transferred to the PWCR0.
Note:
To select or change a measurement mode, make sure to do it when the counter is stopped.
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12.3 Operation of the 16-bit PWC
MB91345 Series
• Data of measurement results
- Depending on the one-time measurement mode and continuous measurement mode, there are
differences in the handling of measurement results and counter value, and PWCR0 functions. The
differences of measurement results between these modes are as follows.
- One-time measurement mode:
If PWCR0 is read during the operation, the counted value will be obtained during the measurement. If
PWCR0 is read after the measurement, data of measurement results will be obtained.
- Continuous measurement mode:
Upon the termination of the measurement, measurement results of the counter are transferred to the
PWCR0. If PWCR0 is read, the last measurement results will be obtained. During the measurement,
the last measurement result will be retained. Counted values during the measurement will not be read.
If the next measurement is terminated before the measurement results are read when it is in the
continuous measurement mode, the last measurement result is overwritten by the new measurement
result. In this case, an error flag (ERR) in the PWCSR0 is set. Error flag (ERR) is automatically
cleared upon the reading of the PWCR0.
• Measurement mode and counting operation
Depending on which part of inputted pulse is measured, measurement mode can be selected from among
the five types of measurement modes. In addition, it provides the mode which divides the inputted pulse to
measure the cycle so that pulse width with upper frequency is accurately measured. These are described in
the following table.
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12.3 Operation of the 16-bit PWC
MB91345 Series
Table 12.3-5 Measurement Mode and Counting Operation
Measurement
mode
MOD2
MOD1
MOD0
Measured description (W: pulse width to be measured)
W
Pulse-width
measurement
between all edges
↑ Counting
is started.
0
0
0
Cycle
measurement
between rising
edges
↑ Stop
↑ Start
W
0
0
1
It measures the cycle by dividing the input pulse according to the
division ratio selected in the division ratio setting register, PDIVR0.
Counting (measurement) starts when the rising edge is detected right
after the starting.
Counting (measurement) terminates when the single cycle terminates
after the division.
W
0
1
0
↑ Counting
is started.
W
W
↑ Counting
is stopped.
↑
↑ Stop
↑ Start
0
1
1
↑ Counting
is started.
W
↓ Counting
is stopped.
↑
Start
346
↓
Stop
Pulse width within the "H" cycle is measured.
Counting (measurement) starts when the rising edge is detected.
Counting (measurement) terminates when the falling edge is detected.
W
1
0
0
↓ Counting
is started.
↑ Counting
is stopped.
↓ Counting
is started.
1
0
↓
Start
↑
Stop
Pulse width within the "L" cycle is measured.
Counting (measurement) starts when the falling edge is detected.
Counting (measurement) terminates when the rising edge is detected.
W
Cycle
measurement
between falling
edges
↑
It measures the cycles between the rising edges.
Counting (measurement) starts when the rising edge is detected.
Counting (measurement) terminates when the rising edge is detected.
W
"L" pulse-width
measurement
W
↓ Counting
↑ Counting is stopped.
is started.
↓
↑ Start
Stop
(Example of 4 divisions)
W
"H" pulse-width
measurement
↓
Stop
Pulse width between edges continuously inputted will be measured.
Counting (measurement) starts when the edge is detected.
Counting (measurement) terminates when the edge is detected.
W
Division cycle
measurement
W
W
↓ Counting
is stopped.
↓ Start
W
W
↓ Counting
is stopped.
1
↓ Stop
↓ Start
↓
Stop
It measures the cycles between the falling edges.
Counting (measurement) starts when the falling edge is detected.
Counting (measurement) terminates when the falling edge is detected.
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12.3 Operation of the 16-bit PWC
MB91345 Series
In either mode, the counter does not carry out the counting operation until the measurement start edge is
inputted after the measurement is activated. Upon the input of the measurement start edge, the counter is
cleared to "0000H" and then up counting is continued for each count clock until the measurement
termination edge is inputted. Upon the input of the measurement termination edge, the following
operation will be carried out.
1) Measurement termination flag (EDIR) in the PWCSR0 is set.
2) Counter stops the counting operation. (Except for the case when restart occurs at the same time.)
3) Continuous measurement mode : Counter value (measurement results) is transferred to the PWCR0
and then it stops the counting to wait until the next measurement
start edge is inputted.
4) One-time measurement mode : It terminates the measurement. (Except for the case when restart
occurs at the same time.)
When it is in the continuous measurement mode, if pulse-width measurement between all edges or cycle
measurement is carried out, termination edge will be the next measurement start edge.
• Minimum inputted pulse width
- To input pulse width for the pulse-width measurement input pin (PWC0), please input the pulses
more than the minimum pulse width below.
- Minimum input width: more than machine cycle  4 (In case of 25MHz peripheral clock, more than
0.16µs is required.)
- If you input the pulse less than pulse above, we cannot assure the operation.
• Calculation formula of pulse width/cycle
Upon the termination of the measurement, calculation formula of the measured pulse width/cycle is
obtained based on measurement result data obtained by the PWCR0 as follows.
TW = n  t / DIV [s]
TW
n
t
DIV
: Measured pulse width/cycle [s]
: Measurement result data in the PWCR0
: Cycle of the count clock [s]
: Division ratio selected in the division ratio register of
PDIVR0
("1" is assigned in all modes except for the division cycle
measurement mode.)
• Measurement range of pulse width/cycle
Depending on the combination of count clock and division ratio for input divider, pulse width/cycle
range available for the measurement varies.
As an example, the following list shows sample measurement range list where peripheral clock () =
25MHz.
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12.3 Operation of the 16-bit PWC
MB91345 Series
Table 12.3-6 Measurement Range of Pulse Width/Cycle
Division ratio
DIV2,
DIV1,
DIV0
CKS1, CKS0 =
when 00B (/4)
CKS1, CKS0 =
when 01B (/16)
CKS1, CKS0 =
when 10B (/32)
No division

0.16 s to 10.5 ms
0.64 s to 41.9 ms
1.28 s to 83.9 ms
000B
0.32 s to 10.5 ms
0.64 s to 41.9 ms
1.28 s to 83.9 ms
2 divisions
0.16 s to 5.2 ms
0.32 s to 21.0 ms
0.64 s to 41.9 ms
001B
0.64 s to 10.5 ms
0.64 s to 41.9 ms
0.64 s to 83.9 ms
4 divisions
0.16 s to 2.6 ms
0.16 s to10.5 ms
0.16 s to 21.0 ms
1.28 s to 10.5 ms
1.28 s to 41.9 ms
1.28 s to 83.9 ms
0.16 s to 1.3 ms
0.16 s to 5.2 ms
0.16 s to 10.5 ms
2.56 s to 10.5 ms
2.56 s to 41.9 ms
2.56 s to 83.9 ms
0.16 s to 0.7 ms
0.16 s to 2. 6 ms
0.16 s to 5.2 ms
10.24 s to 10.5 ms
10.24 s to 41.9 ms
10.24 s to 83.9 ms
0.16 s to 0.2 ms
0.16 s to 0.7 ms
0.16 s to 1.3 ms
40.96 s to 10.5 ms
40.96 s to 41.9 ms
40.96 s to 83.9 ms
0.16 s to 41.0 s
0.16 s to 0.2 ms
0.16 s to 0.3 ms
8 divisions
010B
16 divisions
011B
64 divisions
100B
256 divisions
101B

Others
Remarks
Upper:
Counter
measurement
value
Lower:
Average pulse
width
Setting disabled.
• To generate interrupt request
The following two interrupt requests are is enabled to generate when it is in the pulse-width measurement
mode.
- Interrupt request for the counter overflow
During the measurement, if the overflow occurs due to the counting up, the overflow flag is set. If the
overflow interrupt request is permitted, interrupt request is generated.
- Interrupt request at the termination of the measurement
Upon the detection of the measurement termination edge, the measurement termination flag (EDIR)
in the PWCSR0 is set. If the measurement termination interrupt request is permitted, interrupt request
is generated. Measurement termination flag (EDIR) is automatically cleared upon the reading of the
measurement result of PWCR0.
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CHAPTER 12 16-bit PWC
12.3 Operation of the 16-bit PWC
MB91345 Series
Settings
• Pulse-width measurement operation flow
Restart
Count clock selection
Operation/Measurement mode selection
Interrupt flag clear
Interrupt permission
Measurement input pin selection
Started by the STRT bit
Continuous measurement mode
One-time measurement mode
Measurement start edge
is detected.
Counter is cleared.
Counter is cleared.
Counting is started.
Counting is started.
Up counting
Up counting
Overflow occurs.
→ OVIR flag is set.
CM71-10132-3E
Measurement start edge
is detected.
Overflow occurs.
→ OVIR flag is set.
Measurement termination edge
is detected. → EDIR flag is set.
Measurement termination edge
is detected. → EDIR flag is set.
Counting is stopped.
Counting is stopped.
Counted value is transferred
to the PWCR0.
Operation is stopped.
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CHAPTER 12 16-bit PWC
12.4 Notes on Using in the 16-bit PWC
12.4
MB91345 Series
Notes on Using in the 16-bit PWC
This section explains caution when using the 16-bit PWC.
■ Caution
• Caution in register rewritings
- These bits of the PWCSR0 register are not permitted to rewrite during the operation. Make sure to
rewrite them before the activation or after the stop.
- [bit7, bit6] CKS1, CKS0:
Clock selection bits
- [bit3] SC:
Measurement mode (one-time/continuous) selection bits
- [bit2, bit1, bit0] MOD2, MOD1, MOD0: Operation mode/Measurement edge selection bits
- PDIVR0 register is not permitted to rewrite during the operation. Make sure to rewrite it before the
activation or after the stop.
• STRT bit and STOP bit of the PWCSR0 register
Note that both bits have different functions depending on the writing and reading. (See section "12.2.1
PWC Control Status Register (PWCSR0)"). When Read/Modify/Write (RMW) commands are used, read
value will be "11B" regardless of its bit value. Therefore, bit processing command cannot be used for
reading the operation status. (When it is read, note that "Counting is running". is always displayed.) To
write the data into STRT or STOP bits for starting or stopping the counter, you can use bit processing
commands (e.g. bit clearing command) for the corresponding bits.
• Clearing the counter
Since the counter is cleared at the measurement start edge if it is in pulse-width measurement mode, all
the data within the counter before the activation is disabled.
• Minimum inputted pulse width
- Pulses available to be inputted into pulse-width measurement input pin have the following restriction.
- Minimum input width: machine cycle  4 (Where machine cycle 40ns  160ns)
- Maximum input frequency: Peripheral clock divided by 4 (Where Machine cycle 25MHz  6.2MHz)
- If you input the pulse less than above width or more than frequency pulse, we cannot assure the
operation. If input signal has such a noises, please input those by clearing such a noise using filters at
the outside the chip.
• Division cycle measurement mode
Since input pulse is divided when it is in the division cycle measurement mode of the pulse-width
measurement mode, note that pulse width which can be obtained through calculation from the
measurement result will be the average value.
• Clock selection bits
[bit7, bit6] CKS1, CKS0 in the PWCSR0 register: "11B" is disabled for the clock selection bits.
• Reserved bit
[bit8] in the PWCSR0 register is reserved bit. If you write the value in to this bit, make sure to write "0".
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MB91345 Series
CHAPTER 12 16-bit PWC
12.4 Notes on Using in the 16-bit PWC
• Restart during the operation
If the restart is activated after the counting operation is started, the following may occur depending on its
timing.
- When it is in the pulse-width one-time measurement mode if the measurement termination edge
occurs at the same time
Restart will be carried out and it will be in the status waiting for the measurement start edge.
However, the measurement termination flag (EDIR) will be set.
- When it is in the pulse-width continuous measurement mode if the measurement termination edge
occurs at the same time
Restart will be carried out and it will be in the status waiting for the measurement start edge.
However, the measurement termination flag (EDIR) will be set. Measurement results at that time
are transferred into the PWCR0.
As mentioned above, for the restart during the operation, ensure to control the interrupts by paying
attention to the flag operation.
CM71-10132-3E
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CHAPTER 12 16-bit PWC
12.4 Notes on Using in the 16-bit PWC
352
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MB91345 Series
CM71-10132-3E
CHAPTER 13
PPG Timer
This chapter describes the overview, the configuration
and functions of registers, and operation of the PPG
timer.
13.1 Overview of PPG Timer
13.2 Block Diagrams of PPG Timer
13.3 PPG Timer Registers
13.4 Operation Descriptions about PPG Timer
13.5 Timing Generator to PPG Timer
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CHAPTER 13 PPG Timer
13.1 Overview of PPG Timer
13.1
MB91345 Series
Overview of PPG Timer
PPG is an 8-bit reload timer module, which outputs PPG at a pulse output control in
accordance with timer operation.
On the hardware level, it contains 8-bit down counter  8, 8-bit reload register  16,
control register, external pulse output  8 and interrupt output  8.
This microcontroller is equipped with 16 channels as an 8-bit PPG and 8 channels as a
16-bit PPG.
■ PPG Functions
● 8-bit PPG output independent operation mode
Independent PPG output operation is enabled.
● 16-bit PPG output operation mode
16-bit PPG output operation of 1 channel is enabled.
● 8+8-bit PPG output operation mode
When ch.(n+1) output is set as a clock input of ch.(n), 8-bit PPG output can be operated for any period.
(n = 0, 2, 4, 6, 8, 10, 12, 14)
● 16+16-bit PPG output operation mode
This mode sets the 16-bit prescaler output of ch.(n+3)+ch.(n+2) as the 16-bit PPG clock input of ch.(n+1)
plus ch.(n).
(n = 0, 4, 8, 12)
● PPG output operation
• This operation allows pulse waves to be output at any period/duty ratio.
• When combined with an external circuit, it can also be used as a D/A converter.
● Output inversion function
This function allows PPG output values to be inverted.
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CHAPTER 13 PPG Timer
13.1 Overview of PPG Timer
MB91345 Series
■ Register List
Figure 13.1-1 PPG Start Register (PPGTRG)
PPG start register (PPGTRG)
Address
000130H
bit15
bit14
bit13
bit2
bit11
bit10
bit9
bit8
PEN15 PEN14 PEN13 PEN12 PEN11 PEN10 PEN09 PEN08
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PEN07 PEN06 PEN05 PEN04 PEN03 PEN02 PEN01 PEN00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
Initial value
00000000B
R/W
R/W: Readable/writable
Figure 13.1-2 Output Inversion Register (PPGREVC)
Output inversion register (PPGREVC)
Address
000134H
bit15
bit14
bit13
bit2
bit11
bit10
bit9
bit8
REV15 REV14 REV13 REV12 REV11 REV10 REV09 REV08
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
REV07 REV06 REV05 REV04 REV03 REV02 REV01 REV00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
Initial value
00000000B
R/W
R/W: Readable/writable
Figure 13.1-3 GATE Function Control Register (PPGGATEC)
GATE function control register (PPGGATEC)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000133H






STGR

XXXXXX00B






R/W

R/W: Readable/writable
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CHAPTER 13 PPG Timer
13.1 Overview of PPG Timer
MB91345 Series
Figure 13.1-4 PPG0 to PPGF Operation Mode Control Register (PPGC0 to PPGCF)
PPG0 to PPGF ope ration mode control register (PPGC0 to PPGCF)
Addresses:
ch.0 :000108H
ch.1 :000109H
ch.2 :00010AH
ch.3 :00010BH
ch.4 :000114H
ch.5 :000115H
ch.6 :000116H
ch.7 :000117H
ch.8 :000120H
ch.9 :000121H
ch.A :000122H
ch.B :000123H
ch.C :00012CH
ch.D :00012DH
ch.E :00012EH
ch.F :00012FH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PIEn
PEN07 PUFn
PEN06 INTMn
PEN05 PCS1
PEN04 PCS0
PEN03 MD1*
PEN02 MD0*
PEN01 TTRGn
PEN00
PEN07 PEN06 PEN05 PEN
04
PEN03 PEN02
PEN07 PEN06 PEN05 PEN04 PEN03
PEN01 PEN00
PEN07 PEN06 PEN05 PEN04 PEN03 PEN02 PEN01 PEN00
PEN07 PEN06 PEN05 PEN04
R/W
R/W
R/W
R/W
R/W
n = 0 to F
R/W
R/W
R/W
Initial value: 0000000XB
* : MD1 and MD0 only exist in
even-numbered channels and do not
exist in odd-numbered channels. The
initial values for odd-numbered
channels are indeterminate. Write is
invalid.
R/W : Readable/Writable
Figure 13.1-5 Reload Registers: 8-bit PPG Mode
Reload register H (PRLH0 to PRLHF)
Addresses:
ch.0 :000100 H
ch.1 :000102 H
ch.2 :000104 H
ch.3 :000106 H
ch.4 :00010C H
ch.5 :00010E H
ch.6 :000110 H
ch.7 :000112 H
ch.8 :000118 H
ch.9 :00011A H
ch.A :00011C H
ch.B :00011E H
ch.C :000124 H
ch.D :000126 H
ch.E :000128 H
ch.F :00012A H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: XXXXXXXXB
Reload register L (PRLL0 to PRLLF)
Addresses:
ch.0 :000101H
ch.1 :000103H
ch.2 :000105H
ch.3 :000107H
ch.4 :00010DH
ch.5 :00010FH
ch.6 :000111H
ch.7 :000113H
ch.8 :000119H
ch.9 :00011BH
ch.A :00011DH
ch.B :00011FH
ch.C :000125H
ch.D :000127H
ch.E :000129H
ch.F :00012BH
bit7
bit6
R/W
bit5
R/W
bit4
R/W
bit3
R/W
bit2
R/W
bit1
R/W
bit0
R/W
R/W
Initial value: XXXXXXXXB
R/W: Readable/writable
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CHAPTER 13 PPG Timer
13.1 Overview of PPG Timer
MB91345 Series
● Reload registers: 16-bit PPG mode
Reload register H (PRLH0, PRLH2, PRLH4, PRLH6, PRLH8, PRLHA, PRLHC, PRLHE)
Figure 13.1-6 Reload Register H: 16-bit PPG Mode
Reload register H (PRLH0, PRLH2, PRLH4, PRLH6, PRLH8, PRLHA, PRLHC, PRLHE)
Addresses:
ch.0 :000100H
ch.2 :000104H
ch.4 :00010CH
ch.6 :000110H
ch.8 :000118H
ch.A :00011CH
ch.C :000124H
ch.E :000128H
bit15
bit14
R/W
bit13
R/W
bit7
R/W
bit6
R/W
bit12
R/W
bit5
R/W
bit11
R/W
bit4
R/W
bit10
R/W
bit3
R/W
bit9
R/W
R/W
Initial value: XXXXXXXXB
bit2
R/W
bit8
bit1
R/W
bit0
R/W
R/W
Initial value: XXXXXXXXB
R/W: Readable/writable
Reload register L (PRLL0, PRLL2, PRLL4, PRLL6, PRLL8, PRLLA, PRLLC, PRLLE)
Figure 13.1-7 Reload Register L: 16-bit PPG Mode
Reload register L (PRLL0, PRLL2, PRLL4, PRLL6, PRLL8, PRLLA, PRLLC, PRLLE)
Addresses:
ch.0 :000101H
ch.2 :000105H
ch.4 :00010DH
ch.6 :000111H
ch.8 :000119H
ch.A :00011DH
ch.C :000125H
ch.E :000129H
R/W: Readable/writable
CM71-10132-3E
bit15
bit14
R/W
bit13
R/W
bit7
bit6
R/W
R/W
bit12
R/W
bit5
R/W
bit11
R/W
bit4
R/W
bit10
R/W
bit3
R/W
bit9
R/W
bit8
R/W
R/W
Initial value: XXXXXXXXB
bit2
bit1
bit0
R/W
R/W
R/W
Initial value: XXXXXXXXB
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CHAPTER 13 PPG Timer
13.2 Block Diagrams of PPG Timer
13.2
MB91345 Series
Block Diagrams of PPG Timer
This section displays PPG block diagrams.
■ Block Diagram of 8-bit PPG ch.0, ch.2, ch.4, ch.6
Figure 13.2-1 Block Diagram of 8-bit PPG ch.0, ch.2, ch.4, ch.6
Borrow of ch.(n+1)
Peripheral clock divided by 64
Peripheral clock divided by 16
Peripheral clock divided by 4
Peripheral clock
To a port
PPG
output latch
Inverted
Cleared
0
1
TTRGn
Count clock
selection
S
R Q
PCNT (down counter)
PEN(n+1)
TTRGI(n+1)
From the
timing
generator
IRQn
Reload
“H”/“L” select
“H”/“L” selector
PRLLn
PIEn
PRLHn
PUFn
“L”-side data bus
“H”-side data bus
PPGCn / PPGTRG
n = 0, 2, 4, 6
358
Operation mode (control)
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CM71-10132-3E
CHAPTER 13 PPG Timer
13.2 Block Diagrams of PPG Timer
MB91345 Series
■ Block Diagram of 8-bit PPG ch.1, ch.5
Figure 13.2-2 Block Diagram of 8-bit PPG ch.1, ch.5
Borrow of ch.(n+1)
Peripheral clock divided by 64
Peripheral clock divided by 16
Peripheral clock divided by 4
Peripheral clock
To a port
PPG
output latch
Inverted
Cleared
0
1
PEN(n+1)
TTRGI(n+1)
TTRGn From the
timing generator
S
R Q
IRQn
Count clock
selection
PCNT (down counter)
Reload
“H”/“L” select
.
“H”/“L” selector
PUFn
PIEn
PRLLn
PRLHn
“L”-side data bus
“H”-side data bus
PPGCn / PPGTRG
n = 1, 5
CM71-10132-3E
Operation mode (control)
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CHAPTER 13 PPG Timer
13.2 Block Diagrams of PPG Timer
MB91345 Series
■ Block Diagram of 8-bit PPG ch.3, ch.7
Figure 13.2-3 Block Diagram of 8-bit PPG ch.3, ch.7
To a port
Peripheral clock divided by 64
Peripheral clock divided by 16
Peripheral clock divided by 4
Peripheral clock
PPG
output latch
Inverted
Cleared
0
1
TTRGn
S
R Q
Count clock
selection
PEN(n+1)
TTRGI(n+1)
From the
timing generator
IRQn
PCNT (down counter)
Reload
“H”/“L” select
“H”/“L” selector
PUFn
PIEn
PRLLn
PRLHn
“L”-side data bus
“H”-side data bus
PPGCn / PPGTRG
n = 3, 7
360
Operation mode (control)
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 13 PPG Timer
13.2 Block Diagrams of PPG Timer
MB91345 Series
■ Block Diagram of the GATE Function
Figure 13.2-4 Block Diagram of the GATE Function
From TRG register
PEN0 PEN1
Selector
Selector
0
1
PEN0 of
PPG ch.0
0 clip
Selector
PEN1 of
PPG ch.1
STGR
0
1
CM71-10132-3E
0
X
1
X
1
X
FUJITSU SEMICONDUCTOR LIMITED
MD1
MD0
ch.0
MD1
MD0
ch.1
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CHAPTER 13 PPG Timer
13.3 PPG Timer Registers
13.3
MB91345 Series
PPG Timer Registers
This section describes the PPG registers.
■ PPGCn Register (PPGn Operation Mode Control Register)
n=0 to F
Figure 13.3-1 PPGCn Register (PPGn Operation Mode Control Register)
PPGn Operation Mode Control Register(PPGCn) n=0 to F
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ch.0:000108H
ch.1:000109H
ch.2:00010AH
ch.3:00010BH
ch.4:000114H
ch.5:000115H
ch.6:000116H
ch.7:000117H
ch.8:000120H
ch.9:000121H
ch.A:000122H
ch.B:000123H
ch.C:00012CH
ch.D:00012DH
ch.E:00012EH
ch.F:00012FH
PIEn
PUFn
INTMn
PCS1
PCS0
MD1
MD0
TTRGn
0000000XB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W:
Readable/writable
[bit7] PIEn(Ppg Interrupt Enable) : PPG interrupt enable bit
PPG interrupts are controlled in the following manner.
Table 13.3-1 PPG Interrupt Enable Bit
0
Disables interrupts
1
Enables interrupts
• When PUFn becomes "1" while this bit is "1", an interrupt request is generated.
• When the bit is "0", no interrupt request is generated.
• A reset initializes the status to "0".
• Read/write is enabled.
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CHAPTER 13 PPG Timer
13.3 PPG Timer Registers
MB91345 Series
[bit6] PUFn(Ppg Underflow Flag) : PPG counter underflow bit
The PPG counter underflow bit is controlled in the following manner.
Table 13.3-2 PPG Counter Underflow Bit
0
PPG counter underflow is not detected.
1
PPG counter underflow is detected.
• In the 8-bit PPG 2-channel mode and the 8-bit prescaler plus 8-bit PPG mode, it is set to "1" by the
underflow that occurs when the count value for ch.0 becomes "00H"-"FFH".
• In the 16-bit PPG 1-channel mode, it is set to "1" by the underflow that occurs when the count value
for ch.1/ch.0 becomes "0000H"-"FFFFH".
• It becomes "0" by writing "0".
• Writing "1" to this bit is invalid.
• When a read operation is performed to read-modify-write (RMW) instruction, "1" is read.
• A reset initializes the status to "0".
• Read/write is enabled.
[bit5] INTMn(Interrupt Mode) : Interrupt mode bit
This bit allows PUFn bit to be detected only when underflow from PRLBHn occurs.
Table 13.3-3 Interrupt Mode Bit
0
Sets PUFn to "1" when underflow occurs.
1
Sets PUFn to "1" only when underflow from PRLBHn occurs.
• A reset initializes the status to "0".
• Read/write is enabled.
• When this bit is set to "1", interrupts can be generated in outputting one period of PPG waveform.
• This bit must not be rewritten when interrupts are enabled.
[bit4, bit3] PCS1/PCS0(Ppg Count Select): Count clock selection bits
The operation clock of the down counter is selected in the following method.
Table 13.3-4 Count Clock Selection Bits
PCS1
PCS0
Operation Mode
0
0
Peripheral clock
(when a 40ns peripheral clock is used at 25MHz)
0
1
Peripheral clock/4
(when a 160ns peripheral clock is used at 25MHz)
1
0
Peripheral clock/16
(when a 0.64µs peripheral clock is used at 25MHz)
1
1
Peripheral clock/64
(when a 2.56µs peripheral clock is used at 25MHz)
• Reset initializes the status to "00B".
• Read/write is enabled.
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CHAPTER 13 PPG Timer
13.3 PPG Timer Registers
MB91345 Series
[bit2, bit1] MD1/MD0(ppg count MoDe) : Operation mode selection bits
The operation mode of the PPG timer is selected in the following method.
Table 13.3-5 Operation Mode Selection Bits
MD1
MD0
Operation Mode
0
0
8-bit PPG 2-channel independent mode
0
1
8-bit prescaler plus 8-bit PPG mode
1
0
16-bit PPG mode
1
1
16-bit prescaler plus 16-bit PPG mode
• A reset initializes the status to "00B".
• Read/write is enabled.
• These bits only exist in even-numbered channels.
[bit0] TTRGn(Timing TRGer) : Timing trigger selection bit
This bit allows PPG to be started only when a start signal is sent from the timing generator.
Table 13.3-6 Timing Trigger Selection Bit
0
Starts by the PPGTRG register
1
Starts only by the timing generator
• A reset initializes the status to "0".
• Read/write is enabled.
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CHAPTER 13 PPG Timer
13.3 PPG Timer Registers
MB91345 Series
■ PRLL/PRLH Registers (Reload Registers)
Figure 13.3-2 PRLL/PRLH Registers (Reload Registers)
Reload register H (PRLH0 to PRLHF)
Addresses:
ch.0 :000100 H
ch.1 :000102 H
ch.2 :000104 H
ch.3 :000106 H
ch.4 :00010C H
ch.5 :00010E H
ch.6 :000110 H
ch.7 :000112 H
ch.8 :000118 H
ch.9 :00011A H
ch.A :00011C H
ch.B :00011E H
ch.C :000124 H
ch.D :000126 H
ch.E :000128 H
ch.F :00012A H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: XXXXXXXXB
Reload register L (PRLL0 to PRLLF)
Addresses:
ch.0 :000101H
ch.1 :000103H
ch.2 :000105H
ch.3 :000107H
ch.4 :00010DH
ch.5 :00010FH
ch.6 :000111H
ch.7 :000113H
ch.8 :000119H
ch.9 :00011BH
ch.A :00011DH
ch.B :00011FH
ch.C :000125H
ch.D :000127H
ch.E :000129H
ch.F :00012BH
bit7
bit6
R/W
bit5
R/W
bit4
R/W
bit3
R/W
bit2
R/W
bit1
R/W
bit0
R/W
R/W
Initial value: XXXXXXXXB
R/W : Readable/writable
These registers retain the reload values for the down counter PCNT. Each register has the following role.
Table 13.3-7 Role of PRLL/PRLH Register
Register Name
Function
PRLL
Retains the reload value for the "L"-side
PRLH
Retains the reload value for the "H"-side
Both registers are enabled to read/write.
Note:
When used in the 8-bit prescaler plus 8-bit PPG mode and the 16-bit prescaler plus 16-bit PPG
mode, it is recommended to set the same value to both PRLL and PRLH on the prescaler side
because PPG waveform may vary from cycle to cycle if different values are set to them.
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CHAPTER 13 PPG Timer
13.3 PPG Timer Registers
MB91345 Series
■ PPGTRG Register (PPG Start Register)
Figure 13.3-3 PPGTRG Register (PPG Start Register)
PPG start register (PPGTRG)
Address
000130H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
PEN15 PEN14 PEN13 PEN12 PEN11 PEN10 PEN09 PEN08
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PEN07 PEN06 PEN05 PEN04 PEN03 PEN02 PEN01 PEN00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
Initial value
00000000B
R/W
R/W: Readable/writable
[bit15 to bit0] PEN15 to PEN00(Ppg ENable) : PPG operation enable bits
PPG operation is started and its operation mode is selected in the following method.
Table 13.3-8 PPG Operation Enable Bits
PEN15 to PEN00
Operation State
0
Stops operation (Retains the "L" level of output)
1
Enables the operation of PPG
• A reset initializes the status to "0".
• Read/write is enabled.
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CHAPTER 13 PPG Timer
13.3 PPG Timer Registers
MB91345 Series
■ PPGREVC Register (Output Inversion Register)
Figure 13.3-4 PPGREVC Register (Output Inversion Register)
Output inversion register (PPGREVC)
Address
000134H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
REV15 REV14 REV13 REV12 REV11 REV10 REV09 REV08
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
REV07 REV06 REV05 REV04 REV03 REV02 REV01 REV00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
Initial value
00000000B
R/W
R/W: Readable/writable
[bit15 to bit0] REV15 to REV00 : Output inversion bits
These bits invert the PPG output values including the initial level.
Table 13.3-9 Output Inversion Bits
REV15 to REV00
Output Level
0
Normal
1
Inverted
• A reset initializes the status to "0".
• Read/write is enabled.
• As this bit simply inverts a PPG output, the initial level is also inverted.
"L" and "H" of the reload register are also inverted.
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CHAPTER 13 PPG Timer
13.3 PPG Timer Registers
MB91345 Series
■ PPGGATEC Register (GATE Function Control Register)
Figure 13.3-5 PPGGATEC Register (GATE Function Control Register)
GATE function control register (PPGGATEC)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000133H






STGR

XXXXXX00B






R/W

R/W: Readable/writable
[bit1] STGR : GATE function selection bit
Whether to start PPG by using the TRG register is determined in the following manner.
Table 13.3-10 GATE Function Selection Bit
STGR
Operation Mode
0
Starts PPG by using the TRG register
1
Disables this setting
• A reset initializes the status to "0".
• Read/write is enabled.
368
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
MB91345 Series
13.4
CHAPTER 13 PPG Timer
13.4 Operation Descriptions about PPG Timer
Operation Descriptions about PPG Timer
PPG has 8 channels of 8-bit-long PPG units. When these channels are jointly operated,
PPG can perform three types of operations, not only the independent mode, but also the
8-bit prescaler plus 8-bit PPG mode, the 16-bit PPG 1 channel mode, and the 16-bit
prescaler plus 16-bit PPG mode.
Each of the 8-bit long PPG units contains two 8-bit long reload registers on the "L" and "H" sides (PRLL
and PRLH). The values written in these registers are reloaded to the 8-bit down counter (PCNT)
alternatively on the "L" and "H" sides. After down-counted by every count clock, they invert the values of
the pin output (PPG) when reload is performed by a counter borrow. Through this operation, the pin output
(PPG) becomes pulse output with the "L"/"H" widths supporting reload register values.
The operation is started/restarted by writing a bit to the register.
The relation between reload operation and pulse output is as follows.
Table 13.4-1 Relationship Between Reload Operation and Pulse Output
Reload Operation
Pin Output Change
PRLH  PCNT
PPGn [0 1]
PRLL  PCNT
PPGn [1 0]
n = 0 to 7
When bit7: PIEn of the PPGCn register is "1", an interrupt request is output by a borrow to the counter
"00H" to "FFH" (in the 16-bit PPG mode, a borrow to "0000H" to "FFFFH").
● Operation modes
This block contains four types of operation modes: the independent mode, the 8-bit prescaler plus 8-bit
PPG mode, the 16-bit PPG 1 channel mode, and the 16-bit prescaler plus 16-bit PPG mode.
• The independent mode allows PPG to operate as a 8-bit PPG independently. The PPG output of ch.(n) is
connected to the PPG(n) pin. (n = 0 to 7)
• The 8-bit prescaler plus 8-bit PPG mode allows 1 channel to be operated as an 8-bit prescaler. Any
period of 8-bit PPG waveform can be output when its borrow output is used to count. For example, the
prescaler output of ch.1 is connected to the PPG1 pin. The PPG output of ch.0 is connected to the PPG0
pin.
• The 16-bit PPG 1 channel mode allows PPG to operate as a 16-bit PPG by joining two channels. For
example, when ch.0 and ch.1 are joined together, the 16-bit PPG output is connected to both PPG0 and
PPG1 pins.
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CHAPTER 13 PPG Timer
13.4 Operation Descriptions about PPG Timer
MB91345 Series
● PPG output operation
In relation to PPG, this block is activated to start count operation by setting the bit of each channel in
PPGTRG register (PPG start register) to "1". Once the operation has started, it is stopped by writing "0" to
the bit of each channel in the PPGTRG register. When the operation is stopped, the pulse output retains
Level "L".
In the 8-bit prescaler plus 8-bit PPG mode and the 16-bit prescaler plus 16-bit PPG mode, please do not set
PPG channels to the operation state while the prescaler channel is stopped.
In the 16-bit PPG mode, please simultaneously start/stop PENn of PPGTRG registers in the channels. (n =
0 to 7)
PPG output operation is described below.
During PPG operation, PPG continuously outputs pulse waves at the any frequency/any duty ratio (ratio
between "H" level period and "L" level period in pulse waves). Once PPG has started to output pulse
waves, the operation continues until it is set to stop.
Figure 13.4-1 PPG Output Operation - Output Waveform
PENn
Operation
started
by PENn
(from "L" side)
Output pin
PPG
T x (L+1)
T x (H+1)
Start
n = 0-7
L : PRLL value
H : PRLH value
T : Peripheral clock
(φ, φ/4, φ/16)
or
Input from the timer base counter
● Relation between the reload value and pulse width
The pulse width is calculated by adding one to the value written in the reload register and then multiplying
that figure by the count clock period. Therefore, caution should be taken when the reload register value is
"00H" during the 8-bit PPG operation and also when the value is "0000H" during the 16-bit PPG operation,
as it has a pulse width equivalent to one period of the count clock. Moreover, it should also be noted that
when the reload register value is "FFH" during the 8-bit PPG operation, it has a pulse width equivalent to
256 periods of the count clock, and when the reload register value is "FFFFH" during the 16-bit PPG
operation, it has a pulse width of 65536 periods of the count clock.
The following shows the calculating formula for the pulse width.
Pl = T  (L+1)
Ph = T  (H+1)
370
L
H
T
Ph
Pl
: PRLL value
: PRLH value
: Input clock period
: "H" pulse width
: "L" pulse width
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 13 PPG Timer
13.4 Operation Descriptions about PPG Timer
MB91345 Series
● Count Clock Selection
The count clock used for the operation of this block applies input from peripheral clocks and time-base
counters. Four types of count clock input can be selected.
The count clock operates in the following manner.
Table 13.4-2 Count Clock Operation
PPGC0 to PPGCF
Registers
Count Clock Operation
PCS1
PCS0
0
0
The count clock counts one per peripheral clock cycle.
0
1
The count clock counts one per 4 cycles of peripheral clock.
1
0
The count clock counts one per 16 cycles of peripheral clock.
1
1
The count clock counts one per 64 cycles of peripheral clock.
It should be noted that in the 8-bit prescaler plus 8-bit PPG mode and also the 16-bit prescaler plus 16-bit
PPG mode, the first count period may be deviated if the PPG side is started in the situation where the
prescaler side is in operation state but the PPG side is in the stopped state.
● Control of pulse pin output
Pulse output generated in the operation of this module can be output from the external pins PPG0 to PPGF.
In the 16-bit PPG mode, the same waveform is output from PPG(m) and PPG(m+1). Therefore, whichever
external pin output is enabled, the same output can be achieved. (m = 0, 2, 4, 6)
In the 8-bit prescaler plus 8-bit PPG mode and the 16-bit prescaler plus 16-bit PPG mode, the toggle
waveform of the 8-bit prescaler is output on the prescaler side while the waveform of the 8-bit PPG is
output on the PPG side. The following shows an example of an output waveform in this mode.
Figure 13.4-2 8+8 PPG Output Operation - Output Waveform
Ph1
PI1
PPG1
PPG0
Pl0
Ph0
Pl1 = T × (L1+1)
Ph1 = T × (L1+1)
Pl0 = T × (L1+1) × (L0+1)
Ph0 = T × (L1+1) × (H0+1)
Note: It is recommended to set
the same value to both
PRLL and PRLH of ch.1
CM71-10132-3E
L1 :
L0 :
H0 :
T :
Ph0 :
Pl0 :
Ph1 :
Pl1 :
PRLL & PRLH values of ch.1
PRLL value of ch.0
PRLH value of ch.0
Input clock period
“H” pulse width of PPG0
“L” pulse width of PPG0
“H” pulse width of PPG1
“L” pulse width of PPG1
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CHAPTER 13 PPG Timer
13.4 Operation Descriptions about PPG Timer
MB91345 Series
● Interrupts
Interrupt of this module becomes active when the reload value counts out and a borrow occurs. However,
when the INTMn bit is set to "1", the interrupt becomes active only during an underflow (borrow) from
PRLHn. That is, the interrupt occurs when "H" width pulse ends.
In the 8-bit PPG mode and the 8-bit prescaler plus 8-bit PPG mode, an interrupt request is made by a
borrow from their counters. In the 16-bit PPG mode and the 16-bit prescaler plus 16-bit PPG mode, on the
other hand, PUF(m) and PUF(m+1) are simultaneously set by a borrow from the 16-bit counter. Therefore,
in order to integrate interrupt factors, it is recommended to enable only either one of PIE(m) or PIE(m+1).
It is also recommended to clear interrupt factors for PUF(m) and PUF(m+1) both at the same time. (m = 0,
2, 4, 6)
● Initial Values of Hardware Components
Each hardware component of this block is reset to its initial state in the following manner.
<Register>
PPGC(n)
 0000000XB
<Pulse output>
<Interrupt request>
PPG(n)
IRQ(n)
 "L"
 "L"
(n = 0 to 7)
Hardware components other than the ones shown above are not initialized.
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CHAPTER 13 PPG Timer
13.4 Operation Descriptions about PPG Timer
MB91345 Series
● PPG Combinations
Table 13.4-3 PPG Combination List
ch.0: PPGC
ch.2: PPGC
MD1
MD0
MD1
MD0
0
0
0
0
0
0
ch.0
ch.1
ch.2
ch.3
0
8-bit PPG
8-bit PPG
8-bit PPG
8-bit PPG
0
1
8-bit PPG
8-bit PPG
8-bit
PPG
8-bit
prescaler
0
1
0
8-bit PPG
8-bit PPG
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
16-bit PPG
8-bit PPG
8-bit PPG
1
0
0
1
16-bit PPG
8-bit
PPG
8-bit
prescaler
1
0
1
0
16-bit PPG
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
16-bit PPG
Setting disabled
8-bit
PPG
8-bit
PPG
8-bit
PPG
8-bit
prescaler
8-bit
prescaler
8-bit
prescaler
8-bit PPG
8-bit PPG
8-bit
PPG
8-bit
prescaler
16-bit PPG
Setting disabled
16-bit PPG
Setting disabled
16-bit PPG
16-bit prescaler
ch.4, ch.5, ch.6 and ch.7 can also be combined in operation in the same manner as ch.0, ch.1, ch.2 and ch.3.
Please replace each channel as described below.
ch.0 = ch.4
ch.1 = ch.5
ch.2 = ch.6
ch.3 = ch.7
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CHAPTER 13 PPG Timer
13.4 Operation Descriptions about PPG Timer
MB91345 Series
■ Duty Change
It should be noted that when changing a duty setting while operating a PPG output, the duty does not
change until the next cycle starts.
• Overview of PPG timer operation
The 8/16-bit PPG timer alternatively reloads the values that are set to the "L"-width setup register
(PRLL) and the "H"-width setup register (PRLH) to the down counter by each underflow of the down
counter.
Figure 13.4-3 PPG Timer Operation
PPGn
PPG output latch
8-bit or 16-bit down counter
Underflow
“H”/“L” selector
PUF
Interrupt
PIE
PRLLn
PRLHn
Bus
The timer functions of the PPG timer include:
- In the PWM timer mode:
Period = "L" width setup register + "H" width setup register
- In the reload timer mode:
Setup time = "L" width setup register + "H" width setup register
• Timings for register updates in the PWM timer mode
In general, when using the PPG timer to control PWM, the period and duty of PPG output should be
able to be changed even when the timer is in operation by interrupting a period to simultaneously
change the "L" and "H" width setup registers. However, the registers of this PPG timer are configured
to immediately respond to the updated value when reloading the selected register value. Therefore, an
inconsistency occurs between the "L" and "H" width setups, in accordance with the update timing.
The update and output timings are shown below.
Figure 13.4-4 Update and Output Timings in PWM Timer Mode (1)
This is normally "H1" counter
"L1"
"H1"
"L1"
"H2"
"L2"
"H3"
"L3"
"H43"
"L4"
"H5"
PPG
L2/H2
updated
Start
Interrupt
374
L3/H3
updated
Interrupt
Interrupt
L4/H4
updated
L5/H5
updated
Interrupt
PRLH
H1
H2
H3
H4
H5
PRLL
L1
L2
L3
L4
L5
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CM71-10132-3E
CHAPTER 13 PPG Timer
13.4 Operation Descriptions about PPG Timer
MB91345 Series
• Notes on the use of the PWM timer mode
When the PPG timer is used to control PWM, an interrupt can be performed every time an underflow
occurs in the counter. Therefore, duties can be controlled by updating the values of the "L" and "H"
width setup registers for each interrupt. However, when the time set to the "L" and "H" widths is short,
the duration from an interrupt to the following interrupt also becomes short. As a result, the second
interrupt occurs while the register is still being updated in the process of the first interrupt, causing the
first interrupt to be ignored due to the timing of clearing the interrupt flag. Therefore, it is required to
set the time in such a way that interrupts are not ignored or program the software to handle the situation
when an interrupt is ignored.
The update timing and output timing are shown below.
Figure 13.4-5 Update and Output Timings in PWM Timer Mode (2)
Interrupt ignored
"L1"
"H1"
"L2"
"H2"
"H3"
"L3"
"L4" "H4" "L5"
PPG
H2
L2
updated
updated
Start
Interrupt
H4
updated
L3/H3
updated
L4
Interrupt
Interrupt
L5
Interrupt
H5/L6
updated
Interrupt
Note: When the time set to the "L" and "H" widths is short, interrupts are ignored.
Therefore, a software solution is required for updating the timings.
Proposal 1: Set the time in such a way that interrupts are not ignored.
Proposal 2: Program the software to handle the situation when an interrupt is ignored.
• Interrupt processing time
The following shows the times required to process the interrupts that are described in notes on the use
of the PWM timer mode.
Please note that as the durations shown below are the minimum requirement indicated by the number of
cycles, enough extra time should be added to each setup time.
1. Time spent until interrupt processing begins
Approx. 6 cycles
2. Processing at the entry point of an interrupt function
CM71-10132-3E
STM (R0 to R7)
; Up to 9 cycles
STM (R8 to R15)
; Up to 9 cycles
ST MDH,@-R15
; 1 cycle
ST MDL,@-R15
; 1 cycle
ST RP,@-R15
; 1 cycle
ENTER
; 2 cycles
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CHAPTER 13 PPG Timer
13.4 Operation Descriptions about PPG Timer
MB91345 Series
3. Flag Clear and Reload register settings
LDI:20 #PPGCn,R0
; 2 cycles
BANDH #B,@R0
; 3 cycles
LDI:20 #0x0XXXX,R0
; 2 cycles
LDI:20 #PRLn,R12
; 2 cycles
STH R0,@R12
; 1 cycle
This is a program used in the
interrupt processing. Cycles
must be calculated based on the
content of actual program.
Total: 65 cycles + 
(Instruction to be given at the
execution of an interrupt)
4. Processing at the exit of an interrupt function
LEAVE
; 1 cycle
LD @R15+,RP
; 1 cycle
LD @R15+,MDL
; 1 cycle
LD @R15+,MDH
; 1 cycle
LDM1(R8-R15)
; 9 cycles
LDM0(R0-R7)
; 9 cycles
RETI
; 9 cycles
This time does not include the processing time required for multiple interrupts. Therefore, when using
them, it is necessary to add the processing time of the interrupt which has a higher priority than the PPG
timer interrupt.
The following shows an example of a duty ratio in consideration of this type of time.
Conditions: period = 5000 cycles, no multiple interrupts, minimum setup time = 250 cycles
Figure 13.4-6 Example of Duty Ratio in Multiple Interrupt
PPG
4750 cycles
250
250
4750 cycles
Duty ratio = 4750:250 to 250:4750 = 5% to 95%
The longer the period is, the wider the duty ratio becomes. In other words, when the period is short, the
duty ratio becomes narrower.
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CHAPTER 13 PPG Timer
13.4 Operation Descriptions about PPG Timer
MB91345 Series
5. Processing method in consideration of the situation when an interrupt is ignored
Figure 13.4-7 Processing Flowchart in Consideration of the Situation when the Interrupt is Ignored
Main
PPG interrupt
Flag=1
Deciding flag
Flag=0
Updating "L" width setup register
Updating "H" width setup register
Clearing interrupt flag
Clearing interrupt flag
PPGx=0
PPGx=1
Deciding pin
PPGx=1
Flag inversion process
Updating "H" width setup register
Deciding pin
PPGx=0
Updating "L" width setup register
RETI
1) An interrupt occurs in the PPG timer.
2) The "L" and "H" width decision flags are checked.
3) When the flags are "0", the "L" width setup register is updated.
And when the flags are "1", the "H" width setup register is updated.
4) The interrupt flag is cleared.
5) After it is cleared, the state of PPG output pins is decided.
6) When the PPG pin state is "plus", the flag is inverted.
When the state is "minus", the setup registers are updated.
7) RETI is executed to return to "Main".
CM71-10132-3E
Program to prevent interrupts
from being ignored
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CHAPTER 13 PPG Timer
13.5 Timing Generator to PPG Timer
13.5
MB91345 Series
Timing Generator to PPG Timer
The timing generator allows multiple PPG timers to be synchronized in order to delay a
start.
■ Register List
Figure 13.5-1 Register List
Control register: TTCR0, TTCR1
Address
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Initial value
000554H
TRG6
TRG4
TRG2
TRG0
CS1
CS0
MONI
STR
11110000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
Initial value
TRG8
CS1
CS0
MONI
STR
11110000B
R/W
R/W
R/W
R/W
R/W
Address
00055CH
TRG14 TRG12 TRG10
R/W
R/W
R/W
Test register: TSTPR0, TSTPR1 (Write disabled, Read value invalid)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000557H
00055FH








00000000B
R
R
R
R
R
R
R
R
Compare register 0: COMP0
Address
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Initial value
000558H
D7
D6
D5
D4
D3
D2
D1
D0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Compare register 2: COMP2
Address
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
Initial value
000559H
D7
D6
D5
D4
D3
D2
D1
D0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Compare register 4: COMP4
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00055AH
D7
D6
D5
D4
D3
D2
D1
D0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00000000B
Compare register 6: COMP6
Address
00055BH
R/W:
R:
bit7
bit6
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Readable/writable
Read only
(Continued)
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CHAPTER 13 PPG Timer
13.5 Timing Generator to PPG Timer
MB91345 Series
(Continued)
Compare register 8: COMP8
Address
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Initial value
000560H
D7
D6
D5
D4
D3
D2
D1
D0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit21
bit20
bit19
bit18
bit17
bit16
Initial value
00000000B
Compare register 10: COMP10
Address
000561H
bit23
bit22
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Compare register 12: COMP12
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000562H
D7
D6
D5
D4
D3
D2
D1
D0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Compare register 14: COMP14
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000563H
D7
D6
D5
D4
D3
D2
D1
D0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
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CHAPTER 13 PPG Timer
13.5 Timing Generator to PPG Timer
MB91345 Series
■ Block Diagram
Figure 13.5-2 Block Diagram
Prescaler
CS1/CS0
1/2
1/8
1/32
1/64
STR
MONI
8-bit counter
Counter value
COMP0
Compare circuit
Set
Clr
PPG0TG
Set
Clr
PPG2TG
Set
Clr
PPG4TG
Set
Clr
PPG6TG
COMP2
Compare circuit
COMP4
Compare circuit
COMP6
Compare circuit
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CHAPTER 13 PPG Timer
13.5 Timing Generator to PPG Timer
MB91345 Series
■ Register for the Timing Generator
● Control register: TTCR0, TTCR1
Figure 13.5-3 Control Register: TTCR0, TTCR1
Control register: TTCR0, TTCR1
Address
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Initial value
000554H
TRG6
TRG4
TRG2
TRG0
CS1
CS0
MONI
STR
11110000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
Initial value
TRG8
CS1
CS0
MONI
STR
11110000B
R/W
R/W
R/W
R/W
R/W
Address
00055CH
TRG14 TRG12 TRG10
R/W
R/W:
R/W
R/W
Readable/writable
This register controls the timing generator.
[bit31, bit30, bit29, bit28] TRG6/TRG4/TRG2/TRG0 : PPG Trigger Clear bits
Writing "0" to these bits clears the PPG start triggers that are being output.
Each bit corresponds to the following trigger.
TRG00:TRG0TG
TRG20:TRG2TG
TRG40:TRG4TG
TRG60:TRG6TG
The read value of this register is always "1".
[bit27, bit26] CS1/CS0(Count Select bit) : Count clock selection bits
The operation clock of the 8-bit counter is selected in the following manner.
Table 13.5-1 Count Clock Selection Bits
CM71-10132-3E
CS 1
CS 0
Clock Source
0
0
Peripheral clock/2 (80ns @25MHz)
0
1
Peripheral clock/8 (320ns @25MHz)
1
0
Peripheral clock/32 (1.28µs @25MHz)
1
1
Peripheral clock/64 (2.56µs @25MHz)
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CHAPTER 13 PPG Timer
13.5 Timing Generator to PPG Timer
MB91345 Series
[bit25] MONI(MONITER bit) : Monitor bit during the operation of the 8-bit counter
The operation of the 8-bit counter is selected in the following manner.
Table 13.5-2 Monitor Bit during the Operation of the 8-bit Counter
0
When the counter is in a stopped state
1
When the counter is in operation
The write value is invalid.
[bit24] STR(START bit) : 8-bit counter operation enable bit
The operation of the 8-bit counter is selected in the following manner.
Table 13.5-3 8-bit Counter Operation Enable Bit
0
Invalid
1
Starts counter operation
Writing "0" is invalid. The read value is always "0".
● Compare register: COMP0, COMP2, COMP4, COMP6, COMP8, COMP10, COMP12, COMP14
Figure 13.5-4 Compare Register: COMP0, COMP2, COMP4, COMP6, COMP8, COMP10, COMP12, COMP14
Compare register 0: COMP0
Address
000558H
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Initial value
00000000B
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Compare register 2: COMP2
Address
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
Initial value
000559H
D7
D6
D5
D4
D3
D2
D1
D0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Compare register 4: COMP4
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00055AH
D7
D6
D5
D4
D3
D2
D1
D0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00000000B
Compare register 6: COMP6
Address
00055BH
R/W:
bit7
bit6
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Readable/writable
(Continued)
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CHAPTER 13 PPG Timer
13.5 Timing Generator to PPG Timer
MB91345 Series
(Continued)
Compare register 8: COMP8
Address
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Initial value
000560H
D7
D6
D5
D4
D3
D2
D1
D0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit21
bit20
bit19
bit18
bit17
bit16
Initial value
00000000B
Compare register 10: COMP10
Address
000561H
bit23
bit22
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Compare register 12: COMP12
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000562H
D7
D6
D5
D4
D3
D2
D1
D0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Compare register 14: COMP14
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000563H
D7
D6
D5
D4
D3
D2
D1
D0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
When the value of the 8-bit counter matches with the value of this register, a PPG start signal is set.
Please do not rewrite this register during a count operation.
When this register value is "00000000B", the PPG start signal cannot be set.
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CHAPTER 13 PPG Timer
13.5 Timing Generator to PPG Timer
MB91345 Series
■ Overview of the Timing Generator Operation
● Prescaler operation
This operation allows the count clock for the 8-bit counter to be divided by the peripheral clock.
● 8-bit counter
The 8-bit counter counts by using the STR bit for the count clock from the prescaler. The 8-bit counter
starts to count up, and when an overflow occurs, it stops counting. During counting, a counter start is
ignored.
While the 8-bit counter is counting, "1" can be read in the MONI bit. And once it stops counting, "0" can be
read.
The count value of the 8-bit counter is entered in each comparator.
Figure 13.5-5 Timing for Operating/Stopping the 8-bit Counter
8-bit counter
STR= 1
STR= 1
MONI= 1
Counting
MONI= 0
Stops Counting
MONI= 1
Counting
MONI= 0
Stops Counting
Overflow stops counter operation
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CHAPTER 13 PPG Timer
13.5 Timing Generator to PPG Timer
MB91345 Series
Figure 13.5-6 Trigger Timing
8-bit counter
STR=1
TRG00, TRG20 = 0
TRG40, TRG60 = 0
F0H
A0H
80H
40H
COMP0
40H
COMP2
80H
COMP4
A0H
COMP6
F0H
PPG0TG
PPG2TG
PPG4TG
PPG6TG
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CHAPTER 13 PPG Timer
13.5 Timing Generator to PPG Timer
386
MB91345 Series
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 14
Up/Down Counter
This chapter explains the overview, the configuration
and functions of registers, and operations of the 8/16bit up/down counter.
14.1 Overview of Up/Down Counter
14.2 Up/Down Counter Registers
14.3 Operations of Up/Down Counter
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CHAPTER 14 Up/Down Counter
14.1 Overview of Up/Down Counter
14.1
MB91345 Series
Overview of Up/Down Counter
The up/down counter/timer consists of three event input pins, a 16-bit up/down counter,
16-bit reload/compare registers, and their control circuits.
The operation mode can be switched to an 8-bit counter  2 channels or a 16-bit counter  1
channel, depending on its setting.
■ Features of Up/Down Counter
• Capable of counting in the 0 to 65535 range by the 16-bit count register
• Four types of count mode by selection of the count clock
- Timer mode
- Up/down counter mode
- Phase difference count mode (2 multiplication)
- Phase difference count mode (4 multiplication)
• Capable of selecting a count clock signal in timer mode, from among the inputs from two internal clocks
and an internal circuit
- Divided by 2
- Divided by 8
• Capable of selecting the detection edge of the external pin input signal in up/down count mode
- Detection at falling edge
- Detection at rising edge
- Detection at both rising edge and falling edge
- Edge detection disabled
• The phase difference count mode is suitable for counting encoder such as of motors. Capable of count
accurately and easily rotation angles, number of rotation, and so on, by inputting the output of phases A,
B, and Z of encoder
• Two types of function available for the ZIN pin (Enabled in all modes)
- Counter clear function
- Gate function
• Compare and reload functions available not only separately but also in combination for up/down
counting at an arbitrary width
- Compare function (comparison interrupt request output)
- Compare function (comparison interrupt request output and counter clear)
- Reload function (underflow interrupt request output and reload)
- Compare/reload function (comparison interrupt request output and counter clear, underflow interrupt
request output and reload)
- Compare/reload disabled
• Count direction flag used to identify the preceding count direction
• Capable of individually controlling interrupt generation when comparison results match, when reload
(underflow) or overflow occurs, or when the count direction changes
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CHAPTER 14 Up/Down Counter
14.1 Overview of Up/Down Counter
MB91345 Series
■ Block Diagram of Up/Down Counters
Figure 14.1-1 Block Diagram of 8/16-bit Up/Down Counter/Timer (ch.0)
Data bus
8 bits
CGE1
CGE0
CGSC
RCR0
(Reload compare register 0)
RCUT
ZIN0
M16E
Reload control
To ch.1
Carry
Edge/level detection
UCRE
RLDE
Counter
clear
UDCC
8 bits
CES1
CES0
CMS1
CMS0
UDCR0
(Up/down count register 0)
CMPF
UDFF
OVFF
AIN0
BIN0
Up/down
count clock
selection
Count
clock
CSTR
UDF1
UDIE
UDF0
CDCF
Prescaler
CITE
CLKS
UFIE
Interrupt output
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CHAPTER 14 Up/Down Counter
14.1 Overview of Up/Down Counter
MB91345 Series
Figure 14.1-2 Block Diagram of 8/16-bit Up/Down Counter/Timer (ch.1)
Data bus
8 bits
CGE1
CGE0
CGSC
RCR1
(Reload compare register 1)
RCUT
ZIN0
Reload control
Edge/level detection
UCRE
RLDE
Counter
clear
UDCC
8 bits
CES1
CES0
CMS1
CMS0
UDCR1
(Up/down count register 1)
CMPF
Carry
M16E
UDFF
OVFF
AIN0
BIN0
Up/down
count clock
selection
Count
clock
CSTR
UDF1
UDIE
UDF0
CDCF
Prescaler
CITE
CLKS
UFIE
Interrupt output
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CHAPTER 14 Up/Down Counter
14.2 Up/Down Counter Registers
MB91345 Series
14.2
Up/Down Counter Registers
The up/down counter has Up/Down Count Register (UDCR), Reload Compare Register
(RCR), Counter Status Register (CSR), and Counter Control Register (CCR).
This section describes these registers.
■ Register List of Up/Down Counter
Figure 14.2-1 Register List of Up/Down Counter
UDCRH
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
ch.1: 000186H
ch.3: 000196H
D15
D14
D13
D12
D11
D10
D09
D08
00000000B
R
R
R
R
R
R
R
R
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ch.0: 000187H
ch.2: 000197H
D07
D06
D05
D04
D03
D02
D01
D00
Initial value
UDCRL
R
R
R
R
R
R
R
R
00000000B
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000184H
D15
D14
D13
D12
D11
D10
D09
D08
00000000B
W
W
W
W
W
W
W
W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000184H
D07
D06
D05
D04
D03
D02
D01
D00
00000000B
W
W
W
W
W
W
W
W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000188H
CSTR
CITE
UDIE
CMPF
OVFF
UDFF
UDF1
UDF0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00018CH
M16E
CDCF
CFIE
CLKS
CMS1
CMS0
CES1
CES0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
UCRE
RLDE
UDCC
CGSC
CGE1
CGE0
00000000B
R/W
R/W
R/W
R/W
R
R
RCRH
RCRL
CSR
CCRH
CCRL
Address
00018CH
Reserved CTUT
R/W
R/W:
R:
W:
R/W
Readable/writable
Read only
Write only
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CHAPTER 14 Up/Down Counter
14.2 Up/Down Counter Registers
14.2.1
MB91345 Series
Up/Down Count Register (UDCR0 to UDCR3)
Up/Down Count Register (UDCR) is an 8-bit count register. It processes the up/down
counting, based on input from the internal circuit, internal prescaler, or input of AIN/BIN
pins. In 16-bit count mode, UDCR operates as a 16-bit count register.
■ Up/Down Count Register (UDCR0 to UDCR3)
Figure 14.2-2 Up/Down Count Register (UDCR0 to UDCR3)
UDCRH
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
ch.1: 000186H
ch.3: 000196H
D15
D14
D13
D12
D11
D10
D09
D08
00000000B
R
R
R
R
R
R
R
R
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ch.0: 000187H
ch.2: 000197H
D07
D06
D05
D04
D03
D02
D01
D00
Initial value
R
00000000B
UDCRL
R
R
R
R
R
R
R
R: Read only
It is not allowed to write directly to UDCR. The write operation to this register must be performed through
RCR. First, write the desired value to RCR, and then write "1" into the CTUT bit in the CCRL register. The
value is transferred from RCR to this register (software reload).
In 16-bit mode, 16 bits should be read from this register at a time.
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CHAPTER 14 Up/Down Counter
14.2 Up/Down Counter Registers
MB91345 Series
14.2.2
Reload Compare Register (RCR)
Reload Compare Register (RCR) is an 8-bit reload/compare register. This register is
used to set a reload value and compare value. The reload value and compare value are
the same. Activating the reload function and compare function enables up/down
counting between "00H" and this register value (0000H and this register value for 16-bit
operation mode).
■ Reload Compare Register (RCR)
Figure 14.2-3 Reload Compare Register (RCR)
RCRH
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000184H
D15
D14
D13
D12
D11
D10
D09
D08
00000000B
W
W
W
W
W
W
W
W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000184H
D07
D06
D05
D04
D03
D02
D01
D00
00000000B
W
W
W
W
W
W
W
W
RCRL
W: Write only
This register is write-only and cannot be read. This register value can be transferred to UDCR by writing
"1" into the CTUT bit in the CCR register while counting is stopped.
(Software reload)
In 16-bit mode (M16E=1), 16 bits should be written to this register at a time.
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CHAPTER 14 Up/Down Counter
14.2 Up/Down Counter Registers
14.2.3
MB91345 Series
Counter Status Register (CSR)
Counter Status Register (CSR) can be used to check the status of up/down counter and
control interrupts.
■ Bit Configuration of Counter Status Register (CSR)
Figure 14.2-4 Bit Configuration of Counter Status Register (CSR)
CSR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000188H
CSTR
CITE
UDIE
CMPF
OVFF
UDFF
UDF1
UDF0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W:
R:
Readable/writable
Read only
[bit7] CSTR: Count start bit
This bit controls starting/stopping of the UDCR count operation.
CSTR
Count operation
0
Count operation stopped [Initial value]
1
Count operation started
[bit6] CITE: Compare interrupt enable bit
This bit controls enabling/disabling of interrupt output to CPU when CMPF is set (a compare operation
is performed).
CITE
Compare interrupt control
0
Compare interrupt disabled [Initial value]
1
Compare interrupt enabled
[bit5] UDIE: Overflow/underflow interrupt enable bit
This bit controls enabling/disabling of interrupt output to CPU when OVFF and UDFF are set (an
overflow/underflow occurs).
UDIE
394
Overflow/underflow interrupt control
0
Overflow/underflow interrupt disabled [Initial value]
1
Overflow/underflow interrupt enabled
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CHAPTER 14 Up/Down Counter
14.2 Up/Down Counter Registers
MB91345 Series
[bit4] CMPF: Compare detection flag
This flag indicates that the result of comparing the UDCR value and the RCR value is a match.
Only "0" can be written to this bit, but "1" cannot.
CMPF
Content of compare detection flag
0
The result of comparison is not a match [Initial value]
1
The result of comparison is a match
[bit3] OVFF: Overflow detection flag
This flag indicates that an overflow occurred.
Only "0" can be written to this bit, but "1" cannot.
OVFF
Content of overflow detection flag
0
No overflow occurred [Initial value]
1
An overflow occurred
[bit2] UDFF: Underflow detection flag
This flag indicates that an underflow occurred.
Only "0" can be written to this bit, but "1" cannot.
UDFF
Content of underflow detection flag
0
No underflow occurred [Initial value]
1
An underflow occurred
[bit1, bit0] UDF1, UDF0: Up/down flags
These bits indicate the preceding count operation (up/down).
These bits are read-only and cannot be written to.
CM71-10132-3E
UDF1
UDF0
Detection edge
0
0
No input [Initial value]
0
1
Down counting
1
0
Up counting
1
1
Simultaneous up and down counting
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CHAPTER 14 Up/Down Counter
14.2 Up/Down Counter Registers
14.2.4
MB91345 Series
Counter Control Register (CCR)
Counter Control Register (CCR) is used to control the operation mode of up/down
counter. Function of bit15 (M16E) varies depending on whether the channel is odd or
even numbered.
■ Bit Configuration of Counter Control Register (CCR)
Figure 14.2-5 Bit Configuration of Counter Control Register (CCR)
CCRH
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00018CH
M16E
CDCF
CFIE
CLKS
CMS1
CMS0
CES1
CES0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
UCRE
RLDE
UDCC
CGSC
CGE1
CGE0
00000000B
R/W
R/W
R/W
R/W
R
R
CCRL
Address
00018CH
Reserved CTUT
R/W
R/W:
R:
R/W
Readable/writable
Read only
[bit15] M16E: 16-bit mode enable setting bit
This bit switches between 8-bit  2-channel and 16-bit  1 channel operation mode.
M16E
16-bit mode enable setting
0
8-bit  2-channel operation mode [Initial value]
1
16-bit  1 channel operation mode
Note:
The M16E bit resides only in even-numbered channels. Be sure to set "0" in odd-numbered
channels.
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CHAPTER 14 Up/Down Counter
14.2 Up/Down Counter Registers
MB91345 Series
[bit14] CDCF: Count direction change flag
This flag is set when the count direction changes. This bit is set to "1" if the count direction changes
from up to down or from down to up while counting is in progress.
This bit is cleared by writing "0".
Writing "1" is ignored, and the value of this bit does not change.
CDCF
Direction change detection
0
Direction not changed [Initial value]
1
Direction changed at least once
The count direction immediately after a reset is down. Thus, CDCF is set to "1" to count up
immediately after a reset.
[bit13] CFIE: Count direction change interrupt enable bit
This bit controls interrupt output to CPU if CDCF is set. An interrupt is caused even if the count
direction is changed only once while counting is in progress.
CFIE
Direction change interrupt control
0
Direction change interrupt disabled [Initial value]
1
Direction change interrupt enabled
[bit12] CLKS: Built-in prescaler selection bit
This bit selects the frequency of the built-in prescaler when timer mode is selected.
CLKS is valid only in timer mode, where only down counting is available.
CLKS
Selected internal clock
0
2 machine cycles [Initial value]
1
8 machine cycles
[bit11, bit10] CMS1, CMS0: Count mode selection bits
These bits are used to select the count mode.
CM71-10132-3E
CMS1
CMS0
Count mode
0
0
Timer mode (down-counting) [Initial value]
0
1
Up/down count mode
1
0
Phase difference count mode (multiply by 2)
1
1
Phase difference count mode (multiply by 8)
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14.2 Up/Down Counter Registers
MB91345 Series
[bit9, bit8] CES1, CES0: Count clock edge selection bits
These bits are used to select the detection edge of the internal circuit input and the external pins AIN
and BIN in up/down count mode.
These settings are valid only in up/down count mode.
CES1
CES0
Selected edge
0
0
Edge detection disabled [Initial value]
0
1
Detection at falling edge
1
0
Detection at rising edge
1
1
Detection at both rising edge and falling edge
[bit7] Reserved bit
This bit is reserved. Be sure to set "0".
[bit6] CTUT: Counter write bit
This bit is used to transfer data from RCR to UDCR.
Writing "1" to this bit transfers data from RCR to UDCR.
Writing "0" has no effect. The read value is always "0".
Do not write "1" to this bit while counting is in progress (while the CSTR bit in CSR is "1").
[bit5] UCRE: UDCR clear enable bit
This bit controls clearing of UDCR based on compare operation.
The UDCR clear function that is not related to clearing based on the compare operation (such as
clearing based on the ZIN pin) is not affected.
UCRE
Counter clearing based on compare operation
0
Counter clearing disabled [Initial value]
1
Counter clearing enabled
[bit4] RLDE: Reload enable bit
This bit controls starting of the reload function. If an underflow occurs in UDCR when the reload
function is started, the RCR value is transferred to UDCR.
RLDE
398
Reload function
0
Reload function disabled [Initial value]
1
Reload function enabled
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14.2 Up/Down Counter Registers
MB91345 Series
[bit3] UDCC: UDCR clear bit
This bit is used to clear UDCR. Writing "0" to this bit clears UDCR to "0000H".
Writing "1" has no effect. The read value is always "1".
[bit2] CGSC: Count clear/gate selection bit
This bit is used to select the function of the external pin ZIN.
CGSC
ZIN pin function
0
Counter clear function [Initial value]
1
Gate function
[bit1, bit0] CGE1, CGE0: Count clear/gate edge selection bits
These bits are used to select the detection edge/level of the external pin ZIN.
CM71-10132-3E
When counter clear
function selected
CGE1
CGE0
0
0
Edge detection disabled
[Initial value]
Level detection disabled [Initial value]
(counting disabled)
0
1
Falling edge
"L" level
1
0
Rising edge
"H" level
1
1
Settings disabled
Settings disabled
When gate function selected
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CHAPTER 14 Up/Down Counter
14.3 Operations of Up/Down Counter
14.3
MB91345 Series
Operations of Up/Down Counter
This section describes the operations of up/down counter.
■ Selecting the Count Mode
This timer/counter has four types of count modes. Selection of the count mode is controlled by the CMS1
and CMS0 bits in the CCR register.
Table 14.3-1 Selecting the Count Mode
CMS1
CMS0
Count mode
0
0
Timer mode (down-counting) [Initial value]
0
1
Up/down count mode
1
0
Phase difference count mode (multiply by 2)
1
1
Phase difference count mode (multiply by 8)
● Timer mode [down-counting]
In timer mode, output of the internal prescaler is counted down. For the internal prescaler, either 2 machine
cycles or 8 machine cycles can be selected using the CLKS bit in the CCRH register.
● Up/down count mode
In up/down count mode, counting up and down is done by counting the inputs of the AIN and BIN external
pins. Input from the AIN pin controls counting up and input from the BIN pin controls counting down.
Input of the AIN and BIN pins is detected by edges. The detection edge can be selected with the CES1 and
CES0 bits in the CCRH register.
Table 14.3-2 Selecting Edge for Detection
400
CES1
CES0
Selected edge
0
0
Edge detection disabled [Initial value]
0
1
Detection at falling edge
1
0
Detection at rising edge
1
1
Detection at both rising edge and falling edge
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CHAPTER 14 Up/Down Counter
14.3 Operations of Up/Down Counter
MB91345 Series
● Phase difference count mode (2 multiplication/4 multiplication)
In phase difference count mode, in order to count the phase difference between phase A and phase B of the
encoder output signal, the input level of the BIN pin is detected when the input edge of the AIN pin is
detected, and counting is performed.
In 2 multiplication/4 multiplication mode, if the AIN pin is earlier based on the phase difference between
AIN pin input and BIN pin input, counting up is performed. If the BIN pin is earlier, counting down is
performed.
In 2 multiplication mode, the following counting is performed according to detection of the AIN pin value
when the timing for the BIN pin is both rising and falling edges:
Table 14.3-3 Counting Operation for Phase Difference Count Mode (2/4 Multiplication)
BIN pin edge
AIN pin level
Counting
Rising edge 
"H" level
Up counting
Rising edge 
"L" level
Down counting
Falling edge 
"H" level
Down counting
Falling edge 
"L" level
Up counting
Figure 14.3-1 Summary of Operation in Phase Difference Count Mode (2 Multiplication)
AIN pin
BIN pin
+1
1
Count value 0
+1
2
+1
3
+1
4
+1
5
-1
4
+1
5
-1
4
-1
3
-1
2
-1
1
-1
0
In 4 multiplication mode, the following counting is performed according to detection of the AIN pin value
when the timing for the BIN pin is both rising and falling edges, or detection of the BIN pin value when the
timing for the AIN pin is both rising and falling edges:
Table 14.3-4 Counting Operation for 4 Multiplication
Edge input
Edge
Level input
Rising edge 
BIN
Level
Counting
"H" level
Up counting
"L" level
Down counting
"H" level
Down counting
"L" level
Up counting
"H" level
Down counting
"L" level
Up counting
"H" level
Up counting
"L" level
Down counting
AIN
Falling edge
Rising edge 
AIN
BIN
Falling edge
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14.3 Operations of Up/Down Counter
MB91345 Series
Figure 14.3-2 Summary of Operation in Phase Difference Count Mode (4 Multiplication)
AIN pin
BIN pin
Count value 0
+1+1 +1+1 +1+1 +1+1 +1+1
1 2 3 4 5 6 7 8 9 10
-1
9
+1
10
-1
9
-1-1
8 7
-1-1
6 5
-1-1
4 3
-1-1
2 1
It is possible to count the rotation angle and the number of revolutions with high accuracy and to detect the
rotation direction by inputting phase A to the AIN pin, phase B to the BIN pin, and phase Z to the ZIN pin
when encoder output is counted.
Note that detection edge selection using the CES1 and CES0 bits is invalid if this count mode is selected.
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CHAPTER 14 Up/Down Counter
14.3 Operations of Up/Down Counter
MB91345 Series
■ Reload/Compare Function
This counter has a reload function and a clear function that is based on the compare operation. These two
functions can be combined to execute processing. The following is an example of settings:
Table 14.3-5 Example of Setting Reload/Compare Function
RLDE
UCRE
Reload/compare function
0
0
Clearing by Reload/compare disabled [Initial value]
0
1
Clearing by compare enabled
1
0
Reload enabled
1
1
Clearing by reload/compare enabled
● Reload function
When the reload function is started, the RCR value is transferred to UDCR at the timing of the next countdown clock after an underflow occurs. Then, the UDFF bit is set and an interrupt request is generated.
In a mode where counting down is not performed, starting this function has no effect.
Figure 14.3-3 Summary of Operation for Reload Function
(0FFFFH)
FFH
RCR
Reload interrupt
occurs
Reload interrupt
occurs
Underflow
Underflow
00H
● Clear function on compare
The clear function based on compare can be used in any mode other than timer mode. If the RCR value and
the UDCR value match when the compare function is started, the CMPF bit is set and an interrupt request
is generated. When the compare clear function is started, UDCR is cleared at the timing of the next countup clock. (The register is not cleared while counting down is in progress.)
In a mode where counting up is not performed, starting this function has no effect.
Figure 14.3-4 Summary of Operation for Compare Function
(0FFFFH)
FFH
RCR
Compare match
Compare match
Counter cleared,
interrupt occurs
Counter cleared,
interrupt occurs
00H
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CHAPTER 14 Up/Down Counter
14.3 Operations of Up/Down Counter
MB91345 Series
■ Starting the Reload/Compare Functions Together
If the reload and compare functions are started together, counting up and down can be performed at any
width.
The reload function transfers the RCR value to UDCR after it is started when an underflow occurs. The
compare function clears UDCR when the RCR value and the UDCR value match. The combination of these
two functions allows counting both up and down between "0000H" and the RCR value to be performed.
Figure 14.3-5 Summary of Operation when the Reload/Compare Functions are Started Together
FFH
RCR
Compare
match
Compare
match
Counter
clear
Counter
clear
Reload
Reload
Reload
Underflow
Underflow
Underflow
Compare
match
00H
Counter
clear
An interrupt to CPU can take place when a compare match or reloading (underflow) occurs. Whether such
interrupts are enabled can be controlled individually.
The timing for clearing UDCR depends on whether counting has started or has been stopped.
Reloading (writing "1" to the CTUT bit) by software is not allowed while counting is in progress.
• If a clear event occurs while counting is in progress, the whole process is done in synchronization with
the count clock.
UDCR
Clear event
0065H
0066H
0000H
0001H
In sync with this clock
Count clock
Reference:
If reloading occurs due to an underflow while counting is in progress, the whole process is done in
synchronization with the count clock.
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CHAPTER 14 Up/Down Counter
14.3 Operations of Up/Down Counter
MB91345 Series
• If a clear event occurs while counting is in progress, and then the counting is stopped waiting for the
count clock synchronization (waiting for a count input for synchronization), clearing is performed when
the counting is stopped.
UDCR
0065H
0066H
0000H
Clear event
Count clock
Counting enabled
Disable (counting disabled)
Enable (counting enabled)
• If a reload or clear event occurs while counting is in progress, the whole process is done when the event
occurs.
UDCR
0065H
0080H
Reload or
clear event
Clearing based on a compare operation is done if the UDCR value and the RCR value match and if
counting up is being performed. Even if the UDCR value and the RCR value match, clearing is not
performed if counting down occurs or the counting is stopped subsequently.
Clearing is performed according to the above timing for all events except reset input. Reloading is
performed according to the above timing for all events.
If a clear event and a reload event occur simultaneously, the clear event takes precedence.
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CHAPTER 14 Up/Down Counter
14.3 Operations of Up/Down Counter
MB91345 Series
■ Writing Data to UDCR
It is not allowed to write data directly from the data bus to UDCR. To write data to UDCR, use the
following procedure:
a. First, write the data to be written to UDCR to RCR. (Note that data already in RCR will be lost.)
b. Write "1" to the CTUT bit in CCR to transfer the data from RCR to UDCR.
The above procedure should be performed while counting is stopped (while the CSTR bit in CSR is "0").
Reference:
If "1" is erroneously written to the CTUT bit while counting is in progress, the value in RCR is
transferred to UDCR at the timing of the write.
In addition to the method described above, the following methods are also available to clear the counter:
• Reset input
• Edge input from the ZIN pin
• Writing "0" to the UDCC bit in CCR
• Compare function
The above methods can be used regardless of whether the counting has started or has been stopped.
■ Count Clear/Gate Function
ZIN pin can use to select the count clear function or gate function by the CGSC bit of the CCR register.
When the count clear function is started, the counter is cleared by the ZIN pin. The CGE1 and CGE0 bits in
the CCRL register can be used to control which of the edge input of the ZIN pin to perform the count.
When the gate function is started, the count is enabled or disabled by the ZIN pin. The CGE1 and CGE0
bits in the CCR register can be used to control which of the level input of the ZIN pin to enable the count.
These functions can be used in all count modes.
Table 14.3-6 Selecting Function of ZIN Pin
CGSC
ZIN pin function
0
Counter clear function [Initial value]
1
Gate function
Table 14.3-7 Setting Operation of Counter Clear/Gate Function
406
When counter clear
function selected
CGE1
CGE0
0
0
Edge detection disabled
[Initial value]
Level detection disabled [Initial value]
(counting disabled)
0
1
Falling edge
"L" level
1
0
Rising edge
"H" level
1
1
Settings disabled
Settings disabled
When gate function selected
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CHAPTER 14 Up/Down Counter
14.3 Operations of Up/Down Counter
MB91345 Series
■ Count Direction Flag
The count direction flags (UDF1 and UDF0) indicate whether the immediately preceding counting was up
or down when up/down counting is being performed. The flags are rewritten after each count operation,
based on the count clock generated from the input of both the AIN and BIN pins. For purposes such as
controlling a motor, you can determine the current direction of rotation by checking this flag.
Table 14.3-8 Function of Count Direction Flag
UDF1
UDF0
Count direction
0
0
No input [Initial value]
0
1
Down counting
1
0
Up counting
1
1
Simultaneous up and down counting (no counting)
■ Count Direction Change Flag
The count direction change flag (CDCF) is set if the count direction changes (up to down or down to up).
An interrupt request to CPU can occur when this flag is set. You can determine in which way the counting
direction changed, by referring the interrupt and the count direction flag. However, note that if the direction
rapidly changes more than once in a row, the flag may be reversed quickly, thus sometimes seeming that
the direction remains the same even if it actually changed.
Table 14.3-9 Function of Count Direction Change Flag
CDCF
Direction change detection
0
Direction not changed [Initial value]
1
Direction changed at least once
■ Compare Detection Flag
The compare detection flag (CMPF) is set if the UDCR value and the RCR value match while counting is
in progress. The flag is also set if a match occurs due to a reload event or a match has already existed when
counting is started, in addition to the case in which a match occurs during counting up/down.
■ 8-bit  2-channel / 16-bit  1 channel Operation
This module can be used for two 8-bit up/down counter channels or one 16-bit up/down counter channel.
Writing "0" to the M16E bit in the CCR register sets 8-bit  2-channel mode. Writing "1" sets 16-bit  1
channel mode.
In 16-bit  1 channel operation mode, the CSR0, CCRL0, and CCRH0 registers are enabled and the CSR1,
CCRL1, and CCRH1 registers cannot be used. The AIN0, BIN0, and ZIN0 pins are enabled as the input
pins, and the AIN1, BIN1, and ZIN1 pins cannot be used.
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CHAPTER 14 Up/Down Counter
14.3 Operations of Up/Down Counter
MB91345 Series
■ Interrupt Generation Timing
Table 14.3-10 List of Interrupt Generation Timing
Interrupt flag
Flag setting interrupt
Reload
Clear
CDCF
(Count direction
change flag)
An interrupt occurs as the
flag is set when the direction
of counting changes


CMPF
(Compare detection
flag)
An interrupt occurs as the
flag is set, if RCR and
UDCR match when counting
up, counting down, or reload
counting is started

UDCR is cleared when
the next counting up is
started after RCR and
UDCR match
(not cleared during
counting down)
OVFF
(Overflow detection
flag)
An interrupt occurs as the
flag is set when the next
counting up is started after
count "FFFFH"

UDCR is cleared when
the next counting is
started after count
"FFFFH"
UDFF
(Underflow detection
flag)
An interrupt occurs as the
flag is set when the next
counting down is started
after count "0000H"
The RCR value is
transferred to UDCR
when the next counting
is started after count
"0000H"

• When an interrupt occurs, counting is stopped until the interrupt flag is cleared.
• Since the RCR is used as both the reload value and compare value, the compare flag is always set when
reloading is performed.
• When counting down with the clear function enabled is being performed if a compare match occurs and
counting up is performed, clear processing is executed.
■ Note
The count direction immediately after a count reset is down. Thus, the CDCR bit is set to "1", indicating
that a change of direction occurred during counting up immediately after a reset.
If the up/down count register (UDCR) counts to its FULL count, counting continues without a carry. This
makes it appear that the up/down count register is cleared to continue counting.
The minimum pulse width of AIN, BIN, and ZIN is 2  T (where "T" indicates peripheral clock machine
cycle).
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CHAPTER 15
Serial Interface
This chapter describes the overview, the configuration
and functions of registers, and operations of serial
interface.
15.1 Overview of Serial Interface
15.2 Function of UART (Asynchronous Serial Interface)
15.3 Registers of UART (Asynchronous Serial Interface)
15.4 UART Interrupt
15.5 Operation of UART
15.6 Dedicated Baud Rate Generator
15.7 Setting Procedure and Program Flow of Operation Mode 0
(In Asynchronous Normal Mode)
15.8 Setting Procedure and Program Flow of Operation Mode 1
(In Asynchronous Multiprocessor Mode)
15.9 Notes on UART Mode
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CHAPTER 15 Serial Interface
15.1 Overview of Serial Interface
15.1
MB91345 Series
Overview of Serial Interface
The serial interface has the following characteristics.
■ Interface Mode
This serial interface selects one of the following interface modes, depending on its operation mode.
• UART0 (ordinary asynchronous serial interface)
• UART1 (asynchronous multiprocessor serial interface)
• CSIO (clock synchronous serial interface) (SPI-enabled)
• I2C (I2C bus interface)
■ Switch of Interface Mode
If you communicate through each serial interface, set the operation mode in the registers shown in Table
15.1-1 before starting the communication.
Figure 15.1-1 Bit Configuration of Serial Mode Register (SMR)
SMR0 to SMRA
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ch.0
ch.1
ch.2
ch.3
ch.4
ch.5
ch.6
ch.7
ch.8
ch.9
ch.A
MD2
MD1
MD0

SBL
BDS
SCKE
SOE
00000000B
R/W
R/W
R/W

R/W
R/W
R/W
R/W
000061H
000071H
000081H
000091H
0000A1H
0000B1H
0001B1H
0001C1H
0001D1H
0001E1H
0001F1H
R/W: Readable/writable
Table 15.1-1 Switch of Interface Mode
MD2
MD1
MD0
Interface mode
0
0
0
UART0 (ordinary asynchronous serial interface)
0
0
1
UART1 (asynchronous multiprocessor serial interface)
0
1
0
CSIO (clock synchronous serial interface) (SPI-enabled)
1
0
0
I2C (I2C bus interface)
Note: Setting other than the above is disabled.
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CHAPTER 15 Serial Interface
15.1 Overview of Serial Interface
MB91345 Series
Notes:
• If a mode is switched to another using a single serial interface during the transmit or reception
operation, the safety of the operation is not guaranteed.
• Set the operation mode first, because the other registers are initialized when the operation mode
is changed. However, if you write SCR and SMR simultaneously using 16-bit writing, the writing is
applied to SCR.
■ Transmit / Reception FIFO (ch.0 and ch.1)
ch.0 and ch.1 include the 16-byte FIFO for transmit and 16-byte FIFO for reception. In the explanations
that follow, change the number of FIFO stages to 16-byte. Other channels but 1 and 0 have no FIFO, so
ignore the information about FIFO.
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CHAPTER 15 Serial Interface
15.2 Function of UART (Asynchronous Serial Interface)
15.2
MB91345 Series
Function of UART (Asynchronous Serial Interface)
This section describes a UART function of the multi function serial interfaces, which is
supported on operation mode 0 and 1.
■ Function of UART (Asynchronous Serial Interface)
UART (asynchronous serial interface) is a generic serial communication interface to perform asynchronous
communication with external device. It supports the duplex communication function (for the normal mode)
and master/slave communication function (for the multiprocessor mode: both master and slave supported).
Table 15.2-1 Function of UART (Asynchronous Serial Interface)
Item
Function
1
Data
• Full-duplex double buffer (at not using FIFO)
• Transmit / reception FIFO (maximum size is 16 bytes per FIFO) (at using FIFO)
2
Serial input
Performs over-sampling three times, and determines the value to be received by majority
of the sampling values.
3
Transfer format
Asynchronous
4
Baud rate
• The dedicated baud rate generator (15-bit reload counter configuration)
• The reload counter can adjust external clock input.
5
Data length
5-bit to 9-bit (in the normal mode), 7-bit, 8-bit (in the multiprocessor mode)
6
Signal type
NRZ (Non Return to Zero), Inversion NRZ
7
Start bit detection
• Synchronized on the start bit falling edge (for the NRZ method)
• Synchronized on the start bit rising edge (for the inverse NRZ method)
8
Detection of receive
error
• Framing error
• Overrun error
• Parity error *
9
Interrupt request
•
•
•
•
10
Master/slave type
communication
function (multi
processor mode)
11
FIFO option
Reception interrupt (reception completed, framing error, overrun error, parity error *)
Transmit interrupt (transmit data empty, transmit bus idle)
Transmit FIFO interrupt (When transmit FIFO is empty)
The DMA function are available for both transmit and reception
1 (master) to n (slave) communication is available (both the master and the slave system
are supported)
• Built-in transmit / reception FIFO (Maximum capacity: transmit FIFO 16 bytes,
reception FIFO 16 bytes) *
• Transmit FIFO or reception FIFO can be selected.
• Transmission data can be transmitted again.
• Interrupt timing for reception FIFO can be changed by software.
• Support FIFO reset independently.
*: Parity error is only used in normal mode.
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CHAPTER 15 Serial Interface
15.3 Registers of UART (Asynchronous Serial Interface)
MB91345 Series
15.3
Registers of UART (Asynchronous Serial Interface)
This section lists the UART (asynchronous serial interface) registers.
■ List of UART (Asynchronous Serial Interface) Registers
Figure 15.3-1 List of UART (Asynchronous Serial Interface) Registers
Address
bit15
bit8 bit7
UART 0000X0H 0000X1H
SCR (Serial control register)
0000X2H 0000X3H
SSR (Serial status register)
0000X4H 0000X5H
FIFO
0000X6H 0000X7H
0000X8H 0000X9H
0000YAH 0000YBH
0000YCH 0000YDH
bit0
RDR1/TDR1
(Transmit / receive data register 1)
BGR1 (Baud rate generator register 1)
SMR (Serial mode register)
ESCR (Extended communication
control register)
RDR0/TDR0
(Transmit / receive data register 0)
BGR0 (Baud rate generator register 0)


FCR1 (FIFO control register 1)
FCR0 (FIFO control register 0)
FBYTE02 (FIFO2 byte register)
FBYTE01 (FIFO1 byte register)
(X=06,07,08,09,0A,0B,1B,1C,1D,1E,1F, Y=6,7)
Table 15.3-1 Bit Allocation of UART (Asynchronous Serial Interface)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SCR0 to SCRA/
SMR0 to SMRA
UPCL
-
-
RIE
TIE
TBIE
RXE
TXE
MD2
MD1
MD0
-
SBL
BDS
SCKE
SOE
SSR0 to SSRA/
ESCR0 to ESCRA
REC
-
PE
FRE
ORE
RDRF
TDRE
TBI
-
-
INV
PEN
P
L2
L1
L0
D8(AD)
D7
D6
D5
D4
D3
D2
D1
D0
B8
B7
B6
B5
B4
B3
B2
B1
B0
TDR0 to TDRA
(RDR0 to RDRA)
BGR01/BGR00
-
EXT
B14
B13
B12
-
B11
B10
B9
-
FCR01/FCR00
FBYTE02/
FBYTE01
Reserved Reserved
FD15
FD14
-
-
FLSTE
FRIIE
FDRQ
FTIE
FSEL
-
FLST
FLD
FSET
FCL2
FCL1
FE2
FE1
FD13
FD12
FD11
FD10
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
■ Operation Mode
UART (asynchronous serial interface) operates in two different modes. Determined based on MD2, MD1,
MD0 in Serial Mode Register (SMR).
Table 15.3-2 Operation Mode of UART (Asynchronous Serial Interface)
operation mode
MD2
MD1
MD0
0
0
0
0
UART0 (Asynchronous normal mode)
1
0
0
1
UART1 (Asynchronous multiprocessor mode)
CM71-10132-3E
Type
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CHAPTER 15 Serial Interface
15.3 Registers of UART (Asynchronous Serial Interface)
15.3.1
MB91345 Series
Serial Control Register (SCR0 to SCRA)
Serial control register (SCR0 to SCRA) enables or disables the transmit or reception
operation, the transmit or reception interrupt, and the transmit bus idle interrupt. It also
performs the UART resetting.
■ Serial Control Register (SCR0 to SCRA)
Figure 15.3-2 shows the bit configuration of the serial control register (SCR0 to SCRA). Table 15.3-3 lists
the function of each bit.
Figure 15.3-2 Bit Configuration of Serial Control Register (SCR0 to SCRA)
bit15 bit14 bit13 bit12 bit11 bit10 bit9
SCR
Address
UPCL


RIE
TIE
TBIE
RXE
ch.0 000060H R/W


R/W R/W R/W R/W
ch.1 000070H
ch.2 000080H
ch.3 000090H
ch.4 0000A0H
ch.5 0000B0H
ch.6 0001B0H
ch.7 0001C0H
ch.8 0001D0H
ch.9 0001E0H
ch.A 0001F0H
bit8
bit7
Initial value
bit0
TXE
0--00000B
(SMR)
R/W
TXE
0
1
Transmission operation enable bit
Disable transmission.
Enable transmission.
RXE
0
1
Reception operation enable bit
Disable reception.
Enable reception.
TBIE
0
1
Transmission bus idle interrupt enable bit
Disable transmission bus idle interrupt
Enable transmission bus idle interrupt
TIE
0
1
Transmission interrupt enable bit
Disable transmission interrupts.
Transmission Interrupt enable
RIE
0
1
Receive interrupt enable bit
Disable reception interrupt
Enable reception interrupt
Unused bit
Read value is undefined. Writing has no effect.
UPCL
0
1
R/W

414
Programmable clear bit
Write
Read
No effect
Always read "0".
Programmable clear
: Readable/writable
: Unused bit
: Initial value
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
MB91345 Series
CHAPTER 15 Serial Interface
15.3 Registers of UART (Asynchronous Serial Interface)
Table 15.3-3 Functional Description of Each Bit in Serial Control Register (SCR)
Bit name
Function
bit15
UPCL:
Programmable clear bit
This bit initializes internal status of the UART.
If set to "1":
UART will directly be reset (software reset).
However, register setting is maintained. In this case, the transmit or reception
operation will be disconnected immediately.
• The baud rate generator reloads the setting value in the BGR1/BGR0 register,
and restarts it.
• All transmission/reception interrupt sources (PE, FRE, ORE, RDRF, TDRE,
and TBI) are initialized (000011B).
If set to "0": No effect.
"0" is always read at read operation.
Notes:
• Execute the programmable clear after disabling interrupt.
• When using FIFO, execute the programmable clear after disabling FIFO
(FE2, FE1=0).
bit14,
bit13
Unused bits
Read: The value is undefined.
Write: No effect.
bit12
RIE:
Receive interrupt enable bit
• This bit enables / disables the receive interrupt request output to CPU.
• If the RIE bit and reception data flag bit (RDRF) are "1", or if one of the error
flag bits (PE, ORE and FREs) is "1", the reception interrupt request will be
output.
bit11
TIE:
Transmission interrupt
enable bit
• This bit enables / disables the Transmission interrupt request output to CPU.
• When the TDRE and TIE bits are both "1", a transmission interrupt request is
output.
bit10
TBIE:
Transmission bus idle
interrupt enable bit
• This bit enables / disables the transmission bus idle interrupt request output to
CPU.
• When TBIE bit and TBI bit are "1", a transmission bus idle interrupt request is
output.
RXE:
Reception enable bit
This bit enables / disables the reception operation of the UART.
When the bit is set to "0": Reception is disabled.
When the bit is set to "1": Reception is enabled.
Notes:
• The reception operation will not be started until the falling edge of the start
bit is inputted (for NRZ format (INV=0)) even when the reception operation
is enabled (RXE=1).
(For the inverse NRZ format, or INV=1, the reception operation will not be
started before the rising edge is entered)
• When the reception operation is disabled (RXE=0) during the reception, the
operation will be stopped immediately.
TXE:
Transmission enable bit
This bit enables / disables the transmission operation of the UART.
When the bit is set to "0": Transmission is disabled.
When the bit is set to "1": Transmission is enabled.
Notes:
When the transmission operation is disabled (TXE=0) during the transmission,
the operation will be stopped immediately.
bit9
bit8
CM71-10132-3E
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CHAPTER 15 Serial Interface
15.3 Registers of UART (Asynchronous Serial Interface)
15.3.2
MB91345 Series
Serial Mode Register (SMR0 to SMRA)
Serial Mode Register (SMR0 to SMRA) sets the operation mode, and selects the transfer
direction, data length, and stop bit length. It also enables or disables the output to the
serial data and the clock pin.
■ Serial Mode Register (SMR0 to SMRA)
Figure 15.3-3 shows the bit configuration of the serial mode register (SMR0 to SMRA). Table 15.3-4 lists
the function of each bit.
Figure 15.3-3 Bit Configuration of Serial Mode Register (SMR0 to SMRA)
bit15
SMR
Address:
ch.0 000061H
ch.1 000071H
ch.2 000081H
ch.3 000091H
ch.4 0000A1H
ch.5 0000B1H
ch.6 0001B1H
ch.7 0001C1H
ch.8 0001D1H
ch.9 0001E1H
ch.A 0001F1H
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00000000B
MD2
MD1
MD0

SBL
BDS
SCKE
SOE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(SCR)
SOE
0
1
Serial-data output enable bit
SO output disable
SO output enable
SCKE
1
Serial clock output enable bit
SCK output disable
or
SCK input enable
SCK output enable
BDS
0
1
Transfer direction selection bit
LSB first (transfer from LSB)
MSB first (transfer from MSB)
SBL
0
1
Stop-bit length select bit
1-bit
2-bit
0
Unused bit
Read value is undefined. Writing has no effect.
R/W

416
: Readable/writable
: Unused bit
: Initial value
MD2
MD1
MD0
0
0
0
0
0
1
0
1
1
0
0
0
Operation mode setting bits
Operation mode 0
(asynchronous normal mode)
operation mode 1
(asynchronous multiprocessor mode)
operation mode 2 (clock synchronous mode)
operation mode 4 (I2C mode)
Note: The registers and operations of the operation modes 0 and 1 are
explained.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
MB91345 Series
CHAPTER 15 Serial Interface
15.3 Registers of UART (Asynchronous Serial Interface)
Table 15.3-4 Functional Description of Each Bit in Serial Mode Register (SMR0 to SMRA)
Bit name
Function
bit7
to
bit5
MD2, MD1, MD0:
Operation mode
setting bits
These bits set the operation mode of the asynchronous serial interface.
"000B": Set to the operation mode 0 (asynchronous normal mode).
"001B": Set to the operation mode 1 (asynchronous multiprocessor mode).
"010B": Set to the operation mode 2 (clock synchronous mode).
"100B": Set to the operation mode 4 (I2C mode).
Notes:
• Setting other than the above is disabled.
• If you switch the operation mode, perform the programmable clear (SCR:UPCL=1)
before changing the mode.
• Specify each register after the operation mode is set.
bit4
Unused bit
Read: The value is undefined.
Write: No effect.
bit3
SBL:
Stop-bit length
select bit
This bit sets the bit length of the stop bit (frame end mark of transmit data).
When "0" is set: The stop bit is set to bit-1.
When "1" is set: The stop bit is set to bit-2.
Notes:
• During receiving data, only the first bit of the stop bit is detected in all cases.
• This bit should be set if transmit is disabled (TXE=0).
bit2
BDS:
Transfer direction
selection bit
This bit selects whether transfer serial data is transferred starting with LSB (LSB first,
BDS=0) or with MSB (MSB first, BDS=1).
Note:
Set the bit when the transmission/reception is disabled (TXE=RXE=0).
bit1
SCKE:
Serial clock output
enable bit
This bit controls the I/O port of the serial clock.
If set to "0": It will be the SCK "H" output or the SCK input will be enabled. If used as
the SCK input, set the generic I/O port to the input port. In addition, select
the external clock using the external clock select bit (BGR:EXT=1).
If set to "1": The SCK output is enabled.
bit0
SOE:
Serial data output
enable bit
This bit enables or disables the output of the serial data.
If set to "0": The bit is SO "H" output.
If set to "1": The bit is SO output enable.
Note:
Set the operation mode first, because the other registers are initialized when the operation mode is
changed. However, if you write SCR and SMR simultaneously using 16-bit writing, the writing is
applied to SCR.
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CHAPTER 15 Serial Interface
15.3 Registers of UART (Asynchronous Serial Interface)
15.3.3
MB91345 Series
Serial Status Register (SSR0 to SSRA)
Serial Status Register (SSR0 to SSRA) checks the transmit or reception status. It also
checks and clears the reception error flag.
■ Serial Status Register (SSR0 to SSRA)
Figure 15.3-4 shows the bit configuration of the serial status register (SSR0 to SSRA). Table 15.3-5 lists
the function of each bit.
Figure 15.3-4 Bit Configuration of Serial Status Register (SSR0 to SSRA)
bit15 bit14 bit13 bit12 bit11 bit10
SSR
Address:
REC

PE
FRE
ORE RDRF
ch.0 000062H R/W

R
R
R
R
ch.1 000072H
ch.2 000082H
ch.3 000092H
ch.4 0000A2H
ch.5 0000B2H
ch.6 0001B2H
ch.7 0001C2H
ch.8 0001D2H
ch.9 0001E2H
ch.A 0001F2H
bit9
bit8
TDRE
TBI
R
R
bit7
bit0
Initial value
0-000011B
(ESCR)
TBI
0
1
Transmit bus idle flag bit
Transmitting
No transmission operation
TDRE
0
1
Transmission data empty flag bit
Data exists in transmit data register (TDR).
Transmit data register (TDR) is empty.
RDRF
0
1
Receive data full flag bit
Receive data register (RDR) is empty.
Data exists in receive data register (RDR).
ORE
0
1
Overrun error flag bit
No overrun error
Overrun error
FRE
0
1
Framing error flag bit
No framing error
Framing error
PE
0
1
Parity error flag bit
No parity error
Parity error
Unused bit
Read value is undefined. Writing has no effect.
REC
R/W
R

418
: Readable/writable
: Read only
: Unused bit
: Initial value
0
1
Receive error flag clear bit
Write
Read
No effect
Clear reception error flags Always read "0".
(PE, FRE, and ORE)
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
MB91345 Series
CHAPTER 15 Serial Interface
15.3 Registers of UART (Asynchronous Serial Interface)
Table 15.3-5 Functional Description of Each Bit in Serial Status Register (1 / 2)
Bit name
Function
bit15
REC:
Receive error flag clear bit
This bit clears the PE, FRE, and ORE bits of the serial status register (SSR).
• Writing "1" clears the error flag.
• Writing "0" has no effect.
When read: "0" always read.
bit14
Unused bit
Read: The value is undefined.
Write: No effect.
PE:
Parity error flag bit
(Function only in
operation mode 0)
• This bit is set to "1" when the parity error occurs during reception at
SMR:PEN=1, and cleared when "1" is written to the REC bit of the serial
status register (SSR).
• When the PE and SCR:RIE bits are both "1", a reception interrupt request is
output.
• The data in the receive data register (RDR) is not valid when this bit is set.
• If this flag is set when using the reception FIFO, the enable bit for the
reception FIFO will be cleared, and the reception data will not be contained in
the reception FIFO.
FRE:
Framing error flag bit
• This bit is set to "1" when the framing error occurs during reception, and
cleared when "1" is written to the REC bit of the serial status register (SSR).
• When the PEE and SCR:RIE bits are both "1", a reception interrupt request is
output.
• The data in the receive data register (RDR) is not valid when this bit is set.
• If this flag is set when using the reception FIFO, the enable bit for the
reception FIFO will be cleared, and the reception data will not be contained in
the reception FIFO.
PRE:
Overrun error flag bit
• This bit is set to "1" when the overrun occurs during reception, and cleared
when "1" is written to the REC bit of the serial status register (SSR).
• When the ORE and RIE bits are both "1", a reception interrupt request is
output.
• The data in the receive data register (RDR) is not valid when this bit is set.
• If this flag is set when using the reception FIFO, the enable bit for the
reception FIFO will be cleared, and the reception data will not be contained in
the reception FIFO.
RDRF:
Receive data full flag bit
• This flag indicates the status of the receive data register (RDR).
• The bit is set to "1" when the RDR loads received data. The bit is cleared to
"0" when the receive data register is read.
• When the RDRF and RIE bits are both "1", a reception interrupt request is
output.
• When using the reception FIFO, RDRF will be set to "1" if the FIFO receives
the specified number of data.
• When using the reception FIFO, the RDRF is set to "1" in the following
conditions:
- Reception FIFO idle detection enable bit (FCR1:FRIIE) is set to "1"
- Data is remained in reception FIFO without receiving number of specified
data items to the FIFO
- Receive idle state is kept 8 clocks or more with the baud rate clock
When having read RDR during the eight clocks count, the counter is reset to
"0", and then it counts another eight clocks.
• When using the reception FIFO, it will be cleared to "0" if the reception FIFO
is empty.
bit13
bit12
bit11
bit10
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CHAPTER 15 Serial Interface
15.3 Registers of UART (Asynchronous Serial Interface)
MB91345 Series
Table 15.3-5 Functional Description of Each Bit in Serial Status Register (2 / 2)
Bit name
bit9
bit8
420
Function
TDRE:
Transmission data empty
flag bit
• This flag indicates the status of the transmit data register (TDR).
• Goes to "0" when send data written to TDR to indicate that TDR contains
valid data. When the data is loaded into the transmit shift register and the
communication is started, it will be "1" indicating that no valid data exists in
TDR.
• When the TDRE and TIE bits are both "1", a transmission interrupt request is
output.
• If the UPCL bit in serial control register (SCR) is set to "1", the TDRE bit is
"1".
• See Section "15.4.4 Timing when the Interrupt Occurs and the Flag Should be
Set during the Use of the Transmit FIFO" for set/reset timing of the TDRE bit
when using transmit FIFO.
TBI:
Transmit bus idle flag bit
• This bit indicates the UART does not perform transmission operation.
• If the transmit data is written to transmit data register (TDR), this bit will be
"0".
• If transmit data register (TDR) is empty (TDRE=1) and no transmit operation
is performed, this bit will be "1".
• If the UPCL bit in serial control register (SCR) is set to "1", the TBI bit is "1".
• If this bit is "1" and the transmit bus idle interrupt is enabled (SCR:TBIE=1),
the transmit interrupt request will be output.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 15 Serial Interface
15.3 Registers of UART (Asynchronous Serial Interface)
MB91345 Series
15.3.4
Extended Communication Control Register (ESCR0 to
ESCRA)
Extended Communication Control Register (ESCR0 to ESCRA) sets the transmit or
reception data length, enables or disables the parity bit, selects the parity bit, and sets
the inverse of serial data format.
■ Bit Configuration of Extended Communication Control Register (ESCR0 to ESCRA)
Figure 15.3-5 shows the bit configuration of the extended communication control register (ESCR0 to
ESCRA). Table 15.3-6 lists the function of each bit.
Figure 15.3-5 Bit Configuration of Extended Communication Control Register (ESCR0 to ESCRA)
ESCR
bit15
Address
ch.0 000063H
ch.1 000073H
ch.2 000083H
ch.3 000093H
ch.4 0000A3H
ch.5 0000B3H
ch.6 0001B3H
ch.7 0001C3H
ch.8 0001D3H
ch.9 0001E3H
ch.A 0001F3H
bit8
(SSR)
bit7
bit6




L2
0
0
0
0
1
L1
0
0
1
1
0
bit5
bit4
INV PEN
R/W
L0
0
1
0
1
0
R/W
bit3
bit2
bit1
bit0
Initial value
P
L2
L1
L0
--000000B
R/W
R/W
R/W
R/W
Data-length select bit
bit length 8
bit length 5
bit length 6
bit length 7
bit length 9
P
0
1
Parity selection bit
Even parity
Odd parity
PEN
0
1
Parity enable bit
Disable parity
Enable parity
INV
0
1
Inverse serial data format bit
NRZ format
Inverse NRZ format
Unused bit
Read value is undefined. Writing has no effect.
R/W

: Readable/writable
: Unused bit
: Initial value
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CHAPTER 15 Serial Interface
15.3 Registers of UART (Asynchronous Serial Interface)
MB91345 Series
Table 15.3-6 Functional Description of Each Bit in Extended Communication Control Register
(ESCR0 to ESCRA)
Bit name
Function
bit7,
bit6
Unused bits
bit5
INV:
Inverse serial data
format bit
bit4
PEN:
Parity enable bit
(Function only in
operation mode 0)
This bit sets whether a parity bit is added (at transmission) or detected (at reception).
• If set to "0": The parity bit will not be added.
• If set to "1": The parity bit will be added.
Note:
This bit is internally fixed to "0" in the operation mode 1.
bit3
P:
Parity selection bit
(Function only in
operation mode 0)
This bit sets either "1" for odd parity or "0" for even parity when the parity is enabled
(ESCR:PEN=1).
• When set to "0": set to even parity.
• When set to "1": set to odd parity.
L2, L1, L0:
Data-length select
bit
This bit specifies the data length of the transmission/reception data.
• When set to "000B": the data length is set to 8-bit.
• When set to "001B": the data length is set to 5-bit.
• When set to "010B": the data length is set to 6-bit.
• When set to "011B": the data length is set to 7-bit.
• When set to "100B": the data length is set to 9-bit.
Notes:
• Setting other than the above is disabled.
• If the operation mode is 1, set the data length to 7-bit, 8-bit. Other settings are
prohibited.
bit2
to
bit0
422
Read: The value is undefined.
Write: No effect.
This bit selects NRZ format or inverse NRZ format as the serial data format.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 15 Serial Interface
15.3 Registers of UART (Asynchronous Serial Interface)
MB91345 Series
15.3.5
Receive Data Register (RDR0 to RDRA), Transmit Data
Register (TDR0 to TDRA)
The receive data and send data registers are located at the same address. It works as a
reception data register when read, and it works as a transmit data register when written.
If the FIFO operation is enabled, the RDR/TDR address will be a FIFO read/write
address.
■ Receive Data Register (RDR0 to RDRA)
Figure 15.3-6 shows the bit configuration of the receive data register (RDR0 to RDRA).
Figure 15.3-6 Bit Configuration of Receive Data Register (RDR0 to RDRA)
RDR
bit15
Address:
ch.0: 000064H, 000065H
ch.1: 000074H, 000075H
ch.2: 000084H, 000085H
ch.3: 000094H, 000095H
ch.4: 0000A4H, 0000A5H
ch.5: 0000B4H, 0000B5H
R/W : Readable/writable
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D8
D7
D6
D5
D4
D3
D2
D1
D0
000000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ch.6: 0001B4H, 0001B5H
ch.7: 0001C4H, 0001C5H
ch.8: 0001D4H, 0001D5H
ch.9: 0001E4H, 0001E5H
ch.A: 0001F4H, 0001F5H
Reception Data Register (RDR0 to RDRA) is a 9-bit data buffer register to receive the serial data.
• The signal sent to the serial input pin (SIN pin) is converted via a shift register and saved in the receive
data register (RDR0 to RDRA).
• Depending on the data length, the value "0" is inserted into the higher bit as follows:
Data length D8
D7
D6
D5
D4
D3
D2
D1
D0
bit9
X
X
X
X
X
X
X
X
X
bit8
0
X
X
X
X
X
X
X
X
bit7
0
0
X
X
X
X
X
X
X
bit6
0
0
0
X
X
X
X
X
X
bit5
0
0
0
0
X
X
X
X
X
(X is receive data bit.)
• The receive data full flag bit (SSR:RDRF) is set to "1" when the receive data is stored in the receive data
register (RDR0 to RDRA). If the reception interrupt is enabled (SSR:RIE=1), a reception interrupt
request will occur.
• Read the receive data register (RDR0 to RDRA) contents when the receive data full flag bit
(SSR:RDRF) is "1". The receive data full flag bit (SSR:RDRF) is automatically cleared to "0" when the
receive data register (RDR0 to RDRA) is read.
• The data in the receive data register (RDR0 to RDRA) is invalid if a receive error has occurred (any of
SSR:PE, ORE, or FRE is "1").
• For the operation mode 1 (multiprocessor mode), it is a 7-or 8-bit length operation, and the received AD
bit will be contained in the D8 bit.
• For the 9-bit transfer and the operation mode 1, RDR0 to RDRA is read through the 16-bit access.
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CHAPTER 15 Serial Interface
15.3 Registers of UART (Asynchronous Serial Interface)
MB91345 Series
Notes:
• When using the reception FIFO, SSR:RDRF will be set to "1" if the FIFO receives the specified
number of data.
• While the reception FIFO is being used, the SSR:RDRF is cleared to "0" when the reception FIFO
becomes empty.
• If a reception error (either SSR:PE, ORE, or FRE is "1") occurs when using the reception FIFO,
the enable bit for the reception FIFO will be cleared, and the reception data will not be contained
in the reception FIFO.
■ Transmit Data Register (TDR0 to TDRA)
Figure 15.3-7 shows the bit configuration of the transmit data register (TDR0 to TDRA).
Figure 15.3-7 Bit Configuration of Transmit Data Register (TDR0 to TDRA)
TDR
bit15
Address:
ch.0: 000064H, 000065H
ch.1: 000074H, 000075H
ch.2: 000084H, 000085H
ch.3: 000094H, 000095H
ch.4: 0000A4H, 0000A5H
ch.5: 0000B4H, 0000B5H
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D8
D7
D6
D5
D4
D3
D2
D1
D0
000000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ch.6: 0001B4H, 0001B5H
ch.7: 0001C4H, 0001C5H
ch.8: 0001D4H, 0001D5H
ch.9: 0001E4H, 0001E5H
ch.A: 0001F4H, 0001F5H
R/W: Readable/writable
Transmit data register (TDR0 to TDRA) is a 9-bit data buffer register to transmit the serial data.
• When the transmission data is written to the transmission data register (TDR0 to TDRA) while the
transmission operation is enabled (SCR: TXE=1), the transmission data is transferred to the
transmission shift register and converted into the serial data, then transmitted from the serial data output
pin (SOT pin).
• The invalid data is set from the higher bit toward the lower bit in order as follows, according to the data
length.
Data length D8
D7
D6
D5
D4
D3
D2
D1
D0
bit9
X
X
X
X
X
X
X
X
X
bit8
Invalid X
X
X
X
X
X
X
X
bit7
Invalid Invalid X
X
X
X
X
X
X
bit6
Invalid Invalid Invalid X
X
X
X
X
X
bit5
Invalid Invalid Invalid Invalid X
X
X
X
X
(X is transmit data bit.)
• The transmit data empty flag (SSR:TDRE) will be cleared to "0" if the transmit data is written into
transmit data register (TDR0 to TDRA).
• After the transmission data is transferred to the transmission shift register and the transmission is
started, the transmission data empty flag (SSR:TDRE) is set to "1" when the transmission FIFO is
disabled or empty.
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• The transmit data can be written if the transmit data empty flag (SSR:TDRE) is "1".When sending
interrupts are enabled, a sending interrupt is generated. The transmit data should be written when the
transmit interrupt occurs or if the transmit data empty flag (SSR:TDRE) is "1".
• The transmit data cannot be written if the transmit data empty flag (SSR:TDRE) is "0" and the transmit
FIFO is disabled or is full.
• For the operation mode 1 (multiprocessor mode), it is a 7-bit or 8-bit length operation, and the AD bit
will be transmitted by writing to the D8 bit.
• For the 9-bit transfer and the operation mode 1, TDR0 to TDRA is written through the 16-bit access.
Notes:
• The transmission data register is a write-only register and the reception data register is a readonly register. As the transmit or reception registers are placed in the same address, the written
value is different from the read value. Instructions, such as the INC/DEC instruction, which
provide the read-modify-write (RMW) instruction cannot be used.
• See Section "15.4.4 Timing when the Interrupt Occurs and the Flag Should be Set during the Use
of the Transmit FIFO" for set timing of the transmission data empty flag (SSR:TDRE) when using
transmit FIFO.
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CHAPTER 15 Serial Interface
15.3 Registers of UART (Asynchronous Serial Interface)
15.3.6
MB91345 Series
Baud Rate Generator Registers 0/1 (BGR00 to BGRA0,
BGR01 to BGRA1)
The baud rate generator registers 0/1 (BGR00 to BGRA0/BGR01 to BGRA1) set the serial
clock divide ratio. In addition, you can select the external clock as a clock source for the
reload counter.
■ Bit Configuration of Baud Rate Generator Registers 0/1 (BGR00 to BGRA0, BGR01 to
BGRA1)
Figure 15.3-8 shows bit configuration of baud rate generator registers 0 and 1 (BGR0, BGR1).
Figure 15.3-8 Bit Configuration of Baud Rate Generator Registers 0/1 (BGR00 to BGRA0, BGR01 to
BGRA1)
BGR00→BGRx0
(x = 0 to A)
Address
ch.0 000067H
ch.1 000077H
ch.2 000087H
ch.3 000097H
ch.4 0000A7H
ch.5 0000B7H
ch.6 0001B7H
ch.7 0001C7H
ch.8 0001D7H
ch.9 0001E7H
ch.A 0001F7H
BGR01→BGRx1
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
(x = 0 to A)
Address
00000000B
EXT
(BGR1)
(BGR0)
ch.0 000066H
00000000B
ch.1 000076H
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
ch.2 000086H
ch.3 000096H
ch.4 0000A6H
ch.5 0000B6H
ch.6 0001B6H
ch.7 0001C6H
ch.8 0001D6H
ch.9 0001E6H
BGR0
Baud Rate Generator Registers 0
ch.A 0001F6H
R/W: Readable/writable
Write
Read/
Write to reload counter bit0 to bit7.
Read setting value of BGR0.
BGR1
Write
Read
Baud Rate Generator Registers 1
Write to reload counter bit8 to bit14.
Read setting value of BGR1.
EXT
0
1
External clock selection bit
Use internal clock
Use external clock
• The baud rate generator registers 0/1 (BGR00 to BGRA0, BGR01 to BGRA1) set the serial clock divide
ratio.
• BGR1 corresponds to upper bits and BGR0 corresponds to lower bits, and the reload value to be
counted can be written and the setting value of BGR1/BGR0 can be read.
• Once the reload value is written to the baud rate generator registers (BGR00 to BGRA0, BGR01 to
BGRA1), the reload counter starts to count.
• Bit15 is an EXT bit that selects between internal or external clock for the reload counter clock source.
When EXT is set to "0", select the internal clock. When EXT is set to "1", select the external clock.
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CHAPTER 15 Serial Interface
15.3 Registers of UART (Asynchronous Serial Interface)
Notes:
• Writing to the baud rate generator registers 0/1 (BGR00 to BGRA0, BGR01 to BGRA1) should be
done by 16-bit access.
• When the setting value of the baud rate generator registers 0/1 (BGR00 to BGRA0, BGR01 to
BGRA1) are changed, the new value will be reloaded after the counter value gets to "0000H".
Therefore, if you immediately want to activate the new value, change the setting value of BGR0/
BGR1, and then perform the programmable clear (UPCL).
• If the reload value is an even number, the "L" width for the reception serial clock will be longer
than the "H" width by 1 cycle of the peripheral clock. If the value is an odd number, the "H" and "L"
widths for the serial clock will be the same.
• Set a value of 4 or more for BGR0/BGR1. However, the data might not be received normally due
to the deviation of the baud rate and the setting of the reload value.
• To change the setting to external clock (EXT=1) while baud rate generator is operating, write "0"
to the baud rate generators 1 and 0 (BGR0/BGR1) and set external clock (EXT=1) after executing
program clear (UPCL).
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CHAPTER 15 Serial Interface
15.3 Registers of UART (Asynchronous Serial Interface)
15.3.7
MB91345 Series
FIFO Control Register 1 (FCR01, FCR11)
FIFO Control Register 1 (FCR01, FCR11) sets the FIFO test, selects the transmit or
reception FIFOs, enables the transmit FIFO interrupt, and controls the interrupt flags.
■ Bit Configuration of FIFO Control Register 1 (FCR01, FCR11)
Figure 15.3-9 shows the bit configuration of the FIFO control register 1 (FCR01, FCR11). Table 15.3-7
lists the function of each bit.
Figure 15.3-9 Bit Configuration of FIFO Control Register 1 (FCR01, FCR11)
FCRx1
(x = 0, 1)
Address
ch.0 00006AH
ch.1 00007AH
bit15 bit14 bit13 bit12 bit11 bit10
Reserved Reserved
R/W
R/W

()
FLSTE FRIIE FDRQ
R/W
R/W
R/W
bit9
bit8
FTIE
FSEL
R/W
R/W
bit7
bit0
(FCR0)
Initial value
00-0000000000000B
FSEL
0
1
FIFO selection bits
(Transmit FIFO:FIFO1, Receive FIFO:FIFO2)
(Transmit FIFO:FIFO2, Receive FIFO:FIFO1)
FTIE
0
1
Transmit FIFO interrupt enable bit
Disable transmission FIFO interrupts
Enable transmission FIFO interrupt
FDRQ
0
1
Transmit FIFO data request bit
No transmission FIFO data request
Transmission FIFO data request
FRIIE
0
1
Reception FIFO idle detection enable bit
Disable reception FIFO idle detection.
Enable reception FIFO idle detection.
FLSTE Retransmission data lost detection enable bit
0
Disable data lost detection.
1
Enable data lost detection.
Unused bit
The read value is undefined. Writing has no effect.
Reserved
0
R/W

428
FIFO test bit
Be sure to set "0" to this bit..
: Readable/writable
: Unused bit
: Initial value
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CHAPTER 15 Serial Interface
15.3 Registers of UART (Asynchronous Serial Interface)
MB91345 Series
Table 15.3-7 Functional Description of Each Bit in the FIFO Control Register 1 (FCR01, FCR11)
Bit name
Function
bit15,
bit14
Reserved bit
This bit is reserved bit.
Be sure to set "0" to this bit.
bit13
Unused bit
Read: The value is undefined.
Write: No effect.
bit12
FLSTE:
Retransmission data
lost detection enable
bit
This bit enables detection of the FLST bit.
When set to "0": Disable detection of the FLST bit.
When set to "1": Enable detection of the FLST bit.
Note:
Set "1" to this bit after "1" is set to FSET bit.
bit11
FRIIE:
Reception FIFO idle
detection enable bit
This bit sets whether the reception idle state of 8-bit time or more is detected while valid
data exists in reception FIFO. If the reception interrupt is enabled (SCR:RIE=1), the
reception interrupt will occur when the reception idle status is detected.
When set to "0": The reception idle status detection is disabled.
When set to "1": The reception idle status detection is enabled.
bit10
FDRQ:
Transmit FIFO data
request bit
This bit is the data request bit of transmit FIFO. When this bit is set to "1", it indicates the
transmission data is requested. If the transmit FIFO interrupt is enabled (FTIE=1), the
FIFO transmit interrupt request will be output.
The FDRQ set condition:
• FBYTE (transmit)=0 (transmit FIFO is empty)
The FDRQ reset condition:
• Writing "0" to this bit.
• When transmit FIFO is full.
Notes:
• Writing "0" to this bit is valid when transmit FIFO is enabled.
• When the FBYTE (for transmission)=0, writing "0" to this bit is disabled.
• When this bit is set to "1", there is no influence on the operation.
• When having a read-modify-write (RMW) related instruction, "1" is read out.
bit9
FTIE:
Transmit FIFO
interrupt enable bit
bit8
FSEL:
FIFO selection bit
This bit is the interrupt enable bit of transmit FIFO. An interrupt occurs if this bit is set to
"1" when the FDRQ bit is "1".
This bit selects transmit / reception FIFO.
When set to "0": Assign to transmit FIFO:FIFO1, reception FIFO:FIFO2.
When set to "1": Assign to transmit FIFO:FIFO2, reception FIFO:FIFO1.
Notes:
• This bit is not cleared by FIFO reset (FCL2, FCL1=1).
• To change this bit, disable the FIFO operation (FCR:FE2, FE1=0) first.
Note:
The transmit interrupts include the transmit FIFO interrupt request and the transmit buffer interrupt request.
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CHAPTER 15 Serial Interface
15.3 Registers of UART (Asynchronous Serial Interface)
15.3.8
MB91345 Series
FIFO Control Register 0 (FCR00, FCR10)
The FIFO Control Register 0 (FCR00, FCR10) enables or disables the FIFO operation,
resets FIFO, saves the read pointer, and sets retransmit.
■ Bit Configuration of FIFO Control Register 0 (FCR00, FCR10)
Figure 15.3-10 shows the bit configuration of the FIFO control register 0 (FCR00, FCR10). Table 15.3-8
lists the function of each bit.
Figure 15.3-10 Bit Configuration of FIFO Control Register 0 (FCR00, FCR10)
FCRx0
(x = 1, 0)
Address
ch.0 00006BH
ch.1 00007BH
bit15
bit8
(FCR1)
bit1
bit0
Initial value

FLST FLD FSET FCL2 FCL1
FE2
FE1
00000000B
()
R/W
R/W
R/W
bit7
bit6
R/W
FIFO2 Operation Enable Bit
FIFO2 operation disabled
FIFO2 Enabling Operations
0
1
FSET
0
1
430
R/W
bit2
FE2
0
1
FCL2
: Readable/writable
: Unused bit
: Initial value
R/W
bit3
FIFO1 Operation Enable Bit
FIFO1 operation disabled
FIFO1 Enabling Operations
0
1

R/W
bit4
FE1
0
1
FCL1
R/W
bit5
FIFO1 reset bit
Write
Read
No effect
Always read "0".
FIFO1 Reset
FIFO2 reset bit
Write
Read
No effect
Always read "0".
FIFO2 Reset
FIFO pointer save bit
Write
Read
No save
Always read "0".
Execute save
FLD
0
1
FIFO pointer reload bit
No reload
Execute reload
FLST
0
1
FIFO retransmit data lost flag bit
No data lost
Data lost
Unused bit
"0" is always read at read operation.
"0" is always written at write operation.
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CM71-10132-3E
MB91345 Series
CHAPTER 15 Serial Interface
15.3 Registers of UART (Asynchronous Serial Interface)
Table 15.3-8 Functional Description of Each Bit in the FIFO Control Register 0 (FCR00, FCR10) (1 / 2)
Bit name
bit7
bit6
bit5
bit4
bit3
bit2
Function
Unused bit
When read: "0" is always read.
When write: "0" is always written.
FLST:
FIFO retransmit
data lost flag bit
This bit indicates that the retransmission data of transmit FIFO was lost.
FLST set condition:
Data is written (overwritten) to FIFO when the FLSTE bit of the FIFO control register 1
(FCR1) is "1" and the write pointer of transmit FIFO and the read pointer saved by the FSET
bit match.
FLST reset condition:
• FIFO reset (write "1" to FCL)
• Write "1" to the FSET bit
When "1" is set to this bit, data which the read pointer saved by the FSET bit indicates is
overwritten, and retransmission cannot be set by the FLD bit even if error occurs. When you
retransmit the data while this bit is set to "1", you must reset the FIFO, and write the data to
the FIFO again.
FLD:
FIFO pointer
reload bit
This bit reloads data saved to transmit FIFO by the FSET bit to the read pointer. This bit is
used to retransmit the data when a communication error occurs.
Once the retransmit setting is completed, this bit becomes "0".
Notes:
• Data is being reloaded to the read pointer while this bit is set to "1". Therefore, do not
write reset other than FIFO reset.
• Setting "1" to this bit is not allowed during FIFO enable condition or transmission.
• Set the TIE and TBIE bits to "0" before writing "1" to this bit, and after enabling the
transmit FIFO, set the bits to "1".
FSET:
FIFO pointer save
bit
This bit saves the read pointer of transmit FIFO.
By saving the read pointer before communicating, retransmit will be available if the FLST bit
is "0" when a communication error occurs.
When set to "1": Current read pointer value is saved.
When the bit is set to "0": No effect.
Note:
Set this bit to "1" while number of transmission bytes (FBYTE) indicates "0".
FCL2:
FIFO2 reset bit
This bit resets FIFO2.
When this bit is set to "1", the internal status of FIFO2 is initialized.
Only the FCR1:FLST bit is initialized. Other bits of the FCR1/FCR0 register are retained as is.
Notes:
• Execute FIFO2 reset after disabling the transmission/reception operation.
• Enable the transmit FIFO interrupt by setting the value to "0" before running it.
• Number of valid data for the FBYTE2 register is "0".
FCL1:
FIFO1 reset bit
This bit resets FIFO1.
When this bit is set to "1", the internal status of FIFO1 is initialized.
Only the FCR1: FLST bit is initialized. Other bits of the FCR1/FCR0 register are retained as
is.
Notes:
• Execute FIFO1 reset after disabling the transmission/reception operation.
• Enable the transmit FIFO interrupt by setting the value to "0" before running it.
• Number of valid data for the FBYTE1 register is "0".
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CHAPTER 15 Serial Interface
15.3 Registers of UART (Asynchronous Serial Interface)
MB91345 Series
Table 15.3-8 Functional Description of Each Bit in the FIFO Control Register 0 (FCR00, FCR10) (2 / 2)
Bit name
bit1
bit0
432
Function
FE2:
FIFO2 Operation
Enable Bit
This bit enables / disables the operation of FIFO2.
• If FIFO2 is used, set this bit to "1".
• The transmit will be started immediately when UART is enabled for transmit (TXE=1), if
FIFO2 is set to the transmit FIFO (FCR1:FSEL=1) and the data exists in FIFO2 at writing
"1" to this bit. Set the TIE and TBIE bits to "0" before writing "1" to this bit, and then set
the bits to "1".
• If this is selected as a reception FIFO by FSEL bit, this bit is cleared to "0" in case of the
reception error, and this bit cannot be set to "1" until the reception error is cleared.
• This bit should set to "1" or "0" when the transmit buffer is empty (TDRE=1) to use with
the transmit FIFO, or when the reception buffer is empty (RDRF=0) to use with the
reception FIFO.
• FIFO2 state is maintained even when FIFO2 is disabled.
FE1:
FIFO1 Operation
Enable Bit
This bit enables / disables the operation of FIFO1.
• If FIFO1 is used, set this bit to "1".
• The transmit will be started immediately when UART is enabled for transmit (TXE=1), if
FIFO1 is set to the transmit FIFO (FCR1:FSEL=0) and the data exists in FIFO1 at writing
"1" to this bit. Set the TIE and TBIE bits to "0" before writing "1" to this bit, and then set
the bits to "1".
• If this is selected as a reception FIFO by FSEL bit, this bit is cleared to "0" in case of the
reception error, and this bit cannot be set to "1" until the reception error is cleared.
• This bit should set to "1" or "0" when the transmit buffer is empty (TDRE=1) to use with
the transmit FIFO, or when the reception buffer is empty (RDRF=0) to use with the
reception FIFO.
• FIFO1 state is maintained even when FIFO1 is disabled.
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CHAPTER 15 Serial Interface
15.3 Registers of UART (Asynchronous Serial Interface)
MB91345 Series
15.3.9
FIFO Byte Register (FBYTE01, FBYTE02, FBYTE11,
FBYTE12)
The FIFO byte register (FBYTE01, FBYTE02, FBYTE11, FBYTE12) indicates the number
of the data available for FIFO. In addition, you can set whether the reception interrupt
should occur when the reception FIFO receives the specified number of data.
■ Bit Configuration of FIFO Byte Register (FBYTE01, FBYTE02, FBYTE11, FBYTE12)
Figure 15.3-11 shows the bit configuration of the FIFO byte register (FBYTE01, FBYTE02, FBYTE11,
FBYTE12).
Figure 15.3-11 Bit Configuration of FIFO Byte Register (FBYTE01, FBYTE02, FBYTE11, FBYTE12)
FBYTE01
FBYTE02
FBYTE11
FBYTE12
bit15 bit14 bit13 bit12 bit11 bit10
Address
ch.01 00006DH
ch.02 00006CH R/W
ch.11 00007DH
ch.12 00007CH
bit9
bit8
bit7
bit6
bit5
(FBYTE2)
R/W
R/W
R/W
R/W
bit4
bit3
bit2
bit1
bit0
00000000B
00000000B
(FBYTE1)
R/W
R/W
R/W
R/W
R/W: Readable/writable
Read (number of valid data)
At transmission : Number of data written to FIFO and not
transmitted
At reception
: Number of data received in FIFO
Write (number of transfer)
At transmission : Set "00H".
At reception
: Set number of data which generates
the reception interrupt
R/W
R/W
R/W
R/W
Initial value
R/W
R/W
R/W
FBYTE1
Write
Read
FIFO1 data count indication bit
Set number of transfer.
Read number of valid data.
FBYTE2
Write
Read
FIFO2 data count indication bit
Set number of transfer.
Read number of valid data.
The FBYTE register indicates the number of the valid data that was received or written to FIFO, as shown
in the following list depending on the setting of the FCR1:FSEL bit.
Table 15.3-9 Indicate Number of Data
FSEL
CM71-10132-3E
FIFO selection
Indicate number of data
0
FIFO2: Reception FIFO, FIFO1: Transmit FIFO
FIFO2: FBYTE2, FIFO1: FBYTE1
1
FIFO2: Transmit FIFO, FIFO1: Reception FIFO
FIFO2: FBYTE2, FIFO1: FBYTE1
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15.3 Registers of UART (Asynchronous Serial Interface)
MB91345 Series
• Initial value of transfer count for the FBYTE register is "08H".
• Specify the data count that causes the reception interrupt flag to be generated in FBYTE of the reception
FIFO. The interrupt flag (SSR:RDRF) is set to "1" if the specified number of the transfers matches the
number of the data displayed for the FBYTE register.
• While the reception FIFO idle detection enable bit (FRIIE) is "1" and the data count that exists in the
reception FIFO is under the transfer count, the interrupt flag (RDRF) is set to "1" when the reception
idle status continues for 8 or more clocks in the baud rate clock. When having read RDR during the
eight clocks count, the counter is reset to "0", and then it counts another eight clocks. When the
reception FIFO is disabled, the counter is reset to "0". If you enable the reception FIFO when the data
remains in the FIFO, the counting process will be started again.
Notes:
• Set the FBYTE register for transmit FIFO to "00H".
• Set data of "1" or more to the FBYTE for reception FIFO.
• Execute change operation after disabling the reception operation.
• This register cannot use the read-modify-write (RMW) related commands.
• Setting that exceeds capacity of FIFO is disabled.
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CHAPTER 15 Serial Interface
15.4 UART Interrupt
MB91345 Series
15.4
UART Interrupt
UART has the transmit/reception interrupt. The interrupt request can be occurred by the
following factors:
• When received data is set in the receive data register (RDR) or a reception error
occurs.
• When the send data is transferred from the send data register (TDR) to the send shift
register and sending starts.
• Transmission bus idle (no transmission operation)
• Transmission FIFO data request
■ UART Interrupt
Table 15.4-1 shows the interrupt control bit and the interrupt factor of UART.
Table 15.4-1 Interrupt Control Bit of UART and Interruption Factor (1 / 2)
Interrupt
type
Interrupt
Flag
request
register
flag bit
RDRF
Operation
mode
0
Interrupt factor
1
SSR
Read receive data (RDR).
Receiving the FBYTE
setting value
Read the receive data (RDR)
until reception FIFO is empty.
ORE
SSR
Overrun error
FRE
SSR
Framing error
PE
SSR
CM71-10132-3E
×
Clear interrupt request flag
1-byte reception
Detect the reception idle
state of 8-bit time or more
while the FRIIE bit is "1"
and valid data exists in
reception FIFO.
Receive
Interrupt
factor
enable bit
SCR:RIE
Write "1" to the reception error
flag clear bit (SSR:REC).
Parity error
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CHAPTER 15 Serial Interface
15.4 UART Interrupt
MB91345 Series
Table 15.4-1 Interrupt Control Bit of UART and Interruption Factor (2 / 2)
Interrupt
type
Interrupt
Flag
request
register
flag bit
TDRE
SSR
Operation
mode
0
Interrupt factor
1
Transmit register is
empty.
Transmit
TBI
FDRQ
SSR
FCR1
No transmission
operation.
Transmit FIFO is empty.
Interrupt
factor
enable bit
Clear interrupt request flag
SCR:TIE
Write "1" to the transmission
FIFO operation enable bit when
writing to the transmit data
(TDR) or the transmission FIFO
operation enable bit is "0", and
valid data exists in transmit
FIFO (Resend). *
Write "1" to the transmission
FIFO operation enable bit when
writing to the transmit data
SCR:TBIE (TDR) or the transmission FIFO
operation enable bit is "0", and
valid data exists in transmit
FIFO (Resend). *
FCR1:
FTIE
Write "0" to the FIFO
transmission data request bit
(FCR1:FDRQ) or transmit FIFO
is full.
*: Set the TIE bit to "1" after the TDRE bit becomes "0".
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CHAPTER 15 Serial Interface
15.4 UART Interrupt
MB91345 Series
15.4.1
Reception Interrupt Generation and Flag Set Timing
Interrupts during reception are one generated upon completion of reception
(SSR:RDRF) and one generated upon occurrence of a reception error (SSR:PE, ORE,
FRE).
■ Reception Interrupt Generation and Flag Set Timing
When the first stop bit is detected, the reception data is contained in Reception Data Register (RDR). If a
reception error occurs (SSR:PE, ORE, FRE=1) upon completion of reception (SSR:RDRF=1), the
corresponding flag is set. A receive interrupt is also generated if the receive interrupt is enabled
(SSR:RIE=1).
Note:
If a reception error occurs, the data in Reception Data Register (RDR) will be invalid.
Figure 15.4-1 The Set Timing for the RDRF (Reception Data Full) Flag Bit
Reception data
ST
D0
D1
D2
D5
D6
D7
SP
ST
RDRF
Generate receive interrupt
Figure 15.4-2 The Set Timing for the FRE (Framing Error) Flag Bit
Reception data
ST
D0
D1
D2
D5
D6
D7
SP
ST
RDRF
FRE
Generate receive interrupt
Notes :
When the first stop bit's level is "L" , the framing error is generated.
Receive data is invalid though RDRF is set to "1" and the data is receive even if the framing
error is generated.
Figure 15.4-3 The Set Timing for the ORE (Overrun Error) Flag Bit
Reception data
ST D0 D1 D2 D3
D4 D5 D6 D7 SP
ST D0
D1 D2 D3 D4 D5 D6 D7 SP
RDRF
ORE
Note : If the next data is transferred before receive data is read, the over-run error is generated.
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CHAPTER 15 Serial Interface
15.4 UART Interrupt
15.4.2
MB91345 Series
Timing when the interrupt occurs and the flag should be
set during the use of the reception FIFO
During the use of the reception FIFO, an interrupt occurs when the setting value in the
FBYTE register (FBYTE) is received.
■ Timing when the Reception Interrupt Occurs and the Flag Should be Set during the
Use of the Reception FIFO
An occurrence of interrupt during the use of the reception FIFO is determined by the setting value in the
FBYTE register.
• When the data of the set transfer count of FBYTE register have been received, the reception data full
flag (SSR:RDRF) of the serial status register is set to "1". And if the reception interrupt is enabled
(SCR:RIE), a reception interrupt will occur.
• While the reception FIFO idle detection enable bit (FRIIE) is "1" and the data count that exists in the
reception FIFO is under the transfer count, the interrupt flag (RDRF) is set to "1" when the reception
idle status continues for 8 or more clocks in the baud rate clock. When having read RDR during the
eight clocks count, the counter is reset to "0", and then it counts another eight clocks. When the
reception FIFO is disabled, the counter is reset to "0". If you enable the reception FIFO when the data
remains in the FIFO, the counting process will be started again.
• When the reception data (RDR) is read until the reception FIFO becomes empty, the reception data full
flag (SSR:RDRF) is cleared.
• If the number of valid reception data indicates the FIFO capacity, an overrun error (SSR:ORE=1) will
occur when receiving the next data.
Figure 15.4-4 Timing when the Reception Interrupt Occurs during the Use of the Reception FIFO
Reception data
ST 1st byte SP
ST 2nd byte SP
ST 3rd byte SP
FBYTE setting
(number of transmission)
FBYTE read
(valid byte display)
ST 4th byte SP
ST 5th byte SP
3
0
1
2
3
2 1
0
1
2
RDRF
Reading of RDR
Read all receive data
Interrupt is generated when FBYTE setting
(number of transmission) and number of
reception data are matched.
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15.4 UART Interrupt
MB91345 Series
Figure 15.4-5 The Set Timing for the ORE (Overrun Error) Flag Bit
ST 62nd byte SP
Reception data
ST 63rd byte SP
FBYTE setting
(number of transmission)
FBYTE read
(valid byte display)
ST 64th byte SP
ST 65th byte SP
ST 66th byte SP
62
62
63
64
RDRF
ORE
Overrun error generation
Note:
When FBYTE read receives the next data at the state of specifying FIFO capacitance, overrun error is generated.
This figure shows the case of using 64-byte FIFO capacitance.
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CHAPTER 15 Serial Interface
15.4 UART Interrupt
15.4.3
MB91345 Series
Transmit Interrupt Generation and Flag Set Timing
Interrupt during the transmit will occur if the transmit data is transferred from transmit
data register (TDR) to the shift register for the transmit (SSR:TDRE=1) and the transmit
is started, and if there is no transmit operation (SSR:TBI=1).
■ Transmit Interrupt Generation and Flag Set Timing
● The set timing for the transmit data empty flag (TDRE)
When the data written to transmit data register (TDR) is transferred to the transmit shift register, it will be
available to write the next data (SSR:TDRE=1). A send interrupt is generated at this time if the send
interrupt is enabled (SSR:TIE=1). Since TDRE bit is a read-only bit, it is cleared to "0" by writing data to
the transmission data register (TDR).
Figure 15.4-6 The Set Timing for the Transmit Data Empty Flag (TDRE)
Transmission interrupt generation
Transmission data
(mode 0, 1)
ST
D0
D1
D2
Transmission interrupt generation
D3
D4
D5
D6
D7
SP ST
D0
D1
D2
TDRE
Write to TDR
ST: Start bit
D0 to D7: Data bit
SP: Stop bit
● The set timing for the transmit bus idle flag (TBI)
When the transmit data register is empty (TDRE=1) and does not transmit, the SSR: TBI bit is set to "1". In
this case, if the transmit bus idle interrupt is enabled (SCR:TBIE=1), the transmit interrupt will occur.
When the transmission data is set to the transmission data register (TDR), the TBI bit and the transmit
interrupt request will be cleared.
Figure 15.4-7 The Set Timing for the Transmit Bus Idle Flag (TBI)
Transmission
data
ST
D0
D1
D2
D3
D4
D5 D6
D7
SP
ST
D0
D1
D2
D3
D4
D5 D6
D7
TBI
TDRE
Transmission interrupt
generation by TBI
TDR write
ST: Start bit
440
D0 to D7: Data bit
SP: Stop bit
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CHAPTER 15 Serial Interface
15.4 UART Interrupt
MB91345 Series
15.4.4
Timing when the Interrupt Occurs and the Flag Should
be Set during the Use of the Transmit FIFO
Interrupt during the use of the transmit FIFO will occur when there is no data in the
transmit FIFO.
■ Timing when the Transmit Interrupt Occurs and the Flag Should be Set during the Use
of the Transmit FIFO
• When the data does not exist in the transmission FIFO, the FIFO transmission data request bit
(FCR1:FDRQ) is set to "1". If the FIFO transmit interrupt is enabled (FCR1:FTIE=1) at this time, the
transmit interrupt occurs.
• When a transmit interrupt is generated and the necessary data is written to the transmit FIFO, write "0"
to FIFO transmit data request bit (FCR1:FDRQ) to clear the interrupt request.
• When the transmission FIFO becomes get to full, the FIFO transmission data request bit (FCR1:FDRQ)
becomes "0".
• The existence of transmit FIFO data can be checked by reading out the FIFO byte register (FBYTE).
FBYTE=00B indicates that no data exists in the transmit FIFO.
Figure 15.4-8 Timing when the Transmit Interrupt Occurs during the Use of the Transmit FIFO
Transmission
data
FBYTE
ST 1st byte SP
0
1
2
1
ST 2nd byte SP
0
1
ST 3rd byte ST
2
SP 4th byte SP
SP 5th byte
0
1
FDRQ
TDRE
Write to
transmission
FIFO (TDR)
Transmission
Clear by "0" write interrupt generation *1
Clear by "0" write
Transmission
interrupt generation *1
Transmission data register is empty *2
*1 : FDRQ=1 is set because transmission FIFO is empty.
*2 : TDRE=1 is set because the data does not exist in transmission shift register and transmission buffer register.
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CHAPTER 15 Serial Interface
15.5 Operation of UART
15.5
MB91345 Series
Operation of UART
UART works on the duplex serial asynchronous transmission for the mode 0, or the
master/slave multiprocessor transmission for the mode 1.
■ Operation of UART
● Format of transmit/receive data
• The transmit or reception data always start from the start bit. The data is transmitted or received by the
specified data bit length, and it ends at the stop bit with 1-bit at least.
• The data transfer direction (LSB-first or MSB-first transfer) is determined by the BDS bit in Serial
Mode Register (SMR). When parity is used, the parity bit is always placed between the last data bit and
the first stop bit.
• For the operation mode 0 (normal mode), you can select whether parity should be added or not.
• For the operation mode 1 (multiprocessor mode), the AD bit will be added, not parity.
Format of transmit and receive data for the operation mode 0 and the operation mode 1 is shown in Figure
15.5-1.
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CHAPTER 15 Serial Interface
15.5 Operation of UART
MB91345 Series
Figure 15.5-1 Example of Transmit and Receive Data Format (Operation Mode 0 and 1)
[Operation mode 0]
ST
D0 D1
D2
D3
D4
D5
D6
D7
SP1 SP2
ST
D0 D1
D2
D3
D4
D5
D6
D7
SP1
ST
D0 D1
D2
D3
D4
D5
D6
D7
P
Without P
Data 8-bit
SP1 SP2
With P
ST
D0 D1
D2
D3
D4
D5
D6
D7
P
ST
D0 D1
D2
D3
D4
D5
D6 SP1 SP2
ST
D0 D1
D2
D3
D4
D5
D6 SP1
ST
D0 D1
D2
D3
D4
D5
D6
SP1
Without P
Data 7-bit
P
SP1 SP2
With P
ST
D0 D1
D2
D3
D4
D5
D6
P
SP1
[Operation mode 1]
ST
D0 D1
D2
D3
D4
D5
D6
D7
AD SP1 SP2
ST
D0 D1
D2
D3
D4
D5
D6
D7
AD SP1
ST
D0 D1
D2
D3
D4
D5
D6
AD SP1 SP2
Data 8-bit
Data 7-bit
ST
D0 D1
D2
D3
D4
D5
D6
AD SP1
ST : Start bit
SP : Stop bit
P : Parity bit
AD : Address bit
D0 to D7 : Data bit
Notes:
• The figure shows the data length set to 7-bit, 8-bit. (For the operation mode 0, the data length
can be set to 5-bit to 9-bit.)
• If the BDS bit in Serial Mode Register (SMR) is set to "1" (MSB-first), the bit will be processed
in the order of D7, D6, D5, ...D1, D0(P).
• If the data length is set to the X bit length, the lower X bit in transmit or reception Data Register
(RDR/TDR) will be enabled.
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CHAPTER 15 Serial Interface
15.5 Operation of UART
MB91345 Series
● Transmission Operation
• If the transmit data empty flag bit (TDRE) in Serial Status Register (SSR) is "1", the transmit data can
be written to transmit data register (TDR) (When the transmit FIFO is enabled, the transmit data can be
written if TDRE=0).
• If the transmit data is written to transmit data register (TDR), the transmit data empty flag bit (TDRE)
will be "0".
• If the transmit operation enable bit in Serial Control Register (SCR:TXE) is set to "1", the transmit data
will be loaded into the transmit shift register, and the transmit will be started from the start bit.
• When the transmit is started, the transmit data empty flag bit (TDRE) will be set to "1" again. And if the
transmit interrupt is enabled (SCR:TIE=1), a transmit interrupt will occur. In interrupt processing, the
next data to transmit can be written to the transmit data register (TDR).
Notes:
• The transmit data empty flag bit (SSR:TDRE) is initially set to "1", and if the transmit interrupt is
enabled (SCR:TIE), the transmit interrupt will occur immediately.
• The FIFO transmit data request bit (FCR1:FDRQ) is initially set to "1", and if the FIFO transmit
interrupt is enabled (FCR1:FTIE=1), the transmit interrupt will occur immediately.
● Reception Operation
• When the reception operation is enabled (SCR:RXE=1), the reception operation starts.
• When the start bit is detected, the 1 frame data is received based on the data format that was set in
Extended Communication Control Register (ESCR:PEN, P, L2, L1, L0) and Serial Mode Register
(SMR:BDS).
• When the 1 frame reception is completed, the reception data full flag bit (SSR:RDRF) is set to "1". And
if the reception interrupt is enabled (SCR:RIE=1), a reception interrupt will occur.
• When reading the reception data, read the reception data after the 1 frame data is completely received,
and check the status of the error flag in Serial Status Register (SSR). When a reception error occurs,
perform error handling.
• The reception data full flag bit (SSR:RDRF) is set to "0" by reading the reception data.
• If the reception FIFO is enabled, the reception data full flag bit (SSR:RDRF) will be set to "1" when the
frames that were set in the reception FBYTE are received.
• While the reception FIFO idle detection enable bit (FRIIE) is "1" and the data count that exists in the
reception FIFO is under the transfer count, the interrupt flag (RDRF) is set to "1" when the reception
idle status continues for 8 or more clocks in the baud rate clock. When having read RDR during the
eight clocks count, the counter is reset to "0", and then it counts another eight clocks. When the
reception FIFO is disabled, the counter is reset to "0". If you enable the reception FIFO when the data
remains in the FIFO, the counting process will be started again.
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CHAPTER 15 Serial Interface
15.5 Operation of UART
MB91345 Series
• If the reception FIFO is enabled, when the error flag in Serial Status Register (SSR) is set to "1", the
reception FIFO will not contain the data in which that error occurred. In addition, the reception data full
flag bit (SSR:RDRF) will not be set to "1". (For an overrun error, however, the RDRF flag is set to "1".)
Displayed reception FBYTE indicates the number of data, which was normally received before an error
occurred. The reception FIFO will not be enabled unless the error flag in Serial Status Register (SSR) is
cleared to "0".
• If the reception FIFO is enabled, the reception data full flag bit (SSR:RDRF) will be cleared to "0" when
the data no longer exists in the reception FIFO.
Note:
The data in Reception Data Register (RDR) will be valid if no reception error occurs (SSR:PE, ORE,
FRE=0) when the reception data register full flag bit (SSR:RDRF) is set to "1".
● Clock Selection
• The internal or external clock can be used.
• When the external clock is used, set SMR:EXT=1. In this case, the external clock will be divided in the
baud rate generator.
● Start Bit Detection
• When using the asynchronous mode, the start bit is identified with the falling edge of the SIN signal.
Therefore, if the reception operation is enabled (SCR:RXE=1), the operation will not be started unless
the falling edge of the SIN signal is entered.
• When the falling edge of the start bit is detected, the reception reload counter of the baud rate generator
is reset, and then starts reload and count down again. This always enables a sampling at the center of the
data.
Start bit
Data bit
SIN
SIN (OverSampled)
SEDGE
(Internal
signal)
Reload counter
reset
Data sampling
Reception
sampling
clock
1 bit time
● Stop Bit
• During transmission, one bit or two bits can be selected.
• The reception data full flag bit (SSR:RDRF) will be set to "1" when the first stop bit is detected.
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CHAPTER 15 Serial Interface
15.5 Operation of UART
MB91345 Series
● Error detection
• For the operation mode 0, the parity error, overrun error, and frame error can be detected.
• For the operation mode 1, the overrun error and frame error can be detected. Parity errors cannot be
detected.
● Parity bit
• The addition of a parity bit can be set only in operation mode 0. You can set whether the parity should
be added or not using the parity enable bit (ESCR:PEN), and whether the parity should be even or odd
using the parity selection bit (ESCR:P).
• Parity cannot be used in operation mode 1.
Figure 15.5-2 shows transmit and receive data when the parity is available.
Figure 15.5-2 Operation when the Parity is Available
ST
Reception
data
(mode 0)
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
When receiving in even parity,
parity error is generated.
(ESCR:P=0)
SMR:PE
Transmission
data
(mode 0)
Transmission of even parity
(ESCR:P=0)
Transmission
data
(mode 0)
Transmission of odd parity
(ESCR:P=1)
ST: Start bit SP: Stop bit In case which has parity (ESCR:PEN=1) and 8-bit length
Note: Parity is not used in operation mode 1.
● Data signal type
By setting the INV bit in Extended Communication Control Register, you can select either the NRZ
(NonReturntoZero) signal method (ESCR:INV=0) or the inverse NRZ signal method (ESCR:INV=1).
The figure below shows the Non Return to Zero (NRZ) signal method and the inverse NRZ signal method.
Figure 15.5-3 Non Return to Zero (NRZ) Signal Method and Inverse NRZ Signal Method
SIN (NRZ)
INV = 0
SIN (Inverse NRZ)
INV = 1
SOT (NRZ)
INV = 0
SOT (Inverse NRZ)
INV = 1
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
● Data transfer method
The data bit transfer method can be either LSB-first or MSB-first.
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CHAPTER 15 Serial Interface
15.6 Dedicated Baud Rate Generator
MB91345 Series
15.6
Dedicated Baud Rate Generator
The transmission/reception clock source for the UART can be selected from among the
following.
• Dedicated baud rate generator (reload counter)
• Input external clock to the baud rate generator (reload counter)
■ UART Baud Rate Selection
You can select either of the following two different baud rates.
● Baud rate obtained by dividing the internal clock in the dedicated baud rate generator (reload counter)
Two internal reload counters are provided and are used for the send and receive serial clocks respectively.
You can select a baud rate by setting a 15-bit reload value in the baud rate generator registers 1 and 0
(BGR1, BGR0).
The reload counter divides the internal clock frequency by the set value.
Select the internal clock (SMR:EXT=0) for the clock source setting.
● Baud rate obtained by dividing the external clock in the dedicated baud rate generator (reload counter)
The external clock is used as the clock source for the reload counter.
You can select a baud rate by setting a 15-bit reload value in the baud rate generator registers 1 and 0
(BGR1, BGR0).
The reload counter divides the external clock frequency by the set value.
To set the clock source, select the external clock and the use of the baud rate generator clock
(SMR:EXT=1).
This mode is provided for a use by dividing an oscillator of special frequency.
Notes:
• Set the external clock (EXT=1) when the reload counter is idle (BGR1/BGR0=0000H).
• If the external clock is set (EXT=1), at least two peripheral clock cycles are needed for "H" width
and "L" widths of the external clock.
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CHAPTER 15 Serial Interface
15.6 Dedicated Baud Rate Generator
15.6.1
MB91345 Series
Baud Rate Setting
Baud rate settings are shown. The calculation result for the serial clock frequency is
also shown.
■ Baud Rate Operation
The two 15-bit reload counters are set by baud rate generator registers 1 and 0 (BGR1 and BGR0).
The baud rate is calculated by the following equation.
(1) Reload value:
V = / b  1
V: Reload value
b: Baud rate
: Peripheral clock, external clock frequency
(2) Calculation example
The reload value is calculated by the following equation when setting 16 MHz for the peripheral
clock and 19200 bps for the baud rate.
Reload value:
V = (16  1000000) / 19200  1 = 832
Therefore, the baud rate is:
b = (16  1000000) / (832 + 1) = 19208 bps
(3) Error of baud rate
Error of baud rate is obtained by the following equation.
Error (%) = (Calculated value  Target value) / Target value  100
(Example) When setting peripheral clock 20 MHz and baud rate 153600 bps
Reload value = (20  1000000) / 153600  1 = 129
Baud rate (Calculated value) = (20  1000000) / (129 + 1) = 153846 (bps)
Error (%) = (153846  153600) / 153600  100 = 0.16 (%)
Notes:
• Setting a reload value of "0" stops the reload counter.
• If the reload value is an even number, the "L" width for the reception serial clock will be longer
than the "H" width by 1 cycle of the peripheral clock. If the value is an odd number, the "H" and "L"
widths for the serial clock will be the same.
• Set 4 or more reload values. However, the data might not be received normally due to the
deviation of the baud rate and the setting of the reload value.
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CHAPTER 15 Serial Interface
15.6 Dedicated Baud Rate Generator
MB91345 Series
■ The Reload Value and Baud Rate for Each Peripheral Clock Frequency
Table 15.6-1 Reload Value and Baud Rate
Baud rate
(bps)
8 MHz
1 0 MHz
16 MHz
20 MHz
24 MHz
32 MHz
Va lue
ERR
Val ue
ER R
Value
ERR
Va lue
ER R
Val ue
ERR
Val ue
ERR
4M





0
4
0
5
0
7
0
2.5M



0








2M

0
4
0
7
0
9
0
11
0
15
0
1M
7
0
9
0
15
0
19
0
23
0
31
0
5 0 0 0 00
15
0
19
0
31
0
39
0
47
0
63
0
4 6 0 8 00








51
-0.16


2 5 0 0 00
31
0
39
0
63
0
79
0
95
0
127
0
2 3 0 4 00








1 03
-0.16


1 5 3 6 00
51
-0.16
64
- 0. 1 6
103
-0.16
129
- 0. 1 6
1 55
-0.16
20 7
-0 . 1 6
1 2 5 0 00
63
0
79
0
127
0
159
0
191
0
255
0
115200
68
- 0.64
86
0.22
138
0.08
173
0.22
207
- 0.16
277
0.08
7 6 8 00
103
-0.16
12 9
- 0. 1 6
207
-0.16
259
- 0. 1 6
3 11
-0.16
41 6
0.08
57600
138
0. 08
173
0.22
277
0.08
346
-0.16
416
0.08
555
0.08
38400
207
-0.16
259
-0.16
416
0.08
520
0.03
624
0
832
-0.04
2 8 8 00
277
0. 0 8
34 6
<0.01
554
-0.01
693
- 0. 0 6
8 32
-0.03
1 11 0
-0 . 0 1
19200
416
0. 08
520
0.03
832
-0.03
1041
0.03
1249
0
1666
0.02
10417
767
<0.01
959
<0.01
1535
<0.01
1919
<0.01
2303
< 0.01
3071
<0.01
9600
832
0. 04
1041
0.03
1666
0.02
2083
0.03
2499
0
3332
-0.01
7200
1110
< 0 . 01
13 8 8
<0.01
2221
<0.01
2777
<0.01
3332
< 0.01
4443
-0.01
4800
1666
0. 0 2
20 8 2
-0. 0 2
3332
<0.01
4166
<0.01
4999
0
6666
<0.01
2400
3332
< 0 . 01
41 6 6
<0.01
6666
<0.01
8332
<0.01
9999
0
13332
<-0.01
1200
6666
<0.01
8334
0.02
13332
<0.01
16666
<0.01
19999
0
26666
<0.01
600
13332
< 0 . 01
1 66 6 6
<0.01
26666
<0.01






300
26666
26666
<0.01









Notes:
• Value: The setting value of the BGR1/0 registers (decimal)
• ERR: The error in the baud rate (%)
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CHAPTER 15 Serial Interface
15.6 Dedicated Baud Rate Generator
MB91345 Series
■ Allowable Baud Rate Range in Receive
It is shown next how much deviation of the baud rate for destination is allowed in a reception.
Use a formula shown below for the deviation of the baud rate in receive. Set the deviation within the
allowable deviation range.
Figure 15.6-1 Allowable Baud Rate Range in Receive
Sampling
Transfer rate
of UART
Start
bit 0
bit 1
bit 7
Parity
Stop
FL
1 data frame (11 x FL)
Transfer rate
of minimum
capacitance
Start
bit 0
bit 1
bit 7
Parity
Stop
FLmin
Transfer rate
of maximum
capacitance
bit 0
Start
bit 1
bit 7
Parity
Stop
FLmax
As shown in the figure, the counter set in the BGR1/BGR0 registers decides the sampling timing of receive
data after the start bit detection. If you can catch the final data (stop bit) in this sampling timing, the
reception will be successfully processed.
It theoretically goes like this, if applied to the 11-bit reception:
Suppose that a margin of the sampling timing is the same as 2 clocks of the peripheral clock (), the
minimum allowable transfer rate (FLmin) will be calculated as follows:
FLmin = (11bit × (V+1)  (V+1)/2 + 3)/ = (21V+27)/2 (s)
V: reload value,  : peripheral clock
Therefore, the maximum baud rate (BGmax) receivable for the destination will be like this:
BGmax = 11/FLmin = 22/(21V+27) (bps)
V: reload value,  : peripheral clock
Similarly, the maximum allowable transfer rate (FLmax) will be calculated as follows:
FLmax = (11bit × (V+1) + (V+1)/2  3)/ = (23V+17)/2 (s)
V: reload value,  : peripheral clock
Therefore, the minimum baud rate (BGmin) receivable for the destination will be like this:
BGmin = 11/FLmax = 22/(23V+17) (bps)
V: reload value,  : peripheral clock
The allowable baud rate error between UART and the destination is calculated using the formula for the
minimum and the maximum baud rate value. The result is shown below.
The reload value (V)
450
Allowable maximum baud
rate error
Allowable minimum baud
rate error
3
0%
0
10
+2.98%
-2.81%
50
+4.37%
-4.02%
100
+4.56%
-4.18%
200
+4.66%
-4.26%
32767
+4.76%
-4.35%
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CHAPTER 15 Serial Interface
15.6 Dedicated Baud Rate Generator
MB91345 Series
Note:
The reception accuracy depends on the number of bits per frame, the peripheral clock, and the
reload value. As the peripheral clock and divide ratio get higher value, the accuracy will be higher.
■ External Clock
When "1" is written to the EXT bit of the baud rate generator register (BGR), the baud rate generator
divides the external clock.
Note:
The external clock signal synchronizes with the internal clock by UART. Therefore, if the external
clock is not synchronizable, the operation will be unstable.
■ Function of the Reload Counter
A pair of the transmission and reception reload counters serves as the dedicated baud rate generator. The
block consists of a 15-bit register for reload values; it generates the transmission/reception clock signal
from the external or internal clock.
■ Start Counting
Once the reload value is written to the baud rate generator registers (BGR1, BGR0), the reload counter
starts to count.
■ Re-start
The reload counter will restart in the following conditions.
● Both send and receive reload counters
Programmable reset (SCR:UPCL bit)
● Reception reload counter
Falling edge of start bit detected in asynchronous mode
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CHAPTER 15 Serial Interface
15.7 Setting Procedure and Program Flow of Operation Mode 0
(In Asynchronous Normal Mode)
15.7
MB91345 Series
Setting Procedure and Program Flow of Operation Mode 0
(In Asynchronous Normal Mode)
For the operation mode 0, you can use the asynchronous serial duplex transmission.
■ Inter-CPU Connection
The duplex transmission is selected in the operation mode 0 (normal mode). As shown in Figure 15.7-1, 2
CPUs are mutually connected.
Figure 15.7-1 Example of Duplex Transmission Connection in UART Operation Mode 0
SOT
SOT
SIN
SIN
CPU-1 (Master)
CPU-2 (Slave)
■ Flowchart
● FIFO unused
Figure 15.7-2 Example of Duplex Transmission Flowchart (FIFO Unused)
(Transmission side)
(Reception side)
Start
Start
Operation mode setting
(setting to mode 0)
Operation mode setting
(matching to
transmission side)
Setting 1-byte data to
TDR to transmit
Data
transmission
NO
RDRF=1
YES
NO
RDRF=1
YES
Reception data read
and process
452
Data
transmission
(ANS)
Reception data read
and processing
1-byte data
transmission
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 15 Serial Interface
15.7 Setting Procedure and Program Flow of Operation Mode 0 (In
Asynchronous Normal Mode)
MB91345 Series
● FIFO used
Figure 15.7-3 Example of Duplex Transmission Flowchart (FIFO Used)
(Transmission side)
(Reception side)
Start
Start
Operation mode setting
(setting to mode 0)
Operation mode setting
(setting to mode 0)
· Transmission/reception
FIFO enable
· FBYTE setting
Setting N byte to transmission
FIFO
· Transmission/reception
FIFO enable
· FBYTE setting
Data
transmission
NO
RDRF=1
YES
Read and operate based on
the FBYTE setting value
Writing "0" to FDRQ bit
NO
Data reply
RDRF=1
Setting N byte to transmission
FIFO
YES
Read and operate based on
the FBYTE setting value
CM71-10132-3E
Writing "0" to FDRQ bit
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CHAPTER 15 Serial Interface
15.8 Setting Procedure and Program Flow of Operation Mode 1
(In Asynchronous Multiprocessor Mode)
15.8
MB91345 Series
Setting Procedure and Program Flow of Operation Mode 1
(In Asynchronous Multiprocessor Mode)
For the operation mode1 (multiprocessor mode), you can use the communication with
master/slave connections of multiple CPUs. It is usable as master/slave.
■ Inter-CPU Connection
As shown in the figure, connecting a master CPU and multiple slave CPUs with 2 common
communication lines makes the communication system in master/slave type communication. The UART
can be used with either the master or slave.
Figure 15.8-1 Connection Example for UART Master-slave Communications
SOT
SIN
Master CPU
STO
SIN
STO
Slave CPU #0
SIN
Slave CPU #1
■ Function Selection
Select the operation mode and the data transfer method in master/slave type communication as shown in
Table 15.8-1.
Table 15.8-1 Selection of Master/Slave Type Communication Function
Operation mode
Data
Master CPU
Address
Transmit or
Reception
Data Transmit
or Reception
Parity
Stop bit
Bit direction
None
1-bit or 2-bit
LSB or
MSB first
Slave CPU
Mode 1 (AD bit Mode 1 (AD bit
transmit)
Reception)
AD = 1
+
7-bit or 8-bit
address
AD = 0
+
7-bit or 8-bit
data
Note:
Transmit and reception data (RDR/TDR) must be accessed in word in the operation mode 1.
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CM71-10132-3E
MB91345 Series
CHAPTER 15 Serial Interface
15.8 Setting Procedure and Program Flow of Operation Mode 1 (In
Asynchronous Multiprocessor Mode)
● Communication procedure
Master/slave communication is started by the master CPU by transmitting address data.The address data,
having an D8 bit as "1", locates the slave CPU as the destination. Each slave CPU determines the address
data in program, and communicates (typically data) with the master CPU if the data matches the specified
address.
Figure 15.8-2 and Figure 15.8-3 show the flowchart for master/slave type communication (multi processor
mode).
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CHAPTER 15 Serial Interface
15.8 Setting Procedure and Program Flow of Operation Mode 1
(In Asynchronous Multiprocessor Mode)
MB91345 Series
■ Flowchart
● FIFO Unused
Figure 15.8-2 Example of Flowchart for Master/Slave Type Communication (FIFO Unused)
(Master CPU)
(Slave CPU)
Start
Start
Operation mode setting
(setting to mode 1)
Operation mode setting
(setting to mode 1)
Setting SIN pin to serial
data input
Setting SOT pin to serial
data output
Setting SIN pin to serial
data input
Setting SOT pin to serial
data output
7 or 8 data bit setting
1 or 2 stop bit setting
7 or 8 data bit setting
1 or 2 stop bit setting
Setting "1" to D8 bit
Transmission/reception
operation enable
Transmission/reception
operation enable
Reception byte
NO
Transmission of slave
address
D8 bit = 1
YES
NO
Setting "0" to D8 bit
Slave address is
matched.
YES
Communication with slave
CPU
Is communication
completed?
Communication with
master CPU
NO
Is communication
completed?
YES
YES
Communication
with other slave
CPU
NO
NO
YES
Transmission/reception
operation disable
End
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CM71-10132-3E
CHAPTER 15 Serial Interface
15.8 Setting Procedure and Program Flow of Operation Mode 1 (In
Asynchronous Multiprocessor Mode)
MB91345 Series
● FIFO Used
Figure 15.8-3 Example of Flowchart for Master/Slave Type Communication (FIFO used)
(Master CPU)
(Slave CPU)
Start
Start
Operation mode setting
(setting to mode 1)
Operation mode setting
(setting to mode 1)
· Transmission/reception
FIFO enable
· FBYTE setting
Transmission/reception
FIFO enable
Setting "1" to AD bit
Setting slave address to
transmission FIFO and
writing "0" to FDRQ bit
Setting to FBYTE=1
Slave address
transmission
RDRF=1
NO
YES
AD=1 &
slave address is
matched.
Setting "0" to AD bit
NO
YES
Setting N byte to transmission/ Data transmission
reception FIFO and
writing "0" to FDRQ bit
Setting to FBYTE=N
Reception
FIFO full
Setting "0" to D8 bit
NO
YES
NO
Read and operate based on
the FBYTE setting value
RDRF=1
YES
Data transmission
Read and operate based on
the FBYTE setting value
CM71-10132-3E
Setting N byte to transmission
FIFO and writing "0" to
FDRQ bit
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CHAPTER 15 Serial Interface
15.9 Notes on UART Mode
15.9
MB91345 Series
Notes on UART Mode
The notes for when you use the UART mode are shown below.
• FIFO cannot be used for requesting DMA transfer with a channel with FIFO. Please set as FIFO
operation disable.
• To request a DMA transfer request, set the block size of DMA to one time.
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CM71-10132-3E
CHAPTER 16
CSIO (Clock Synchronous
Serial Interface)
This chapter describes a UART function of the multi
function serial interface functions, which is supported
on operation mode 2.
16.1 Overview of CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
16.3 CSIO (Clock Synchronous Serial Interface) Interrupts
16.4 Operation of CSIO (Clock Synchronous Serial Interface)
16.5 Dedicated Baud Rate Generator
16.6 Setting Procedure and Program Flow of CSIO (Clock Synchronous
Serial Interface)
16.7 Notes on CSIO Mode
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.1 Overview of CSIO (Clock Synchronous Serial Interface)
16.1
MB91345 Series
Overview of CSIO (Clock Synchronous Serial Interface)
CSIO (clock synchronous serial interface) is a generic serial data communication
interface to perform synchronous communication with external device. (SPI supported)
In addition, it has the transmit or reception (up to 16-byte) FIFOs.
■ Function of CSIO (Clock Synchronous Serial Interface)
Item
1
Data buffer
2
Transfer method
3
Baud rate
4
Data Length
5
Detection of
reception error
6
Interrupt request
7
Synchronous mode
8
Pin access
9
FIFO option
Function
• Full-duplex double buffer (when FIFO is not used)
• Transmit/receive FIFO (maximum 16 bytes each) * (when FIFO is used)
• Clock synchronization (without start bit/stop bit)
• Master/slave function
• SPI supported (for both master and slave)
• Dedicated baud rate generator (configured from the 15-bit reload counter, for the master
operation)
• Input available from the external clock (for the slave operation)
Possible to change to 5 bits to 9 bits
Overrun error
•
•
•
•
Reception interrupt (reception completed, overrun error)
Transmit interrupt (transmit data empty, transmit bus idle)
Transmit FIFO interrupt (when the transmit FIFO is empty)
Extended Intelligent I/O Services (EI2OS) and the DMA transfer support function
Master or slave function
Serial data output pin can be set to "1".
• Transmit/receive FIFO (maximum capacity: transmit FIFO 16 bytes, receive FIFO 16
bytes) *
• Transmit FIFO and Receive FIFO can be selected.
• Transmit data can be resent.
• Receive FIFO interrupt timing can be changed by software
• Independent and support FIFO reset.
* : ch.0 and ch.1 have FIFO. (Transmit and reception are 16 bytes each.)
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
MB91345 Series
16.2
CSIO (Clock Synchronous Serial Interface) Registers
This section lists the CSIO (clock synchronous serial interface) registers.
■ List of the CSIO (Clock Synchronous Serial Interface) Registers
Figure 16.2-1 List of the CSIO (Clock Synchronous Serial Interface) Registers
Address
bit15
bit8
CSIO 0000X0H 0000X1H
SCR (Serial Control Register)
0000X2H 0000X3H
SSR (Serial Status Register)
RDR1/TDR1 (Transmit and reception
data register 1)
BGR1 (Baud rate Generator Register 1)
0000X4H 0000X5H
FIFO
0000X6H
0000X8H
0000Y0H
0000Y2H
bit7
0000X7H
0000X9H
0000Y1H
0000Y3H

FCR1 (FIFO control register 1)
FBYTE2 (FIFO2 byte register)
bit0
SMR (Serial Mode Register)
ESCR (Extended Communication
Control Register)
RDR0/TDR0 (Transmit and reception
data register 0)
BGR0 (Baud rate Generator Register 0)

FCR0 (FIFO control register 0)
FBYTE1 (FIFO1 byte register)
(X=06,07,08,09,0A,0B,1C,1D,1E,1F, Y=6,7)
Table 16.2-1 Bit of Allocation CSIO (Clock Synchronous Serial Interface)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
SCR0 to SCRA/
SMR0 to SMRA
UPCL
MS
SPI
RIE
TIE
TBIE
RXE
TXE
MD2
MD1
MD0
-
SSR0 to SSRA/
ESCR0 to ESCRA
REC
-
-
-
ORE
RDRF TDRE
TBI
SOP
-
-
-
-
D8
D7
D6
D5
D4
B8
B7
B6
B5
B4
TDR0 to TDRA
(RDR0 to RDRA)
-
BGR01/BGR00
-
B14
B13
B12
FCR01/FCR00
FBYTE02/
FBYTE01
B11
B10
B9
Reserved Reserved
FD15
CM71-10132-3E
FD14
FD13
bit3
bit2
bit1
bit0
SCKE
SOE
L2
L1
L0
D3
D2
D1
D0
B3
B2
B1
B0
SCINV BDS
-
FLSTE FRIIE FDRQ
FTIE
FSEL
-
FLST
FLD
FSET
FCL2
FCL1
FE2
FE1
FD12
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
FD11
FD10
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
16.2.1
MB91345 Series
Serial Control Register (SCR0 to SCRA)
Serial control register (SCR0 to SCRA) enables or disables the transmit or reception
interrupts, the transmit idle interrupt, the transmit or reception operations. It also
enables to set the connection to SPI and reset CSIO.
■ Serial Control Register (SCR0 to SCRA)
Figure 16.2-2 shows the bit configuration of serial control register (SCR0 to SCRA), and Table 16.2-2
shows function of each bit.
Figure 16.2-2 Bit Configuration of Serial Control Register (SCR0 to SCRA)
bit15 bit14 bit13 bit12 bit11 bit10 bit9
SCR
Address
UPCL
MS
SPI
RIE
TIE
TBIE
RXE
ch.0 000060H R/W R/W R/W R/W R/W R/W R/W
ch.1 000070H
ch.2 000080H
ch.3 000090H
ch.4 0000A0H
ch.5 0000B0H
ch.6 0001B0H
ch.7 0001C0H
ch.8 0001D0H
ch.9 0001E0H
ch.A 0001F0H
bit8
bit7
bit0
TXE
(SMR)
462
: Readable/writable
: Initial value
00000000B
R/W
TXE
0
1
Transmission enable bit
Disable reception
Enable reception
RXE
0
1
Reception enable bit
Disable reception.
Enable reception.
TBIE
0
1
Transmit bus idle interrupt enable bit
Disable transmit bus idle interrupt
Enable transmit bus idle interrupt
TIE
0
1
Send interrupt enable bit
Disable transmission interrupts.
Transmission Interrupt enable
RIE
0
1
Receive interrupt enable bit
Reception Interrupt disable
Reception Interrupt enable
SPI
0
1
SPI support bit
Normal synchronization transfer
SPI support
MS
0
1
Master-slave function selection bit
Master mode
Slave mode
UPCL
R/W
Initial value
0
1
Programmable clear bit
Write
Read
No effect
Always read "0".
Programmable clear
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CM71-10132-3E
MB91345 Series
CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
Table 16.2-2 Functional Description of Each Bit in Serial Control Register (SCR0 to SCRA)
Bit name
Function
bit15
UPCL:
The programmable
clear bit.
This bit initializes the inner status of CSIO.
• When set to "1":
- CSIO will directly be reset (software reset). However, the setting of register
is retained. In this case, the transmit or reception operation will be
disconnected immediately.
- The baud rate generator reloads the setting value in the BGR1/BGR0
register, and restarts it.
- All transmit and reception interrupt factors (TDRE, TBI, RDRF, and ORE)
are initialized.
• When set to "0": Operation is not affected.
When reading, always read "0".
Notes:
• Perform a programmable clear after set to the prohibition of interrupt.
• When using FIFO, disable FIFO (FE2, FE1=0) before performing a
programmable clear.
bit14
MS:
The master/slave
function selection
bit.
This bit specifies whether the master or slave mode should be used.
• When set to "0": The mode will be master.
• When set to "1": The mode will be slave.
Note:
When the slave mode is selected, the external clock is directly input if
SMR:SCKE=0.
bit13
SPI:
The SPI support bit.
This is a bit to support the SPI-enabled communication.
• When set to "0": Normal synchronization communication is executed.
• When set to "1": Support SPI.
bit12
RIE:
The reception
interrupt enable bit.
• This bit enables or disables the reception interrupt request output to the CPU.
• If the RIE bit and reception data flag bit (RDRF) are "1", or if one of the error
flag bits (OREs) is "1", the reception interrupt request will be output.
bit11
TIE:
The transmit
interrupt enable bit.
• This bit enables or disables the transmit interrupt request output to the CPU.
• When the TDRE and TIE bits are both "1", a transmission interrupt request is
output.
bit10
TBIE:
The transmit bus idle
interrupt enable bit.
• This bit enables or disables the transmit bus idle interrupt request output to the
CPU.
• When TBIE bit and TBI bit are "1", a transmission bus idle interrupt request is
output.
RXE:
The reception
operation enable bit.
This bit enables or disables the reception operation of CSIO.
• When set to "0": Data frame reception is disabled.
• When set to "1": Data frame reception is enabled.
Note:
If reception operation is prohibited (RXE=0) during reception, reception
operation stops immediately.
TXE:
The transmit
operation enable bit.
This bit enables or disables the transmit operation of CSIO.
• When set to "0": Data frame sending is disabled.
• When set to "1": Data frame sending is enabled.
Note:
If transmit operation is prohibited (TXE=0) during transmit, transmit
operation stops immediately.
bit9
bit8
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
16.2.2
MB91345 Series
Serial Mode Register (SMR0 to SMRA)
Serial Mode Register (SMR0 to SMRA) sets the operation mode, transfer direction, data
length, and serial clock inverse. It also enables or disables the output to the serial data
and the clock pin.
■ Serial Mode Register (SMR0 to SMRA)
Figure 16.2-3 shows the bit configuration of serial mode register (SMR0 to SMRA), and Table 16.2-3
shows function of each bit.
Figure 16.2-3 Bit Configuration of Serial Mode Register (SMR0 to SMRA)
bit15
SMR
Address
ch.0 000061H
ch.1 000071H
ch.2 000081H
ch.3 000091H
ch.4 0000A1H
ch.5 0000B1H
ch.6 0001B1H
ch.7 0001C1H
ch.8 0001D1H
ch.9 0001E1H
ch.A 0001F1H
bit8
(SCR)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
MD2
MD1
MD0

SCINV
BDS
SCKE
SOE
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SOE
0
1
Serial-data output enable bit
SO output disable
SO output enable
SCKE
1
Serial clock output enable bit
SCK output disable
or
SCK input enable
SCK output enable
BDS
0
1
Transfer direction selection bit
LSB first (transfer from LSB)
MSB first (transfer from MSB)
SCINV
0
1
Serial clock inverse bit
Mark level "H" format
Mark level "L" format
0
Unused bit
Read value is undefined. Writing has no effect.
R/W

: Readable/writable
: Unused bit
: Initial value
MD2
MD1
MD0
0
0
0
0
0
1
0
1
1
0
0
0
Operation mode setting bits
Operation mode 0
(asynchronous normal mode)
operation mode 1
(asynchronous multiprocessor mode)
operation mode 2 (clock synchronous mode)
operation mode 4 (I2C mode)
Note: This chapter explains the register and the operation in operation mode 2.
464
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CM71-10132-3E
MB91345 Series
CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
Table 16.2-3 Functional Description of Each Bit in Serial Mode Register (SMR0 to SMRA)
Bit name
Function
bit7
to
bit5
MD2, MD1, MD0:
The operation mode
set bit.
This bit sets the operation mode.
"000B": Set to the operation mode 0 (asynchronous normal mode).
"001B": Set to the operation mode 1 (asynchronous multiprocessor mode).
"010B": Set to the operation mode 2 (clock synchronous mode).
"100B": Set to the operation mode 4 (I2C mode).
This chapter describes the registers and operations for the operation mode 2 (clock
synchronous mode).
Notes:
• The setting other than the above is prohibited.
• If you switch the operation mode, perform the programmable clear (SCR:UPCL=1)
before changing the mode.
• Specify each register after the operation mode is set.
bit4
Unused bit
Read: The value is undefined.
Write: No effect.
bit3
SCINV:
The serial clock
inverse bit.
This bit inverts the serial clock format.
If set to "0":
• The mark level of the serial clock output will be "H".
• The transmit data outputs synchronizing with the falling edge of serial clock in
normal transfer, and synchronizing with the rising edge of serial clock in SPI transfer.
• The reception data will be sampled on the rising edge of the serial clock for the
normal transfer, or on the falling edge of the serial clock for the SPI transfer.
If set to "1":
• The mark level of the serial clock output will be "L".
• The transmit data outputs synchronizing with the rising edge of serial clock in normal
transfer, and synchronizing with the falling edge of serial clock in SPI transfer.
• The reception data will be sampled on the falling edge of the serial clock for the
normal transfer, or on the rising edge of the serial clock for the SPI transfer.
Note:
This bit should be set when transmit and receive are prohibited (TXE=RXE=0).
bit2
BDS:
The transfer direction
selection bit.
This bit specifies whether the transfer serial data should be transferred from the lowest
bit (LSB first, BDS=0) or the highest bit (MSB first, BDS=1).
Note:
This bit should be set when transmit and receive are prohibited (TXE=RXE=0).
bit1
SCKE:
The serial clock
output enable bit.
This bit controls the I/O port for the serial clock.
If set to "0": It will be the SCK "H" output or the SCK input will be enabled.
If used as the SCK input, set the generic I/O port to the input port.
If set to "1": The SCK output will be enabled.
bit0
SOE:
The serial data output
enable bit.
This bit enables or disables the output of the serial data.
If set to "0": It will be the SO "H" output.
If set to "1": The SO output will be enabled.
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
MB91345 Series
Note:
Set the operation mode first, because the other registers are initialized when the operation mode is
changed. However, if you write SCR and SMR simultaneously using 16-bit writing, the writing is
applied to SCR.
466
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
MB91345 Series
16.2.3
Serial Status Register (SSR0 to SSRA)
Serial Status Register (SSR0 to SSRA) checks the transmit or reception status. It also
checks and clears the reception error flag.
■ Serial Status Register
Figure 16.2-4 shows the bit configuration of serial status register (SSR0 to SSRA), and Table 16.2-4 shows
function of each bit.
Figure 16.2-4 Bit Configuration of Serial Status Register (SSR0 to SSRA)
bit15 bit14 bit13 bit12 bit11 bit10
SSR
Address
REC



ORE RDRF
ch.0 000062H R/W



R
R
ch.1 000072H
ch.2 000082H
ch.3 000092H
ch.4 0000A2H
ch.5 0000B2H
ch.6 0001B2H
ch.7 0001C2H
ch.8 0001D2H
ch.9 0001E2H
ch.A 0001F2H
bit9
bit8
TDRE
TBI
R
R
bit7
bit0
(ESCR)
Initial value
0-000011B
TBI
0
1
Transmit bus idle flag bit
During transfer
No transfer operation
TDRE
0
1
Transmission data empty flag bit
Data exists in the transmit data register (TDR).
The transmit data register is empty.
RDRF
0
1
Receive data full flag bit
The reception data register (RDR) is empty.
Data exists in the reception data register (RDR).
ORE
0
1
Overrun error flag bit
No overrun error
Overrun error
Unused bit
Read value is undefined. Writing has no effect.
REC
0
1
R/W
R

Receive error flag clear bit
Write
Read
No effect
Always read "0".
Clear reception error
flags (FRE and ORE)
: Readable/writable
: Read only
: Unused bit
: Initial value
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
MB91345 Series
Table 16.2-4 Functional Description of Each Bit in Serial Status Register (SSR0 to SSRA)
Bit name
bit15
REC:
Reception error flag
clear bit
bit14
to
bit12
Unused bit
bit11
bit10
bit9
bit8
468
Function
This bit clears the ORE flag in the serial status register (SSR).
• When set to writing "1": Clear the error flag.
• When set to writing "0": No affect.
When read: "0" always read.
Read: The value is undefined.
Write: No effect.
ORE:
The overrun error
flag bit
• This bit will be set to "1" if the overrun error occurs when receiving, and cleared if
"1" is written into the REC bit in Serial Status Register (SSR).
• When the ORE and RIE bits are both "1", a reception interrupt request is output.
• The data in the receive data register (RDR) is not valid when this bit is set.
• If this flag is set when using the reception FIFO, the enable bit for the reception
FIFO will be cleared, and the reception data will not be contained in the reception
FIFO.
RDRF:
The reception data
full flag bit.
• This flag indicates the status of Reception Data Register (RDR).
• The bit is set to 1 when the RDR loads received data. The bit is cleared to 0 when the
receive data register is read.
• When the RDRF and RIE bits are both "1", a reception interrupt request is output.
• When using the reception FIFO, RDRF will be set to "1" if the FIFO receives the
specified number of data.
• When using the reception FIFO, RDRF will be set to "1" if the reception FIFO keeps
the data without receiving the specified number of data while the reception idle
status continues for eight or more clocks with the baud rate clock.
When having read RDR during the eight clocks count, the counter is reset to "0", and
then it counts another eight clocks.
• When using the reception FIFO, it will be cleared to "0" if the reception FIFO is
empty.
TDRE:
The transmit data
empty flag bit.
• This bit indicates the status of transmit data register (TDR).
• Goes to "0" when send data written to TDR to indicate that TDR contains valid data.
When the data is loaded into the transmit shift register and the communication is
started, it will be "1" indicating that no valid data exists in TDR.
• When the TDRE and TIE bits are both "1", a transmission interrupt request is output.
• If the UPCL bit in serial control register (SCR) is set to "1", the TDRE bit is "1".
• As for set/reset timing of the TDRE bit when using transmit FIFO, see "16.3.4
Timing when the Interrupt Occurs and the Flag Should be Set during the Use of the
Transmit FIFO".
TBI:
The transmit bus
idle flag bit.
• This bit indicates that CSIO is not performing the transmit operation.
• If the transmit data is written to transmit data register (TDR), this bit will be "0".
• If transmit data register (TDR) is empty (TDRE=1) and no transmit operation is
performed, this bit will be "1".
• If the UPCL bit in serial control register (SCR) is set to "1", the TDRE bit is "1".
• If this bit is "1" and the transmit bus idle interrupt is enabled (SCR:TBIE=1), the
transmit interrupt request will be output.
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
MB91345 Series
16.2.4
Extended Communication Control Register (ESCR0 to
ESCRA)
Extended Communication Control Register (ESCR0 to ESCRA) sets the transmit or
reception data lengths and fixes the serial output to "H".
■ Bit Configuration of Extended Communication Control Register (ESCR0 to ESCRA)
Figure 16.2-5 shows the bit configuration of extended communication control register (ESCR0 to ESCRA),
and Table 16.2-5 shows function of each bit.
Figure 16.2-5 Bit Configuration of Extended Communication Control Register (ESCR0 to ESCRA)
bit15
ESCR
Address
ch.0 000063H
ch.1 000073H
ch.2 000083H
ch.3 000093H
ch.4 0000A3H
ch.5 0000B3H
ch.6 0001B3H
ch.7 0001C3H
ch.8 0001D3H
ch.9 0001E3H
ch.A 0001F3H
bit8

bit7
bit6
bit5
bit4
bit3
bit2
SOP




L2
R/W




R/W
L2
0
0
0
0
1
L1
0
0
1
1
0
L0
0
1
0
1
0
bit0
Initial value
L1
L0
0----000B
R/W
R/W
bit1
Data-length select bit
8-bit length
5-bit length
6-bit length
7-bit length
9-bit length
Unused bit
Read value is undefined. Writing has no effect.
SOP
R/W

CM71-10132-3E
: Readable/writable
: Unused bit
: Initial value
0
1
Serial output pin set bit
Write
Read
No effect
Always read "0".
Set the SOT pin to "H"
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
MB91345 Series
Table 16.2-5 Functional Description of Each Bit in Extended Communication Control Register
(ESCR0 to ESCRA)
Bit name
bit7
SOP:
The serial output pin set bit.
bit6
to
bit3
Unused bit
bit2
to
bit0
470
L2, L1, L0:
The data length selection bit.
Function
• This bits sets the serial output pin to "H".
When "1" is written to this bit, SOT pin is set to "H". You do not need to
write "0" to this bit after that.
• Read: "0" is always read.
Note:
• Do not set this bit during serial data transmit.
• The value of this bit is valid only when the TXE bits in the serial control
registers (SCR0 to SCRA) are "0".
Read: The value is undefined.
Write: No effect.
This bit specifies the data length of the transmit or reception data.
• When set to "000B": the data length is set to 8-bit.
• When set to "001B": the data length is set to 5-bit.
• When set to "010B": the data length is set to 6-bit.
• When set to "011B": the data length is set to 7-bit.
• When set to "100B": the data length is set to 9-bit.
Note:
The setting other than the above is prohibited.
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
MB91345 Series
16.2.5
Receive Data Register (RDR0 to RDRA), Transmit Data
Register (TDR0 to TDRA)
The receive data and transmit data registers are located at the same address. It works
as a reception data register when read, and it works as a transmit data register when
written.
■ Receive Data Register (RDR0 to RDRA)
Figure 16.2-6 shows the bit configuration of receive data register (RDR0 to RDRA).
Figure 16.2-6 Bit Configuration of Receive Data Register (RDR0 to RDRA)
bit15
RDR
Address:
ch.0 000064H
ch.1 000074H
ch.2 000084H
ch.3 000094H
ch.4 0000A4H
ch.5 0000B4H
ch.6 0001B4H
ch.7 0001C4H
ch.8 0001D4H
ch.9 0001E4H
ch.A 0001F4H
R/W
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D8
D7
D6
D5
D4
D3
D2
D1
D0
000000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
: Readable/writable
Reception Data Register (RDR0 to RDRA) is a 9-bit data buffer register to receive the serial data.
• The signal sent to the serial input pin (SIN pin) is converted via a shift register and saved in the receive
data register (RDR0 to RDRA).
• "0" is set from the higher bit toward the lower bit in order as follows, according to the data length.
Data length
D8
D7
D6
D5
D4
D3
D2
D1
D0
9-bit
X
X
X
X
X
X
X
X
X
8-bit
0
X
X
X
X
X
X
X
X
7-bit
0
0
X
X
X
X
X
X
X
6-bit
0
0
0
X
X
X
X
X
X
5-bit
0
0
0
0
X
X
X
X
X
(X is the receive data bit.)
• The receive data full flag bit (SSR:RDRF) is set to "1" when the receive data is stored in the receive data
register (RDR0 to RDRA). When receiving interrupts are enabled (SSR:RIE=1), receiving interrupt
requests are generated.
• Read the receive data register (RDR0 to RDRA) contents when the receive data full flag bit
(SSR:RDRF) is "1". Once the serial reception data register (RDR0 to RDRA) is read, the reception data
full flag bit (SSR:RDRF) is automatically cleared to "0".
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
MB91345 Series
• When a reception error occurred (SSR:ORE), the data of the reception data register (RDR0 to RDRA)
becomes invalid.
• RDR0 to RDRA is read by 16-bit access in case of the 9-bit length transfer.
Notes:
• When using the reception FIFO, RDRF will be set to "1" if the FIFO receives the specified number
of data.
• While the reception FIFO is being used, the RDRF is cleared to "0" when the reception FIFO
becomes empty.
• While the reception FIFO is being used, the enable bit of the reception FIFO is cleared and the
reception data is not stored in the reception FIFO when a reception error occurred (SSR:ORE is
"1").
■ Transmit Data Register (TDR0 to TDRA)
Figure 16.2-7 shows the bit configuration of transmit data register (TDR0 to TDRA).
Figure 16.2-7 Bit Configuration of Transmit Data Register (TDR0 to TDRA)
bit15
TDR
Address:
ch.0 000065H
ch.1 000075H
ch.2 000085H
ch.3 000095H
ch.4 0000A5H
ch.5 0000B5H
ch.6 0001B5H
ch.7 0001C5H
ch.8 0001D5H
ch.9 0001E5H
ch.A 0001F5H
R/W
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D8
D7
D6
D5
D4
D3
D2
D1
D0
000000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
: Readable/writable
Transmit data register (TDR0 to TDRA) is a 9-bit data buffer register to transmit the serial data.
• When the transmission data is written to the transmission data register (TDR0 to TDRA) while the
transmission operation is enabled (SCR:TXE=1), the transmission data is transferred to the transmission
shift register and converted into the serial data, then transmitted from the serial data output pin (SOT
pin).
• The invalid data is set from the higher bit toward the lower bit in order as follows, according to the data
length,
Data length
D8
D7
D6
D5
D4
D3
D2
D1
D0
9-bit
X
X
X
X
X
X
X
X
8-bit
Invalid
X
X
X
X
X
X
X
X
7-bit
Invalid
Invalid
X
X
X
X
X
X
X
6-bit
Invalid
Invalid
Invalid
X
X
X
X
X
X
5-bit
Invalid
Invalid
Invalid
Invalid
X
X
X
X
X
(X is the receive data bit.)
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
• The send data empty flag (SSR:TDRE) is cleared to "0" when send data is written to the send data
register (TDR0 to TDRA).
• After the transmission data is transferred to the transmission shift register and the transmission is
started, the transmission data empty flag (SSR:TDRE) is set to "1" when the transmission FIFO is
disabled or empty.
• If the transmit data empty flag (SSR:TDRE) is set to "1", the next sending data can be written in. When
sending interrupts are enabled, a sending interrupt is generated. You can use the send interrupt to write
the next send data. Only write the next data when the transmit data empty flag (SSR:TDRE) is "1".
• When the transmission data empty flag (SSR:TDRE) is set to "0" and the transmission FIFO is disabled
or full, the transmission data cannot be written to the transmission data register (TDR0 to TDRA).
• TDR0 to TDRA is written by 16-bit access in case of the 9-bit length transfer.
Notes:
• The transmission data register is a write-only register and the reception data register is a readonly register. Both of the registers are located in the same address, so the writing values and
reading values are different. Instructions, such as the INC/DEC instruction, which provide the
read-modify-write (RMW) instruction cannot be used.
• As for set timing of transmit data empty flag (SSR:TDRE) when using transmit FIFO, see "16.3.4
Timing when the Interrupt Occurs and the Flag Should be Set during the Use of the Transmit
FIFO".
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
16.2.6
MB91345 Series
Baud Rate Generator Registers 0/1 (BGR00 to BGRA0/
BGR01 to BGRA1)
The baud rate generator registers 0/1 (BGR00 to BGRA0/BGR01 to BGRA1) set the serial
clock divide ratio.
■ Bit Configuration of Baud Rate Generator Registers 0/1 (BGR00 to BGRA0/BGR01 to
BGRA1)
Figure 16.2-8 shows bit configuration of baud rate generator registers 0/1 (BGR00 to BGRA0/BGR01 to
BGRA1).
Figure 16.2-8 Bit Configuration of Baud Rate Generator Registers 0/1 (BGR00 to BGRA0/BGR01 to
BGRA1)
BGR00→BGRx0
(x = 0 to A)
Address
ch.0 000067H
ch.1 000077H
ch.2 000087H
ch.3 000097H
ch.4 0000A7H
ch.5 0000B7H
ch.6 0001B7H
ch.7 0001C7H
ch.8 0001D7H
ch.9 0001E7H
ch.A 0001F7H
BGR01→BGRx1
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
(x = 0 to A)
Address
00000000B

(BGR1)
(BGR0)
ch.0 000066H
00000000B
ch.1 000076H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

ch.2 000086H
ch.3 000096H
ch.4 0000A6H
ch.5 0000B6H
ch.6 0001B6H
ch.7 0001C6H
ch.8 0001D6H
ch.9 0001E6H
ch.A 0001F6H
BGR0
Baud Rate Generator Register 0
R/W : Readable/writable
:
Unused bit
Write
Read
Write into reload counter bit0 to bit7.
Read the setting value of BGR0.
BGR1
Write
Read
Baud Rate Generator Register 1
Write into reload counter bit8 to bit14.
Read the setting value of BGR1.
Unused bit
Read: The value is undefined.
Write : No effect
• Set the value to baud rate generator register 0/1 (BGR00 to BGRA0/BGR01 to BGRA1).
• BGR1 supports the upper bit and BGR0 supports the lower bit. It is possible to write the reload value
and to read the setting value of BGR0/BGR1.
• If the reload value is written into baud rate generator (BGR00 to BGRA0/BGR01 to BGRA1), the
reload counter starts counting.
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MB91345 Series
CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
Notes:
• Writing to the baud rate generator registers (BGR1, BGR0) should be done by 16-bit access.
• When the reload value is the even number, the "H" and "L" widths of the serial clock are as
follows depending on the SCINV bit setting. If the value is an odd number, the "H" and "L" widths
for the serial clock will be the same.
When SCINV=0, "H" width of the serial clock will increase by one cycle of the peripheral clock.
When SCINV=1, "L" width of the serial clock will increase by one cycle of the peripheral clock.
• Set "1" or more for the reload value. However, when these CSIOs are used as the master and
slave, the reload value of the master CSIO should be set to "3" or more.
• When the setting value of the baud rate generator registers (BGR1, BGR0) are changed, the new
value will be reloaded after the counter value gets to "0000H". Therefore, if the new value should
be applied immediately, the setting value of the BGR1/BGR0 must be changed before the CSIO
reset (UPCL) is performed.
• While the reception FIFO is being used, the baud rate should be set to the BGR1/BGR0 when the
reception FIFO idle detection enable bit (FCR1:FRIIE) is set to "1" and the operation is in the
slave mode.
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
16.2.7
MB91345 Series
FIFO Control Register 1 (FCR01, FCR11)
FIFO Control Register1 (FCR01, FCR11) sets the FIFO test, selects the transmit or
reception FIFOs, enables the transmit FIFO interrupt, and controls the interrupt flags.
■ Bit Configuration of FIFO Control Register 1 (FCR01, FCR11)
Figure 16.2-9 shows the bit configuration of FIFO control register 1 (FCR01, FCR11), and Table 16.2-6
shows function of each bit.
Figure 16.2-9 Bit Configuration of FIFO Control Register 1 (FCR01, FCR11)
FCRx1
(x = 1, 0)
Address
ch.0 00006AH
ch.1 00007AH
bit15 bit14 bit13 bit12 bit11 bit10
Reserved Reserved
R/W
R/W


FLSTE FRIIE FDRQ
R/W
R/W
R/W
bit9
bit8
FTIE
FSEL
R/W
R/W
bit7
bit0
Initial value
00000000B
(FCR0)
FSEL
0
1
FIFO selection bit
(Transmit FIFO:FIFO1, Receive FIFO:FIFO2)
(Transmit FIFO:FIFO2, Receive FIFO:FIFO1)
FTIE
0
1
Transmit FIFO interrupt enable bit
Disable FIFO transmission interrupts.
Transmission FIFO Interrupt enable
FDRQ
0
1
Transmit FIFO data request bit
No transmit FIFO data request
Transmit FIFO data request
FRIIE
0
1
Reception FIFO idle detection enable bit
Reception FIFO idle detection prohibited
Reception FIFO idle detection enabled
FLSTE
0
1
retransmit data lost detection enable bit
Data lost detection prohibited
Data lost detection enabled
Unused bit
Read value is undefined. Writing has no effect.
FTST
0
R/W

476
FIFO test bit
Be sure to set "0" to this bit.
: Readable/writable
: Unused bit
: Initial value
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
MB91345 Series
CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
Table 16.2-6 Functional Description of Each Bit in the FIFO Control Register 1 (FCR01, FCR11)
Bit name
Function
bit15,
bit14
Reserved bit
This bit is reserved bit.
Be sure to set "0" to this bit.
bit13
Unused bit
Read: The value is undefined.
Write: No effect.
bit12
FLSTE:
The re-transmission data
lost detection enable bit.
This bit enables the FLST bit detection.
If set to "0": FLST bit detection prohibited
If set to "1": FLST bit detection enabled
Note:
Set "1" to this bit after setting "1" to the FSET bit.
FRIIE:
The reception FIFO idle
detection enable bit.
This bit sets whether to detect the reception idle status longer than 8-bit time when
the reception FIFO has the valid data.
If the reception interrupt is enabled (SCR:RIE=1), the reception interrupt will occur
when the reception idle status is detected.
When set to "0": The reception idle status detection is disabled.
When set to "1": The reception idle status detection is enabled.
bit10
FDRQ:
The transmit FIFO data
request bit.
This is a bit to request the data of the transmit FIFO.
When this bit is set to "1", it indicates the transmission data is requested.
In this case, the transmission FIFO interrupt request is output if the transmission
FIFO interrupt is enabled (FTIE=1).
FDRQ setting conditions:
• FBYTE (for transmission)=0 (the transmission FIFO is empty)
• Reset of the transmission FIFO
FDRQ resetting conditions:
• Writing "0" to this bit.
• If transmit FIFO is full.
Notes:
• When FBYTE (for transmit)=0, writing "0" to this bit is prohibited.
• When this bit is "0", any change of the FSEL bit is prohibited.
• When this bit is set to "1", there is no influence on the operation.
• When having a read-modify-write (RMW) related instruction, "1" is read out.
bit9
FTIE:
The transmit FIFO interrupt
enable bit.
bit11
bit8
FSEL:
FIFO selection bit
CM71-10132-3E
This bit enables the interrupt of the transmit FIFO.
When this bit is set to "1", an interruption occurs if the FDRQ bit is "1".
Bit to select transmit and receive FIFO.
If set to "0": Allocate to transmit FIFO:FIFO1 and reception FIFO:FIFO2.
If set to "1": Allocate to transmit FIFO:FIFO2 and reception FIFO:FIFO1.
Notes:
• This bit is not cleared by FIFO reset (FCL2, FCL1=1).
• Before you change this bit, the FIFO operation (FE2, FE1=0), and
transmission/reception (TXE=RXE=0) should be disabled.
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
16.2.8
MB91345 Series
FIFO Control Register 0 (FCR00, FCR10)
The FIFO Control Register 0 (FCR00, FCR10) enables or disables the FIFO operation,
resets FIFO, saves the read pointer, and sets retransmit.
■ Bit Configuration of FIFO Control Register 0 (FCR00, FCR10)
Figure 16.2-10 shows the bit configuration of the FIFO control register 0 (FCR00, FCR10), Table 16.2-7
lists the function of each bit.
Figure 16.2-10 Bit Configuration of FIFO Control Register 0 (FCR00, FCR10)
FCRx0
(x = 1, 0)
Address
ch.0 00006BH
ch.1 00007BH
bit15
bit8
(FCR1)
bit1
bit0
Initial value

FLST FLD FSET FCL2 FCL1
FE2
FE1
-0000000B
( )
R/W
R/W
R/W
bit7
bit6
R/W
FIFO2 Operation Enable Bit
FIFO2 operation disabled
FIFO2 operation enabled
0
1
FSET
0
1
478
R/W
bit2
FE2
0
1
FCL2
: Readable/writable
: Unused bit
: Initial value
R/W
bit3
FIFO1 Operation Enable Bit
FIFO1 operation disabled
FIFO1 operation enabled
0
1

R/W
bit4
FE1
0
1
FCL1
R/W
bit5
FIFO1 reset bit
Write
Read
No effect
Always read "0".
FIFO1 Reset
FIFO2 reset bit
Write
Read
No effect
Always read "0".
FIFO2 Reset
FIFO pointer save bit
Write
Read
No save
Always read "0".
Execute save
FLD
0
1
FIFO pointer reload bit
No reload
Execute reload
FLST
0
1
FIFO retransmit data lost flag bit
No data lost
Data lost
Unused bit
"0" is always read at read operation.
"0" is always written at write operation.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
MB91345 Series
CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
Table 16.2-7 Functional Description of Each Bit in the FIFO Control Register 0 (FCR00, FCR10) (1 / 2)
Bit name
bit7
bit6
bit5
bit4
bit3
Function
Unused bit.
When read: "0" is always read.
When write: "0" is always written.
FLST:
The FIFO retransmit
data lost flag bit.
This bit indicates that the retransmit data of the transmit FIFO is lost.
FLST set condition:
Data is written to FIFO when the FLSTE bit of the FIFO control register 1 (FCR1) is "1"
and the write pointer of transmit FIFO and the read pointer saved by the FSET bit match.
FLST reset condition:
• FIFO reset (write "1" to FCL)
• Write "1" to the FSET bit
When "1" is set to this bit, data which the read pointer saved by the FSET bit indicates is
overwritten, and retransmission cannot be set by the FLD bit even if error occurs. When
you retransmit the data while this bit is set to "1", you must reset the FIFO, and write the
data to the FIFO again.
FLD:
The FIFO pointer
reload bit.
This bit reloads the data saved in the transmit FIFO by the FSET bit to the read pointer.
This bit is used to retransmit the data when a communication error occurs.
Once the retransmit setting is completed, this bit becomes "0".
Notes:
• Data is being reloaded to the read pointer while this bit is set to "1". Therefore, do
not write reset other than FIFO reset.
• Do not set this bit to "1" during FIFO enable status or the transmission.
• TIE bit and TBIE bit should be set to "0" before you write "1" in this bit. After
transmission FIFO is enabled, then set TIE bit and TBIE bit to "1".
FSET:
The FIFO pointer
save bit.
This is a bit to save the read pointer of the transmit FIFO.
If you save the read pointer before the transmission, you may retransmit as long as FLST
bit is set to "0" even if a communication error occurred.
When set to "1": Current read pointer value is saved.
When the bit is set to "0": No effect.
Note:
Set this bit to "1" while number of transmission bytes (FBYTE) indicates "0".
FCL2:
FIFO2 reset bit
This bit resets FIFO2.
When this bit is set to "1", the internal status of FIFO2 is initialized.
Only the FCR1:FLST bit is initialized. Other bits of the FCR1/FCR0 register are retained
as is.
Notes:
• Execute FIFO2 reset after disabling the transmission/reception operation.
• Set the transmission FIFO interrupt enable bit to "0" before the operation.
• Number of valid data for the FBYTE2 register is "0".
CM71-10132-3E
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
MB91345 Series
Table 16.2-7 Functional Description of Each Bit in the FIFO Control Register 0 (FCR00, FCR10) (2 / 2)
Bit name
bit2
bit1
bit0
480
Function
FCL1:
FIFO1 reset bit
This bit resets FIFO1.
When this bit is set to "1", the internal status of FIFO1 is initialized.
Only the FCR1:FLST bit is initialized. Other bits of the FCR1/FCR0 register are retained
as is.
Notes:
• Execute FIFO1 reset after disabling the transmission/reception operation.
• Set the transmission FIFO interrupt enable bit to "0" before the operation.
• Number of valid data for the FBYTE1 register is "0".
FE1:
The FIFO2
operation enable bit.
This bit enables or disables the FIFO2 operation.
• If FIFO2 is used, set this bit to "1".
• The transmission is started immediately if FIFO2 is set to the transmission FIFO
(FCR1:FSEL=1), the data exists in FIFO2 when writing "1" to this bit, and UART is
enabled for the transmission (TXE =1). Set the TIE and TBIE bits to "0" before
writing "1" to this bit, and then set the bits to "1".
• If this is selected as a reception FIFO by FSEL bit, this bit is cleared to "0" in case of
the reception error, and this bit cannot be set to "1" until the reception error is cleared.
• Set this bit to "1" or "0" when the transmission buffer is empty (TDRE=1) if this is
used in the transmission FIFO2, or when the reception buffer is empty (RDRF=0) if
this is used in the reception FIFO2.
• FIFO2 state is maintained even when FIFO2 is disabled.
FE1:
The FIFO1
operation enable bit.
This bit enables or disables the FIFO1 operation.
• If FIFO1 is used, set this bit to "1".
• The transmission is started immediately if FIFO1 is set to the transmission FIFO
(FCR1:FSEL=0), the data exists in FIFO1 when writing "1" to this bit, and UART is
enabled for the transmission (TXE =1). Set the TIE and TBIE bits to "0" before
writing "1" to this bit, and then set the bits to "1".
• If this is selected as a reception FIFO by FSEL bit, this bit is cleared to "0" in case of
the reception error, and this bit cannot be set to "1" until the reception error is cleared.
• Set this bit to "1" or "0" when the transmission buffer is empty (TDRE=1) if this is
used in the transmission FIFO, or when the reception buffer is empty (RDRF=0) if this
is used in the reception FIFO.
• FIFO1 state is maintained even when FIFO1 is disabled.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
MB91345 Series
16.2.9
FIFO Byte Register (FBYTE01, FBYTE02, FBYTE11,
FBYTE12)
The FIFO byte register (FBYTE01, FBYTE02, FBYTE11, FBYTE12) indicates the number
of the data available for FIFO.
■ Bit Configuration of FIFO Byte Register (FBYTE01, FBYTE02, FBYTE11, FBYTE12)
Figure 16.2-11 shows the bit configuration of the FIFO byte register (FBYTE01, FBYTE02, FBYTE11,
FBYTE12).
Figure 16.2-11 Bit Configuration of FIFO Byte Register (FBYTE01, FBYTE02, FBYTE11, FBYTE12)
FBYTE01
00006DH
FBYTE02
00006CH
FBYTE11
00007DH
FBYTE12
00007CH
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
bit7
bit6
bit5
bit4
(FBYTE2)
R/W
R/W
R/W
R/W
bit3
bit2
bit1
bit0
00000000B
00000000B
(FBYTE1)
R/W
R/W
R/W
R/W
R/W : Readable/writable
Read (number of valid data)
At transmission : Number of data written to FIFO and not
transmitted
At reception
: Number of data received in FIFO
Write (number of transfer)
At transmission : Set "00H"
At reception
: Set number of data which generates
the reception interrupt
R/W
R/W
R/W
R/W
R/W
Initial value
R/W
R/W
R/W
FBYTE1
Write
Read
FIFO1 data count indication bit
Set number of transfer.
Read number of valid data.
FBYTE2
Write
Read
FIFO2 data count indication bit
Set number of transfer.
Read number of valid data.
The FBYTE register indicates the number of valid data pieces of FIFO. It operates as follows according to
the setting of the FSEL bit.
Table 16.2-8 Indicate Number of Data
FSEL
FIFO selection
Indicate number of data
0
FIFO2: Receive FIFO, FIFO1: Transmit FIFO
FIFO2: FBYTE2, FIFO1: FBYTE1
1
FIFO2: Transmit FIFO, FIFO1: Receive FIFO
FIFO2: FBYTE2, FIFO1: FBYTE1
• Initial value of transfer count for the FBYTE register is "08H".
• Specify the data count that causes the reception interrupt flag to be generated in FBYTE of the reception
FIFO.
The interrupt flag (RDRF) is set to "1" if the specified number of the transfers matches the data
displayed for the FBYTE register.
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.2 CSIO (Clock Synchronous Serial Interface) Registers
MB91345 Series
• While the reception FIFO idle detection enable bit (FRIIE) is "1" and the data count that exists in the
reception FIFO is under the transfer count, the interrupt flag (RDRF) is set to "1" when the reception
idle status continues for 8 or more clocks in the baud rate clock. When having read RDR during the
eight clocks count, the counter is reset to "0", and then it counts another eight clocks. When the
reception FIFO is disabled, the counter is reset to "0". If you enable the reception FIFO when the data
remains in the FIFO, the counting process will be started again.
• When you receive the data in the master operation (master reception), set TIE bit and TBIE bit to "0",
specify the reception data count in FBYTE register of the transmission FIFO, and write "0" to FDRQ
bit. Then the number of serial clocks corresponding to given data is output and amount of data
corresponding the specified value can be received, when TXE bit is "1". After FDRQ becomes "1", set
TIE bit and TBIE bit to "1", if you want to do so.
Notes:
• Specify "800H" in FBYTE of the transmission FIFO except receiving the data in the master
operation.
• Set the transmission data count to receive the data in the master operation, when the
transmission FIFO is empty and TIE and TBIE bit are "0".
• If you disable the reception (RXE=0) when receiving the data in the master operation, disable the
transmission FIFO first then disable the transmission/reception.
• Set data of "1" or more to the FBYTE for reception FIFO.
• If you change FBYTE of the reception FIFO, change it after the reception is disabled.
• This register cannot use the read-modify-write (RMW) related commands.
• Setting that exceeds capacity of FIFO is disabled.
482
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CM71-10132-3E
CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.3 CSIO (Clock Synchronous Serial Interface) Interrupts
MB91345 Series
16.3
CSIO (Clock Synchronous Serial Interface) Interrupts
There are the reception interrupt and the transmission interrupt in CSIO (clock
synchronous serial interface) interrupts. The interrupt request can be generated by
following factors.
• When received data is set in the receive data register (RDR) or a reception error
occurs.
• When the send data is transferred from the transmit data register (TDR) to the send
shift register and sending starts.
• Transmission bus idle (no transmission operation)
• Transmission FIFO data request
■ CSIO interrupt
Table 16.3-1 shows the interrupt control bit and the interrupt factor of CSIO.
Table 16.3-1 Interrupt Control Bit of CSIO and Interruption Factor
Interrupt
Interrupt
Flag
request
type
register
flag bit
Interrupt factor
Interrupt
factor
enable bit
1-byte reception
Clear of the interrupt request flag
Read receive data (RDR).
Receiving the FBYTE setting value
RDRF
SSR
Receive
ORE
TDRE
SSR
SSR
Detect the reception idle state of 8bit time or more while the FRIIE bit
is "1" and valid data exists in
reception FIFO.
SCR:RIE
Reading the reception data (RDR) before
the reception FIFO is empty.
Overrun error
Writing "1" to Reception error flag clear
bit (SSR:REC).
The transmit register is empty
SCR:TIE
Writing to the transmit data (TDR), or
writing "1" to the transmit FIFO
operation enable bit when the transmit
FIFO operation enable bit is "0" and the
valid data exists in the transmit FIFO
(Resend). *
TBI
SSR
No transmit operation
SCR:
TBIE
Writing to the transmit data (TDR), or
writing "1" to the transmit FIFO
operation enable bit when the transmit
FIFO operation enable bit is "0" and the
valid data exists in the transmit FIFO
(Resend). *
FDRQ
FCR1
The transmit FIFO is empty
FCR1:
FTIE
Writing "0" to the FIFO transmit data
request bit (FCR1:FDRQ), or the
transmit FIFO is full.
Transmit
*: Set the TIE bit to "1" after the TDRE bit becomes "0".
CM71-10132-3E
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.3 CSIO (Clock Synchronous Serial Interface) Interrupts
16.3.1
MB91345 Series
Reception Interrupt Generation and Flag Set Timing
Interrupts during reception are one generated upon completion of reception
(SSR:RDRF) and one generated upon occurrence of a reception error (SSR:ORE).
■ Reception Interrupt Generation and Flag Set Timing
The reception data is stored in the reception data register (RDR) by detecting the last data bit. If a reception
error occurs (SSR:ORE=1) upon completion of reception (SSR:RDRF=1), the corresponding flag is set. A
receive interrupt is also generated if the receive interrupt is enabled (SSR:RIE=1).
Note:
When a reception error occurs, data in the receive data register (RDR) is invalid.
Figure 16.3-1 Reception Operation and Flag Set Timing
SCK
SIN
D0
D1
D2
D3
D4
D5
D6
D7
Reception data
sampling
RDRF
Note:
This figure shows the timing at the following conditions.
SCR : MS=1, SPI=0
ESCR : L2 to L0=000B
SMR : SCINV=0, BDS=0, SCKE=0, SOE=0
484
Reception interrupt generation
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.3 CSIO (Clock Synchronous Serial Interface) Interrupts
MB91345 Series
Figure 16.3-2 Set Timing for the ORE (Overrun Error) Flag
SCK
D0
SIN
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3 D4 D5 D6
D7
Reception data
sampling
RDRF
ORE
Overrun error generation
Notes:
· This figure shows the timing at the following condition.
SCR : MS=1, SPI=0
ESCR : L2 to L0=000B
SMR : SCINV=0, BDS=0, SCKE=0, SOE=0
· Overrun error is generated if the next data is transferred before reading the reception data (RDRF=1).
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.3 CSIO (Clock Synchronous Serial Interface) Interrupts
16.3.2
MB91345 Series
Timing when the Interrupt Occurs and the Flag Should
be Set during the Use of the Reception FIFO
During the use of the reception FIFO, an interrupt occurs when the setting value in the
FBYTE register (FBYTE) is received.
■ Timing when the Reception Interrupt Occurs and the Flag Should be Set during the
Use of the Reception FIFO
An occurrence of interrupt during the use of the reception FIFO is determined by the setting value in the
FBYTE register.
• When the data of the set transfer count of FBYTE register have been received, the reception data full
flag (SSR:RDRF) of the serial status register is set to "1". And if the reception interrupt is enabled
(SCR:RIE), a reception interrupt will occur.
• While the reception FIFO idle detection enable bit (FRIIE) is "1" and the data count that exists in the
reception FIFO is under the transfer count, the interrupt flag (RDRF) is set to "1" when the reception
idle status continues for 8 or more clocks in the baud rate clock. When having read RDR during the
eight clocks count, the counter is reset to "0", and then it counts another eight clocks. When the
reception FIFO is disabled, the counter is reset to "0". If you enable the reception FIFO when the data
remains in the FIFO, the counting process will be started again.
• When the receive data (RDR) is read until the reception FIFO is empty, the reception data full flag
(SSR:RDRF) is cleared.
• If the number of valid reception data indicates the FIFO capacity, an overrun error (SSR:ORE=1) will
occur when receiving the next data.
Figure 16.3-3 Reception Interrupt Generation Timing during the Use of the Reception FIFO
SCK
Reception
data
1st byte
2nd byte
3rd byte
FBYTE
(reception)
Valid byte
display
4th byte
5th byte
6th byte
1
2
7th byte
3
0
1
2
3 2 1 0
3 2 1 0
1
RDRF
Reading of
RDR
Interrupt is generated when FBYTE setting
(number of transmission) and number of
reception data are matched.
486
Reading of the all reception data
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.3 CSIO (Clock Synchronous Serial Interface) Interrupts
MB91345 Series
Figure 16.3-4 The set Timing for the ORE (Overrun Error) Flag Bit
SCK
Reception
data
1st byte
2nd byte
3rd byte
FBYTE
(reception)
Valid byte
display
4th byte
5th byte
6th byte
63
64
7th byte
60
59
60
61
62
RDRF
ORE
Interrupt is generated when number of
FBYTE (reception) setting + 1 and
number of reception data are matched.
Overrun error generation
Note:
Overrun is generated when the next data is received at the state that FIFO display specifies FIFO capacitance.
This figure shows the case of using 64-byte FIFO capacitance.
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.3 CSIO (Clock Synchronous Serial Interface) Interrupts
16.3.3
MB91345 Series
Transmit Interrupt Generation and Flag Set Timing
Interrupt during the transmit will occur if the transmit data is transferred from Transmit
Data Register (TDR) to the shift register for the transmit (SSR:TDRE=1) and the transmit
is started, and if there is no transmit operation (SSR:TBI=1).
■ Transmit Interrupt Generation and Flag Set Timing
● The set timing for the transmit data empty flag (TDRE)
When the data written to transmit data register (TDR) is transferred to the transmit shift register, it will be
available to write the next data (SSR:TDRE=1). A send interrupt is generated at this time if the send
interrupt is enabled (SCR:TIE=1). Since TDRE bit is a read-only bit, it is cleared to "0" by writing data to
the transmission data register (TDR).
Figure 16.3-5 Set Timing for the Transmit Data Empty Flag (TDRE)
SCK
Transmission
data
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
TDRE
Writing to
TDR
Transmission interrupt generation
● Set timing for the transmit bus idle flag (TBI)
SSR: TBI bit is set to "1" when the transmit data register is empty (TDRE=1) and the transmission
operation is not performed. In this case, if the transmit bus idle interrupt is enabled (SCR:TBIE=1), the
transmit interrupt will occur. When the transmission data is set to the transmission data register (TDR), the
TBI bit and the transmission interrupt request are cleared.
Figure 16.3-6 Set Timing for the Transmit Bus Idle Flag (TBI)
SCK
Transmission
data
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
TBI
TDRE
Writing to
TDR
Transmission interrupt generation by bus idle
488
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CM71-10132-3E
CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.3 CSIO (Clock Synchronous Serial Interface) Interrupts
MB91345 Series
16.3.4
Timing when the Interrupt Occurs and the Flag Should
be Set during the Use of the Transmit FIFO
Interrupt during the use of the transmit FIFO will occur when there is no data in the
transmit FIFO.
■ Timing when the Transmit Interrupt Occurs and the Flag Should be Set during the Use
of the Transmit FIFO
• When data does not exist in the transmit FIFO, the FIFO transmission data request bit (FCR1:FDRQ) is
set to "1".
At this time, if the FIFO transmit interrupt is enabled (FCR1:FTIE=1), the transmit interrupt occurs.
• When the transmit interrupt occurs and the required data is written to the transmit FIFO, write "0" to the
FIFO transmission data request bit (FCR1:FDRQ) and clear the interrupt request.
• When the transmission FIFO gets to full, the FIFO transmission data request bit (FCR1:FDRQ) becomes
"0".
• You can check that whether the transmission FIFO data exists or not by reading the FIFO byte register
(FBYTE).
FBYTE=00H indicates that no data exists in the transmit FIFO.
Figure 16.3-7 Transmit Interrupt Generation Timing during the Use of the Transmit FIFO
SCK
Transmission
data
FIFOBYTE
display
1st byte
0
1
2
1
2nd byte
0
3rd byte
1
4th byte
0
FDRQ
TDRF
Writing to
transmission
FIFO
Cleared by "0" writing
Transmission interrupt generation *1
Transmission buffer is empty *2
TXE
* 1 : FDRQ=1 is set because transmission FIFO is empty.
* 2 : TDRE=1 is set because the data is not existed in the transmission buffer register.
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.4 Operation of CSIO (Clock Synchronous Serial Interface)
16.4
MB91345 Series
Operation of CSIO (Clock Synchronous Serial Interface)
Transfer method is clock synchronous.
■ Operation of CSIO (Clock Synchronous Serial Interface)
(1) Normal Transfer (I)
● Feature
Item
Explanation
1
Mark level of serial clock (SCK)
"H"
2
Output timing of transmit data
Falling edge of SCK
3
Sampling of receive data
Rising edge of SCK
4
Data length
5 bits to 9 bits
● Register setting
Following are the setting value of the register required for the normal transfer (I).
Table 16.4-1 Register Setting for Normal Transfer (I)
SCR0 to SCRA/
SMR0 to SMRA
SSR0 to SSRA/
ESCR0 to ESCRA
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
UPCL
MS
SPI
RIE
TIE
TBIE
RXE
TXE
MD2
MD1
MD0 WUCR SCINV
0
1/0
0
*
*
*
*
*
0
1
0
0
REC



ORE
TBI
SOP


0





0


D8
D7

*
TDR0 to TDRA
(RDR0 to RDRA)
BGR01/BGR00
RDRF TDRE


bit4
bit3
bit2
bit1
bit0
BDS
SCKE
SOE
0
*
1/0
1/0


L2
L1
L0



*
*
*
D6
D5
D4
D3
D2
D1
D0
*
*
*
*
*
*
*
*

B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1 : Set "1".
0 : Set "0".
*: Setting determined by the user
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.4 Operation of CSIO (Clock Synchronous Serial Interface)
MB91345 Series
Note:
The setting values (1/0) of the bits above are different. in the master and slave operations.
At master transmission: SCR:MS=0, SMR:SCKE=1, SOE=1
At master reception:
SCR:MS=0, SMR:SCKE=1, SOE=0
At slave transmission:
SCR:MS=1, SMR:SCKE=0, SOE=1
At slave reception:
SCR:MS=1, SMR:SCKE=0, SOE=0
● Timing chart for Normal Transfer (I)
Transmission operation
1st byte
2nd byte
SCK
SOT
D0 D1 D2
D3 D4
D5 D6
D7 D0 D1
D2 D3 D4
D5 D6
D7
D2
D5
D7
TDRE
TDR RW
TXE
Reception operation
SIN
D0 D1
D2 D3 D4
D5 D6 D7
D0 D1
D3 D4
D6
Sampling
RDRF
RDR RD
RXE
● Operation explanation
[1] Master operation (Set to SCR:MS=0, SMR:SCKE=1)
• Transmission Operation
(1) When the transmit data is written to TDR by enabling the serial data output (SMR:SOE=1), enabling
the transmit operation (SCR:TXE=1), and disabling the reception operation (SCR:RXE=0),
SSR:TDRE becomes 0 and the transmit data is outputted in synchronization with the falling edge of
output for the serial clock (SCK).
(2) When the transmit data of the first 1-bit is outputted, SSR:TDRE is set to 1, and when the transmit
interrupt is enabled (SCR:TIE=1), the transmit interrupt request is outputted. In this case, the
transmission data of the second byte can be written.
CM71-10132-3E
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.4 Operation of CSIO (Clock Synchronous Serial Interface)
MB91345 Series
• Reception Operation
(1) When dummy data is written to TDR by disabling the serial data output (SMR:SOE=0) enabling the
transmit operation (SCR:TXE=1), and enabling the reception operation (SCR:RXE=1), the reception
data is sampling with the rising edge of the serial clock output (SCK).
(2) When last bit is received, SSR:RDRF=1 is set to 1, and when the reception interrupt is enabled
(SCR:RIE=1), the reception interrupt request is outputted.
In this case, the receive data (RDR) can be read.
(3) When the receive data (RDR) is read, SSR:RDRF is cleared to "0".
Notes:
• If only the reception is operated, write the dummy data to TDR in order to output the serial clock
(SCK).
• When the transmission/reception FIFO is enabled, the serial clock (SCK) in the frame of the
setting value is output by setting the frames to be transferred into FBYTE register.
[2] Slave operation (Set to SCR:MS=1, SMR:SCKE=0)
• Transmission Operation
(1) When the transmission data is written to TDR after the serial data output is enabled (SMR:SOE=1),
the transmission operation is enabled (SCR:TXE=1), SSR:TDRE=0 and the transmission data is
output synchronously with the falling edge of the serial clock (SCK).
(2) After the output of the transmission data of the first bit, SSR:TDRE=1. If the transmission interrupt
is enabled (SCR:TIE=1), the transmission interrupt request is output. In this case, the transmission
data of the second byte can be written.
• Reception Operation
(1) When disabling the serial data output (SMR:SOE=0) and enabling the reception operation
(SCR:RXE=1), the reception data is sampling with the rising edge of the serial clock input (SCK).
(2) When last bit is received, SSR:RDRF is set to 1, and when the reception interrupt is enabled
(SCR:RIE=1), the reception interrupt request is outputted.
In this case, the receive data (RDR) can be read.
(3) When the receive data (RDR) is read, SSR:RDRF is cleared to "0".
492
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.4 Operation of CSIO (Clock Synchronous Serial Interface)
MB91345 Series
(2) Normal Transfer (II)
● Feature
Item
Explanation
1
Mark level of serial clock (SCK)
"L"
2
Output timing of transmit data
Rising edge of SCK
3
Sampling of receive data
Falling edge of SCK
4
Data length
5 bits to 9 bits
● Register setting
Following are the setting value of the register required for the normal transfer (II).
Table 16.4-2 Register Setting for Normal Transfer (II)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
SCR0 to SCRA/
SMR0 to SMRA
UPCL
MS
SPI
RIE
TIE
TBIE
RXE
TXE
MD2
MD1
MD0
0
1/0
0
*
*
*
*
*
0
1
0
0
SSR0 to SSRA/
ESCR0 to ESCRA
REC



ORE
TBI
SOP


0





0


D8
D7

*
TDR0 to TDRA
(RDR0 to RDRA)
BGR01/BGR00
RDRF TDRE


bit4
bit3
bit2
bit1
bit0
BDS
SCKE
SOE
1
*
1/0
1/0


L2
L1
L0



*
*
*
D6
D5
D4
D3
D2
D1
D0
*
*
*
*
*
*
*
*
WUCR SCINV

B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1 : Set "1".
0 : Set "0".
*: Setting determined by the user
Note:
The setting values (1/0) of the bits above are different. in the master and slave operations.
At master transmission:
SCR:MS=0, SMR:SCKE=1, SOE=1
At master reception:
SCR:MS=0, SMR:SCKE=1, SOE=0
At slave transmission:
SCR:MS=1, SMR:SCKE=0, SOE=1
At slave reception:
SCR:MS=1, SMR:SCKE=0, SOE=0
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.4 Operation of CSIO (Clock Synchronous Serial Interface)
MB91345 Series
● Timing chart for Normal Transfer (II)
Transmission operation
1st byte
2nd byte
Mark level
SCK
SOT
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
TDRE
TDR RW
TXE
Reception operation
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
SIN
Sampling
RDRF
RDR RD
RXE
● Operation explanation
[1] Master operation (Set to SCR:MS=0, SMR:SCKE=1)
• Transmission Operation
(1) When the transmit data is written to TDR by enabling the serial data output (SMR:SOE=1), enabling
the transmit operation (SCR:TXE=1), and disabling the reception operation (SCR:RXE=0),
SSR:TDRE becomes 0 and the transmit data is outputted in synchronization with rising edge of
output for the serial clock (SCK).
(2) When the transmit data of the first 1-bit is outputted, SSR:TDRE is set to 1, and when the transmit
interrupt is enabled (SCR:TIE=1), the transmit interrupt request is outputted. In this case, the
transmission data of the second byte can be written.
• Reception operation
(1) When dummy data is written to TDR by disabling the serial data output (SMR:SOE=0), enabling the
transmit operation (SCR:TXE=1), and enabling the reception operation (SCR:RXE=1), the reception
data is sampling with the falling edge of the serial clock output (SCK).
(2) When last bit is received, SSR:RDRF is set to 1, and when the reception interrupt is enabled
(SCR:RIE=1), the reception interrupt request is outputted.
In this case, the receive data (RDR) can be read.
(3) When the receive data (RDR) is read, SSR:RDRF is cleared to "0".
494
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MB91345 Series
CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.4 Operation of CSIO (Clock Synchronous Serial Interface)
Notes:
• If only the reception is operated, write the dummy data to TDR in order to output the serial clock
(SCK).
• When the transmission/reception FIFO is enabled, the serial clock (SCK) in the frame of the
setting value is output by setting the frames to be transferred into FBYTE register.
[2] Slave operation (Set to SCR:MS=1, SMR:SCKE=0)
• Transmission Operation
(1) When the transmission data is written to TDR after the serial data output is enabled (SMR:SOE=1),
and the transmission operation is enabled (SCR:TXE=1), SSR:TDRE=0 and the transmission data is
output synchronously with the rising edge of the serial.
(2) After the output of the transmission data of the first bit, SSR:TDRE=1. If the transmission interrupt
is enabled (SCR:TIE=1), the transmission interrupt request is output. In this case, the transmission
data of the second byte can be written.
• Reception Operation
(1) When disabling the serial data output (SMR:SOE=0) and enabling the reception operation
(SCR:RXE=1), the reception data is sampling with the falling edge of the serial clock input (SCK).
(2) When last bit is received, SSR:RDRF is set to 1, and when the reception interrupt is enabled
(SCR:RIE=1), the reception interrupt request is outputted.
In this case, the receive data (RDR) can be read.
(3) When the receive data (RDR) is read, SSR:RDRF is cleared to "0".
CM71-10132-3E
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.4 Operation of CSIO (Clock Synchronous Serial Interface)
MB91345 Series
(3) SPI Transfer (I)
● Feature
Item
Explanation
1
Mark level of serial clock (SCK)
"H"
2
Output timing of transmit data
Rising edge of SCK
3
Sampling of receive data
Falling edge of SCK
4
Data length
5 bits to 9 bits
● Register setting
Followings are the register settings required for the SPI transmission (I).
Table 16.4-3 Register Setting for SPI Transfer (I)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
SCR0 to SCRA/
SMR0 to SMRA
UPCL
MS
SPI
RIE
TIE
TBIE
RXE
TXE
MD2
MD1
MD0
0
1/0
1
*
*
*
*
*
0
1
0
0
SSR0 to SSRA/
ESCR0 to ESCRA
REC



ORE
TBI
SOP


0





0


D8
D7

*
TDR0 to TDRA
(RDR0 to RDRA)
BGR01/BGR00
RDRF TDRE


bit4
bit3
bit2
bit1
bit0
BDS
SCKE
SOE
0
*
1/0
1/0


L2
L1
L0



*
*
*
D6
D5
D4
D3
D2
D1
D0
*
*
*
*
*
*
*
*
WUCR SCINV

B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1 : Set "1".
0 : Set "0".
*: Setting determined by the user
Note:
The setting values (1/0) of the bits above are different. in the master and slave operations.
At master transmission: SCR:MS=0, SMR:SCKE=1, SOE=1
496
At master reception:
SCR:MS=0, SMR:SCKE=1, SOE=0
At slave transmission:
SCR:MS=1, SMR:SCKE=0, SOE=1
At slave reception:
SCR:MS=1, SMR:SCKE=0, SOE=0
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.4 Operation of CSIO (Clock Synchronous Serial Interface)
MB91345 Series
● Timing Chart for SPI Transfer (I)
Transmission operation
SCK
1st byte
2nd byte
*A
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
SOT
D7
TDRE
TDR RW
TXE
Reception operation
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
SIN
Sampling
RDRF
RDR RD
RXE
*A: At a slave transmission (MS=1, SCKE=0, SOE=1), more than 4-machine
cycle time is required after writing to TDR.
● Operation explanation
[1] Master operation (Set to SCR:MS=0, SMR:SCKE=1)
• Transmission Operation
(1) When the transmission data is written to TDR after the serial date output is enabled (SMR:SOE=1),
the transmission operation is enabled (SCR:TXE=1), and the reception operation is disabled
(SCR:RXE=0), SSR:TDRE=0 and the first bit is output. Then the transmission data is output
synchronously with the rising edge of the serial clock (SCK) output.
(2) The transmit interrupt request is outputted when both conditions are met.
- SSR:TDRE is 1 before half cycle of falling edge for first serial clock
- Transmit interrupt is enabled (SCR:TIE=1)
In this case, the transmission data of the second byte can be written.
• Reception Operation
(1) When dummy data is written to TDR by disabling the serial data output (SMR:SOE=0), enabling the
transmit operation (SCR:TXE=1), and enabling the reception operation (SCR:RXE=1), the reception
data is sampling with the falling edge of the serial clock output (SCK).
(2) When last bit is received, SSR:RDRF is set to 1, and when the reception interrupt is enabled
(SCR:RIE=1), the reception interrupt request is outputted.
In this case, the receive data (RDR) can be read.
(3) When the receive data (RDR) is read, SSR:RDRF is cleared to "0".
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.4 Operation of CSIO (Clock Synchronous Serial Interface)
MB91345 Series
Notes:
• If only the reception is operated, write the dummy data to TDR in order to output the serial clock
(SCK).
• When the transmission/reception FIFO is enabled, the serial clock (SCK) in the frame of the
setting value is output by setting the frames to be transferred into FBYTE register.
[2] Slave operation (Set to SCR:MS=1, SMR:SCKE=0)
• Transmission Operation
(1) When the transmission data is written to TDR after the serial data output is enabled (SMR:SOE=1)
and the transmission operation is enabled (SCR:TXE=1), SSR:TDRE=0 and the first bit is output.
Then the transmission data is output synchronously with the rising edge of the serial clock (SCK)
output.
(2) The transmit interrupt request is outputted when both conditions are met.
- SSR:TDRE is 1 before half cycle of falling edge for first serial clock
- Transmit interrupt is enabled (SCR:TIE=1)
In this case, the transmission data of the second byte can be written.
• Reception Operation
(1) When disabling the serial data output (SMR:SOE=0) and enabling the reception operation
(SCR:RXE=1), the reception data is sampling with the falling edge of the serial clock input (SCK).
(2) When last bit is received, SSR:RDRF is set to 1, and when the reception interrupt is enabled
(SCR:RIE=1), the reception interrupt request is outputted.
In this case, the receive data (RDR) can be read.
(3) When the receive data (RDR) is read, SSR:RDRF is cleared to "0".
498
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.4 Operation of CSIO (Clock Synchronous Serial Interface)
MB91345 Series
(4) SPI Transfer (II)
● Feature
Item
Explanation
1
Mark level of serial clock (SCK)
"L"
2
Output timing of transmit data
Falling edge of SCK
3
Sampling of receive data
Rising edge of SCK
4
Data length
5 bits to 9 bits
● Register setting
Followings are the register settings required for the SPI transmission (II).
Table 16.4-4 Register Setting for SPI Transfer (II)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
SCR0 to SCRA/
SMR0 to SMRA
UPCL
MS
SPI
RIE
TIE
TBIE
RXE
TXE
MD2
MD1
MD0 WUCR SCINV
0
1/0
1
*
*
*
*
*
0
1
0
0
SSR0 to SSRA/
ESCR0 to ESCRA
REC



ORE
TBI
SOP


0





0


D8
D7

*
TDR0 to TDRA
(RDR0 to RDRA)
BGR01/BGR00
RDRF TDRE


bit4
bit3
bit2
bit1
bit0
BDS
SCKE
SOE
1
*
1/0
1/0


L2
L1
L0



*
*
*
D6
D5
D4
D3
D2
D1
D0
*
*
*
*
*
*
*
*

B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1 : Set "1".
0 : Set "0".
*: Setting determined by the user
Note:
The setting values (1/0) of the bits above are different. in the master and slave operations.
At master transmission: SCR:MS=0, SMR:SCKE=1, SOE=1
At master reception:
SCR:MS=0, SMR:SCKE=1, SOE=0
At slave transmission:
SCR:MS=1, SMR:SCKE=0, SOE=1
At slave reception:
SCR:MS=1, SMR:SCKE=0, SOE=0
CM71-10132-3E
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.4 Operation of CSIO (Clock Synchronous Serial Interface)
MB91345 Series
● Timing Chart for SPI Transfer (II)
1st byte
Transmission operation
2nd byte
*A
SCK
SOT
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
TDRE
TDR RW
TXE
Reception operation
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
SIN
Sampling
RDRF
RDR RD
RXE
*A: At a slave transmission (MS=1, SCKE=0, SOE=1), more than 4-machine
cycle time is required after writing to TDR.
● Operation explanation
[1] Master operation (Set to SCR:MS=0, SMR:SCKE=1)
• Transmission Operation
(1) When the transmit data is written to TDR by enabling the serial data output (SMR:SOE=1), enabling
the transmit operation (SCR:TXE=1), and disabling the reception operation (SCR:RXE=0),
SSR:TDRE becomes 0 and the transmit data is outputted in synchronization with the falling edge of
output for the serial clock (SCK).
(2) When the transmit data of the first 1-bit is outputted, SSR:TDRE is set to 1, and when the transmit
interrupt is enabled (SCR:TIE=1), the transmit interrupt request is outputted. In this case, the
transmission data of the second byte can be written.
• Reception Operation
(1) When dummy data is written to TDR by disabling the serial data output (SMR:SOE=1), enabling the
transmit operation (SCR:TXE=1), and enabling the reception operation (SCR:RXE=1), the reception
data is sampling with the rising edge of the serial clock output (SCK).
(2) When last bit is received, SSR:RDRF is set to 1, and when the reception interrupt is enabled
(SCR:RIE=1), the reception interrupt request is outputted.
In this case, the receive data (RDR) can be read.
(3) When the receive data (RDR) is read, SSR:RDRF is cleared to "0".
500
FUJITSU SEMICONDUCTOR LIMITED
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MB91345 Series
CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.4 Operation of CSIO (Clock Synchronous Serial Interface)
Notes:
• If only the reception is operated, write the dummy data to TDR in order to output the serial clock
(SCK).
• When the transmission/reception FIFO is enabled, the serial clock (SCK) in the frame of the
setting value is output by setting the frames to be transferred into FBYTE register.
[2] Slave operation (Set to SCR:MS=1, SMR:SCKE=0)
• Transmission Operation
(1) When the transmission data is written to TDR after the serial date output is enabled (SMR:SOE=1)
and the transmission operation is enabled (SCR:TXE=1), SSR: TDRE=0 and the transmission data
is output synchronously with the falling edge of the serial clock (SCK).
(2) After the output of the transmission data of the first bit, SSR:TDRE=1. If the transmission interrupt
is enabled (SCR:TIE=1), the transmission interrupt request is output. In this case, the transmission
data of the second byte can be written.
• Reception Operation
(1) When disabling the serial data output (SMR:SOE=0) and enabling the reception operation
(SCR:RXE=1), the reception data is sampling with the rising edge of the serial clock input (SCK).
(2) When last bit is received, SSR:RDRF is set to 1, and when the reception interrupt is enabled
(SCR:RIE=1), the reception interrupt request is outputted.
In this case, the receive data (RDR) can be read.
(3) When the receive data (RDR) is read, SSR:RDRF is cleared to "0".
CM71-10132-3E
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.5 Dedicated Baud Rate Generator
16.5
MB91345 Series
Dedicated Baud Rate Generator
The dedicated baud rate generator functions only in the master operation. When you
use the reception FIFO, set the dedicated baud rate generator even in the slave
operation.
■ Select the CSIO (Clock Synchronization Serial Interface) Baud Rate
The settings for the dedicated baud rate generator are different in the master and in slave operations.
● At master operation
Select the baud rate by dividing the internal clock using the dedicated baud rate generator.
• There are two internal reload counters, and each of them corresponds to the transmit/reception serial
clock. You can select a baud rate by setting a 15-bit reload value in the baud rate generator registers 1
and 0 (BGR1, BGR0).
• Reload counters divide the internal clock by the specified value.
● At slave operation
The dedicated baud rate generator does not function in the slave operation (SCR:MS=1). (External clock,
which was inputted from clock input pin SCK is directly used.)
Note:
When you use the reception FIFO, configure the dedicated baud rate generator even in the slave
operation.
502
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.5 Dedicated Baud Rate Generator
MB91345 Series
16.5.1
Baud Rate Setting
Baud rate settings are shown. The calculation result for the serial clock frequency is
also shown.
■ Baud Rate Opearion
The two 15-bit reload counters are set by baud rate generator registers 1 and 0 (BGR1 and BGR0).
The baud rate is calculated by the following equation.
(1) Reload value:
V = / b  1
V: Reload value
b: Baud rate
: Peripheral clock frequency
(2) Calculation example
The reload value is calculated by the following equation when setting 16 MHz for the peripheral
clock and 19200 bps for the baud rate.
Reload value:
V = (16 1000000) / 19200  1 = 832
Therefore, the baud rate is:
b = (16 1000000) / (832 + 1) = 19208 bps
(3) Error of baud rate
Error of baud rate is obtained by the following equation.
Error (%) = (Calculated value - Target value) / Target value 100
(Example) When setting peripheral clock 20 MHz and baud rate 1536000 bps
Reload value = (20 1000000) / 153600  1 = 129
Baud rate (Calculated value) = (20 1000000) / (129 + 1) = 153846 (bps)
Error (%) = (153846  153600) / 153600 100 = 0.16 (%)
Notes:
Setting a reload value of "0" stops the reload counter.
• When the reload value is the even number, the "H" and "L" widths of the serial clock are as
follows depending on the SCINV bit setting. If the value is an odd number, the "H" and "L" widths
of the serial clock will be the same.
When SCINV=0, "H" width of the serial clock will increase by one cycle of the peripheral clock.
When SCINV=1, "L" width of the serial clock will increase by one cycle of the peripheral clock.
• Set the reload value to 3 or more.
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.5 Dedicated Baud Rate Generator
MB91345 Series
■ Reload Value and Baud Rate for Each Peripheral Clock Frequency
Table 16.5-1 Reload Values and Baud Rates
Baud rate
(bps)
8 MHz
10 MHz
16 MHz
20 MHz
24 MHz
32 MHz
Value
ERR
Value
ERR
Value
ERR
Value
ERR
Value
ERR
Value
ERR
8M










3
0
6M








3
0


5M






3
0




4M




3
0
4
0
5
0
7
0
2.5M


3
0








2M
3
0
4
0
7
0
9
0
11
0
15
0
1M
7
0
9
0
15
0
19
0
23
0
31
0
500000
15
0
19
0
31
0
39
0
47
0
63
0
460800








51
-0.16


250000
31
0
39
0
63
0
79
0
95
0
127
0
230400








103
-0.16


153600
51
-0.16
64
-0.16
103
-0.16
129
-0.16
155
-0.16
207
-0.16
125000
63
0
79
0
127
0
159
0
191
0
255
0
115200
68
-0.64
86
0.22
138
0.08
173
0.22
207
-0.16
277
0.08
76800
103
-0.16
129
-0.16
207
-0.16
259
-0.16
311
-0.16
416
0.08
57600
138
0.08
173
0.22
277
0.08
346
-0.16
416
0.08
555
0.08
38400
207
-0.16
259
-0.16
416
0.08
520
0.03
624
0
832
-0.04
28800
277
0.08
346
<0.01
554
-0.01
693
-0.06
832
-0.03
1110
-0.01
19200
416
0.08
520
0.03
832
-0.03
1041
0.03
1249
0
1666
0.02
10417
767
<0.01
959
<0.01
1535
<0.01
1919
<0.01
2303
<0.01
3071
<0.01
9600
832
0.04
1041
0.03
1666
0.02
2083
0.03
2499
0
3332
-0.01
7200
1110
<0.01
1388
<0.01
2221
<0.01
2777
<0.01
3332
<0.01
4443
-0.01
4800
1666
0.02
2082
-0.02
3332
<0.01
4166
<0.01
4999
0
6666
<0.01
2400
3332
<0.01
4166
<0.01
6666
<0.01
8332
<0.01
9999
0
13332
<-0.01
1200
6666
<0.01
8334
0.02
13332
<0.01
16666
<0.01
19999
0
26666
<0.01
600
13332
<0.01
16666
<0.01
26666
<0.01






300
26666
26666
<0.01









(Note) Value : Setting value of BGR1/BGR0 registers
ERR
504
: Error of baud rate (%)
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.5 Dedicated Baud Rate Generator
MB91345 Series
■ Function of the Reload Counter
A pair of the transmission and reception reload counters serves as the dedicated baud rate generator. It
consists of 15-bit register for the reload value, and generates the transmission/reception clock from the
internal clock.
■ Start Counting
Once the reload value is written to the baud rate generator registers (BGR1, BGR0), the reload counter
starts to count.
■ Re-start
The reload counter will restart in the following condition.
Both send and receive reload counters
Programmable reset (SCR:UPCL bit)
CM71-10132-3E
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.6 Setting Procedure and Program Flow of CSIO (Clock
Synchronous Serial Interface)
16.6
MB91345 Series
Setting Procedure and Program Flow of CSIO
(Clock Synchronous Serial Interface)
The serial duplex synchronous transmission is available in the CSIO (clock
synchronization serial interface).
■ Inter-CPU Connection
The duplex transmission is selected in the CSIO (clock synchronous serial interface). Two CPUs are
reciprocally connected as shown in Figure 16.6-1.
Figure 16.6-1 Example of the Connection by the Duplex Transmission in CSIO
(Clock Synchronous Serial Interface)
SOT
SOT
SIN
SIN
SCK
SCK
CPU -2 (Slave)
CPU -1 (Master)
■ Flowchart
● When FIFO is not used
Figure 16.6-2 Example of the Flowchart for the Duplex Transmission (When FIFO is not Used)
(Master side)
(Slave side)
Start
Start
Operation format setting
Operation format setting
(matching to master side)
Set 1-byte data to TDR
and communicate
Data
transmission
NO
RDRF=1
YES
NO
RDRF=1
Data
transmission
(ANS)
Read and process of
reception data
YES
Read and process of
reception data
506
1-byte data
transmission
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.6 Setting Procedure and Program Flow of CSIO (Clock Synchronous
Serial Interface)
MB91345 Series
● When FIFO is used
Figure 16.6-3 Example of the Flowchart for the Duplex Transmission (When FIFO is Used)
(Master side)
(Slave side)
Start
Start
Operation format setting
Operation format setting
(matching to master side)
Transmission/reception
FIFO enable
Transmission/reception
FIFO enable
Setting of received FBYTE
Setting of received FBYTE
Setting N byte to
transmission FIFO and
writing "0" to FDRQ bit
Data
tranmsmission
RDRF=1
YES
Data
tranmsmission
NO
(ANS)
RDRF=1
YES
NO
Read and operate based on
the FIFOBYTE setting value
Setting N byte to
transmission FIFO and
writing "0" to FDRQ bit
Read and operate based on
the FBYTE setting value
CM71-10132-3E
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CHAPTER 16 CSIO (Clock Synchronous Serial Interface)
16.7 Notes on CSIO Mode
16.7
MB91345 Series
Notes on CSIO Mode
The notes for when you use the CSIO mode are shown below.
• FIFO cannot be used for requesting DMA transfer with a channel with FIFO. Please set as FIFO
operation disable.
• To request a DMA transfer request, set the block size of DMA to one time.
• When master reception and slave reception are selected, it is required to use two channels for DMA;
one is used for DMA transfer to receive data and the other one is used for DMA transfer to send dummy
data.
508
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 17
I2C Interface
I2C interface, which is supported by the operation mode
4, among the multi function interfaces is described.
17.1 Overview of I2C Interface
17.2 I2C Interface Register
17.3 I2C Interface Interruption
17.4 Dedicated Baud Rate Generator
17.5 Notes on I2C Mode
CM71-10132-3E
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CHAPTER 17 I2C Interface
17.1 Overview of I2C Interface
17.1
MB91345 Series
Overview of I2C Interface
I2C interface supports the inter IC bus and works as the master/slave device on the I2C
bus. The transmission/reception FIFO (maximum 16 bytes each) is also loaded.
■ Function of I2C Interface
The I2C interface has the following functions.
• Function of master/slave transmission and reception.
• Function of arbitration
• Function of clock synchronization
• Function of transmission direction detection
• Generation of repeat start condition and detection function
• Function of bus error detection
• Function of general call addressing
• 7-bit addressing as the master/slave
• Enable to generate the interrupt at transfer and bus error.
• 10-bit addressing function can be supported by the program
■ Functions of the FIFO
FIFO has the following function.
• Transmission/reception FIFO is loaded (maximum capacitance: 16 bytes at a transmission FIFO and 16
bytes at a reception FIFO).
• Transmission FIFO and reception FIFO can be selected.
• Transmission data can be resended.
• Interrupt timing of reception FIFO can be changed by a soft.
• FIFO reset is supported independently.
510
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
17.2
I2C Interface Register
The register list of I2C interface is shown.
■ Register List of I2C Interface
Figure 17.2-1 List of I2C Interface Registers
Address
I2C
FIFO
bit15
bit8 bit7
bit0
0000X0H 0000X1H
IBCR (I2C bus control register)
SMR (serial mode register)
0000X2H 0000X3H
SSR (serial status register)
IBSR (I2C bus status register)
0000X4H 0000X5H

RDR/TDR
(transmission/reception data register)
0000X6H 0000X7H
BGR1
(Baud rate generator register 1)
BGR0
(Baud rate generator register 0)
0000X8H 0000X9H
ISMK
(7bit slave address mask register)
ISBA
(7bit slave address register)
0000Y0H 0000Y1H
FCR1 (FIFO control register 1)
FCR0 (FIFO control register 0)
0000Y2H 0000Y3H
FBYTE2 (FIFO2 byte register)
FBYTE1 (FIFO1 byte register)
(X=06,07,08,09,0A,0B,1B,1C,1D,1E,1F, Y=6,7)
Table 17.2-1 Bit Allocation of I2C Interface
bit15
bit14
bit13
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
IBCR0 to IBCRA/
SMR0 to SMRA
MSS
ACT/
SCC
ACKE WSEL CNDE
INTE
BER
INT
MD2
MD1
MD0

RIE
TIE
SSR0 to SSRA/
IBSR0 to IBSRA
REC
TSET


ORE

FBT
TRX
AL
RSC
SPC
BB
TDR1/0








D7
D6
D5
D4
D3
D2
D1
D0
BGR1/0

B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
ISMK0 to ISMKA/
ISBA
EN
SM6
SM5
SM4
SM3
SM2
SM1
SM0
SAEN
SA6
SA5
SA4
SA3
SA2
SA1
SA0
FTIE
FSEL

FLST
FLD
FSET FCL2 FCL1
FE2
FE1
FD9
FD8
FD7
FD6
FD5
FD4
FD1
FD0
FCR1/FCR0
Reserved Reserved
FBYTE2/1
CM71-10132-3E
FD15
FD14

FD13
bit12
RDRF TDRE
FLSTE FRIIE FDRQ
FD12
FD11
FD10
RACK RSA
FUJITSU SEMICONDUCTOR LIMITED
FD3
FD2
bit1
bit0
ITST1 ITST0
511
CHAPTER 17 I2C Interface
17.2 I2C Interface Register
17.2.1
MB91345 Series
I2C Bus Control Register (IBCR)
I2C Bus Control Register (IBCR) selects the master/slave mode, sets the repetitive start
condition, enables acknowledgement, enables interrupts, and displays the interrupt
flag.
■ I2C Bus Control Register (IBCR)
Figure 17.2-2 shows the bit configuration of I2C bus control register (IBCR), and Table 17.2-2 shows the
function of each bit.
Figure 17.2-2 Bit Configuration of I2C Bus Control Register (IBCR)
IBCR
Address
ch.0 00060H
ch.1 00070H
ch.2 00080H
ch.3 00090H
ch.4 000A0H
ch.5 000B0H
ch.6 001B0H
ch.7 001C0H
ch.8 001D0H
ch.9 001E0H
ch.A 001F0H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
MSS
ACT/SCC
ACKE
WSEL
CNDE
INTE
BER
INT
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
INT
0
1
Interrupt flag bit
Write
Read
Clear of INT
No interrupt request
No effect
Interrupt request
INTE
0
1
Interrupt enable bits
Interrupt disable
Interrupt enable
CNDE
0
1
Condition detect interrupt enable bit
Repeat start or stop condition interrupt disable
Repeat start or stop condition interrupt enable
WSEL
0
1
Wait select bit
Wait after acknowledge (9 bits)
Wait after data transmission/reception (8 bits)
ACKE
0
1
Acknowledge enable bit
Acknowledge disable
Acknowledge enable
1
512
00000000B
Bus error detect bit
No error
Detecting error
0
: Readable/writable
: Read only
: Initial value
(SMR)
BER
0
1
ACT/SCC
R/W
R
Initial value
bit7
MSS
0
1
Operation flag/repeat start condition
generating bit
Write
Read
No effect
No operation
Generate repeat start
I2C operating
condition
Master/slave selection bit
Selecting slave mode
Selecting master mode
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
Table 17.2-2 Functional Description of Each Bit in I2C bus Control Register (IBCR) (1 / 4)
Bit name
Function
• If this bit is set to "1", the mode will be the master when I2C bus is in the idle status (EN=1,
BB=0).
• If this bit is set to "1", when the BB bit of IBSR register is "1", it waits to generate the start
condition until the BB bit becomes "0". If the slave address matches during the wait, and
works as the slave, this bit becomes "0" and the AL bit of IBSR register becomes "1".
• When the interrupt flag (INT) is "1" in the master operation (MSS=1, ACT=1), the stop
condition is generated by writing "0" to this bit.
MSS bit is cleared at the condition as following.
(1) Disabling I2C interface (EN bit=0)
(2) Generating arbitration lost
(3) Detecting bus error (BER bit=1)
(4) At INT=1, writing "0" to MSS bit
The relation between MSS bit and ACT bit is shown below.
bit15
MSS: Master/
slave selection
bit
MSS bit ACT bit
Condition
0
0
Idle
0
1
ACK corresponding* to slave address match or
reserved address and operating (slave mode)
1
0
Waiting master operation
1
1
Master operating (master mode)
*: ACK corresponding indicates SDA of I2C bus is "L" at interval of
acknowledge.
Notes:
• When the MSS bit is changed to "0" if it has already been set to "1", perform it in MSS
bit=1 and INT bit=1. If "0" is written to MSS bit when ACT bit is "1", INT bit is also
cleared to "0".
• As long as ACT bit is "1", "1" is read for MSS bit in the master operation, even if "0" is
written to MSS bit.
CM71-10132-3E
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CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
Table 17.2-2 Functional Description of Each Bit in I2C bus Control Register (IBCR) (2 / 4)
Bit name
Function
This bit works differently in read and write.
bit14
514
ACT/SCC:
Operation flag
bit/Repetition
start condition
generation bit
Read
Write
ACT bit
SCC bit
ACT bit indicates either it works as the master or slave mode.
Set condition of ACT bit:
• When start condition is outputted to I2C bus (master mode)
• When slave address matches address transmitted from master
(slave mode)
• When reserved address is detected and acknowledge is responded to it (slave mode in
MSS=0)
Reset condition of ACT bit:
<Master mode>
• Stop condition is detected.
• Arbitration lost is detected.
• Bus error is detected.
• I2C interface is disabled (EN bit=0).
<Slave mode>
• (Repeat) start condition is detected.
• Stop condition is detected.
• When acknowledge is not responded with reserved address detection state (RSA=1).
• I2C interface is disabled (EN bit=0).
• Bus error is occurred (BER bit=1).
Writing "1" to this bit in the master mode executes repeat start.
Writing "0" has no effect.
Notes:
• Write "1" to the SCC bit while an interrupt in the master mode generates (MSS=1, ACT=1,
INT=1). If "1" is written to SCC bit when ACT bit is "1", INT bit is also cleared to "0".
• You must not write "1" to this bit in the slave mode (MSS=0, ACT=1).
• When "1" is written to SCC bit and "0" to MSS bit, MSS bit has a priority.
• The read command in read-modify-write (RMW) related commands reads SCC bit.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
Table 17.2-2 Functional Description of Each Bit in I2C bus Control Register (IBCR) (3 / 4)
Bit name
Function
ACKE:
The data byte
acknowledge
enable bit
• If this bit is set to "1", "L" is output on the acknowledge timing.
• If you change this bit in ACT=1, do the change in INT bit=1.
This bit is invalid in the following conditions.
• Acknowledge to the address field other than the reserved address (auto generation).
• The data is transmitted (RSA=0, TRX=1, FBT=0).
• When the reception FIFO is enabled and in the slave reception (FE=1, MSS=0, ACT=1),
always answer the ACK.
• When the reception FIFO is enabled, WSEL is set to "0", and in the master reception
(FE=1, MSS=1, ACT=1, WSEL=0), answer the ACK response in TDRE bit=0, or answer
the NACK response in TDRE bit=1.
• When the reception FIFO is enabled, WSEL=0, and the slave transmission detecting the
reserved address (RSA=1, TRX=1, FBT=1), always answer the ACK response. If you want
the NACK response, disable the reception FIFO and set ACKE=0 when interrupting after
the reserved address is detected.
• When the reception FIFO is enabled, WSEL is set to "1", and the data exist in the transmit
register in the master reception (FE=1, MSS=1, ACT=1, WSEL=1, TDRE=0).
bit12
WSEL:
Wait selection
bit
• This bit enables to select whether waiting for the I2C bus or not by generating the interrupt
(INT=1) before or after the acknowledge.
• The WSEL bit is invalid in the following conditions.
• When an interrupt is generated (INT=1) to the first byte*1
• When the reserved address is detected (FBT=1, RSA=1)
• When the NACK response*2 is detected during data transfer at using FIFO (FE=1,
RACK=1, ACT=1)
• When the reception FIFO is full at using the reception FIFO
*1: First byte: This indicates data after (repeat) start condition.
*2: NACK response: Acknowledge period. This indicates the SDA of I2C bus is "H".
bit11
CNDE:
The condition
detection
interrupt
enable bit
This bit enables to generate the interrupt when the stop condition or repetition start condition is
detected in the master or slave mode (ACT=1). When RSC or SPC bit of IBSR register=1 and
this bit=1, the interrupt is generated.
bit10
INTE:
Interrupt
enable bit
This bit enables the interrupt (INT=1) to the data transmission/reception and bus error in the
master or slave mode.
bit13
bit9
BER:
Bit for bus
error flag
detection
CM71-10132-3E
This bit indicates that the error is detected on I2C bus.
Set condition of BER bit:
• Start or stop condition is detected while the first byte* is transferred.
• Start or stop condition is detected in 2nd to 9th (acknowledge) bit of data after the second
or subsequent byte.
Reset condition of BER bit:
• When "0" is written to the INT bit in BER=1
• When the I2C interface is disabled (EN=0)
*: First byte: This indicates data after (repeat) start condition.
Note:
Check this bit when the interrupt flag (INT bit) is set to "1". This is because the transmission/
reception operation cannot perform correctly, processing such as retransmission is executed.
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CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
Table 17.2-2 Functional Description of Each Bit in I2C bus Control Register (IBCR) (4 / 4)
Bit name
bit8
516
INT:
Interrupt flag
bit
Function
This bit set this flag to "1" under the following set conditions. Except the case of the bus error,
SCL is set to "L" when INT bit is "1", while the "L" of SCL is cancelled when INT bit is "0".
Set condition of INT bit:
<Eighth bit>
• When the reserved address is detected in the first byte
• When the WSEL is "1" and the arbitration lost is detected in the second or subsequent byte
• When the WSEL is "1", the master is operating, and the TDRE bit is "1" in the second or
subsequent byte
• When the WSEL is "1", the slave is operating, the reception FIFO is disabled, and the
TDRE bit is "1" in the second or subsequent byte
• When the WSEL is "1", the slave is transmitting, and the TDRE bit is "1" in the second or
subsequent byte
<Ninth bit>
• When the arbitration lost is detected in the first byte
• When the NACK is received except for output setting of stop condition (write "0" to the
MSS bit in the master operation)
• When the TDRE bit is "1" at the transmit direction (TRX=1) in the master or slave mode
without detecting the reserved address in the first byte
• When data exists in the reception FIFO during the reception FIFO is enabled at the
reception direction (TRX=0) in the master or slave mode without detecting the reserved
address in the first byte
• When the TDRE bit is "1" while the reception FIFO is disabled at the reception direction
(TRX=0) in the master or slave mode without detecting the reserved address in the first
byte
• When the arbitration lost is detected in the second or subsequent byte at WSEL=0
• When the TDRE bit is "1" in the second or subsequent byte while the master mode is
operating at WSEL=0
• When the TDRE bit is "1" in the second or subsequent byte while the slave is sending at
WSEL=0
• When the slave is received with the reception FIFO disabled at WSEL=0. However, the
interrupt is not generated in 9th bit in the slave reception of the first byte which detects the
reserved address.
• When reception FIFO is full while reception FIFO is enabled and the slave is received
<Others>
• Bus error is detected.
Reset condition of INT bit:
• Write "0" to INT bit.
• Write "0" to MSS bit when the INT and ACT bits are "1".
• Write "1" to SCC bit when the INT and ACT bits are "1".
Write "1" to the INT bit is invalid.
Notes:
• When EN bit is set to "0", the RDRF and INT bits may be "1" due to reception timing. In
this case, read the reception data and clear INT bit.
• The read command in read-modify-write (RMW) related commands reads "1".
• When reception FIFO is enabled, INT bit is not set to "1" in the master reception operation
even if the reception FIFO is Full.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
17.2.2
Serial Mode Register (SMR0 to SMRA)
Serial mode register (SMR0 to SMRA) sets the operation mode, and enables or disables
the interrupt of the transmission/reception.
■ Serial Mode Register (SMR0 to SMRA)
Figure 17.2-3 shows the bit configuration of serial mode register (SMR0 to SMRA), and Table 17.2-3
shows the function of each bit.
Figure 17.2-3 Bit Configuration of Serial Mode Register (SMR0 to SMRA)
bit15
SMR
Address
ch.0 000061H
ch.1 000071H
ch.2 000081H
ch.3 000091H
ch.4 0000A1H
ch.5 0000B1H
ch.6 0001B1H
ch.7 0001C1H
ch.8 0001D1H
ch.9 0001E1H
ch.A 0001F1H
bit8
(IBCR)
bit7
bit6
bit5
bit4
bit3
bit2
MD2
MD1
MD0

RIE
TIE
R/W
R/W
R/W
R/W
R/W
R/W
bit1
bit0
ITST1 ITST0
R/W
Initial value
00000000B
R/W
I2C test bit
test disable
I2C test enable
ITST
0
1
I2 C
TIE
0
1
Transmit interrupt enable bit
Transmission interrupts disable
Transmission Interrupt enable
RIE
0
1
Receive interrupt enable bit
Reception interrupt disable
Reception Interrupt enable
Unused bit
Read value is undefined. Writing has no effect.
R/W

: Readable/writable
:Unused bit
: Initial value
CM71-10132-3E
MD2
MD1
MD0
0
0
0
0
0
1
0
1
1
0
0
0
Operation mode setting bits
Operation mode 0
(asynchronous normal mode)
operation mode 1
(asynchronous multiprocessor mode)
operation mode 2 (clock synchronous mode)
operation mode 4 (I2C mode)
Note: The register and operation of the operation mode 4 are
explained.
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CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
Table 17.2-3 Functional Description of Each Bit in Serial Mode Register (SMR0 to SMRA)
Bit name
Function
bit7
to
bit5
MD2, MD1,
MD0:
The operation
mode set bit
These bits set the operation mode.
"000B": Set to the operation mode 0 (asynchronous normal mode).
"001B": Set to the operation mode 1 (asynchronous multiprocessor mode).
"010B": Set to the operation mode 2 (clock synchronous mode).
"100B": Set to the operation mode 4 (I2C mode).
Notes:
• Setting other than the above is disabled.
• When you switch the operation mode, disable I2C (ISMK:EN=0) first, then switch the
operation mode.
• Specify each register after the operation mode is set.
bit4
Unused bit
Read: The value is undefined.
Write: No effect.
bit3
RIE:
The reception
interrupt enable
bit
• This bit enables or disables the reception interrupt request output to the CPU.
• When RIE bit and the reception data flag bit (RDRF) are "1", or any of the error flag bits
(ORE) is "1", the interrupt request is output.
Note:
When data is received using the INT bit of the I2C bus control register (IBCR), this bit is set
to "0".
bit2
TIE:
The transmit
interrupt enable
bit
• This bit enables or disables the transmit interrupt request output to the CPU.
• When the TIE and TDRE bits are "1", the transmit interrupt request is outputted.
Note:
When data is transmitted using the INT bit of the I2C bus control register (IBCR), this bit is
set to "0".
ITST1, ITST0:
I2C test bit
This bit is I2C test bit.
This bit is always set "0".
Note:
When setting "1" to this bit, I2C test is executed.
bit1,
bit0
Note:
If you change the operation mode, other registers are initialized. Set the operation mode first.
However, if you write IBCR and SMR simultaneously using 16-bit writing, the writing is applied to
IBCR.
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CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
I2C Bus Status Register (IBSR)
17.2.3
I2C bus status register (IBSR) indicates that repetition start, acknowledge, data
direction, arbitration lost, stop condition, I2C bus status, and/or bus error are detected.
■ I2C bus Status Register (IBSR)
Figure 17.2-4 shows the bit configuration of I2C bus status register (IBSR), and Table 17.2-4 shows the
function of each bit.
Figure 17.2-4 Bit Configuration of I2C Bus Status Register (IBSR)
IBSR
Address
0000X3H
bit15
bit8
(SSR)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
FBT
RACK
RSA
TRX
AL
RSC
SPC
BB
00000000B
R
R
R
R
R
R/W
R/W
R
BB
0
1
Bus state bit
Bus idle state
Bus transmission/reception state
SPC
0
1
Master
Slave
R/W
R
: Readable/writable
: Read only
: Initial value
CM71-10132-3E
Stop condition check bit
Stop condition is not detected.
Stop condition is detected or arbitration
lost is generated at stop condition output.
Stop condition is detected.
RSC
0
1
Repeat start condition check bit
Repeat start condition is not detected.
Repeat start condition is detected.
AL
0
1
Arbitration lost bit
Arbitration lost is not generated.
Arbitration lost is generated.
TRX
0
1
Data direction bit
Reception direction
Transmission direction
RSA
0
1
Reserved address detection bit
Reserved address is not detected.
Reserved address is detected.
RACK
0
1
Acknowledge flag bit
"L" reception
"H" reception
FBT
0
1
First byte bit
Other than first byte
During transmission/reception of first byte
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CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
Table 17.2-4 Functional Description of Each Bit in I2C Bus Status Register (IBSR) (1 / 3)
Bit name
bit7
bit6
bit5
520
Function
FBT:
First byte bit
This bit indicates the first byte.
FBT bit setting conditions:
• (Repetition) start condition is detected.
Clear condition of FBT bit:
• Transmission/reception of the second byte.
• The stop condition is detected.
• I2C interface is disabled (EN bit=0).
• The bus error is detected (BER bit=1).
RACK:
Acknowledge flag
bit
This bit in the first byte indicates received acknowledge in the master or slave mode.
Condition of renewal of RACK bit
• Acknowledge at the first byte
• Data acknowledge at a master or slave mode
Condition of clearing RACK bit (RACK bit=0)
• (Repeat) start condition detection
• I2C interface disable (EN bit=0)
• Bus error detection (BER bit=1)
RSA:
Reserved address
detection bit
This bit indicates that the reserved address is detected.
RSA bit setting conditions (RSA=1):
• The first byte is (0000xxxx) or (1111xxxx). "x" shows "0" or "1".
RSA bit setting conditions (RSA=0):
• (Repeat) start condition detection
• Stop condition detection
• I2C interface disable (EN bit=0)
• Bus error detection (BER bit=1)
When the RSA bit becomes "1" in the first byte, the interrupt flag (INT) is set to "1" and the
SCL is set to "L" at the falling edge of SCL in eighth bit of the first byte regardless of
enabling/disabling FIFO. If you want to read the reception data and make it work as the
slave, set ACKE to "1" and clear the interrupt flag (INT) to "0". Then, when TRX bit is "0",
receive the data as the slave. If you do not want to receive the data along the way, set ACKE
bit to "0". After that, data is not received.
Notes:
• When the ACKE is set to "0" during data transfer, the ACKE cannot set to "1" until the
stop or repeat start condition is detected.
• When the slave transmission is confirmed in interrupting by detecting the reserved
address, ACK response is answered if the reception FIFO is enabled. Disable the
reception FIFO and set ACKE=0.
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CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
Table 17.2-4 Functional Description of Each Bit in I2C Bus Status Register (IBSR) (2 / 3)
Bit name
bit4
bit3
bit2
Function
TRX:
Data direction bit
This bit indicates the data direction.
TRX bit setting conditions:
• Transfer (repeat) start condition at a master mode.
• When the eighth bit of the first byte is "1" at a slave mode (transmission direction as a
slave)
TRX bit resetting conditions:
• Generating arbitration lost (AL=1)
• When the eighth bit of the first byte is "0" at a slave mode (reception direction as a
slave)
• When the eighth bit of the first byte is "1" at a master mode (reception direction as a
master)
• Stop condition detection
• (Repeat) start condition other than the master mode is detected.
• I2C interface disable (EN bit=0)
• Bus error detection (BER bit=1)
AL:
Arbitration lost bit
This bit indicates the arbitration lost.
AL bit setting conditions:
• When data outputted in the master mode differs from received data
• When the MSS bit is set to "1", but this device is operating as slave.
• When repeat start condition is detected in first bit of data for the second or
subsequent byte in the master mode
• When stop condition is detected in first bit of data for the second or subsequent byte in
the master mode
• When repeat start condition is tried to generate in the master mode, but it cannot
generate.
• When stop condition is tried to generate in the master mode, but it cannot generate.
AL bit resetting conditions:
• Writing "1" to MSS bit
• Writing "0" to INT bit
• Writing "0" to SPC bit at AL bit=1, SPC bit=1
• I2C interface disable (EN bit=0)
• Bus error detection (BER bit=1)
RSC:
Repetition start
condition
confirmation bit
This bit indicates that the repetition start condition is detected in the master or slave mode.
RSC bit setting conditions:
• When repeat start condition is detected after acknowledge during operation in the slave
or master mode
RSC bit setting conditions:
• Writing "0" to RSC bit
• Writing "1" to MSS bit
• I2C interface disable (EN bit=0)
Writing "1" to this bit is invalid.
Notes:
• While the reception is operating as the slave mode due to detection of the reserved
address, the slave mode is completed if the acknowledge is not responded. Therefore,
this bit is not set to "1" even if next repeat start condition is detected.
• The read command in read-modify-write (RMW) related commands reads "1".
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CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
Table 17.2-4 Functional Description of Each Bit in I2C Bus Status Register (IBSR) (3 / 3)
Bit name
bit1
bit0
522
Function
SPC:
Stop condition
confirmation bit.
This bit indicates that the stop condition is detected in the master or slave mode.
SPC bit setting conditions:
• When the stop condition is detected during operation in the slave or master mode
• When the arbitration lost occurs during operation of the stop condition in the
master mode
SPC bit resetting conditions:
• Writing "0" to this bit
• Writing "1" to MSS bit
• I2C interface disable (EN bit=0)
Writing "1" to this bit is invalid.
Notes:
• While the reception is operating as the slave mode due to detection of the reserved
address, the slave mode is completed if the acknowledge is not responded. Therefore,
this bit is not set to "1" even if next stop condition is detected.
• The read command in read-modify-write (RMW) related commands reads "1".
BB:
Bus status bit.
This bit indicates the bus status.
BB bit setting conditions:
• "L" is detected in SDA or SCL of I2C bus.
BB bit resetting conditions:
• The stop condition is detected.
• I2C interface is disabled (EN bit=0).
• The bus error is detected (BER bit=1).
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CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
17.2.4
Serial Status Register (SSR0 to SSRA)
Serial status register (SSR0 to SSRA) confirms the transmission/reception condition.
■ Serial Status Register (SSR0 to SSRA)
Figure 17.2-5 shows the bit configuration of serial status register (SSR0 to SSRA), and Table 17.2-5 shows
the function of each bit.
Figure 17.2-5 Bit Configuration of Serial Status Register (SSR0 to SSRA)
bit15 bit14 bit13 bit12 bit11 bit10
SSR
Address
REC TSET


ORE RDRF
ch.0 000062H R/W R/W


R
R
ch.1 000072H
ch.2 000082H
ch.3 000092H
ch.4 0000A2H
ch.5 0000B2H
ch.6 0001B2H
ch.7 0001C2H
ch.8 0001D2H
ch.9 0001E2H
ch.A 0001F2H
bit9
bit8
TDRE

R

bit7
bit0
(IBSR)
Initial value
0-000011B
Unused bit
Read value is undefined. Writing has no effect.
TDRE
0
1
Transmission data empty flag bit
Data is existed in transmission data register (TDR).
Transmission data register TDR is empty.
RDRF
0
1
Receive data full flag bit
Reception data register (RDR) is empty.
Data is existed in reception data register (RDR).
ORE
0
1
Overrun error flag bit
No overrun error
Overrun error
Unused bit
Read value is undefined. Writing has no effect.
TSET
0
1
REC
R
R/W

CM71-10132-3E
: Read only
: Readable/writable
: Unused bit
: Initial value
0
1
Transmission data empty flag set bit
Write
Read
No effect
"0" is always read.
TDRE bit set
Receive error flag clear bit
Write
Read
No effect
"0" is always read.
Clearing of reception
error flag (ORE)
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17.2 I2C Interface Register
MB91345 Series
Table 17.2-5 Functional Description of Each Bit of the Serial Status Registers (SSR0 to SSRA)
Bit name
Function
bit15
REC:
The reception error
flag clear bit
This bit clears the ORE bit of the serial status register (SSR0 to SSRA).
• Writing "1" clears the ORE bit.
• Writing "0" has no effect.
Read: 0 is always read.
bit14
TSET:
Empty flag set bit
for the transmission
data
This bit sets the TDRE bit of Serial status register (SSR0 to SSRA).
• Writing "1" sets the TDRE bit.
• Writing "0" has no effect.
Read: 0 is always read.
bit13,
bit12
Unused bit
Read: The value is undefined.
Write: No effect.
ORE:
Overrun error flag
bit
• This bit is set to "1" when the overrun is generated in the reception, and cleared when
"1" is written to the REC bit of the serial status register (SSR0 to SSRA).
• When the ORE and RIE bits are "1", the reception interrupt request is outputted.
• If this flag is set, the reception data register (RDR0 to RDRA) is disabled.
• If this flag is set in using the reception FIFO, the reception data is not stored in the
reception FIFO.
RDRF:
The reception data
full flag bit
• This flag indicates the status of Reception Data Register (RDR0 to RDRA).
• When RIE bit and the reception data flag bit (RDRF) are "1", the reception interrupt
request is output.
• The bit is set to "1" when the RDR0 to RDRA loads received data. The bit is cleared to
"0" when the receive data register is read.
• This is set in the timing of the SCL falling of the 8th bit of the data.
• This is set by the NACK response *.
• When using the reception FIFO, RDRF will be set to "1" if the FIFO receives the
specified number of data.
• When using the reception FIFO, it will be cleared to "0" if the reception FIFO is
empty.
• When the reception FIFO is used, the RDRF is set to "1" if the predefined data count is
not received and the data is left in the reception FIFO, and the reception idle status
continues for 8 or more clocks in the reception baud rate clock, and BER bit is "0".
When having read RDR during the eight clocks count, the counter is reset to "0", and
then it counts another eight clocks.
*: NACK response: Acknowledge period. This indicates the SDA of I2C bus is "H".
bit9
TDRE:
The transmit data
empty flag bit
• This bit indicates the status of transmit data register (TDR0 to TDRA).
• When the TIE and TDRE bits are "1", the transmit interrupt request is outputted.
• Goes to "0" when send data written to TDR0 to TDRA to indicate that TDR0 to TDRA
contains valid data. Changes to "1" when the data is loaded into the send shift register
and sending starts. This indicates that the TDR0 to TDRA does not contain valid data.
• This is set when "1" is written to the TSET bit of the serial status register (SSR0 to
SSRA). Use it when you want to set the TDRE bit to "1" if the arbitration lost, or bus
error is detected.
bit8
Unused bit
Read: The value is undefined.
Write: No effect.
bit11
bit10
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CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
17.2.5
Receive Data Register (RDR0 to RDRA), Transmit Data
Register (TDR0 to TDRA)
The reception data register and the transmission data register are allocated in the same
address. It works as a reception data register when read, and it works as a transmit data
register when written.
■ Receive Data Register (RDR0 to RDRA)
Figure 17.2-6 shows the bit configuration of reception data register (RDR0 to RDRA).
Figure 17.2-6 Bit Configuration of Reception Data Register (RDR0 to RDRA)
bit15
RDR
Address:
ch.0 000065H
ch.1 000075H
ch.2 000085H
ch.3 000095H
ch.4 0000A5H
ch.5 0000B5H
ch.6 0001B5H
ch.7 0001C5H
ch.8 0001D5H
ch.9 0001E5H
ch.A 0001F5H
R/W
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
: Readable/writable
The receive data register (RDR0 to RDRA) acts as a data buffer register for the received serial data.
• The serial data signal which transmitted to the serial data line (SDA pin) is converted at the shift
register, and stored in the reception data register (RDR0 to RDRA).
• The lowest bit (RDR:D0) becomes the data direction bit when the first byte * is received.
• The receive data full flag bit (SSR:RDRF) is set to "1" when the receive data is stored in the receive data
register (RDR0 to RDRA).
• The receive data full flag bit (SSR:RDRF) is automatically cleared to "0" when the receive data register
(RDR0 to RDRA) is read.
*: The first byte: Data after the (Repetition) start condition.
Notes:
• When using the reception FIFO, RDRF will be set to "1" if the FIFO receives the specified number
of data.
• While the reception FIFO is being used, the RDRF is cleared to "0" when the reception FIFO
becomes empty.
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CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
■ Transmit Data Register (TDR0 to TDRA)
Figure 17.2-7 shows the bit configuration of transmission data register (TDR0 to TDRA).
Figure 17.2-7 Bit Configuration of Transmission Data Register (TDR0 to TDRA)
bit15
TDR
Address:
ch.0 000065H
ch.1 000075H
ch.2 000085H
ch.3 000095H
ch.4 0000A5H
ch.5 0000B5H
ch.6 0001B5H
ch.7 0001C5H
ch.8 0001D5H
ch.9 0001E5H
ch.A 0001F5H
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit8
: Readable/writable
The transmit data register (TDR0 to TDRA) is a data buffer register for the serial send data.
• This is output by the MSB first in the transmission data register (TDR0 to TDRA) value to the serial
data line (SDA pin).
• The lowest bit (TDR:D0) becomes the data direction bit when the first byte is transmitted.
• The transmit data empty flag (SSR:TDRE) is cleared to "0" when send data is written to the transmit
data register (TDR0 to TDRA).
• The transmission data empty flag (SSR:TDRE) is set to "1" when transmitted to the shift register for the
transmission.
• The next transmission data should be written when following conditions are filled.
- Interrupt flag (INT bit) is "1".
- Bus error is not generated. (BER bit=0)
- Acknowledge is ACK response (0 is received as acknowledge).
• While the transmission FIFO is disabled, it is impossible to write the transmission data to the
transmission data register (TDR0 to TDRA) when the data empty flag (SSR:TDRE) is "0".
• While the transmission FIFO is used, the transmission data can be written till it reaches to the
transmission FIFO capacity even if the data empty flag (SSR:TDRE) is "0".
Note:
The transmission data register is a write-only register and the reception data register is a read-only
register. The written value and read value are different because two registers are placed in the same
address. Therefore, the commands which operate the read-modify-write (RMW) such as INC/DEC
command are not available.
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CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
17.2.6
7-bit Slave Address Mask Register (ISMK0 to ISMKA)
7-bit slave address mask register (ISMK0 to ISMKA) compares/configures each bit of
the slave address.
■ 7-bits Slave Address Mask Register (ISMK0 to ISMKA)
Figure 17.2-8 shows the bit configuration of 7-bits slave mask register (ISMK0 to ISMKA), and Table
17.2-6 shows the function of each bit.
Figure 17.2-8 Bit Configuration of 7-bits Slave Mask Register (ISMK0 to ISMKA)
bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit8
bit7
ISMK
Address
EN SM6 SM5 SM4 SM3 SM2 SM1 SM0
ch.0 000068H R/W R/W R/W R/W R/W R/W R/W R/W
ch.1 000078H
ch.2 000088H
ch.3 000098H
ch.4 0000A8H
ch.5 0000B8H
ch.6 0001B8H
SM6 to SM0
0
ch.7 0001C8H
1
ch.8 0001D8H
ch.9 0001E8H
EN
ch.A 0001F8H
0
1
R/W
bit0
(ISBA)
Initial value
01111111B
7 bits slave address mask bit
No bit comparison
Bit comparison
I2C interface enable bit
Interdiction
Permission
: Readable/writable
: Initial value
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CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
Table 17.2-6 Functional Description of Each Bit of 7-bit Slave Mask Register (ISMK0 to ISMKA)
Bit name
Function
bit15
EN:
I2C interface
enable bit
This bit enables/disables the I2C interface operation.
When set to "0": I2C interface is disabled to be operated.
When set to "1": I2C interface is enabled to be operated.
Notes:
• If the BER bit of the IBCR register is set to "1", this bit is not cleared to "0".
• Set up the baud rate generator when this bit is "0".
• Set up the 7-bit slave address and the 7-bit slave mask register when this bit is "0".
• If the EN bit is set to "0" during transmission, a pulse may be generated in the SDA/SCL
of the I2C bus.
• When FIFO is enabled, disable FIFO and write "0" into the EN bit.
• Disabling the I2C interface operation stops transmission/reception immediately.
• Before disabling the I2C interface operation (EN=0:ICCR) after writing "0" to the MSS
bit to generate a stop condition, make sure that the stop condition has been generated
(BB=0:IBSR).
bit14
to
bit8
SM6 to SM0:
7-bit slave
address mask
bits
These bits specify whether to include the 7-bit slave address and received address in the
comparison.
Bit set to "1": Comparing
Bit set to "0": Processing as result of comparison
Note:
Set this register when EN bit is "0".
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CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
17.2.7
7-bit Slave Address Register (ISBA)
The 7-bit slave address register (ISBA) is a register which sets a slave address.
■ 7-bit Slave Address Register (ISBA)
Figure 17.2-9 shows the bit configuration of the 7-bit slave address register (ISBA). Table 17.2-7 lists the
functions of each bit.
Figure 17.2-9 Bit Configuration of 7-bit Slave Address Register (ISBA)
ISBA
Address
0000X9H
R/W
bit15
bit8
(ISMK)
: Readable/writable
: Initial value
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
SAEN
SA6
SA5
SA4
SA3
SA2
SA1
SA0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SA
-
7-bit slave address setting bit
7-bit slave address
SAEN
0
1
Slave address enable bit
Interdiction
Permission
Table 17.2-7 Functional Description of Each Bit of the 7-bit Slave Address Register (ISBA)
Bit name
bit7
bit6 to bit0
Function
SAEN:
Slave address
enable bit
This bit enables the detection of slave addresses.
When "0" is set: The slave address is not detected.
When "1" is set: The ISBA and ISMK are set and compared with the first byte being
received.
SA6 to SA0:
7-bit slave
address
• The 7-bit slave address register (ISBA) compares with 7-bit data received after
(repeat) start condition is detected if the slave address detection is enabled
(SAEN=1). If the result of all bits matches, the register operates as the slave mode
and outputs the ACK. The slave addresses received during the comparison are set
into this register. (ACK is not output if SAEN=0)
• The address bit of which the ISMK register is set to "0" is not used for the
comparison.
Notes:
• Setting of reserved address is disabled.
• Set up this register when the EN bit of the ISMK register is "0".
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CHAPTER 17 I2C Interface
17.2 I2C Interface Register
17.2.8
MB91345 Series
Baud Rate Generator Register 1/Baud Rate Generator
Register 0 (BGR00 to BGRA0/BGR01 to BGRA1)
The baud rate generator register 1/the baud rate generator register0 (BGR00 to BGRA0/
BGR01 to BGRA1) set the serial clock divide ratio.
■ Bit Configuration of Baud Rate Generator Registers (BGR00 to BGRA0/BGR01 to
BGRA1)
Figure 17.2-10 shows bit configuration of baud rate generator registers 1 and 0 (BGR00 to BGRA0/BGR01
to BGRA1).
Figure 17.2-10 Bit Configuration of Baud Rate Generator Register 1/Baud Rate Generator Register 0
(BGR00 to BGRA0/BGR01 to BGRA1)
BGR
Address
0000X7H
0000X6H
(X =6,7,8,9,A,B,
1C,1D,1E,1F)
bit15 bit14 bit13 bit12 bit11 bit10

()
R/W : Readable/writable
:
Unused bit
bit9
bit8
bit7
bit6
bit5
(BGR1)
R/W
R/W
R/W
R/W
bit4
bit3
bit2
bit1
Initial value
bit0
00000000B
00000000B
(BGR0)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BGR0
Write
Read
Baud Rate Generator Registers 0
Writing to reload counter bit0 to bit7
Reading set value of BGR0
BGR1
Write
Read
Baud Rate Generator Registers 1
Writing to reload counter bit8 to bit14
Reading set value of BGR1
Unused bit
At read, value is undefined. Writing has no effect.
The baud rate generator registers set the serial clock divide ratio.
• BGR1 corresponds to upper bits and BGR0 corresponds to lower bits, and the reload value to be
counted can be written and the setting value of BGR1/BGR0 can be read.
• Once the reload value is written to the baud rate generator registers (BGR00 to BGRA0/BGR01 to
BGRA1), the reload counter starts to count.
Notes:
• Writing to the baud rate generator registers (BGR00 to BGRA0/BGR01 to BGRA1) should be
done by 16-bit access.
• Set up the baud rate generator register when the EN bit of the ISMK register is "0".
• Specify the baud rate regardless of whether the master mode or slave mode is currently used.
• In the operation mode 4 (I2C mode), use the peripheral clock at 8 MHz or more. It is prohibited to
set the baud rate generator to the value higher than 400 kbps.
530
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CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
17.2.9
FIFO Control Register 1 (FCR01, FCR11)
FIFO Control Register 1 (FCR01, FCR11) sets the FIFO test, selects the transmit or
reception FIFOs, enables the transmit FIFO interrupt, and controls the interrupt flags.
■ Bit Configuration of FIFO Control Register 1 (FCR01, FCR11)
Figure 17.2-11 shows the bit configuration of FIFO control register 1 (FCR01, FCR11), and Table 17.2-8
shows the function of each bit.
Figure 17.2-11 Bit Configuration of FIFO Control Register 1 (FCR01, FCR11)
FCRx1 (x = 0, 1)
bit15 bit14 bit13 bit12 bit11 bit10
Address
ch.0 00006AH
ch.1 00007AH
FTST1 FTST0
R/W
R/W


FLSTE FRIIE FDRQ
R/W
R/W
R/W
bit9
bit8
FTIE
FSEL
R/W
R/W
bit7
bit0
(FCR0)
Initial value
00000000B
FSEL
0
1
FIFO selection bits
Transmit FIFO:FIFO1, Receive FIFO:FIFO2
Transmit FIFO:FIFO2, Receive FIFO:FIFO1
FTIE
0
1
Transmission FIFO interrupt enable bit
Disable transmission FIFO interrupts.
Transmission FIFO Interrupt enable
FDRQ
0
1
Transmission FIFO data request bit
No transmission FIFO data request
Transmission FIFO data request
FRIIE
0
1
Reception FIFO idle detection enable bit
Reception FIFO idle detection disable
Reception FIFO idle detection enable
FLSTE
0
1
Re-transfer data lost detection enable bit
Data lost detection disable
Data lost detection enable
Unused bit
Read value is undefined. Writing has no effect.
Reserved
0
R/W

Reserved bit
Be sure to set "0" to this bit.
: Readable/writable
: Unused bit
: Initial value
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CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
Table 17.2-8 Functional Description of Each Bit in the FIFO Control Register 1 (FCR01, FCR11)
Bit name
Function
bit15,
bit14
Reserved bit
This bit is reserved bit.
Be sure to set "0" to this bit.
bit13
Unused bit
Read: The value is undefined.
Write: No effect.
bit12
FLSTE:
The retransmission
data lost detection
enable bit
This bit enables the FLST bit detection.
When the bit is set to "0": Disable detection of FLST bit
When the bit is set to "1": Enable detection of FLST bit
Note:
Set this bit to "1" after the FSET bit is set to "1".
FRIIE:
Reception FIFO idle
detection enable bit
This bit sets whether to detect a reception idle status for 8-bit time or longer under the
condition where data valid for reception FIFO exists. If the reception interrupt is enabled
(SMR:RIE=1), the reception interrupt will occur when the reception idle status is
detected.
When set to "0": The reception idle status detection is disabled.
When set to "1": The reception idle status detection is enabled.
bit10
FDRQ:
The transmit FIFO
data request bit
This is a bit to request the data of the transmit FIFO.
When this bit is set to "1", it indicates the transmission data is requested. In this case, the
transmission FIFO interrupt request is output if the transmission FIFO interrupt is
enabled (FTIE=1).
FDRQ setting conditions:
• FBYTE (for transmission)=0 (the transmission FIFO is empty)
• Reset of the transmission FIFO.
FDRQ resetting conditions:
• Writing "0" to this bit.
• When the transmit FIFO is full.
Notes:
• Writing "0" to this bit is prohibited in FBYTE (for transmission)=0.
• The FSEL bit cannot be changed while this bit is "0".
• When this bit is set to "1", there is no influence on the operation.
• When having a read-modify-write (RMW) related instruction, "1" is read out.
bit9
FTIE:
The transmit FIFO
interrupt enable bit
bit11
bit8
532
FSEL:
FIFO selecting bit
This bit enables the interrupt of the transmit FIFO.
When this bit is set to "1", an interruption occurs if the FDRQ bit is "1".
This bit selects the transmission/reception FIFO.
When the bit is set to "0": Assign to transmit FIFO:FIFO1, reception FIFO:FIFO2
When the bit is set to "1": Assign to transmit FIFO:FIFO2, reception FIFO:FIFO1
Notes:
• This bit is not cleared at a FIFO reset (FCL2, FCL1=1).
• Before updating this bit, disable the FIFO operation (FE2, FE1=0), and I2C interface
operation (ISMK:EN=0).
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
17.2.10
FIFO Control Register 0 (FCR00, FCR10)
The FIFO Control Register 0 (FCR00, FCR10) enables or disables the FIFO operation,
resets FIFO, saves the read pointer, and sets retransmit.
■ Bit Configuration of FIFO Control Register 0 (FCR00, FCR10)
Figure 17.2-12 shows the bit configuration of FIFO control register 0 (FCR00, FCR10), and Table 17.2-9
shows the function of each bit.
Figure 17.2-12 Bit Configuration of FIFO Control Register 0 (FCR00, FCR10)
FCRx0
(x = 1, 0)
Address
ch.0 00006BH
ch.1 00007BH
bit15
bit8
(FCR1)
bit1
bit0
Initial value
FLST FLD FSET FCL2 FCL1
FE2
FE1
00000000B
R/W
R/W
R/W
bit7

bit6

R/W
FIFO2 operation enable bit
FIFO2 operation disabled
FIFO2 operation enabled
0
1
CM71-10132-3E
R/W
bit2
FE2
0
1
FCL2
: Readable/writable
: Unused bit
: Initial value
R/W
bit3
FIFO1 operation enable Bit
FIFO1 operation disabled
FIFO1 operation enabled
0
1

R/W
bit4
FE1
0
1
FCL1
R/W
bit5
FIFO1 reset bit
Write
Read
No effect
"0" is always read.
FIFO1 reset
FIFO2 reset bit
Write
Read
No effect
"0" is always read.
FIFO2 reset
FSET
0
1
FIFO pointer save bit
Not saved.
Saved.
FLD
0
1
FIFO pointer reload bit
Not reloaded.
Reloaded.
FLST
0
1
FIFO re-transfer data lost flag bit
No data lost
Data lost
Unused bit
At read, "0" is always read. At write, "0" is always write.
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CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
Table 17.2-9 Functional Description of Each Bit in the FIFO Control Register 0 (FCR00, FCR10) (1 / 3)
Bit name
bit7
bit6
bit5
bit4
bit3
534
Function
Unused bit
Read: "0" is always read.
Write: Always write "0".
FLST:
The FIFO retransmit
data lost flag bit
This bit indicates that the retransmit data of the transmit FIFO is lost.
FLST setting condition:
• Data is written to FIFO when the FLSTE bit of the FIFO control register 1 (FCR1) is
"1" and the write pointer of transmit FIFO and the read pointer saved by the FSET bit
match.
FLST resetting condition:
• FIFO reset (writing "1" to FCL)
• Write "1" to FSET bit
When "1" is set to this bit, data which the read pointer saved by the FSET bit indicates
is overwritten, and retransmission cannot be set by the FLD bit even if error occurs.
When you retransmit the data while this bit is set to "1", you must reset the FIFO, and
write the data to the FIFO again.
FLD:
The FIFO pointer
reload bit
This bit reloads the data saved in the transmit FIFO by the FSET bit to the read pointer.
This bit is used to retransmit the data when a communication error occurs. Once the
retransmit setting is completed, this bit becomes "0".
Notes:
• Data is being reloaded to the read pointer while this bit is set to "1". Therefore, do
not write reset other than FIFO reset.
• Do not set this bit to "1" during FIFO enable status or the transmission.
• First, set the TIE bit to "0", write "1" into this bit, enable the transmission FIFO,
and then set the TIE bit to "1".
FSET:
The FIFO pointer save
bit
This is a bit to save the read pointer of the transmit FIFO.
If you save the read pointer before the transmission, you may retransmit as long as
FLST bit is set to "0" even if a communication error occurred.
When set to "1": Current read pointer value is saved.
When the bit is set to "0": No effect.
Note:
Set this bit to "1" while number of transmission bytes (FBYTE) indicates "0".
FCL2:
FIFO2 reset bit
This bit sets FIFO2.
When this bit is set to "1", the internal status of FIFO is initialized.
Only the FCR0:FLST bit is initialized. Other bits of the FCR1/FCR0 register are
retained as is.
Notes:
• Execute FIFO2 reset after disabling FIFO2.
• Set the transmission FIFO interrupt enable bit to "0" before the operation.
• Number of valid data for the FBYTE2 register is "0".
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CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
Table 17.2-9 Functional Description of Each Bit in the FIFO Control Register 0 (FCR00, FCR10) (2 / 3)
Bit name
bit2
bit1
Function
FCL1:
FIFO1 reset bit
This bit resets FIFO1.
When this bit is set to "1", the internal status of FIFO is initialized.
Only the FCR0:FLST bit is initialized. Other bits of the FCR1/FCR0 register are
retained as is.
Notes:
• Execute FIFO1 reset after disabling FIFO1.
• Set the transmission FIFO interrupt enable bit to "0" before the operation.
• Number of valid data for the FBYTE1 register is "0".
FE2:
The FIFO2 operation
enable bit
This bit enables or disables the FIFO2 operation.
• If FIFO2 is used, set this bit to "1".
• If this is selected as a reception FIFO by FSEL bit, this bit is cleared to "0" in case of
the reception error, and this bit cannot be set to "1" until the reception error is cleared.
• To use as the transmission FIFO, set this bit to "1" or "0" when transmission data is
empty (TDRE=1). To use as the reception FIFO, set this bit to "1" or "0" when
reception data is empty (RDRF=0).
• FIFO2 state is maintained even when FIFO2 is disabled.
Notes:
• Change enable/disable operation when the BB bit is "0" or the INT bit is "1".
• When the reception FIFO is selected, and if you want to detect the reserved address
and to perform slave transmission operation, set this bit to "0" and ACKE=0 using
the interrupt by the reserved address detection.
• When the reception FIFO is used, and the RDRF bit of the SSR is "1" while this bit
is changed from "1" to "0", the reception FIFO is not disabled until the RDRF bit is
set to "0".
• When the transmission FIFO is used and data exists in FIFO2, and if you want to
change this bit from "0" to "1", set the FIE bit to "0" and write "1" into this bit to
set the TIE bit to "1".
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CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
Table 17.2-9 Functional Description of Each Bit in the FIFO Control Register 0 (FCR00, FCR10) (3 / 3)
Bit name
bit0
536
FE1:
The FIFO1 operation
enable bit
Function
This bit enables or disables the FIFO1 operation.
• If FIFO1 is used, set this bit to "1".
• If this is selected as a reception FIFO by FSEL bit, this bit is cleared to "0" in case of
the reception error, and this bit cannot be set to "1" until the reception error is cleared.
• To use as the transmission FIFO, set this bit to "1" or "0" when transmission data is
empty (TDRE=1). To use as the reception FIFO, set this bit to "1" or "0" when
reception data is empty (RDRF=0).
• FIFO1 state is maintained even when FIFO1 is disabled.
Notes:
• Change enable/disable operation when the BB bit is "0" or the INT bit is "1".
• When the reception FIFO is selected, and if you want to detect the reserved address
and to perform slave transmission operation, set this bit to "0" and ACKE=0 using
the interrupt by the reserved address detection.
• When the reception FIFO is used, and the RDRF bit of the SSR is "1" while this bit
is changed from "1" to "0", the reception FIFO is not disabled until the RDRF bit is
set to "0".
• When the transmission FIFO is used and data exists in FIFO1, and if you want to
change this bit from "0" to "1", set the FIE bit to "0" and write "1" into this bit to
set the TIE bit to "1".
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
17.2.11
FIFO Byte Register (FBYTE01, FBYTE02, FBYTE11,
FBYTE12)
The FIFO byte register (FBYTE01, FBYTE02, FBYTE11, FBYTE12) indicates the number
of the data available for FIFO. In addition, you can set whether the reception interrupt
should occur when the reception FIFO receives the specified number of data.
■ Bit Configuration of FIFO Byte Register (FBYTE01, FBYTE02, FBYTE11, FBYTE12)
Figure 17.2-13 shows the bit configuration of FIFO byte register (FBYTE01, FBYTE02, FBYTE11,
FBYTE12).
Figure 17.2-13 Bit Configuration of FIFO Byte Register (FBYTE01, FBYTE02, FBYTE11, FBYTE12)
FBYTE01
00006DH
FBYTE02
00006CH
FBYTE11
00007DH
FBYTE12
00007CH
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
bit7
bit6
bit5
(FBYTE2)
R/W
R/W
R/W
R/W
R/W
bit4
bit3
bit2
bit1
bit0
00000000B
00000000B
(FBYTE1)
R/W
R/W
R/W
R/W : Readable/writable
Read (the number of valid data)
At transmission : Number of data written to FIFO and
not transmitted
At reception
: Number of data received in FIFO
Write (the number of transmission)
At transmission : Set "00H"
At reception
: Set number of data which generates
the reception interrupt.
R/W
R/W
R/W
R/W
R/W
Initial value
R/W
R/W
R/W
FBYTE1
Write
Read
Displaying the number of FIFO1 data bit
Set the number of transmission
Read the number of valid data
FBYTE2
Write
Read
Displaying the number of FIFO2 data bit
Set the number of transmission
Read the number of valid data
The FBYTE register indicates the number of valid data pieces of FIFO. It operates as follows according to
the setting of the FCR1:FSEL bit.
Table 17.2-10 Indicate Number of Data
FSEL
FIFO selection
Indicate number of data
0
FIFO2: Reception FIFO, FIFO1: Transmission FIFO
FIFO2: FBYTE2, FIFO1: FBYTE1
1
FIFO2: Transmission FIFO, FIFO1: Reception FIFO
FIFO2: FBYTE2, FIFO1: FBYTE1
• The initial value for the number of FBYTE register is "08H".
• Specify the data count that causes the reception interrupt flag to be generated in FBYTE of the reception
FIFO. The interrupt flag (RDRF) is set to "1" if the specified number of the transfers matches the data
displayed for the FBYTE register.
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CHAPTER 17 I2C Interface
17.2 I2C Interface Register
MB91345 Series
• While the reception FIFO idle detection enable bit (FRIIE) is "1" and the data count that exists in the
reception FIFO is under the transfer count, the interrupt flag (RDRF) is set to "1" when the reception
idle status continues for 8 or more clocks in the baud rate clock. When having read RDR during the
eight clocks count, the counter is reset to "0", and then it counts another eight clocks. When the
reception FIFO is disabled, the counter is reset to "0". If you enable the reception FIFO when the data
remains in the FIFO, the counting process will be started again.
• To receive data with the master operation (master reception), set the TIE bit to "0", specify the number
of data pieces to receive in the FBYTE register of the transmission FIFO, and write "0" into the FDRQ
bit. The clock of the SCL is output for the amount of specified data, and then the INT bit turns to "1". If
you want to set "1" into the TIE bit, set "1" after the FDRQ turns to "1".
Notes:
• Except for the case where you receive data with the master operation, set FBYTE for the
transmission FIFO to "800H".
• Set the number of transmission data pieces to receive data with the master operation when the
transmission FIFO is empty and the TIE bit is "0".
• To disable the I2C interface (EN=0) while data is being received with the master operation, do it
after disabling the transmission/reception FIFO.
• Set data of "1" or more to the FBYTE for reception FIFO.
• Execute change operation after disabling the transmit/reception operation.
• This register cannot use the read-modify-write (RMW) related commands.
• Setting that exceeds capacity of FIFO is disabled.
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CHAPTER 17 I2C Interface
17.3 I2C Interface Interruption
MB91345 Series
17.3
I2C Interface Interruption
The interrupt request for the I2C interface interrupt can be generated with the following
factors:
• After first byte/data is transmitted and received
• Stop condition
• Repeat start condition
• FIFO transmission data request
• FIFO reception data completion
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CHAPTER 17 I2C Interface
17.3 I2C Interface Interruption
MB91345 Series
■ I2C Interface Interruption
Table 17.3-1 shows the interrupt control bit and interrupt causes of I2C interface.
Table 17.3-1 Interrupt Control Bits and Interrupt Causes of I2C Interface
Interrupt
type
Interrupt
request
flag bit
Flag
register
Interrupt Factor
Interrupt
factor enable
bit
Clear of the interrupt request flag
After the transmission/
reception of the first byte*1
After the transmission/
reception of data *1
Writing "0" into the interrupt flag bit
(IBCR:INT)
Bus error detection
Arbitration lost detected
INT
IBCR
Reception of data
specified with the FBYTE
setting value
IBCR:INTE
Write "0" into the interrupt flag bit
(IBCR:INT) after reading the received
data (RDR) until the reception FIFO
becomes empty.
The receive idle state of 8bit time or more is
detected when the FRIIE is
"1" and valid data exists in
the reception FIFO.
Reception
Reserved address detection
Reading the received data (RDR)
After data reception
RDRF
SSR
Reception of data
specified with the FBYTE
setting value
SMR: RIE
Read received data (RDR) until the
reception FIFO becomes empty.
ORE
SSR
Overrun error
Write "1" into the reception error flag bit
(SSR:REC)
SPC
IBSR
Stop condition
Write "0" into the stop condition detection
bit
IBCR:CNDE
RSC
IBSR
Repetitive start condition
The transmit register is
empty
TDRE
SSR
FDRQ
FCR1
Transmit
Write "1" into the
transmission buffer empty
flag set bit (SSR:TSET)
The transmit FIFO is
empty
SMR:TIE
FCR1:FTIE
Write "0" into the repetitive start detection
flag bit (IBSR:RSC)
Writing to the transmit data (TDR), or
writing "1" to the transmit FIFO operation
enable bit when the transmit FIFO
operation enable bit is "0" and the valid
data exists in the transmit FIFO
(Resend) *2
Writing "0" to the FIFO transmit data
request bit or the transmit FIFO is full.
*1: Interrupt does not occur when correct data can be transmitted/received and the TDRE is set to "0". This is for
supporting DMA transfer. To generate the INT flag during data transmission/reception, the TDRE bit must be "1"
before the timing when the INT flag is set.
*2: Set the TIE bit to "1" after the TDRE bit becomes "0".
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CHAPTER 17 I2C Interface
17.3 I2C Interface Interruption
MB91345 Series
17.3.1
Operation of I2C Interface Communication
The I2C interface establishes communication using two two-way bus line, a serial data
line (SDA) and a serial clock line (SCL).
■ I2C Bus Start Condition
Start condition of I2C bus is shown below.
Figure 17.3-1 Start Condition
SDA
SCL
Start condition
■ I2C Bus Stop Condition
Stop condition of I2C bus is shown below.
Figure 17.3-2 Stop Condition
SDA
SCL
Stop condition
■ I2C Bus Repeat Start Condition
Repeat start condition of I2C bus is shown below.
Figure 17.3-3 Repeat Start Condition
SDA
SCL
ACK
Repeat start condition
CM71-10132-3E
ACK : Acknowledge
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CHAPTER 17 I2C Interface
17.3 I2C Interface Interruption
17.3.2
MB91345 Series
Master Mode
The master mode makes the I2C bus generate the start condition and outputs a clock to
the I2C bus. When the I2C bus is idle (SCL=H, SDA=H), setting "1" into the MSS bit of the
IBCR register activates the master mode, and the ACT bit of the IBCR register turns to
"1".
■ Generation of Start Condition
The following condition output the start condition.
When SDA=H, SCL=H, EN=1 and BB=0, writing "1" to MSS bit
When the start condition is output to the I2C bus, the ACT bit is set to "1". Then, the BB bit is set to "1"
when the start condition is received, indicating that the I2C bus is being communicated (see Figure 17.3-4).
Figure 17.3-4 Output of Start Condition and Relation Between each bit
Start condition
SDA
A6
A5
SCL
1
2
BB bit
MSS bit
"1" write
ACT bit
TRX bit
FBT bit
TDRE bit
A6 : Address bit 6
A5 : Address bit 5
Note:
542
In the operation mode 4 (I2C mode), use the peripheral clock at 8 MHz or more. It is prohibited to set
the baud rate generator to the value higher than 400 kbps.
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CHAPTER 17 I2C Interface
17.3 I2C Interface Interruption
MB91345 Series
■ Slave Address Output
When the start condition is output, the data specified to the TDR register is output from bit7 as an address.
When FIFO is enabled, the data of the TDR register which was written first is output. Bit0 is used as a data
direction bit (R/W). When the data direction bit (R/W) is "0", the data is written (from master to slave).
Finish the address setting to the TDR register before writing MSS=1 or SCC=1.
Output timing of address and data direction are shown in Figure 17.3-5 and Figure 17.3-6.
Figure 17.3-5 Address and Data Direction (When FIFO is Disabled)
1
2
3
4
5
6
7
8
SCL
SDA
A6(D7) A5(D6) A4(D5) A3(D4) A2(D3) A1(D2) A0(D1) R/W(D0)
ACK
BB bit
MSS bit *
TDRE bit
INT bit
<Reservation address detection>
RSA bit
RDRF bit
INT bit
SCL is "L" while INT has been "1"
A6 to A0 : Address
D7 to D0 : TDR register bit
R/W : Data derection (Write in "L" state)
ACK : Acknowledge (Acknowledge in "L" state. Output from slave)
* : Set an address to the TDR register before writing "1" to the MSS bit.
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CHAPTER 17 I2C Interface
17.3 I2C Interface Interruption
MB91345 Series
Figure 17.3-6 Address and Data Direction (When Transmission/Reception FIFO is Enabled)
1
2
3
4
5
6
7
8
SCL
SDA
A6(D7) A5(D6) A4(D5) A3(D4) A2(D3) A1(D2) A0(D1) R/W(D0)
ACK
BB bit
MSS bit *1
INT bit *2
<Reservation address derection>
RSA bit
RDRF bit
INT bit
A6 to A0 : Address
SCL is "L" while INT has been "1"
D7 to D0 : TDR register bit
R/W : Data detection (Write in "L" state)
ACK : Acknowledge (Acknowledge in "L" state. Output from slave)
*1 : Set an address to the TDR register before writing "1" to the MSS bit.
*2 : When acknowledge is "L" and R/W=L, data exists in transmit FIFO, or when acknowledge is "L" and R/W=H,
the INT bit can not be "1" if no data exists in reception FIFO.
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CHAPTER 17 I2C Interface
17.3 I2C Interface Interruption
MB91345 Series
■ Acknowledge Reception by the First Byte Transmit
When the data direction bit (R/W) is output, the I2C interface receives an acknowledge from the slave.
Operation in FIFO enabled and FIFO disabled is shown below.
Table 17.3-2 Operation after Transmission/Reception of Acknowledge (RSA Bit=0)
Transmission Reception Transmission
FIFO
FIFO
FIFO status
Data
Operation immediately after acknowledge reception
Reception
direction
FIFO
Acknowledge is ACK
Acknowledge is NACK
status bit (R/W)
0
Disable
Disable


1
No data
0
Disable
Enable

1
0
Enable
Disable


1
No data
0
Enable
Enable

CM71-10132-3E
When the TDRE bit is "1",
the INT bit is set to "1" and
wait occurs. If the TDRE bit
is "0", the INT bit is kept to
"0" and wait does not occur.
When the TDRE bit is "1",
the INT bit is set to "1" and
The INT bit is set to "1"
wait occurs. If the TDRE bit
and wait occurs.
is "0", the INT bit is kept to
"0" and wait does not occur.
If the TDRE bit is "1", the
INT bit is set to "1" and wait
occurs. If the TDRE bit is
"0", the INT bit is kept to "0"
and wait does not occur.
The INT bit is set to "1" and The INT bit is set to "1"
and wait occurs.
wait occurs.
Data
-
When the TDRE bit is "1",
the INT bit is set to "1" and
wait occurs. If the TDRE bit
is "0", the INT bit is kept to
"0" and wait does not occur.
The INT bit is set to "1" and The INT bit is set to "1"
and wait occurs.
wait occurs.
Data

When the TDRE bit is "1",
the INT bit is set to "1" and
The INT bit is set to "1"
wait occurs. If the TDRE bit
and wait occurs.
is "0", the INT bit is kept to
"0" and wait does not occur.
1
If the TDRE bit is "1", the
INT bit is set to "1" and wait
occurs. If the TDRE bit is
"0", the INT bit is kept to "0"
and wait does not occur.
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● FIFO disable (Both transmit FIFO and reception FIFO are disabled)
• When the RSA bit is "0", and when the TDRE bit is "1" after an acknowledge is received, the interrupt
flag (INT) is set to "1", the SCL is kept to "L", and wait occurs. When "0" is written into the interrupt
flag, the flag is set to "0" and the wait is canceled. If the TDRE bit is "0" and ACK is received, the
interrupt flag is not set to "1" and a clock is generated for the SCL.
• If the RSA bit is "1", the interrupt flag (INT) is set to "1", the SCL is kept to "L", and wait occurs after
an reserved address is received (before an acknowledge is received). After the RDR register is read, the
ACKE bit and transmission data are set. When "0" is written into the interrupt flag, the flag is set to "0"
and the wait is canceled.
• The received acknowledge is set into the RACK bit. The RACK bit is checked during the wait. If it is
NACK, "0" is written into the MSS bit or "1" is written into the SCC bit, and the stop condition or
repetitive start condition is generated respectively.
● FIFO enable
• Before setting "1" into the MSS bit, you need to set the following for FIFO:
- To transmit data to the slave (Data direction bit=0), set the data including the slave address to the
transmission FIFO.
- To receive data from the slave (Data direction bit=1), set the number of reception data pieces to
receive into the FIFO byte count register. Then, write dummy data into the transmission data register
for the amount of the slave address and the data direction bit to be received.
• When the RSA bit is "0" and the received acknowledge is ACK, the interrupt flag (INT) is not set to "1",
and the data is transmitted/received according to the data direction bit setting (no wait). If the
acknowledge is NACK, the interrupt flag (INT) is set to "1", the SCL is kept to "L" and wait occurs.
• The received acknowledge is stored in the RACK bit. If the RACK bit is confirmed that it is NACK for
waiting, writing "0" to the MSS bit or writing "1" to the SCC bit generates the stop condition or the
repeat start condition. At this time, the INT bit is automatically cleared to "0".
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Figure 17.3-7 Acknowledge (FIFO Disabled, RSA=0, ACK Response)
"L" by INT bit
Data
SCL
SDA
R/W
ACK
"0" write
INT bit
RACK bit
FBT bit
Write to TDR register
TDRE bit
Wait to the address
• If the RSA bit is "0", wait is after acknowledge.
• If the RSA bit is "1", wait is before acknowledge.
That does not depend on the setting of WSEL.
Figure 17.3-8 Acknowledge (FIFO Disabled, RSA=0, NACK Response)
"L" by INT bit
SCL
SDA
R/W
NACK
"0" write
Stop condition
INT bit
MSS bit
RACK bit
FBT bit
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Figure 17.3-9 Acknowledge (FIFO Disabled, RSA=1, ACK Response)
"L" by INT bit
Data
SCL
SDA
R/W
ACK
"0" write
INT bit
RACK bit
FBT bit
RSA bit
Read RDR register
RDRF bit
Figure 17.3-10 Acknowledge (FIFO Disabled, RSA=1, NACK Response)
"L" by INT bit
SCL
SDA
R/W
NACK
"0" write
Stop condition
INT bit
MSS bit
RACK bit
FBT bit
RSA bit
Read RDR register
RDRF bit
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Figure 17.3-11 Acknowledge (FIFO Enabled, Transmission FIFO with Data, Reception FIFO without Data,
RSA=0, ACK Response)
Data
SCL
SDA
R/W
ACK
INT bit
RACK bit
FBT bit
TDRE bit
■ Data Transmission by Master
When the data direction bit (R/W) is "0", data is sent from the master. The slave returns a response of ACK
or NACK every time one byte of data is transmitted.
The location where wait occurs varies as follows depending on the WSEL bit setting:
Table 17.3-3 WSEL Bit at Master Data Transfer
WSEL bit
Operation
0
In the second and later bytes, when an acknowledge is returned in the condition where the TDRE bit is "1"
or arbitration lost is detected, the interrupt flag (INT) is set to "1", the SCL is set to "L", and wait occurs. If
FIFO is enabled, when an acknowledge is returned in the condition where arbitration lost is detected or there
is no more valid data for the transmission data register (TDRE=1), the interrupt flag (INT) is set to "1" and
wait occurs.
1
In the second and later bytes, when the master send one byte of data in the condition where the TDRE bit is
"1" or when arbitration lost is detected, the interrupt flag (INT) is set to "1", the SCL is set to "L", and wait
occurs. If FIFO is enabled, when arbitration lost is detected or when there is no valid data for the
transmission data register (TDRE=1) after data is transmitted, the interrupt flag (INT) is set to "1" and wait
occurs.
Note that in the following case, the interrupt flag (INT) is set when the acknowledge is returned regardless
of the WSEL setting:
• If NACK is received when other conditions than stop condition (MSS=0, ACT=1) are set.
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The following is an example procedure to send data to the slave:
● When sending to other than a reservation address.
• If transmit FIFO is disabled
(1) Set the slave address (including the data direction bit) into the TDR register and write "1" into the
MSS bit.
(2) Interrupt flag (INT) is "1" by receiving ACK after sending slave address.
(3) Write data which is sent to the TDR register.
(4) Upon the WSEL bit update, write "0" into the interrupt flag (INT) and cancel the wait for the I2C
bus.
(5) If WSEL=0 when one byte of data is sent, set the interrupt flag to "1" after an acknowledge is
received and wait for the I2C bus. Repeat steps (2) through (4) until the specified number of data
pieces is sent. If, however, WSEL=1 and NACK is received after the wait is canceled, an interrupt
occurs again after an acknowledge is received to wait for the bus.
(6) Set "0" into the MSS bit or "1" into the SCC bit to generate the stop condition or repetitive start
condition respectively.
• If transmit FIFO is enabled
(1) Write the slave address (including the data direction bit) and transmission data into the TDR
register.
(2) Write "1" to the MSS bit setting the WSEL bit.
(3) If NACK is received during the transmission, set the interrupt flag (INT) to "1" immediately after
that and wait for the I2C bus. If all the received response is ACK and after the last byte is
transmitted, set the interrupt flag to "1" according to the WSEL setting and wait for the I2C bus.
(4) Write "0" into the MSS bit and generate the stop condition.
● When sending to the reservation address
• If transmit FIFO is disabled
(1) Set a reserved address into the TDR register as a slave address, and write "1" into the MSS bit.
(2) Interrupt flag (INT) is "1" after sending slave address.
(3) Read the RDR register and check the reservation address. *
(4) Write data which is sent to the TDR register.
(5) Upon the WSEL bit update, write "0" into the interrupt flag (INT) and cancel the wait for the I2C
bus.
(6) If WSEL=0 after one byte of data is sent, set the interrupt flag to "1" after an acknowledge is
received and wait for the I2C bus. If WSEL=1, do it immediately after sending one bye of data.
Repeat steps (4) through (6) until the specified number of data pieces is sent. If, however, WSEL=1
and NACK is received after the wait is canceled, an interrupt occurs again after an acknowledge is
received to wait for the bus.
(7) Setting "0" to the MSS bit or "1" to the SCC bit generates the stop condition or the repeat start
condition.
* : When it is a multi master and the reservation address is a general call, it is necessary to confirm
whether it works as master or slave at next data setting the ACKE bit to "1" and the WSEL bit to "1" if
there is a possibility to work as slave because of generation of arbitration lost.
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• If transmit FIFO is enabled
(1) Set a reserved address into the TDR register as a slave address, and write "1" into the MSS bit.
(2) Interrupt flag (INT) is "1" after sending slave address.
(3) Read the RDR register and check the reservation address. *
(4) Write all transmission data into the TDR register (if the transmission FIFO becomes full, write data
to that amount).
(5) If NACK is received during the transmission, set the interrupt flag (INT) to "1" immediately after
that and wait for the I2C bus. If all the received response is ACK and after the last byte is
transmitted, set the interrupt flag to "1" according to the WSEL setting and wait for the I2C bus.
(6) Set "0" into the MSS bit or "1" into the SCC bit to generate the stop condition or repetitive start
condition respectively.
* : When it is a multi master and the reservation address is a general call, it is necessary to confirm
whether it works as master or slave at next data setting the ACKE bit to "1" and the WSEL bit to "1" if
there is a possibility to work as slave because of generation of arbitration lost.
Notes:
• To change the IBCR register during transmission, change it while the interrupt flag (INT) is "1".
• When the WSEL bit is changed, the new setting is used in the generation condition of the interrupt
flag (INT) for the next data.
• When the TDRE is "1" during data transmission and if transmission data is written into the TDR
register and an ACK response is detected, the interrupt flag (INT) is not set to "1" and the written
data is transmitted.
• When the TDRE is "1" during data reception and if transmission data is written into the TDR
register and ACK is returned, the interrupt flag (INT) is not set to "1" and only the RDRF is set to
"1" (When the reception FIFO is enabled and the data is received for the length set in the FBYTE
register).
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Figure 17.3-12 Master Transmit Interrupt 1 by FIFO Disabled (WSEL=0, RSA=0)
S
Slave Address
W ACK
Data
ACK
1
Data
ACK Data
ACK P or Sr
3
2
2
S : Start condition
W : Data direction bit (write direction)
P : Stop condition
Sr : Repeat start condition
: Interrupt by INTE=1
: Interrupt by CNDE=1
1 Interrupt generation by slave address transmit + direction bit transmit + acknoledge reception.
Write INT=0 after writing trasmit data to the TDR register.
2 Interrupt generation by 1 byte transmit + acknowledge reception.
Write INT=0 after writing trasmit data to the TDR register.
3 Interrupt generation by 1 byte transmit + acknowledge reception.
Set MSS=0 or MSS=1, and SCC=1.
Note: The TDRE bit is "1" when generating interrupt flag (INT).
Figure 17.3-13 Master Transmit Interrupt 2 by FIFO Disabled (WSEL=1, RSA=0, ACK Response)
S
Slave Address
W ACK
Data
1
ACK
Data
2
ACK Data
2
ACK P or Sr
3
S : Start condition
W : Data direction bit (write direction)
P : Stop condition
Sr : Repeat start condition
: Interrupt by INTE=1
: Interrupt by CNDE=1
1 Interrupt generation by slave address transmit + direction bit transmit + acknoledge reception.
Write INT=0 after writing trasmit data to the TDR register.
2 Interrupt is generated by 1 byte transmit.
Write INT=0 after writing trasmit data to the TDR register.
3 Interrupt is generated by 1 byte transmit.
Set MSS=0 or MSS=1, and SCC=1.
Note: The TDRE bit is "1" when generating interrupt flag (INT).
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Figure 17.3-14 Master Transmit Interrupt 3 by FIFO Disabled (WSEL=1, RSA=0, NACK Response)
S
Slave Address W ACK
Data
ACK
1
Data
ACK Data
2
2
NACK P or Sr
3
S : Start condition
W : Data direction bit (write direction)
P : Stop condition
Sr : Repeat start condition
: Interrupt by INTE=1
: Interrupt by CNDE=1
1 Interrupt generation by slave address transmit + direction bit transmit + acknoledge reception.
Write INT=0 after writing trasmit data to the TDR register.
2 Interrupt is generated by 1 byte transmit.
Write INT=0 after writing trasmit data to the TDR register.
3 Interrupt is generated by 1 byte transmit.
Set MSS=0 or MSS=1, and SCC=1.
Note: The TDRE bit is "1" when generating interrupt flag (INT).
Figure 17.3-15 Master Transmit Interrupt 4 by FIFO Disabled
(WSEL=1, RSA=0, NACK Response during Master Transmit)
S
Slave Address
W ACK
Data
1
ACK
Data
2
ACK Data
2
NACK P or Sr
2
3
S : Start condition
W : Data direction bit (write direction)
P : Stop condition
Sr : Repeat start condition
: Interrupt by INTE=1
: Interrupt by CNDE=1
1 Interrupt generation by slave address transmit + direction bit transmit + acknoledge reception.
Write INT=0 after writing trasmit data to the TDR register.
2 Interrupt is generated by 1 byte transmit.
Write INT=0 after writing trasmit data to the TDR register.
3 Interrupt is generated by NACK response.
Set MSS=0 or MSS=1, and SCC=1.
Note: The TDRE bit is "1" when generating interrupt flag (INT).
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Figure 17.3-16 Master Transmit Interrupt 5 by FIFO Disabled (WSEL=1->"0", RSA=0, ACK Response)
S
Slave Address W
ACK
Data
ACK
Data
ACK Data
2
2
1
ACK P or Sr
3
S : Start condition
W : Data direction bit (write direction)
P : Stop condition
Sr : Repeat start condition
: Interrupt by INTE=1
: Interrupt by CNDE=1
1 Interrupt generation by slave address transmit + direction bit transmit + acknoledge reception.
Write INT=0 after writing trasmit data to transmit buffer.
2 Interrupt is generated by 1 byte transmit.
Write WSEL=0 and INT=0 after writing trasmit data to transmit buffer.
3 Interrupt is generated by 1 byte transmit.
Set MSS=0 or MSS=1, and SCC=1.
Note: The TDRE bit is "1" when generating interrupt flag (INT).
Figure 17.3-17 Master Transmit Interrupt 6 by FIFO Disabled (WSEL=0, RSA=1)
S
Slave Address
W ACK
1
Data
ACK
Data
2
ACK Data
2
ACK P or Sr
3
S : Start condition
W : Data direction bit (write direction)
P : Stop condition
Sr : Repeat start condition
: Interrupt by INTE=1
: Interrupt by CNDE=1
1 Interrupt is generated by slave address (reservation address) transmit+ direction bit transmit
+ acknoledge reception.
Write INT=0 after writing trasmit data to the TDR register.
2 Interrupt generation by 1 byte transmit + acknowledge reception.
Write INT=0 after writing trasmit data to the TDR register.
3 Interrupt generation by 1 byte transmit + acknowledge reception.
Set MSS=0 or MSS=1, and SCC=1.
Note: The TDRE bit is "1" when generating interrupt flag (INT).
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Figure 17.3-18 Master Transmit Interrupt 7 by FIFO Enabled (WSEL=0, RSA=0, ACK Response)
S
Slave Address
W ACK
Data
ACK
Data
ACK Data
ACK P or Sr
2
1
S : Start condition
W : Data direction bit (write direction)
P : Stop condition
Sr : Repeat start condition
: Interrupt by INTE=1
: Interrupt by CNDE=1
1 Interrupt is generated by the case that transmit FIFO is empty
Write INT=0 after writing trasmit data to transmit FIFO.
2 Interrupt is generated by the last byte transmit (transmit FIFO is empty) + acknowledge reception.
Set MSS=0 or MSS=1, and SCC=1.
Figure 17.3-19 Master Transmit Interrupt 8 by FIFO Enabled (WSEL=1, RSA=0)
S
Slave Address
W ACK
Data
ACK
Data
ACK Data
1
ACK P or Sr
2
S : Start condition
W: Data direction bit (Write direction)
P: Stop condition
Sr: Repeat start condition
: Interrupt by INTE=1
: Interrupt by CNDE=1
1 Interrupt is generated by the transmit FIFO is enpty.
Write INT=0 after writing transmit-data to transmit FIFO
2 Interrupt is generated by transmit of the last byte (the transmit FIFO is enpty).
Set MSS=0 or MSS=1, and SCC=1.
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Figure 17.3-20 Master Transmit Interrupt 9 by FIFO Enabled
(WSEL=1, RSA=0, NACK Response)
S
Slave Address
W ACK
Data
ACK
Data
ACK Data
1
NACK P or Sr
2
S : Start condition
W : Data direction bit (Write direction)
P : Stop condition
Sr : Repeat start condition
: Interrupt by INTE=1
: Interrupt by CNDE=1
1 Interrupt is generated by the transmit FIFO is enpty.
Write INT=0 after writing transmit-data to transmit FIFO
2 Interrupt is generated by NACK response.
Set MSS=0 or MSS=1, and SCC=1.
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■ Data Reception by Master
If the data direction bit (R/W) is "1", the data sent from the slave is received.
If FIFO is disabled and the TDRE bit is "1", the master generates wait every time one byte of data is
received (INT=1, RDRF=1), and according to the WSEL bit, returns an ACK or NACK response based on
the ACKE bit setting of the IBCR register. When the TDRE bit is "0" and the ACKE bit setting of the
IBCR register is ACK, wait does not occur (INT=0) and the next data is received. If the ACKE bit setting is
NACK, wait occurs (INT=1).
If FIFO is enabled, the RDRF bit is set after data of the same number of bytes as the reception byte setting
is received. The interrupt flag is set when the TDRE bit is "1" to wait for the I2C bus. If WSEL=0, a NACK
response is returned and the interrupt flag is set to "1" when the TDRE bit turns to "1". If WSEL=1, wait
occurs after the last byte is received. The ACKE bit is set during the wait, the interrupt flag is cleared to
"0", and then an ACK or NACK response is returned according to the ACKE setting. Even when NACK is
output, the data is stored in the reception FIFO as received data.
See the following section for the wait by interrupt.
Table 17.3-4 WSEL Bit at Receive Master Data
WSEL bit
Operation
0
In the second and later bytes, when an acknowledge is received in the condition where
the TDRE bit is "1", the interrupt flag (INT) is set to "1", the SCL is set to "L", and
wait occurs.
1
In the second and later bytes, when the master receives one byte of data in the
condition where the TDRE bit is "1", the interrupt flag (INT) is set to "1", the SCL is
set to "L", and wait occurs.
The following is an example procedure to receive data from the slave:
• When the receive FIFO is disabled
(1) Set the slave address (including the data direction bit) into the TDR register and write "1" into the
MSS bit.
(2) ACK is received after transferring the slave address, and the interrupt flag is set to "1".
(3) Upon the WSEL bit update, write "0" into the interrupt flag (INT) and cancel the wait for the I2C
bus.
(4) If WSEL=0 after one byte of data is received, set the interrupt flag to "1" after an acknowledge is
sent and wait for the I2C bus. If WSEL=1, do it immediately after one byte of data is received.
Repeat steps (2) through (4) until the specified number of data pieces is received.
(5) After the last data is received, output NACK, set "0" into the MSS bit or "1" to the SCC bit and
generate the stop condition or repetitive start condition respectively.
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• When the transfer FIFO is enabled.
(1) Set receiving number to FBYTE register
(2)Write dummy data into the TDR register for the amount of the slave address (including the data
direction bit) and the data to be received.
(3) Write "1" to MSS bit.
(4) ACK keeps responding, and being received during TDRE bit=0. If the number of data pieces
specified in FBYTE is received during the reception, set RDRF to "1". Read out the RDR register
when RDRF has turned to "1".
(5) If WSEL=0 when the TDRE bit turns to "1", set the interrupt flag to "1" after NACK is output and
wait for the I2C bus. If WSEL=1, do it immediately after receiving one byte of data.
(6) If WSEL=1, set the ACKE bit to "0". If WSEL=0, setting the ACKE bit is unnecessary. Set the MSS
bit to "0" or the SCC bit to "1" to generate the stop condition or repetitive start condition
respectively.
Notes:
• When TDRE is "0", output the acknowledge according to the ACKE bit setting even if an overrun
error is generated. Then, perform the following:
• To change the IBCR register during transmission, change it while the interrupt flag (INT) is "1".
• During the master reception, write dummy data into the TDR register. If the TDRE bit is "0" at the
timing when the interrupt flag (INT) turns to "1", the interrupt flag (INT) remains "0" and the next
data is received.
• If you receive data when the reception FIFO is enabled and WSEL=0, the RDRF bit turns to "1"
after the last bit is received, and the interrupt flag (INT) turns to "1" after ACK is transmitted.
Figure 17.3-21 Master Receive Interrupt 1 by FIFO Disabled (WSEL=0, RSA=0)
S
Slave Address
R ACK
Data
ACK
Data
ACK
1
Data
2
NACK P or Sr
3
: Interrupt by INTE=1.
: Interrupt by CNDE=1.
1 Interrrupt generation by slave address transmit + direction bit transmit + acknowledge reception
Interrupt is cleared to "0" by writing INT=0.
2 Interrrupt generation by 1 byte reception + acknowledge transmit
Write INT=0 setting ACKE=0 after reading reception data.
3 Interrrupt generation by 1 byte reception + acknowledge transmit
Set MSS=0 or MSS=1, and SCC=1.
Note: The TDRE bit is "1" when the interrupt flag (INT) is generated.
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Figure 17.3-22 Master Receive Interrupt 2 by FIFO Disabled (WSEL=1, RSA=0)
S
Slave Address
R ACK
Data
ACK
Data
2
1
ACK
Data NACK P or Sr
3
2
: Interrupt by INTE=1.
: Interrupt by CNDE=1.
1 Interrrupt generation by slave address transmit + direction bit transmit + acknowledge reception
Interrupt is cleared to "0" by writing INT=0 .
2 Interrrupt generation by 1 byte reception
Write INT=0 after reading reception data.
3 Interrrupt generation by 1 byte reception
Set MSS=0 or MSS=1, and SCC=1 setting ACKE=0 after reading reception data.
Note: The TDRE bit is "1" when the interrupt flag (INT) is generated.
Figure 17.3-23 Master Receive Interrupt 3 by FIFO Enabled (WSEL=0, ACKE=0, RSA=0)
S
Slave Address
R ACK
Data
ACK
Data
NACK P or Sr
ACK Data
1
: Interrupt by INTE=1.
: Interrupt by CNDE=1.
1 Interrupt generation by TDRE = 1
Set MSS=0 or MSS=1, and SCC=1 after reading all data from reception FIFO.
Figure 17.3-24 Master Receive Interrupt 4 by FIFO Enabled (WSEL=1, RSA=0)
S
SlaveAddress
R ACK
Data
ACK
Data
ACK
Data NACK P or Sr
1
: Interrupt by INTE=1.
: Interrupt by CNDE=1.
1 Interrupt generation by TDRE = 1
Set ACKE=0, MSS=0 or MSS=1, and SCC=1 after reading all data from reception FIFO.
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■ Arbitration Lost
If the master experiences collision of data with the other masters data and receives different data from the
transmitted data, it judges the condition as arbitration lost. The MSS bit is set to "0", the AL bit is set to
"1", and the operation is enabled in the slave mode.
The AL bit can be cleared to "0" with the following conditions:
• "1" is written to the MSS bit.
• "0" is written to the INT bit
• Write "0" to SPC bit at AL bit=1, SPC bit=1.
• I2C interface disable (EN bit=0)
When arbitration lost occurs, the interrupt flag (INT) is set to "1" and the SCL of the I2C bus is set to "L"
according to the WSEL setting.
■ Wait in Master Mode
If "1" is set into the MSS bit while the BB bit is "1" and if the operation is not in the slave mode, it waits
for the master mode while the BB bit is "1". When the BB bit turns to "0", the start condition is transmitted.
You can judge whether the operation is waiting for the master mode or not by using the MSS and ACT bits
(If MSS=1 and ACT=0, it is waiting for the master mode.). If the operation is in the slave mode after "1" is
set into the MSS bit, set the AL bit to "1", the MSS bit to "0", and the ACT bit to "1".
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17.3.3
Slave Mode
When the (repetitive) start condition is detected, and the combination of the ISBA and
ISMK registers matches with the received address, an ACK response is returned and
the slave mode is activated.
■ Slave Address Match Detection
When the (repetitive) start condition is detected, the 7 bits of the next data are received as an address. The
bits to which "1" is set in the ISMK register are compared between the ISBA register and the received
address. When they match, ACK is output.
Table 17.3-5 Operation Immediately after the Acknowledge Output for the Slave Address
Data
Transmission Reception Transmission Reception
direction
FIFO
FIFO
FIFO
FIFO status
bit (R/W)
status
0
Disable
Disable


1
No data
0
Data
Disable
Enable


1
0
Enable
Disable


1
No data
0
Data
Enable
Enable


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Operation immediately after acknowledge
Acknowledge is ACK
When the TDRE bit is "1",
the INT bit is set to "1" and
wait occurs. When the
TDRE bit is "0", the INT bit
is kept to "0" and wait does
not occur.
The INT bit is kept to "0"
and wait does not occur.
The INT bit is set to "1" and
wait occurs.
When the TDRE bit is "1",
the INT bit is set to "1" and
wait occurs. If the TDRE
bit is "0", the INT bit is kept
to "0" and wait does not
occur.
When the TDRE bit is "1",
the INT bit is set to "1" and
wait occurs. When the
TDRE bit is "0", the INT bit
is kept to "0" and wait does
not occur.
The INT bit is kept to "0"
and wait does not occur.
The INT bit is set to "1" and
wait occurs.
When the TDRE bit is "1",
the INT bit is set to "1" and
wait occurs. If the TDRE bit
is "0", the INT bit is kept to
"0" and wait does not occur.
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Acknowledge is NACK
The INT bit is kept to "0"
and wait does not occur.
The INT bit is kept to "0"
and wait does not occur.
The INT bit is kept to "0"
and wait does not occur.
The INT bit is kept to "0"
and wait does not occur.
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17.3 I2C Interface Interruption
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• Reserved address detection
If the data matches with the reserved address ("0000xxxxB" or "1111xxxxB") in the first byte, the INT
bit is set to "1" to wait for the I2C bus after the 8th bit data is received, independently of the setting
whether the transmission/reception FIFO is enabled. At this point, the received data is read. If you want
operation as a slave, set ACKE to "1" and clear the INT bit. When ACKE is set to "0", the slave
operation is disabled after an acknowledge is output.
■ Data Direction Bit
After the address is received, the data direction bit, which determines whether to send or receive data, is
received. When this bit is "0", it indicates the transmission from the master, which means that the slave
receives data.
■ Reception by a Slave
When the slave address matches and the data direction bit is "0", it indicates the reception in the slave
mode. The following is an example procedure to receive data in the slave mode:
• When receive FIFO is disabled.
(1) After sending ACK, set the interrupt flag (INT) to "1" and wait for the I2C bus. Determine that the
interrupt is caused by the slave address match by checking the MSS, ACT, and FBT bits. Write "1"
into the ACKE bit, "0" into the interrupt flag (INT), and cancel the wait for the I2C bus. (Refer to
Table 17.3-5.)
(2) After receiving one byte of data, set the interrupt flag (INT) to "1" and wait for the I2C bus
according to the WSEL setting.
(3) Read the data received from the RDR register and set the ACKE bit. Then, write "0" into the
interrupt flag (INT) and cancel the wait for the I2C bus.
(4) Repeat steps (2) through (3) until the stop condition or repetitive start condition is detected.
• When receive FIFO is enabled:
(1) When the NACK detection or the reception FIFO becomes full, the interrupt flag (INT) turns to "1"
to wait for the I2C bus. If the stop condition or repetitive start condition is detected, the SPC or RSC
bit is set to "1" and the interrupt flag (INT) is not set to "1" (no wait for the I2C bus). For the
reception FIFO, set the RDRF bit to "1" if the number of received data pieces matches with the
value specified in the FBYTE register. If the RIE bit is "1" at this point, an reception interrupt
occurs.
(2) When the interrupt flag (INT) turns to "1", read the data received from the RDR register. After
reading all the data, write "0" into the interrupt flag and cancel the wait for the I2C bus. If the stop
condition or repetitive start condition is detected, read all the received data from the RDR register,
and clear the SPC or RSC bit to "0".
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17.3 I2C Interface Interruption
MB91345 Series
Figure 17.3-25 Slave Receive Interrupt 1 by FIFO Disabled (WSEL=0, RSA=0)
S
Slave Address
W ACK
Data
1
ACK
Data
ACK
Data
P or Sr
3
2
2
ACK
: Interrupt by INTE=1.
: Interrupt by CNDE=1.
1
ACK is output because a slave address matches, and interrupt is generated
Write ACKE=1 and INT=0.
2 Interrrupt generation by 1 byte reception + ACK response
Write INT=0 after reading reception data from reception buffer.
3 Interrrupt generation by 1 byte reception + NACK response
Write INT=0 after reading reception data from reception buffer.
Figure 17.3-26 Slave Receive Interrupt 2 by FIFO Disabled (WSEL=1, RSA=0)
S
Slave Address
W ACK
Data
1
ACK Data
ACK Data
P or Sr
3
2
2
ACK
: Interrupt by INTE=1.
: Interrupt by CNDE=1.
1
ACK is output because a slave address matches, and interrupt is generated
Write ACKE=1 and INT=0.
2 Interrrupt generation by 1 byte reception
Write INT=0 after reading reception data from reception buffer.
3 Interrrupt generation by 1 byte reception
Write INT=0 after reading reception data from reception buffer.
Figure 17.3-27 Slave Receive Interrupt 3 by FIFO Disabled (WSEL=1, RSA=0)
S
Slave Address
W ACK
1
Data
ACK Data
2
ACK Data NACK P or Sr
2
2
3
: Interrupt by INTE=1.
: Interrupt by CNDE=1.
1 ACK is output because a slave address matches, and interrupt is generated
Write ACKE=1 and INT=0.
2 Interrrupt generation by 1 byte reception
Write INT=0 after reading reception data from reception buffer.
3 Interrupt generation by NACK response
Write INT=0
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MB91345 Series
Figure 17.3-28 Slave Receive Interrupt 4 by Receive FIFO Enabled (RSA=0)
S
Slave Address
W ACK
Data
ACK Data
ACK Data
ACK P or Sr
1
: Interrupt by INTE=1
: Interrupt by CNDE=1
1
Interrupt generation by detection of stop condition or repeat start condition
Read all data from reception FIFO
Figure 17.3-29 Slave Receive Interrupt 5 by Receive FIFO Enabled (RSA=0)
S
Slave Address
W ACK
Data
ACK
Data
ACK
Data
ACK P or Sr
1
: Interrupt by INTE=1
: Interrupt by CNDE=1
1
Interrupt generation because reception FIFO is full
Read all data from reception FIFO and write INT=0.
Figure 17.3-30 Slave Receive Interrupt 6 by FIFO Disabled (WSEL=0, RSA=1)
S
Slave Address
W ACK
1
Data
ACK Data
2
ACK
Data
2
ACK P or Sr
3
: Interrupt by INTE=1
: Interrupt by CNDE=1
1 Interrupt generation by reserved address match ("0000xxxxH" or "1111xxxxH")
Read the reception data and write ACKE=1 and INT=0.
2 Interrupt generation by 1 byte reception + acknowledge output
INT=0 write
3 Interrupt generation by 1 byte reception + acknowledge output
Interrupt by INT=0 write
■ Transmission by a Slave
When the slave address matches and the data direction bit is "1", this indicates the transmission by the
slave. If FIFO is disabled, set the interrupt flag (INT) to "1" and generate wait after sending one byte of
data or after returning an acknowledge. The timing depends on the WSEL setting.
(Refer to Table 17.3-5.)
When you can confirm the acknowledge output from the master with the RACK bit, and the master returns
NACK, it indicates that the master fails the reception or the data reception has finished. If NACK is
detected while WSEL=1, an interrupt occurs to generate wait.
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17.3 I2C Interface Interruption
MB91345 Series
17.3.4
Bus Error
If the stop condition or (repetitive) start condition is detected while data is transmitted
on the I2C bus, the operation is considered to be a bus error.
■ Condition of Bus Error Generation
Bus error sets the BER bit to "1" with the following conditions.
• When the (repetitive) start condition or stop condition is detected while the first byte of data is
transmitted.
• When the (repetitive) start condition or stop condition is detected in the second bit through ninth
(acknowledge) bit of the data
■ Bus Error Operation
When the interrupt flag (INT) turns to "1" by transmission/reception, check the BER bit. If the BER bit is
"1", correct the error. The BER bit can be cleared by writing "0" into the INT bit.
Although INT bit is set to "1" by bus error, SCL of I2C bus is set to "L" to avoid WAIT condition.
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CHAPTER 17 I2C Interface
17.4 Dedicated Baud Rate Generator
17.4
MB91345 Series
Dedicated Baud Rate Generator
Dedicated baud rate generator sets serial clock frequency.
■ Baud Rate Selection
● Baud rate obtained by dividing the internal clock in the dedicated baud rate generator (reload counter)
Two internal reload counters are provided and are used for the send and receive serial clocks respectively.
You can select a baud rate by setting a 15-bit reload value in the baud rate generator registers 1, 0 (BGR1,
BGR0).
The reload counter divides the internal clock frequency by the set value.
■ Baud Rate Opearion
The two 15-bit reload counters are set by baud rate generator registers 1 and 0 (BGR1 and BGR0).
The baud rate is calculated by the following equation.
(1) Reload value:
V=/b1
V: Reload value
b: Baud rate
: Peripheral clock frequency
However, the baud rate set according to the rise time of SCL of the I2C bus is not
generated. In that case, please adjust the reload value.
(2) Calculation example
Reload at peripheral clock 16 MHz, baud rate 400 kbps is as follows:
Reload value:
V = (16  1000000) / 40000  1 = 39
So, baud rate is as follows:
b = (16  1000000) / (38 + 2) = 400 kbps
Notes:
• Writing to the baud rate generator registers (BGR1, BGR0) should be done by 16-bit access.
• Set up the baud rate generator register when the EN bit of the ISMK register is "0".
• In the operation mode 4 (I2C mode), use the peripheral clock at 8 MHz or more. It is prohibited to
set the baud rate generator to the value higher than 400 kbps.
• Setting a reload value of 0 stops the reload counter.
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17.4 Dedicated Baud Rate Generator
MB91345 Series
■ The Reload Value and Baud Rate for Each Peripheral Clock Frequency
Table 17.4-1 Reload Values and Baud Rates
8 MHz
10 MHz
16 MHz
20 MHz
24 MHz
32 MHz
Reload
Value
Reload
Value
Reload
Value
Reload
Value
Reload
Value
Reload
Value
400000
19
24
39
49
59
79
200000
39
49
79
99
119
159
100000
79
99
159
199
239
319
Baud rates
[bps]
This value is a numerical value when SCL rising of the I2C bus is "0". When SCL of I2C bus rises slow, the
baud rate becomes slower than the above values.
■ Function of the Reload Counter
It consists of 15bit register for the reload value, and generates the transmission/reception clock from the
internal clock. The count value of the transmission reload counter can be read from the baud rate generator
registers (BGR1, BGR0).
■ Start Counting
Once the reload value is written to the baud rate generator registers (BGR1, BGR0), the reload counter
starts to count.
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CHAPTER 17 I2C Interface
17.4 Dedicated Baud Rate Generator
17.4.1
MB91345 Series
Example of I2C Flowcharts
Below are some example flowcharts for I2C communication.
■ I2C Master Reception/Slave Transmission FIFO Communication Flow
Figure 17.4-1 Master Reception Main Settings
Start
Master Reception
Initial Settings
Communication error?
NO
Error flag =1
YES
Stop I2C (ISMK:EN=0)
End
ISMK: 7-bit slave address mask register (ISMK)
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MB91345 Series
Figure 17.4-2 Master Reception Initial Settings
Start
Set initial settings:
I2C mode settings (SMR)
Baud rate settings (BGR)
Set FIFO settings
FIFO control register 1 settings (FCR1)
FIFO control register 0 settings (FCR0)
Enable INT interrupt
(IBCR:INTE=1)
Set I2C enable settings (ISMK:EN=1)
Reception FIFO depends on
FSEL value of FIFO control
register 1.
Set FIFO reception byte count
(FBYTE1=xx FBYTE2=00, or
FBYTE1=00 FBYTE2=xx)
Write FIFO buffer:
Slave address + communication
direction (Read)
Store Dummy data FIFO (TDR)
Bus busy?
YES
IBSR:BB=1
NO
Error
Set operation mode:
Master (IBCR:MSS=1)
End
SMR:
BGR:
ISBA:
ISMK:
FCR1:
FCR0:
IBCR:
IBSR:
FBYTE1:
FBYTE2:
TDR:
Serial mode register (SMR)
Baud rate generator register (BGR)
7-bit slave address register (ISBA)
7-bit slave address mask register (ISMK)
FIFO control register 1 (FCR1)
FIFO control register 0 (FCR0)
I2C bus control register (IBCR)
I2C bus status register (IBSR)
FIFO1 byte register (FBYTE1)
FIFO2 byte register (FBYTE2)
Transmitted data register (TDR)
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Figure 17.4-3 Master Reception Interrupt Process
Reception interrupt
process
Bus error?
YES
IBCR.BER=1
NO
Arbitration error?
YES
IBSR.AL=1
NO
NO
SSR.RDRF=1
YES
FIFO END?
(Reception is completed)
Read FIFO received data (RDR)
3
1
Error
2
IBCR: I2C bus control register (IBCR)
IBSR: I2C bus status register (IBSR)
SSR: serial status register (SSR)
RDR: received data register (RDR)
* For actual error handling, please judge each status error flag and handle each error by considering your
systems.
* For final ACK process when receiving FIFO continuously, a wait will be generated after receiving the final data,
if setting WSEL=1. Please respond with NACK by setting IBSR.RACK=1 during this wait.
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1
IBCR.MSS=1, and
IBCR.ACT=1
Confirm I2C / master operation
NO
YES
Software checks whether
all the expected data (for
dummy data write) have
been received.
Are all data transferred ?
NO
YES
Iterative start ?
NO
YES
Write FIFO buffer:
Slave address + communication direction
(Read)
Store dummy data FIFO (TDR)
Iterative start condition settings
(IBCR.SCC=1)
When WSEL=1, a user
should set NACK
transmission settings.
INT flag becomes "1" after
the NACK transmission.
2
When WSEL=1, a user
should set NACK
transmission settings.
3
Clear interrupt (IBCR.INT=0)
Stop Condition (IBCR.MSS=0)
End
IBCR: I2C bus control register (IBCR)
TDR: Transmitted data register (TDR)
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MB91345 Series
Figure 17.4-4 Slave Transmission Main Settings
Start
Slave transmission
initial settings
Communication error?
NO
Error flag=1
YES
Stop I2C (ISMK:EN=0)
End
ISMK: 7-bit slave address mask register (ISMK)
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MB91345 Series
Figure 17.4-5 Slave Transmission Initial Settings
Start
Set initial settings:
I2C mode settings (SMR)
Baud rate settings (BGR)
Slave address settings (ISBA)
Slave mask settings (ISMK)
Enable iterative start interrupt
(IBCR:CNDE=1)
Enable INT interrupt
(IBCR:INTE=1)
Set I2C enable settings
(ISMK:EN=1)
Set Slave settings (IBCR:MSS=0)
Set FIFO settings
FIFO control register 1settings
(FCR1)
FIFO control register 0 settings
(FCR0)
Write FIFO buffer:
Store Transmitted data FIFO
(TDR)
End
SMR:
BGR:
ISBA:
ISMK:
IBCR:
FCR1:
FCR0:
TDR:
Serial mode register (SMR)
Baud rate generator register (BGR)
7-bit slave address register (ISBA)
7-bit slave address mask register (ISMK)
I2C bus control register (IBCR)
FIFO control register 1 (FCR1)
FIFO control register 0 (FCR0)
Transmitted data register (TDR)
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MB91345 Series
Figure 17.4-6 Slave Transmission Interrupt Process
Transmission
interrupt process
Bus error?
YES
IBCR:BER=1
NACK is output
from master even if
transmission/
reception are
interrupted.
NO
Detected iterative start?
(IBSR:RSC=1)
YES
Write FIFO buffer:
Store Transmitted data FIFO
(TDR)
Clear the interrupt flag
(IBSR:RSC=0)
NO
NACK response
at final data?
(IBSR:RACK=1)
NO
YES
Error
Is there data in FIFO?
(SSR:TDRE=0)
YES
Whether
transmission/
reception are
interrupted is
judged by the
existence of FIFO
data.
Prohibit FIFO operation
(FCR0=0x00)
NO
Reset FIFO (FCR0:FCL=1)
Set transmitted data empty
flag (SSR:TSET=1)
Enable FIFO operation
(FCR0=0x03)
Clear interrupt (IBCR:INT=0)
End
IBSR:
TDR:
SSR:
FCR0:
IBCR:
I2C bus status register (IBSR)
Transmitted data register (TDR)
Serial status register (SSR)
FIFO control register 0 (FCR0)
I2C bus control register (IBCR)
* For actual error handling, please judge each status error flag and handle each error by considering your systems.
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17.4 Dedicated Baud Rate Generator
MB91345 Series
■ I2C Master Transmission/ Slave Reception FIFO Communication Flow
Figure 17.4-7 Master Transmission Main Settings
Start
Master Transmission
Initial Setting
Communication error?
NO
Error flag=1
YES
Stop I2C (ISMK:EN=0)
End
ISMK: 7-bit slave address mask register (ISMK)
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MB91345 Series
Figure 17.4-8 Master Transmission Initial Settings
Start
Set initial settings:
I2C mode settings (SMR)
Baud rate settings (BGR)
Set FIFO settings
FIFO control register 1 settings(FCR1)
FIFO control register 0 settings(FCR0)
Enable INT interrupt (IBCR:INTE=1)
Set I2C enable settings (ISMK:EN=1)
Write FIFO buffer:
Slave address + communication
direction (Write)
Store transmission data FIFO (TDR)
Bus busy?
YES
IBSR:BB=1
NO
Error
Set operation mode:
Master (IBCR:MSS=1)
End
SMR:
BGR:
ISBA:
ISMK:
FCR1:
FCR0:
IBCR:
IBSR:
TDR:
576
Serial mode register (SMR)
Baud rate generator register (BGR)
7-bit slave address register (ISBA)
7-bit slave address mask register (ISMK)
FIFO control register 1 (FCR1)
FIFO control register 0 (FCR0)
I2C bus control register (IBCR)
I2C bus status register (IBSR)
Transmitted data register (TDR)
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17.4 Dedicated Baud Rate Generator
MB91345 Series
Figure 17.4-9 Master Transmission Interrupt Process
Transmission
interrupt process
Bus error?
YES
IBCR:BER=1
NO
Arbitration error?
YES
IBSR:AL=1
NO
NACK error?
YES
IBSR:RACK=1
NO
Error
1
IBCR:
IBSR:
2
I2C bus control register (IBCR)
I2C bus status register (IBSR)
* For actual error handling, please judge each status error flag and handle each error by considering your systems.
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17.4 Dedicated Baud Rate Generator
MB91345 Series
1
Confirm I2C/ master operation
NO
IBCR.MSS=1, and
IBCR.ACT=1
Software checks whether
all the transmission data
have been written to the
transmission buffer.
YES
NO
SSR: TDRE=1, and
Are all data transferred?
YES
Judge iterative packet
operation requests for
the whole system.
NO
Iteration start request?
YES
Iteration operation initial settings
Write FIFO buffer:
Slave address + communication direction
(Write)
Score Transmitted data FIFO (TDRx)
Iteration start condition settings
(IBCR.SCC=1)
2
Clear interrupt (IBCR.INT=0)
Stop Condition (IBCR.MSS=0)
End
IBCR: I2C bus control register (IBCR)
TDR: Transmitted data register (TDR)
SSR: Serial status register (SSR)
* For actual error handling, please judge each status error flag and handle each error by considering your systems.
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17.4 Dedicated Baud Rate Generator
MB91345 Series
Figure 17.4-10 Slave Reception Main Settings
Start
Slave reception initial settings
Communication error?
NO
Error flag=1
YES
Stop I2C (ISMK:EN=0)
End
ISMK: 7-bit slave address mask register (ISMK)
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Figure 17.4-11 Slave Reception Initial Settings
Start
Set initial settings:
I2C mode settings (SMR)
Baud rate settings (BGR)
Slave address settings (ISBA)
Slave mask settings (ISMK)
Enable INT interrupt
(IBCR:INTE=1)
Set I2C enable settings
(ISMK:EN=1)
Set slave settings (IBCR:MSS=0)
Set FIFO settings
FIFO control register 1 settings
(FCR1)
FIFO control register 0 settings
(FCR0)
Reception FIFO depends on
FSEL value of FIFO control
register 1.
Set FIFO reception byte count
(FBYTE1=xx FBYTE2=00, or
FBYTE1=00 FBYTE2=xx)
End
SMR:
BGR:
ISBA:
ISMK:
IBCR:
FCR1:
FCR0:
FBYTE1:
FBYTE2:
580
Serial mode register (SMR)
Baud rate generator register (BGR)
7-bit slave address register (ISBA)
7-bit slave address mask register (ISMK)
I2C bus control register (IBCR)
FIFO control register 1 (FCR1)
FIFO control register 0 (FCR0)
FIFO1 byte register (FBYTE1)
FIFO2 byte register (FBYTE2)
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17.4 Dedicated Baud Rate Generator
MB91345 Series
Figure 17.4-12 Slave Reception Interrupt Process
Reception
interrupt process
Bus error?
YES
IBCR:BER=1
NO
FIFO END?
(Reception is completed)
SSR:RDRF=1
NO
YES
Error
Read FIFO received data
(RDR)
Clear interrupt (IBCR:INT=0)
End
IBSR:
SSR:
RDR:
IBCR:
I2C bus status register (IBSR)
Serial status register (SSR)
Received data register (RDR)
I2C bus control register (IBCR)
* For actual error handling, please judge each status error flag and handle each error by considering your
systems.
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17.5 Notes on I2C Mode
17.5
MB91345 Series
Notes on I2C Mode
The notes for when you use the I2C mode are shown below.
• FIFO cannot be used for requesting DMA transfer with a channel with FIFO. Please set as FIFO
operation disable.
• To request a DMA transfer request, set the block size of DMA to one time.
• When master reception and slave reception are selected, it is required to use two channels for DMA;
one is used for DMA transfer to receive data and the other one is used for DMA transfer to send dummy
data.
• In I2C mode, if there is no valid data in transmission register (TDR), and transmission data empty flag
bit (TDRE) is "1", the interrupt flag (INT) becomes "1" as shown in Figure 17.5-1 when the data on I2C
bus for 9 bits (WSEL=0) or for 8 bits (WSEL=1) is transmitted. When the interrupt flag (INT) becomes
"1" during DMA transfer, DMA transfer cannot be continued unless clearing the bit to "0" by software.
(Common to master transmission, slave transmission, mater reception, and slave reception.)
Figure 17.5-1 INT Bit Change Timing of I2C (WSEL= 0)
SCL
SDA
DATA
ACK
DATA
ACK
TDRE bit
DMA transfer
to TDR
INT bit
To perform DMA transfer in I2C mode, since the specification is as shown above, such operations listed
below are required for performing DMA transfer to TDR before the interrupt flag (INT) becomes "1".
Below operations are possible to perform to prioritize DMA transfer of I2C.
- Use DMA which has a higher priority (channel number is small). It is enabled to use by fixing the
priority setting bit (AT=0).
- Set the value of DMA-halt by interrupt level bit as small as possible (LVL4-LVL0 bit in DILVR
register).
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CHAPTER 17 I2C Interface
17.5 Notes on I2C Mode
MB91345 Series
• In case of writing the transmission data to transmission data register (TDR) by DMA transfer after
transmission data empty flag (SSR: TDRE) becomes "1", or writing the data by software confirming the
transmission data empty flag (SSR:TDRE), transmission data empty flag (SSR:TDRE) may not become
"0". Therefore, the transmission data should be written before SCL in ACK field falls. There are no
restrictions on writing the transmission data by software after the interrupt flag (IBCR:INT) becomes
"1".
When performing DMA transfer or sending the data by software confirming the transmission data
empty flag (SSR:TDRE), please follow below procedures if the data cannot be written before SCL in
ACK field falls.
- Setting
Set the timing of interrupt flag (IBCR:INT) becoming "1" to the 8th bit (WSEL=1).
- Procedures
To transmit or receive data by master, the following procedures are required. To transmit or receive
data by slave, it is not required to perform the following.
1. Write the first byte (slave address) to the transmission data register by software.
2. Set to 8-bit for wait selection (IBCR:WSEL="1" write) at the same time that master is started
(IBCR:MSS="1" write).
3. After sending the first byte, the interrupt flag (IBCR:INT) becomes "1". Write the second byte to
transmission data register (TDR) by software after confirming ACK response (IBSR:RACK="0").
Set the DMAC, and activate DMA transfer, then write "0" to interrupt flag (IBCR:INT).
4. After transmission and reception are completed, terminate the master (IBCR:MSS="0" write) or
reboot (IBCR:SCC="1" write).
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CHAPTER 17 I2C Interface
17.5 Notes on I2C Mode
584
MB91345 Series
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CHAPTER 18
A/D Converter
This chapter describes an overview of the A/D converter,
configuration/function of the register, and its operation.
18.1 Overview of A/D Converter
18.2 Block Diagram of A/D Converter
18.3 Registers of A/D Converter
18.4 Operation of A/D Converter
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CHAPTER 18 A/D Converter
18.1 Overview of A/D Converter
18.1
MB91345 Series
Overview of A/D Converter
The A/D converter converts an analog input voltage to a digital value. The features of
the A/D converter are as follows:
■ Features of the A/D Converter
• Equipped with 2 units (UNIT-0: 8channels, UNIT-1: 8channels).
• Simultaneous activation function of 2 units is available.
• Conversion time: Minimum of 1.2 µs per channel (with 16MHz CLKP)
• Uses RC-type successive comparison conversion method with a sample and hold circuit.
• 10-bit resolution
• Analog input is selectable from among 8 channels by a program.
• Single conversion mode: Selects and converts one channel.
• Scan conversion mode: Converts consecutive multiple channels. Up to 8 channels can be programmed.
• Continuous conversion mode: Converts a specified channel repeatedly.
• Stop conversion mode: Converts a specified channel, pauses, and stands by until the next activation
occurs (conversion start can be synchronized).
• Interrupt request: When the A/D conversion ends, an interrupt request for A/D conversion end can be
generated to CPU. This interrupt is used as a start for the DMA transfer that transfers
a result of A/D conversion to a memory.
• Activation source can be selected: Activation sources are software, external trigger (falling edge), or
timer (rising edge).
■ Input Impedance
A sampling circuit of the A/D converter is shown in an equivalent circuit of Figure 18.1-1.
Figure 18.1-1 Input Impedance
Rext
Rin
Analog
signal
source
ANx
Analog SW
Cin
ADC
Set Rext not to exceed the maximum time of sampling time (Tsamp).
Rext = Tsamp/(8 × Cin) — Rin
586
Rext: Outputimpedance of external circuit
Rin: Input resistonce of A/D converter
Cin: Input capacitance of A/D converter
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CHAPTER 18 A/D Converter
18.2 Block Diagram of A/D Converter
MB91345 Series
18.2
Block Diagram of A/D Converter
The block diagram of the A/D converter is shown below.
■ Block Diagram of the A/D Converter
Figure 18.2-1 Block Diagram of A/D Converter
AVCC
AVRH/L AVSS
D/A converter
Successive
approximation register
MPX
Internal data bus
Sample &
hold circuit
Decoder
Comparator
Input circuit
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Data register
A/D control register 0
A/D control register 1
ADCS0/
ADCS1
Operation
clock
ATGX pin
16-bit
reload timer
Prescaler
CLKP
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CHAPTER 18 A/D Converter
18.3 Registers of A/D Converter
18.3
MB91345 Series
Registers of A/D Converter
The A/D converter has the following types of registers:
• Analog input enable register (ADERH)
• A/D control status register (ADCS)
• Data register (ADCR)
• Data mirror register (ADCRM)
• Sampling timer setting register (ADCT)
• Start/End channels setting registers (ADSC, ADEC)
• Trigger control register (ADTGS)
■ Register List
Figure 18.3-1 Register List
000020H
000022H
000024H
000026H
000028H
00002AH
00002CH
00002EH
000030H
000032H
000034H
000036H
000038H
00003AH
...
000578H
588
Reserved
Reserved
ADCS01
ADERH0
ADCS00
ADCR0
ADCT0
ADSCH0
ADECH0
ADCR0M
ADCR1M
Reserved
Reserved
ADCS11
ADERH1
ADCS10
ADCR1
ADCT1
ADSCH1
ADECH1
...
ADTGS
Reserved
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CHAPTER 18 A/D Converter
18.3 Registers of A/D Converter
MB91345 Series
18.3.1
Analog Input Enable Register (ADERH)
Always write "1" to the ADERH bit corresponding to the pin used in analog input.
■ Analog Input Enable Register (ADERH0, ADERH1)
ADERH0
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000033H
ADE7
ADE6
ADE
ADE4
ADE3
ADE2
ADE1
ADE0
11111111B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000023H
ADE7
ADE6
ADE
ADE4
ADE3
ADE2
ADE1
ADE0
11111111B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADERH1
R/W:
Readable/writable
[bit7 to bit0] ADE7 to ADE0 (A/D Input Enable)
ADE
Function
0
Port input/output mode [initial value]
1
Analog input mode
These bits are initialized to "1" at reset.
Be sure to write "1" to the analog input enable register of the start channel and end channel.
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CHAPTER 18 A/D Converter
18.3 Registers of A/D Converter
18.3.2
MB91345 Series
A/D Control Status Register (ADCS)
The A/D control status register controls the A/D converter and indicates the A/D
converter status. Do not rewrite the ADCS0 register during A/D conversion.
■ A/D Control Status Register (ADCS0, ADCS1)
ADCS01
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000024H
BUSY
INT
INTE
PAUS
STS1
STS0
STRT
Reserved
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000025H
MD1
MD0
S10
ACH2
ACH1
ACH0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000034H
BUSY
INT
INTE
PAUS
STS1
STS0
STRT
Reserved
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000035H
MD1
MD0
S10
ACH2
ACH1
ACH0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
ADCS00
Reserved Reserved
ADCS11
ADCS10
R/W:
Reserved Reserved
R/W
R/W
Readable/writable
[bit15] BUSY (busy flag and stop)
BUSY
Function
Read
This bit is used to indicate A/D converter operation. This bit is set when A/D
conversion starts and cleared when A/D conversion of the last channel ends.
Write
Setting this bit to "0" during A/D operation forcibly stops the operation. This
bit is used to forcibly stop the operation in continuous and stop modes.
The bit for indicating the operation cannot be set to "1".
Read-modify-write (RMW) instructions always read "1". In single mode, the bit is cleared after A/D
conversion of the last channel you set ends.
In continuous and stop modes, the bit is not cleared until it is set to "0" to stop the operation.
This bit is initialized to "0" at reset.
Do not perform a forced stop and software activation simultaneously (BUSY=0, STRT=1).
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18.3 Registers of A/D Converter
MB91345 Series
[bit14] INT (interrupt)
This bit is set when conversion data is written to the ADCR.
When bit5 (INTE) is "1", setting the INT bit will generate an interrupt request. The DMA will be
activated if DMA operation is enabled.
This bit is cleared by setting "0".
Note: Do not write "0" to clear this bit when A/D is stopping.
This bit is initialized to "0" at reset.
When using DMA, this bit is cleared at the end of the DMA transfer.
[bit13] INTE (Interrupt enable)
This bit is used to enable or disable interrupts at the end of the conversion.
INTE
Function
0
Interrupt disabled [initial value]
1
Interrupt enabled
This bit is initialized to "0" at reset.
[bit12] PAUS (A/D converter pause)
This bit is set when A/D conversion stops temporarily.
Because there is only one register to store the A/D conversion result, the conversion result must be
transferred by the DMA when a continuous conversion is running, otherwise the previous data will be
overwritten. To protect the previous data, the new conversion data will not be stored until the data
register contents are transferred by the DMA. The A/D conversion is suspended during this time. The
A/D conversion restarts when the DMA transfer ends. This bit is valid only when the DMA is used.
This bit can be cleared only by writing "0" to it (This bit is not cleared at the end of the DMA transfer).
However, this bit cannot be cleared in the DMA transfer wait state.
See section "18.4 Operation of A/D Converter" for the conversion data protection function. This bit is
initialized to "0" at reset.
[bit11, bit10] STS1, STS0 (Start source select)
These bits are initialized to "00" at reset. A/D start sources are selected by setting these bits.
CM71-10132-3E
STS1
STS0
Function
0
0
Software activation
0
1
External pin trigger activation and software activation
1
0
16-bit reload imer activation and software activation
1
1
External pin trigger activation, software activation, and timer
activation
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18.3 Registers of A/D Converter
MB91345 Series
For modes that enable multiple start sources, the A/D conversion is activated by the source generated
first. Since the start source change is reflected immediately after the bit setting is changed, caution
should be exercised when changing the start source during the A/D conversion operation. For the
external pin trigger, the falling edge is detected. If the external trigger input level is "L" level, the A/D
converter may be activated when this bit is rewritten to set external pin trigger activation. When the
timer activation is selected, the 16-bit reload timer 2 is selected for both A/D ch.0 and ch.1.
[bit9] STRT (Start)
Setting this bit to "1" activates the A/D converter (software activation).
To restart the A/D converter, set this bit to "1" again. This bit is initialized to "0" at reset. In
continuous mode and stop mode, the restart is not enabled due to the functional reason. Check the
BUSY bit before writing "1" to this bit (Activate the converter after clearing the BUSY bit). Do not
perform a forced stop and software activation simultaneously (BUSY=0 and STRT=1).
[bit8] Reserved bit
Always set "0" to this bit.
[bit7, bit6] MD1, MD0 (A/D converter mode set)
MD1 and MD0 bits are used to set the operation mode.
MD1
MD0
Operation mode
0
0
Setting disabled
0
1
Single mode. Restart is disabled during operation.
1
0
Continuous mode. Restart is disabled during operation.
1
1
Stop mode. Restart is disabled during operation.
Single mode:
- A/D conversion is continuously performed for the channels set by ANS2 to ANS0 up to the channels
set by ANE2 to ANE0, and the conversion stops when the conversion of all channels is completed.
Continuous mode:
- A/D conversion is performed repeatedly for the channels set by ANS2 to ANS0 up to the channels set
by ANE2 to ANE0.
Stop mode:
- A/D conversion is performed for the channels set by ANS2 to ANS0 up to the channels set by ANE2
to ANE0, but the operation stops temporarily for each channel. The A/D conversion is restarted by
the start source generation.
These bits are initialized to "00B" at reset.
When A/D conversion is activated in continuous or stop mode, the conversion operation will continues
until a forced stop is made by the BUSY bit.
The forced stop is made by setting "0" to the BUSY bit.
When A/D conversion is activated after a forced stop, the conversion starts from the channels set by
ANS2 to ANS0.
Restart is disabled during each operation in single, continuous, or stop mode, and this applies to all the
activation by the timer, external trigger, and software.
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CHAPTER 18 A/D Converter
18.3 Registers of A/D Converter
MB91345 Series
Note:
If the A/D conversion mode select bit (MD1, MD0) is set to "00B", restart during the A/D conversion
becomes available.
In this mode, you can only set to the software start (STS, STS0 = 00B).
To restart:
(1) Clear INT bit to "0".
(2) Write "1" to STR bit and "0" to INT bit at the same time.
[bit5] S10
This bit specifies the resolution of the conversion. When setting this bit to "0", the 10-bit A/D
conversion is performed. Otherwise, the 8-bit A/D conversion is performed and its result is stored in the
ADCR0. This bit is initialized to "0" at reset.
[bit4, bit3] Reserved
These bits are reserved bits. Always set "0" to them.
[bit2 to bit0] ACH2, ACH1, ACH0 (Analog convert select channel)
These bits indicate the channel of the A/D conversion in progress.
ACH2
ACH1
ACH0
Conversion channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN6
1
1
1
AN7
ACH
Function
Read
During the A/D conversion (BUSY bit=1), the current conversion channel
is indicated by these bits. When stopped by a forced stop (BUSY bit=0),
the channel that the conversion is stopped is indicated.
Write
Writing to these bits is invalid.
These bits are initialized to "000B" at reset.
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CHAPTER 18 A/D Converter
18.3 Registers of A/D Converter
18.3.3
MB91345 Series
Data Register (ADCR)
The data registers (ADCR0, ADCR1) are used to store a digital value generated as a
result of conversion. The ADCR0 stores the lower 8 bits, and ADCR1 stores the most
significant 2 bits of the conversion result. These registers’ values are rewritten every
time conversion is completed. The last converted value is stored in these registers
normally.
■ Data Register (ADCR0, ADCR1)
ADCR0(Upper)
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000026H






D9
D8
------XXB






R
R
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000027H
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R
R
R
R
R
R
R
R
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000036H






D9
D8
------XXB






R
R
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000037H
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R
R
R
R
R
R
R
R
ADCR0(Lower)
ADCR1(Upper)
ADCR1(Lower)
R: Read only
: Undefined
"0" is always read out from bit10 to bit15 of the ADCR0 and ADCR1 registers.
A conversion data protection function is available. See section "18.4 Operation of A/D Converter".
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CHAPTER 18 A/D Converter
18.3 Registers of A/D Converter
MB91345 Series
18.3.4
Mirror Data Register (ADCR0M, ADCR1M)
The same data as that in data registers (ADCR0, ADCR1) can be read with a different address.
This is called mirror data register. The content is the same as that of "18.3.3 Data Register
(ADCR)".
■ Mirror Data Register (ADCR0M, ADCR1M)
ADCR0M
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00002CH






MRD9
MRD8
------XXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADCR0M
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00002DH
MRD7
MRD6
MRD5
MRD4
MRD3
MRD2
MRD1
MRD0
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00002EH






MRD9
MRD8
------XXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00002FH
MRD7
MRD6
MRD5
MRD4
MRD3
MRD2
MRD1
MRD0
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADCR1M
ADCR1M
R/W: Readabel/writable
:
Undefined
"0" is always read out from bit10 to bit15 of the ADCR0M and ADCR1M registers.
A conversion data protection function is available. See "18.4 Operation of A/D Converter".
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CHAPTER 18 A/D Converter
18.3 Registers of A/D Converter
18.3.5
MB91345 Series
A/D Conversion Time Setting Register (ADCT)
The A/D conversion time setting registers (ADCT0, ADCT1) control the sampling time
and comparison time of the analog input. The A/D conversion time is set by setting
ADCT registers.
Do not rewrite ADCT0 and ADCT1 registers during A/D conversion operation.
■ A/D Conversion Time Setting Register (ADCT0, ADCT1)
ADCT0(Upper)
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000028H
CT5
CT4
CT3
CT2
CT1
CT0
ST9
ST8
00010000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADCT0(Lower)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000029H
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0
00101100B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000038H
CT5
CT4
CT3
CT2
CT1
CT0
ST9
ST8
00010000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000039H
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0
00101100B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADCT1(Upper)
ADCT1(Lower)
R/W: Readable/writable
[bit15 to bit10] CT5 to CT0 (A/D compare time set)
Setting these bits specifies the clock division value of the comparison operation time.
When setting the CT5 to CT0 to "000001B" (01H), no division = CLKP is set.
Do not set the CT5 to CT0 to "000000B" (00H).
These bits are initialized to "000100B" (04H) at reset.
Comparison operation time (Compare Time) = CT set value  CLKP cycle  10 + (4  CLKP cycle)
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18.3 Registers of A/D Converter
MB91345 Series
[bit9 to bit0] ST9 to ST0 (Analog input sampling time set)
Setting these bits specifies the sampling time of the analog input.
These bits are initialized to "0000101100B" (02CH) at reset.
Sampling time (Sampling Time) = ST set value  CLKP cycle
Calculate the required sampling time and ST set time by using the following formulas.
Required sampling time (Tsamp) = (Rext + Rin)  Cin  8
ST9 to ST0 set values = required sampling time (Tsamp) / CLKP cycle
Set the ST set values so that A/D sampling time becomes longer than the required sampling time.
The required sampling time is determined by the Rext value so the Rext should be determined by taking
the conversion time into consideration.
Note:
"0000000000B" (00H), "0000000001B" (01H) and "0000000010B" (02H) must not be set to ST9 to
ST0.
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CHAPTER 18 A/D Converter
18.3 Registers of A/D Converter
18.3.6
MB91345 Series
A/D Start/End Channels Setting Registers (ADSCH,
ADECH)
These are registers to set a start channel and end channel of the A/D conversion.
Do not rewrite the ADSCH and ADECH registers during A/D conversion.
■ A/D Start/End Channel Setting Registers (ADSCH, ADECH)
ADSCH0(Upper)
Address
bit15
00002AH
TRGC
bit14
bit13
bit12
bit11
Reserved Reserved Reserved Reserved
bit10
bit9
bit8
Initial value
ANS2
ANS1
ANS0
0----000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ANE2
ANE1
ANE0
-----000B
ADECH0(Lower)
Address
00002BH
Reserved Reserved Reserved Reserved Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00003AH
TRGC
ANS2
ANS1
ANS0
0----000B
ADSCH1(Upper)
Reserved Reserved Reserved Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ANE2
ANE1
ANE0
-----000B
R/W
R/W
R/W
ADECH1(Lower)
Address
00003BH
Reserved Reserved Reserved Reserved Reserved
R/W
R/W
R/W
R/W
R/W
R/W: Readable/writable
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CHAPTER 18 A/D Converter
18.3 Registers of A/D Converter
MB91345 Series
[bit15] TRGC (triger control)
This bit controls the external trigger activation. When the initial value "0" is set, the own trigger signal
is taken.
When "1" is set, the external trigger signal of another unit becomes ATRG. It is used to activate UNIT0 and UNIT-1 by the same trigger ATRG0.
See the block diagram (Figure 18.3-3) of "■ Trigger Control Register (ADTGS)" in section "18.3.7
Trigger Control Register (ADTGS)" for ATRG0 and ATRG1.
Figure 18.3-2 Block Diagram of TRGC bit
ATRG0
ATRG1
S
E
L
S
E
L
UNIT - 0
TRGC
UNIT - 1
TRGC
[bit14, bit13, bit7 to bit5] Reserved
These are reserved bits.
[bit12, bit11, bit4, bit3] Reserved
These are reserved bits. Always write "0" to these bits.
[bit10 to bit8, bit2 to bit0] ANS2 to ANS0, ANE2 to ANE0
These bits set a start channel and end channel of the A/D conversion.
When the same channels are written to the ANS2 to ANS0 and ANE2 to ANE0, the conversion is
performed only for one channel (single conversion).
When the continuous mode or stop mode is being set, the conversion returns to the start channel set by
the ANS2 to ANS0 after the conversion of the channels set by these bits ends.
These bits are initialized to ANS=000B and ANE=000B at reset.
Note:
When the set channel is ANS > ANE, the operation will not be performed correctly. Be sure to set
ANS  ANE.
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CHAPTER 18 A/D Converter
18.3 Registers of A/D Converter
MB91345 Series
[bit10 to bit8] ANS2, ANS1, ANS0 (Analog start channel set)
[bit2 to bit0] ANE2, ANE1, ANE0 (Analog end channel set)
600
ANS2
ANE2
ANS1
ANE1
ANS0
ANE0
Start/End channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN6
1
1
1
AN7
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CM71-10132-3E
CHAPTER 18 A/D Converter
18.3 Registers of A/D Converter
MB91345 Series
18.3.7
Trigger Control Register (ADTGS)
The trigger control register (ADTGS) selects either the external trigger signal ADTRG0
or ADTRG0-2, and selects either ADTRG1 or ADTRG1-2.
■ Trigger Control Register (ADTGS)
ADTGS
Address
bit7
bit6
bit5
bit4
bit3
bit2
000578H






R/W
R/W
R/W
R/W
R/W
R/W
bit1
bit0
ADTRGS1 ADTRGS0
R/W
Initial value
------00B
R/W
R/W: Readable/writable
[bit1, bit0] ADTRGS1, ADTRGS0
These bits control the selection of the external trigger signals. When the initial value "0" is set to both,
ADTRG0 and ADTRG1 are selected. When "1" is set, ADTRG0-2 and ADTRG1-2 are selected.
The block diagram is shown below.
Figure 18.3-3 Block Diagram of Trigger Control Register (ADTGS)
ADTRG0
ADTRG0-2
ADTRG1
ADTRG1-2
ADTRGS0
CM71-10132-3E
S
E
L
ATRG0
S
E
L
ATRG1
ADTRGS1
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CHAPTER 18 A/D Converter
18.4 Operation of A/D Converter
18.4
MB91345 Series
Operation of A/D Converter
The A/D converter operates using a successive comparison method and its resolution
is 10 bits. The conversion data registers (ADCR0 and ADCR1) are rewritten each time
the conversion is completed because this A/D converter has only one register (16 bits)
for storing the conversion result. Therefore, it is recommended to convert by
transferring the conversion data to a memory by using DMA since the A/D converter is
not appropriate for the continuous conversion processing by itself. The operation
modes are described below.
■ Single Mode
This mode sequentially converts the analog input set by the ANS and ANE bits, and A/D stops the
operation after performing conversion up to the end channel specified by the ANE bit. The conversion
operation is performed only for either one of the channels if the start channel and end channel are the same
(ANS=ANE).
[Example]
• ANS = 000B, ANE = 011B
Start  AN0  AN1 AN2  AN3  End
• ANS = 010B, ANE = 010B
Start  AN2  End
■ Continuous Mode
This mode sequentially converts the analog input set by the ANS and ANE bits, returns to the analog input
of ANS after performing the conversion up to the end channel defined by the ANE bit, and continues the
conversion operation. The conversion operation continues only for either one of the channels if the start
channel and end channel are the same (ANS=ANE).
[Example]
• ANS = 000B, ANE = 011B
Start  AN0  AN1  AN2  AN3  AN0  Repeated
• ANS = 010B, ANE = 010B
Start  AN2  AN2  AN2  Repeated
Conversion in the continuous mode continues repeatedly until "0" is written to the BUSY bit (writing "0" to
the BUSY bit  terminate forcibly). Please note that the conversion in progress will be stopped before it is
completed when a forced stop is performed (If operation is forcibly terminated, the conversion register
holds the previous data that the conversion has been completed).
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CHAPTER 18 A/D Converter
18.4 Operation of A/D Converter
MB91345 Series
■ Stop Mode
This mode sequentially converts the analog input set by the ANS and ANE bits and temporarily stops the
operation each time conversion has been performed for one channel. To clear the temporary stop, start A/D
conversion again.
This mode returns to the analog input of ANS after performing conversion up to the end channel specified
by the ANE bit, and then continues the operation. The conversion operation is performed for either one of
the channels if the start channel and end channel are the same (ANS=ANE).
[Example]
• ANS = 000B, ANE = 011B
Start  AN0  Stop  Start  AN1  Stop  Start  AN2  Stop 
Start  AN3  Stop  Start  AN0 Repeated
• ANS = 010B, ANE = 010B
Start  AN2  Stop  Start  AN2  Stop  Start  AN2  Repeated
Only start sources specified by STS1 and STS0 are used at this time.
This mode can be used to synchronize the start of the conversion.
■ Setting Example of the Compare/Sampling time
Table 18.4-1 Specification of Compare Time Setting Register (1 / 2)
CM71-10132-3E
Resource clock frequency [MHz]
Register value
CT5 to CT0
33
30
25
24
16
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
727
1,030
1,333
1,636
1,939
2,242
2,545
2,848
3,152
3,455
3,758
4,061
4,364
4,667
4,970
5,273
5,576
5,879
6,182
6,485
6,788
7,091
800
1,133
1,467
1,800
2,133
2,467
2,800
3,133
3,467
3,800
4,133
4,467
4,800
5,133
5,467
5,800
6,133
6,467
6,800
7,133
7,467
7,800
960
1,360
1,760
2,160
2,560
2,960
3,360
3,760
4,160
4,560
4,960
5,360
5,760
4,160
6,560
6,690
7,360
7,760
8,160
8,560
8,960
9,360
1,000
1,417
1,833
2,250
2,667
3,083
3,500
3,917
4,333
4,750
5,167
5,538
6,000
6,417
6,833
7,250
7,667
8,083
8,500
8,917
9,333
9,750
875
1,500
2,125
2,750
3,375
4,000
4,625
5,250
5,875
6,500
7,125
7,750
8,375
9,000
9,625
10,250
10,875
11,500
12,125
12,750
13,375
14,000
14,625
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CHAPTER 18 A/D Converter
18.4 Operation of A/D Converter
MB91345 Series
Table 18.4-1 Specification of Compare Time Setting Register (2 / 2)
Resource clock frequency [MHz]
Register value
CT5 to CT0
33
30
25
24
16
24
25
26
27
28
29
30
31

7,394
7,697
8,000
8,303
8,606
8,909
9,121
9,515

8,133
8,467
8,800
9,133
9,467
9,800
10,133
10,467

9,760
10,160
10,560
10,960
11,360
11,760
12,160
12,560

10,167
10,583
11,000
11,417
11,833
12,250
12,677
13,083

15,250
15,875
16,500
17,125
17,750
18,375
19,000
19,625

(Note) Setting is not allowed for "-".
The above table shows the time only for comparison (ns).
Table 18.4-2 Specification of Sampling Time Setting Register
Resource clock
frequency [MHz]
Sampling time [ns]
External impedance [k]
Register value
ST9 to ST0
33
30
25
24
16
33
30
25
24
16
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

212
242
273
303
333
364
394
424
455
485
515
545
576
606
636

233
267
300
333
367
400
433
467
500
533
567
600
633
667
700

280
320
360
400
440
480
520
560
600
640
680
720
760
800
840

292
333
375
417
458
500
542
583
625
667
708
750
792
833
875

438
500
563
625
688
750
813
875
938
1,000
1,063
1,125
1,188
1,250
1,313

26
215
405
594
783
973
1,162
1,352
1,541
1,730
1,920
2,109
2,298
2,488
2,677

158
367
575
783
992
1,200
1,408
1,617
1,825
2,033
2,242
2,450
2,658
2,867
3,075

450
700
950
1,200
1,450
1,700
1,950
2,200
2,450
2,700
2,950
3,200
3,450
3,700
3,950

523
783
1,044
1,304
1,565
1,825
2,085
2,346
2,606
2,867
3,127
3,388
3,648
3,908
4,169

1,434
1,825
2,216
2,606
2,997
3,388
3,778
4,169
4,559
4,950
5,341
5,731
6,122
6,513
6,903

24

727

800

960

1,000

1,500

3,245

3,700

4,700

4,950

8,075

(Note) The above table shows the time only for sampling.
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CHAPTER 19
FLASH MEMORY
This chapter provides an outline of flash memory and
explains its register configuration, register functions,
and operations.
19.1
Outline of Flash Memory
19.2
Flash Memory Registers
19.3
Flash Memory Access Modes
19.4
Automatic Algorithm of Flash Memory
19.5
Execution Status of the Automatic Algorithm
19.6
Data Writing to and Erasing from Flash Memory
19.7
Restrictions on Data Polling Flag (DQ7) and How to
Avoid Erroneous Judgment
19.8
Notes on Flash Memory Programming
Code: CM71-00512-2E
Page: 606, 606, 607, 608, 609, 611, 613, 616, 627, 630, 636
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CHAPTER 19 FLASH MEMORY
19.1 Outline of Flash Memory
19.1
MB91345 Series
Outline of Flash Memory
MB91345 series contains a flash memory with a capacity of 512 Kbytes/1 Mbytes.
The internal flash memory operates on a single power supply voltage of 3.3 V, and can
be erased in sector units, erased all sectors at once, and written in half-word (16 bits)
units by the FR-CPU.
■ Outline of Flash Memory
This flash memory is an internal flash memory operated at 3 V. The flash memory enables
writing from an external device using a ROM writer just like a single flash memory does.
In addition to features equivalent to the features of a single flash memory, when this memory is
used as FR-CPU internal ROM, it becomes possible to read instructions and data in word units
(32 bits) and so high-speed device operation can be realized.
This product supports the following features by combining flash memory macros and FR-CPU
interface circuits:
•
Features for use as CPU memory, for storing programs and data
Accessibility through 32-bit bus when used as ROM
Allowing read, write, and erase (automatic algorithm*) by the CPU
•
Features equivalent to single flash memory product
Allowing read or write (automatic algorithm*) by a ROM writer
*: Automatic algorithm: embedded algorithm
Embedded Algorithm is a trademark of Advanced Micro Devices, Inc.
This section explains use of the flash memory accessed from the FR-CPU.
For information on using the flash memory accessed from a ROM writer, see the instruction
manual provided with the ROM writer.
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CHAPTER 19 FLASH MEMORY
19.1 Outline of Flash Memory
MB91345 Series
■ Block Diagram of Flash Memory
Figure 19.1-1 shows a block diagram of the flash memory.
Figure 19.1-1 Block Diagram of Flash Memory
Delay circuit
RDY/BUSYX
Control signal
RESETX
BYEX
OEX
FLASH memory
512K/1M bytes
WEX
RDY
WE
Bus control signal
CEX
FA18(FA19)
DO31
to FA0
DI15 to DI0 to DO0
Address buffer
FA18(FA19)
to FA0
Data buffer
FD31
to FD0
FR F-bus (instruction/data)
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CHAPTER 19 FLASH MEMORY
19.1 Outline of Flash Memory
MB91345 Series
■ Memory Map of Flash Memory
Figure 19.1-2 shows a sector map of the flash memory in CPU mode.
Figure 19.1-2 Memory Map of Flash Memory (MB91F345B: 512 Kbytes)
00100000H
000FC000H
SA7
SA5
8Kbytes
8Kbytes
SA6
SA4
8Kbytes
000F8000H
000F4000H
SA3
8Kbytes
SA2
8Kbytes
000F0000H
SA1
8Kbytes
SA0
8Kbytes
SA15
8Kbytes
SA14
32Kbytes
32Kbytes
000E0000H
SA13
SA12
64Kbytes
64Kbytes
000C0000H
SA11
SA10
64Kbytes
64Kbytes
000A0000H
SA9
SA8
64Kbytes
64Kbytes
00080000H
+0
+1
+2
+3
+4
+5
+6
+7
64 bits
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CHAPTER 19 FLASH MEMORY
19.1 Outline of Flash Memory
MB91345 Series
Figure 19.1-3 Memory Map of Flash Memory (MB91F346B: 1 Mbytes)
00180000H
SA22
SA23
64Kbytes
64Kbytes
00160000H
SA20
SA21
64Kbytes
64Kbytes
00140000H
SA18
SA19
64Kbytes
64Kbytes
00120000H
SA16
SA17
64Kbytes
64Kbytes
00100000H
000FC000H
SA7
8Kbytes
SA6
8Kbytes
000F8000H
SA5
8Kbytes
SA4
8Kbytes
000F4000H
SA3
8Kbytes
SA2
8Kbytes
000F0000H
SA1
8Kbytes
SA0
8Kbytes
SA14
SA15
32Kbytes
32Kbytes
000E0000H
SA12
SA13
64Kbytes
64Kbytes
000C0000H
SA10
SA11
64Kbytes
64Kbytes
000A0000H
SA8
SA9
64Kbytes
64Kbytes
00080000H
+0
+1
+2
+3
+4
+5
+6
+7
64bits
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CHAPTER 19 FLASH MEMORY
19.2 Flash Memory Registers
19.2
MB91345 Series
Flash Memory Registers
The flash memory has two registers: flash control status register (FLCR) and wait
register (FLWC).
■ List of Flash Memory Registers
Figure 19.2-1 shows a list of flash memory registers.
Figure 19.2-1 Flash Memory Registers
bit 7
0
Flash control status register(FLCR)
Wait register (FLWC)
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CHAPTER 19 FLASH MEMORY
19.2 Flash Memory Registers
MB91345 Series
19.2.1
Flash Control Status Register (FLCR)
The flash control status register (FLCR) indicates the operation status of flash memory.
■ Configuration of Flash Control Status Register (FLCR) (CPU Mode)
This register controls writing to flash memory.
This register can only be accessed in CPU mode. Do not access this register using the Read
Modify Write instruction.
Figure 19.2-2 shows the bit configuration of FLCR.
Figure 19.2-2 Bit Configuration of FLCR
bit7
00007000H
bit6
bit5
bit4
Reserved Reserved Reserved Reserved
R/W
(0)
R/W
(1)
R/W
(1)
R
(0)
bit3
bit2
bit1
bit0
RDY
Reserved
WE
Reserved
R
(0)
R/W
(0)
R/W
(0)
R/W
(0)
[bit7] Reserved bit
This is a reserved bit. Always set this bit to "0."
[bit6, bit5] Reserved bits
These are reserved bits. Always set these bits to "1."
[bit4] Reserved bit
This is a reserved bit. It is initialized to "0" during a reset.
[bit3] RDY: Ready bit
This bit indicates the operation status of the automatic algorithm (data write/erase).
The read data indicates the flash memory status as listed in the table below.
0
Data writing or erasing is in process, flash memory is not ready to accept a new
Data write/Erase command, and no data can be read from a flash memory
address.
1
Flash memory is ready to accept a new Data write/Erase command and data can
be read from a flash memory address.
• This bit is not initialized during a reset.
• Only read operation is possible, but write operation does not affect this bit.
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CHAPTER 19 FLASH MEMORY
19.2 Flash Memory Registers
MB91345 Series
[bit2] Reserved bit
This is a reserved bit. Always set this bit to "0".
[bit1] WE : Write Enable bit
This bit controls the writing of data and commands to flash memory in CPU mode.
In flash memory mode, writing is enabled regardless of this bit.
0
Writing to flash memory is disabled and data is read from flash memory in 32-bit
access mode.
1
Writing to flash memory is enabled and data is read from flash memory in 16-bit
access mode.
This bit is initialized to "0" during reset.
Notes:
• If this is overwritten, confirm that the RDY bit has stopped the automatic algorithm. When the RDY
bit is set to "0", the value of this bit cannot be charged.
• When WE=1, do not respond to the instruction access request and only respond to the data
access request.
[bit0] Reserved bit
This is a reserved bit. Always set this bit to "0".
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CHAPTER 19 FLASH MEMORY
19.2 Flash Memory Registers
MB91345 Series
19.2.2
Wait Register (FLWC)
The wait register (FLWC) controls the wait status of flash memory access in CPU mode.
■ Bit Configuration of the Wait Register (FLWC)
The bit configuration of the wait register (FLWC) is shown below:
Figure 19.2-3 Bit configuration of the wait register (FLWC)
FLWC
Address
bit7
00007004H
bit6
bit4
bit3
bit2
Reserved Reserved Reserved Reserved Reserved WTC2
R/W
R/W:
bit5
R/W
R/W
R/W
R/W
R/W
bit1
bit0
Initial value
WTC1
WTC0
00110011B
R/W
R/W
Readable/writable
[bit7 to bit3] Reserved: Reserved bits
These are reserved bits.
Always set them to "00110B".
[bit2 to bit0] WTC2, WTC1, WTC0: Wait cycle bits
WTC2
WTC1
WTC0
Wait cycle
Read
Write
0
0
0

Setting not allowed
Setting not allowed
0
0
1
1
Setting not allowed
Setting not allowed
0
1
0
2
Allowed Up to 50 MHz
Setting not allowed
0
1
1
3
Allowed Up to 50 MHz
Allowed Up to 50 MHz
1
0
0
4
Setting not allowed
Setting not allowed
1
0
1
5
Setting not allowed
Setting not allowed
1
1
0
6
Setting not allowed
Setting not allowed
1
1
1
7
Setting not allowed
Setting not allowed
[Initial value]
• These bits are initialized to "011B" at reset.
• Set them not to exceed the cycle number set by FAC1, FAC0 bits.
• The initial value is set for write access. For read only (when FLCR WE bit is "0"), high-speed setting
(WTC2 to WTC0 = 010B) is allowed.
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CHAPTER 19 FLASH MEMORY
19.3 Flash Memory Access Modes
19.3
MB91345 Series
Flash Memory Access Modes
The following two types of access mode are available for the FR-CPU:
• FR-CPU ROM mode:
One word (32 bits) data can be read but not written in a single cycle.
• FR-CPU Programming mode:
Word (32 bits) access is prohibited but reading/writing data with half-word (16 bits) is
enabled.
■ FR-CPU ROM Mode (32 Bits, Read Only)
In this mode, the flash memory serves as FR-CPU internal ROM. This mode enables to read one
word (32 bits) in one cycle but does not enable to write to flash memory or to start the automatic
algorithm.
❍ Mode specification
When specifying this mode, set the WE bit of the flash control status register (FLCR) to "0".
This mode is always set after releasing a reset at CPU run time.
This mode can be set only when the CPU is running.
❍ Detailed operation
In this mode, one word (32 bits) can be read from the flash memory area in one cycle.
❍ Restrictions
•
Address assignment and endians in this mode differ from those for writing with the ROM
writer.
•
In this mode, commands and data cannot be written to flash memory together.
■ FR-CPU Programming Mode (16 Bits, Read/Write)
This mode enables data to be written and erased. As one word (32 bits) cannot be accessed in
one cycle, program execution in flash memory is disabled in this mode.
❍ Mode specification
When specifying this mode, set the WE bit of the flash control status register (FLCR) to "1".
When a reset is released at CPU run time, the WE bit indicates "0". To set to this mode, set the
WE bit to "1". If the WE bit is set again to "0" through a writing operation or because of a reset,
the device enters FR-CPU ROM mode.
When the RDY bit of the flash control status register (FLCR) is "0", the WE bit cannot be overwritten.
When overwriting the WE bit, ensure that the RDY bit is set to "1".
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19.3 Flash Memory Access Modes
MB91345 Series
❍ Detailed operation
Half word (16 bits) data can be read from the flash memory area in one cycle.
The automatic algorithm can be started by writing a command to flash memory.
When the automatic algorithm starts, data can be written to or erased from flash memory. For
details on the automatic algorithm, see "19.4 Automatic Algorithm of Flash Memory".
❍ Restrictions
•
Address assignment and endians in this mode differ from those for writing with the ROM
writer.
•
This mode inhibits reading data in words (32 bits).
■ Automatic Algorithm Execution Status
When the automatic algorithm is started in FR-CPU programming mode, the operation status of
the automatic algorithm can be checked by reading the RDY bit in the flash control status register
(FLCR).
When the RDY bit is set to "0", data is being written or erased with the automatic algorithm, and
no write or erase command can be accepted. Moreover, data cannot be read from any address in
flash memory.
Data read with the RDY bit set to "0" is a hardware sequence flag to indicate flash memory
status.
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19.4 Automatic Algorithm of Flash Memory
19.4
MB91345 Series
Automatic Algorithm of Flash Memory
The flash memory automatic algorithm can be started using a Reset, Write, Chip Erase,
or Sector Erase command. The Sector Erase command can suspend and resume the
automatic algorithm.
■ Command Sequence
To start the automatic algorithm, write one to six half-words (16 bits) data in sequence. This is
called the command.
If the address and data to be written are invalid or are written in an incorrect sequence, the flash
memory is reset to read mode.
Table 19.4-1 lists commands that can be used to write data to or erase data from flash memory.
Table 19.4-1 Command Sequence
Fifth bus write cycle
Sixth bus write cycle
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
1
RA
RD
--
--
--
--
--
--
--
--
--
--
Reset*2
1
AXXXXH
F0F0H
--
--
--
--
--
--
--
--
--
--
Reset
3
A5556H
AAAAH
AAAAAH
5555H
A5556H
F0F0H
--
--
--
--
--
--
Data Write
4
A5556H
AAAAH
AAAAAH
5555H
A5556H
A0A0H
PA
PD
--
--
--
--
Chip Erase
6
A5556H
AAAAH
AAAAAH
5555H
A5556H
8080H
A5556H
AAAAH
AAAABH
5555H
A5556H
1010H
Sector Erase
6
A5556H
AAAAH
AAAAAH
5555H
A5556H
8080H
A5556H
AAAAH
AAAABH
5555H
SA*3
3030H
Command
sequence
Bus write
cycle
Read*1
First bus write cycle Second bus write cycle Third bus write cycle Fourth bus write cycle
Sector erase temporary stop
Erasing sectors is temporary stopped by specifying the address = AXXXXH, data = B0B0H.
Sector erase restart
Erasing sectors is resumed after being temporary stopped by specifying the address = AXXXXH, data = 3030H.
Continuous
mode
3
A5556H
AAAAH
AAAABH
5555H
A5557H
2020H
--
--
--
--
--
--
Write
continuously
2
AXXXXH
A0A0H
PA
PD
--
--
--
--
--
--
--
--
Continuous
mode reset
2
AXXXXH
9090H
AXXXXH
F0F0H
or 0000H
--
--
--
--
--
--
--
--
RA: Read address
PA: Write address
SA: Sector address
RD: Read data
*1: Reading of the data array doesn't require the command cycle.
*2: When the timing limit over flag (TLOVER) is "1", the reset command is required to return to the read operation of the data array.
*3: Sector address should specify the address that indicates lower 32 bits side of the address space that indicates the inside of the desired sector.
(example) Lower 4 bits are either of 2H, 6H, AH or EH addresses.
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19.4 Automatic Algorithm of Flash Memory
MB91345 Series
❍ Reset command
Set flash memory into Read/Reset mode.
The flash memory remains in reading state until another command is entered.
When the power is turned on, flash memory is automatically set to the read or reset state. In this
case, data can be read without a reset command of the automatic algorithm.
To return to read/reset mode after the time limit is exceeded, issue a Reset command. Data is
read from flash memory in the next read cycle.
❍ Program (Data write)
In FR-CPU programming mode, data is basically written in half-word units. The data write
operation is performed in four cycles of bus operation. Writing to memory starts when the last
write cycle is performed.
After executing automatic algorithm of data writing, it becomes unnecessary to control the flash
memory externally. The flash memory itself internally generates write pulses to check the margin
of the cells to which data is written. The data polling function compares bit7 of the original data
with data polling flag (DQ7) of the written data, and if these bits are the same, the automatic write
operation ends (see "■Hardware Sequence Flag" in "19.5 Execution Status of the Automatic
Algorithm"). The automatic write operation then returns to the read/reset mode and accepts no
more write addresses. After that, the flash memory requests the next valid address. In this
manner, the data polling function indicates a write operation in memory.
During a write operation, all commands written to the flash memory are ignored. If a hardware
reset starts during write operation, the data at the address for writing may become invalid.
Writing operations can be performed in any address sequence and outside of sector boundaries.
However, write operations cannot change a data item "0" to "1". If a "0" is overwritten with a "1",
the data polling algorithm either determines that the elements are defective, or that "1" has been
written. In the latter case, however, the respective data item is read as "0" in reset or read/reset
mode. A data item "0" can be changed to "1" only after an erase operation.
❍ Chip Erase
The Chip Erase command sequence ("erase all sectors simultaneously") is executed in six
access cycles.
During the Chip Erase command sequence, the user does not have to write to flash memory
before the erase operation. When the automatic algorithm of chip erasure is executed, flash
memory checks cell states by writing a pattern of zeros before automatically erasing the contents
of all cells (preprogram). In this operation, flash memory does not have to be controlled
externally.
The automatic erase operation starts with the write operation of the command sequence and
ends when data polling flag (DQ7) is set to "1", where flash memory returns to the read/reset
mode. The chip erase time can be expressed as follows: time for sector erase  number of all
sectors + time for writing to the chip (preprogram).
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19.4 Automatic Algorithm of Flash Memory
MB91345 Series
❍ Sector Erase
The Sector Erase command sequence is executed in six access cycles. The Sector Erase
command is entered in the sixth cycle for starting the sector erase operation. The next Sector
Erase command can be accepted within a time-out period of 40 s to 160 s after the last Sector
Erase command is written.
Multiple Sector Erase commands can be accepted during the six bus cycles of the writing
operation. During the command sequence, Sector Erase commands (3030H) for sectors whose
contents are to be erased simultaneously are written consecutively to the addresses for these
sectors. The sector erase operation itself starts from the end of the time-out period of 40 s to
160 s after the last Sector Erase command is written. When the contents of multiple sectors are
erased simultaneously, the subsequent Sector Erase commands must be input within the 40 s
time-out period to ensure that they are accepted. For checking whether the succeeding Sector
Erase command is valid, read sector erase timer flag (DQ3) (see "■Hardware Sequence Flag" in
"19.5 Execution Status of the Automatic Algorithm").
During the time-out period, any command other than Sector Erase and Temporarily Stop Erase is
reset at read time, and the preceding command sequence is ignored. In the case of the
Temporary Stop Erase command, the contends of the sector are erased again and the erase
operation is completed.
Any combination and number (from 0 to 6) of sector addresses can be entered in the sector erase
buffers.
The user does not have to write to flash memory before the sector erase operation.
Flash memory automatically writes to all cells in a sector whose data is automatically erased
(preprogram). When the contents of a sector are erased, the other cells remain intact. In these
operations, flash memory does not have to be controlled externally.
The automatic sector erase operation starts from the end of the 40 s to 160 s time-out period
after the last Sector Erase command is written. When data polling flag (DQ7) is set to "1", the
automatic sector erase operation ends and flash memory returns to the read/reset mode. At this
time, other commands are ignored.
The data polling function is enabled for any sector address in which data has been erased. The
time required for erasing the data of multiple sectors can be expressed as follows: time for sector
erase + time for sector write (preprogram) × number of erased sectors.
❍ Temporarily Stop Erase
The Temporarily Stop Erase command temporarily stops the automatic algorithm in flash memory
when the user is erasing the data of a sector, thereby making it possible to write data to and read
data from the other sectors. This command is valid only during the sector erase operation and
ignored during chip erase and write operations.
The Temporarily Stop Erase command (B0B0H) is effective only during sector erasure operation
that includes the sector erase time-out period after a Sector Erase command (3030H) is issued.
When this command is entered within the time-out period, waiting for time-out ends and the erase
operation is suspended. The erase operation is restarted when a Restart Erase command was
written. Temporarily Stop Erase and Restart Erase commands can be entered with any address.
When a Temporarily Stop Erase command is entered during sector erase operation, the flash
memory needs a maximum of 20 s to stop the erase operation. When flash memory enters
temporary erase stop mode, a RDY bit in FLCR register and data polling flag (DQ7) output "1",
and toggle bit flag (DQ6) stops to toggle. For checking whether the erase operation has stopped,
enter the address of the sector whose data is being erased and read the values of toggle bit flag
(DQ6) and data polling flag (DQ7). At this time, another Temporarily Stop Erase command entry
is ignored.
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19.4 Automatic Algorithm of Flash Memory
When the erase operation stops, flash memory enters the temporary erase stop and read mode.
Data reading is enabled in this mode for sectors that are not subject to temporary erase. Other
than that, there is no difference from the standard read operation.
After the temporary erase stop and read mode is entered, the user can write to flash memory by
writing a Write command sequence. The write mode in this case is the temporary erase stop and
write mode. In this mode, data write operations become valid for sectors that are not subject to
temporary erase stop. Other than that, there is no difference from the standard byte writing
operation. The temporary toggle bit flag (DQ6) can be used to detect this operation.
Note that toggle bit flag (DQ6) can be read from any address, but data polling flag (DQ7) must be
read from write addresses.
To restart the sector erase operation, a Restart Erase command (3030H) must be entered.
Another Restart Erase command entry is ignored in this case. On the other hand, a Temporarily
Stop Erase command can be entered after flash memory restarts the erase operation.
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19.5 Execution Status of the Automatic Algorithm
19.5
MB91345 Series
Execution Status of the Automatic Algorithm
Data write/erasure operation of flash memory is performed by automatic algorithm. The
operation status of automatic algorithm can be checked by hardware sequence flag and
RDY bit.
■ RDY bit
The flash memory uses RDY bit in flash memory status register (FLCR) in addition to the hardware
sequence flag to indicate whether the automatic algorithm is running or ends.
When the value of the RDY bit is "0", the flash memory is executing a data write or erase
operation, where new Data Write and Erase commands are not accepted.
When the value of the RDY bit is "1", the flash memory is in read/data write or erase operation
wait state.
■ Hardware Sequence Flag
For obtaining the hardware sequence flag as data, read an arbitrary address (an odd address in
byte access) from flash memory when the automatic algorithm is executed. The data contains five
validity bits which indicate the status of the automatic algorithm.
When the automatic algorithm is executed for ROM1, specify an address in ROM1. When executed
for ROM2, specify an address in ROM2.
Figure 19.5-1 shows the structure of the hardware sequence flag.
Figure 19.5-1 Structure of the Hardware Sequence Flag
bit
During half-word read
During byte read
(from odd address only)
15
8 7
0
Hardware sequence flag
(Undefined)
0
bit 7
Hardware sequence flag
* Reading in units of words is disabled. (Only use this function in FR-CPU programming mode.)
bit
7
6
5
4
3
2
1
0
(In half-word and
DPOLL TOGGLE TLOVER (Undefined) SETIMER (Undefined) (Undefined) (Undefined)
byte access)
The hardware sequence flag becomes invalid in FR-CPU ROM mode. Always use FR-CPU
programming mode and read only in half-words or bytes.
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19.5 Execution Status of the Automatic Algorithm
MB91345 Series
Table 19.5-1 lists the possible statuses of the hardware sequence flag.
Table 19.5-1 Statuses of the Hardware Sequence Flag
Status
DPOLL
Data write
Chip erase
Sector erase
Executing
Temporary
erase stop
mode
TOGGLE TLOVER SETIMR
Reverse data
Toggle
0
0
0
Toggle
0
1
Time-out duration
1
Toggle
0
0
Erase duration
0
Toggle
0
1
Read (from sectors in temporary erase
stop)
1
1
0
0
Data
Data
Data
Data
Reverse data
Toggle*
0
0
Reverse data
Toggle
1
0
0
Toggle
1
1
0
Toggle
1
1
Read (from sectors not in temporary
erase stop)
Data write (to sectors not in temporary
erase stop)
Data write
Time limit
Chip/sector erase
exceeded
Write operation during temporary erase stop
*: TOGGLE toggles continuous read operations from any address.
The hardware sequence flags are explained below.
[bit7] DPOLL: Data polling flag (DQ7)
This flag is used with the data polling function to report that the automatic algorithm is being
executed or terminated.
• Automatic data write operation status
When read access is performed while the automatic algorithm of data write is being executed,
flash memory outputs the inversion of bit7 of the last data written regardless of the address
indicated by the address signal. When read access is performed at the end of the automatic
write algorithm, flash memory outputs bit7 of the read data to the address indicated by the
address signal.
• Chip erase operation status
When read access is performed while the automatic algorithm of chip erase is being
executed, flash memory outputs "0", regardless of the address indicated by the address
signal. Similarly, flash memory outputs "1" at the end of the chip erase.
• During a sector erase operation:
When read access is performed from the sector being erased during execution of the sector
erase automatic algorithm, it outputs "0". Due to restrictions on the function in this series, the
flash memory outputs "1" for 40 s to 160 s after the sector erase command is issued, and
then outputs "0".
After the sector erase is terminated, the flash memory outputs "1".
For restrictions on the data polling flag (DQ7) and how to avoid erroneous judgment of sector
erase completion, see section "19.7 Restrictions on Data Polling Flag (DQ7) and How to Avoid
Erroneous Judgment".
• Temporary sector erase stop status
When read access is performed during temporary sector erase stop status, flash memory
outputs "1" when the address indicated by the address signal is included in the sector in erase
status. If the address is not included in the sector in erase status, flash memory outputs bit7 of
the read value to the address. For checking whether a sector is in temporary sector erase stop
status and which sector is in erase status, read this bit and the toggle bit flag.
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19.5 Execution Status of the Automatic Algorithm
MB91345 Series
Note:
Read access to a specified address is ignored while the automatic algorithm is active. Values can be
output to other bits after data polling flag operation terminates in data read operation. Therefore,
when data is to be read after terminating the automatic algorithm, confirm that data polling is
terminated in the current read access.
[bit6] TOGGLE: Toggle bit flag (DQ6)
This flag is used with the toggle bit function to mainly report that the automatic algorithm is being
executed or terminated as well as data polling flag.
• Write or chip/sector erase operation status
When continuous read operations are performed while the automatic algorithm of data write
or chip/sector erase is being executed, flash memory outputs "1" and "0" toggle results to bit6
regardless of the address indicated by the address signal. When continuous read operations
are performed at the end of the automatic algorithm of write or chip/sector erase algorithm,
flash memory stops toggle operation of bit6 and outputs bit6 (DATA: 6) of the data read from
the address indicated by the address signal.
If a write target sector is protected from overwriting during a write operation, the toggle bit
tries to toggle for about 2 s and stops toggling without changing data. If all selected sectors
are protected from overwriting, the toggle bit tries to toggle for about 100 s and the system
returns to read/reset status without changing data.
• Temporary sector erase stop status
When a read operation is performed during a temporary sector erase stop operation, flash
memory outputs "1" if the address indicated by the address signal is included in the sector in
erase state. If the address is not included in the sector in erase state, flash memory outputs
the data of bit6 of the read value at the address indicated by the address signal.
[bit5] TLOVER: Timing limit over flag (DQ5)
This flag is used to report that a time (number of internal pulses) specified internally with flash
memory is exceeded while the automatic algorithm is being executed.
• Write or chip/sector erase operation status
When read access is performed within a specified time (necessary for write or erase) after
activating the automatic algorithm of write or chip/sector erase, flash memory outputs "0". If
read access is performed beyond the specified time, flash memory outputs "1". Because these
output operations are not affected by whether the automatic algorithm is being executed or
terminated, these operations can be used to check whether data write or erase operation is
successful. If flash memory outputs "1" while the automatic algorithm is being executed with
the data polling function or toggle bit function, consider the write operation to be unsuccessful.
For example, when "1" is written to a flash memory address where "0" is written, failure
occurs. Flash memory is locked and the automatic algorithm is not terminated. Thus, valid
data is not output from the data polling flag. The toggle bit flag does not stop toggling, the time
limit is exceeded, and "1" is output to the TLOVER flag. This status indicates that flash
memory was not used correctly, not that it was defective. Execute a Reset command.
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19.5 Execution Status of the Automatic Algorithm
MB91345 Series
[bit3] SETIMR: Sector erase timer flag (DQ3)
This flag is used to report that sector erasure is being awaited after starting a Sector Erase
command.
• Sector erase operation status
When read access is performed within a sector erase time-out period after starting a Sector
Erase command, flash memory outputs "0" regardless of the address indicated by the address
signal of the target sector. If read access is performed beyond the time-out period, flash memory
outputs "1" regardless of the address.
When "1" is set in this flag while the data polling or toggle bit function indicates that the
automatic algorithm is being executed, an internally controlled erase operation has started.
The writing of subsequent sector erase code and commands other than Erase Temporary
Stop is ignored until erase operation terminates.
When this flag is "0", flash memory accepts another sector erase code entry. In this case, it is
recommended to check the status of this flag by software before writing the succeeding sector
erase code. If this flag is "1" at the second time of status check, the additional sector erase
code may not be accepted.
• Sector erase operation status
When a read operation is performed during a temporary sector erase stop operation, flash
memory outputs "1" if the address indicated by the address signal is included in the sector that
is subject to the erase operation. If the address is not included in the sector that is subject to
the erase operation, flash memory outputs the data of bit3 of the read value at the address
indicated by the address signal.
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19.6 Data Writing to and Erasing from Flash Memory
19.6
MB91345 Series
Data Writing to and Erasing from Flash Memory
This section explains how to issue a command to start the automatic algorithm for
following operations in flash memory.
• Reset • Data write • Chip erase • Sector erase • Temporary sector erase stop
• Sector erase restart
■ Data Writing/Erase
Automatic algorithm (data write, chip erase, sector erase, temporary sector erase stop, sector
erase restart) of flash memory is activated by writing the command sequence into bus. The write
cycles for each bus must always be executed continuously. Termination of the automatic
algorithm can be checked with the data polling function and toggle bit function. Flash memory is
set again into read/reset status after the automatic algorithm terminates normally.
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19.6 Data Writing to and Erasing from Flash Memory
MB91345 Series
19.6.1
Read/Reset Status
This section explains the procedure to set flash memory into read/reset status by
issuing reset command.
■ Read/Reset Status
To set the flash memory read/reset status, issue the reset command sequence table continuously
to target sector in the flash memory.
A bus operation is performed one or three times with a Reset command sequence. There is no
essential difference between these two sequences. Read/reset status is the initial status of flash
memory, and flash memory is set in this status at power-on or when a command terminates
normally. In this status, the system waits for a command other than Read/Reset to be entered.
Data can be read using normal read access in this status. Programs can be accessed from the
CPU the same way the programs in mask ROM are accessed. The Read/Reset command is not
necessary for reading data in normal read access. This command is required, however, to
initialize the automatic algorithm if a command does not terminate normally.
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19.6 Data Writing to and Erasing from Flash Memory
19.6.2
MB91345 Series
Data Writing
This section explains the procedure to write data to flash memory by issuing data write
command.
■ Data Writing
To activate the automatic algorithm of data write, issue the data write command in command
sequence table continuously to target sector in flash memory. The automatic algorithm and
automatic writing start when writing data to the target address terminates in the fourth cycle.
❍ How to specify address
Only even-numbered addresses can be specified in write data cycles. If an odd-numbered address
is specified, data cannot be written correctly. In other words, data must be written to evennumbered addresses in units of half-words.
Data can be written by freely specifying the order of addresses where data is to be written.
Moreover, data can be written beyond sector boundaries. Note that items of data can only be
written with each write command in units of half-words.
❍ Notes on writing data
Data "0" cannot be changed to "1" in a write operation. If data "1" is overwritten, the data polling
algorithm or toggle operation does not terminate, and the flash memory device is considered
defective. An error is assumed with the time limit over flag if the specified write time is exceeded,
or if only data "1" is apparently written, although data "0" is read in read/reset status. Data "0" can
be changed to "1" only with an erase operation. All commands are ignored during automatic
writing. If a hardware reset is activated during writing, the data being written is not guaranteed.
❍ Write procedure
Figure 19.6-1 shows an example of the write procedure.
The status of the automatic algorithm in flash memory can be checked using the hardware
sequence flag. In the example in Figure 19.6-1, the data polling flag (DQ7) is used to check for
termination of the write operation.
Data for the flag check is read from the address where the last data was written.
The data polling flag (DQ7) changes together with the timing limit over flag (DQ5). Therefore,
data polling flag (DQ7) must be rechecked even though timing limit over flag (DQ5) is set to "1".
The toggle bit flag (DQ6) also stops toggling simultaneously when the value of timing limit over
flag (DQ5) is changed to "1". Therefore, this flag must also be rechecked.
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19.6 Data Writing to and Erasing from Flash Memory
MB91345 Series
Figure 19.6-1 Example of Flash Memory Writing Procedure
Writing start
Enable writing to FLASH memory
with WE (bit1) in FLCR.
Write command sequence
AAAAH
A5556H
5555H
AAAAAH
A0A0H
A5556H
Write address
Write data
Read internal adress
Data polling
(DPOLL)
Next address
Data
Data
0
Time limit
(TLOVER)
1
Read internal adress.
Data
Data polling
(DPOLL)
Data
Write error
NO
Last address
YES
Disable writing to FLASH memory
with WE (bit1) in FLCR.
Check hardware
sequence flag
DPOLL:Data polling flag (DQ6)
TLOVER:Timing limit over flag (DQ6)
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19.6 Data Writing to and Erasing from Flash Memory
19.6.3
MB91345 Series
Erasing Data (Chip Erase)
This section explains the procedures to erase all items of data in flash memory by
issuing chip erase commands.
■ Erasing Data (Chip Erase)
To erase all data in flash memory, issue the chip erase command in command sequence table to
the target section in flash memory.
Six bus operations are necessary to execute a chip erase operation. The operation starts when
the sixth write cycle is completed. The user need not write any value to flash memory before chip
erase operation. Flash memory automatically writes "0" to erase all cells.
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19.6 Data Writing to and Erasing from Flash Memory
MB91345 Series
19.6.4
Erasing Data (Sector Erase)
This section explains the procedures to erase specified sectors in flash memory by
issuing sector erase commands. Erasure in sector units is possible and two or more
sectors can be specified with this command.
■ Sector Erase
To erase the sectors, issue the sector erase command continuously to the target sector in the
flash memory.
❍ How to specify sectors
A sector erase operation can be performed with six bus operations. A 40s to 160s sector erase timeout period starts when a sector erase code (3030H) is written to an even-numbered address
accessible in the target sector in the sixth cycle. To erase another sector, a sector code (3030H)
must be written in the same cycle the same way.
❍ Note on specifying two or more sectors
A sector erase operation starts when the 40 s to 160 s sector erase time-out period terminates
after the final sector erase code is written. Therefore, when two or more sectors are to be
specified, the address and erase code of each target sector must be entered within 40 s (in the
sixth cycle of the command sequence) after specifying the preceding sector. Note that an address
and erase code not entered within 40 s may not be accepted. The sector erase timer flag (DQ3)
of hardware sequence flag can be used to check the validity of a written sector erase code. The
address at which the read sector erase time is written should indicate the target sector.
❍ Sector erase procedure
The hardware sequence flag can be used to check the status of the automatic algorithm in flash
memory.
Figure 19.6-2 shows an example of the sector erase procedure. In this example, the toggle bit
flag (DQ6) is used to check for termination of the erase operation.
Note that data for the flag check is read from the sector to be erased.
The toggle bit flag (DQ6) stops toggling simultaneously when the value of the timing limit over flag
(DQ5) changes to "1". Therefore, the toggle bit flag (DQ6) must be rechecked even though the
timing limit over flag (DQ5) is set to "1".
Because the data polling flag (DQ7) also changes with the timing limit over flag (DQ5), it must
also be rechecked.
■ Restrictions on Data Polling Flag (DQ7)
Due to restrictions on the function in this series, the data polling flag(DQ7) outputs "1" for 40 s to
160 s after the sector erase command is issued, and then outputs "0". After the sector erase is
terminated, the flash memory outputs "1".
For restrictions on the data polling flag (DQ7) and how to avoid erroneous judgment of sector
erase completion, see section "19.7 Restrictions on Data Polling Flag (DQ7) and How to Avoid
Erroneous Judgment".
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CHAPTER 19 FLASH MEMORY
19.6 Data Writing to and Erasing from Flash Memory
MB91345 Series
Figure 19.6-2 Example of Sector Erasing Procedure
Erase start
FLCR : WE(bit1)
Flash memory erase
enabled
Erase command sequence
A5556H
AAAAAH
A5556H
A5556H
AAAABH
Input to erase sector (3030H)
YES
Internal address read
AAAAH
5555H
8080H
AAAAH
5555H
Is there any
other sector?
NO
Internal address read 1
Sector
erase timer (DQ3)
Internal address read 2
Toggle bit (TOGGLE)
YES
Data 1 = Data 2 ?
No erasing specification
occurs within 40 μs
additionally.
Set the flag for starting
again from the remainder
andsuspend the erasing.
NO
Timing limit
(TLOVER)
Internal address read 1
Internal address read 2
: Check by hardware sequtnce flag
NO
Toggle bit (TOGGLE)
Data 1 = Data 2 ?
YES
Erase error
Set the flag
for starting again from
the remainder ?
YES
NO
FLCR : WE(bit1)
Flash memory erase
disabled
TOGGLE: Toggle bit flag (DQ6)
TLOVER: Timing limit over flag (DQ5)
630
Erase complete
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CM71-10132-3E
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19.6.5
CHAPTER 19 FLASH MEMORY
19.6 Data Writing to and Erasing from Flash Memory
Temporary Sector Erase Stop
This section explains the procedures to stop the sector erase operation temporarily by
issuing temporary sector erase stop command. When sector erase operation is
temporarily stopped by this command, the data can be read from a sector not being
erased by using this command.
■ Temporary Sector Erase Stop
To stop the sector erase temporarily, issue the temporary sector erase command in command
sequence table to target sector in flash memory.
This command stops erase operation temporarily, so, data read from a sector not being erased
becomes available. Data can only be read from the sector; data cannot be written there. This
command is only effective during sector erasure that includes an erase time-out period. It is ignored
during chip erase operation and write operation.
A sector erase operation is stopped temporarily by writing a temporary erase stop code (B0B0H).
The address where the temporary erase stop code is written should indicate an address in flash
memory. A Temporary Sector Erase Stop command issued during temporary erase stop status is
ignored.
If a Temporary Sector Erase Stop command is entered during a sector erase time-out period, the
sector erase time-out is immediately canceled and erase operation in progress is stopped. If a
Temporary Sector Erase Stop command is entered during a sector erase operation after the
sector erase time-out period elapses, sector erase operation is stopped temporarily after up to 20
s elapse.
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CHAPTER 19 FLASH MEMORY
19.6 Data Writing to and Erasing from Flash Memory
19.6.6
MB91345 Series
Sector Erase Restart
This section explains how to restart the temporarily stopped sector erase operation by
issuing the sector erase restart command.
■ Sector Erase Restart
To restart the sector erase which is temporarily stopped, issue the sector erase restart command
in command sequence table to target sector in flash memory.
Restart operation starts when an erase restart code (3030H) is written. The address where the
erase restart code is written should indicate an address in flash memory.
Sector Erase Restart commands issued during a sector erase operation are ignored.
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19.7
CHAPTER 19 FLASH MEMORY
19.7 Restrictions on Data Polling Flag (DQ7) and How to Avoid Erroneous
Judgment
Restrictions on Data Polling Flag (DQ7) and How to Avoid
Erroneous Judgment
This series has some restrictions on how to use the data polling flag (DQ7) during
execution of the automatic sector erase algorithm. This section describes such
restrictions and how to avoid erroneous judgment of sector erase completion.
■
Description of Problems due to Restrictions
The data polling flag (DQ7) is used to indicate that the execution of the automatic algorithm is
currently in progress or completed, by using the data polling function. In its original operation, as
shown in Figure 19.7-1, DQ7 outputs "0" after the sector erase command is issued when the
automatic algorithm is being started, and returns to "1" upon the completion of the erase
operation. Therefore, the DQ7 polling algorithm indicates the completion of the erase operation
by outputting "1".
In this series, DQ7 continues to output "1" for 40 s to 160 s, after the Sector Erase command is
issued, and then it outputs "0". When the erase operation is completed, it then returns to "1". For
this reason, if the sector erase polling is started while "1" is still being output immediately after the
sector erase command is issued, the erroneous judgment that the erase operation has been
completed may occur, although the erase operation has not actually started.
The timing for DQ7 to change from "1" to "0" after the sector erase command is accepted is the
same as the timing for the sector erase timer flag (DQ3), which indicates the sector erase timeout
period, to change from "0" to "1".
Figure 19.7-1 Actual Operation of Data Polling Flag (DQ7)
Writing the last 3030H by
sector erase command
Erase completed
Signal of internal
interruption
DQ7 (Normal)
DQ7(Problems)
First reading
40 μs to 160 μ s
DQ3
The following or other problems may occur, as a result of the erroneous judgment that the erase operation
has been completed,
(1) Runaway or abnormal operation may occur, because the value of the sequence flag is read from the
flash memory even when the CPU attempts to fetch instruction/data; therefore, the value of the program
cannot be read properly.
(2) If the next command is issued after the erroneous judgment that the sector erase operation has been
completed occurs, the first command may be cancelled, resulting in a return to the read state, or the next
command may not be accepted.
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CHAPTER 19 FLASH MEMORY
19.7 Restrictions on Data Polling Flag (DQ7) and How to Avoid
Erroneous Judgment
■
MB91345 Series
How to Avoid Problems
Use one of the following methods to avoid the problems.
● Polling using the toggle bit flag (DQ6)
Determine the state of the automatic algorithm using DQ6, as shown in Figure 19.6-2 in "19.6.4
Data (Sector Erase)"
Erasing
In the same manner as the data polling flag (DQ7), the toggle bit flag (DQ6) indicates that the automatic
algorithm is being executed or has terminated by the toggle bit function.
● Starting polling of DQ7 after the sector erase timeout period elapses
Before starting the polling of DQ7, wait for 160s or more by software after the sector erase command is
issued, or wait until DQ3 is set to "1" (end of the sector erase timeout period). Figure 19.7-2 shows the
judgment method using DQ3 after the sector erase command is issued.
Figure 19.7-2 How to Avoid Problems by Sector Erase Timer Flag (DQ3)
P
Internal address read
0
Sector erase timer flag
(DQ3)
1
Internal address read
Data polling flag (DQ7)
1
0
0
Timing limit over flag
(DQ5)
1
Internal address read
0
Data polling flag (DQ7)
1
Erase error
634
Sector erase
completed
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MB91345 Series
CHAPTER 19 FLASH MEMORY
19.7 Restrictions on Data Polling Flag (DQ7) and How to Avoid Erroneous
Judgment
● Data polling using the 8 bits of hardware sequence flags
Make a judgment by data polling using the 8 bits of hardware sequence flags, rather than using only the
polling of DQ7.
Figure 19.7-3 shows the judgment method using the data polling of the 8 bits after the sector erase
command is issued.
Figure 19.7-3 How to Avoid Problems by Data Polling of 8 Bits
P
Internal address read
Data (DQ0 to DQ7)?
FFH
other
0
Timing limit over flag
(DQ5)
1
Internal address read
other
Data (DQ0 to DQ7)?
FFH
Erase error
CM71-10132-3E
Sector erase
completed
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CHAPTER 19 FLASH MEMORY
19.8 Notes on Flash Memory Programming
19.8
MB91345 Series
Notes on Flash Memory Programming
This section contains notes on flash memory programming.
■
Notes on Flash Memory Programming
When rewriting flash memory using a program, beware of the following points:
• Do not reset while rewriting a flash memory. The contents written at the reset may become invalid.
• Do not execute programs in the flash memory when FR-CPU programming mode (FLCR register
WE=1). Additionally, under the same conditions, do not generate interrupts if an interrupt vector table
exists in the flash memory. In either case, normal value cannot be obtained from flash and so the
program runaway will occur.
• Use the toggle bit flag (DQ6) as well as the RDY bit of FLCR register to check for termination of the
write operation to the flash memory.
If the flash memory is a defective, the RDY bit of FLCR register indicating the termination of the write
operation willnot be set. In such case, checking only with a RDY bit is not enough and the program may
go into an infinite loop.
• Do not make transitions into sub-run mode nor low-power-consumption mode when FR-CPU
programming mode (FLCR register WE=1).
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CHAPTER 20
Wild Register
This chapter describes functions and operations of the
wild register.
20.1 Wild Register Function
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CHAPTER 20 Wild Register
20.1 Wild Register Function
20.1
MB91345 Series
Wild Register Function
Wild register function replaces the data of the patch target address set in the address register
to the data set in the patch data registers.
This control consists of 1 register for controlling and 16 registers for setting, a total of 17
registers.
■ Function of Wild Register
Figure 20.1-1 shows a block diagram.
Figure 20.1-1 Block Diagram
I-bus address
I-bus data
F-bus address F-bus data
Wild Register
Registers
Access control
Flash memory
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CHAPTER 20 Wild Register
20.1 Wild Register Function
MB91345 Series
20.1.1
Description of Registers for Wild Register Function
This section explains the registers of the Wild register function.
Figure 20.1-2 shows a list of the Wild register function registers.
Figure 20.1-2 Map of Wild register Function Registers
Bit 31
Address
0000_7020H
0000_7030H
0000_7034H
0000_7038H
0000_703CH
0000_7040H
0000_7044H
0000_7048H
0000_704CH
0000_7050H
0000_7054H
0000_7058H
0000_705CH
0000_7060H
0000_7064H
0000_7068H
0000_706CH
CM71-10132-3E
24 23
+0
16 15
+1
87
+2
0
+3

WREN
WA0
WD0
WA1
WD1
WA2
WD2
WA3
WD3
WA4
WD4
WA5
WD5
WA6
WD6
WA7
WD7
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CHAPTER 20 Wild Register
20.1 Wild Register Function
MB91345 Series
■ Wild Register Control Register (WAx)
bit31 to bit21
bit20 to bit2
bit1, bit0

A20 to A2


R/W

Initial Value: -----------XXXXXXXXXXXXXXXXXXX--B
[bit31 to bit21] Reserved
No bit exists. Undefined value is read.
[bit20 to bit2] A20 to A2
Bits for specifying Wild register addresses.
These bits set Wild register target addresses.
Note: Do not set the address outside of ROM area for this register.
[bit1, bit0] Reserved
No register exists. Undefined value is read.
■ Wild Register Data Register (WDx)
bit31
bit0
D31 to D0
R/W
Initial Value: XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXB
[bit31 to bit0] D31 to D0
Bits for setting the data for replacing corresponding to WAx registers.
■ Wild Register Enable Register (WREN)
bit7
Address:
WREN7
0000-7020H
R/W
bit6
bit5
bit4
bit3
bit2
bit1
WREN6
WREN5
WREN4
WREN3
WREN2
WREN1
R/W
R/W
R/W
R/W
R/W
R/W
bit0
Initial Value
WREN0 00000000B
R/W
[bit7 to bit0] WRENx
Enable bits for ch.0 to ch.7 of the Wild register function.
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CHAPTER 20 Wild Register
20.1 Wild Register Function
MB91345 Series
■ Operation of Wild Register Function
Wild register replaces data to data set in WDx. Replacement data/register for each channel is shown in the
following table.
Replace Data/Register
Channel
ch.x
(x=0 to 7)
Address+0
Address+1
Address+2
Address+3
WDx (D31 to D24)
WDx (D23 to D16)
WDx (D15 to D08)
WDx (D07 to D00)
■ Restrictions and Notes of Wild Register Function
• Wild register function prioritizes the specification of register with lower number. (Example: ch.0 >
ch.1)
• Wild register is operable only in the memory area of the internal ROM area. If other area is specified,
malfunctions may occur. Do not specify area other than the memory area of the internal ROM area.
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20.1 Wild Register Function
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CHAPTER 21
Arithmetic Macro for the
Minimum, Maximum and
Absolute Values
This chapter describes the overview, the configuration
and functions of registers, and the operation of the
arithmetic macro for MIN/MAX/ABS.
21.1 Overview of Arithmetic Macro for MIN/MAX/ABS
21.2 Register Configuration of Arithmetic Macro for MIN/MAX/ABS
21.3 Operation Description of Arithmetic Macro for MIN/MAX/ABS
21.4 Caution of Arithmetic Macro for MIN/MAX/ABS
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CHAPTER 21 Arithmetic Macro for the Minimum, Maximum and Absolute Values
21.1 Overview of Arithmetic Macro for MIN/MAX/ABS
21.1
MB91345 Series
Overview of Arithmetic Macro for MIN/MAX/ABS
The arithmetic macro for MIN/MAX/ABS is composed of the maximum/minimum values'
detector circuit and the absolute values' arithmetic circuit.
For DATA A and DATA B, it performs an arithmetical operation of the minimum,
maximum, and absolute values to accumulate the result.
■ Register List
Address
644
bit31
···
bit0
Register name
0003A0H
DATA_A
Arithmetic data register A
0003A4H
DATA_B
Arithmetic data register B
0003A8H
MIN
Minimum value results register
0003ACH
MAX
Maximum value results register
0003B0H
ABS
Absolute value arithmetic results register
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21.2
CHAPTER 21 Arithmetic Macro for the Minimum, Maximum and Absolute Values
21.2 Register Configuration of Arithmetic Macro for MIN/MAX/ABS
Register Configuration of Arithmetic Macro for MIN/MAX/
ABS
This section explains the register configuration of the arithmetic macro for MIN/MAX/
ABS.
■ Minimum Value Results Register (MIN)
MIN
Address: 0003A8H
bit31
bit0
Initial value
00000000H
bit0
Initial value
00000000H
R/W
R/W: Readable/writable
[bit31 to bit0]: MIN
This is a register used to accumulate the minimum values (MIN(A,B)).
Initial value is "00000000H".
All bits are readable and writable.
Word data (32 bits) access is only enabled.
Do not access this register using read-modify-write (RMW) instruction.
■ Maximum Value Results Register (MAX)
MAX
Address: 0003ACH
bit31
R/W
R/W: Readable/writable
[bit31 to bit0]: MAX
This is a register used to accumulate the maximum values (MAX(A,B)).
Initial value is "00000000H".
All bits are readable and writable.
Word data (32 bits) access is only enabled.
Do not access this register using read-modify-write (RMW) instruction.
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CHAPTER 21 Arithmetic Macro for the Minimum, Maximum and Absolute Values
21.2 Register Configuration of Arithmetic Macro for MIN/MAX/ABS
MB91345 Series
■ Absolute Value Arithmetic Results Register (ABS)
ABS
Address: 0003B0H
bit31
bit0
Initial value
00000000H
R/W
R/W: Readable/writable
[bit31 to bit0]: ABS
This is a register used to accumulate the absolute difference (ABS(A-B)).
Initial value is "00000000H".
All bits are readable and writable.
Word data (32 bits) access is only enabled.
Do not access this register using read-modify-write (RMW) instruction.
Notes:
• Results of ABS(A-B) may overflow with some values in DATA_A and DATA_B.
If overflows occur, arithmetic results will be incorrect values.
• To perform absolute values’ arithmetic operation, 2 clocks are required. To read the arithmetic
results, begin to read the results by leaving more than one clock spaces to the rear of the writing
in the DATA_B register.
■ Arithmetic Data Register A (DATA_A)
A
bit31
bit16 bit15
Address: 0003A0H
bit0
Initial value
XXXXXXXXH
W
W: Write only
[bit31 to bit0]: A
This is a register used to write arithmetic data A.
Initial value is indeterminate.
It is used for signed 32-bit integers.
These bits are only writable.
Word data (32 bits) access is enabled. Also, half-word data (16 bits) access is enabled for bit15 to bit0.
In the case of a writing using a half-word, all high 16 bits will be "0".
Do not access this register using read-modify-write (RMW) instruction.
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CHAPTER 21 Arithmetic Macro for the Minimum, Maximum and Absolute Values
21.2 Register Configuration of Arithmetic Macro for MIN/MAX/ABS
■ Arithmetic Data Register B (DATA_B)
B
bit31
bit16 bit15
Address: 0003A4H
bit0
Initial value
XXXXXXXXH
W
W: Write only
[bit31 to bit0]: B
This is a register used to write arithmetic data B.
Initial value is indeterminate.
It is used for signed 32-bit integers.
These bits are only writable.
Word data (32 bits) access is enabled. Also, half-word data (16 bits) access is enabled for bit15 to bit0.
In the case of a writing using a half-word, all high 16 bits will be "0".
Do not access this register using read-modify-write (RMW) instruction.
If the value is written into this register, arithmetic operation is performed for the minimum, maximum
and absolute values and then arithmetic results are stored into the register respectively.
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CHAPTER 21 Arithmetic Macro for the Minimum, Maximum and Absolute Values
21.3 Operation Description of Arithmetic Macro for MIN/MAX/ABS
21.3
MB91345 Series
Operation Description of Arithmetic Macro for MIN/MAX/
ABS
This section describes the operation of the arithmetic macro for MIN/MAX/ABS.
■ Registers of the Minimum, Maximum and Absolute Value Arithmetic Results
These registers perform arithmetic operations of MIN(A,B), MAX(A,B) and ABS(A-B) for signed 32-bit
integers written in arithmetic data registers A and B and then accumulates the results in registers
respectively.
When the data is written into arithmetic data registers B, arithmetic operation is performed for the
minimum, maximum and absolute values and then arithmetic results are stored into the register
respectively.
Example
The following shows sample operation.
Where
A(i) = {1,2,3,4,5}
B(i) = {3,2,1,0,1}
0000_03A8H = 0000_0000H // MIN is initialized
0000_03ACH = 0000_0000H // MAX is initialized
0000_03B0H = 0000_0000H // ABS is initialized
0000_03A0H = 0000_0001H // A(1) is set
0000_03A4H = 0000_0003H // B(1) is set  MIN(A,B)=1,MAX(A,B)=3,ABS(A-B)=2
0000_03A0H = 0000_0002H // A(2) is set
0000_03A4H = 0000_0002H // B(2) is set  MIN(A,B)=2,MAX(A,B)=2,ABS(A-B)=0
0000_03A0H = 0000_0003H // A(3) is set
0000_03A4H = 0000_0001H // B(3) is set  MIN(A,B)=1,MAX(A,B)=3,ABS(A-B)=2
0000_03A0H = 0000_0004H // A(4) is set
0000_03A4H = 0000_0000H // B(4) is set  MIN(A,B)=0,MAX(A,B)=4,ABS(A-B)=4
0000_03A0H = 0000_0005H // A(5) is set
0000_03A4H = 0000_0001H // B(5) is set  MIN(A,B)=1,MAX(A,B)=5,ABS(A-B)=4
0000_03A8H : 1+2+1+0+1 = 5
0000_03ACH : 3+2+3+4+5 = 17
0000_03B0H : 2+0+2+4+4 = 12
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CHAPTER 21 Arithmetic Macro for the Minimum, Maximum and Absolute Values
21.3 Operation Description of Arithmetic Macro for MIN/MAX/ABS
■ Direct Transfer Command
Since this macro’s register is assigned to direct addressing areas, you can use the following direct transfer
commands besides general commands if you write it using an assembler.
(A) DMOV @dir10, R13
DMOV R13, @dir10
(B) DMOV @dir10, @R13+
DMOV @R13+, @dir10
(C) DMOV @dir10, @-R15
DMOV @R15+, @dir10
Even if you write it in C language, the command (A) above is generated.
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CHAPTER 21 Arithmetic Macro for the Minimum, Maximum and Absolute Values
21.4 Caution of Arithmetic Macro for MIN/MAX/ABS
21.4
MB91345 Series
Caution of Arithmetic Macro for MIN/MAX/ABS
This section explains caution of the arithmetic macro for MIN/MAX/ABS.
■ Caution of Arithmetic Macro for MIN/MAX/ABS
• Cumulative sum of the minimum, maximum and absolute values may overflow.
If overflows occur, arithmetic results will be incorrect values.
• Results of ABS(A-B) may overflow with some values of DATA_A and DATA_B.
If overflows occur, arithmetic results will be incorrect values.
• To perform absolute values’ arithmetical operation, 2 clocks are required. To read the arithmetic results,
begin to read the results by leaving more than one clock spaces to the rear of the writing in the
DATA_B register.
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CHAPTER 22
Serial Writing Connection
This chapter explains an example of a serial writing
connection using the flash microcontroller programmer
(manufactured by Yokogawa Digital Computer
Corporation).
22.1 Basic Configuration of the Serial Writing
22.2 Pins Used for Fujitsu-Standard Serial Onboard Writing
22.3 Sample Connection of Serial Writing
22.4 System Configuration of Flash Microcontroller Programmer
22.5 Caution of Serial Writing
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CHAPTER 22 Serial Writing Connection
22.1 Basic Configuration of the Serial Writing
22.1
MB91345 Series
Basic Configuration of the Serial Writing
The MB91345 series supports serial onboard writing of Flash ROM (Fujitsu standard).
This section explains its specification.
■ Basic Configuration of the Serial Writing
Fujitsu-standard serial onboard writing uses AF420/AF320/AF220/AF210/AF120/AF110 flash microcontroller
programmers manufactured by Yokogawa Digital Computer Corporation. The following figure shows the basic
configuration of the serial writing connection.
Figure 22.1-1 Basic Configuration of the Serial Writing Connection
Host interface cable
RS232C
AF420/AF320/
AF220/AF210/
AF120/AF110
Flash
microcontroller
programmer
+
Memory card
General-purpose common cable (AZ210)
CLK synchronous serial
MB91345 series
user system
The unit is enabled to operate on a stand-alone basis.
Note:
For information of features of and how to use flash microcontroller programmers, and generalpurpose common cables (AZ210) and connectors used for connection, please contact Yokogawa
Digital Computer Corporation.
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CHAPTER 22 Serial Writing Connection
22.2 Pins Used for Fujitsu-Standard Serial Onboard Writing
MB91345 Series
22.2
Pins Used for Fujitsu-Standard Serial Onboard Writing
This section explains the pins used for Fujitsu-standard serial onboard writing.
■ Pins Used for Fujitsu-Standard Serial Onboard Writing
Table 22.2-1 shows the function of the pins used for Fujitsu-standard serial onboard writing.
Table 22.2-1 Pins used for Fujitsu-Standard Serial Onboard Writing
Pin
Functions
Remarks
MD2, MD1, MD0 Mode pins
These pins are used to set to the writing mode.
Flash serial writing modes: MD2, MD1, MD0=H, L, L
Reference: Single chip modes: MD2, MD1, MD0=L, L, L
P54/RT4
P55/RT5
P53/PPG7
Pins used to activate the
writing program
During the flash serial rewriting, these pins are set to P54=L, P55=H
(clock synchronous mode).
INIT, TRST
Reset pins
P20/SIN0
Pins used to input serial data
[Reference: If P54 is "L" and P55 is "L", it will be in the asynchronous
UART mode.]
P53=H: External clock 12.5 MHz
P53=L: External clock 12 MHz

P21/SOT0/SDA0
These pins use UART ch.0 resources as the interface of serial onboard
Pins used to output serial data writing communication.
P22/SCK0/SCL0
Pins used to input serial clock
VCC
Power voltage supply
Please supply the writing voltage from the user system.
VSS
GND pin
Follow the GND of the flash microcontroller programmer.
Figure 22.2-1 Control Circuit
AF420/AF320/
AF220/AF210/
AF120/AF110
Writing control pin
AF420/AF320/
AF220/AF210/
AF120/AF110
/TICS pin
MB91345 series
Writing control pin
10 kΩ
User circuit
Notes:
• If you use P53, P54, P55, SIN0, SOT0, SCK0 pins for user system, the control circuit in Figure
22.2-1 will be required. (/TICS signal of the flash microcontroller programmer enables user circuits
to be disconnected during the serial writing.)
• Please connect the flash microcontroller programmer when the user's power supply is off.
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CHAPTER 22 Serial Writing Connection
22.3 Sample Connection of Serial Writing
22.3
MB91345 Series
Sample Connection of Serial Writing
This section explains sample connection of the serial writing.
■ Sample Connection of Serial Writing
Figure 22.3-1 shows a sample connection of serial writing.
Figure 22.3-1 Sample Connection of the Serial Writing
Flash microcontroller user system
programmer
MB91345 Series
Connector DX10-28S
TAUX3
(19)
At the serial
rewriting 1
MD2
≥ 4.7 kΩ
MD1
MD0
User circuit
P54
At the serial
rewriting 0
≥ 4.7 kΩ
At the serial
rewriting 1
≥ 4.7 kΩ
P55
User circuit
TRST
≥ 4.7 kΩ
/TRES
(5)
TTXD
(13)
(27)
SIN0
SOT0
(6)
SCK0
(2)
VCC
TRXD
TCK
TVcc
GND
(7,8,
14,15,
21,22
1,28)
INIT
User's power supply (3.3V)
VSS
14 pin
1 pin
Pins of 3, 4, 9, 10, 11, DX10-28S
12, 16, 17, 18, 20, 23,
24, 25 and 26 are open.
28 pin
15 pin
Pin assignment of the connector
DX10-28S: right angle type
(manufactured by Hirose Electric Co., Ltd.)
654
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
CHAPTER 22 Serial Writing Connection
22.4 System Configuration of Flash Microcontroller Programmer
MB91345 Series
22.4
System Configuration of Flash Microcontroller
Programmer
This section shows the system configuration of the flash microcontroller programmer
(manufactured by Yokogawa Digital Computer Corporation).
■ System Configuration of Flash Microcontroller Programmer (Manufactured by
Yokogawa Digital Computer Corporation)
Table 22.4-1 System Configuration of Flash Microcontroller Programmer (Manufactured by
Yokogawa Digital Computer Corporation)
Model name
Functions
AF220
/AC4P
Ethernet interface model
/100V to 220V power adaptor
AF210
/AC4P
Standard model
/100V to 220V power adaptor
AF120
/AC4P
Single-key Ethernet interface model
/100V to 220V power adaptor
AF110
/AC4P
Single key model
/100V to 220V power adaptor
Main unit
Contact: Yokogawa Digital Computer Corporation
Telephone number: +81-42-333-6224
CM71-10132-3E
FUJITSU SEMICONDUCTOR LIMITED
655
CHAPTER 22 Serial Writing Connection
22.5 Caution of Serial Writing
22.5
MB91345 Series
Caution of Serial Writing
This section shows caution of the serial writing connection.
■ Oscillation Clock Frequency
Oscillation clock frequency enabled for the flash memory writing is 12 MHz or 12.5 MHz.
■ Port Status during Flash Memory Writing
The port status during the flash memory writing using the serial writer is equal to the reset status except
pins used for the writing.
656
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
APPENDIX
This section contains detailed information which is not
included in the main text but required for programming,
such as the I/O map, interrupt vectors, pin status in the
CPU state, and notes and instruction lists that may be
needed when using the little endian field.
APPENDIX A I/O Map
APPENDIX B Vector Table
APPENDIX C Pin Status List
CM71-10132-3E
FUJITSU SEMICONDUCTOR LIMITED
657
APPENDIX
APPENDIX A I/O Map
MB91345 Series
APPENDIX A I/O Map
This map shows the mapping status of each register for the memory space field and
peripheral resources.
■ How to Read the I/O Map
Figure A-1shows the correspondence between the memory space area and the peripheral resource registers.
Figure A-1 Reading the table
address
000000H
register
+1
+2
PDR1[R/W]
PDR2[R/W]
XXXXXXXX
XXXXXXXX
+0
PDR0[R/W]
XXXXXXXX
+3
PDR3[R/W]
XXXXXXXX
block
T-unit
Port Data Register
Read/write attribute
Initial value of register after reset
Register name (column 1 of the register is at address 4n,
column 2 is at address 4n + 1...)
Leftmost register address (For word-length access,
column 1 of the register becomes the MSB of the data.)
Notes:
The initial value of bits in a register are indicated as follows:
• "1" : Initial value "1"
• "0" : Initial value "0"
• "X" : Initial value "X"
• "-" : A physical register does not exist at the location.
658
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
APPENDIX
APPENDIX A I/O Map
MB91345 Series
Attached Table A-1 I/O Map (1 / 13)
Address
000000H
000004H
000008H
00000CH
000010H
000014H
000018H
00001CH
Register
+0
+1
+2
PDR0 [R/W] B,H PDR1 [R/W] B,H PDR2 [R/W] B,H
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDR4 [R/W] B,H PDR5 [R/W] B,H PDR6 [R/W] B,H
XXXXXXXX
XXXXXXXX
----XXXX
---PDRC [R/W] B,H PDRD [R/W] B,H PDRE [R/W] B,H
-----XXX
XXXXXXXX
XXXXXXXX
-------------
000020H
000024H
000028H
00002CH
--
--
ADCS01 [R/W] ADCS00 [R,R/W]
00000000
00000000
ADCT0 [R/W]
00010000 00101100
ADCR0M [R]
------XX XXXXXXXX
000030H
--
--
000048H
ADCS11 [R/W] ADCS10 [R,R/W]
00000000
00000000
ADCT1 [R/W]
00010000 00101100
--EIRR0 [R/W]
ENIR0 [R/W]
00000000
00000000
DICR [R/W]
HRCL [R,R/W]
00000000
0--11111
TMRLR0 [W]
XXXXXXXX XXXXXXXX
00004CH
--
000050H
TMRLR1 [W]
XXXXXXXX XXXXXXXX
000054H
--
000058H
TMRLR2 [W]
XXXXXXXX XXXXXXXX
000034H
000038H
00003CH
000040H
000044H
00005CH
000060H
000064H
000068H
00006CH
--
--
SCR0 [R,R/W]
SMR0 [W,R/W]
0--00000
00000000
RDR0/TDR0 [R/W]
00000000
ISMK0 [R/W]
IBSA [R/W]
01111110
00000000
FBYTE02 [R/W] FBYTE01 [R/W]
00000000
00000000
CM71-10132-3E
+3
PDR3 [R/W] B,H
XXXXXXXX
--
--
-
TMR0 [R]
XXXXXXXX XXXXXXXX
TMCSR0 [R,RW]
00000000 00000000
TMR1 [R]
XXXXXXXX XXXXXXXX
TMCSR1 [R,RW]
00000000 00000000
TMR2 [R]
XXXXXXXX XXXXXXXX
TMCSR2 [R,RW]
00000000 00000000
SSR0 [R,R/W]
ESCR0 [R/W]
0-000011
--000000
BGR01 [R/W]
BGR00 [R/W]
00000000
00000000
FCR01 [R/W]
FCR00 [R/W]
00000000
00000000
--
Port Data Registers
--
----ADERH0 [R/W]
-11111111
ADCR0 [R]
------XX XXXXXXXX
ADSCH0 [R/W] ADECH0 [R/W]
0----000
-----000
ADCR1M [R]
------XX XXXXXXXX
ADERH1 [R/W]
-11111111
ADCR1 [R]
------XX XXXXXXXX
ADSCH1 [R/W] ADECH1 [R/W]
0----000
-----000
--ELVR0 [R/W]
00000000 00000000
-
Block
Reserved
Reserved
Reserved
Reserved
A/D converter 0
A/D mirror data register
A/D converter 1
Reserved
External interrupt 0 to
external interrupt 7
Delayed interrupt module
ReLoad Timer 0
ReLoad Timer 1
ReLoad Timer 2
FIFO 0
Multi function interface 0
--
FUJITSU SEMICONDUCTOR LIMITED
659
APPENDIX
APPENDIX A I/O Map
MB91345 Series
Attached Table A-1 I/O Map (2 / 13)
Address
000070H
000074H
000078H
00007CH
000080H
000084H
000088H
00008CH
000090H
000094H
000098H
00009CH
0000A0H
0000A4H
0000A8H
0000ACH
0000B0H
0000B4H
0000B8H
0000BCH
0000C0H
0000C4H
0000C8H
0000CCH
0000D0H
0000D4H
0000D8H
660
Register
+0
+1
SCR1 [R,R/W]
SMR1 [W,R/W]
0--00000
00000000
RDR1/TDR1 [R/W]
00000000
ISMK1 [R/W]
IBSA1 [R/W]
01111110
00000000
FBYTE12 [R/W] FBYTE11 [R/W]
00000000
00000000
SCR2 [R,R/W]
SMR2 [W,R/W]
0--00000
00000000
RDR2/TRD2 [R/W]
00000000
ISMK2 [R/W]
IBSA2 [R/W]
01111110
00000000
--SCR3 [R,R/W]
SMR3 [W,R/W]
0--00000
00000000
RDR3/TRD3 [R/W]
00000000
ISMK3 [R/W]
IBSA3 [R/W]
01111110
00000000
--SCR4 [R,R/W]
SMR4 [W,R/W]
0--00000
00000000
RDR4/TRD4 [R/W]
00000000
ISMK4 [R/W]
IBSA4 [R/W]
01111110
00000000
--SCR5 [R,R/W]
SMR5 [W,R/W]
0--00000
00000000
RDR5/TRD5 [R/W]
00000000
ISMK5 [R/W]
IBSA5 [R/W]
01111110
00000000
--EIRR1 [R/W]
ENIR1 [R/W]
00000000
00000000
EIRR2 [R/W]
ENIR2 [R/W]
00000000
00000000
----CPCLRB/CPCLR [R/W] H
11111111 11111111
TCCSH [R/W] B TCCSL [R/W] B
00000000
01000000
---
+2
SSR1 [R,R/W]
0-000011
BGR11 [R/W]
00000000
FCR11 [R/W]
00000000
+3
ESCR1 [R/W]
--000000
BGR10 [R/W]
00000000
FCR10 [R/W]
00000000
--
--
SSR2 [R,R/W]
0-000011
BGR21 [R/W]
00000000
ESCR2 [R/W]
--000000
BGR20 [R/W]
00000000
--
--
-SSR3 [R,R/W]
0-000011
BGR31 [R/W]
00000000
-ESCR3 [R/W]
--000000
BGR30 [R/W]
00000000
--
--
-SSR4 [R,R/W]
0-000011
BGR41 [R/W]
00000000
-ESCR4 [R/W]
--000000
BGR40 [R/W]
00000000
--
--
-SSR5 [R,R/W]
0-000011
BGR51 [R/W]
00000000
-ESCR5 [R/W]
--000000
BGR50 [R/W]
00000000
--
--
-ELVR1 [R/W]
00000000 00000000
ELVR2 [R/W]
00000000 00000000
----TCDTH/TCDTL [R/W] H
00000000 00000000
Block
FIFO 1
Multi function interface 1
Multi function interface 2
Multi function interface 3
Multi function interface 4
Multi function interface 5
--
--
--
--
--
FUJITSU SEMICONDUCTOR LIMITED
External interrupt 8 to
external interrupt 15
External interrupt 16 to
external interrupt 23
Reserved
Reserved
32bit Free Run Timer 0
Reserved
CM71-10132-3E
APPENDIX
APPENDIX A I/O Map
MB91345 Series
Attached Table A-1 I/O Map (3 / 13)
Register
Address
0000ECH
+0
+1
IPCPH0/IPCPL0 [R]
XXXXXXXX XXXXXXXX
IPCPH2/IPCPL2 [R]
XXXXXXXX XXXXXXXX
ICSH01 [R/W]
ICSL01 [R/W]
------00
00000000
OCCPH0/OCCPL0 [R/W]
XXXXXXXX XXXXXXXX
OCCPH2/OCCPL2 [R/W]
XXXXXXXX XXXXXXXX
+2
+3
IPCPH1/IPCPL1 [R]
XXXXXXXX XXXXXXXX
IPCPH3/IPCPL3 [R]
XXXXXXXX XXXXXXXX
ICSH23 [R/W]
ICSL23 [R/W]
------00
00000000
OCCPH1/OCCPL1 [R/W]
XXXXXXXX XXXXXXXX
OCCPH3/OCCPL3 [R/W]
XXXXXXXX XXXXXXXX
0000F0H
OCS01 [R/W]
11101100 00001100
OCS23 [R/W]
11101100 00001100
0000DCH
0000E0H
0000E4H
0000E8H
0000F4H
0000F8H
0000FCH
OCMOD [R/W] B
-00000000
PWCSR0 [R/W,R] B,H,W
0000000X 00000000
PDIVR0 [R/W]
-B,H,W
XXXXX000
CM71-10132-3E
--
--
Block
16bit input capture
Output compare 1/
Output compare 0
Output compare 3/
Output compare 2
Output compare 3 to
Output compare 0
Ctrl.
OCU Mode Select
PWCR0 [R] H,W
00000000 00000000
PWC
--
--
FUJITSU SEMICONDUCTOR LIMITED
661
APPENDIX
APPENDIX A I/O Map
MB91345 Series
Attached Table A-1 I/O Map (4 / 13)
Address
000100H
000104H
000108H
00010CH
000110H
000114H
000118H
00011CH
000120H
000124H
000128H
00012CH
000130H
000134H
000138H
00013CH
000140H
000144H
000148H
00014CH
000150H
000154H
662
Register
Block
+0
+1
+2
+3
PRLH0 [R/W]
PRLL0 [R/W]
PRLH1 [R/W]
PRLL1 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PRLH2 [R/W]
PRLL2 [R/W]
PRLH3 [R/W]
PRLL3 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PPGC0 [R/W]
PPGC1 [R/W]
PPGC2 [R/W]
PPGC3 [R/W]
B,H,W 0000000X B,H,W 0000000X B,H,W 0000000X B,H,W 0000000X
PRLH4 [R/W]
PRLL4 [R/W]
PRLH5 [R/W]
PRLL5 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PRLH6 [R/W]
PRLL6 [R/W]
PRLH7 [R/W]
PRLL7 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PPGC4 [R/W]
PPGC5 [R/W]
PPGC6 [R/W]
PPGC7 [R/W]
B,H,W 0000000X B,H,W 0000000X B,H,W 0000000X B,H,W 0000000X
PRLH8 [R/W]
PRLL8 [R/W]
PRLH9 [R/W]
PRLL9 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
PPG0 to PPGF
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PRLHA [R/W]
PRLLA [R/W]
PRLHB [R/W]
PRLLB [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PPGC8 [R/W]
PPGC9 [R/W]
PPGCA [R/W]
PPGCB [R/W]
B,H,W 0000000X B,H,W 0000000X B,H,W 0000000X B,H,W 0000000X
PRLHC [R/W]
PRLLC [R/W]
PRLHD [R/W]
PRLLD [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PRLHE [R/W]
PRLLE [R/W]
PRLHF [R/W]
PRLLF [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PPGCC [R/W]
PPGCD [R/W]
PPGCE [R/W]
PPGCF [R/W]
B,H,W 0000000X B,H,W 0000000X B,H,W 0000000X B,H,W 0000000X
PPGTRG [R/W] B,H,W
PPGGATEC [R/W]
-00000000 00000000
B XXXXXX00
PPGREVC [R/W] B,H,W
--00000000 00000000
----Reserved
----Reserved
----Reserved
----Reserved
----Reserved
----Reserved
CPCLRB/CPCLR [R/W] W
11111111 11111111
32bit Free Run Timer 0
TCDT [R/W] W
00000000 00000000 00000000 00000000
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
APPENDIX
APPENDIX A I/O Map
MB91345 Series
Attached Table A-1 I/O Map (5 / 13)
Address
000158H
00015CH
000160H
000164H
000168H
00016CH
000170H
000174H
000178H
00017CH
000180H
000184H
000188H
00018CH
000190H
000194H
000198H
00019CH
0001A0H
0001A4H
0001A8H
0001ACH
0001B0H
0001B4H
0001B8H
0001BCH
Register
Block
+1
+2
+3
TCCSL [R/W] B
--01000000
IPCP4 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP5 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
32bit Input Capture Unit
IPCP6 [R] W
4, Unit 5, Unit 6, Unit 7
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP7 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
ICS45 [R/W]
ICS67 [R/W]
--00000000
00000000
OCCP4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCCP5 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
32bit
OCCP6 [R/W] W
output compare 7 to
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
output compare 4
OCCP7 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCS45 [R/W]
OCS67 [R/W]
11101100 00001100
11101100 00001100
RCRH1 [W] B,H RCRL0 [W] B,H UDCR1 [R] B,H UDCR0 [R] B,H
00000000
00000000
00000000
00000000
CCRH0 [R/W] B,H CCRL0 [R/W] B,H
Up/Down Counter 0/
CSR0 [R/W] B
-00000000
00000000
Up/Down Counter 1
00000000
CCRH1 [R/W] B,H CCRL1 [R/W] B,H
CSR1 [R/W] B
-00000000
00000000
00000000
----Reserved
RCRH3 [W] B,H RCRL2 [W] B,H UDCR3 [R] B,H UDCR2 [R] B,H
00000000
00000000
00000000
00000000
CCRH2 [R/W] B,H CCRL2 [R/W] B,H
Up/Down Counter 2/
CSR2 [R/W] B
-00000000
00000000
Up/Down Counter 3
00000000
CCRH3 [R/W] B,H CCRL3 [R/W] B,H
CSR3 [R/W] B
-00000000
00000000
00000000
----Reserved
----Reserved
----Reserved
----Reserved
SCR6 [R,R/W]
SMR6 [W,R/W]
SSR6 [R,R/W]
ESCR6 [R/W]
0--00000
00000000
0-000011
--000000
RDR6/TRD6 [R/W]
BGR61 [R/W]
BGR60 [R/W]
00000000
00000000
00000000
Multi function interface 6
ISMK6 [R/W]
IBSA6 [R/W]
--01111110
00000000
----+0
TCCSH [R/W] B
00000000
CM71-10132-3E
FUJITSU SEMICONDUCTOR LIMITED
663
APPENDIX
APPENDIX A I/O Map
MB91345 Series
Attached Table A-1 I/O Map (6 / 13)
Address
0001C0H
0001C4H
0001C8H
0001CCH
0001D0H
0001D4H
0001D8H
0001DCH
0001E0H
0001E4H
0001E8H
0001ECH
0001F0H
0001F4H
0001F8H
0001FCH
000200H
000204H
000208H
00020CH
000210H
000214H
000218H
00021CH
000220H
000224H
664
Register
+0
+1
+2
SCR7 [R,R/W]
SMR7 [W,R/W]
SSR7 [R,R/W]
0--00000
00000000
0-000011
RDR7/TRD7 [R/W]
BGR71 [R/W]
00000000
00000000
ISMK7 [R/W]
IBSA7 [R/W]
-01111110
00000000
---SCR8 [R,R/W]
SMR8 [W,R/W]
SSR8 [R,R/W]
0--00000
00000000
0-000011
RDR8/TRD8 [R/W]
BGR81 [R/W]
00000000
00000000
ISMK8 [R/W]
IBSA8 [R/W]
-01111110
00000000
---SCR9 [R,R/W]
SMR9 [W,R/W]
SSR9 [R,R/W]
0--00000
00000000
0-000011
RDR9/TRD9 [R/W]
BGR91 [R/W]
00000000
00000000
ISMK9 [R/W]
IBSA9 [R/W]
-01111110
00000000
---SCRA [R,R/W]
SMRA [W,R/W]
SSRA [R,R/W]
0--00000
00000000
0-000011
RDRA/TRDA [R/W]
BGRA1 [R/W]
00000000
00000000
ISMKA [R/W]
IBSAA [R/W]
-01111110
00000000
---DMACA0 [R/W]
00000000 00000000 00000000 00000000
DMACB0 [R/W]
00000000 00000000 00000000 00000000
DMACA1 [R/W]
00000000 00000000 00000000 00000000
DMACB1 [R/W]
00000000 00000000 00000000 00000000
DMACA2 [R/W]
00000000 00000000 00000000 00000000
DMACB2 [R/W]
00000000 00000000 00000000 00000000
DMACA3 [R/W]
00000000 00000000 00000000 00000000
DMACB3 [R/W]
00000000 00000000 00000000 00000000
DMACA4 [R/W]
00000000 00000000 00000000 00000000
DMACB4 [R/W]
00000000 00000000 00000000 00000000
+3
ESCR7 [R/W]
--000000
BGR70 [R/W]
00000000
Block
Multi function interface 7
--ESCR8 [R/W]
--000000
BGR80 [R/W]
00000000
Multi function interface 8
--ESCR9 [R/W]
--000000
BGR90 [R/W]
00000000
Multi function interface 9
--ESCRA [R/W]
--000000
BGRA0 [R/W]
00000000
FUJITSU SEMICONDUCTOR LIMITED
Multi function interface
10
---
DMAC
CM71-10132-3E
APPENDIX
APPENDIX A I/O Map
MB91345 Series
Attached Table A-1 I/O Map (7 / 13)
Register
Address
000228H
to
00023CH
+0
+1
+2
+3
--
--
--
--
DMACR [R/W]
0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX
000240H
000244H
to
00027CH
000280H
to
00038CH
000390H
to
0003BCH
--
--
Reserved
--
--
--
--
Reserved
--
--
--
--
Reserved
DATA_A [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DATA_B [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MIN [R/W]
00000000 00000000 00000000 00000000
MAX [R/W]
00000000 00000000 00000000 00000000
ABS [R/W]
00000000 00000000 00000000 00000000
0003A8H
0003ACH
0003B0H
0003F4H
0003F8H
0003FCH
000400H
000404H
000408H
00040CH
000410H
000414H
to
00041CH
DMAC
--
0003A4H
0003F0H
Reserved
--
0003A0H
0003B4H
to
0003ECH
Block
--
--
--
MIN/MAX/ABS
--
Reserved
BSD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Bit Search Module
BSDC [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDR0 [R/W] B,H DDR1 [R/W] B,H DDR2 [R/W] B,H DDR3 [R/W] B,H
00000000
00000000
00000000
00000000
DDR4 [R/W] B,H DDR5 [R/W] B,H DDR6 [R/W] B,H
-00000000
00000000
----0000
Data Direction Registers
----DDRC [R/W] B,H DDRD [R/W] B,H DDRE [R/W] B,H
------000
00000000
00000000
-----
CM71-10132-3E
--
--
--
--
FUJITSU SEMICONDUCTOR LIMITED
Reserved
665
APPENDIX
APPENDIX A I/O Map
MB91345 Series
Attached Table A-1 I/O Map (8 / 13)
Address
+0
PFR0 [R/W] B,H
00000000
PFR4 [R/W] B,H
00000000
-PFRC [R/W] B,H
-----000
----ICR00 [R,R/W]
---11111
ICR04 [R,R/W]
---11111
ICR08 [R,R/W]
---11111
ICR12 [R,R/W]
---11111
ICR16 [R,R/W]
---11111
ICR20 [R,R/W]
---11111
ICR24 [R,R/W]
---11111
ICR28 [R,R/W]
---11111
ICR32 [R,R/W]
---11111
ICR36 [R,R/W]
---11111
ICR40 [R,R/W]
---11111
ICR44 [R,R/W]
---11111
+1
PFR1 [R/W] B,H
00000000
PFR5 [R/W] B,H
00000000
-PFRD [R/W] B,H
00000000
----ICR01 [R,R/W]
---11111
ICR05 [R,R/W]
---11111
ICR09 [R,R/W]
---11111
ICR13 [R,R/W]
---11111
ICR17 [R,R/W]
---11111
ICR21 [R,R/W]
---11111
ICR25 [R,R/W]
---11111
ICR29 [R,R/W]
---11111
ICR33 [R,R/W]
---11111
ICR37 [R,R/W]
---11111
ICR41 [R,R/W]
---11111
ICR45 [R,R/W]
---11111
+2
PFR2 [R/W] B,H
00000000
PFR6 [R/W] B,H
----0000
-PFRE [R/W] B,H
00000000
----ICR02 [R,R/W]
---11111
ICR06 [R,R/W]
---11111
ICR10 [R,R/W]
---11111
ICR14 [R,R/W]
---11111
ICR18 [R,R/W]
---11111
ICR22 [R,R/W]
---11111
ICR26 [R,R/W]
---11111
ICR30 [R,R/W]
---11111
ICR34 [R,R/W]
---11111
ICR38 [R,R/W]
---11111
ICR42 [R,R/W]
---11111
ICR46 [R,R/W]
---11111
+3
PFR3 [R/W] B,H
00000000
--
--
--
--
000484H
RSRR [R,R/W]
10000000
CLKR [R/W]
00000000
STCR [R/W]
00110011
WPR [W]
XXXXXXXX
CTBR [W]
XXXXXXXX
DIVR1 [R/W]
00000000
000488H
--
--
00048CH
--
--
TBCR [R/W]
00XXXX00
DIVR0 [R/W]
00000011
OSCCR [R/W]
XXXXXXXX
--
000490H
OSCR [R/W]
00000000
OSCT [R/W]
XXXXXXXX
--
--
000420H
000424H
000428H
00042CH
000430H
000434H
000438H
00043CH
000440H
000444H
000448H
00044CH
000450H
000454H
000458H
00045CH
000460H
000464H
000468H
00046CH
000470H
to
00047CH
000480H
666
Register
Block
---
Port Function Registers
-----ICR03 [R,R/W]
---11111
ICR07 [R,R/W]
---11111
ICR11 [R,R/W]
---11111
ICR15 [R,R/W]
---11111
ICR19 [R,R/W]
---11111
ICR23 [R,R/W]
---11111
ICR27 [R,R/W]
---11111
ICR31 [R,R/W]
---11111
ICR35 [R,R/W]
---11111
ICR39 [R,R/W]
---11111
ICR43 [R,R/W]
---11111
ICR47 [R,R/W]
---11111
FUJITSU SEMICONDUCTOR LIMITED
Reserved
Interrupt Control
Register
Reserved
Clock Control Unit
---
Reserved
Main oscillation
Stabilization Waiting
Timer
CM71-10132-3E
APPENDIX
APPENDIX A I/O Map
MB91345 Series
Attached Table A-1 I/O Map (9 / 13)
Register
Address
+0
+1
+2
+3
000494H
to
0004FCH
--
--
--
--
000500H
PCR0 [R/W] B,H
00000000
000504H
000508H
00050CH
000510H
000514H
to
00051CH
000520H
000524H
000528H
00052CH
000530H
000534H
to
00053CH
000540H
000544H
000548H
00054CH
000550H
000554H
000558H
00055CH
000560H
000564H
to
00056CH
000570H
000574H
000578H
PCR1 [R/W] B,H
-00000000
PCR5 [R/W] B,H PCR6 [R/W] B,H
-00000000
----0000
---PCRC [R/W] B,H PCRD [R/W] B,H PCRE [R/W] B,H
-----000
00000000
00000000
-----
--
--
Block
Reserved
----
Port Pull-up Control
Registers
----
EPFR0 [R/W] B,H EPFR1 [R/W] B,H EPFR2 [R/W] B,H EPFR3 [R/W] B,H
00000000
00000000
11111111
11111111
EPFR4 [R/W] B,H EPFR5 [R/W] B,H EPFR6 [R/W] B,H
-11111111
11111111
----1000
----EPFRC [R/W] B,H EPFRD [R/W] B,H EPFRE [R/W] B,H
------000
00000000
00000000
-----
Reserved
Extra Port Function
Register
--
--
--
--
Reserved
-----TTCR0 [R/W]
B,H,W 11110000
COMP0 [R/W]
B,H,W 00000000
TTCR1 [R/W]
B,H,W 11110000
COMP8 [R/W]
B,H,W 00000000
------
------
Reserved
Reserved
Reserved
Reserved
Reserved
--
--
COMP2 [R/W]
B,H,W 00000000
COMP4 [R/W]
B,H,W 00000000
--
--
COMP10 [R/W]
B,H,W 00000000
COMP12 [R/W]
B,H,W 00000000
-----TSTPR0 [R]
B,H,W 00000000
COMP6 [R/W]
B,H,W 00000000
TSTPR1 [R]
B,H,W 00000000
COMP14 [R/W]
B,H,W 00000000
--
--
--
--
Reserved
--ADTGS [R/W] B
------00
---
---
---
Reserved
Reserved
--
--
--
A/D Trigger Select
--
--
--
--
Reserved
00057CH
to
00063CH
CM71-10132-3E
FUJITSU SEMICONDUCTOR LIMITED
Timing Generator
667
APPENDIX
APPENDIX A I/O Map
MB91345 Series
Attached Table A-1 I/O Map (10 / 13)
Address
000640H
000644H
000648H
00064CH
000650H
000654H
000658H
00065CH
000660H
000664H
000668H
00066CH
000670H
000674H
000678H
00067CH
000680H
000684H
000688H
to
0007F8H
0007FCH
000800H
to
000AFCH
668
Register
+0
+1
+2













+3













Block
Not Used















MODR [W]
XXXXXXXX
Not Used


FUJITSU SEMICONDUCTOR LIMITED


Not Used
CM71-10132-3E
APPENDIX
APPENDIX A I/O Map
MB91345 Series
Attached Table A-1 I/O Map (11 / 13)
Address
000B00H
000B04H
000B08H
000B0CH
000B10H
000B14H
to
000B1CH
000B20H
Register
+0
+1
+2
+3
ESTS0 [R/W] B
ESTS1 [R/W] B
ESTS2 [R] B

X0000000
XXXXXXXX
1XXXXXXX
ECTL0 [R/W] B
ECTL2 [W] B
ECTL3 [R/W] B
ECTL1 [R/W] B 0
0X000000
000X0000
00X00X11
ECNT0 [W] B
ECNT1 [W] B
EUSA [W] B
EDTC [W] B
XXXXXXXX
XXXXXXXX
XXX00000
0000XXXX
EWPT [R] H
ECTL4 [R]([R/W]) ECTL5 [R]([R/W])
00000000 00000000
B -0X00000
B ----000X
EDTR0 [W] H
EDTR1 [W] H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
Block

EIA0 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EIA1 [W] W
000B24H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EIA2 [W] W
000B28H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EIA3 [W] W
000B2CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EIA4 [W] W
000B30H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EIA5 [W] W
000B34H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EIA6 [W] W
000B38H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EIA7 [W] W
000B3CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EDTA [R/W] W
000B40H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EDTM [R/W] W
000B44H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EOA0 [W] W
000B48H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EOA1 [W] W
000B4CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EPCR [R/W] W
000B50H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EPSR [R/W]
000B54H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EIAM0 [W]
000B58H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EIAM1 [W]
000B5CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EOAM0/EODM0 [W]
000B60H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EOAM1/EODM1 [W]
000B64H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EOD0 [W]
000B68H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EOD1 [W]
000B6CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
CM71-10132-3E
FUJITSU SEMICONDUCTOR LIMITED
DSU
(Evaluation
Chip Only)
669
APPENDIX
APPENDIX A I/O Map
MB91345 Series
Attached Table A-1 I/O Map (12 / 13)
Address
000B70H
to
000FFCH
Register
+0
+1
+2
+3




DMASA0 [R/W]
00000000 00000000 00000000 00000000
DMADA0 [R/W]
00000000 00000000 00000000 00000000
DMASA1 [R/W]
00000000 00000000 00000000 00000000
DMADA1 [R/W]
00000000 00000000 00000000 00000000
DMASA2 [R/W]
00000000 00000000 00000000 00000000
DMADA2 [R/W]
00000000 00000000 00000000 00000000
DMASA3 [R/W]
00000000 00000000 00000000 00000000
DMADA3 [R/W]
00000000 00000000 00000000 00000000
DMASA4 [R/W]
00000000 00000000 00000000 00000000
DMADA4 [R/W]
00000000 00000000 00000000 00000000
001000H
001004H
001008H
00100CH
001010H
001014H
001018H
00101CH
001020H
001024H
001028H
to
006FFCH






007004H
FLCR [R/W]
01101000
FLWC [R/W]
00110011



007020H
WREN



670
007030H
WA0
007034H
WD0
007038H
WA1
00703CH
WD1
007040H
WA2
007044H
WD2
007048H
WA3
00704CH
WD3
007050H
WA4
FUJITSU SEMICONDUCTOR LIMITED
Reserved
DMAC

007000H
Block
Reserved
Flash Interface
Wild Register Enble
Register
Wild Register Control
Register
Wild Register Data
Register
Wild Register Control
Register
Wild Register Data
Register
Wild Register Control
Register
Wild Register Data
Register
Wild Register Control
Register
Wild Register Data
Register
Wild Register Control
Register
CM71-10132-3E
APPENDIX
APPENDIX A I/O Map
MB91345 Series
Attached Table A-1 I/O Map (13 / 13)
Address
Register
+0
+1
+2
007054H
WD4
007058H
WA5
00705CH
WD5
007060H
WA6
007064H
WD6
007068H
WA7
00706CH
WD7
CM71-10132-3E
+3
FUJITSU SEMICONDUCTOR LIMITED
Block
Wild Register Data
Register
Wild Register Control
Register
Wild Register Data
Register
Wild Register Control
Register
Wild Register Data
Register
Wild Register Control
Register
Wild Register Data
Register
671
APPENDIX
APPENDIX B Vector Table
MB91345 Series
APPENDIX B Vector Table
This section shows the interrupt vector table.
Attached Table B-1 Interrupt Vector (1 / 3)
Interrupt No.
Offset
Address of
TBR default
DMA
transfer
DMAC
STOP
factor
10
16
Interrupt
level
Reset
0
0
-
3FCH
000FFFFCH
-
-
Mode vector
1
1
-
3F8H
000FFFF8H
-
-
System reserved
2
2
-
3F4H
000FFFF4H
-
-
System reserved
3
3
-
3F0H
000FFFF0H
-
-
System reserved
4
4
-
3ECH
000FFFECH
-
-
System reserved
5
5
-
3E8H
000FFFE8H
-
-
System reserved
6
6
-
3E4H
000FFFE4H
-
-
Coprocessor unattended trap
7
7
-
3E0H
000FFFE0H
-
-
Coprocessor error trap
8
8
-
3DCH
000FFFDCH
-
-
INTE instruction
9
9
-
3D8H
000FFFD8H
-
-
System reserved
10
0A
-
3D4H
000FFFD4H
-
-
System reserved
11
0B
-
3D0H
000FFFD0H
-
-
Step trace trap
12
0C
-
3CCH
000FFFCCH
-
-
NMI request (tool)
13
0D
-
3C8H
000FFFC8H
-
-
Undefined instruction exception
14
0E
-
3C4H
000FFFC4H
-
-
NMI request
15
0F
15 (FH) fixed
3C0H
000FFFC0H
-
-
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
--
-
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
--
-
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
--
-
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
--
-
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
--
-
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
--
-
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
--
-
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
--
-
Reload timer 0
24
18
ICR08
39CH
000FFF9CH
-
Reload timer 1
25
19
ICR09
398H
000FFF98H
Reload timer 2
26
1A
ICR10
394H
000FFF94H
2
UART0 RX/I C0 status
27
1B
ICR11
390H
000FFF90H
UART0 TX
28
1C
ICR12
38CH
000FFF8CH
❍
❍
❍
❍
❍
Interrupt factor
672
FUJITSU SEMICONDUCTOR LIMITED
STOP
-
CM71-10132-3E
APPENDIX
APPENDIX B Vector Table
MB91345 Series
Attached Table B-1 Interrupt Vector (2 / 3)
Interrupt No.
DMAC
STOP
factor
10
16
Interrupt
level
UART1 RX/I2C1 status
29
1D
ICR13
388H
000FFF88H
UART1 TX
30
1E
ICR14
384H
000FFF84H
UART2 RX/I2C2 status
31
1F
ICR15
380H
000FFF80H
UART2 TX
32
20
ICR16
37CH
000FFF7CH
❍
❍
❍
❍
UART3 RX/TX/SX
33
21
ICR17
378H
000FFF78H
--
-
UART4 RX/TX/SX
34
22
ICR18
374H
000FFF74H
--
-
UART5 RX/TX/SX
35
23
ICR19
370H
000FFF70H
--
-
UART6 RX/TX/SX
36
24
ICR20
36CH
000FFF6CH
--
-
UART7 RX/TX/SX
37
25
ICR21
368H
000FFF68H
--
-
UART8 RX/TX/SX
38
26
ICR22
364H
000FFF64H
--
-
UART9 RX/TX/SX
39
27
ICR23
360H
000FFF60H
--
-
UART10 RX/TX/SX
40
28
ICR24
35CH
000FFF5CH
--
-
A/D Converter 0
41
29
ICR25
358H
000FFF58H
-
A/D Converter 1
42
2A
ICR26
354H
000FFF54H
❍
❍
PWC (measurement completed,
overflow)
43
2B
ICR27
350H
000FFF50H
--
-
System reserved
44
2C
ICR28
34CH
000FFF4CH
--
-
Up/Down Counter 1
45
2D
ICR29
348H
000FFF48H
--
-
Up/Down Counter 2,3
46
2E
ICR30
344H
000FFF44H
--
-
Time-Base Timer Overflow
47
2F
ICR31
340H
000FFF40H
--
-
PPG 0/1/4/5
48
30
ICR32
33CH
000FFF3CH
--
-
PPG 2/3/6/7
49
31
ICR33
338H
000FFF38H
--
-
PPG 8/9/C/D
50
32
ICR34
334H
000FFF34H
--
-
PPG A/B/E/F
51
33
ICR35
330H
000FFF30H
--
-
Free-run Timer. 0
52
34
ICR36
32CH
000FFF2CH
--
-
Free-run Timer. 1
53
35
ICR37
328H
000FFF28H
--
-
Input Capture 0/1/2/3
54
36
ICR38
324H
000FFF24H
--
-
Input Capture 4/5/6/7
55
37
ICR39
320H
000FFF20H
--
-
Output Compare 0/1/2/3
56
38
ICR40
31CH
000FFF1CH
--
-
Output Compare 4/5/6/7
57
39
ICR41
318H
000FFF18H
--
-
System reserved
58
3A
ICR42
314H
000FFF14H
--
-
External interrupt 8 to 15
59
3B
ICR43
310H
000FFF10H
--
-
External interrupt 16 to 23
60
3C
ICR44
30CH
000FFF0CH
--
-
Up/Down Counter 0
61
3D
ICR45
308H
000FFF08H
--
-
DMA (ch.0 to ch.4)
62
3E
ICR46
304H
000FFF04H
--
-
Delayed interrupt factor bit
63
3F
ICR47
300H
000FFF00H
--
-
Interrupt factor
CM71-10132-3E
Offset
Address of
TBR default
DMA
transfer
STOP
FUJITSU SEMICONDUCTOR LIMITED
STOP
-
-
673
APPENDIX
APPENDIX B Vector Table
MB91345 Series
Attached Table B-1 Interrupt Vector (3 / 3)
Interrupt No.
Offset
Address of
TBR default
DMA
transfer
DMAC
STOP
factor
10
16
Interrupt
level
System reserved (Used by
REALOS)
64
40
-
2FCH
000FFEFCH
-
-
System reserved (Used by
REALOS)
65
41
-
2F8H
000FFEF8H
-
-
System reserved
66
42
-
2F4H
000FFEF4H
-
-
System reserved
67
43
-
2F0H
000FFEF0H
-
-
System reserved
68
44
-
2ECH
000FFEECH
-
-
System reserved
69
45
-
2E8H
000FFEE8H
-
-
System reserved
70
46
-
2E4H
000FFEE4H
-
-
System reserved
71
47
-
2E0H
000FFEE0H
-
-
System reserved
72
48
-
2DCH
000FFEDCH
-
-
System reserved
73
49
-
2D8H
000FFED8H
-
-
System reserved
74
4A
-
2D4H
000FFED4H
-
-
System reserved
75
4B
-
2D0H
000FFED0H
-
-
System reserved
76
4C
-
2CCH
000FFECCH
-
-
System reserved
77
4D
-
2C8H
000FFEC8H
-
-
System reserved
78
4E
-
2C4H
000FFEC4H
-
-
System reserved
79
4F
-
2C0H
000FFEC0H
-
-
Used by INT instruction
80
to
255
50
to
FF
--
2BCH
to
000H
000FFEBCH
to
000FFC00H
Interrupt factor
674
FUJITSU SEMICONDUCTOR LIMITED
--
-
CM71-10132-3E
APPENDIX
APPENDIX C Pin Status List
MB91345 Series
APPENDIX C Pin Status List
■ Single Chip Mode
Table C-1 Single Chip Mode (1 / 2)
Function macro
Multi function interface ch.1
Multi function interface ch.2
UpDown counter input
Reload timer output
Input capture input
Pin
No.
3
4
5
6
7
8
9
10
11
12
13
When initialized (INIT=0)
Pin Name
Specified function
name
P24/SOT1
P25/SCK1
P26/SIN2
P27/SOT2
P30/SCK2
P31/AIN0/TOT0-2
P32/BIN0/TOT1-2
P33/ZIN0/TOT2-2
P34/AIN2
P35/BIN2/IC4
P36/ZIN2/IC5
Function
Initial value
name
SOT1
SCK1
SIN2
SOT2
SCK2
AIN0/TOT0-2
BIN0/TOT1-2
ZIN0/TOT2-2
AIN2
BIN2/IC4
ZIN2/IC5
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
16-bit free-run timer input
14 P37/FRCK1
FRCK1
P37
External interrupt input
PPG output
15
16
17
18
19
20
21
P40/PPG9/INT16
P41/PPGB/INT17
P42/PPGD/INT18
P43/PPGF/INT19
P44/IC0/INT20
P45/IC1/INT21/SIN10
P46/IC2/INT22/SOT10
PPG9/INT16
PPGB/INT17
PPGD/INT18
PPGF/INT19
IC0/INT20
IC1/INT21/SIN10
IC2/INT22/SOT10
P40
P41
P42
P43
P44
P45
P46
22 P47/IC3/INT23/SCK10
IC3/INT23/SCK10
P47
Input capture input
Multi function
interface ch.10
A/D Input
UpDown counter
input
PPG output
External interrupt
input
27 PD0/AN0/AIN1
AN0/AIN1
PD0
28 PD1/AN1/BIN1
AN1/BIN1
PD1
29
30
31
32
33
AN2/ZIN1
AN3/AIN3
AN4/BIN3
AN5/ZIN3/PPG0
AN6/PPG2
PD2
PD3
PD4
PD5
PD6
34 PD7/AN7/PPG4
AN7/PPG4
PD7
39 PE0/AN8/INT0/PPG6
AN8/INT0/PPG6
PE0
PE1/AN9/INT1/PPG8
PE2/AN10/INT2/PPGA
PE3/AN11/INT3/PPGC
PE4/AN12/INT4/PPGE
PE5/AN13/INT5/SIN8
PE6/AN14/INT6/SOT8
PE7/AN15/INT7/SCK8
AN9/INT1/PPG8
AN10/INT2/PPGA
AN11/INT3/PPGC
AN12/INT4/PPGE
AN13/INT5/SIN8
AN14/INT6/SOT8
AN15/INT7/SCK8
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PC0/FRCK0/SIN9
FRCK0/SIN9
PC0
48 PC1/IC6/SOT9
IC6/SOT9
PC1
49
66
67
68
69
IC7/SCK9
PPG1
PPG2
PPG3
PPG7
PC2
P50
P51
P52
P53
40
41
42
43
44
Multi function
interface ch.8 45
46
16-bit free-run timer
47
input
Multi function
interface ch.9
PPG output
CM71-10132-3E
PD2/AN2/ZIN1
PD3/AN3/AIN3
PD4/AN4/BIN3
PD5/AN5/ZIN3/PPG0
PD6/AN6/PPG2
PC2/IC7/SCK9
P50/PPG1
P51/PPG2
P52/PPG3
P53/PPG7
When stopped
When
sleeping
HIZ=0
HIZ=1
P: Output
Retaining the
Hi-Z
immediately
F: Input 0
preceding
fixed
state
P: Retaining
P: Output
the
Hi-Z
immediately
preceding F: Input
enabled
state
F: Input
enabled
Retaining the
Input state/ immediately
Output Hi-Z preceding
state
FUJITSU SEMICONDUCTOR LIMITED
Retaining the
immediately P: Output
Hi-Z
preceding
F: Input 0
state
fixed
P: Retaining
the
P: Output
immediately
Hi-Z
preceding
F: Input
state
enabled
F: Input
enabled
Retaining the P: Output
immediately
Hi-Z
preceding
F: Input 0
state
fixed
675
APPENDIX
APPENDIX C Pin Status List
MB91345 Series
Table C-1 Single Chip Mode (2 / 2)
Function macro
Output compare output
PWC input
A/D trigger input
External interrupt input
Multi function
interface ch.3
Multi function
interface ch.4
Multi function
interface ch.5
Multi function interface
ch.6
Reload timer
Multi function interface
ch.7
A/D trigger input
Multi function interface
ch.0
Multi function interface ch.1
676
When initialized (INIT=0)
Pin
No.
Pin Name
Specified function
name
70
71
72
73
74
77
78
79
80
P54/RT4
P55/RT5
P58/RT6
P57/RT7
P60/RT0
P61/RT1/PWC0/ADTRG0-2
P62/RT2/ADTRG1-2
P63/RT3
P00/SIN3/INT8
RT4
RT5
RT6
RT7
RT0
RT1/PWC0/ADTRG0-2
RT2/ADTRG1-2
RT3
SIN3/INT8
P54
P55
P56
P57
P60
P61
P62
P63
P00
81 P01/SOT3/INT9
SOT3/INT9
P01
82 P02/SCK3/INT10
SCK3/INT10
P02
83 P03/SIN4/INT11
SIN4/INT11
P03
84 P04/SOT4/INT12
85 P05/SCK4/INT13
SOT4/INT12
SCK4/INT13
P04
P05
86 P06/SIN5/INT14
SIN5/INT14
P06
87 P07/SOT5/INT15
88 P10/SCK5/INT16
SOT5/INT15
SCK5/INT16
P07
P10
89 P11/SIN6/TOT0
SIN6/TOT0
P11
90
91
92
93
94
95
SOT6/TIN1
SCK6/TOT1
SIN7/TIN2
SOT7/TOT2
SCK7/ADTRG1
ADTRG0
P12
P13
P14
P15
P16
P17
P12/SOT6/TIN1
P13/SCK6/TOT1
P14/SIN7/TIN2
P15/SOT7/TOT2
P16/SCK7/ADTRG1
P17/ADTRG0
Function
Initial value
name
96 P20/SIN0
/SIN0
P20
97 P21/SOT0
98 P22/SCK0
99 P23/SIN1
SOT0
SCK0
SIN1
P21
P22
P23
When stopped
When
sleeping
HIZ=0
HIZ=1
Retaining the P: Output
Hi-Z
immediately
F: Input 0
preceding
fixed
state
P: Retaining
the
P: Output
immediately
Hi-Z
preceding
F: Input
state
Retaining the
enabled
Input state/
F: Input
immediately
Output Hi-Z
enabled
preceding state
FUJITSU SEMICONDUCTOR LIMITED
Retaining the P: Output
immediately
Hi-Z
preceding
F: Input 0
state
fixed
CM71-10132-3E
APPENDIX
APPENDIX C Pin Status List
MB91345 Series
■ Serial Writing Mode
Table C-2 Serial Writing Mode (1 / 2)
Function macro
Multi function interface ch.1
Multi function interface ch.2
UpDown counter input
Reload timer output
Input capture input
16-bit free-run timer input
External interrupt input
PPG output
Input capture input
Multi function
interface ch.10
A/D input
UpDown counter
input
PPG output
External interrupt
input
Multi function
interface ch.8
16-bit free-run timer input
Multi function interface ch.9
PPG output
CM71-10132-3E
Pin
No.
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
27
When initialized (INIT=0)
Pin Name
P24/SOT1
P25/SCK1
P26/SIN2
P27/SOT2
P30/SCK2
P31/AIN0/TOT0-2
P32/BIN0/TOT1-2
P33/ZIN0/TOT2-2
P34/AIN2
P35/BIN2/IC4
P36/ZIN2/IC5
P37/FRCK1
P40/PPG9/INT16
P41/PPGB/INT17
P42/PPGD/INT18
P43/PPGF/INT19
P44/IC0/INT20
P45/IC1/INT21/SIN10
P46/IC2/INT22/SOT10
P47/IC3/INT23/SCK10
PD0/AN0/AIN1
Specified function
name
Function
Initial value
name
SOT1
SCK1
SIN2
SOT2
SCK2
AIN0/TOT0-2
BIN0/TOT1-2
ZIN0/TOT2-2
AIN2
BIN2/IC4
ZIN2/IC5
FRCK1
PPG9/INT16
PPGB/INT17
PPGD/INT18
PPGF/INT19
IC0/INT20
IC1/INT21/SIN10
IC2/INT22/SOT10
IC3/INT23/SCK10
AN0/AIN1
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
P40
P41
P42
P43
P44
P45
P46
P47
PD0
28 PD1/AN1/BIN1
AN1/BIN1
PD1
29
30
31
32
33
34
PD2/AN2/ZIN1
PD3/AN3/AIN3
PD4/AN4/BIN3
PD5/AN5/ZIN3/PPG0
PD6/AN6/PPG2
PD7/AN7/PPG4
AN2/ZIN1
AN3/AIN3
AN4/BIN3
AN5/ZIN3/PPG0
AN6/PPG2
AN7/PPG4
PD2
PD3
PD4
PD5
PD6
PD7
39 PE0/AN8/INT0/PPG6
AN8/INT0/PPG6
PE0
40
41
42
43
44
45
46
47
AN9/INT1/PPG8
AN10/INT2/PPGA
AN11/INT3/PPGC
AN12/INT4/PPGE
AN13/INT5/SIN8
AN14/INT6/SOT8
AN15/INT7/SCK8
FRCK0/SIN9
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PC0
48 PC1/IC6/SOT9
IC6/SOT9
PC1
49
66
67
68
69
IC7/SCK9
PPG1
PPG2
PPG3
PPG7
PC2
P50
P51
P52
P53
PE1/AN9/INT1/PPG8
PE2/AN10/INT2/PPGA
PE3/AN11/INT3/PPGC
PE4/AN12/INT4/PPGE
PE5/AN13/INT5/SIN8
PE6/AN14/INT6/SOT8
PE7/AN15/INT7/SCK8
PC0/FRCK0/SIN9
PC2/IC7/SCK9
P50/PPG1
P51/PPG2
P52/PPG3
P53/PPG7
P54-L
P55-H
P55-L
Input state/ Input state/ Input state/
Output Hi-Z Output Hi-Z Output Hi-Z
FUJITSU SEMICONDUCTOR LIMITED
677
APPENDIX
APPENDIX C Pin Status List
MB91345 Series
Table C-2 Serial Writing Mode (2 / 2)
Function macro
Output compare output
PWC input
A/D trigger input
External interrupt input
Multi function
interface ch.3
Multi function
interface ch.4
Multi function interface ch.5
Multi function interface
ch.6
Reload timer
Multi function interface
ch.7
A/D trigger input
Multi function interface
ch.0
Multi function interface ch.1
678
Pin
No.
70
71
72
73
74
77
78
79
80
When initialized (INIT=0)
Pin Name
Specified function
name
P54/RT4
RT4
P55/RT5
RT5
P58/RT6
RT6
P57/RT7
RT7
P60/RT0
RT0
P61/RT1/PWC0/ADTRG0-2 RT1/PWC0/ADTRG0-2
P62/RT2/ADTRG1-2
RT2/ADTRG1-2
P63/RT3
RT3
P00/SIN3/INT8
SIN3/INT8
Function
Initial value
name
P55-H
P55-L
P54
P55
P56
P57
P60
P61
P62
P63
P00
81 P01/SOT3/INT9
SOT3/INT9
P01
82 P02/SCK3/INT10
SCK3/INT10
P02
83 P03/SIN4/INT11
SIN4/INT11
P03
84 P04/SOT4/INT12
85 P05/SCK4/INT13
SOT4/INT12
SCK4/INT13
P04
P05
86 P06/SIN5/INT14
SIN5/INT14
P06
87 P07/SOT5/INT15
88 P10/SCK5/INT16
SOT5/INT15
SCK5/INT16
P07
P10
89 P11/SIN6/TOT0
SIN6/TOT0
P11
90
91
92
93
94
95
SOT6/TIN1
SCK6/TOT1
SIN7/TIN2
SOT7/TOT2
SCK7/ADTRG1
ADTRG0
P12
P13
P14
P15
P16
P17
96 P20/SIN0
SIN0
P20
97 P21/SOT0
SOT0
P21
98 P22/SCK0
SCK0
P22
99 P23/SIN1
SIN1
P23
P12/SOT6/TIN1
P13/SCK6/TOT1
P14/SIN7/TIN2
P15/SOT7/TOT2
P16/SCK7/ADTRG1
P17/ADTRG0
P54-L
Input state/ Input state/
Output Hi-Z Output Hi-Z
Input state/
Output Hi-Z
FUJITSU SEMICONDUCTOR LIMITED
Output state Output state
Input 0
fixed/Output
Input state/
Hi-Z
Output Hi-Z
Input state/
Output Hi-Z
CM71-10132-3E
INDEX
MB91345 Series
INDEX
The index follows on the next page.
This is listed in alphabetic order.
CM71-10132-3E
FUJITSU SEMICONDUCTOR LIMITED
679
INDEX
MB91345 Series
Index
Numerics
16 Bits
FR-CPU Programming Mode
(16 Bits, Read/Write)........................... 614
16-bit Free-run Timer
Block Diagram of the 16-bit Free-run Timer
.......................................................... 244
Interrupt for the 16-bit Free-run Timer ............... 270
Notes on Using the 16-bit Free-run Timer........... 281
Program Example of the 16-bit Free-run Timer
.......................................................... 282
Registers of the 16-bit Free-run Timer................ 247
16-bit Input Capture
Block Diagram of the 16-bit Input Capture ......... 246
Input Timing of the 16-bit Input Capture ............ 280
Interrupt for the 16-bit Input Capture.................. 271
Notes on Using the 16-bit Input Capture ............. 281
Operation of the 16-bit Input Capture ................. 279
Registers of the 16-bit Input Capture .................. 250
16-bit Output Compare
Block Diagram of the 16-bit Output Compare
.......................................................... 245
Interrupt for the 16-bit Output Compare ............. 270
Notes on Using the 16-bit Output Compare......... 281
Operation of the 16-bit Output Compare (Inversion
Mode) ................................................ 276
Program Example of the 16-bit Output Compare
.......................................................... 284
Registers of the 16-bit Output Compare.............. 249
Timing of the 16-bit Output Compare Operation
.......................................................... 278
16-bit PWC
Block Diagram of the 16-bit PWC ..................... 331
Overview of the 16-bit PWC ............................. 330
Register List of the 16-bit PWC ......................... 332
16-bit Reload Register
Bit Configuration of the 16-bit Reload Register
(TMRLR) ........................................... 236
16-bit Reload Timer
Block Diagram of 16-bit Reload Timer............... 230
Overview of 16-bit Reload Timer ...................... 230
Register List of 16-bit Reload Timer .................. 231
16-bit Timer Register
Bit Configuration of the 16-bit Timer Register
(TMR)................................................ 235
32 Bits
FR-CPU ROM Mode (32 Bits, Read Only) ......... 614
32-bit Free-run Timer
Block Diagram of the 32-bit Free-run Timer
.......................................................... 290
680
Interrupt for the 32-bit Free-run Timer ............... 312
Notes on Using the 32-bit Free-run Timer .......... 323
Program Example of the 32-bit Free-run Timer
......................................................... 324
Registers of the 32-bit Free-run Timer ............... 293
32-bit Input Capture
Block Diagram of the 32-bit Input Capture ......... 292
Input Timing of the 32-bit Input Capture ............ 322
Interrupt for the 32-bit Input Capture ................. 313
Notes on Using the 32-bit Input Capture ............ 323
Operation of the 32-bit Input Capture................. 321
Registers of the 32-bit Input Capture.................. 295
32-bit Output Compare
Block Diagram of the 32-bit Output Compare
......................................................... 291
Interrupt for the 32-bit Output Compare ............. 312
Notes on Using the 32-bit Output Compare ........ 323
Operation of the 32-bit Output Compare ............ 318
Program Example of the 32-bit Output Compare
......................................................... 326
Registers of the 32-bit Output Compare ............. 294
Timing of the 32-bit Output Compare Operation
......................................................... 320
7-bit Slave Address Register
7-bit Slave Address Register (ISBA).................. 529
7-bits Slave Address Mask Register
7-bits Slave Address Mask Register (ISMK0 to
ISMKA)............................................. 527
8-bit PPG
Block Diagram of 8-bit
PPG ch.0,ch.2,ch.4,ch.6 ....................... 358
Block Diagram of 8-bit PPG ch.1,ch.5 ............... 359
Block Diagram of 8-bit PPG ch.3,ch.7 ............... 360
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
INDEX
MB91345 Series
A
A/D Control Status Register
A/D Control Status Register
(ADCS0,ADCS1) ............................... 590
A/D Conversion Time Setting Register
A/D Conversion Time Setting Register
(ADCT0,ADCT1) ............................... 596
A/D Converter
A/D Converter: 8 channels + 8 channels 2 unit
.............................................................. 3
Block Diagram of the A/D Converter ................. 587
Features of the A/D Converter........................... 586
A/D Start/End Channel Setting Registers
A/D Start/End Channel Setting Registers
(ADSCH,ADECH).............................. 598
Absolute Value
Registers of the Minimum,Maximum and Absolute
Value Arithmetic Results ..................... 648
Absolute Value Arithmetic Results Register
Absolute Value Arithmetic Results Register
.......................................................... 646
Access
Data Access....................................................... 49
Program Access ................................................. 49
Acknowledge Reception
Acknowledge Reception by the First Byte Transmit
.......................................................... 545
ADCR
Data Register (ADCR0,ADCR1) ....................... 594
Mirror Data Register
(ADCR0M,ADCR1M) ........................ 595
ADCS
A/D Control Status Register
(ADCS0,ADCS1) ............................... 590
ADCT
A/D Conversion Time Setting Register
(ADCT0,ADCT1) ............................... 596
Address
DMAC - ch.0,ch.1,ch.2,ch.3,ch.4 Transfer Source/
Destination Address Setting Register
.......................................................... 172
Address Match Detection
Slave Address Match Detection ......................... 561
Addressing
Addressing Mode............................................. 182
Direct Addressing Area ...................................... 32
ADERH
Analog Input Enable Register (ADERH0,ADERH1)
.......................................................... 589
ADSCH
A/D Start/End Channel Setting Registers
(ADSCH,ADECH).............................. 598
ADTGS
Trigger Control Register (ADTGS).................... 601
CM71-10132-3E
Analog Input Enable Register
Analog Input Enable Register (ADERH0,ADERH1)
..........................................................589
Arbitration Lost
Arbitration Lost ................................................560
Architecture
Features of Internal Architecture ..........................33
Structure of Internal Architecture .........................34
Arithmetic Data Register
Arithmetic Data Register A ...............................646
Arithmetic Data Register B................................647
Arithmetic Macro
Caution of Arithmetic Macro for MIN/MAX/ABS
..........................................................650
Asynchronous Serial Interface
Function of UART (Asynchronous Serial Interface)
..........................................................412
List of UART (Asynchronous Serial Interface)
Registers.............................................413
Automatic Algorithm
Automatic Algorithm Execution Status ...............615
AVCC Pin
About AVCC Pin................................................26
B
Base Clock Dividing Setting Register
Base Clock Dividing Setting Register
(DIVR0) .............................................106
Base Clock Dividing Setting Register 1
(DIVR1) .............................................109
Basic Configuration
Basic Configuration of the Serial Writing ...........652
Baud Rate
Allowable Baud Rate Range in Receive ..............450
Baud Rate Opearion..................................503, 566
Baud Rate Operation.........................................448
Baud Rate Selection..........................................566
Reload Value and Baud Rate for Each Peripheral
Clock Frequency..................................504
Select the CSIO (Clock Synchronization Serial
Interface) Baud Rate. ...........................502
The Reload Value and Baud Rate for Each Peripheral
Clock Frequency..........................449, 567
UART Baud Rate Selection ...............................447
Baud Rate Generator Registers
Bit Configuration of Baud Rate Generator Registers
(BGR00 to BGRA0/BGR01 to BGRA1)
..........................................................530
Bit Configuration of Baud Rate Generator Registers 0/
1 (BGR00 to BGRA0,BGR01 to BGRA1)
..................................................426, 474
FUJITSU SEMICONDUCTOR LIMITED
681
INDEX
MB91345 Series
BGR
Bit Configuration of Baud Rate Generator Registers
(BGR00 to BGRA0/BGR01 to BGRA1)
.......................................................... 530
Bit Configuration of Baud Rate Generator Registers 0/
1 (BGR00 to BGRA0,BGR01 to BGRA1)
.................................................. 426, 474
Bit Configuration
Bit Configuration of Baud Rate Generator Registers
(BGR00 to BGRA0/BGR01 to BGRA1)
.......................................................... 530
Bit Configuration of Baud Rate Generator Registers 0/
1 (BGR00 to BGRA0,BGR01 to BGRA1)
.................................................. 426, 474
Bit Configuration of Counter Control Register
(CCR) ................................................ 396
Bit Configuration of Counter Status Register
(CSR)................................................. 394
Bit Configuration of Enable Interrupts Register
(ENIR0 to ENIR2) .............................. 210
Bit Configuration of Extended Communication
Control Register (ESCR0 to ESCRA)
.................................................. 421, 469
Bit Configuration of External Interrupt Factor Register
(EIRR0 to EIRR2)............................... 211
Bit Configuration of External Interrupt Request Level
Setting Register (ELVR0 to ELVR2)
.......................................................... 212
Bit Configuration of FIFO Byte Register
(FBYTE01,FBYTE02,FBYTE11,FBYTE12
)......................................... 433, 481, 537
Bit Configuration of FIFO Control Register 0
(FCR00,FCR10).................. 430, 478, 533
Bit Configuration of FIFO Control Register 1
(FCR01,FCR11).................. 428, 476, 531
Bit Configuration of Hold Request Cancel Request
Register (HRCL) ................................. 200
Bit Configuration of Interrupt Control Register
(ICR) ................................................. 198
Bit Configuration of the 16-bit Reload Register
(TMRLR) ........................................... 236
Bit Configuration of the 16-bit Timer Register
(TMR)................................................ 235
Bit Configuration of the Control Status Register
(TMCSR) ........................................... 232
Bit Configuration of the Interrupt Control Register
(ICR) ................................................... 59
Bit Ordering
Bit Ordering....................................................... 48
Bit Search Module
Bit Search Module (REALOS is Used)................... 2
Block Diagram of Bit Search Module................. 223
Overview of Bit Search Module......................... 222
Register List of Bit Search Module .................... 223
Block Diagram
Basic Block Diagram of Port ............................. 130
682
Block Diagram ...................................... 5, 90, 380
Block Diagram of 16-bit Reload Timer .............. 230
Block Diagram of 8-bit
PPG ch.0,ch.2,ch.4,ch.6 ....................... 358
Block Diagram of 8-bit PPG ch.1,ch.5 ............... 359
Block Diagram of 8-bit PPG ch.3,ch.7 ............... 360
Block Diagram of Bit Search Module ................ 223
Block Diagram of
Delayed Interrupt Module .................... 219
Block Diagram of DMA Controller
(DMAC) ............................................ 160
Block Diagram of External Interrupt Controller
......................................................... 208
Block Diagram of Flash Memory ...................... 607
Block Diagram of Interrupt Controller ............... 196
Block Diagram of the 16-bit Free-run Timer
......................................................... 244
Block Diagram of the 16-bit Input Capture ......... 246
Block Diagram of the 16-bit Output Compare
......................................................... 245
Block Diagram of the 16-bit PWC ..................... 331
Block Diagram of the 32-bit Free-run Timer
......................................................... 290
Block Diagram of the 32-bit Input Capture ......... 292
Block Diagram of the 32-bit Output Compare
......................................................... 291
Block Diagram of the A/D Converter................. 587
Block Diagram of the Compare Timer ....... 243, 289
Block Diagram of the GATE Function ............... 361
Block Diagram of Up/Down Counters ............... 389
Block Transfer
Block Transfer................................................. 190
Branch Instruction
Branch Instruction with a Delay Slot.................... 52
Branch Instruction without a Delay Slot ............... 55
Operation of Branch Instruction with a Delay Slot
........................................................... 53
Operation of Branch Instruction without a Delay Slot
........................................................... 55
Restrictions on Branch Instructions with a Delay Slot
........................................................... 54
BSD0
Data Register for Detecting 0 (BSD0) ................ 224
BSD1
Data Register for Detecting 1 (BSD1) ................ 224
BSDC
Data Register for Detecting a Change Point (BSDC)
......................................................... 225
BSRR
Detection Result Register (BSRR) ..................... 225
Built-in Peripheral
Built-in Peripheral Request ............................... 178
Burst
Burst Two-cycle Transfer ................................. 179
FUJITSU SEMICONDUCTOR LIMITED
CM71-10132-3E
INDEX
MB91345 Series
Burst Transfer
Burst Transfer.................................................. 191
Bus Error
Bus Error Operation ......................................... 565
Condition of Bus Error Generation .................... 565
Bus Mode
Bus Mode.......................................................... 72
Byte Ordering
Byte Ordering .................................................... 48
C
C Pin
About C Pin....................................................... 26
CCR
Bit Configuration of Counter Control Register
(CCR) ................................................ 396
Change Point
Data Register for Detecting a Change Point
(BSDC).............................................. 225
For Detecting a Change Point............................ 227
Channel
Channel Selection and Control .......................... 188
Chip Erase
Erasing Data (Chip Erase)................................. 628
CLKB
CPU Clock (CLKB) ........................................... 88
CLKP
Peripheral Clock (CLKP).................................... 88
CLKR
Clock Source Control Register (CLKR) ............. 102
Clock
About Clocks..................................................... 25
Clock Dividing .................................................. 89
Clock Generation Control ................................... 84
Count Clock Selection ...................................... 341
CPU Clock (CLKB) ........................................... 88
External Clock................................................. 451
Internal Clock Operations ................................. 237
Oscillation Clock Frequency ............................. 656
Peripheral Clock (CLKP).................................... 88
Program Example for Smooth Activation and Stop of
the Clock............................................ 115
Selected External Count Clock .................. 275, 317
Smooth Activation and Stop of the Clock ........... 114
Source Clock ..................................................... 84
The Reload Value and Baud Rate for Each Peripheral
Clock Frequency ......................... 449, 567
Clock Dividing
Clock Dividing .................................................. 89
Clock Generation Control
Clock Generation Control ................................... 84
Clock Source Control Register
Clock Source Control Register (CLKR) ............. 102
CM71-10132-3E
Clock Synchronization Serial Interface
Select the CSIO (Clock Synchronization Serial
Interface) Baud Rate. ...........................502
Clock Synchronous Serial Interface
Function of CSIO (Clock Synchronous Serial
Interface) ............................................460
List of the CSIO (Clock Synchronous Serial Interface)
Registers.............................................461
Operation of CSIO (Clock Synchronous Serial
Interface) ............................................490
Command Sequence
Command Sequence .........................................616
Compare Clear Register
Compare Clear Register (CPCLRB/CPCLR)
..................................................251, 296
Compare Control Register
Compare Control Register,High-order Byte
(OCSH1,OCSH3) ................................258
Compare Control Register,High-order Byte
(OCSH45,OCSH67).............................303
Compare Control Register,Low-order Byte
(OCSL0,OCSL2) .................................260
Compare Control Register,Low-order Byte
(OCSL45,OCSL67) .............................305
Compare Detection Flag
Compare Detection Flag....................................407
Compare Time
Setting Example of the Compare/Sampling time ..603
Compare Timer
Block Diagram of the Compare Timer
..................................................243, 289
Compare Timer Operation .........................272, 314
Configuration of the Compare Timer ..........242, 288
Connection
Inter-CPU Connection.......................452, 454, 506
Continuous Mode
Continuous Mode .............................................602
Control Status Register
Bit Configuration of the Control Status Register
(TMCSR)............................................232
Control/Status Register
DMAC - ch.0,ch.1,ch.2,ch.3,ch.4 Control/Status
Register A...........................................161
DMAC - ch.0,ch.1,ch.2,ch.3,ch.4 Control/Status
Register B ...........................................166
Co-processor
Co-processor Error Trap......................................71
Co-processor Non Existence Trap ........................70