CT UCT OD U E P R OD t R P T ra TE TITU ente OLE OBS LE SUBS upport C om/tsc sil.c al S SI B POS Technic w.inter A FOR ct our IL or ww a cont -INTERS 8 6-Bit, 8 1-8 HI3086 ® August 2000 140 MSPS, Flash A/D Converter Features Description • Differential Linearity Error. . . . . . . . . . . . . . . . . ±0.2 LSB The HI3086 is a 6-bit, high-speed, flash analog-to-digital converter optimized for high speed, low power, and ease of use. With a 140 MSPS encode rate capability and full-power analog bandwidth of 200MHz, this component is ideal for applications requiring the highest possible dynamic performance. • Integral Linearity Error . . . . . . . . . . . . . . . . . . ±0.2 LSB • Single +5V Power Supply Operation Available • Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . 7pF To minimize system cost and power dissipation, only a +5V power supply is required. The HI3086’s clock input interfaces directly to TTL, ECL, or PECL logic and will operate with singleended inputs. The user may select 16-bit demultiplexed output or 8-bit single-channel digital outputs. The demultiplexed mode interleaves the data through two 8-bit channels at 1/2 the clock rate. Operation in demultiplexed mode reduces the speed and cost of external digital interfaces, while allowing the A/D converter to be clocked to the full 140 MSPS conversion rate. • Wide Analog Input Bandwidth . . . . . . . . . . . . . 200MHz • Low Power Consumption . . . . . . . . . . . . . . . . . . 360mW • CLK/2 Clock Output Pin • Excellent Temperature Characteristics • 1:2 Demultiplexed Output • Internal 1/2 Frequency Divider Circuit (With Reset Function) • Direct Replacement for Sony CXA3086 Fabricated with an advanced bipolar process, the HI3086 is provided in a space-saving 48-lead MQFP surface mount plastic package and is specified over the -20oC to 75oC temperature range. Applications Part Number Information • Compatible with ECL, PECL and TTL Digital Input Levels • RGB Graphics Processing (LCD, PDP) PART NUMBER • Digital Communications (QPSK, QAM) • Magnetic Recording (PRML) TEMP. RANGE ( oC) HI3086JCQ -20 to 75 HI3086EVAL 25 PACKAGE PKG. NO. 48 Ld MQFP Q48.12x12-S Evaluation Board Pinout DVCC2 DGND1 DVCC1 NC INV SELECT CLKOUT DGND1 NC PS DVCC2 DVCC1 HI3086 (MQFP) TOP VIEW DGND2 1 48 47 46 45 44 43 42 41 40 39 38 37 36 P2D0 (LSB) 2 3 35 34 P1D5 (MSB) 4 5 33 P1D3 P1D2 P1D1 10 1 P1D0 (LSB) DGND2 DVCC2 CLK/T 26 CLKN/E CLK/E DGND3 AGND VRT VRTS CCAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved P1D4 28 27 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 DVEE3 RESETN/E 8 9 NC RESET/E 30 29 VIN AVCC DVCC2 RESETN/T 6 7 AVCC DGND2 32 31 VRBS VRB P2D3 P2D4 P2D5 (MSB) AGND P2D1 P2D2 DGND2 File Number 4110.2 HI3086 Functional Block Diagram VRTS 22 VRT 21 AVCC INV DVCC1 DVCC2 DGND3 17 20 42 38 47 9 28 37 48 24 R1 (MSB) R 35 P1D5 34 P1D4 2 32 P1D2 31 P1D1 30 30 P1D0 31 R 32 6-BIT 6-BIT LATCH (LSB) 19 ENCODER VIN 33 P1D3 6-BIT R R TTLOUT LATCH A R 1 6-BIT R (MSB) LATCH B R 62 R R2 VRB 16 VRBS 15 CLK/T 27 CLK/E 25 CLKN/E 26 R 10 RESETN/E 12 RESET/E 11 6-BIT 7 P2D5 6 P2D4 5 P2D3 4 63 P2D2 3 P2D1 2 P2D0 (LSB) DELAY 18 40 NC 45 D RESETN/T TTLOUT 33 Q SELECT Q 43 CLKOUT 14 23 44 41 39 46 AGND PS SELECT DGND1 2 1 8 29 36 DGND2 13 DVEE3 HI3086 Pin Descriptions TYPICAL VOLTAGE LEVEL PIN NO. SYMBOL 14, 23 AGND GND Analog Ground. Separated from the digital ground. 17, 20 AV CC +5V (Typ) Analog Power Supply. Separated from the digital power supply. 1, 8, 29, 36, 39, 46 DGND1 DGND2 GND Digital Ground. 9, 28, 37, 38, 47, 48 DVCC1 DVCC2 +5V (Typ) Digital Power Supply. +5V (Typ) (With a Single Power Supply) Digital Power Supply. Ground for ECL input. +5V for PECL and TTL input. I/O 24 DGND3 EQUIVALENT CIRCUIT DESCRIPTION GND (With Dual Power Supplies) 13 Digital Power Supply. Ground for ECL input. -5V for PECL and TTL input. GND (With a Single Power Supply) DVEE3 -5V (Typ) (With Dual Power Supplies) 18, 40, 45 NC 25 CLK/E 26 No Connect pin. Not connected with the internal circuits. I I ECL/PECL Clock input. DGND3 R CLKN/E R 12 25 11 26 12 I Reset Input. When the input is set to low level, the built-in CLK frequency divider circuit can be reset. RESETN/E 1.2V 11 I RESET/E DVEE3 3 CLK/E Complementary Input. When left open, this pin goes to the threshold potential. Only CLK/E can be used for operation, but complementary input is recommended to attain fast and stable operation. R R RESETN/E Complementary Input. When left open, this pin goes to the threshold voltage. Only RESETN/E can be used for operation. HI3086 Pin Descriptions (Continued) PIN NO. SYMBOL I/O TYPICAL VOLTAGE LEVEL 27 CLK/T I TTL 10 RESETN/T I EQUIVALENT CIRCUIT DESCRIPTION Clock Input. DVCC1 R/2 Reset Input. When left open, this input goes to high level. When the input is set to low level, the built-in CLK frequency divider circuit can be reset. 10 27 1.5V R DGND1 DVEE3 42 INV I TTL 44 PS I TTL Data Output Polarity Inversion Input. When left open, this input goes to high level. (See Table 1; I/O Correspondence Table). DVCC1 Power Saving Input. When the input is set to low level, the power saving mode is set. In this time the all TTL ouputs go into the high impedance state. Normally, set to high level or left open. 42 44 DGND1 DVEE3 41 SELECT VCC or GND Data Output Mode Selection. (See Table 2, Operating Mode Table). DVCC1 41 DGND1 DVEE3 4 HI3086 Pin Descriptions (Continued) PIN NO. SYMBOL I/O 22 VRTS O TYPICAL VOLTAGE LEVEL EQUIVALENT CIRCUIT DESCRIPTION +4.0V (Typ) Reference Voltage Sense. Bypass to AGND with a 0.1µF chip capacitor. 22 21 VRT I VRTS + R1 x IREF R1 21 R COMPARATOR 1 16 VRB I VRBS -R2 x IREF Bottom Reference Voltage. Bypass to AGND with a 1µF tantal capacitor and a 0.1µF chip capacitor. R R 15 VRBS O COMPARATOR 2 +2.0V (Typ) Top Reference Voltage. Bypass to AGND with a 1µF tantal capacitor and 0.1µF chip capacitor. R Reference Voltage Sense. Bypass to AGND with a 0.1µF chip capacitor. R COMPARATOR 62 R R COMPARATOR 63 R R2 16 15 19 VIN I VRT to VRB Analog Input. COMPARATOR AVCC AVCC 19 VREF AGND DVEE3 30 to 35 P1D0 to P1D5 O Port 1 Side Data Output. 2 to 7 P2D0 to P2D5 O DVCC2 Port 2 Side Data Output. 43 CLKOUT O 2 TO 7 Clock Output. (See Table Operating Mode Table.) DVCC1 30 TO 35 100K TTL DGND1 43 DGND2 DVEE3 5 2. HI3086 Absolute Maximum Ratings (TA = 25oC) Thermal Information Supply Voltage . . . . . . . . . . (AVCC , DVCC1 , DVCC2) -0.5V to 7.0V (DGND3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V (DV EE3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7.0V to 0.5V (DGND3 - DV EE3). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V Analog Input Voltage (V IN) . . . . . . . . . . . . . . . . .VRT - 2.7V to AV CC Reference Input Voltage (V RT). . . . . . . . . . . . . . . . . . .2.7V to AVCC (V RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN - 2.7V to AV CC (|VRT - VRB |). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Digital Input Voltage ECL (***/E (Note 2)) . . . . . . . . . . . . . . . . . . . . . . . . DVEE3 to 0.5V PECL (***/E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DGND3 TTL (***/T, INV PS) . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DVCC1 Other (SELECT) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DVCC1 VID (|***/E - ***N/E| (Note 3)) . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V Thermal Resistance (Typical, Note 1) θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC (MQFP - Lead Tips Only) Recommended Operating Conditions WITH A SINGLE POWER SUPPLY MIN TYP MAX Supply Voltage DV CC1 , DVCC2 , AVCC . . . . . . . . . +4.75 +5.0 +5.25V DGND1, DGND2, AGND . . . . . . . -0.05 0 +0.05V DGND3 . . . . . . . . . . . . . . . . . . . . . +4.75 +5.0 +5.25V DV EE3 . . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05V Analog Input Voltage (V IN) . . . . . . . . VRB VRT Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . +2.9 +4.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . 1.4 +2.6V | VRT - VRB |. . . . . . . . . . . . . . . . . . 1.5 2.1V Digital Input Voltage ECL (***/E) VIH . . . . . . . . . . . . . . . . DGND3 - 1.05 DGND3 - 0.5V PECL (***/E) VIL DGND3 . . . . . . . DGND3 - 3.2 DGND3 - 1.4V TTL (***/T, INV, PS) VIH . . . . . . . . 2.0V TTL (***/T, INV) VIL . . . . . . . . . . . . 0.8V Other (SELECT) VIH . . . . . . . . . . . DVCC1 Other (SELECT) VIL . . . . . . . . . . . DGND1 VID (Note 3) (|***/E- ***N/E|) . . . . . 0.4 0.8 Max Conversion Rate (fC , Straight Mode) . . . 100 Units = MSPS Max Conversion Rate (fC , DMUX Mode) . . . . 140 Units = MSPS Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC WITH DUAL POWER SUPPLIES MIN TYP MAX Supply Voltage DV CC1 , DVCC2 , AVCC . . . . . . . . . +4.75 +5.0 +5.25V DGND1, DGND2, AGND . . . . . . . . -0.05 0 +0.05V DGND3 . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05V DV EE3 . . . . . . . . . . . . . . . . . . . . . . -5.5 -5.0 -4.75V Analog Input Voltage (V IN) . . . . . . . . VRB VRT Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . +2.9 +4.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . 1.4 +2.6V |VRT - VRB | . . . . . . . . . . . . . . . . . . 1.5 2.1V Digital Input Voltage ECL (***/E) VIH DGND3 . . . . . . . . DGND3 - 1.05 DGND3 - 0.5V ECL (***/E) VIL DGND3 . . . . . . . . . DGND3 - 3.2 DGND3 - 1.4V TTL (***/T, INV) VIH . . . . . . . . . . . . . . . . . 2.0V TTL (***/T, INV) VIL . . . . . . . . . . . . . . . . . 0.8V Other (SELECT) VIH . . . . . . . . . . . . . . . . DVCC1 Other (SELECT) VIL . . . . . . . . . . . . . . . . DGND1 VID (Note 3) (|***/E- ***N/E|) . . . . . . . . . . 0.4 0.8 Max Conversion Rate (fC , Straight Mode) . . . 100 Units = MSPS Max Conversion Rate (fC , DMUX Mode). . . . 140 Units = MSPS Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. ***/E and ***T indicate CLK/E and CLK/T, etc. for the pin name. 3. V ID: Input Voltage Differential. Electrical Specifications PARAMETER DVCC1 , 2 , AVCC , DGND3 = +5V, DGND1, 2, AGND, DV EE3 = 0V, VRT = 4V, VRB = 2V, TA = 25oC, PECL Input SYMBOL TEST CONDITIONS Resolution MIN TYP MAX UNITS - 6 - Bits - - ±0.2 LSB - - ±0.2 LSB DC CHARACTERISTICS Integral Linearity Error E IL Differential Linearity Error EDL VIN = 2VP-P , fC = 5 MSPS 6 HI3086 Electrical Specifications PARAMETER DVCC1 , 2 , AVCC , DGND3 = +5V, DGND1, 2, AGND, DV EE3 = 0V, VRT = 4V, VRB = 2V, TA = 25oC, PECL Input (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 7 - pF ANALOG INPUT VIN = +3.0V + 0.07VRMS Analog Input Capacitance CIN Analog Input Resistance RIN 16 - 150 kΩ Analog Input Current IIN 0 - 125 µA Reference Resistance (Note 5) RREF 160 225 308 Ω Reference Current (Note 6) IREF 6.5 9.0 12.5 mA REFERENCE INPUT R1 3.0 4.2 5.7 Ω R2 3.0 4.2 5.7 Ω Digital Input Voltage: High VIH DGND3 -1.05 - DGND3 -0.5 V Digital Input Voltage: Low V IL DGND3 -3.2 - DGND3-1.4 V Threshold Voltage VTH - DGND3 -1.2 - V Residual Resistance DIGITAL INPUT (ECL, PECL) Digital Input Current: High IIH VIH = DGND3 -0.8V -50 - +50 µA Digital Input Current: Low IIL VIL = DGND3 -1.6V -75 - 0 µA - - 5 pF Digital Input Capacitance DIGITAL INPUT (TTL) Digital Input Voltage: High VIH 2.0 - - V Digital Input Voltage: Low V IL - - 0.8 V Threshold Voltage VTH - 1.5 - V Digital Input Current: High IIH VIH = 3.5V -50 - 0 µA Digital Input Current: Low IIL VIL = 0.2V -500 - 0 µA - - 5 pF Digital Input Capacitance DIGITAL OUTPUT (TTL) Digital Output Voltage: High V OH IOH = -2mA 2.4 - - V Digital Output Voltage: Low VOL IOL = 1mA - - 0.5 V Leakage Current IOZ Power Saving Mode -15 - 70 µA DMUX Mode 140 - - MSPS SWITCHING CHARACTERISTICS Maximum Conversion Rate fC Aperture Jitter tAJ - 10 - ps Sampling Delay tDS 3 4.5 6 ns Clock High Pulse Width tPW1 CLK 2.9 - - ns Clock Low Pulse Width tPW0 CLK 2.9 - - ns Reset Signal Setup tRS RESETN - CLK 3.5 - - ns RESET Signal Hold tRH RESETN - CLK 0 - - ns (CL = 5pF) 3.5 7 9 ns (CL = 5pF) t (Note 6) t+1 t+2 ns (CL = 5pF) 4.5 8 10 ns CLKOUT Output Delay Data Output Delay (Note 7) tDCLK tDO1 DMUX Mode tDO2 Output Rise Time tr 0.8V to 2.0V (CL = 5pF) - 2 - ns Output Fall Time tf 0.8V to 2.0V (CL = 5pF) - 2 - ns 7 HI3086 Electrical Specifications PARAMETER DVCC1 , 2 , AVCC , DGND3 = +5V, DGND1, 2, AGND, DV EE3 = 0V, VRT = 4V, VRB = 2V, TA = 25oC, PECL Input (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 200 - - MHz DYNAMIC CHARACTERISTICS Input Bandwidth VIN = 2VP-P , -3dB S/N Ratio fC = 140 MSPS, fIN = 1kHz Full Scale, DMUX Mode - 37.0 - dB fC = 140 MSPS, fIN = 34.999MHz Full Scale, DMUX Mode - 34.5 - dB fC = 140 MSPS, fIN = 1kHz Full Scale, DMUX Mode Error > 4 LSB - - 10-12 TPS (Note 8) fC = 140 MSPS, fIN = 34.999MHz Full Scale, DMUX Mode Error > 4 LSB - - 10-9 TPS fC = 100 MSPS, fIN = 24.999MHz Full Scale, Straight Mode Error > 4 LSB - - 10-9 TSP Error Rate POWER SUPPLY Supply Current ICC 54.0 67.5 90.0 mA Supply Current IEE 0.4 0.6 0.8 mA Power Consumption (Note 9) Supply Current Power Consumption 290 360 470 mW ICC + IEE Power Saving Mode 2.0 - 8.0 mA PD Power Saving Mode 28.0 - 58.0 mW PD NOTES: 4. RREF: Resistance value between VRT and VRB . V R T -V R B 5. I R EF = ---------------------------- . R REF 1 6. t = ----- . fC 7. TPS: Times Per Sample. ( VRT -V RB ) 2 -. 8. P D = ( I CC + IEE ) • VC C + ----------------------------------V REF 8 HI3086 DGND3 VIH (MAX) VIL VTH (DGND3 - 1.2V) VID VIH VIL (MIN) FIGURE 1. ECL AND PECL SWITCHING LEVEL TABLE 1. I/O CORRESPONDENCE INV 1 V IN STEP V RTS 63 1 1 1 1 1 1 0 0 0 0 0 0 62 1 1 1 1 1 0 0 0 0 0 0 1 D0 D5 D0 32 1 0 0 0 0 0 0 1 1 1 1 1 31 0 1 1 1 1 1 1 0 0 0 0 0 • • • • • • 1 LSB STEP • • • • • • • • • VRBS D5 63 62 61 60 59 58 0 5 4 3 2 1 0 • • • 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 R2 x IREF R1 x IREF VRT VRTS VIN VRBS VRB FIGURE 2. Test Circuits 100MHz 4V 1.95V 2V VRT 5V 5V A I CC A AVCC DVCC1 DVCC2 VIN VRB OSC1 φ: VARIABLE DGND3 CLK/E DGND2 DGND1 AGND AMP IEE fR 5MHz PECL VIN 6 HI3086 LOGIC ALALYZER CLK 1024 SAMPLES OSC2 DVEE3 ECL BUFFER 100MHz FIGURE 3. CURRENT CONSUMPTION MEASUREMENT CIRCUIT FIGURE 4. SAMPLING DELAY MEASUREMENT CIRCUIT APERTURE JITTER MEASUREMENT CIRCUIT 9 HI3086 Test Circuits (Continued) +V VRT VIN S2 VRB + S1 S1: ON WHEN A < B S2: ON WHEN A > B CLK -V 6 HI3086 “0” A6 TO A1 B6 TO B1 A0 B0 6 “1” NOTE: Where σ (LSB) is the deviation of the output codes when the largest slew rate point is sampled at the clock which has exactly the same frequency as the analog input signal, the aperture jitter Tai is: 64 ∆υ tAJ = σ/ ------- = σ/ ------ x 2πf . 2 ∆T 00...00 TO 11..10 4 FIGURE 6. APERTURE JITTER MEASUREMENT METHOD 6 CLK SAMPLING TIMING FLUCTUATION (= APERTURE JITTER) CLK HI3086 -1kHz (LSB) 29 FIGURE 5. INTEGRAL LINEARITY ERROR MEASUREMENT CIRCUIT DIFFERENTIAL LINEARITY ERROR MEASUREMENT CIRCUIT fC σ BUFFER CONTROLLER VIN 32 31 30 DVM SIGNAL SOURCE 33 ∆t VIN A<B A>B COMPARATOR VIN ∆ν A LATCH COMPARATOR A>B PULSE COUNTER B CLK + LATCH 2VP-P SINE WAVE 4 LSB SIGNAL SOURCE 1/ 8 fC FIGURE 7. ERROR RATE MEASUREMENT CIRCUIT Operating Modes The HI3086 has two types of operating modes which are selected with Pin 41 (SELECT). TABLE 2. OPERATING MODE SELECT MAXIMUM CONVERSION RATE DATA OUTPUT DMUX Mode VCC 140 Mbps Demultiplexed Output 70 Mbps The input clock is 1/2 frequency divided and output at 70MHz. Straight Mode GND 100 Mbps Straight Output 100 Mbps The input clock is inverted and output at 100MHz. OPERATING MODE CLOCK OUTPUT When using multiple HI3086 units in parallel in this mode, differences in the start timing of the 1/2 frequency divided clock may cause operation as shown in Figures 8 and 9. As a countermeasure, the HI3086 is equipped with a function which resets the 1/2 frequency divided clock. When resetting this clock, the RESET pulse must be input to the RESET pin. See the Timing Charts for the RESET pulse input timing. The A/D converter can operate at fC (Min) = 140 MSPS in this mode. Demux Mode (See Figures 19, 20, 21). Set the SELECT pin to VCC for this mode. In this mode, the clock frequency is divided by 2 in the IC, and the data is output after being demultiplexed by this 1/2 frequency divided clock. The 1/2 frequency divided clock, which has adequate setup time and hold time for the output data, is output from the CLKOUT pin. 10 HI3086 CLK HI3086 CLK CLK CLKOUT A 6-BITS DATA RESETN HI3086 CLK CLKOUT B 6-BITS DATA RESETN FIGURE 8. WHEN THE RESET PULSE IS NOT USED CLK RESET PULSE HI3086 CLK CLK CLKOUT A 6-BITS DATA RESETN HI3086 CLK RESET PULSE CLKOUT B 6-BITS DATA RESETN FIGURE 9. WHEN THE RESET PULSE IS USED Straight Mode (See Figures 22, 23, 24 and 25). Digital Input Level and Supply Voltage Settings Set the SELECT pin to GND for this mode. In this mode, data output can be obtained in accordance with the clock frequency applied to the A/D converter for applications which use the clock applied to the A/D converter as the system clock. The logic input level for the HI3086 supports ECL, PECL and TTL levels. The power supplies (D VEE3 , DGND3) for the logic input block must be set to match the logic input (CLK and RESET signals) level. TABLE 3. LOGIC INPUT LEVEL AND POWER SUPPLY SETTINGS The A/D converter can operate at fC (Min) = 100 MSPS in this mode. 11 DIGITAL INPUT LEVEL DVEE3 DGND3 SUPPLY VOLTAGE APPLICATION CIRCUITS ECL -5V 0V ±5V Figures 19, 22 PECL 0V +5V +5V Figures 20, 23 TTL 0V +5V +5V Figures 21, 24, 25 HI3086 Timing Waveforms N-1 VIN N+2 tDS N+1 N t N+3 CLK tDO2 tPW1 tPW0 P1D0 TO D5 N-2 2.0V 0.8V N P2D0 TO D5 N-3 2.0V 0.8V N-1 tDO1 tDCLK t + 1ns 2.0V CLK OUT ≠t N+2 N+1 ≠t 2.0V 0.8V 0.8V tRS RESET PULSE tRH FIGURE 10. DEMUX MODE TIMING CHART (SELECT = VCC) N+2 N-1 VIN N+3 N+1 tDS N t CLK tPW1 tPW0 P1D0 TO D5 N-4 2.0V 0.8V N-3 N-2 N-1 N P2D0 TO D5 N-5 2.0V 0.8V N-4 N-3 N-2 N-1 tD02 CLK OUT (CLK IS INVERTED AND OUTPUT) 2.0V 0.8V tDCLK RESET PULSE FIGURE 11. STRAIGHT MODE TIMING CHART (SELECT = GND) 12 HI3086 Notes on Operation - Ground the power supply pins (AVCC , DVCC1 , DVCC2 , DVEE3) as close to each pin as possible with a 0.1µF or larger ceramic chip capacitor. (Connect the AVCC pin to the AGND pattern and the DV CC1 , DVCC2 , DVEE3 pins to the DGND pattern.) - The digital output wiring should be as short as possible. If the digital output wiring is long, the wiring capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output waveform since the original output slew rate is quite fast. • The HI3086 is a high-speed A/D converter which is capable of TTL, ECL and PECL level clock input. Characteristic impedance should be properly matched to ensure optimum performance during high-speed operation. • The power supply and grounding have a profound influence on converter performance. The power supply and grounding method are particularly important during high-speed operation. General points for caution are as follows: - The ground pattern should be as large as possible. It is recommended to make the power supply and ground patterns wider at an inner layer using a multi-layer board. - To prevent interference between AGND and DGND and between AVCC and DV CC , make sure the respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVCC and DVCC lines at one point each via a ferrite-bead filter. Shorting the AGND and DGND patterns in one place immediately under the A/D converter improves A/D converter performance. • The analog input pin VIN has an input capacitance of approximately 7pF. To drive the A/D converter with proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance or parasitic inductance by using a large capacity drive circuit; keeping wiring as short as possible, and using chip parts for resistors and capacitors, etc. • The VRT and V RB pins must have adequate bypass to protect them from high-frequency noise. Bypass them to AGND with approximately 1µF tantal capacitor and, 0.1µF Typical Performance Curves 90 CURRENT CONSUMPTION (mA) CURRENT CONSUMPTION (mA) 70 65 60 55 80 70 60 fIN = -1kHz 4 DEMUX MODE CL = 5pF 50 50 -25 25 0 75 AMBIENT TEMPERATURE (oC) fCLK 70 140 CONVERSION RATE (MSPS) FIGURE 12. CURRENT CONSUMPTION vs AMBIENT TEMPERATURE CHARACTERISTICS FIGURE 13. CURRENT CONSUMPTION vs CONVERSION RATE CHARACTERISTICS 13 HI3086 Typical Performance Curves (Continued) VRT = 4V VRB = 2V REFERENCE CURRENT (mA) 11 ANALOG INPUT CURRENT (µA) 100 50 10 9 8 7 0 2 3 -25 4 25 75 AMBIENT TEMPERATURE (oC) ANALOG INPUT VOLTAGE (V) FIGURE 14. ANALOG INPUT CURRENT vs ANALOG INPUT VOLTAGE CHARACTERISTICS FIGURE 15. REFERENCE CURRENT vs AMBIENT TEMPERATURE CHARACTERISTICS 40 10-6 fC = 140 MSPS fIN = fCLK -1kHz 4 ERROR > 4 LSB ERROR (TPS) 35 10-8 10-9 10 -10 30 1 3 5 10 30 50 140 100 160 180 CONVERSION RATE (MSPS) INPUT FREQUENCY (MHz) FIGURE 16. SNR vs INPUT FREQUENCY RESPONSE MAXIMUM CONVERSION RATE (MSPS) SNR (dB) 10-7 FIGURE 17. ERROR RATE vs CONVERSION RATE CHARACTERISTICS fIN = fCLK -1kHZ 4 ERROR > 4 LSB ERROR RATE: 10-9 TPS 180 170 160 150 140 -25 25 75 AMBIENT TEMPERATURE (oC) FIGURE 18. MAXIMUM CONVERSION RATE vs AMBIENT TEMPERATURE CHARACTERISTICS 14 200 HI3086 Application Circuits 6-BIT DIGITAL DATA +5V (D) DG ECL RESET PULSE P2D0 TO P2D5 6-BIT DIGITAL DATA LATCH DG 12 11 10 9 8 7 6 5 4 3 2 1 -5V (D) 13 48 AG 14 47 15 46 AG 16 45 +5V (A) 17 44 18 43 19 42 20 41 21 40 2V AG -5V (A) 4V AG 22 39 AG 23 38 DG 24 +5V (D) DG +5V (D) DG 37 +5V (D) 25 26 27 28 29 30 31 32 33 34 35 36 ECL - CLK DG +5V (D) DG P1D0 TO P1D5 6-BIT DIGITAL DATA LATCH 6-BIT DIGITAL DATA FIGURE 19. DEMUX ECL INPUT 6-BIT DIGITAL DATA +5V (D) DG PECL RESET PULSE 12 11 10 9 8 P2D0 TO P2D5 6-BIT DIGITAL DATA DG 7 6 5 4 3 2 1 DG 13 48 AG 14 47 15 46 AG 16 45 +5V (A) 17 44 18 43 AG 19 42 +5V (A) 20 41 21 40 2V AG 4V LATCH 22 39 AG 23 38 +5V (D) 24 +5V (D) DG +5V (D) DG 37 +5V (D) 25 26 27 28 29 30 31 32 33 34 35 36 PECL - CLK DG +5V (D) DG P1D0 TO P1D5 6-BIT DIGITAL DATA FIGURE 20. DEMUX PECL INPUT 15 LATCH 6-BIT DIGITAL DATA HI3086 Application Circuits (Continued) 6-BIT DIGITAL DATA +5V (D) DG TTLL RESET PULSE 12 11 10 9 DG AG P2D0 TO P2D5 6-BIT DIGITAL DATA DG 8 7 6 5 4 3 2 1 13 48 14 47 15 46 AG 16 45 +5V (A) 17 44 18 43 AG 19 42 +5V (A) 20 41 21 40 2V 4V AG LATCH 22 39 AG 23 38 +5V (D) 24 +5V (D) DG +5V (D) DG 37 +5V (D) 25 26 27 28 29 30 31 32 33 34 35 36 DG +5V (D) TTL - CLK DG P1D0 TO P1D5 6-BIT DIGITAL DATA LATCH 6-BIT DIGITAL DATA FIGURE 21. DMUX TTL INPUT +5V (D) DG 12 11 10 9 8 DG 7 6 5 4 3 2 1 -5V (D) 13 48 AG 14 47 15 46 AG 16 45 +5V (A) 17 44 18 43 AG 19 42 +5V (A) 20 41 21 40 22 39 23 38 2V 4V AG AG DG 24 37 +5V (D) DG +5V (D) DG DG +5V (D) 25 26 27 28 29 30 31 32 33 34 35 36 ECL - CLK DG +5V (D) DG P1D0 TO P1D5 6-BIT DIGITAL DATA ECL → TTL FIGURE 22. STRAIGHT ECL INPUT 16 LATCH 6-BIT DIGITAL DATA HI3086 Application Circuits (Continued) +5V (D) DG 12 11 10 9 DG AG 8 DG 7 6 5 4 3 2 1 13 48 14 47 15 46 AG 16 45 +5V (A) 17 44 18 43 AG 19 42 +5V (A) 20 41 21 40 22 39 AG 23 38 +5V (D) 24 2V 4V AG +5V (D) DG +5V (D) DG DG 37 +5V (D) 25 26 27 28 29 30 31 32 33 34 35 36 PECL - CLK DG +5V (D) DG P1D0 TO P1D5 6-BIT DIGITAL DATA LATCH 6-BIT DIGITAL DATA PECL → TTL FIGURE 23. STRAIGHT PECL INPUT +5V (D) DG 12 11 10 9 DG AG 8 DG 7 6 5 4 3 2 1 13 48 14 47 15 46 AG 16 45 +5V (A) 17 44 18 43 AG 19 42 +5V (A) 20 41 21 40 22 39 23 38 2V 4V AG AG +5V (D) 24 37 +5V (D) DG +5V (D) DG DG +5V (D) 25 26 27 28 29 30 31 32 33 34 35 36 TTL - CLK DG +5V (D) DG P1D0 TO P1D5 8-BIT DIGITAL DATA FIGURE 24. STRAIGHT TTL INPUT 17 LATCH 6-BIT DIGITAL DATA HI3086 Application Circuits (Continued) AG ANALOG INPUT 1µF 4V + - AG AG +5V (A) AG +- VRTS AG 1µF 10µF + - SHORT 2V VRBS SHORT 23 22 21 20 19 18 17 16 15 14 AGND VRTS VRT AVCC VIN NC AVCC VRB VRBS AGND RESETN/E 12 25 CLK/E RESETN/T 10 28 DVCC2 DVCC2 9 29 DGND2 DGND2 8 P1D0 30 P1D0 P2D5 7 P2D5 P1D1 31 P1D1 P2D4 6 P2D4 P1D2 32 P1D2 P2D3 5 P2D3 P1D3 33 P1D3 P2D2 4 P2D2 P1D4 34 P1D4 P2D1 3 P2D1 35 P1D5 P2D0 2 P2D0 DGND2 1 P1D5 NC SELECT INV CLKOUT PS NC DGND1 DVCC1 DVCC2 37 38 39 40 41 42 43 44 45 46 47 48 + +5V (D) CLKOUT 10µF DGND1 36 DGND2 DVCC1 (MSB) 27 CLK/T DVCC2 (LSB) RESET/E 11 26 CLKN/E TTL CLK 13 DVEE3 24 DGND3 DG DG SHORT THE ANALOG SYSTEM AND DIGITAL SYSTEM AT ONE POINT IMMEDIATELY UNDER THE A/D CONVERTER. SEE THE NOTES ON OPERATION IS THE CHIP CAPACITOR OF 0.1µF. FIGURE 25. STRAIGHT MODE TTL I/O (WHEN A SINGLE POWER SUPPLY IS USED) 18 (MSB) (LSB)