A3964: Dual Full-Bridge PWM Motor Driver

A3964
Dual Full-Bridge PWM Motor Driver
Discontinued Product
This device is no longer in production. The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: November 1, 2010
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A3964
Dual Full-Bridge PWM Motor Driver
Features and Benefits
Description
▪ ±800 mA continuous output current rating
▪ 30 V output voltage rating
▪ Internal PWM current control, saturated sink drivers
▪ Internally generated, precision 2.5 V reference
▪ Internal transient-suppression diodes
▪ Internal thermal-shutdown circuitry
▪ Crossover-current protection, UVLO protection
Designed for pulse width modulated (PWM) current control
of bipolar stepper motors, the A3964 is capable of continuous
output currents to ±800 mA and operating voltages to 30 V.
Internal fixed off-time PWM current-control circuitry can be
used to regulate the maximum load current to a desired value.
An internal precision voltage reference is provided to improve
motor peak-current control accuracy. The peak load current
limit is set by the user’s selection of an external resistor divider
and current-sensing resistors.
Package: 20 pin SOIC (suffix LB)
The fixed off-time pulse duration is set by user-selected
external RC timing networks. The capacitor in the RC timing
network also determines a user-selectable blanking window
that prevents false triggering of the PWM current control
circuitry during switching transitions. This eliminates the need
for two external RC filter networks on the current-sensing
comparator inputs.
For each bridge the PHASE input controls load current polarity
by selecting the appropriate source and sink driver pair. For
Not to scale
Continued on the next page…
1
LOAD
SUPPLY
4
18
20
OUT 2B
3
OUT 2A
17
OUT 1B
OUT 1A
LOGIC
SUPPLY
Functional Block Diagram
UVLO
& TSD
VCC
1
2
ENABLE1 10
RT
CT
REF IN
2
REF OUT
8
V REF(IN)
–
+
–
+
SENSE 1
RC1
ONE SHOT
14
PHASE 2
11
ENABLE2
SOURCE
DISABLE
2.5 V
REFERENCE
7
RA
RB
RS
19
5 6 15 16
RS
ONE SHOT
13
SENSE 2
SOURCE
DISABLE
12
CT
RC2
9
PWM 1
PHASE 1
PWM 2
VBB
RT
Dwg. FP-033-1
29319.28h
A3964
Dual Full-Bridge PWM Motor Driver
Description (continued)
each bridge the ENABLE input, when held high, disables the output
drivers. Special power-up sequencing is not required. Internal circuit
protection includes thermal shutdown with hysteresis, transientsuppression diodes, and crossover-current protection.
The A3964 is supplied in a 20-lead SOIC with internally fused pins
for enhanced thermal dissipation. The package is lead (Pb) free with
100% matte tin leadframe plating. The power pins are at ground
potential and need no electrical isolation.
Selection Guide
Part Number
Packing
A3964SLBTR-T
Package
20-pin SOIC with internally fused pins
1000 per reel
Absolute Maximum Ratings
Rating
Units
Load Supply Voltage
Characteristic
Symbol
VBB
33
V
Logic Supply Voltage
VCC
7.0
V
Input Voltage
VIN
–0.3 to VDD + 0.3
V
Sense Voltage
VS
1.0
V
1.0
mA
tw = 10 μs
±1.0
A
Continuous
±800
mA
Reference Output Current
Notes
IREF(OUT)
Output Current
Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of
conditions, do not exceed the specified current rating
or a junction temperature of 150°C.
IOUT
Package Power Dissipation
PD
See graph
Operating Ambient Temperature
TA
Range S
Maximum Junction Temperature
TJ(max)
Tstg
Pin-out Diagram
OUT 1B
1
SENSE 1
2
OUT 1A
3
1
2
VBB
20
OUT 2B
19
SENSE 2
18
OUT 2A
17
LOGIC
SUPPLY
4
GROUND
5
16
GROUND
GROUND
6
15
GROUND
V REF(IN)
7
14
V REF(OUT)
RC 1
89
13
RC 2
PHASE 1
9
12
PHASE 2
ENABLE 1
10
11
ENABLE 2
φ1
PWM 2
PWM 1
LOAD
SUPPLY
V CC
φ2
–
ºC
150
ºC
–55 to 150
ºC
Fault conditions that produce excessive junction temperature will activate
the device’s thermal shutdown circuitry. These conditions can be tolerated but should be avoided.
ALLOWABLE PACKAGE POWER DISSIPATION (W)
Storage Temperature
–
–20 to 85
5
RQJT = 6.0oC/W
4
3
2
1
SUFFIX 'LB', R QJA = 61oC/W
0
25
50
75
100
TEMPERATURE IN oC
125
150
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A3964
Dual Full-Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 30 V, VCC = 4.75 V to 5.25 V,
VS = 0 V, 30 kΩ and 1000 pF RC to Ground (unless noted otherwise)
Limits
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Output Drivers
Load Supply Voltage Range
Output Sustaining Voltage
Output Leakage Current
Output Saturation Voltage
Clamp Diode Forward Voltage
VBB
Operating, IOUT = ±800 mA, L = 3 mH
5.0
—
30
V
VCE(sus)
IOUT = ±800 mA, L = 3 mH, VBB = 33 V
33
—
—
V
VOUT = VBB = 33 V
—
<1.0
50
μA
VOUT = 0 V, VBB = 33 V
—
<1.0
-50
μA
Source Driver, IOUT = -500 mA
—
1.0
1.2
V
Source Driver, IOUT = -750 mA
—
1.1
1.5
V
Source Driver, IOUT = -800 mA
—
—
1.7
V
Sink Driver, IOUT = +500 mA
—
0.3
0.6
V
Sink Driver, IOUT = +750 mA
—
0.5
1.2
V
Sink Driver, IOUT = +800 mA
—
—
1.5
V
IF = 500 mA
—
1.1
1.4
V
IF = 750 mA
—
1.3
1.6
V
ICEX
VCE(SAT)
VF
(Sink or Source)
IF = 800 mA
—
—
1.7
V
Motor Supply Current
IBB(ON)
VENABLE = 0.8 V
—
2.0
4.0
mA
(No Load)
IBB(OFF)
VENABLE = 2.4 V
—
0
500
μA
Continued on the next page …
TRUTH TABLE
ENABLE
PHASE
OUTA
OUTB
H
X
Off
Off
L
H
H
L
L
L
L
H
X = Irrelevant
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A3964
Dual Full-Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS (continued) at TA = +25°C, VBB = 30 V, VCC = 4.75 V to 5.25 V,
VSENSE = 0 V, 30 kΩ and 1000 pF RC to Ground (unless noted otherwise)
Limits
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Operating
4.75
—
5.25
V
Control Logic
Logic Supply Voltage Range
VCC
Logic Input Voltage
VIN(1)
2.4
—
—
V
VIN(0)
—
—
0.8
V
Logic Input Current
IIN(1)
VIN = 2.4 V
—
<1.0
20
μA
IIN(0)
VIN = 0.8 V
—
<-2.0
-200
μA
Reference Output Voltage
VREF(OUT)
VCC = 5.0 V, IREF(OUT) = 90 to 900 μA
2.45
2.50
2.55
V
Reference Output Current
IREF(OUT)
3 kΩ ≤ RD = RA + RB ≤ 15 kΩ
150
—
900
μA
Ref. Input Offset Current
IOS
VREF(IN) = 1 V
-2.5
0
1.0
μA
Comparator Input Offset Volt.
VIO
VREF(IN) = 0 V
-6.0
0
6.0
mV
Operating
Comparator Input Volt. Range
PWM RC Fixed Off-time
PWM Propagation Delay Time
VREF
tOFF RC
tPWM
PWM Minimum On Time
tON(min)
Propagation Delay Times
tpd
-0.3
—
1.0
V
CT = 1000 pF, RT = 30 kΩ
27
30
33
μs
Comparator Trip to Source Off
—
1.2
2.0
μs
CT = 1000 pF, RT ≥ 15 kΩ, VCC = 5 V
—
2.5
3.6
μs
—
3.2
—
μs
IOUT = ±800 mA, 50% to 90%:
ENABLE On to Source On
ENABLE Off to Source Off
—
1.2
—
μs
ENABLE On to Sink On
—
3.2
—
μs
ENABLE Off to Sink Off
—
0.7
—
μs
PHASE Change to Sink On
—
3.2
—
μs
PHASE Change to Source On
—
3.2
—
μs
PHASE Change to Sink Off
—
0.7
—
μs
PHASE Change to Source Off
Thermal Shutdown Temp.
TJ
—
1.2
—
μs
—
165
—
°C
—
15
—
°C
Decreasing VCC
4.20
4.40
4.65
V
UVLO Hysteresis
UVLO Enable Volt. - UVLO Disable Volt.
0.075
0.125
0.175
V
UVLO Enable Threshold
Increasing VCC
4.375
4.525
4.725
V
Thermal Shutdown Hysteresis
∆TJ
UVLO Disable Threshold
Logic Supply Current
Logic Supply Current
ICC(ON)
VENABLE 1 = VENABLE 2 = 0.8 V
—
60
85
mA
ICC(OFF)
VENABLE 1 = VENABLE 2 = 2.4 V
—
13
17
mA
∆ICC(ON)
VENABLE 1 = VENABLE 2 = 0.8 V
—
0.18
—
mA/°C
Temperature Coefficient
NOTES: 1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A3964
Dual Full-Bridge PWM Motor Driver
FUNCTIONAL DESCRIPTION
Internal PWM Current Control. The A3964 contain a fixed
off-time, pulse width modulated (PWM) current-control circuit
that can be used to limit the load current to a desired value. The
peak value of the current limiting (ITRIP) is set by the selection
of an external current-sensing resistor (RS) and reference input
voltage (VREF(IN)). The internal circuitry compares the voltage
across the external sense resistor to the voltage on the reference
input terminal (VREF(IN)) resulting in a transconductance function
approximated by:
VREF(IN)
ITRIP ≈
RS
The reference input voltage is typically set with a resistor divider
from VREF(OUT). To ensure proper operation of the voltage
reference, the resistor divider should have an impedance of 3 kΩ
to 15 kΩ (RD = RA+RB). Within this range, a low impedance will
minimize the effect of the REF IN input offset current.
The current-control circuitry limits the load current as follows:
when the load current reaches ITRIP, the comparator resets a latch
that turns off the selected source driver. The load inductance
causes the current to recirculate through the sink driver and
flyback diode.
For each bridge, the user selects an external resistor (RT) and
capacitor (CT) to determine the time period (tOFF = RTCT) during
which the source driver remains disabled (see the RC Fixed
Off-time section, below). The range of recommended values
for CT and RT are 1000 pF to 1500 pF and 15 kΩ to 100 kΩ
respectively. For optimal load current regulation, CT is normally
set to 1000 pF (see the Load Current Regulation section, below).
At the end of the RC interval, the source driver is enabled
allowing the load current to increase again. The PWM cycle
repeats, maintaining the peak load current at the desired value.
RC Blanking. In addition to determining the fixed off-time of
the PWM control circuit, the CT component sets the comparator
blanking time. This function blanks the output of the comparator
when the outputs are switched by the internal current-control
circuitry (or by the PHASE or ENABLE inputs). The comparator
output is blanked to prevent false over-current detections due to
reverse-recovery currents of the clamp diodes, and/or switching
transients related to distributed capacitance in the load.
During internal PWM operation, at the end of the tOFF time, the
comparator’s output is blanked and CT begins to be charged
from approximately 1.1 volts by an internal current source of
approximately 1 mA. The comparator output remains blanked
until the voltage on CT reaches approximately 3 volts.
When a transition of the PHASE input occurs, CT is discharged
to near ground during the crossover delay time (the crossover
delay time is present to prevent simultaneous conduction of
the source and sink drivers). After the crossover delay, CT is
charged by an internal current source of approximately 1 mA.
The comparator output remains blanked until the voltage on CT
reaches approximately 3 volts.
When the device is disabled, via the ENABLE input, CT is
discharged to near ground. When the device is re-enabled, CT is
charged by an internal current source of approximately 1 mA.
The comparator output remains blanked until the voltage on CT
reaches approximately 3 volts.
The minimum recommended value for CT is 1000 pF. This
value ensures that the blanking time is sufficient to avoid false
trips of the comparator under normal operating conditions. For
optimal regulation of the load current, the above value for CT
is recommended and the value of RT can be sized to determine
tOFF. For more information regarding load current regulation, see
below.
Load Current Regulation. Because the device operates in a
slow current-decay mode (2-quadrant PWM mode), there is a
limit to the lowest level that the PWM current control circuitry
can regulate load current. The limitation is due to the minimum
PWM duty cycle, which is a function of the user-selected value
of tOFF and the minimum on-time pulse tON(min)max that occurs
each time the PWM latch is reset. If the motor is not rotating, as
in the case of a stepper motor in hold/detent mode, a brush dc
motor when stalled or at startup, the worst case value of current
regulation can be approximated by:
[(VBB – VSAT(SOURCE+SINK)) x tON(min)max] – [1.05 (VSAT(SINK) + VF) x tOFF]
IAVG ≈
1.05 (tON(min)max + tOFF) x RLOAD
where tOFF = RTCT, RLOAD is the series resistance of the load,
VBB is the motor supply voltage and t ON(min)max is specified in
the electrical characteristics table. When the motor is rotating,
the back EMF generated will influence the above relationship.
For brush dc motor applications, the current regulation is
improved. For stepper motor applications when the motor is
rotating, the effect is dependent on the polarity and magnitude of
the motor’s back EMF.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A3964
Dual Full-Bridge PWM Motor Driver
The following procedure can be used to evaluate the worst case
internal PWM load current regulation in the system: set VREF(IN)
to 0 volts. With the load connected and the PWM current control
operating in slow decay mode, use an oscilloscope to measure the
time the output is low (sink on) for the output that is chopping.
This is the typical minimum on time (tON(min)typ) for the device.
The CT then should be increased until the measured value of
tON(min) is equal to tON(min)max as specified in the electrical
characteristics table. When the new value of CT has been set,
the value of RT should be decreased so the value for tOFF =
RTCT (with the artificially increased value of CT) is equal to the
nominal design value. The worst-case load-current regulation
then can be measured in the system under operating conditions.
PWM of the Phase and Enable Inputs. The PHASE and
ENABLE inputs can be pulse width modulated to regulate
load current. Typical propagation delays from the PHASE and
ENABLE inputs to transitions of the power outputs are specified
in the electrical characteristics table. If the internal PWM current
control is used, the comparator blanking function is active during
phase and enable transitions. This eliminates false tripping of the
over-current comparator caused by switching transients (see the
RC Blanking section, above).
Enable PWM. Toggling the ENABLE input turns on and off
the selected source and sink drivers. The corresponding pair
of flyback and ground clamp diodes conduct after the drivers
are disabled, resulting in fast current decay. When the device is
enabled the internal current control circuitry will be active and
can be used to limit the load current in a slow current-decay
mode.
APPLICATION NOTES
Current Sensing. The actual peak load current (IPEAK) will be
above the calculated value of ITRIP due to delays in the turn off of
the drivers. The amount of overshoot can be approximated by:
(VBB – [(ITRIP x RLOAD) + VBEMF]) x tPWM
IOS ≈
LLOAD
where VBB is the motor supply voltage, VBEMF is the back-EMF
voltage of the load, RLOAD and LLOAD are the resistance and
inductance of the load respectively, and t PWM is specified in the
electrical characteristics table.
To minimize current sensing inaccuracies caused by ground trace
IR drops, each current-sensing resistor should have a separate
return to the ground terminal of the device. For low-value sense
resistors, the IR drops in the PCB can be significant and should
be taken into account. The use of sockets should be avoided as
their contact resistance can cause variations in the effective value
of RS.
Generally, larger values of RS reduce the aforementioned effects
but can result in excessive heating and power loss in the sense
resistor. The selected value of RS should not cause the absolute
maximum voltage rating of 1.0 V, for the SENSE terminal, to be
exceeded. The recommended value of RS is in the range of:
0.5
± 50%
RS ≈
ITRIPmax
Phase PWM. Toggling the PHASE terminal selects which sink/
If desired, the reference input voltage can be filtered by placing
a capacitor from REFIN to ground. The ground return for this
capacitor as well as RB should be independent from the highcurrent power-ground trace to avoid changes in REFIN due to IR
drops.
source pair is enabled, producing a load current that varies with
the duty cycle and remains continuous at all times. This can have
added benefits in bidirectional brush dc servo motor applications
as the transfer function between the duty cycle on the PHASE
input and the average voltage applied to the motor is more linear
than in the case of ENABLE PWM control (which produces a
discontinuous current at low current levels).
Thermal Considerations. For reliable operation, it is
recommended that the maximum junction temperature be
kept below 110°C to 125°C. The junction temperature can be
measured best by attaching a thermocouple to the power tab/
batwing of the device and measuring the tab temperature, TTAB .
The junction temperature can then be approximated by using the
formula:
Miscellaneous Information. An internally generated dead time
prevents crossover currents that can occur when switching phase.
Thermal protection circuitry turns off all drivers should the
junction temperature reach +165°C (typical). This is intended
only to protect the device from failures due to excessive junction
temperatures and should not imply that output short circuits
are permitted. The hysteresis of the thermal shutdown circuit is
approximately 15°C.
TJ ≈ TTAB + (2 ILOAD VF RθJT)
where VF can be chosen from the electrical specification table
for the given level of ILOAD. The value for RθJT is approximately
6°C/W.
The power dissipation of the batwing packages can be improved
by 20 to 30% by adding a section of printed circuit board copper
(typically 6 to 18 square centimeters) connected to the batwing
terminals of the device.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A3964
Dual Full-Bridge PWM Motor Driver
The thermal performance in applications that run at high load
currents and/or high duty cycles can be improved by adding
external diodes from each output to ground in parallel with the
internal diodes. Fast-recovery (≤200 ns) diodes should be used to
minimize switching losses.
load supply voltage. See also the Current Sensing and Thermal
Considerations sections, above.
Fixed Off-Time Selection. With increasing values of tOFF,
switching losses will decrease, low-level load current regulation
will improve, EMI will be reduced, the PWM frequency will
decrease, and ripple current will increase. The value of tOFF can
be chosen for optimization of these parameters. For applications
where audible noise is a concern, typical values of tOFF are
chosen to be in the range of 15 to 35 μs.
The load supply terminal, VBB, should be decoupled with an
electrolytic capacitor (≥47 μF is recommended) placed as close
to the device as is physically practical. To minimize the effect of
system ground IR drops on the logic and reference input signals
the system ground should have a low-resistance return to the
LB package 20-pin SOICW
12.80±0.20
4° ±4
20
20
+0.07
0.27 –0.06
7.50±0.10
10.30±0.33
A
1
2.25
9.50
+0.44
0.84 –0.43
2
1
2
0.65
0.25
20X
SEATING
PLANE
0.10 C
0.41 ±0.10
1.27
C
SEATING PLANE
GAUGE PLANE
1.27
B PCB Layout Reference View
2.65 MAX
0.20 ±0.10
All dimensions nominal, not for tooling use
Dimensions in millimeters
Pins 5, 6, 15 and 16 internally fused
(Reference JEDEC MS-013 AC)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Reference pad layout (reference IPC SOIC127P1030X265-20M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Copyright ©1997-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
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