A5832: BiMOS II 32-Bit Serial-Input Latched Drivers

A5832
BiMOS II 32-Bit Serial Input Latched Driver
Discontinued Product
These parts are no longer in production The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: October 31, 2005
Recommended Substitutions:
For new customers or new applications, refer to the A6832.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a
product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information
included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor
for any infringements of patents or other rights of third parties which may result from its use.
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
Data Sheet
26185.10B
5832
BiMOS II 32-BIT SERIAL-INPUT,
LATCHED DRIVERS
UCN5832A
LOGIC
SUPPLY
1
40 CLOCK
V DD
OUTPUT
ENABLE
STROBE
4
37
OUT 32
OUT 1
5
36
OUT 31
OUT
6
35
OUT 30
7
34
OUT 29
8
33
OUT 28
9
32
OUT 27
2
OUT
OUT
3
4
OUT
OUT
5
6
10
LATCHES
SERIAL
DATA OUT
38
REGISTER
39
3
LATCHES
2
REGISTER
SERIAL
DATA IN
GROUND
31 OUT
26
30 OUT 25
OUT 7
11
OUT 8
12
29
OUT 24
OUT 9
12
28
OUT 23
OUT 10 14
27
OUT
OUT
26
OUT 21
11 15
Intended originally to drive thermal printheads, the UCN5832A
and UCN5832EP have been optimized for low output-saturation
voltage, high-speed operation, and pin configurations most convenient
for the tight space requirements of high-resolution printheads. These
integrated circuits can also be used to drive multiplexed LED displays
or incandescent lamps at up to 150 mA peak current. The combination
of bipolar and MOS technologies gives BiMOS II arrays an interface
flexibility beyond the reach of standard buffers and power driver
circuits.
The devices each have 32 bipolar NPN open-collector saturated
drivers, a CMOS data latch for each of the drivers, two 16-bit CMOS
shift registers, and CMOS control circuitry. The high-speed CMOS
shift registers and latches allow operation with most microprocessor
based systems. Use of these drivers with TTL may require input
pull-up resistors to ensure an input logic high. MOS serial data
outputs permit cascading for interface applications requiring additional
drive lines.
22
OUT 12 16
25
OUT 20
OUT 13 17
24
OUT 19
OUT 14 18
23 OUT 18
OUT 15 19
22
OUT 16 20
21 INTERNAL
CONNECTION
OUT 17
The UCN5832A is supplied in a 40-pin dual in-line plastic package
with 0.600" (15.24 mm) row spacing. Under normal operating conditions, this device will allow all outputs to sustain 100 mA continuously
without derating. The UCN5832EP is supplied in a 44-lead plastic
leaded chip carrier for minimum area, surface-mount applications.
Both devices are also available for operation from -40°C to +85°C.
To order, change the prefix from ‘UCN’ to ‘UCQ’.
Dwg. No. A-12,377A
ABSOLUTE MAXIMUM RATINGS
Similar 32-bit serial-input latched source drivers are available as
the UCN5818AF/EPF. Other high-voltage, high-current 8-bit devices
are available as the UCN5821A, UCN5841A/LW, and UCN5842A.
at +25°C Free-Air Temperature
Output Voltage, VOUT ...................... 40 V
Logic Supply Voltage, VDD ................ 15 V
Input Voltage Range,
VIN ................... -0.3 V to V DD + 0.3 V
Continuous Output Current,
lOUT .................................. 150 mA
Package Power Dissipation,
PD ................................ See Graph
Operating Temperature Range,
TA ........................... -20°C to +85 °C
Storage Temperature Range,
TS .......................... -55°C to +150°C
Caution: CMOS devices have input-static
protection but are susceptible to damage when
exposed to extremely high static electrical charges.
FEATURES
■
■
■
■
■
To 3.3 MHz Data Input Rate
Low-Power CMOS Logic and Latches
40 V Current Sink Outputs
Low Saturation Voltage
Automotive Capable
Always order by complete part number:
Part Number
Package
UCN5832A
40-Pin DIP
UCN5832EP
44-Lead PLCC
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
FUNCTIONAL BLOCK DIAGRAM
2.5
SUFFIX 'A', R
θJA
= 36°C/W
V DD
CLOCK
32-BIT SHIFT REGISTER
2.0
SERIAL
DATA IN
SERIAL DATA
OUT
LATCHES
STROBE
1.5
SUFFIX 'EP', RθJA = 46°C/W
OUTPUT
ENABLE
1.0
MOS
BIPOLAR
0.5
OUT1 OUT2 OUT3
GROUND OUT30 OUT31 OUT32
0
150
Dwg. GP-025A
NC
STROBE
GROUND
SERIAL
DATA IN
LOGIC
SUPPLY
CLOCK
SERIAL
DATA OUT32
OUTPUT
ENABLE
OUT32
NC
5
4
3
2
VDD 1
44
43
42
41
40
7
39 OUT31
8
38
9
37
12
13
36
LATCHES
11
SHIFT REGISTER
10
SHIFT REGISTER
OUT 2
OUT1
UCN5832EP
6
35
34
33
14
32
15
31
30
16
29 OUT21
NC 28
OUT 20 27
26
25
OUT 17 24
IC 23
OUT 16 22
21
20
OUT12 17
OUT 13 19
50
75
100
125
AMBIENT TEMPERATURE IN °C
LATCHES
25
NC 18
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
3.0
Dwg. No. A-14,360
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1984, 1998, Allegro MicroSystems, Inc.
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise noted).
Characteristic
Output Leakage Current
Collector-Emitter
Saturation Voltage
Min.
Limits
Max.
Units
VOUT = 40 V, TA = 70°C
—
10
µA
lOUT = 50 mA
—
275
mV
150
550
mV
—
550
mV
VIN(1)
3.5
5.3
V
VIN(0)
-0.3
+0.8
V
Symbol
ICEX
VCE(SAT)
Test Conditions
lOUT = 100 mA, “A” package
lOUT = 100 mA, “EP” package
Input Voltage
Input Current
Input lmpedance
Serial Data Output Resistance
Supply Current
lIN(1)
VIN = 3.5 V
—
1.0
µA
lIN(0)
VIN = 0.8 V
—
-1.0
µA
ZIN
VIN = 3.5 V
3.5
—
MΩ
—
20
kΩ
One output ON, lOUT = 100 mA
—
5.0
mA
All outputs OFF
—
50
µA
ROUT
lDD
Output Rise Time
tr
lOUT = 100 mA, 10% to 90%
—
1.0
µs
Output Fall Time
tf
lOUT = 100 mA, 90% to 10%
—
1.0
µs
NOTE: Positive (negative) current is defined as going into (coming out of) the specified device pin.
TYPICAL INPUT CIRCUIT
TYPICAL OUTPUT DRIVER
VDD
VDD
IN
OUT
675Ω
Dwg. No. A-12,379A
Dwg. No. A-12,380A
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
CLOCK
A
B
Serial Data present at the input is transferred to the shift register on the logic “0” to
logic “1” transition of the CLOCK input pulse.
On succeeding CLOCK pulses, the registers
shift data information towards the SERIAL
DATA OUTPUT. The SERIAL DATA must
appear at the input prior to the rising edge of
the CLOCK input waveform.
D
DATA IN
E
STROBE
F
C
OUTPUT
ENABLE
G
OUTN
Dwg. No. A-12,276A
TIMING CONDITIONS
(VDD = 5.0 V, Logic Levels are VDD and Ground)
Information present at any register is
transferred to its respective latch when the
STROBE is high (serial-to-parallel conversion). The latches will continue to accept
new data as long as the STROBE is held
high. Applications where the latches are
bypassed (STROBE tied high) will require
that the OUTPUT ENABLE input be low
during serial data entry.
When the OUTPUT ENABLE input is low,
all of the output buffers are disabled (OFF)
without affecting the information stored in the
latches or shift register. With the OUTPUT
ENABLE input high, the outputs are controlled by the state of the latches.
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) .......................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ............................................................................. 75 ns
C. Minimum Data Pulse Width ................................................................ 150 ns
D. Minimum Clock Pulse Width ............................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns
F. Minimum Strobe Pulse Width ............................................................. 100 ns
G. Typical Time Between Strobe Activation and
Output Transition ........................................................................... 500 ns
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 ... IN-1 IN
Serial
Data Strobe
Output Input
Latch Contents
I1
I2
I3
...
IN-1
IN
Output
Enable
Input
Output Contents
I1 I2 I3 ... IN-1 I N
H
H
R1 R2 ...
RN-2 RN-1
RN-1
L
L
R1 R2 ...
RN-2 RN-1
RN-1
X
R1 R2 R3 ...
RN-1 RN
RN
X
X
X
L
R1 R2 R3 ...
RN-1 RN
PN
H
P1 P2 P3 ...
PN-1 PN
H
P1 P2 P3 ... PN-1 PN
X
X
L
H H H ... H
X
X
...
P1 P2 P3 ...
L = Low Logic Level
X
PN-1 PN
H = High Logic Level
X = Irrelevant
X
P = Present State
X
...
X
R = Previous State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
H
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
UCN5832A
Dimensions in Inches
(controlling dimensions)
0.015
0.008
40
21
0.700
MAX
0.580
0.485
0.600
BSC
1
2
0.070
0.030
3
20
0.100
4
2.095
1.980
0.005
MIN
BSC
0.250
MAX
0.015
0.200
0.115
MIN
0.022
0.014
Dwg. MA-003-40 in
Dimensions in Millimeters
(for reference only)
0.381
0.204
40
21
17.78
MAX
14.73
12.32
15.24
BSC
1
2
1.77
0.77
3
4
2.54
53.2
50.3
BSC
20
0.13
MIN
6.35
MAX
0.39
5.08
2.93
MIN
0.558
0.356
NOTES: 1. Lead thickness is measured at seating plane or below.
2. Lead spacing tolerance is non-cumulative.
3. Exact body and lead configuration at vendor’s option within limits shown.
Dwg. MA-003-40 mm
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
UCN5832EP
Dimensions in Inches
(controlling dimensions)
18
28
29
17
0.032
0.026
0.319
0.291
0.695
0.685
0.021
0.013
0.656
0.650
0.319
0.291
0.050
INDEX AREA
BSC
39
7
40
0.020
44
1
2
6
0.656
0.650
MIN
0.695
0.685
0.180
0.165
Dwg. MA-005-44A in
Dimensions in Millimeters
(for reference only)
18
28
29
17
0.812
0.661
8.10
7.39
17.65
17.40
0.533
0.331
16.662
16.510
8.10
7.39
INDEX AREA
1.27
BSC
7
39
40
0.51
MIN
4.57
4.20
44
1
2
6
16.662
16.510
17.65
17.40
Dwg. MA-005-44A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
BiMOS II (Series 5800) & DABiC IV (Series 6800)
INTELLIGENT POWER INTERFACE DRIVERS
SELECTION GUIDE
Function
Output Ratings *
Part Number †
SERIAL-INPUT LATCHED DRIVERS
8-Bit (saturated drivers)
8-Bit
8-Bit
8-Bit
8-Bit
-120 mA
350 mA
350 mA
350 mA
350 mA
50 V‡
50 V
80 V
50 V‡
80 V‡
5895
5821
5822
5841
5842
1.6 A
50 V
5829
10-Bit (active pull-downs)
-25 mA
60 V
5810-F and 6809/10
12-Bit (active pull-downs)
-25 mA
60 V
5811 and 6811
20-Bit (active pull-downs)
-25 mA
60 V
5812-F and 6812
32-Bit (active pull-downs)
32-Bit
32-Bit (saturated drivers)
-25 mA
100 mA
100 mA
60 V
30 V
40 V
5818-F and 6818
5833
5832
9-Bit
PARALLEL-INPUT LATCHED DRIVERS
4-Bit
350 mA
50 V‡
5800
8-Bit
8-Bit
-25 mA
350 mA
60 V
50 V‡
5815
5801
SPECIAL-PURPOSE FUNCTIONS
Unipolar Stepper Motor Translator/Driver
Addressable 28-Line Decoder/Driver
1.25 A
450 mA
50 V‡
30 V
*
Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.
Negative current is defined as coming out of (sourcing) the output.
†
Complete part number includes additional characters to indicate operating temperature range and package style.
‡
Internal transient-suppression diodes included for inductive-load protection.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be required
to permit improvements in the design of its products.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third
parties which may result from its use.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5804
6817
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