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Fujitsu Microelectronics Europe
Application Note
MCU-AN-300215-E-V12
F²MC-16FX FAMILY
16-BIT MICROCONTROLLER
ALL SERIES
A/D CONVERTER
APPLICATION NOTE
A/D CONVERTER
Revision History
Revision History
Date
2006-07-28
2007-03-01
2007-09-04
Issue
First Version; MWi
V1.1, Reviewed the document and updated with review findings, MPi
V1.2, Updated the entire documents with review findings from PHu, MPi
This document contains 28 pages.
MCU-AN-300215-E-V12
-2-
© Fujitsu Microelectronics Europe GmbH
A/D CONVERTER
Warranty and Disclaimer
Warranty and Disclaimer
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its warranties and its liability for all products delivered free of charge (e.g. software include or
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Microelectronics Europe GmbH disclaims all warranties and liabilities for the performance of the
Product and any consequential damages in cases of unauthorised decompiling and/or reverse
engineering and/or disassembling. Note, all these products are intended and must only be used
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1.
Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in
accordance with the accompanying written materials for a period of 90 days form the date of
receipt by the customer. Concerning the hardware components of the Product, Fujitsu
Microelectronics Europe GmbH warrants that the Product will be free from defects in material
and workmanship under use and service as specified in the accompanying written materials
for a duration of 1 year from the date of receipt by the customer.
2.
Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH´s entire liability
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Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in
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However, this warranty is excluded if the defect has resulted from an accident not attributable
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NO LIABILITY FOR CONSEQUENTIAL DAMAGES
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stipulations shall stay in full effect
© Fujitsu Microelectronics Europe GmbH
-3-
MCU-AN-300215-E-V12
A/D CONVERTER
Contents
Contents
REVISION HISTORY ............................................................................................................ 2
WARRANTY AND DISCLAIMER ......................................................................................... 3
CONTENTS .......................................................................................................................... 4
1 INTRODUCTION.............................................................................................................. 6
1.1
Key Features........................................................................................................... 6
2 THE ANALOGUE/DIGITAL CONVERTER....................................................................... 7
2.1
Block Diagram......................................................................................................... 7
2.2
Registers................................................................................................................. 8
2.2.1
Control Status Register (ADCS) .................................................................. 8
2.2.2
Date Register (ADCR)................................................................................. 9
2.2.3
Setting Register (ADSR) ............................................................................. 9
2.2.3.1
Sampling/Conversion Time ...................................................... 10
2.2.3.2
Start/Stop Channels................................................................. 10
2.2.4
ADC Extended Configuration Register (ADECR) ....................................... 11
2.2.5
Analog Input Enable Register (ADER0 – ADERn) ...................................... 11
3 POWER SUPPLY OF A/D CONVERTER ...................................................................... 13
3.1
Power consumption............................................................................................... 13
3.2
Noise consideration............................................................................................... 13
4 ANALOGUE INPUT AND RELATED EXTERNAL CIRCUITS ....................................... 15
4.1
External circuits for analogue input........................................................................ 15
4.2
Input Leakage current consideration...................................................................... 16
5 SAMPLING TIME CONSIDERATION ............................................................................ 18
6 LATCH-UP RELATED TO AVCC/VCC AND LARGE INPUT SIGNAL .............................. 20
6.1
AVCC > VCC ............................................................................................................ 20
6.2
AVCC < VCC............................................................................................................. 20
6.3
UAIN > AVCC or VCC .................................................................................................. 21
6.4
Conclusion ............................................................................................................ 21
7 INPUT IMPEDANCE ...................................................................................................... 22
7.1
Recharging and discharging the Sampling capacitor ............................................. 22
8 ADC EXAMPLE ............................................................................................................. 24
8.1
ADC with interrupts ............................................................................................... 24
9 ADDITIONAL INFORMATION ....................................................................................... 26
MCU-AN-300215-E-V12
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© Fujitsu Microelectronics Europe GmbH
A/D CONVERTER
Contents
LIST OF FIGURES ............................................................................................................. 27
LIST OF TABLES............................................................................................................... 28
© Fujitsu Microelectronics Europe GmbH
-5-
MCU-AN-300215-E-V12
A/D CONVERTER
Chapter 1 Introduction
1 Introduction
This application note describes the functionality of the Analog/Digital Converter (ADC) and
gives some examples.
1.1
Key Features
•
Minimum conversion time per Channel: 1.7 Hs at 20 MHz of CLKP1 (for 4.5V J AVCC
J 5.5V)
•
8-bit or 10-bit conversion resolution
•
Sequential channel conversion, once (Single Mode), continuous (Continuous Mode)
and converts one channel, stops and waits for the next activation (Stop Mode)
•
Interrupt generation after conversion selectable
•
Interrupt can trigger DMA to transfer conversion result to memory
•
Triggered by software, external Pin (ADTG) or Reload Timer 1
MCU-AN-300215-E-V12
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© Fujitsu Microelectronics Europe GmbH
A/D CONVERTER
Chapter 2 The Analogue/Digital Converter
2 The Analogue/Digital Converter
THE BASIC FUNCTIONALITY OF THE ANALOGUE/DIGITAL CONVERTER
2.1
Block Diagram
Figure 2-1 shows the internal block diagram of the ADC.
Figure 2-1: ADC Block Diagram
x is last/highest ADC channel available on the particular device.
© Fujitsu Microelectronics Europe GmbH
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MCU-AN-300215-E-V12
A/D CONVERTER
Chapter 2 The Analogue/Digital Converter
2.2
Registers
2.2.1 Control Status Register (ADCS)
This register controls the A/D converter and indicates its status.
Bit
No.
15
Initial
Value
Name
Explanation
BUSY*
Busy Flag and
Stop*
0
Interrupt Flag*
0
Value
10-Bit Mode
0
0
1
Read: No A/D Conversion
Write: Force Conversion Stop
Read: A/D Conversion ongoing
Write: No effect
Read: No A/D Data
Write: Clear Flag
Read: A/D Data and Interrupt
Write: No effect
Interrupt disabled
Interrupt, if A/D Data
Read: No A/D Conversion Pause
Write: Clear Bit
Read: Pause occurred
Write: No effect
ADC Activation by Software
ADC Activation by Software and
ADTG Pin
ADC Activation by Software and
Timer
ADC Activation by Software, ADTG
Pin, and Timer
Always read; Write: no effect
Start and Restart A/D Conversion
Reserved Bit , always write “0” to it
Single Mode 1; Reactivation during
Conversion allowed
Single Mode 2; Reactivation during
Conversion not allowed
Continuous Mode; Reactivation
during Conversion not allowed
Stop Mode; Reactivation during
Conversion not allowed
10-Bit Conversion Mode
8-Bit Conversion Mode
-
Undefined
X
0
Reserved Bit , always write “0” to it
-
Reserved
0
0
Reserved Bit , always write “0” to it
0
1
0
14
INT*
1
13
INTE
Interrupt
enable
0
12
PAUS
A/D Converter
Pause
0
0
1
0
1
0, 0
0, 1
11, 10
STS1,0 Start Source
Select
0, 0
1, 0
1, 1
9
STRT
8
-
Start
Conversion
Undefined
0
1
0
0
X
0, 0
7, 6
Operation
MD1, 0
Mode Select
0, 1
0, 0
1, 0
1, 1
5
4
…
1
0
Operation
S10
Table 2-1: ADCS
* These bits return “1” during Read-Modify-Write instruction.
MCU-AN-300215-E-V12
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© Fujitsu Microelectronics Europe GmbH
A/D CONVERTER
Chapter 2 The Analogue/Digital Converter
2.2.2 Date Register (ADCR)
This register stores digital value generated as a result of conversion. This register contains
the last converted value and is rewritten every time the conversion ends.
Bit No.
15
…
10
9
…
0
Name
D9
…
D0
Explanation
Value
Operation
-
0
These bits always return “0”
Data Bits
-
These bits contain A/D data after
successful conversion
Table 2-2: ADCR
2.2.3 Setting Register (ADSR)
This registers sets the sampling and conversion time, also sets the starting and ending
channel for conversion.
Bit
No.
Name
Explanation
Initial
Value
15
…
13
ST2
…
ST0
Sampling
Time Setting
0, 0, 0
12
…
10
CT2
…
CT0
Compare
Time Setting
0, 0, 0
Value
0,
0,
0,
0,
1,
1,
1,
1,
0,
0,
0,
0,
1,
1,
1,
1,
0,
0,
1,
1,
0,
0,
1,
1,
0,
0,
1,
1,
0,
0,
1,
1,
Operation
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0, 0, 0
9
…
5
ANS4
…
ANS0
Starting
Channel
Setting
0, 0, 1
0, 0, 0
0, 1, 0
. . .
1, 1, 1
0, 0, 0
4
…
0
ANE4
…
ANE0
Ending
Channel
Setting
0, 0, 1
0, 0, 0
0, 1, 0
. . .
1, 1, 1
4 peripheral clock cycles
6 peripheral clock cycles
8 peripheral clock cycles
12 peripheral clock cycles
24 peripheral clock cycles
36 peripheral clock cycles
48 peripheral clock cycles
128 peripheral clock cycles
22 peripheral clock cycles
33 peripheral clock cycles
44 peripheral clock cycles
66 peripheral clock cycles
88 peripheral clock cycles
132 peripheral clock cycles
176 peripheral clock cycles
264 peripheral clock cycles
AN0 (ADECR_ADSEL = 0)
AN32 (ADECR_ADSEL = 1)
AN1 (ADECR_ADSEL = 0)
AN33 (ADECR_ADSEL = 1)
AN2 (ADECR_ADSEL = 0)
AN34 (ADECR_ADSEL = 1)
...
AN31 (ADECR_ADSEL = 0)
AN0 (ADECR_ADSEL = 0)
AN32 (ADECR_ADSEL = 1)
AN1 (ADECR_ADSEL = 0)
AN33 (ADECR_ADSEL = 1)
AN2 (ADECR_ADSEL = 0)
AN34 (ADECR_ADSEL = 1)
...
AN31 (ADECR_ADSEL = 0)
Table 2-3: ADSR
Note: Always use word access to write to this register.
© Fujitsu Microelectronics Europe GmbH
-9-
MCU-AN-300215-E-V12
A/D CONVERTER
Chapter 2 The Analogue/Digital Converter
Please refer the datasheet for the highest ADC channel number available on the device.
2.2.3.1 Sampling/Conversion Time
The sampling time must be equal to or greater than 0.5 Hs. The Conversion time must be at
least 1 Hs. Therefore an overall A/D conversion time could be 1.5 Hs, but this depends on
the used peripheral clock.
Assume a peripheral clock of 16 MHz (62.5 ns cycle time). The sample cycle number then
has at least to be 8 (0.5 Hs) and the conversion cycle number can be 22 (1.375 Hs).
Therefore the overall A/D conversion time is 1.875 Hs.
All these settings are valid for 4.5 V J AVCC J 5.5 V. Please see the hardware manual for
external impedance considerations.
Please consider that the sampling/conversion time settings also depend on the settings in
the peripheral Clock 1 divider.
CKFCRH_PC1D[3:0]
CLKS1
Peripheral Clock 1
Divider (div-1 to div-16)
CLKP1
to ADC
Figure 2-2: ADC Clock
2.2.3.2 Start/Stop Channels
•
Use start channel = end channel for conversion of only one channel.
•
If start channel is greater then end channel, conversion starts form start channel to
the highest available channel, then from channel 0 to the end channel. For products
with less than 32 A/D converter channels, the conversion results can be incorrect. To
prevent this, do not set ANS larger than ANE.
•
It is not possible to have a start channel < 32 and an end channel Q 32. If this is
needed, please use the following sequence:
o
Set ADECR:ADSEL = 0 to convert channels from required start channel to
channel 31.
o
Set ADECR:ADSEL = 1 and convert channel 32 to the required end channel.
MCU-AN-300215-E-V12
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© Fujitsu Microelectronics Europe GmbH
A/D CONVERTER
Chapter 2 The Analogue/Digital Converter
2.2.4 ADC Extended Configuration Register (ADECR)
If there are more than 32 ADC channels available, the ADECR switches between upper and
lower ADC channel set. The deselected set cannot be accessed then. It also selects A/D
converter’s high and low reference voltage, if available.
Bit
No.
7
…
3
2, 1
Name
Explanation
Initial
Value
Value
-
Reserved Bits
X
0
LSEL,HSEL Reference
Voltage
ADSEL
0
Read value is undefined; Write
“0” to these Bits.
Low reference
voltage
AVRL/AVRH2
AVSS
0,0
0,1
1,0
1,1
0
1
0,0
ADC Channel
Set Select
Operation
0
High reference
voltage
AVRH
AVRH
AVSS
AVRH
AVSS
AVRL/AVRH2
Select ADC Channels 0 - 31
Select ADC Channels Q 32
Table 2-4: ADECR
It should be noted that the reference voltage switch is available on selected devices. In the
devices where the reference voltage switch is unavailable, bits LSEL and HSEL are
unavailable and high reference voltage pin is AVRH and low voltage reference pin is AVSS
always.
2.2.5 Analog Input Enable Register (ADER0 – ADERn)
The ADER0 - ADERn selects whether a corresponding pin is used as an analog input or a
digital I/O channel. The following formula shows the relation between total number of ADC
channels and the highest ADER register:
n=
x
1
8
where, x is the total number of ADC channels available on the device
n is the highest ADER register
The following table shows ADER0.
Bit
No.
7
…
0
Name
Explanation
ADE7
…
ADE0
ADC Input
Selection
Initial
Value
0
Value
Operation
0
Digital I/O Port enabled
Analog Input enabled
1
Table 2-5: ADER0
The following table shows ADER1.
Bit
No.
7
…
0
Name
Explanation
ADE15
…
ADE8
ADC Input
Selection
Initial
Value
0
Value
Operation
0
Digital I/O Port enabled
Analog Input enabled
1
Table 2-6: ADER1
© Fujitsu Microelectronics Europe GmbH
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MCU-AN-300215-E-V12
A/D CONVERTER
Chapter 2 The Analogue/Digital Converter
The following table shows ADERn.
Bit
No.
7
…
0
Name
ADE(X-1)
…
ADE(X-8)
Explanation
ADC Input
Selection
Initial
Value
0
Value
Operation
0
Digital I/O Port enabled
1
Analog Input enabled
Table 2-7: ADERx
Hence if total number of ADC channels available on a particular device is 24 then the
highest ADER register is ADER2 and bits of the same would be ADE16 to ADE23.
MCU-AN-300215-E-V12
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© Fujitsu Microelectronics Europe GmbH
A/D CONVERTER
Chapter 3 Power supply of A/D converter
3 Power supply of A/D converter
ELECTRICAL POWER CONSIDERATIONS
3.1
Power consumption
The power consumption (IR, IA) of the ADC increases in case a conversion is in progress
(ADCSH_BUSY = 1). While the ADC is halted (ADCSH_BUSY = 0), only leakage current (IRH,
IAH) flows. The following diagrams reflect this behaviour:
ADCSH_BUSY
[Bit-value]
1
ADCSH_BUSY=1
0
t
Reference Voltage Current
[mA]
(AVRH, AVRL)
IR
IRH
t
Power Supply Current
[mA] AVCC
IA
IAH
t
Figure 3-1: Power consumption and operating status of ADC
Note:
Please refer to the datasheet in order to get the absolute values of IR, IRH, IA and IAH.
3.2
Noise consideration
Fujitsu microcontroller has implemented an embedded 10-bit Successive Approximated
Register (SAR) ADC. Due to the high resolution, the digital bit stream from the ADC output is
sensitive to the environment noise. For example, 1LSB corresponds to only 4.9mV for
UREF=5V. Hence, the noise introduced from the external circuits must be considered and
should be reduced to the minimum as possible.
© Fujitsu Microelectronics Europe GmbH
- 13 -
MCU-AN-300215-E-V12
A/D CONVERTER
Chapter 3 Power supply of A/D converter
The reference voltage UREF, which is equal to AVRH-AVRL (depends on ADECR setting if
reference voltage switch is available), is connected to the weighted capacitor array and the
resistor array of the ADC. The noise coupled to AVR will not be rejected by ADC. This noise
will be added to the UREF directly, introducing an error with a ratio of UNoise/UREF. For
example, to keep the error caused by this kind of noise below 0.1LSB, the noise level of UREF
must be kept within 0.49mV.
As a result, the pin AVRH and AVRL pins must be connected with low impedance. In
practice often a simple low-pass RC-filter is used for noise reduction. In this case the
reference voltage supply current (see datasheet) has to be taken into account when
calculating the resistor of the filter, in order to minimize the voltage drop while converting.
Normally two capacitors in parallel are recommended, one filtering low frequency noise, the
other one filtering high frequency noise ((10nF–1µF)||(10pF-100pF)). In most cases, this
configuration suppresses the noise efficiently. If very high frequency noise appears in the
environment, an additional noise filter such as a dedicated mode RC filter might be useful.
The analogue power path AVCC supplies the internal voltage comparator and the analogue
switches of the ADC, while the VCC path supplies all the digital parts in the microcontroller.
Internal parasitic capacitors may couple noise from AVCC to the internal voltage comparator
of the ADC. For this reason, also AVCC should not be connected directly to VCC but filter
should be used, too. For more efficient noise filtering the same configuration as for AVRH is
recommended.
VCC
+5
VSS
AVCC
AVRH
10 G
10pF 100pF
10nF
10pF 100pF
10nF
1uF
10pF 100pF
10nF
1uF
1uF
Reference
Voltage
µC
AVRL
Reference
Voltage
AVSS
Figure 3-2: A suggested connection for the power supplies
MCU-AN-300215-E-V12
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© Fujitsu Microelectronics Europe GmbH
A/D CONVERTER
Chapter 4 Analogue input and related external circuits
4 Analogue input and related external circuits
4.1
External circuits for analogue input
Usignal
AVCC
~
Dclamp
R1
Rclamp
R2
AN x
Cnoise
µC
Dclamp
Figure 4-1: A typical external circuit for analogue input
To protect the analogue pins to suffer from an over-voltage, the so-called “clamping resistor”
is usually added to the input pins. The minimum value of the resistor can be chosen as
Rclamp= Uovervoltage/Iclamp,
Where, Iclamp is the specified maximum clamp current in the data sheet.
For some applications, a large clamp resistor is sometimes unacceptable. As a compromise,
an external clamping diode with low leakage current could be added between the input pin
and AVCC pin.
In some cases, the sensor has been biased with a voltage supply higher than the maximum
allowed voltage for the microcontroller. For example, in the automotive applications, the
sensors could be biased directly with the car battery, which exhibits a voltage of 12V/24V. A
resistor divider consisting of R1/R2 is commonly used to tail the sensor voltage signal “seen”
on the pin down to the value which is equal or smaller than AVCC/VCC (see Figure 4-1).
The ratio between R1 and R2 should satisfy the following constrain:
R1
R2
U Signal
AVCC
1
Other factor which influences the size dimension of R1, R2 and Rclamp, is related to current
consumption budget and the input signal noise suppressing. The second factor will be
discussed here with more detail. The signal from the sensors could be also noisy. The noise,
which has a time constant smaller than the sampling time Tsampling, is transparent to the ADC,
resulting distorted output. In this case, an additional dedicated bypass capacitor together
with the clamping resistor or resistor divider, works as a low pass filter. A larger capacitor will
lower the AC impedance and will be more effective at shunt away the noise signal.
Generally, the time constant of this low pass filter (Rclamp + R1 || R2) x Cnoise should be chosen
considerably larger than the sampling time (5 to 10 times larger with a rule of thumb).
However, at the same time this time constant should be also considerably smaller than the
one of the sensor signal, depending on the applications. In this way, the analogue pin is able
to follow the dynamic changes, which the ADC is being used to track. These, along with the
dimension of R1/R2 or Rclamp must be considered when choosing the capacitor dimension to
avoid rolling off any high frequency signal components of interest.
© Fujitsu Microelectronics Europe GmbH
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MCU-AN-300215-E-V12
A/D CONVERTER
Chapter 4 Analogue input and related external circuits
4.2
Input Leakage current consideration
The analogue input pins show a small leakage current, whose maximum value is about 3µA
and ranged from 3µA down to 1µA depending on the temperature. The leakage current,
which flows through the external resistor, introduces an undesired voltage drop. This error
voltage is a function of the external resistor and the leakage current itself. The following
example shows a dimension of the resistor with this factor taken into consideration. For the
case of using a resistor divider to reduce the error due to leakage current, the size of R1 || R2
+ Rclamp should not be chosen too large and should be according to the following equation:
R1 || R2 + Rclamp
U LSB
I leakage
Note:
ULSB = UREF / 1024
To keep the error smaller than one LSB for a leakage of 3µA, the size of R1 || R2 + Rclamp
should be smaller than 1.6k . As the leakage current drops down to 1 µA, the value of R1 ||
R2 + Rclamp can be chosen as large as 5k . This is considering UREF of 5V.
It is found in the test that the leakage current consists of two parts: one is due to the leakage
current of the input ESD structure. Another leakage current appears only as the multiplexer
is switched on during the sampling time, whose contribution is usually considerably larger
than the one created from ESD structure. The second leakage current can be regarded as a
noise during the sampling time by the bypass capacitor, which is commonly used to filter the
noise from the sensor input. If this capacitor is large enough, it can absorb most of the
second leakage current during the sampling time, eliminating its contribution to the error
voltage.
VCC
Ileakage2 appears after switches
ESD
Ileakage1
Usignal
Cnoise
~
Ileakage2
MUX
Reff
Cbypass
within the MUX turn on
Csampling
ESD
µC
Figure 4-2: Leakage current flowing to the analogue input pin
MCU-AN-300215-E-V12
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© Fujitsu Microelectronics Europe GmbH
A/D CONVERTER
Chapter 4 Analogue input and related external circuits
Leakage
current
Ileakage1+Ileakage2
Ileakage1
Ileakage1
t
Error voltage due to leakage current
without the bypass capacitor
Error
voltage
Error voltage due to leakage current
with the bypass capacitor
t
No active
phase
Sampling
phase
Comparison
phase
Figure 4-3: Reducing the leakage current with the bypass capacitor
To show the effect of the bypass capacitor on reducing the leakage current error, we take a
sampling time of 5µs and a leakage current of 3µA as an example. If we want to keep the
voltage drop due to the second leakage current small than 0.5 LSB, the minimum size of the
bypass capacitor should be chosen as:
C=
© Fujitsu Microelectronics Europe GmbH
3µA × 5µs
4.9mV / 2
- 17 -
6nF
MCU-AN-300215-E-V12
A/D CONVERTER
Chapter 5 Sampling time consideration
5 Sampling time consideration
SAMPLING TIME CONSIDERATION
Fujitsu applies an embedded 10-bit successive approximation register ADC with an internal
integrated sampling and hold stage. The signal will charge the sampling capacitor at first and
then the voltage signal on the sampling capacitor will be evaluated by the 10-bit ADC
successively. The time to charge the sampling capacitor to its final value equal to the signal
level is a function of the sampling capacitor Csampling, the external resistor and the internal
switch on-resistor.
To reduce the error caused by the limited sampling time to an acceptable level, the sampling
time should be chosen much larger than the time constant to charge the sampling capacitor.
For example, if we choose a sampling time with a factor 7 of the RC constant, namely,
7 × ( Rextern + Rswitch ) × Csampling . Then the error amounts to e 7 × U REF , corresponding
0.94 × U LSB only.
For MB96340 Series, the on-resistor of the transmission gate amounts to 2.25k and the
sampling capacitor Csampling equals to 10.7pF at AVCC = 5V. For an external resistor of
2.25k ,
the
sampling
time
should
be
chosen
larger
than
7 × (2.25k + 2.25k ) × 10.7 pF = 0.38µs by using above thumb rule.
Rswitch=2.25k
(max.)
Usampling
Rextern
COMP
Sequential
Comparison
Register
~
Usignal
Csampling=10.7pF (max.)
µC
Figure 5-1: Block diagram for ADC in MB96340 Series
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A/D CONVERTER
Chapter 5 Sampling time consideration
Usampling
Error<[email protected] time=7
Usignal
Sampling time
7
Figure 5-2: Error related to sampling time
For the Fujitsu microcontroller the sampling time can be set by defining the register bit ST2
to ST0 of the ADC data register (ADCRH). Please refer to the hardware manual.
Please also refer Chapter 7: Input Impedance.
© Fujitsu Microelectronics Europe GmbH
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Chapter 6 Latch-up related to AVCC/VCC and large input signal
6 Latch-up related to AVCC/VCC and large input signal
RECOMMENDATIONS TO PREVENT LATCH-UP
Latch-up conditions can permanently damage the device and must be avoided. It is up to the
application to assign any precautions in order to avoid any latch-up condition.
6.1
AVCC > VCC
VCC
ESD D3
1
µC
AVCC
ESD
VSS
Figure 6-1: Latch-up in case AVCC > VCC
Latch-up can happen if AVCC becomes larger than VCC. This might be related to the
application cases that VCC is switched on later than AVCC or VCC is switched off earlier than
AVCC. The ESD diode D3 becomes forward biased, introducing a possible latch-up.
6.2
AVCC < VCC
PMOS
VCC
VCC
D1
Digital
Control
Transmission gate
VSS
VSS
To ADC
AVSS
AVCC
D2
2
Figure 6-2: Latch-up in case AVCC < VCC
This case happens if the analogue pin is used as a digital output pin, the output level is “H”,
and at the same time, AVCC is switched off. In this case, the PMOS in the output is on and
the parasitic diode D2 of the transmission gate within the analogue multiplex becomes
forward biased. A quiescent current flows through PMOS and D2. In case that a latch-up
does not happen, a reliable logic “1” should not be expected at the output, due to the load
diode D2.
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A/D CONVERTER
Chapter 6 Latch-up related to AVCC/VCC and large input signal
6.3
UAIN > AVCC or VCC
PMOS
VCC
D1
Digital
Control
3
UAIN
Transmission gate
VSS
To ADC
AVSS
AVCC
D2
3
Figure 6-3: Problem in case UAIN > AVCC or VCC
If UAIN becomes larger than VCC or AVCC, then the ESD diode D1 or D2 will be forward
biased. A latch-up can happen. Even if a latch-up does not always happen in this case, the
input signal, which exceeds VCC or AVCC, cannot be converted by the ADC properly.
6.4
Conclusion
It is strongly suggested that AVCC and VCC should be DC short circuit together to avoid any
possible latch-up.
With the presence of AVCC and VCC voltage, an analogue input signal, which is smaller than
AVCC and VCC can be always put on the analogue pins, independent on the MCU modes.
Latch-up conditions can permanently damage the device if the related specified
currents are exceeded. So Latch-up conditions must be avoided under all
circumstances. It is up to the application to assign any precautions in order to avoid
any latch-up condition.
© Fujitsu Microelectronics Europe GmbH
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Chapter 7 Input Impedance
7 Input Impedance
ADC BEHAVIOR ON HIGH INPUT IMPEDANCES
7.1
Recharging and discharging the Sampling capacitor
Because the ADC uses a sampling capacitor the input impedance must be set to a value
below 15 k to recharge or discharge this capacitor within the sampling time.
Example:
Assume an application uses two ADC inputs. At one pin there is a voltage of about Vcc and
at the other pin Vss. The first conversion charges the internal capacitor to Vcc within the
sample time (A). After this the conversion starts (B). At the second conversion the MUX
switches to the other input and the capacitor is discharged to Vss (C). The second
conversion starts (D). If the input impedance (Z0) is too high, a rest of charge will remain and
a wrong conversion will result.
Figure 7-1: Current flow in the example
The left illustration shows the voltage glitch on AN0 if Z0 is
low.
The glitch occurs, when the sampling switch is closed.
Figure 7-2: Voltage glitch at low input impedance
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A/D CONVERTER
Chapter 7 Input Impedance
In this illustration the input impedance Z0 is too high. The
sampling capacitor is not discharged within the sampling
time and thus a wrong voltage is converted (red circle).
Figure 7-3: Voltage glitch at high input impedance
Note:
At high impedance input circuit, there will always be a glitch of about 0.5 Volts max even if
the previous conversion was at 0 Volt. This results from the ADC internal architecture itself.
For the same reason discussed in this chapter an EMI capacitors for any analogue input pins
should not exceed 1 nF.
© Fujitsu Microelectronics Europe GmbH
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Chapter 8 ADC Example
8 ADC Example
EXAMPLES FOR THE ADC
8.1
ADC with interrupts
Main.c
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
void InitADC (void)
{
ADER0 = 0x02;
/* channel 1 to analog input
*/
ADCSL = 0xA0;
/* ADC set to 8 bit continuous mode
*/
ADSR = 0xFC21;
/* ADSRL + ADSRH, Sampling time – 128 CLKP1 Cycles,
Conversion time – 264 CLKP1 Cycles, convert only
AN1 */
ADCSH = 0xA2;
/* interrupt enabled, software trigger,
start conversion */
}
void main (void)
{
DDR00 = 0xFF ;
InitIrqLevels();
__set_il(7);
__EI();
InitADC();
/* Data direction Port 0 = Output
*/
/* allow all levels
/* globally enable interrupts
*/
*/
/* init AD - converter
*/
while(1)
/* waiting for interrupt (no operation)
__asm("\tnop");
*/
}
__interrupt void ISR_ADC (void)
{
PDR00 = ADCRL;
/* shows voltage on Port 0 ( LEDs )
ADCSH = 0xA2;
/* clear interrupt flag
}
*/
*/
The above example demonstrates to configure ADC in the continuous mode with 8 bit
conversion resolution with interrupts enabled. The maximum possible sampling and
conversion time is used here. After every ADC interrupt the converted data is output to the
LEDs connected to Port 0.
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A/D CONVERTER
Chapter 8 ADC Example
vectors.c
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
void InitIrqLevels (void)
{
. . .
ICR = (76 << 8) | 6;
/* Priority Level 6 for ADC of MB96340 Series */
. . .
}
/* ISR prototype */
__interrupt void ISR_ADC (void);
. . .
#pragma intvect ISR_ADC 76
. . .
© Fujitsu Microelectronics Europe GmbH
/* ADC of MB96340 Series */
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Chapter 9 Additional Information
9 Additional Information
Information about FUJITSU Microcontrollers can be found on the following Internet page:
http://mcu.emea.fujitsu.com/
The software examples related to this application note is:
96340_adc
96340_adc_rlt
96340_adc_dma
96340_ppg16_rlt_adc_dma
It can be found on the following Internet page:
http://mcu.emea.fujitsu.com/mcu_product/mcu_all_software.htm
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List of Figures
List of Figures
Figure 2-1: ADC Block Diagram ............................................................................................. 7
Figure 2-1: ADC Clock ......................................................................................................... 10
Figure 3-1: Power consumption and operating status of ADC .............................................. 13
Figure 3-2: A suggested connection for the power supplies ................................................. 14
Figure 4-1: A typical external circuit for analogue input ........................................................ 15
Figure 4-2: Leakage current flowing to the analogue input pin ............................................. 16
Figure 4-3: Reducing the leakage current with the bypass capacitor.................................... 17
Figure 5-1: Block diagram for ADC in MB96F340................................................................. 18
Figure 5-2: Error related to sampling time ............................................................................ 19
Figure 6-1: Latch-up in case AVCC > VCC .............................................................................. 20
Figure 6-2: Latch-up in case AVCC < VCC .............................................................................. 20
Figure 6-3: Problem in case UAIN > AVCC or VCC .................................................................. 21
Figure 7-1: Current flow in the example ............................................................................... 22
Figure 7-2: Voltage glitch at low input impedance ................................................................ 22
Figure 7-3: Voltage glitch at high input impedance............................................................... 23
© Fujitsu Microelectronics Europe GmbH
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List of Tables
List of Tables
Table 2-1: ADCS ..................................................................................................................... 8
Table 2-2: ADCR ..................................................................................................................... 9
Table 2-3: ADSR ..................................................................................................................... 9
Table 2-4: ADECR ................................................................................................................. 11
Table 2-5: ADER0 ................................................................................................................. 11
Table 2-1: ADER1 ................................................................................................................. 11
Table 2-1: ADERx ................................................................................................................. 12
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