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Application Note
MCU-AN-300220-E-V15
F²MC-16FX FAMILY
16-BIT MICROCONTROLLER
ALL SERIES
DIRECT MEMORY ACCESS
APPLICATION NOTE
DIRECT MEMORY ACCESS
Revision History
Revision History
Date
2006-07-24
2007-03-23
2007-08-14
2010-02-22
2010-02-25
2013-09-05
Issue
First Version; MWi
V1.1, Reviewed the document and updated with review findings, MPi
V1.2, Updated with review findings from PHu, MPi
V1.3, UART TX DMA reference to other application note added; MWi
V1.4, DCT remarks added, conditions for DMA request added; MWi
V1.5, page 12, ADC IRQ number corrected; HWe
This document contains 18 pages.
MCU-AN-300220-E-V15
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© Spansion International Inc.
DIRECT MEMORY ACCESS
Warranty and Disclaimer
Warranty and Disclaimer
Copyright (C) 2013 Spansion LLC. All Rights Reserved.
This software is owned and published by:
Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion").
BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE
BOUND BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
This software contains source code for use with Spansion components. This software is
licensed by Spansion to be adapted only for use in systems utilizing Spansion components.
Spansion shall not be responsible for misuse or illegal use of this software for devices not
supported herein. Spansion is providing this software "AS IS" and will not be responsible for
issues arising from incorrect user implementation of the software.
SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR
OTHERWISE, REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING
WRITTEN MATERIALS),ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED
USE, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTY OF
MERCHANTABILITY, THE IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR
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SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING,
WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
ARISING FROM USE OR INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT
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This software may be replicated in part or whole for the licensed use, with the restriction that
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whether used in part or whole, at all times.
© Spansion International Inc.
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MCU-AN-300220-E-V15
DIRECT MEMORY ACCESS
Contents
Contents
REVISION HISTORY ............................................................................................................ 2
WARRANTY AND DISCLAIMER ......................................................................................... 3
CONTENTS .......................................................................................................................... 4
1 INTRODUCTION .............................................................................................................. 5
1.1
Key Features ........................................................................................................... 5
2 DIRECT MEMORY ACCESS ........................................................................................... 6
2.1
2.2
Outline..................................................................................................................... 6
2.1.1
Single Transfer .......................................................................................... 6
2.1.2
Multiple Transfers ...................................................................................... 7
Registers ................................................................................................................. 8
2.2.1
DMA Interrupt Request Select Register (DISELn) ..................................... 8
2.2.2
DMA Status Register (DSRL/H) ................................................................. 8
2.2.3
DMA Enable Register (DERL/H) ................................................................ 9
2.2.4
DMA Stop Status Register (DSSRL/H) ....................................................... 9
2.2.5
DMA Descriptor ......................................................................................... 9
2.2.5.1
Data Count Register (DCTL/H) ................................................ 10
2.2.5.2
I/O Register Address Pointer (IOAL/H) ................................... 10
2.2.5.3
DMA Control Register (DMACS) ................................................ 11
2.2.5.4
Buffer Address Pointer (BAPL/M/H)......................................... 11
3 DMA EXAMPLES .......................................................................................................... 12
3.1
DMA Example with ADC........................................................................................ 12
3.2
DMA Example with UART ..................................................................................... 14
4 ADDITIONAL INFORMATION ....................................................................................... 16
LIST OF FIGURES ............................................................................................................. 17
LIST OF TABLES ............................................................................................................... 18
MCU-AN-300220-E-V15
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© Spansion International Inc.
DIRECT MEMORY ACCESS
Chapter 1 Introduction
1 Introduction
This application note describes the functionality of the Direct Memory Access (DMA) module
and gives some examples.
The DMA is mainly used to transfer data between a source and a destination memory
location without any CPU load. The direction can be from resource (peripheral) to memory
and vice versa. This transfer can be a single transfer or multiple transfers from single
address or an address area. DMA is always triggered by a resource interrupt and does not
interrupt the CPU until the transfer has ended.
1.1
Key Features
•
8 bit or 16 bit Transfer
•
Transfer from resource (registers in bank 0x00) to complete address Area (24 bit)
and vice versa
•
Single Transfer or Multiple Transfers with possibility of update (increment or
decrement) of source and destination address
•
DMA can be stopped by STOP request (supported by UART-Receive interrupt, in
case of receive error)
It should be noted that the DMA should only be used with such peripheral those interrupts
can be cleared by DMA. The same is indicated by “Yes” in the “DMA can clear” column in
the interrupt vector table in the datasheet.
© Spansion International Inc.
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MCU-AN-300220-E-V15
DIRECT MEMORY ACCESS
Chapter 2 Direct Memory Access
2 Direct Memory Access
THE BASIC FUNCTIONALITY OF THE DMA MODULE
2.1
Outline
The DMA module is used to transfer data from one address (space) to another without
involving the CPU. The address space includes RAM, ROM or resource registers.
Three conditions must be fulfilled before a DMA request is served:
-
IRQ must match with a DMA channel configuration
-
The channel which matches must be enabled
-
The DTE (Data Transfer End) bit of the matching channel must be zero
2.1.1 Single Transfer
The following diagram shows a standard interrupt sequence and a single transfer DMA
sequence:
Standard Interrupt Sequence
CPU Task
DMA Sequence
CPU Task
DMA Task
Interrupt occurs
Application
Application
Interrupt occurs
DMA Transfer
Application
Interrupt
Service Routine
End of DMA interrupts Application
Application
Interrupt
Service Routine
Application
Figure 2-1: Single Transfer
For a single transfer the DMA does not offer a real advantage against a standard interrupt.
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© Spansion International Inc.
DIRECT MEMORY ACCESS
Chapter 2 Direct Memory Access
2.1.2 Multiple Transfers
The following diagram shows a standard interrupt sequence and a multiple transfer DMA
sequence:
Standard Interrupt Sequence
CPU Task
DMA Sequence
CPU Task
Application
Application
DMA Task
Interrupt occurs
Interrupt occurs
Interrupt
Service Routine
Application
Application
DMA Transfer 3
Interrupt occurs
Interrupt occurs
Interrupt
Service Routine
Application
Application
DMA Transfer 2
Interrupt occurs
Interrupt occurs
Interrupt
Service Routine
Application
DMA Transfer 1
End of DMA interrupts Application
Application
Interrupt
Service Routine
Application
Figure 2-2: Multiple Transfers
For a multiple transfer the DMA advantage is obvious. During Transfer 3 and 2 the
application is not interrupted as in the standard interrupt sequence. Only after the Transfer 1,
the interrupt service routine of the resource which is generating the interrupts is executed.
However, it should be also noted that the DMA shares the same bus as of CPU, hence
during the time DMA is engaged in the data transfer the CPU is either waiting for the DMA to
finish the transfer or it is executing the code from the pre-fetch queue.
© Spansion International Inc.
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DIRECT MEMORY ACCESS
Chapter 2 Direct Memory Access
2.2
Registers
2.2.1 DMA Interrupt Request Select Register (DISELn)
This register specifies the IRQ number of the corresponding peripheral that is used to trigger
DMA transfer on the specific channel.
Bit
No.
7
I
4
Name
IS7
…
IS4
IS3,
IS2
IS1,
IS0
3, 2
1, 0
Explanation
Initial
Value
Value
0
-
1
-
0
-
Interrupt Number
for Channel 0 –15
Operation
Assigns Interrupt Number to DMA
Channel
Table 2-1: DISELn
It is recommended to maintain all unused DISEL registers to 0x0C, if DMA is used.
2.2.2 DMA Status Register (DSRL/H)
This 16 bit register contains the DMA transfer end interrupt request flags for each of the
DMA channel. That means the bit 0 is corresponding to the request flag for DMA channel 0
and bit 15 is corresponding to the request flag for DMA channel 15.
Bit
No.
Name
Explanation
15
I
0
DTE15
…
DTE0
Data Transfer End
Interrupt
(Channel 0 – 15)
Initial
Value
Value
0
0
1
Operation
Read: No Interrupt for Channel n
Write: Clear Bit
DMA transfer is completed or
stopped for Channel n
Table 2-2: DSRL/H
Caution:
For cyclic interrupts such as ADC interrupts, it is not enough to clear the
corresponding DTE bit for ending the DMA transfer (Condition described in 2.1 is
fulfilled again)!
To end the DMA transfer please also disable the interrupts of the resource itself.
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© Spansion International Inc.
DIRECT MEMORY ACCESS
Chapter 2 Direct Memory Access
2.2.3 DMA Enable Register (DERL/H)
This 16 bit register contains the DMA enable bits for each of the DMA channel. That means
the bit 0 is corresponding DMA channel 0 and bit 15 is corresponding to DMA channel 15.
Bit
No.
Name
15
I
0
EN15
…
EN0
Initial
Value
Explanation
DMA Enable
(Channel 0 – 15)
Operation
Value
0
0
1
No DMA. Resource Interrupts are
enabled
Resource Interrupts are passed to
the DMA controller until last transfer
Table 2-3: DERL/H
2.2.4 DMA Stop Status Register (DSSRL/H)
This 16 bit register contains the DMA Stop status flags for each of the DMA channel. That
means the bit 0 is corresponding DMA channel 0 and bit 15 is corresponding to DMA
channel 15.
Bit
No.
15
I
0
Name
STP15
…
STP0
Initial
Value
Explanation
0
Data Stop Status
(Channel 0 – 15)
Operation
Value
0
1
Read: No Stop request occurred for
channel n
Write: Clear Bit
DMA transfer is stopped due to
Stop request issued by resource
peripheral for Channel n
Table 2-4: DSSRL/H
The DMA Stop request feature is only provided by the UART Receive interrupt. If the SE bit
of DMACS register of the corresponding DMA channel is set and if there is an error while the
UART reception, then the ongoing DMA transfer would be stopped and the STPx bit for the
corresponding DMA channel will be set.
2.2.5 DMA Descriptor
Each of the DMA channels has an 8 byte descriptor. The following table shows the structure
of a single descriptor:
Address
0x00107 + 8
0x00106 + 8
0x00105 + 8
0x00104 + 8
0x00103 + 8
0x00102 + 8
0x00101 + 8
0x00100 + 8
*
*
*
*
*
*
*
*
ch
ch
ch
ch
ch
ch
ch
ch
Descriptor Register
Upper 8 Bits of Data Counter (DCTH)
Lower 8 Bits of Data Counter (DCTL)
Upper 8 Bits of I/O Register Address Pointer (IOAH)
Lower 8 Bits of I/O Register Address Pointer (IOAL)
DMA Control Register (DMACS)
Upper 8 Bits of Buffer Address Pointer (BAPH)
Middle 8 Bits of Buffer Address Pointer (BAPM)
Lower 8 Bits of Buffer Address Pointer (BAPL)
Table 2-5: DMA Descriptor
In the above table the value of ch can be between 0 to Number of DMA channels-1.
Note that all the DMA descriptor registers have undefined initial values and are read and
writeable.
© Spansion International Inc.
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MCU-AN-300220-E-V15
DIRECT MEMORY ACCESS
Chapter 2 Direct Memory Access
2.2.5.1 Data Count Register (DCTL/H)
This 16 bit register holds the number of data transfers in terms of bytes per DMA. The
decrement value of this register depends on the transfer type and transfer cycles are
dependent on the alignment of the I/O and buffer address.
The following table describes various scenarios for the DMA transfer:
Configuration/Status
BW
0
1
1
1
1
1
0
DCT
IOA
>
>
>
>
>
=
=
Even Even
Even Odd
Odd Even
Odd Odd
-
0
1
1
1
1
1
0
BAP
Transfer Type
I/O
Buffer
Byte
Word
Word
2x Byte
Byte
Byte
Byte
Byte
Word
2x Byte
Word
Byte
Byte
Byte
Post Transfer Update of
IOA
IOA
DCT (DMACS_ (DMACS_
IF = 1) BF = 1)
-1
+1
+/-1
-2
+2
+/-2
-2
+2
+/-2
-2
+2
+/-2
-1
+1
+/-1
-1
+1
+/-1
-1
+1
+/-1
Transfer
Cycles
2
2
3
3
2
2
2 (x 65536)
Table 2-6: Transfer type and descriptors
As shown in the 2nd to last row of the above table, even if the BW bit of DMACS register is
configured for the word transfer, since the DCT is written with a value of 1, a single byte
transfer would be performed.
The last row shows, that for a full 64 KBytes data block to be transferred the DCT should
contain the count value “0” for byte transfer.
Please note that a count value “0” means the maximum of possible DMA transfers
(65535 for byte and 32768 for word) – not “no transfer”!
2.2.5.2 I/O Register Address Pointer (IOAL/H)
This 16 bit register holds the address of the I/O register address. The upper 8 bits (A16-A23)
are “0”. This allows an address space from 0x000000 to 0x00FFFF. The post transfer
update of this register is described in the above Table 2-6.
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© Spansion International Inc.
DIRECT MEMORY ACCESS
Chapter 2 Direct Memory Access
2.2.5.3 DMA Control Register (DMACS)
This register controls the overall DMA transfer functionality.
Bit
No.
15,
14
Name
-
Explanation
Reserved
Initial
Value
Value
X
0
13
BPD
12
IF
11
BW
10
BF
9
DIR
8
SE
Buffer Pointer
Decrement Bit
IOA update/fixed
Selection Bit
Byte/Word
Selection Bit
BAP update/fixed
Selection Bit
Data Transfer
Direction Bit
DMA Stop Request
Enable Bit
X
1
X
X
X
X
1
0
1
0
1
0
1
0
1
0
1
Operation
Reserved. Always write “0”
BAP increments after each transfer,
if BF=0
BAP decrements after each transfer,
if BF=0.
If BPD=BW=1, please set even
values to IOA, BAP, and DCT
IOA increments after each transfer
IOA stays fixed after transfer
Enable Byte Transfer
Enable Word Transfer
BAP is updated after transfer
BAP stays fixed after transfer
Transfer from IOA to BAP address
Transfer from BAP to IOA address
No reaction on Stop Request
DMA is stopped on Stop Request
from resource (UART-Rx)
Table 2-7: DMACS
2.2.5.4 Buffer Address Pointer (BAPL/M/H)
This 24 bit register holds the address of the buffer. The whole memory area can be
accessed.
© Spansion International Inc.
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DIRECT MEMORY ACCESS
Chapter 3 DMA Examples
3 DMA Examples
EXAMPLES FOR DIRECT MEMORY ACCESS
3.1
DMA Example with ADC
The following example code shows how to set up the DMA with the ADC. The ADC converts
channel 0 to 7 and the 8 bit results are transferred via DMA0 to the global array unsigned
char adc_array[8]. After this the ADC interrupt is executed and the transfer is initialized
again.
Main.c
__far unsigned char adc_array[8]; // Declared as __far for 24 bit addressing.
// If declared as __near, BAPHn must be set
// to DATA bank (usually 0x00).
void init_adc(void)
{
ADCS = 0xA020;
// single, 8 bit
ADSR = 0x9007;
// 24 cycle sampling, 88 cycle conversion, channel 0-7
ADER0 = 0xFF;
// enable ADC pins
}
void init_dma(void)
{
DISEL0 = 76;
DCTH0 = 0x00;
DCTL0 = 0x08;
IOAH0 = (unsigned
IOAL0 = (unsigned
DMACS0 = 0x10; //
// ADC interrupt number for MB9634x Series
// 8 Bytes
char) &ADCR >> 8; // I/O Bank 00
char) &ADCR & 0xFF;
no IOA update, BAP increment, byte transfer, IOA -> BAP
BAPH0 = (__far unsigned long) &adc_array >> 16;
BAPM0 = (__far unsigned long) &adc_array >> 8;
BAPL0 = (__far unsigned long) &adc_array & 0xFF;
DSR = 0x0000;
DER = 0x0001;
// Clear transfer end interrupt, if any
// DMA 0 enable
}
void main(void)
{
InitIrqLevels();
__set_il(7);
// allow all levels
init_dma();
init_adc();
__EI();
// globally enable interrupts
ADCS_STRT = 1;
// start ADC
while(1);
// Do nothing: DMA, ADC interrupt do the rest
}
__interrupt void irq_adc(void)
{
ADCS = 0xA020; // Clear ADC interrupt
DSR = 0x0000;
// Clear DMA end request
init_dma();
ADCS_STRT = 1;
// restart ADC
}
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© Spansion International Inc.
DIRECT MEMORY ACCESS
Chapter 3 DMA Examples
Vectors.c
Please note, that the corresponding interrupt vector and level has to be defined in the
vectors.c module of our standard template project.
void InitIrqLevels(void)
{
. . .
ICR = ((76 & 0xFF) << 8) | 6;
// Priority Level 6 for ADC of MB9634x
// Series
. . .
}
__interrupt void irq_adc (void);
// Prototype
. . .
#pragma intvect irq_adc
76
// ADC of MB9634x Series
. . .
Note that this example has no direct result output, but the converted channels can be
observed during runtime with an emulation system and by watching the global array
unsigned char adc_array[8].
© Spansion International Inc.
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MCU-AN-300220-E-V15
DIRECT MEMORY ACCESS
Chapter 3 DMA Examples
3.2
DMA Example with UART
The following example code shows how to configure the DMA with the UART0. If the data is
received on UART0 receive buffer RDR0 then the DMA channel 0 transfers the same data to
the UART0 transmit buffer TDR0. The transfer takes places unless 50 receptions or if there
is any error in the reception. After that the receive interrupt clears DMA transfer end flag and
also disables the reception interrupt.
Main.c
void init_uart0(void)
{
PIER08_IE2 = 1;
DDR08_D2 = 0;
// Enable UART0 RX
// Enable UART0 RX
BGR0 = 1666;
SCR0 = 0x17;
// 9600 baud at 16MHz CLKP1
// 8 bit, clear reception errors, Tx & Rx enabled
ESIR0 = 0x01;
//
//
//
//
SSR0_RIE = 1;
SMR0 = 0x0D;
Disable USART automatic interrupt clear,
Clear TDRE and RDRF flags
Enable receive interrupt
Mode 0, Reset Counter, Reset UART, SOT0 enabled
}
void init_dma(void)
{
unsigned long temp;
DISEL0 = 79;
// UART0 receive interrupt number for MB9634x Series
DCT0 = 0x0032;
// 50 Bytes
IOA0 = (unsigned int)&RDR0;
//Source
temp = (unsigned long)&TDR0;
//Destination
BAPL0 = (unsigned char) temp;
temp >>= 8;
BAPM0 = (unsigned char) temp;
temp >>= 8;
BAPH0 = (unsigned char) temp;
DMACS0 = 0x15;
// no IOA & BAP update, byte transfer, IOA -> BAP, DMA
// Stop request by UART if error in Receive
DSR = 0x0000;
// Clear transfer end interrupt, if any
DER = 0x0001;
// DMA 0 enable
}
void main(void)
{
InitIrqLevels();
__set_il(7);
// allow all levels
init_dma();
init_uart0();
__EI();
// globally enable interrupts
while(1);
// Do nothing: DMA, UART0-Rx interrupt do the rest
}
__interrupt void UART0_RXISR (void)
{
DSR = 0x0000;
// Clear DMA end request
ESIR0_RDRF = 0;
// Clear RDRF flags
SCR0_CRE = 1;
// Clear all error flags
SSR0_RIE = 0;
// Disable reception interrupt
}
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© Spansion International Inc.
DIRECT MEMORY ACCESS
Chapter 3 DMA Examples
Vectors.c
Please note, that the corresponding interrupt vector and level has to be defined in the
vectors.c module of our standard template project.
void InitIrqLevels(void)
{
. . .
ICR = ((79 & 0xFF) << 8) | 6; // Priority Level 6 for UART0-Rx of MB9634x
// Series
. . .
}
__interrupt void UART0_RXISR (void);
// Prototype
. . .
#pragma intvect UART0_RXISR
79
// UART0-Rx of MB9634x Series
. . .
Note:
For usage of consecutive DMA transmission via UART please read the application note:
mcu-an-300205-e-16fx_usart
© Spansion International Inc.
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DIRECT MEMORY ACCESS
Chapter 4 Additional Information
4 Additional Information
Information about SPANSION Microcontrollers can be found on the following Internet page:
http://www.spansion.com
The software examples related to this application note is:
96340_dma_uart0
96340_ppg_rlt_adc_dma
96340_adc_dma
In case of any further question please contact: [email protected]
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© Spansion International Inc.
DIRECT MEMORY ACCESS
List of Figures
List of Figures
Figure 2-1: Single Transfer .................................................................................................... 6
Figure 2-2: Multiple Transfers ................................................................................................ 7
© Spansion International Inc.
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DIRECT MEMORY ACCESS
List of Tables
List of Tables
Table 2-1: DISELn ................................................................................................................. 8
Table 2-2: DSRL/H ................................................................................................................. 8
Table 2-3: DERL/H ................................................................................................................. 9
Table 2-4: DSSRL/H ............................................................................................................... 9
Table 2-5: DMA Descriptor ..................................................................................................... 9
Table 2-6: Transfer type and descriptors .............................................................................. 10
Table 2-7: DMACS ................................................................................................................. 11
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© Spansion International Inc.
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