7.2MB

The following document contains information on Cypress products.
MB9EF226 Series
32-bit Microcontrollers
FCR4 Family
MB9EF226
MB9EF226 Series Cover Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume
such that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.
Publication Number MB9EF226_DS707-00004
Revision 2.1
Issue Date January 30, 2015
Data

Shee t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers
of product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion
data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc.
therefore places the following conditions upon Advance Information content:
"This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice."
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process
that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:
"This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process
that require maintaining efficiency and quality, this document may be revised by subsequent versions
or modifications due to changes in technical specifications."
Combination
Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page
refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify
a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
"This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur."
Questions regarding these document designations may be directed to your local sales office.
2
MB9EF226_DS707-00004-2v1-E, January 30, 2015
MB9EF226 Series
32-bit Microcontrollers
FCR4 Family
MB9EF226
MB9EF226 Series Cover Sheet
DESCRIPTION
MB9EF226 series is based on Spansion advanced ARM architecture (32-bit with instruction pipeline for
RISC-like performance). Improvements compared to the previous generation include significantly improved
performance at higher frequency, reduced power consumption and faster start-up time.
For highest processing speed at optimized power consumption an internal PLL can be selected to supply
the CPU with up to 128MHz operation frequency from an external resonator.
Note: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Thumb and CoreSight are the trademarks of ARM Limited in the EU and other countries.
Spansion provides information facilitating product development via the following website.
The website contains information useful for customers.
http://www.spansion.com/Support/microcontrollers/
®
Publication Number MB9EF226_DS707-00004
Revision 2.1
Issue Date January 30, 2015
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid
combinations offered may occur.
Data
4
Shee t
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
TABLE OF CONTENTS
1 Overview ........................................................................................................................ 7
1.1 Block diagram ....................................................................................................... 7
1.2 Power Domains ..................................................................................................... 8
2 Feature list ..................................................................................................................... 9
2.1
2.2
2.3
2.4
2.5
2.6
Overview ................................................................................................................ 9
Features ............................................................................................................... 10
Memory Map ........................................................................................................ 17
Resource distribution for non-modulated clock .............................................. 24
Lock/unlock values for protection units ........................................................... 24
ID-Values for Module Identification Registers ................................................. 25
3 Package and Pin Assignment .................................................................................... 27
3.1 Package ............................................................................................................... 27
3.1.1 QFP-240 Pin Assignment .......................................................................... 27
3.1.2 QFP-176 Pin Assignment .......................................................................... 31
3.2 I/O Pins and their functions ............................................................................... 34
3.2.1 Port Pin Multiplexing table ........................................................................ 34
3.2.2 Resource input source table ..................................................................... 44
3.3 I/O Pin Types ....................................................................................................... 74
3.3.1 Pin Circuit type of QFP-240 ....................................................................... 74
3.3.2 Pin Circuit type of QFP-176 ....................................................................... 77
3.4 IO Circuit Types .................................................................................................. 79
3.5 Package ............................................................................................................... 84
4 Interrupt / DMA ........................................................................................................... 87
4.1
4.2
4.3
4.4
4.5
Interrupt table ...................................................................................................... 87
NMI ....................................................................................................................... 99
DMA Overview ................................................................................................... 100
PPU .................................................................................................................... 106
Master ID ............................................................................................................ 107
5 I/O map ....................................................................................................................... 109
6 Electrical characteristics .......................................................................................... 313
6.1 Absolute Maximum Ratings ............................................................................. 313
6.2 Recommended operating conditions ............................................................. 320
6.3 DC Characteristics ........................................................................................... 321
6.4 AC Characteristics ............................................................................................ 329
6.4.1 Source Clock timing ................................................................................ 329
6.4.2 Internal Clock timing ................................................................................ 331
6.4.3 External Reset timing .............................................................................. 332
6.4.4 External Input timing ............................................................................... 333
6.4.5 Slew Rate High Current Outputs ............................................................ 334
6.4.6 USART timing ........................................................................................... 335
6.4.7 I2C timing .................................................................................................. 338
January 30, 2015, MB9EF226_DS707-00004-2v1-E
5
Data
Shee t
6.4.8 HSSPI timing ............................................................................................. 340
6.4.9 SPI timing .................................................................................................. 342
6.5 Analog Digital Converter .................................................................................. 347
6.6 FLASH memory program/erase characteristics ............................................ 350
6.7 RC Oscillator Frequency .................................................................................. 351
7 Procedures ................................................................................................................ 353
7.1 Boundary scan .................................................................................................. 353
7.2 Flash Parallel Programming ............................................................................ 356
7.2.1 Memory Map ............................................................................................. 361
7.2.2 Flash macro selection and address mapping in FPP ........................... 364
7.2.3 Flash Power On Sequence ...................................................................... 366
7.3 Debug and Trace ............................................................................................... 368
8 Handling Devices ...................................................................................................... 371
8.1 Preventing Latch-up ......................................................................................... 371
8.2 Handling of unused input pins ........................................................................ 371
8.3 Power supply pins ............................................................................................ 371
8.4 Power on sequence .......................................................................................... 371
8.5 Pin State while Power-On-Reset ..................................................................... 372
8.6 Crystal oscillator circuit ................................................................................... 373
8.7 Notes on using external clock ......................................................................... 373
8.7.1 Opposite phase clock supply: Oscillation Mode .................................. 373
8.7.2 Single phase clock supply ...................................................................... 373
8.7.3 Single phase clock supply: Fast Clock Input Mode .............................. 374
8.8 Unused sub clock signal .................................................................................. 374
9 Ordering Information ................................................................................................ 375
6
MB9EF226_DS707-00004-2v1-E, January 30, 2015
RTC_WOT
SYSC_CKOT
SYSC_CKOTX
RTC
SYSC
Power Control
IRQ Control
TPU
CLK_HPM_PD2
PPU
GPIO
(117 pins)
UDC
(1 ch)
RLT
(10 ch)
GPIOn_mo
GPIOn_mi
CRC
CLK_HPM_PD2
ECC
RetRAM
16K
TCMRAM
128K
MLB
(1 ch)
I2S
(2 ch)
SRAM
64K
Bus Matrix
CLK_GFX_PD5
MLBn_SIGo
MLBn_DATo
MLBn_CLKi
CANn_RX
CANn_TX
SG_SGA
SG_SGO
PPG_ETRG0˘.. PPG_ETRG3
PPGA
PPGB
FRTn_FRCK
ICUn_IN0, ICUn_IN1
OTDn,OTDn_I,OTDn_G,OTDn_GI
SPIn_CLKo
SPIn_DATA[0]o˘. SPIn_DATA[3]o
SPIn_SSo
SPIn_SSO[1]˘. SPIn_SSO[3]
I2Sn_SDo
I2Sn_WSo
I2Sn_SCKo
Trace
CLK_TRACE_PD2
On−chip
Debug
CLK_DBG_PD2
16−bit PPG
(8 ch)
I/O Timer
(4 ch)
FRT 16/17/18/19
ICU 18/19
OCU 16/17
USART
(1 ch)
CAN
(2 ch)
SG
(1 ch)
Peripheral Bus
Bridge 1
MPU
8 ch
D−Cache
8K
I−Cache
8K
16−bit PPG
(16 ch)
SMC
(6 ch)
I2C
(1 ch)
USART
(1 ch)
I/O Timer
(4 ch)
FRT 0/1/2/3
ICU 2/3
OCU 0/1
(50 ch)
10−bit ADC
Peripheral Bus
Bridge 0
PERI5_AHB BUS
CLK_HPM_PD2
CLK_HPM_PD2
CLK_SYS_PD3
128 MHz
Cortex R4
DBG0_CTL
DBG0_CLK
DBG0_TRACE0.... DBG0_TRACE7
GFX0_DISP[0].... GFX0_DISP[25]
GFX0_TSIG[0].... GFX0_TSIG[11]
CLK_DMA_PD2
DMA
(8 ch)
USART6_SCKi
USART6_SIN
USART6_SCKo
USART6_SOT
DMA0_DEOP_ACK0, DMA0_DEOP_ACK1
DMA0_DREQ0, DMA0_DREQ1
DMA0_DSTP0, DMA0_DSTP1
DMA0_DREQ_ACK0, DMA0_DREQ_ACK1
DMA0_DSTP_ACK0, DMA0_DSTP_ACK1
DMA0_DEOP0, DMA0_DEOP1
I2Sn_ECLK
I2Sn_SCKi
I2Sn_SDi
I2Sn_WSi
VRAM
512KB/1M
SPI−MEM
256MB
HS−SPI
Signature
TCON
GFX0_DCLKI
GFXSPI_CLKi
GFXSPI_DATA0i.... GFXSPI_DATA3i
GFXSPI_SSi
High Performance Matrix (HPM)
Command
Seq
Pixel
Engine
SPIn_CLKi
SPIn_DATA0i˘. SPIn_DATA3i
SPIn_SSi
CLK_HPM_PD2
TCFlash
2M
CLK_MEM_E_PD3
SPI
(3 ch)
Peripheral Bus
Bridge 4
BootROM
16K
Memories
CLK_CFG_PD4
CLK_MEM_E_PD3
EEFlash
48K option
UDC0_AIN0, UDC0_AIN1
UDC0_BIN0, UDC0_BIN1
UDC0_ZIN0, UDC0_ZIN1
UDC0_UDOT0
UDC0_UDOT1
RLTn_TIN
RLTn_TOUT
Memory
Map
HS−SPI
(1 ch)
EIC0_NMI
Peripheral Bus
Bridge 3
PERI3_eRBUS
EIC0_INT00.... EIC0_INT31
NMI
Watchdog
CLK_CFG_PD1
CLK_PERI3_PD2
EIC
PERI4_SLAVE AHB BUS
Controlgroup
CLK_PERI4_PD2
Display
Controller
PERI1_RBUS
Graphical Subsystem "IRIS−SDL "
CLK_PERI1_PD2
January 30, 2015, MB9EF226_DS707-00004-2v1-E
PERI0_RBUS
CSV/CLK−out
PLL’s
PPG_ETRG0˘.. PPG_ETRG3
PPGn_PPGA
PPGn_PPGB
SMCn_M1
SMCn_P1
SMCn_M2
SMCn_P2
I2C0_SCLi
I2C0_SDAi
I2C0_SCLo
I2C0_SDAo
USART0_SCKi
USART0_SIN
USART0_SCKo
USART0_SOT
FRTn_FRCK
ICUn_IN0, ICUn_IN1
OTDn,OTDn_I,OTDn_G,OTDn_GI
AVDD5
AVSS5
AVRH
ADC0_AN0..... ADC0_AN31
ADC0_EDGI
SHE
Oscillators
Clock group
X0
X1
MODE
X0A
X1A
RSTX
1.1
CLK_PERI0_PD2
Da ta
Sh eet
1 Overview
Block diagram
7
Data
1.2
8
Shee t
Power Domains
Power
Domain
Modules
PD1
Clockgroup (Osc, PLL, CSV), Controlgroup (EIC, NMI, RTC, SYSC, WDG, TPU, IRQ
Control, Power Control)
PD2
Peripheral bus 0 (ADC, FRT, ICU, OCU, USART, I2C, SMC, PPG), Peripheral bus 1 (SG,
CAN, USART, FRT, ICU, OCU, PPG), Peripheral bus 3 (RLT, UDC, GPIO, PPU), Peripheral bus 4 (SPI, I2S), On-Chip Debug, Trace, SRAM, CRC, Cortex R4, SHE, MPU, ICache, D-Cache, TCM, TCFlash, EEFlash, TPU, BootROM, HS-SPI, MLB, IRIS-SDL
PD4
RetRAM
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
2 Feature list
2.1
Overview
Feature
MB9EF226 / QFP-176
MB9EF226L / QFP-176
MB9EF226 / QFP-240
Max. Core frequency
128 MHz
128 MHz
128 MHz
DMA
8 channels
8 channels
8 channels
TCFlash
2 MB
2 MB
2 MB
EEFlash
48 KB
48 KB
48 KB
AXI RAM (with ECC)
64 KB
64 KB
64 KB
TCM RAM (with ECC)
128 KB
128 KB
128 KB
RetRAM
Core has 4-way-associative
cache
SHE
16 KB
16 KB
16 KB
I/D each 8KB
I/D each 8KB
I/D each 8KB
yes
yes
yes
Boot-ROM
16 KB
16 KB
16 KB
IRQ Ctrl
256
256
256
Graphics subsystem
Iris-SDL
-
Iris-SDL
Graphic RAM (VRAM)
1MB
1MB
1MB
RTC (with auto calibration)
1 channel
1 channel
1 channel
Source clock timer
4
4
4
RLT (Reload Timer) (32 bit)
10 channels
10 channels
10 channels
FRT
8 channels
8 channels
8 channels
ICU
8 channels
8 channels
8 channels
OCU
8 channels
8 channels
8 channels
PPG
24 channels
24 channels
24 channels
SG (Sound Generator)
1 channel
1 channel
1 channel
UDC (UpDown Counter)
2 channels
2 channels
2 channels
CAN
2 channels
2 channels
2 channels
USART (LIN-USART)
2 channels
2 channels
2 channels
SPI
3 channels
3 channels
3 channels
I2C
1 channel
1 channel
1 channel
I2S
2 channels
2 channels
2 channels
Quad - SPI
2 channel
2 channel
2 channel
Media LB
1 channel
1 channel
1 channel
EIC (External Interrupts)
32 channels
32 channels
32 channels
NMI (intern / extern)
32/1
32/1
32/1
SMC
4(6) channels
4 channels
6 channels
ADC (10-bit)
50 channels
(including 24 channels
shared with SMC)
50 channels
(including 24 channels
shared with SMC)
50 channels
(including 24 channels
shared with SMC)
CRC
1 channel
1 channel
1 channel
Package
QFP-176
QFP-176
QFP-240
January 30, 2015, MB9EF226_DS707-00004-2v1-E
9
Data
2.2
Shee t
Features
Table 2-1: Device features (1 / 7)
Feature
Technology
Description
• 90nm CMOS with embedded flash
•
•
•
•
•
•
•
•
Cortex R4 CPU core
32-bit ARM architecture, dual-issue superscalar eight stage pipeline
ARMv7 and Thumb-2 instruction set compliant
Memory Protection Unit (MPU) with 12 regions
Two Tightly Coupled Memory (TCM) ports. 64-bit AXI slave port for access to
TCMs
64-bit AXI master port
Vectored Interrupt Controller (VIC) port for faster interrupt processing
Single error correction, double error detection (SECDED) Error Correction Coding (ECC) for memory error detection and correction
Instruction cache: 8KB 4-way set-associative
Data cache: 8KB 4-way set-associative
Up to 8 break-points and 8 watchpoints
Debug and Trace
•
•
•
•
ARM Coresight technology
Standard 5-pin JTAG interface
4-bit, 8-bit and 16-bit trace data width supported depending on package
Secure entry supported for debugger
Graphics Subsystem
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2D graphics engine with base level hardware acceleration
Maximum frame resolution: 1024 pixel x 1024 pixel
Video modes up to 40MHz pixel clock
1MB embedded SRAM video memory
64-bit multi-layer AXI bus for memory access
Quad SPI interface for external flash
One background and 3 alpha blended foreground layers.
One dedicated alpha layer.
Rotation of display by 90/180/270 degrees
Gamma correction for display output
Color dithering for low resolution panels
Copy and blend blit operations (OpenGL and OpenVG blending modes)
Pixel formats 1, 2, 4, 8, 16, 24, and 32 bpp
Raster operations (ROP2 and ROP3)
Processor Subsystem
Clocks
Clock Supervisor
10
•
•
•
•
•
•
•
•
External main clock of 4MHz (up to 8MHz under evaluation)
External sub clock (typical 32.768 kHz)
Embedded RC oscillator (typical 8/12 MHz, configurable)
Embedded Slow RC oscillator (typical 100 kHz)
On-chip Phase Locked Loop (PLL) clock multiplier for main clock, Spread Spectrum Clock Generation (SSCG), SSCG for graphics
• Stabilization timers for all source clocks
• Clock supervision for all source clocks and PLL outputs
• Reset generation for out-of-bound clock frequencies on input source clocks, or
PLL output clocks
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 2-1: Device features (2 / 7)
Feature
Resets
Watchdog Timer
DMA
Interrupts
External Interrupts
Description
•
•
•
•
•
•
•
Power on Reset (PoR)
External Reset
Software triggered hard reset
Clock supervision resets
Watchdog
Low Voltage Detection reset
Software reset
• 32-bit counter
• Supports selection of four clock sources (Main clock, Sub clock, RC clock or Slow
RC clock)
• Support for window watchdog functionality
• Reset or NMI generation support on watchdog errors
• Support for preemptive warning interrupt before watchdog reset or NMI generation
• Additional safety provision through three times redundancy and error correction
logic for important configuration bits
• Option to halt watchdog counter in case of core reaching break-point
•
•
•
•
•
•
•
64-bit AHB Master Interface
32-bit AHB Slave Interface
Block, burst and demand transfer modes
Fixed and incremental addressing for source as well as destination
116 clients
8 channels to handle independent data flows
Fixed priority, dynamic priority, and round robin arbitration
•
•
•
•
•
•
Interrupt Request (IRQ) and Fast Interrupt Request (FIQ) capability
NMI sources can generate FIQ
Supports 32 Non Maskable Interrupt (NMI) source for FIQ generation
Supports 512 Normal Interrupt sources for IRQ generation
Supports request for low power mode entry
Programmable 32-level priority controller for normal IRQ sources. Also, supports
programmable priority level masking
• Programmable 16-level priority controller for NMI interrupt sources
• Software interrupt generation
• Privileged mode support for restricted access
•
•
•
•
•
•
•
Up to 32 pins can be used as external interrupts
Optional 25ns (typical) noise filters on all lines
DMA support
NMI support
Five polarity support (‘H’, ‘L’, rising edge, falling edge, and, any edge)
Event capture support for all 32 external interrupt pins
Software enabled monitoring of external events, with sampling frequency of
500Hz to 16MHz
January 30, 2015, MB9EF226_DS707-00004-2v1-E
11
Data
Shee t
Table 2-1: Device features (3 / 7)
Feature
Description
Timing Protection
• Up to eight identical 24-bit timers for execution time protection, locking time protection, inter-arrival time protection or deadline protection
• Normal and overflow mode support
• Global linear prescaler (1 to 64) to scale down clock frequency
• Additional, individual timer prescaler to support 4 different software programmable frequencies (1, 1/2, 1/4, and 1/16 )
• Start, stop, and continue options per timer controllable by software
Memory Protection
• Memory protection unit for all bus masters
• AXI interface support
• 8 programmable memory regions, and one background region which covers entire 4GB address space
• Unauthorized access generates NMI
Peripheral Protection
• Protection to all peripherals and General Purpose IOs (GPIO)
• Individual protection setting for up to 512 peripherals, and 512 GPIO channels
• DMA access support for faster register configuration
CAN
USART/LIN
•
•
•
•
•
•
•
•
• Programmable LIN or USART function
• Full-duplex support
• Clock synchronous (start-stop synchronization and start-stop-bit option),and
Clock asynchronous (using start-, stop-bits) transfer modes
• Dedicated baud rate generator. Mechanism for automatic baud rate adjust available in LIN mode
• Support for data length of 7-bits (not in synchronous or LIN mode) and 8-bits
• Support for signal modes Non-Return to Zero (NRZ) and Non-Return to Zero
Inverted (NRZI)
• Reception error detection for framing, overrun, parity, checksum, sync field timeout, and frame-ID (only in LIN mode) errors
• Interrupt capability for transmission, reception, and errors
• DMA support
•
•
•
•
I2C
•
•
•
•
12
Supports CAN protocol version 2.0 part A and B
Bit rates up to 1 Mbps
64 message objects
Each message object has its own identifier mask
Programmable FIFO mode (concatenation of message objects)
Maskable interrupt
Disabled automatic retransmission mode for time triggered CAN applications
Programmable loop-back mode for self-test operation
Master/slave transmitting and receiving functions
7-bit addressing as master and slave
10-bit addressing as master and slave
Acknowledge disable option upon slave address reception (master-only operation)
Address mirroring to give interface several slave addresses
Up to 400 kbps transfer rate
Optional noise filters for SDA and SCL
Interrupt capability on transmission and bus error events
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 2-1: Device features (4 / 7)
Feature
Stepper Motor Control
A/D Converter
Description
• PWM duty cycle programmable from 0% to 100%
• Programmable setting to select ‘L’, ‘H’, ‘PWM’ and ‘HighZ’ output
• High current output pins
•
•
•
•
•
•
•
•
•
50 channels
Conversion time: 1us per channel
RC type Successive Approximation (SAR) with sample and hold circuit
10-bit or 8-bit resolution
Program selection analog input from 32 channels
Single conversion, continuous conversion, and scan conversion options
Interrupt capability
DMA support
4 range comparator channels for comparing conversion output with thresholds
I2S
• Programmable master/slave operations
• Supports transmission only, reception only and simultaneous transmission/reception operations
• Support for 1 sub frame and 2 sub frame constructions
• Up to 32 channels supported in each sub frame
• Support for individual configuration of channel number, channel length, word
length in each sub frame
• Word length support from 7-bits to 32-bits
• Programmable frequency, polarity, and phase of frame synchronous signal
• Programmable sampling point of received data (center or at the end of received
data)
• Support for frequency division from 1 to 126 in multiples of 2
• DMA support
• Interrupt capability
Sound Generator
• Produces sound/melody with varying frequency and amplitude
• Square wave sound output with frequency of 100Hz – 6kHz (resolution 20Hz)
• Programmable Pulse Width Modulated (PWM) cycle width of 255 or 511 clocks.
PWM duty cycle programmable from 0% to 100%
• Two 2-bit prescaler with programmable clock division of 1, 1/2, 1/3, and 1/4
• Automatic linear or exponential amplitude increment or decrement
• Start, stop, resume functionality
• DMA support
• Automatic sound output stop when amplitude becomes 0
Up Down Counter
• Format: 32-bit or 2 times 16-bit
• Three count modes (timer mode, up/down count mode, and phase difference
count mode) supported
• Multiply by 2 or multiply by 4 in phase difference count mode
• Count source can be internal clock or external trigger
• Counting range: any value between 0 and 232-1 can be set
• 4 interrupt options (Compare-match interrupt, Underflow interrupt, Overflow interrupt, and Count direction change interrupt)
January 30, 2015, MB9EF226_DS707-00004-2v1-E
13
Data
Shee t
Table 2-1: Device features (5 / 7)
Feature
Reload Timers
Free Running Timers
Description
•
•
•
•
•
•
•
32-bit reload counter
External and Internal clock/event source
Trigger signal programmable as rising/falling edge or both
Gated count function
One-shot or reload counter mode
Counter state can be made visible at external pin
Prescaler with six different settings for the internal clock and two settings for the
external clock
• Several Reload Timers can be cascaded to form a longer Reload Timer
• DMA support
• Signals an interrupt on overflow, match with Compare registers, zero-detection,
or match with Compare Clear Register
• Option to mask zero detection, compare clear match interrupt, or both to allow
for interrupt generation only after multiple events
• Programmable timer period up to 1 s
• Support for 11 counter clocks. Prescaler with 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512, and 1/1024 of peripheral clock frequency
• DMA support
Input Capture Units
•
•
•
•
•
Consists of 2 independent input channels
16-bit wide capture registers per channel
Signals an interrupt upon external event
Rising edge, falling edge or rising & falling edge sensitive
DMA support
Output Compare
Units
•
•
•
•
•
Consists of 2 independent channels
16-bit wide
Signals an interrupt when a match with 16-bit I/O Timer occurs
A pair of compare registers can be used to generate an output signal
Interrupt capability
Programmable Pulse
Generator
•
•
•
•
16-bit down counter, cycle and duty setting registers
Interrupt at trigger, counter borrow and/or duty match
PWM operation and one-shot operation
Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock
and Reload timer underflow as clock input
• Can be triggered by software or reload timer
•
•
•
•
Real Time Clock
•
•
•
•
Internal MemoriesTCMRAM
14
Can be clocked from main clock, sub clock or RC clock
Automatic calibration support even when device is in low power state
Interrupt capability on half-second, 1 second, 1 minute, 1 hour, and 1 day duration
Additional capability for interrupt generation on calibration failure detection and
calibration done event
Auto calibration of Sub clock or RC clock with respect to Main clock
Separate clock selector for calibration
Configurable calibration duration
Auto/manual trigger for calibration
• 128 KB
• 64-bit interface
• Single error correction, double error detection (SECDED) ECC support
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 2-1: Device features (6 / 7)
Feature
Description
Internal MemoriesSystem RAM
•
•
•
•
64-bit AXI interface
64 KB
Single error correction, double error detection (SECDED) ECC support
Parallel read/write capability for 2 different banks
Internal MemoriesRetention RAM
•
•
•
•
16 KB
4 banks
32-bit AHB
Low leakage RAMs for low power consumption
Tightly Coupled Flash
Memory
EEPROM Emulation
Flash Memory
Quad SPI
Error Collection
Low Voltage Detect
I/O Ports
• 2 MB
• Parallel Programming support
• Mapped to TCM address space as well as Cacheable address space through
AXI interface
• Single error correction, double error detection (SECDED) ECC support
• TCM address space supports only read access
• Cacheable AXI address space supports write and read access
• Detection of hang-up 1 state
• 32 large sectors of 64KB each
• 16 small sectors of 8KB each
• Sector-wise access protection for write and read accesses
•
•
•
•
•
•
•
48 KB
Single error correction, double error detection (SECDED) ECC support
Support for sector erase
EEPROM emulation mode support
Support for mirroring of memory in 3 diverse memory-mapped regions
6 sectors of 8KB each
Sector-wise access protection for write and read accesses
• Supports legacy as well as the dual-bit and quad-bit modes of SPI operation
• Supports up to four slave devices in master mode
• Programmable transfer rate, active-level of slave-select signal, polarity, and
phase of the serial clock per slave select
• Support for memory mapped operation of external serial flash and serial SRAM
devices in command sequencer mode
• Additional direct mode support for standard SPI operation through FIFO interface
• Error collection on all peripherals
• Optional Non-Maskable Interrupt (NMI) generation capability
• Low voltage detection for 5V, 3.3V, and 1.2V
• Programmable thresholds
• Reset generation capability on low voltage events
•
•
•
•
All functional pins can be used as GPIO
Programmable analog or digital functionality selection
Programmable input levels (Automotive, CMOS, and TTL)
Programmable pull-up/pull-down and output drive
January 30, 2015, MB9EF226_DS707-00004-2v1-E
15
Data
Shee t
Table 2-1: Device features (7 / 7)
Feature
Description
MediaLB
• Implements
• Supports 16 logical channels
• Each logical channel can be programmed as synchronous, asynchronous, isochronous and control channel type and as transmit or receive
• Loop back mode between the logical channel 0 (reception) and logical channel
1(transmission)
• Programmable for 256Fs, 512Fs and 1024Fs transfer rates of operation at either
44.0kHz, 48.0kHz, or 48.1kHz.
• 3-pin mode
SHE
• Implements all commands defined by the functional specification of SHE (chapter
7)
• Provides AES-128 encryption and decryption operations
• Electronic cipher book (ECB) and cipher block chaining (CBC) modes
• Supports generation of the cipher-based message authentication code (CMAC)
• Implements Miyaguchi-Preneel compression function.
• Provides random number generation function
• Supports secure booting
• Measurement during / before application start-up
• Secure boot mode, start address and length of the bootloader are configurable
by the user
• Secure key storage implemented in EEFLASH
CRC
•
•
•
•
•
•
•
•
Packages
Programmable 8, 16, 24 or 32 bit input data width
Programmable polynomial value (Polynomial degree from 2 to 32)
Programmable initial seed value
Programmable final checksum XOR value
Interrupt and DMA trigger capability
Configurable input/output bit reflection and byte swapping
Supports PPU
Supports block/multiple data transfers (more than 32-bit)
• QFP-240 (evaluation variant with additional trace pins)
• QFP-176 (series variant)
Note: EEPROM (Electronically Erasable and Programmable Read-Only Memory)
16
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
2.3
Sh eet
Memory Map
Table 2-2: Device Memory Map
Start Address
Module
FFFF4000
Reserved
FFFF0000
BOOTROM
FFFEF000
ERCFG_CONFIG
B0D01000
Reserved
B0D00000
SYSTEM_RAM_CONFIG
B0C00000
PERI5_AHB
B0B00000
PERI4_SLAVE
B0A00000
PERI3_ERBUS
B0900000
Reserved
B0800000
PERI1_RBUS
B0700000
PERI0_RBUS
B0600000
MCU_CONFIG
B0500000
DEBUG_BUS
B0400000
MEMORY_CONFIG
B0180000
Reserved
B0100000
GFXCFG
B0080000
Reserved
B0000000
HSSPI0CFG
90000000
Reserved
80000000
HSSPI0_MEMORY
60000000
Reserved
40000000
GFXMEM
06000000
Reserved
05FE0000
AXI_SLAVE_CORE0_TCM_FLASH_SMALL_SECTORS
05A00000
Reserved
05800000
AXI_SLAVE_CORE0_TCM_FLASH_LARGE_SECTORS
05020000
Reserved
05000000
AXI_SLAVE_CORE0_TCM_RAM
04800000
AXI_SLAVE_CORE0_DCACHE
04000000
AXI_SLAVE_CORE0_ICACHE
01A10000
Reserved
01A00000
SYSTEM_RAM
01800000
Reserved
017E0000
AXI_FLASH_MEMORY_SMALL_SECTORS
01200000
Reserved
01000000
AXI_FLASH_MEMORY_LARGE_SECTORS
00FE0000
TCM_FLASH_SMALL_SECTORS
00A00000
Reserved
0008_0000
TCM_FLASH_LARGE_SECTORS
00020000
Reserved
00000000
TCM_RAM
January 30, 2015, MB9EF226_DS707-00004-2v1-E
17
Data
Shee t
Table 2-3: HSSPI0 Memory Map
Start Address
Module
B007FC00
BSU8
B0078400
Reserved
B0078000
RICFG8
B0000000
HSSPI0
Table 2-4: Memory and Config (MEMORY_CONFIG) AHB Bus Memory Map
18
Start Address
Module
B04C0000
EEFLASH_NOECC_MIR
B0480000
EEFLASH_TABLE_MIR
B0440000
EEFLASH_ECC_MIR
B0418400
Reserved
B0418000
BSU6
B0414400
Reserved
B0414000
MPUXSHE0
B0413400
Reserved
B0413000
SHE_IF_CFG
B0412400
Reserved
B0412000
EEFCFG
B0411400
Reserved
B0411000
TCFCFG
B0410400
Reserved
B0410000
TRCFG
B0408400
Reserved
B0408000
TPU0
B0404000
Reserved
B0400000
IRQ0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 2-5: MCU_CONFIG AHB Bus Memory Map
Start Address
Module
B06FFC00
BSU7
B06F8000
RICFG7
B0648000
Reserved
B063B000
RETRAMBANK3
B063A000
RETRAMBANK2
B0639000
RETRAMBANK1
B0638000
RETRAMBANK0
B0628400
Reserved
B0628000
EICU0
B0620400
Reserved
B0620000
EIC0
B0618400
Reserved
B0618000
RTC
B0610400
Reserved
B0610000
RRCFG
B0608400
Reserved
B0608000
WDG
B0601000
Reserved
B0600000
SYSC
January 30, 2015, MB9EF226_DS707-00004-2v1-E
19
Data
Shee t
Table 2-6: PERI0_RBUS Memory Map
20
Start Address
Module
Start Address
B07FFC00
BSU0
B0720000
Module
I2C0
B07F8000
RICFG0
B071C000
Reserved
B07F0400
Reserved
B0718400
OCU1
B07F0000
BECU0
B0718000
OCU0
B07EC000
Reserved
B0714000
Reserved
B07E8000
PPC
B0710C00
ICU3
B074C400
Reserved
B0710800
ICU2
B074C000
PPGGLC0
B070C000
Reserved
B0748C00
PPGGRP3
B0708C00
FRT3
B0748800
PPGGRP2
B0708800
FRT2
B0748400
PPGGRP1
B0708400
FRT1
B0748000
PPGGRP0
B0708000
FRT0
B073BC00
PPG15
B0700400
Reserved
B073B800
PPG14
B0700000
ADC0
B073B400
PPG13
B073B000
PPG12
B073AC00
PPG11
B073A800
PPG10
B073A400
PPG9
B073A000
PPG8
B0739C00
PPG7
B0739800
PPG6
B0739400
PPG5
B0739000
PPG4
B0738C00
PPG3
B0738800
PPG2
B0738400
PPG1
B0738000
PPG0
B0731C00
Reserved
B0731800
SMCTG0
B0731400
SMC5
B0731000
SMC4
B0730C00
SMC3
B0730800
SMC2
B0730400
SMC1
B0730000
SMC0
B0729800
Reserved
B0728000
USART0
B0720C00
Reserved
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 2-7: PERI1_RBUS Memory Map
Start Address
Module
B08FFC00
BSU1
B08F8000
RICFG1
B08F0400
Reserved
B08F0000
BECU1
B085C400
Reserved
B085C000
PPGGLC1
B0858400
PPGGRP17
B0858000
PPGGRP16
B0849C00
PPG71
B0849800
PPG70
B0849400
PPG69
B0849000
PPG68
B0848C00
PPG67
B0848800
PPG66
B0848400
PPG65
B0848000
PPG64
B0839800
Reserved
B0838000
USART6
B082C000
Reserved
B0828400
OCU17
B0828000
OCU16
B0824000
Reserved
B0820C00
ICU19
B0820800
ICU18
B081C000
Reserved
B0818C00
FRT19
B0818800
FRT18
B0818400
FRT17
B0818000
FRT16
B080A000
Reserved
B0808400
CAN1
B0808000
CAN0
B0801000
Reserved
B0800000
SG0
January 30, 2015, MB9EF226_DS707-00004-2v1-E
21
Data
Shee t
Table 2-8: PERI3_eRBUS Memory Map
Start Address
22
Module
B0AFFC00
BSU3
B0AF8000
RICFG3
B0AF0400
Reserved
B0AF0000
BECU3
B0A21000
Reserved
B0A20000
UDC0
B0A18000
Reserved
B0A12400
RLT9
B0A12000
RLT8
B0A11C00
RLT7
B0A11800
RLT6
B0A11400
RLT5
B0A11000
RLT4
B0A10C00
RLT3
B0A10800
RLT2
B0A10400
RLT1
B0A10000
RLT0
B0A09000
Reserved
B0A08000
GPIO
B0A00400
Reserved
B0A00000
PPU0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 2-9: PERI4_SLAVE AHB Bus Memory Map
Start Address
Module
B0BFFC00
BSU4
B0BF8000
RICFG4
B0B40400
Reserved
B0B40000
ARH0
B0B3B000
Reserved
B0B38800
SPI2
B0B38400
SPI1
B0B38000
SPI0
B0B30800
Reserved
B0B30000
CRC0
B0B22000
Reserved
B0B20400
I2S1
B0B20000
I2S0
B0B10800
Reserved
B0B10400
MPUHMLB0
B0B10000
MLB0
B0B00400
Reserved
B0B00000
MPUXGFX
Table 2-10: PERI5_AHB Bus Memory Map
Start Address
Module
B0CFFC00
BSU5
B0C09000
Reserved
B0C08000
MPUXDMA0
B0C04000
Reserved
B0C00000
DMA0
B0800000
B0700000
PERI1_RBUS
PERI0_RBUS
January 30, 2015, MB9EF226_DS707-00004-2v1-E
23
Data
2.4
Shee t
Resource distribution for non-modulated clock
Some of the resources are available with modulated and non-modulated clock. Find below the distribution:
2.5
Module
Non-modulated
Modulation possible
CAN
2
-
SG
1
-
ICU/OCU/FRT
4
4
PPG
8
16
USART/LIN
1
1
I2C
1
-
SMC
-
6
Lock/unlock values for protection units
For various protection and system relevant units, registers must be unlocked before configuring and can be
locked for protection. For the details about functionality, see the FCR4 Hardware Manual.
Table 2-11: Lock/unlock values for FCR4 protection module instances.
24
Module
Unlock value
Lock value
TPU0
ACC5A110
B10CACC5
PPU0
ACC5BB01
BB0B10C1
MPUHMLB0
D76ACC01
D76B10C1
MPUXDMA0
ACCABB56
112ABB56
MPUXGFX
01ACC384
0B10C834
MPUXSHE0
EA1221AE
10CE0EB1
TRCFG
ACC55ECC
5ECCB10C
EXCFG
ACC5B007
B007ECF6
IRQ0
17ACC911
17B10C11
RRCFG
ACC5DECC
DECCB10C
SCCFG
5ECACCE5
A135331A
SRCFG
5ECC551F
551FB10C
GFXSIG
A1ACC384
AB10C834
GFXGCTR
7E1ECA57
D15AB1E0
TCFCFG
CF61F1A5
EEFCFG
CF6DF1A5
WDG
EDACCE55
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
2.6
Sh eet
Module
Unlock value
SYSC
5CACCE55
Lock value
ID-Values for Module Identification Registers
For several peripheral and system related modules, the hardware contains Module Identification Registers that
hold read-only values which contain information about the module number, the version and possible patches.
Table 2-12: List of Module ID
Module
ID-Register
ID Value
System Controller
SYSC_SYSIDR
0x00040100 / 0x00041100
Security Checker
SCCFG_MODID
0x00020400
SRAM Interface
SRCFG_MID
0x00040300
TC-Flash Interface
TCFCFG_FMIDR
0x000E0400
EE-Flash Interface
EEFCFG_MIR
0x00090700
Interrupt Controller 0
IRQ0_MID
0x000B0100
DMA Controller 0
DMA0_ID
0x00010400
Timing Protection Unit 0
TPU0_MID
0x00050200
Memory Protection Unit for DMA
MPUXDMA0_MID
0x000D0200
Memory Protection Unit for GFX
MPUXGFX_MID
0x000D0200
Memory Protection Unit for SHE
MPUXSHE0_MID
0x000D0200
Memory Protection Unit for MLB
MPUHMLB0_MID
0x00110100
Bus Error Collection Unit 0
BECU0_MIDH / BECU0_MIDL
0x0008 / 0x0300
Bus Error Collection Unit 1
BECU1_MIDH / BECU1_MIDL
0x0008 / 0x0300
Bus Error Collection Unit 3
BECU3_MIDH / BECU3_MIDL
0x0008 / 0x0300
High Speed SPI Interface 0
HSSPI0_MID
0x00060400
SPI Interface 0
SPI0_MID
0x00070400
SPI Interface 1
SPI1_MID
0x00070400
SPI Interface 2
SPI2_MID
0x00070400
Inter IC Sound 0
I2S0_MIDREG
0x000A0300
Inter IC Sound 1
I2S1_MIDREG
0x000A0300
SHE
SHE_IF_CFG_MID
0x000F0200
January 30, 2015, MB9EF226_DS707-00004-2v1-E
25
Data
26
Shee t
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
3 Package and Pin Assignment
3.1
Package
The same die will be used for two packages.
QFP-176 and QFP-240 packages will be used for MB9EF226. The package code is FPT-176P-M07.
Also an optional QFP-240 package with trace pins is shown in Section 3.1.1. The package code is FPT-240PM06.
3.1.1
QFP-240 Pin Assignment
VDP5
PT_TESTPAD
AVDD5
AVRH5
AVRL5
AVSS5
NB
DVCC
DVSS
P1_23
P1_22
P1_21
P1_20
P1_19
P1_18
P1_17
P1_16
DVCC
DVCC
DVSS
DVSS
P1_15
P1_14
P1_13
P1_12
P1_11
P1_10
P1_09
P1_08
DVCC
DVCC
DVSS
DVSS
P1_07
P1_06
P1_05
P1_04
P1_03
P1_02
P1_01
P1_00
DVCC
DVCC
DVSS
DVSS
VSS
VSS
VDP3
VDP3
VDD
VDD
DBG0_TRACE15
P1_47
P1_46
DBG0_TRACE14
P1_45
P1_44
DBG0_TRACE13
P1_43
VDP3
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
Figure 3-1: QFP-240 Pin Assignment
VSS
181
120
VSS
182
119
P1_41
P0_24
183
118
DBG0_TRACE12
P1_42
P0_25
184
117
P1_40
P0_40
185
116
P1_39
P0_41
186
115
VSS
187
114
P1_28
VSS
188
113
DBG0_TRACE11
VDD
189
112
P1_27
P1_29
VDD
190
111
P0_42
191
110
VSS
P0_43
192
109
DBG0_TRACE10
NB
193
108
VDP3
P0_44
194
107
P0_45
195
106
P1_58
P0_46
196
105
DBG0_TRACE9
P0_47
197
104
P1_57
VSS
198
103
P1_56
VSS
199
102
VDP5
200
101
P1_54
P0_48
201
100
DBG0_TRACECLK
P0_49
202
99
P2_32
203
98
VDP3
NB
204
97
P1_53
P2_33
P1_26
P1_59
P1_55
VSS
205
96
P1_52
P2_34
206
95
DBG0_TRACECTL
P2_35
207
94
P1_51
P1_50
P2_36
208
93
P2_37
209
92
VSS
210
91
P1_48
VSS
211
90
DBG0_TRACE8
VDD
212
89
VDD
213
88
VDP3
NB
214
87
P2_25
P2_38
P1_49
VSS
215
86
P2_24
P2_39
216
85
DBG0_TRACE7
P2_40
217
84
P2_41
218
83
VSS
NB
219
82
P2_23
P2_42
220
81
P2_22
P2_43
221
80
P2_48
222
79
VDD
P2_49
223
78
P2_21
VSS
224
77
P2_20
DBG0_TRACE6
VSS
VDD
VSS
225
76
VDP5
226
75
NB
227
74
VDP3
VDP5
228
73
P2_19
P2_50
229
72
P2_18
NB
VDP3
230
71
VSS
P2_51
231
70
P2_17
P0_62
232
69
P2_16
DBG0_TRACE5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
VDP5
VSS
VSS
VDP3
VDP3
P1_30
P1_31
P1_32
P1_33
P1_34
DBG0_TRACE0
P1_35
P1_36
P1_37
P1_38
DBG0_TRACE1
P1_61
P1_62
P1_60
VSS
VSS
VDP3
VDP3
P2_00
P2_01
VSS
VSS
DBG0_TRACE2
P2_02
P2_03
VDD
VDD
P2_04
P2_05
VDP3
VDP3
DBG0_TRACE3
P2_06
P2_07
VSS
VSS
P2_08
P2_09
VDP3
VDP3
P2_10
P2_11
VSS
VSS
P2_12
P2_13
VDD
9
VDD
61
VDP5
DBG0_TRACE4
62
240
8
63
239
RSTX
238
JTAG_TCK
7
JTAG_TMS
JTAG_NTRST
X1A
P2_14
6
64
X0A
237
5
NB
4
P2_15
VSS
65
VSS
236
3
VDP3
NB
2
66
1
67
235
X0
68
234
X1
233
JTAG_TDI
MODE
P0_63
JTAG_TDO
January 30, 2015, MB9EF226_DS707-00004-2v1-E
VDP3
27
Data
Shee t
Table 3-1: QFP-240 Pin Assignment
28
Pin No
Pin name
Pin No
Pin name
Pin No
Pin name
1
MODE
33
P2_00
65
P2_15
2
X1
34
P2_01
66
VDP3
3
X0
35
VSS
67
VDP3
4
VSS
36
VSS
68
DBG0_TRACE5
5
VSS
37
DBG0_TRACE2
69
P2_16
6
X0A
38
P2_02
70
P2_17
7
X1A
39
P2_03
71
VSS
8
RSTX
40
VDD
72
P2_18
9
VDP5
41
VDD
73
P2_19
10
VDP5
42
P2_04
74
VDP3
11
VSS
43
P2_05
75
VDP3
12
VSS
44
VDP3
76
DBG0_TRACE6
13
VDP3
45
VDP3
77
P2_20
14
VDP3
46
DBG0_TRACE3
78
P2_21
15
P1_30
47
P2_06
79
VDD
16
P1_31
48
P2_07
80
VDD
17
P1_32
49
VSS
81
P2_22
18
P1_33
50
VSS
82
P2_23
19
P1_34
51
P2_08
83
VSS
20
DBG0_TRACE0
52
P2_09
84
VSS
21
P1_35
53
VDP3
85
DBG0_TRACE7
22
P1_36
54
VDP3
86
P2_24
23
P1_37
55
P2_10
87
P2_25
24
P1_38
56
P2_11
88
VDP3
25
DBG0_TRACE1
57
VSS
89
VSS
26
P1_61
58
VSS
90
DBG0_TRACE8
27
P1_62
59
P2_12
91
P1_48
28
P1_60
60
P2_13
92
P1_49
29
VSS
61
VDD
93
P1_50
30
VSS
62
VDD
94
P1_51
31
VDP3
63
DBG0_TRACE4
95
DBG0_TRACECTL
32
VDP3
64
P2_14
96
P1_52
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Pin No
Pin name
Pin No
Pin name
Pin No
Pin name
97
P1_53
131
VDD
165
P1_17
98
VDP3
132
VDP3
166
P1_18
99
VSS
133
VDP3
167
P1_19
100
DBG0_TRACECLK
134
VSS
168
P1_20
101
P1_54
135
VSS
169
P1_21
102
P1_55
136
DVSS
170
P1_22
103
P1_56
137
DVSS
171
P1_23
104
P1_57
138
DVCC
172
DVSS
105
DBG0_TRACE9
139
DVCC
173
DVCC
106
P1_58
140
P1_00
174
NB
107
P1_59
141
P1_01
175
AVSS5
108
VDP3
142
P1_02
176
AVRL5
109
DBG0_TRACE10
143
P1_03
177
AVRH5
110
VSS
144
P1_04
178
AVDD5
111
P1_26
145
P1_05
179
PT_TESTPAD
112
P1_27
146
P1_06
180
VDP5
113
DBG0_TRACE11
147
P1_07
181
VSS
114
P1_28
148
DVSS
182
VSS
115
P1_29
149
DVSS
183
P0_24
116
P1_39
150
DVCC
184
P0_25
117
P1_40
151
DVCC
185
P0_40
118
DBG0_TRACE12
152
P1_08
186
P0_41
119
P1_41
153
P1_09
187
VSS
120
P1_42
154
P1_10
188
VSS
121
VDP3
155
P1_11
189
VDD
122
P1_43
156
P1_12
190
VDD
123
DBG0_TRACE13
157
P1_13
191
P0_42
124
P1_44
158
P1_14
192
P0_43
125
P1_45
159
P1_15
193
NB
126
DBG0_TRACE14
160
DVSS
194
P0_44
127
P1_46
161
DVSS
195
P0_45
128
P1_47
162
DVCC
196
P0_46
129
DBG0_TRACE15
163
DVCC
197
P0_47
130
VDD
164
P1_16
198
VSS
January 30, 2015, MB9EF226_DS707-00004-2v1-E
29
Data
30
Pin No
Pin name
Pin No
Pin name
199
VSS
233
P0_63
200
VDP5
234
JTAG_TDO
Shee t
201
P0_48
235
JTAG_TDI
202
P0_49
236
NB
203
P2_32
237
NB
204
NB
238
JTAG_TMS
205
P2_33
239
JTAG_TCK
206
P2_34
240
JTAG_NTRST
207
P2_35
208
P2_36
209
P2_37
210
VSS
211
VSS
212
VDD
213
VDD
214
NB
215
P2_38
216
P2_39
217
P2_40
218
P2_41
219
NB
220
P2_42
221
P2_43
222
P2_48
223
P2_49
224
VSS
225
VSS
226
VDP5
227
NB
228
VDP5
229
P2_50
230
NB
231
P2_51
232
P0_62
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
3.1.2
Sh eet
QFP-176 Pin Assignment
VDP5
AVDD5
AVRH5
AVSS5
DVCC
DVSS
P1_23
P1_22
P1_21
P1_20
P1_19
P1_18
P1_17
P1_16
DVCC
DVSS
P1_15
P1_14
P1_13
P1_12
P1_11
P1_10
P1_09
P1_08
DVCC
DVSS
P1_07
P1_06
P1_05
P1_04
P1_03
P1_02
P1_01
P1_00
DVCC
DVSS
VSS
VDP3
VDD
P1_47
P1_46
P1_45
P1_44
P1_43
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
Figure 3-2: QFP-176 Pin Assignment
VSS
133
88
P1_42
P0_24
134
87
P1_41
P0_25
135
86
P1_40
P0_40
136
85
P1_39
P0_41
137
84
P1_29
VSS
138
83
P1_28
VDD
139
82
P0_42
140
81
P1_26
P0_43
141
80
VSS
P0_44
142
79
VDP3
P0_45
143
78
P1_59
P0_46
144
77
P1_58
P0_47
145
76
P1_57
VSS
146
75
P1_56
VDP5
147
74
P0_48
148
73
P1_54
P0_49
149
72
VSS
P2_32
150
71
VDP3
P2_33
151
70
P1_53
P2_34
152
69
P1_52
P2_35
153
68
P1_51
P2_36
154
67
P1_50
P2_37
155
66
P1_27
P1_55
P1_49
VSS
156
65
P1_48
VDD
157
64
VSS
P2_38
158
63
VDP3
P2_39
159
P2_40
160
61
P2_24
P2_41
161
60
VSS
P2_42
162
59
P2_23
P2_43
163
58
P2_22
P2_48
164
57
VDD
P2_49
165
56
P2_21
VSS
166
55
P2_20
`
`
`
`
62
P2_25
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P1_32
P1_33
P1_34
P1_35
P1_36
P1_37
P1_38
P1_61
P1_62
P1_60
VSS
VDP3
P2_00
P2_01
VSS
P2_02
P2_03
VDD
P2_04
P2_05
VDP3
P2_06
P2_07
VSS
P2_08
P2_09
VDP3
P2_10
P2_11
VSS
P2_12
P2_13
VDD
12
45
P1_31
176
11
P2_14
JTAG_NTRST
10
46
VDP3
175
P1_30
P2_15
JTAG_TCK
9
47
VSS
174
8
JTAG_TMS
VDP5
VDP3
7
P2_16
48
RSTX
49
173
6
172
JTAG_TDI
X1A
JTAG_TDO
5
VSS
50
4
51
171
X0A
170
P0_63
VSS
P0_62
3
P2_18
X0
P2_19
52
2
VDP3
53
1
54
169
X1
167
168
P2_51
MODE
VDP5
P2_50
January 30, 2015, MB9EF226_DS707-00004-2v1-E
P2_17
31
Data
Shee t
Table 3-2: QFP-176 Package pinout
32
Pin No
Pin Name
Pin No
Pin Name
Pin No
Pin Name
1
MODE
33
VDP3
65
P1_48
2
X1
34
P2_06
66
P1_49
3
X0
35
P2_07
67
P1_50
4
VSS
36
VSS
68
P1_51
5
X0A
37
P2_08
69
P1_52
6
X1A
38
P2_09
70
P1_53
7
RSTX
39
VDP3
71
VDP3
8
VDP5
40
P2_10
72
VSS
9
VSS
41
P2_11
73
P1_54
10
VDP3
42
VSS
74
P1_55
11
P1_30
43
P2_12
75
P1_56
12
P1_31
44
P2_13
76
P1_57
13
P1_32
45
VDD
77
P1_58
14
P1_33
46
P2_14
78
P1_59
15
P1_34
47
P2_15
79
VDP3
16
P1_35
48
VDP3
80
VSS
17
P1_36
49
P2_16
81
P1_26
18
P1_37
50
P2_17
82
P1_27
19
P1_38
51
VSS
83
P1_28
20
P1_61
52
P2_18
84
P1_29
21
P1_62
53
P2_19
85
P1_39
22
P1_60
54
VDP3
86
P1_40
23
VSS
55
P2_20
87
P1_41
24
VDP3
56
P2_21
88
P1_42
25
P2_00
57
VDD
89
P1_43
26
P2_01
58
P2_22
90
P1_44
27
VSS
59
P2_23
91
P1_45
28
P2_02
60
VSS
92
P1_46
29
P2_03
61
P2_24
93
P1_47
30
VDD
62
P2_25
94
VDD
31
P2_04
63
VDP3
95
VDP3
32
P2_05
64
VSS
96
VSS
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Pin No
Pin Name
Pin No
Pin Name
Pin No
Pin Name
97
DVSS
131
AVDD5
165
P2_49
98
DVCC
132
VDP5
166
VSS
99
P1_00
133
VSS
167
VDP5
100
P1_01
134
P0_24
168
P2_50
101
P1_02
135
P0_25
169
P2_51
102
P1_03
136
P0_40
170
P0_62
103
P1_04
137
P0_41
171
P0_63
104
P1_05
138
VSS
172
JTAG_TDO
105
P1_06
139
VDD
173
JTAG_TDI
106
P1_07
140
P0_42
174
JTAG_TMS
107
DVSS
141
P0_43
175
JTAG_TCK
108
DVCC
142
P0_44
176
JTAG_NTRST
109
P1_08
143
P0_45
110
P1_09
144
P0_46
111
P1_10
145
P0_47
112
P1_11
146
VSS
113
P1_12
147
VDP5
114
P1_13
148
P0_48
115
P1_14
149
P0_49
116
P1_15
150
P2_32
117
DVSS
151
P2_33
118
DVCC
152
P2_34
119
P1_16
153
P2_35
120
P1_17
154
P2_36
121
P1_18
155
P2_37
122
P1_19
156
VSS
123
P1_20
157
VDD
124
P1_21
158
P2_38
125
P1_22
159
P2_39
126
P1_23
160
P2_40
127
DVSS
161
P2_41
128
DVCC
162
P2_42
129
AVSS5
163
P2_43
130
AVRH5
164
P2_48
January 30, 2015, MB9EF226_DS707-00004-2v1-E
33
Data
3.2
Shee t
I/O Pins and their functions
IO Pin configuration needs to be done by writing into Port Pin Multiplexing registers and Resource Input Configuration registers which are described in Section 3.2.1 and Section 3.2.2 respectively. GPIO_PPERn register
must
be enabled before starting IO Pin configuration, since GPIO_PPERn enables corresponding pin of the device.
Note: Since writing GPIO PPERn registers are required for both Portmux & resource-mux registers.
3.2.1
Port Pin Multiplexing table
Table 3-3: Port Pin Multiplexing table (1 / 10)
Resource Functional Outputs
Register
(Offset
PCFGR024
(0x0030)
PCFGR025
(0x0032)
PCFGR040
(0x0050)
PCFGR041
(0x0052)
PCFGR042
(0x0054)
PCFGR043
(0x0056)
34
Port
POF=0
P0_24
GPIO0_24o
P0_25
P0_40
P0_41
P0_42
P0_43
POF=1
GPIO0_41o
GPIO0_42o
GPIO0_43o
POF=3
OCU0_OTD0_GI
GPIO0_25o
GPIO0_40o
POF=2
OCU0_OTD1_GI
SPI2_SSo
SPI2_DATA1o
SPI2_DATA0o
SPI2_CLKo
CAN1_TX
RTC_WOT
SYSC_CKOT
SYSC_CKOTX
WDG_OBSERVE
POF=4
POF=5
POF=6
POF=7
PPG8_PPGB
OCU0_OTD0
RLT3_TOT
PPG0_PPGA
GPIO0_24i,
EIC0_INT09,
EIC0_INT10,
CAN1_RX,
ICU2_IN0
PPG1_PPGA
GPIO0_25i,
EIC0_INT08,
CAN0_RX,
ICU2_IN1,
ADC0_AN25
PPG8_PPGA
GPIO0_40i,
EIC0_INT05,
EIC0_INT12,
EIC0_INT11,
SPI2_SSi,
USART6_SIN,
USART0_SIN,
FRT0_FRCK,
RLT5_TIN,
ADC0_AN15
PPG9_PPGA
GPIO0_41i,
EIC0_INT15,
SPI2_DATA1i,
USART6_SCKi,
USART0_SCKi,
FRT1_FRCK,
RLT6_TIN,
ICU2_IN0,
ICU18_IN1,
ADC0_AN16
PPG10_PPGA
GPIO0_42i,
EIC0_INT08,
EIC0_INT10,
EIC0_INT11,
SPI2_DATA0i,
CAN0_RX,
FRT2_FRCK,
CAN1_RX,
ICU2_IN1,
ICU19_IN0,
USART0_SIN,
ADC0_AN17
PPG11_PPGA
GPIO0_43i,
EIC0_INT09,
SPI2_CLKi,
CAN1_RX,
FRT3_FRCK,
RLT2_TIN,
ADC0_AN18
PPG9_PPGB
OCU0_OTD1
RLT4_TOT
PPG64_PPGB OCU16_OTD0_G
USART6_SCKo PPG65_PPGB OCU16_OTD1_G
USART6_SOT PPG66_PPGB OCU17_OTD0_G
CAN0_TX
Possible
Resource
Function
inputs
PPG67_PPGB OCU17_OTD1_G
RLT2_TOT
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 3-3: Port Pin Multiplexing table (2 / 10)
Resource Functional Outputs
Register
(Offset
PCFGR044
(0x0058)
PCFGR045
(0x005A)
PCFGR046
(0x005C)
PCFGR047
(0x005E)
PCFGR048
(0x0060)
Port
P0_44
P0_45
P0_46
P0_47
P0_48
POF=0
GPIO0_44o
GPIO0_45o
GPIO0_46o
GPIO0_47o
GPIO0_48o
POF=1
SPI0_SSo
SPI0_DATA1o
SPI0_DATA0o
SPI0_CLKo
SPI1_SSo
POF=2
SPI2_SSO2
SPI2_SSO3
SPI2_SSO1
UDC0_UDOT0
SPI0_SSO2
POF=3
SPI2_DATA2o
SPI2_DATA3o
POF=4
POF=5
PPG68_PPGB OCU0_OTD0_G
POF=6
PPG12_PPGA
GPIO0_44i,
EIC0_INT03,
SPI2_DATA2i,
SPI0_Ssi,
FRT16_FRCK,
UDC0_AIN0,
ADC0_AN19
PPG13_PPGA
GPIO0_45i,
EIC0_INT11,
EIC0_INT12,
FRT16_FRCK,
FRT18_FRCK,
SPI2_DATA3i,
SPI0_DATA1i,
USART0_SIN,
USART6_SIN,
FRT17_FRCK,
RLT3_TIN,
FRT19_FRCK,
UDC0_BIN0,
ADC0_AN20
PPG14_PPGA
GPIO0_46i,
EIC0_INT16,
SPI0_DATA0i,
USART0_SCKi,
USART6_SCKi,
FRT18_FRCK,
RLT4_TIN,
UDC0_ZIN0,
ICU18_IN0,
ADC0_AN21
OCU16_OTD0_
PPG15_PPGA
GI
GPIO0_47i,
FRT0_FRCK,
FRT1_FRCK,
FRT2_FRCK,
EIC0_INT17,
FRT3_FRCK,
SPI0_CLKi,
FRT16_FRCK,
FRT17_FRCK,
FRT19_FRCK,
RLT0_TIN,
FRT18_FRCK,
EIC0_INT12,
ICU18_IN1,
USART6_SIN,
ADC0_AN22
RLT3_TOT
PPG69_PPGB OCU0_OTD1_G
USART0_SCKo PPG70_PPGB OCU1_OTD0_G
USART0_SOT PPG71_PPGB OCU1_OTD1_G
SPI0_DATA2o
PPG0_PPGB
OCU0_OTD0
POF=7
Possible
Resource
Function
inputs
RLT4_TOT
PPG64_PPGA
GPIO0_48i,
EIC0_INT04,
EIC0_INT09,
EIC0_INT08,
SPI0_DATA2i,
SPI1_Ssi,
CAN1_RX,
CAN0_RX,
ICU2_IN0,
UDC0_AIN1,
ADC0_AN23
PPG65_PPGA
GPIO0_49i,
EIC0_INT10,
SPI1_DATA1i,
ICU2_IN1,
CAN0_RX,
UDC0_BIN1,
ADC0_AN24
PCFGR049
(0x0062)
P0_49
GPIO0_49o
SPI1_DATA1o
PCFGR062
(0x007C)
P0_62
GPIO0_62o
I2C0_SCLo
GPIO0_62i,
EIC0_INT24,
I2C0_SCLi
PCFGR063
(0x007E)
P0_63
GPIO0_63o
I2C0_SDAo
GPIO0_63i,
EIC0_INT00,
I2C0_SDAi
PCFGR100
(0x0080)
P1_00
GPIO1_00o
SMC0_M2
SPI0_SSO1
January 30, 2015, MB9EF226_DS707-00004-2v1-E
CAN1_TX
PPG1_PPGB
PPG64_PPGB
OCU0_OTD1
RLT0_TOT
PPG0_PPGA
GPIO1_00i,
CAN0_RX,
EIC0_INT08,
EIC0_INT25,
ADC0_AN26
35
Data
Shee t
Table 3-3: Port Pin Multiplexing table (3 / 10)
Resource Functional Outputs
Register
(Offset
PCFGR101
(0x0082)
POF=0
POF=1
P1_01
GPIO1_01o
SMC0_P2
POF=2
POF=3
POF=4
POF=5
PPG65_PPGB
CAN0_TX
POF=6
POF=7
PPG1_PPGA
GPIO1_01i,
EIC0_INT26,
ADC0_AN26
PPG2_PPGA
GPIO1_02i,
EIC0_INT13,
CAN1_RX,
EIC0_INT09,
ADC0_AN26
PPG3_PPGA
GPIO1_03i,
EIC0_INT27,
ADC0_AN26
PCFGR102
(0x0084)
P1_02
GPIO1_02o
SMC0_M1
PPG66_PPGB
PCFGR103
(0x0086)
P1_03
GPIO1_03o
SMC0_P1
PPG67_PPGB
PCFGR104
(0x0088)
P1_04
GPIO1_04o
SMC1_M2
PPG68_PPGB
PPG4_PPGA
GPIO1_04i,
EIC0_INT28,
ADC0_AN27
PCFGR105
(0x008A)
P1_05
GPIO1_05o
SMC1_P2
PPG69_PPGB
PPG5_PPGA
GPIO1_05i,
EIC0_INT29,
ADC0_AN27
PCFGR106
(0x008C)
P1_06
GPIO1_06o
SMC1_M1
PPG70_PPGB
PPG6_PPGA
GPIO1_06i,
EIC0_INT30,
ADC0_AN27
PCFGR107
(0x008E)
P1_07
GPIO1_07o
SMC1_P1
PPG71_PPGB
PPG7_PPGA
GPIO1_07i,
EIC0_INT31,
ADC0_AN27
PPG8_PPGA
GPIO1_08i,
USART0_SIN,
RLT3_TIN,
EIC0_INT00,
SPI0_SSi,
ADC0_AN28,
EIC0_INT03,
EIC0_INT11
PCFGR108
(0x0090)
P1_08
GPIO1_08o
SMC2_M2
PPG0_PPGB
CAN1_TX
SPI0_SSo
PCFGR109
(0x0092)
P1_09
GPIO1_09o
SMC2_P2
PPG1_PPGB
SPI0_DATA1o
USART0_SCKo PPG9_PPGA
GPIO1_09i,
USART0_SCKi,
RLT4_TIN,
EIC0_INT01,
SPI0_DATA1i,
ICU2_IN1,
ADC0_AN28
PCFGR110
(0x0094)
P1_10
GPIO1_10o
SMC2_M1
PPG2_PPGB
SPI0_DATA0o
USART0_SOT PPG10_PPGA
GPIO1_10i,
EIC0_INT02,
SPI0_DATA0i,
ICU2_IN0,
ADC0_AN28
PCFGR111
(0x0096)
P1_11
GPIO1_11o
SMC2_P1
PPG3_PPGB
SPI0_CLKo
PPG11_PPGA
GPIO1_11i,
EIC0_INT03,
SPI0_CLKi,
RLT0_TIN,
ADC0_AN28
PPG12_PPGA
GPIO1_12i,
USART6_SIN,
RLT5_TIN,
EIC0_INT04,
SPI1_SSi,
ADC0_AN29,
EIC0_INT12
PCFGR112
(0x0098)
P1_12
GPIO1_12o
SMC3_M2
PPG4_PPGB
SPI1_SSo
PCFGR113
(0x009A)
P1_13
GPIO1_13o
SMC3_P2
PPG5_PPGB
SPI1_DATA1o
USART6_SCKo PPG13_PPGA
GPIO1_13i,
USART6_SCKi,
RLT6_TIN,
EIC0_INT05,
SPI1_DATA1i,
ICU18_IN0,
ADC0_AN29
PCFGR114
(0x009C)
P1_14
GPIO1_14o
SMC3_M1
PPG6_PPGB
SPI1_DATA0o
USART6_SOT PPG14_PPGA
GPIO1_14i,
EIC0_INT06,
SPI1_DATA0i,
ICU19_IN1,
ADC0_AN29
PPG15_PPGA
GPIO1_15i,
EIC0_INT07,
SPI1_CLKi,
RLT1_TIN,
ADC0_AN29
PCFGR115
(0x009E)
36
Port
Possible
Resource
Function
inputs
P1_15
GPIO1_15o
SMC3_P1
PPG7_PPGB
SPI1_CLKo
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 3-3: Port Pin Multiplexing table (4 / 10)
Resource Functional Outputs
Register
(Offset
Port
POF=0
POF=1
POF=2
POF=3
POF=4
POF=5
POF=6
POF=7
Possible
Resource
Function
inputs
PCFGR116
(0x00A0)
P1_16
GPIO1_16o
SMC4_M2
PPG8_PPGB
SPI2_SSo
SPI1_SSO2
PPG64_PPGA
GPIO1_16i,
EIC0_INT10,
EIC0_INT13,
SPI2_SSi,
ADC0_AN30,
EIC0_INT05
PCFGR117
(0x00A2)
P1_17
GPIO1_17o
SMC4_P2
PPG9_PPGB
SPI2_DATA1o
SPI1_SSO1
PPG65_PPGA
GPIO1_17i,
EIC0_INT14,
SPI2_DATA1i,
ADC0_AN30
PCFGR118
(0x00A4)
P1_18
GPIO1_18o
SMC4_M1
DMA0_DREQ_A
PPG10_PPGB
CK1
SPI2_DATA0o
SPI1_SSO3
PPG66_PPGA
GPIO1_18i,
EIC0_INT15,
SPI2_DATA0i,
ICU18_IN0,
ADC0_AN30
PPG67_PPGA
GPIO1_19i,
EIC0_INT16,
SPI2_CLKi,
ICU19_IN1,
RLT2_TIN,
ADC0_AN30
SG0_SGA
PCFGR119
(0x00A6)
P1_19
GPIO1_19o
SMC4_P1
PCFGR120
(0x00A8)
P1_20
GPIO1_20o
SMC5_M2
DMA0_DEOP1 PPG12_PPGB
PPG68_PPGA
GPIO1_20i,
EIC0_INT17,
ADC0_AN31
PCFGR121
(0x00AA)
P1_21
GPIO1_21o
SMC5_P2
PPG13_PPGB
PPG69_PPGA
GPIO1_21i,
EIC0_INT18,
DMA0_DREQ1,
ADC0_AN31
PCFGR122
(0x00AC)
P1_22
GPIO1_22o
SMC5_M1
PPG14_PPGB
PPG70_PPGA
GPIO1_22i,
EIC0_INT19,
DMA0_DSTP1,
ADC0_AN31
PCFGR123
(0x00AE)
P1_23
GPIO1_23o
SMC5_P1
PPG15_PPGB
PPG71_PPGA
GPIO1_23i,
EIC0_INT20,
DMA0_DEOP_AC
K1, ADC0_AN31
PCFGR126
(0x00B4)
P1_26
GPIO1_26o
DBG0_TRACE0 DMA0_DEOP0
I2S1_WSo
PPG71_PPGA
GPIO1_26i,
EIC0_INT07,
I2S1_Wsi,
ICU19_IN1
PCFGR127
(0x00B6)
P1_27
GPIO1_27o
DBG0_TRACE1
I2S1_SCKo
PCFGR128
(0x00B8)
P1_28
GPIO1_28o
DBG0_CTL
RLT3_TOT
GPIO1_28i,
EIC0_INT22,
DMA0_DSTP0
PCFGR129
(0x00BA)
P1_29
GPIO1_29o
DBG0_CLK
RLT4_TOT
GPIO1_29i,
EIC0_INT23,
DMA0_DEOP_AC
K0
SG0_SGO
DMA0_DSTP_A
PPG11_PPGB
CK1
PPG7_PPGB
SPI2_CLKo
OCU17_OTD1
GPIO1_27i,
EIC0_INT21,
DMA0_DREQ0,
I2S1_SCKi
PCFGR130
(0x00BC)
P1_30
GPIO1_30o
HSSPI0_SSO3
OCU0_OTD0
DBG0_TRACE2
DMA0_DREQ_AC
K0
GPIO1_30i,
EIC0_INT11,
PPG_ETRG2,
GFX0_DCLKI,
USART0_SIN,
RLT3_TIN,
ADC0_EDGI
PCFGR131
(0x00BE)
P1_31
GPIO1_31o
HSSPI0_SSO2
OCU0_OTD1
USART0_SCKo DBG0_TRACE3
DMA0_DSTP_AC
K0
GPIO1_31i,
EIC0_INT24,
USART0_SCKi,
ICU3_IN1,
RLT4_TIN
PCFGR132
(0x00C0)
P1_32
GPIO1_32o
HSSPI0_SSO1
OCU1_OTD0
USART0_SOT DBG0_TRACE4
PCFGR133
(0x00C2)
P1_33
GPIO1_33o
HSSPI0_SSo
OCU1_OTD1
PCFGR134
(0x00C4)
P1_34
GPIO1_34o
HSSPI0_DATA3
o
January 30, 2015, MB9EF226_DS707-00004-2v1-E
CAN0_TX
DBG0_TRACE5
GPIO1_32i,
EIC0_INT25,
ICU3_IN0
GPIO1_33i,
EIC0_INT01,
HSSPI0_SSi
GPIO1_34i,
EIC0_INT08,
HSSPI0_DATA3i,
CAN0_RX,
UDC0_AIN0
37
Data
Shee t
Table 3-3: Port Pin Multiplexing table (5 / 10)
Resource Functional Outputs
Register
(Offset
PCFGR135
(0x00C6)
POF=0
POF=1
P1_35
GPIO1_35o
HSSPI0_DATA2
o
POF=2
POF=3
POF=4
POF=5
POF=6
POF=7
GPIO1_35i,
EIC0_INT26,
HSSPI0_DATA2i,
ICU2_IN0,
UDC0_BIN0
CAN1_TX
GPIO1_36i,
EIC0_INT09,
HSSPI0_DATA1i,
CAN1_RX,
ICU2_IN1,
UDC0_ZIN0
PCFGR136
(0x00C8)
P1_36
GPIO1_36o
HSSPI0_DATA1
o
PCFGR137
(0x00CA)
P1_37
GPIO1_37o
HSSPI0_DATA0
UDC0_UDOT0
o
RLT5_TOT
GPIO1_37i,
EIC0_INT13,
HSSPI0_DATA0i,
ICU3_IN0
PCFGR138
(0x00CC)
P1_38
GPIO1_38o
HSSPI0_CLKo
RLT6_TOT
GPIO1_38i,
EIC0_INT10,
HSSPI0_CLKi,
ICU3_IN1/
PCFGR139
(0x00CE)
P1_39
GPIO1_39o
GFXSPI_SSO3
OCU16_OTD0
GPIO1_39i,
EIC0_INT12,
GFX0_DCLKI,
USART6_SIN,
RLT5_TIN
GPIO1_40i,
EIC0_INT27,
PPG_ETRG3,
USART6_SCKi,
RLT6_TIN,
ADC0_EDGI,
ICU2_IN0
PCFGR140
(0x00D0)
P1_40
GPIO1_40o
GFXSPI_SSO2
OCU16_OTD1
USART6_SCKo DBG0_TRACE6
PCFGR141
(0x00D2)
P1_41
GPIO1_41o
GFXSPI_SSO1
OCU17_OTD0
USART6_SOT DBG0_TRACE7
PCFGR142
(0x00D4)
P1_42
GPIO1_42o
GFXSPI_SSo
OCU17_OTD1
PCFGR143
(0x00D6)
PCFGR144
(0x00D8)
38
Port
Possible
Resource
Function
inputs
P1_43
P1_44
GPIO1_43o
GPIO1_44o
GFXSPI_DATA2
o
PPG6_PPGA
GPIO1_42i,
EIC0_INT02,
GFXSPI_SSi
PPG7_PPGA
GPIO1_43i,
EIC0_INT11,
GFXSPI_DATA3i,
USART0_SIN,
ICU18_IN0,
RLT3_TIN,
UDC0_AIN1
PPG8_PPGA
GPIO1_44i,
EIC0_INT29,
GFXSPI_DATA2i,
USART0_SCKi,
ICU18_IN1,
RLT4_TIN,
UDC0_BIN1
PPG1_PPGB
PPG9_PPGA
GPIO1_45i,
EIC0_INT30,
GFXSPI_DATA1i,
ICU19_IN0,
UDC0_ZIN1
PPG70_PPGB
GFXSPI_DATA3
o
GPIO1_41i,
EIC0_INT28,
ICU2_IN1
RLT3_TOT
PPG71_PPGB
USART0_SCKo PPG0_PPGB
RLT4_TOT
PCFGR145
(0x00DA)
P1_45
GPIO1_45o
GFXSPI_DATA1
o
PCFGR146
(0x00DC)
P1_46
GPIO1_46o
GFXSPI_DATA0
UDC0_UDOT1
o
PPG2_PPGB
PPG10_PPGA
GPIO1_46i,
EIC0_INT31,
GFXSPI_DATA0i,
ICU19_IN1
PCFGR147
(0x00DE)
P1_47
GPIO1_47o
GFXSPI_CLKo
PPG3_PPGB
PPG11_PPGA
GPIO1_47i,
EIC0_INT00,
GFXSPI_CLKi
PCFGR148
(0x00E0)
P1_48
GPIO1_48o
GFX0_TSIG0
PPG4_PPGB
PPG12_PPGA
GPIO1_48i,
EIC0_INT01
PCFGR149
(0x00E2)
P1_49
GPIO1_49o
GFX0_TSIG1
PPG5_PPGB
PPG13_PPGA
GPIO1_49i,
EIC0_INT02
PCFGR150
(0x00E4)
P1_50
GPIO1_50o
GFX0_TSIG2
PPG6_PPGB
PPG14_PPGA
GPIO1_50i,
EIC0_INT14
PCFGR151
(0x00E6)
P1_51
GPIO1_51o
GFX0_TSIG3
PPG7_PPGB
PPG15_PPGA
GPIO1_51i,
EIC0_INT15
PCFGR152
(0x00E8)
P1_52
GPIO1_52o
GFX0_TSIG4
PPG8_PPGB
PPG64_PPGA
GPIO1_52i,
EIC0_INT16,
ICU2_IN0
USART0_SOT
UDC0_UDOT0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 3-3: Port Pin Multiplexing table (6 / 10)
Resource Functional Outputs
Register
(Offset
Possible
Resource
Function
inputs
Port
POF=0
POF=1
PCFGR153
(0x00EA)
P1_53
GPIO1_53o
GFX0_TSIG5
PPG9_PPGB
PPG65_PPGA
GPIO1_53i,
EIC0_INT17,
ICU2_IN1,
UDC0_AIN0
PCFGR154
(0x00EC)
P1_54
GPIO1_54o
GFX0_TSIG6
PPG10_PPGB
PPG66_PPGA
GPIO1_54i,
EIC0_INT18,
ICU3_IN0,
UDC0_BIN0
PCFGR155
(0x00EE)
P1_55
GPIO1_55o
GFX0_TSIG7
PPG11_PPGB
PPG67_PPGA
GPIO1_55i,
EIC0_INT19,
ICU3_IN1,
UDC0_ZIN0
PCFGR156
(0x00F0)
P1_56
GPIO1_56o
GFX0_TSIG8
PPG12_PPGB
PPG68_PPGA
GPIO1_56i,
EIC0_INT20,
ICU18_IN0
PCFGR157
(0x00F2)
P1_57
GPIO1_57o
GFX0_TSIG9
PPG13_PPGB
PPG69_PPGA
GPIO1_57i,
EIC0_INT21,
ICU18_IN1,
UDC0_AIN1
PCFGR158
(0x00F4)
P1_58
GPIO1_58o
GFX0_TSIG10
PPG14_PPGB
PPG70_PPGA
GPIO1_58i,
EIC0_INT22,
ICU19_IN0,
UDC0_BIN1
PCFGR159
(0x00F6)
P1_59
GPIO1_59o
GFX0_TSIG11
PPG15_PPGB
PPG71_PPGA
GPIO1_59i,
EIC0_INT23,
ICU19_IN1,
UDC0_ZIN1
PCFGR160
(0x00F8)
P1_60
GPIO1_60o
OCU17_OTD1 OCU17_OTD1_G OCU17_OTD1_I PPG70_PPGB OCU17_OTD1_GI
PPG6_PPGA
GPIO1_60i,
MLB0_CLKi,
EIC0_INT00
PCFGR161
(0x00FA
P1_61
GPIO1_61o
MLB0_SIGo
GPIO1_61i,
MLB0_SIGi,
EIC0_INT01
PCFGR162
(0x00FC)
P1_62
GPIO1_62o
MLB0_DATo
GPIO1_62i,
MLB0_DATi,
EIC0_INT02
PCFGR200
(0x0100)
P2_00
GPIO2_00o
GFX0_DISP0
PPG64_PPGB
PPG0_PPGA
GPIO2_00i,
EIC0_INT21
PCFGR201
(0x0102)
P2_01
GPIO2_01o
GFX0_DISP1
PPG65_PPGB
PPG1_PPGA
GPIO2_01i,
EIC0_INT22
PCFGR202
(0x0104)
P2_02
GPIO2_02o
GFX0_DISP2
PPG66_PPGB
PPG2_PPGA
GPIO2_02i,
EIC0_INT23,
FRT0_FRCK
PCFGR203
(0x0106)
P2_03
GPIO2_03o
GFX0_DISP3
PPG67_PPGB
PPG3_PPGA
GPIO2_03i,
EIC0_INT24,
FRT1_FRCK
PCFGR204
(0x0108)
P2_04
GPIO2_04o
GFX0_DISP4
PPG68_PPGB
PPG4_PPGA
GPIO2_04i,
EIC0_INT25,
FRT2_FRCK,
ICU2_IN0
PCFGR205
(0x010A)
P2_05
GPIO2_05o
GFX0_DISP5
PPG69_PPGB
PPG5_PPGA
GPIO2_05i,
EIC0_INT26,
FRT3_FRCK,
ICU2_IN1
PCFGR206
(0x010C)
P2_06
GPIO2_06o
GFX0_DISP6
PPG70_PPGB
PPG6_PPGA
GPIO2_06i,
EIC0_INT27,
FRT16_FRCK,
ICU3_IN0
PCFGR207
(0x010E)
P2_07
GPIO2_07o
GFX0_DISP7
PPG71_PPGB
PPG7_PPGA
GPIO2_07i,
EIC0_INT28,
FRT17_FRCK,
ICU3_IN1
PCFGR208
(0x0110)
P2_08
GPIO2_08o
GFX0_DISP8
PPG0_PPGB
OCU0_OTD0
PPG8_PPGA
GPIO2_08i,
EIC0_INT29,
FRT18_FRCK,
ICU18_IN0
PCFGR209
(0x0112)
P2_09
GPIO2_09o
GFX0_DISP9
PPG1_PPGB
OCU0_OTD1
PPG9_PPGA
GPIO2_09i,
EIC0_INT30,
FRT19_FRCK,
ICU18_IN1
PCFGR210
(0x0114)
P2_10
GPIO2_10o
GFX0_DISP10
PPG2_PPGB
OCU1_OTD0
PPG10_PPGA
GPIO2_10i
EIC0_INT31
FRT0_FRCK
ICU19_IN0
POF=2
UDC0_UDOT1
January 30, 2015, MB9EF226_DS707-00004-2v1-E
POF=3
POF=4
POF=5
POF=6
RLT4_TOT
POF=7
39
Data
Shee t
Table 3-3: Port Pin Multiplexing table (7 / 10)
Resource Functional Outputs
Register
(Offset
Port
POF=0
POF=1
PCFGR211
(0x0116)
P2_11
GPIO2_11o
PCFGR212
(0x0118)
P2_12
GPIO2_12o
PCFGR213
(0x011A)
GPIO2_13o
POF=3
POF=4
POF=5
GFX0_DISP11
PPG3_PPGB
OCU1_OTD1
PPG11_PPGA
GPIO2_11i,
EIC0_INT14,
FRT1_FRCK,
ICU19_IN1
GFX0_DISP12
PPG4_PPGB
OCU16_OTD0
PPG12_PPGA
GPIO2_12i,
EIC0_INT15,
FRT2_FRCK,
ICU2_IN0
PPG13_PPGA
GPIO2_13i,
USART0_SIN,
EIC0_INT11,
EIC0_INT16,
FRT3_FRCK,
ICU2_IN1,
RLT3_TIN
GFX0_DISP13
PPG5_PPGB
POF=6
OCU16_OTD1
POF=7
PCFGR214
(0x011C)
P2_14
GPIO2_14o
GFX0_DISP14
USART0_SCKo
OCU17_OTD0
GPIO2_14i,
USART0_SCKi,
EIC0_INT17,
FRT16_FRCK,
ICU3_IN0,
RLT4_TIN
PCFGR215
(0x011E)
P2_15
GPIO2_15o
GFX0_DISP15
USART0_SOT
OCU17_OTD1
GPIO2_15i,
EIC0_INT18,
FRT17_FRCK,
ICU3_IN1
PCFGR216
(0x0120)
P2_16
GPIO2_16o
GFX0_DISP16
OCU17_OTD0
PPG6_PPGB
PPG14_PPGA
GPIO2_16i,
EIC0_INT19,
FRT18_FRCK,
ICU3_IN0
PCFGR217
(0x0122)
P2_17
GPIO2_17o
GFX0_DISP17
OCU17_OTD1
PPG7_PPGB
PPG15_PPGA
GPIO2_17i,
EIC0_INT20,
FRT19_FRCK,
ICU3_IN1
PCFGR218
(0x0124)
P2_18
GPIO2_18o
GFX0_DISP18
SPI2_SSo
RLT0_TOT
GPIO2_18i,
SPI2_SSi,
EIC0_INT21,
EIC0_INT05
PCFGR219
(0x0126)
P2_19
GPIO2_19o
GFX0_DISP19
SPI2_DATA1o
RLT1_TOT
GPIO2_19i,
SPI2_DATA1i,
EIC0_INT22
PCFGR220
(0x0128)
P2_20
GPIO2_20o
GFX0_DISP20
SPI2_DATA0o
OCU0_OTD0
PPG64_PPGB
RLT2_TOT
PPG0_PPGA
GPIO2_20i,
SPI2_DATA0i,
EIC0_INT23
PCFGR221
(0x012A)
P2_21
GPIO2_21o
GFX0_DISP21
SPI2_CLKo
OCU0_OTD1
PPG65_PPGB
RLT5_TOT
PPG1_PPGA
GPIO2_21i,
SPI2_CLKi,
EIC0_INT24,
RLT2_TIN
PCFGR222
(0x012C)
P2_22
GPIO2_22o
GFX0_DISP22
SPI0_CLKo
OCU1_OTD0
PPG66_PPGB
SPI2_DATA2o
PPG2_PPGA
GPIO2_22i,
SPI0_CLKi,
SPI2_DATA2i,
EIC0_INT25,
RLT0_TIN
PCFGR223
(0x012E)
P2_23
GPIO2_23o
GFX0_DISP23
SPI0_DATA1o
OCU1_OTD1
PPG67_PPGB
SPI2_DATA3o
SPI2_SSO3
PPG3_PPGA
GPIO2_23i,
SPI0_DATA1i,
SPI2_DATA3i,
EIC0_INT26,
RLT1_TIN
PCFGR224
(0x0130)
P2_24
GPIO2_24o
GFX0_DISP24
SPI0_DATA0o
OCU16_OTD0 PPG68_PPGB
SG0_SGO
SPI2_SSO2
PPG4_PPGA
GPIO2_24i,
SPI0_DATA0i,
EIC0_INT27,
ICU19_IN0,
RLT2_TIN
PPG5_PPGA
GPIO2_25i,
SPI0_SSi,
EIC0_INT28,
EIC0_INT03,
ICU19_IN1,
RLT5_TIN
PCFGR225
(0x0132)
40
P2_13
POF=2
Possible
Resource
Function
inputs
P2_25
GPIO2_25o
GFX0_DISP25
SPI0_SSo
OCU16_OTD1 PPG69_PPGB
SG0_SGA
SPI2_SSO1
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 3-3: Port Pin Multiplexing table (8 / 10)
Resource Functional Outputs
Register
(Offset
PCFGR232
(0x0140)
PCFGR233
(0x0142)
PCFGR234
(0x0144)
PCFGR235
(0x0146)
PCFGR236
(0x0148)
PCFGR237
(0x014A)
PCFGR238
(0x014C)
Port
P2_32
P2_33
P2_34
P2_35
P2_36
P2_37
P2_38
POF=0
GPIO2_32o
GPIO2_33o
GPIO2_34o
GPIO2_35o
GPIO2_36o
GPIO2_37o
GPIO2_38o
POF=1
SPI2_SSo
POF=2
UDC0_UDOT0
SPI2_DATA1o
I2S0_SDo
SPI2_DATA0o
SPI2_CLKo
SPI1_SSo
I2S0_WSo
I2S0_SCKo
UDC0_UDOT1
SPI1_DATA1o
SPI1_DATA0o
January 30, 2015, MB9EF226_DS707-00004-2v1-E
I2S1_SDo
I2S1_WSo
POF=3
SPI1_DATA2o
SPI1_DATA3o
POF=4
PPG8_PPGB
PPG9_PPGB
OCU1_OTD1_I PPG10_PPGB
OCU1_OTD0_I PPG11_PPGB
PPG12_PPGB
PPG13_PPGB
OCU17_OTD1_I PPG14_PPGB
POF=5
OCU0_OTD0
OCU0_OTD1
OCU1_OTD0
OCU1_OTD1
OCU16_OTD0
OCU16_OTD1
OCU17_OTD0
POF=6
POF=7
Possible
Resource
Function
inputs
PPG0_PPGA
GPIO2_32i,
I2S0_ECLK,
I2S1_ECLK,
SPI1_DATA2i,
SPI2_Ssi,
SPI0_Ssi,
ICU2_IN0,
EIC0_INT05,
EIC0_INT03,
ADC0_EDGI
RLT8_TOT
PPG1_PPGA
GPIO2_33i,
I2S0_Sdi,
I2S1_Sdi,
SPI1_DATA3i,
UDC0_AIN0,
SPI2_DATA1i,
SPI0_DATA1i,
ICU2_IN1,
EIC0_INT26,
ADC0_AN0
RLT7_TOT
GPIO2_34i,
I2S0_WSi,I2S1_W
Si, UDC0_BIN0,
SPI2_DATA0i,
PPG2_PPGA
SPI0_DATA0i,
ICU3_IN0,
EIC0_INT06,
EIC0_INT07,
ADC0_AN1
RLT9_TOT
PPG3_PPGA
GPIO2_35i,
I2S0_SCKi,
I2S1_SCKi,
UDC0_ZIN0,
SPI2_CLKi,
SPI0_CLKi,
RLT2_TIN,
ICU3_IN1,
EIC0_INT29,
ADC0_AN2
PPG4_PPGA
GPIO2_36i,
I2S1_ECLK,
I2S0_ECLK,
SPI1_SSi,
SPI2_SSi,
RLT9_TIN,
ICU18_IN0,
EIC0_INT04,
EIC0_INT05,
ADC0_AN3
PPG5_PPGA
GPIO2_37i,
I2S1_SDi,
I2S0_SDi,
UDC0_AIN1,
SPI1_DATA1i,
SPI2_DATA1i,
RLT8_TIN,
ICU18_IN1,
EIC0_INT30,
ADC0_AN4
OCU17_OTD1_
PPG6_PPGA
GI
GPIO2_38i,
I2S1_WSi,
I2S0_WSi,
PPG_ETRG0,
UDC0_BIN1,
SPI1_DATA0i,
SPI2_DATA0i,
RLT7_TIN,
ICU19_IN0,
EIC0_INT06,
EIC0_INT07,
ADC0_AN5
41
Data
Shee t
Table 3-3: Port Pin Multiplexing table (9 / 10)
Resource Functional Outputs
Register
(Offset
PCFGR239
(0x014E)
PCFGR240
(0x0150)
PCFGR241
(0x0152)
PCFGR242
(0x0154)
PCFGR243
(0x0156)
PCFGR248
(0x0160)
PCFGR249
(0x0162)
42
Port
P2_39
P2_40
P2_41
P2_42
P2_43
P2_48
P2_49
POF=0
GPIO2_39o
GPIO2_40o
GPIO2_41o
GPIO2_42o
GPIO2_43o
GPIO2_48o
GPIO2_49o
POF=1
SPI1_CLKo
SPI0_SSo
SPI0_DATA1o
SPI0_DATA0o
SPI0_CLKo
SG0_SGA
SG0_SGO
POF=2
I2S1_SCKo
reserved
reserved
reserved
reserved
CAN1_TX
I2S1_SDo
POF=3
POF=4
OCU17_OTD0_I PPG15_PPGB
OCU1_OTD1_G
PPG64_PPGB
I
OCU1_OTD0_G
PPG65_PPGB
I
SG0_SGA
SG0_SGO
POF=5
OCU17_OTD1
OCU0_OTD1_I
OCU0_OTD0_I
PPG66_PPGB OCU0_OTD1_GI
POF=6
OCU17_OTD0_
PPG7_PPGA
GI
USART6_SOT PPG69_PPGB OCU16_OTD0_I
GPIO2_39i,
I2S1_SCKi,
I2S0_SCKi,
PPG_ETRG1,
UDC0_ZIN1,
SPI1_CLKi,
SPI2_CLKi,
RLT1_TIN,
ICU19_IN1,
EIC0_INT31,
ADC0_AN6
PPG8_PPGA
GPIO2_40i,
I2S0_ECLK,
SPI0_SSi,
SPI1_SSi,
ICU2_IN0,
FRT16_FRCK,
CAN1_RX,
EIC0_INT03,
EIC0_INT04,
EIC0_INT10,
ADC0_AN7
PPG9_PPGA
GPIO2_41i,
I2S0_Sdi,
CAN0_RX,
CAN1_RX,
SPI0_DATA1i,
SPI1_DATA1i,
RLT8_TIN,
ICU2_IN1,
FRT17_FRCK,
EIC0_INT08,
EIC0_INT09,
ADC0_AN8
OCU16_OTD1_
PPG10_PPGA
GI
GPIO2_42i,
I2S0_WSi,
SPI0_DATA0i,
SPI1_DATA0i,
RLT9_TIN,
ICU3_IN0,
FRT18_FRCK,
EIC0_INT06,
ADC0_AN9
PPG11_PPGA
GPIO2_43i,
I2S0_SCKi,
EIC0_NMI,
SPI0_CLKi,
SPI1_CLKi,
RLT0_TIN,
ICU3_IN1,
FRT19_FRCK,
ADC0_AN10
PPG12_PPGA
GPIO2_48i,
I2S1_ECLK,
RLT6_TIN,
CAN0_RX,
ICU18_IN0,
FRT0_FRCK,
USART6_SCKi,
USART0_SCKi,
EIC0_INT08,
ADC0_AN11
PPG13_PPGA
GPIO2_49i,
I2S1_Sdi,
CAN1_RX,
FRT0_FRCK,
EIC0_INT08,
RLT7_TIN,
ICU18_IN1,
FRT1_FRCK,
FRT2_FRCK,
FRT3_FRCK,
CAN0_RX,
EIC0_INT09,
ADC0_AN12
RLT8_TOT
RLT9_TOT
PPG67_PPGB OCU0_OTD0_GI
USART6_SCKo PPG68_PPGB OCU16_OTD1_I
POF=7
Possible
Resource
Function
inputs
RLT7_TOT
RLT1_TOT
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 3-3: Port Pin Multiplexing table (10 / 10)
Resource Functional Outputs
Register
(Offset
PCFGR250
(0x0164)
PCFGR251
(0x0166)
Port
P2_50
P2_51
POF=0
GPIO2_50o
GPIO2_51o
POF=1
SPI1_DATA0o
SPI1_CLKo
POF=2
SPI0_SSO3
UDC0_UDOT1
January 30, 2015, MB9EF226_DS707-00004-2v1-E
POF=3
SPI0_DATA3o
CAN0_TX
POF=4
PPG2_PPGB
PPG3_PPGB
POF=5
OCU1_OTD0
OCU1_OTD1
POF=6
I2S1_WSo
I2S1_SCKo
POF=7
Possible
Resource
Function
inputs
PPG66_PPGA
GPIO2_50i,
EIC0_INT08,
RLT5_TIN,
I2S1_WSi,
EIC0_INT07,
SPI0_DATA3i,
SPI1_DATA0i,
CAN0_RX,
EIC0_INT11,
ICU3_IN0,
EIC0_INT12,
FRT2_FRCK,
CAN1_RX,
UDC0_ZIN1,
USART6_SIN,
USART0_SIN,
EIC0_INT09,
ADC0_AN13
PPG67_PPGA
GPIO2_51i,
EIC0_INT09,
FRT2_FRCK,
I2S1_SCKi,
FRT16_FRCK,
FRT17_FRCK,
SPI1_CLKi,
FRT18_FRCK,
CAN1_RX,
ICU3_IN1,
RLT1_TIN,
FRT3_FRCK,
FRT19_FRCK,
FRT0_FRCK,
FRT1_FRCK,
ADC0_AN14
43
Data
3.2.2
Resource input source table
3.2.2.1
RICFG0_ADC
Register
Resource
Register
(offset)
input
Field
Source for resource input
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
PORTPIN
OCU
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
OCU10
OCU11
reserved
reserved
reserved
reserved
0: Pins selected by
PORTSEL
registers will be
ADC0EDGIL
disabled
1: Pins selected by
PORTSEL
registers will be
enabled for ADC0
trigger.
ADC0EDGI
(0x000C)
ADC0_EDGI
PORTSEL
ADC0EDGIH
Shee t
All the signals
that are enabled
by the
ADC0EDGIOCU
n registers
ANDed together.
-
000:reserved
001: reserved
010: P1_30 is
selected
011: P1_40 is
selected
100: reserved
101: P2_32 is
selected
110: reserved
111: reserved
OCU00
OCU01
ADC0EDGIOC 0: OCU0_OTD0 is 0: OCU0_OTD1 0: OCU1_OTD0 0: OCU1_OTD1
U0L
disabled
is disabled
is disabled
is disabled
1: OCU0_OTD0 is 1: OCU0_OTD1 1: OCU1_OTD0 1: OCU1_OTD1
ADC0EDGIOCU
ADC0_EDGI
enabled
is
enabled
is
enabled
is enabled
0 (0x000E)
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
ADC0EDGIOCU
ADC0_EDGI
1 (0x0010)
-
ADC0EDGIOCU
ADC0_EDGI
2 (0x0012)
-
ADC0EDGIOCU
ADC0_EDGI
3 (0x0014)
reserved
reserved
reserved
reserved
OCU160
OCU161
OCU170
OCU171
ADC0EDGIOC 0: OCU16_OTD0 0: OCU16_OTD1 0: OCU17_OTD0 0: OCU17_OTD1
U4L
is disabled
is disabled
is disabled
is disabled
1: OCU16_OTD0 1: OCU16_OTD1 1: OCU17_OTD0 1: OCU17_OTD1
ADC0EDGIOCU
ADC0_EDGI
is enabled
is enabled
is enabled
is enabled
4 (0x0016)
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
44
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Register
Resource
Register
(offset)
input
Field
Sh eet
Source for resource input
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RLT
PPGL
PPGH
-
-
reserved
reserved
reserved
reserved
reserved
ADC0EDGIOCU
ADC0_EDGI
5 (0x0018)
-
ADC0EDGIOCU
ADC0_EDGI
6 (0x001A)
-
ADC0EDGIOCU
ADC0_EDGI
7 (0x001C)
-
ADC0TIMI
(0x001E)
ADC0_TIMI
ADTRGH and
ADTRGL signals
of PPG0 to
PPG63 OR-ed All the signals for
UFSET output of
together which the
RLT that is
ADC0TIMIL
disabled (0), corresponding bit
selected by
enabled (1). All is set are OR-ed
ADC0TIMIRLT bits
the signals for
together is
[3:0] is disabled
which the
disable (0) or
(0) or enabled (1)
corresponding bit
enabled (1)
is set are OR-ed
together,is
enabled (2).
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
-
RLT
ADC0TIMIRLTL
ADC0TIMIRLT
(0x0020)
ADC0_TIMI
0000:
RLT0_UFSET
0001:
RLT1_UFSET
...
1001:
RLT9_UFSET
1010 - 1111:
reserved
-
ZPDEN
ADC0ZPDEN1
(0x003E)
ADC0_ZPD
ADC0ZPDIEN
0: ZPD is disabled
1: ZPD is enabled
Note: The ADC0ZPDEN register is write-only-once protected.
January 30, 2015, MB9EF226_DS707-00004-2v1-E
45
Data
3.2.2.2
Register
ADC0AN26
(0x0000)
ADC0AN27
(0x0002)
ADC0AN28
(0x0004)
ADC0AN29
(0x0006)
ADC0AN30
(0x0008)
ADC0AN31
(0x000A)
ADC0EDGI 0
(0x00C)
FRT0TEXT
(0x0400)
FRT1TEXT
(0x0420)
FRT2TEXT
(0x0440)
46
Shee t
RICFG0
Resource
Input
RESSEL[3:0]/
Source for resource input
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
P1_00
P1_01
P1_02
P1_03
P1_00/P1_01
P1_01/P1_00
P1_02/P1_03
P1_03/P1_02
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
P1_04
P1_05
P1_06
P1_07
P1_04/P1_05
P1_05/P1_04
P1_06/P1_07
P1_07/P1_06
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL[3:0]
ADC0_AN26
ADC0_AN27
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
P1_08
P1_09
P1_10
P1_11
P1_08/P1_09
P1_09/P1_08
P1_10/P1_11
P1_11/P1_10
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
ADC0_AN28
ADC0_AN29
PORTSEL (0-7)
P1_12
P1_13
P1_14
P1_15
P1_12/P1_13
P1_13/P1_12
P1_14/P1_15
P1_15/P1_14
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
ADC0_AN30
PORTSEL (0-7)
P1_16
P1_17
P1_18
P1_19
P1_16/P1_17
P1_17/P1_16
P1_18/P1_19
P1_19/P1_18
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
P1_20
P1_21
P1_22
P1_23
P1_20/P1_21
P1_21/P1_20
P1_22/P1_23
P1_23/P1_22
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
ADC0_AN31
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P1_30
P1_40
reserved
P2_32
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PORT_PIN
RLT2_TOT
RLT3_TOT
RLT0_TOT
PPG10_PPGB
reserved
reserved
reserved
ADC0_EDGI
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
reserved
P0_40
P0_47
reserved
reserved
reserved
PORTSEL (8-15)
P2_48
P2_49
P2_51
P2_02
P2_10
reserved
reserved
reserved
RESSEL (0-7)
PORT_PIN
RLT2_TOT
RLT3_TOT
RLT1_TOT
PPG11_PPGB
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P0_41
P0_47
reserved
reserved
P2_49
P2_51
FRT0_TEXT
FRT1_TEXT
PORTSEL (8-15)
P2_03
P2_11
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PORT_PIN
RLT2_TOT
RLT3_TOT
RLT4_TOT
PPG12_PPGB
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
GND
P0_42
P0_47
reserved
reserved
reserved
PORTSEL (8-15)
P2_49
P2_50
P2_51
P2_04
P2_12
reserved
reserved
reserved
FRT2_TEXT
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Resource
Register
Input
RESSEL[3:0]/
PORTSEL[3:0]
RESSEL (0-7)
FRT3TEXT
(0x0460)
ICU2IN0
(0x0840)
ICU2IN1
(0x0842)
ICU2FRTSEL
(0x0844)
ICU3IN0
(0x0860)
ICU3IN1
(0x0862)
ICU2FRTSEL
(0x0864)
Sh eet
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
PORT_PIN
RLT2_TOT
RLT3_TOT
RLT5_TOT
PPG13_PPGB
reserved
reserved
reserved
Source for resource input
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P0_43
P0_47
reserved
reserved
P2_49
P2_51
PORTSEL (8-15)
P2_05
P2_13
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
FRT3_TEXT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
reserved
P0_24
reserved
P0_48
P1_35
P1_52
PORTSEL (8-15)
P0_41
P1_10
P2_32
P2_40
reserved
P1_40
P2_04
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
reserved
P0_25
reserved
P0_49
P1_36
P1_53
PORTSEL (8-15)
P0_42
P1_09
P2_33
P2_41
reserved
P1_41
P2_05
ICU2_IN0
P2_12
ICU2_IN1
P2_13
RESSEL (0-7)
FRT2
FRT0
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
ICU2_FRTSEL
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
reserved
reserved
reserved
P1_37
P1_54
P1_32
PORTSEL (8-15)
P2_34
P2_42
reserved
reserved
P2_50
P2_06
P2_14
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
P1_31
ICU3_IN0
P2_16
ICU3_IN1
PORTSEL (0-7)
reserved
reserved
reserved
reserved
reserved
P1_38
P1_55
PORTSEL (8-15)
P2_35
P2_43
reserved
reserved
P2_51
P2_07
P2_15
RESSEL (0-7)
FRT3
FRT1
ICU2
reserved
reserved
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
RLT4_TOT
RLT0_TOT
PPG5_PPGA
PPG6_PPGA
OCU1_OTD0
OCU1_OTD1
reserved
reserved
P2_17
ICU2_FRTSEL
OCU0OTD0GAT OCU0_OTD0GAT
E (0x0C00)
E
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (8-15)
RESSEL (0-7)
OCU0OTD0GM
(0x0C02)
Da ta
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
OCU0_OTD0GM
OCU0OTD1GAT OCU0_OTD1GAT
E (0x0C04)
E
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
RLT4_TOT
RLT1_TOT
PPG5_PPGA
PPG7_PPGA
OCU1_OTD0
OCU1_OTD1
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
January 30, 2015, MB9EF226_DS707-00004-2v1-E
47
Data
Resource
Register
Input
RESSEL[3:0]/
PORTSEL[3:0]
RESSEL (0-7)
OCU0OTD1GM
(0x0C06)
OCU1CMP0EXT
OCU1_CMP0EXT
(0x0C20)
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
reserved
reserved
reserved
reserved
reserved
reserved
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
OCU0_CMP0O
OCU1_MTRG
UT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
FRT1_CNT_EN FRT0_CNT_EN
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
RLT4_TOT
RLT2_TOT
PPG5_PPGA
PPG8_PPGA
OCU0_OTD0
OCU0_OTD1
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
RLT4_TOT
RLT3_TOT
PPG5_PPGA
PPG9_PPGA
OCU0_OTD0
OCU0_OTD1
reserved
reserved
OCU1_OTD0GM
OCU1OTD1GAT OCU1_OTD1GAT
E (0x0C28)
E
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
PORTSEL (8-15)
RESSEL (0-7)
USART0SIN
(0x1402)
Bit 3
OCU1_FRTSEL
OCU1OTD0GAT OCU1_OTD0GAT
E (0x0C24)
E
USART0SCKI
(0x1400)
Bit 2
RESSEL (8-15)
RESSEL (0-7)
OCU1OTD1GM
(0x0C2A)
Bit 1
PORTSEL (0-7)
PORTSEL (8-15)
OCU1OTD0GM
(0x0C26)
Source for resource input
Bit 0
OCU0_OTD1GM
RESSEL (0-7)
OCU1FRTSEL
(0x0C22)
Shee t
RESSEL (8-15)
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
OCU1_OTD1GM
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
USART0_SCKI
PORTSEL (0-7)
reserved
reserved
P0_41
P0_46
P1_31
P1_44
P1_09
GND
PORTSEL (8-15)
reserved
P2_48
P2_14
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
USART0_SIN
PPG0PPGAGAT PPG0_PPGAGAT
E (0x1C00)
E
PORTSEL (0-7)
reserved
reserved
reserved
P0_40
P0_45
P1_30
P1_43
P0_42
PORTSEL (8-15)
P1_08
reserved
reserved
reserved
P2_50
P2_13
reserved
reserved
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
48
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Resource
Register
Input
RESSEL[3:0]/
PORTSEL[3:0]
RESSEL (0-7)
PPG0PPGAGM
(0x1C02)
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
reserved
reserved
reserved
reserved
reserved
reserved
Source for resource input
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PPG0_PPGBGM
PPG1PPGAGAT PPG1_PPGAGAT
E (0x1C20)
E
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
PPG1_PPGAGM
PPG1PPGBGAT PPG1_PPGBGAT
E (0x1C24)
E
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
PORTSEL (8-15)
RESSEL (0-7)
RESSEL (8-15)
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
PPG1_PPGBGM
PPG2PPGAGAT PPG2_PPGAGAT
E (0x1C40)
E
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (8-15)
RESSEL (0-7)
PPG2PPGAGM
(0x1C42)
Bit 1
RESSEL (8-15)
RESSEL (0-7)
PPG1PPGBGM
(0x1C26)
Bit 0
PORTSEL (0-7)
PORTSEL (8-15)
PPG1PPGAGM
(0x1C22)
Sh eet
PPG0_PPGAGM
PPG0PPGBGAT PPG0_PPGBGAT
E (0x1C04)
E
PPG0PPGBGM
(0x1C06)
Da ta
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
PPG2_PPGAGM
PPG2PPGBGAT PPG2_PPGBGAT
E (0x1C44)
E
January 30, 2015, MB9EF226_DS707-00004-2v1-E
49
Data
Resource
Register
Input
RESSEL[3:0]/
PORTSEL[3:0]
RESSEL (0-7)
PPG2PPGBGM
(0x1C46)
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
reserved
reserved
reserved
reserved
reserved
reserved
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
PPG3_PPGBGM
PPG4PPGAGAT PPG4_PPGAGAT
E (0x1C80)
E
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
PORTSEL (8-15)
RESSEL (0-7)
RESSEL (8-15)
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
PPG4_PPGAGM
PPG4PPGBGAT PPG4_PPGBGAT
E (0x1C84)
E
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (8-15)
RESSEL (0-7)
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
PPG4_PPGBGM
PPG5PPGAGAT PPG5_PPGAGAT
E (0x1CA0)
E
50
Bit 3
PPG3_PPGAGM
PPG3PPGBGAT PPG3_PPGBGAT
E (0x1C64)
E
PPG4PPGBGM
(0x1C86)
Bit 2
RESSEL (8-15)
RESSEL (0-7)
PPG4PPGAGM
(0x1C82)
Bit 1
PORTSEL (0-7)
PORTSEL (8-15)
PPG3PPGBGM
(0x1C66)
Source for resource input
Bit 0
PPG2_PPGBGM
PPG3PPGAGAT PPG3_PPGAGAT
E (0x1C60)
E
PPG3PPGAGM
(0x1C62)
Shee t
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Resource
Register
Input
RESSEL[3:0]/
PORTSEL[3:0]
RESSEL (0-7)
PPG5PPGAGM
(0x1CA2)
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
reserved
reserved
reserved
reserved
reserved
reserved
Source for resource input
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PPG5_PPGBGM
PPG6PPGAGAT PPG6_PPGAGAT
E (0x1CC0)
E
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
PPG6_PPGAGM
PPG6PPGBGAT PPG6_PPGBGAT
E (0x1CC4)
E
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
PORTSEL (8-15)
RESSEL (0-7)
RESSEL (8-15)
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
PPG6_PPGBGM
PPG7PPGAGAT PPG7_PPGAGAT
E (0x1CE0)
E
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (8-15)
RESSEL (0-7)
PPG7PPGAGM
(0x1CE2)
Bit 1
RESSEL (8-15)
RESSEL (0-7)
PPG6PPGBGM
(0x1CC6)
Bit 0
PORTSEL (0-7)
PORTSEL (8-15)
PPG6PPGAGM
(0x1CC2)
Sh eet
PPG5_PPGAGM
PPG5PPGBGAT PPG5_PPGBGAT
E (0x1CA4)
E
PPG5PPGBGM
(0x1CA6)
Da ta
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
PPG7_PPGAGM
PPG7PPGBGAT PPG7_PPGBGAT
E (0x1CE4)
E
January 30, 2015, MB9EF226_DS707-00004-2v1-E
51
Data
Resource
Register
Input
RESSEL[3:0]/
PORTSEL[3:0]
RESSEL (0-7)
PPG7PPGBGM
(0x1CE6)
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
reserved
reserved
reserved
reserved
reserved
reserved
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
PPG8_PPGBGM
PPG9PPGAGAT PPG9_PPGAGAT
E (0x1D20)
E
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
PORTSEL (8-15)
RESSEL (0-7)
RESSEL (8-15)
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
PPG9_PPGAGM
PPG9PPGBGAT PPG9_PPGBGAT
E (0x1D24)
E
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (8-15)
RESSEL (0-7)
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
PPG9_PPGBGM
PPG10PPGAGAT PPG10_PPGAGAT
E (0x1D40)
E
52
Bit 3
PPG8_PPGAGM
PPG8PPGBGAT PPG8_PPGBGAT
E (0x1D04)
E
PPG9PPGBGM
(0x1D26)
Bit 2
RESSEL (8-15)
RESSEL (0-7)
PPG9PPGAGM
(0x1D22)
Bit 1
PORTSEL (0-7)
PORTSEL (8-15)
PPG8PPGBGM
(0x1D06)
Source for resource input
Bit 0
PPG7_PPGBGM
PPG8PPGAGAT PPG8_PPGAGAT
E (0x1D00)
E
PPG8PPGAGM
(0x1D02)
Shee t
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Resource
Register
Input
RESSEL[3:0]/
PORTSEL[3:0]
RESSEL (0-7)
PPG10PPGAGM
PPG10_PPGAGM
(0x1D42)
PPG10PPGBGAT PPG10_PPGBGAT
E (0x1D44)
E
PPG11PPGBGAT PPG11_PPGBGAT
E (0x1D64)
E
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
reserved
reserved
reserved
reserved
reserved
reserved
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
RESSEL (8-15)
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PPG12PPGBGAT PPG12_PPGBGAT
E (0x1D84)
E
Bit 4
-
PORTSEL (8-15)
PPG12PPGAGM
PPG12_PPGAGM
(0x1D82)
Bit 3
Source for resource input
-
RESSEL (0-7)
PPG12PPGAGAT PPG12_PPGAGAT
E (0x1D80)
E
Bit 2
-
PORTSEL (8-15)
PPG11PPGBGM
PPG11_PPGBGM
(0x1D66)
Bit 1
-
RESSEL (0-7)
PPG11PPGAGM
PPG11_PPGAGM
(0x1D62)
Bit 0
RESSEL (8-15)
RESSEL (0-7)
PPG11PPGAGAT PPG11_PPGAGAT
E (0x1D60)
E
Sh eet
PORTSEL (0-7)
PORTSEL (8-15)
PPG10PPGBGM
PPG10_PPGBGM
(0x1D46)
Da ta
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
January 30, 2015, MB9EF226_DS707-00004-2v1-E
53
Data
Resource
Register
Input
RESSEL[3:0]/
PORTSEL[3:0]
RESSEL (0-7)
PPG12PPGBGM
PPG12_PPGBGM
(0x1D86)
PPG13PPGAGAT PPG13_PPGAGAT
E (0x1DA0)
E
PPG14PPGAGAT PPG14_PPGAGAT
E (0x1DC0)
E
54
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
reserved
reserved
reserved
reserved
reserved
reserved
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
RESSEL (8-15)
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PPG15PPGAGAT PPG15_PPGAGAT
E (0x1DE0)
E
Bit 5
-
PORTSEL (8-15)
PPG14PPGBGM
PPG14_PPGBGM
(0x1DC6)
Bit 4
-
RESSEL (0-7)
PPG14PPGBGAT PPG14_PPGBGAT
E (0x1DC4)
E
Bit 3
-
PORTSEL (8-15)
PPG14PPGAGM
PPG14_PPGAGM
(0x1DC2)
Bit 2
-
RESSEL (0-7)
PPG13PPGBGM
PPG13_PPGBGM
(0x1DA6)
Bit 1
RESSEL (8-15)
RESSEL (0-7)
PPG13PPGBGAT PPG13_PPGBGAT
E (0x1DA4)
E
Source for resource input
Bit 0
PORTSEL (0-7)
PORTSEL (8-15)
PPG13PPGAGM
PPG13_PPGAGM
(0x1DA2)
Shee t
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Resource
Register
Input
RESSEL[3:0]/
PORTSEL[3:0]
RESSEL (0-7)
PPG15PPGAGM
PPG15_PPGAGM
(0x1DE2)
PPG15PPGBGAT PPG15_PPGBGAT
E (0x1DE4)
E
PPGGRP0ETRG PPGGRP0_ETRG
1 (0x2402)
1
PPGGRP0ETRG PPGGRP0_ETRG
2 (0x2404)
2
PPGGRP0ETRG PPGGRP0_ETRG
3 (0x2406)
3
PPGGRP0RLTTR PPGGRP0_RLTTR
G1 (0x2408)
G1
PPGGRP1ETRG PPGGRP1_ETRG
0 (0x2420)
0
PPGGRP1ETRG PPGGRP1_ETRG
1 (0x2422)
1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
reserved
reserved
reserved
reserved
reserved
reserved
Source for resource input
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
RESSEL (0-7)
PPGGRP0ETRG PPGGRP0_ETRG
0 (0x2400)
0
Sh eet
PORTSEL (0-7)
PORTSEL (8-15)
PPG15PPGBGM
PPG15_PPGBGM
(0x1DE6)
Da ta
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
PORT_PIN
OCU0_OTD0
OCU0_OTD1
OCU1_OTD0
OCU1_OTD1
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
PORT_PIN
OCU0_OTD0
OCU0_OTD1
OCU1_OTD0
OCU1_OTD1
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
PORT_PIN
reserved
reserved
reserved
OCU16_OTD0 OCU16_OTD1 OCU17_OTD0 OCU17_OTD1
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
PORT_PIN
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
OCU16_OTD0 OCU16_OTD1 OCU17_OTD0 OCU17_OTD1
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RLT8_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
PORT_PIN
OCU0_OTD0
OCU0_OTD1
OCU1_OTD0
OCU1_OTD1
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
PORT_PIN
OCU0_OTD0
OCU0_OTD1
OCU1_OTD0
OCU1_OTD1
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
January 30, 2015, MB9EF226_DS707-00004-2v1-E
55
Data
Resource
Register
Input
RESSEL[3:0]/
PORTSEL[3:0]
RESSEL (0-7)
PPGGRP1ETRG PPGGRP1_ETRG
2 (0x2424)
2
PPGGRP1ETRG PPGGRP1_ETRG
3 (0x2426)
3
PPGGRP1RLTTR PPGGRP1_RLTTR
G1 (0x2428)
G1
PPGGRP2ETRG PPGGRP2_ETRG
0 (0x2440)
0
PPGGRP2ETRG PPGGRP2_ETRG
1 (0x2442)
1
PPGGRP2ETRG PPGGRP2_ETRG
2 (0x2444)
2
PPGGRP2ETRG PPGGRP2_ETRG
3 (0x2446)
3
PPGGRP2RLTTR PPGGRP2_RLTTR
G1 (0x2448)
G1
PPGGRP3ETRG PPGGRP3_ETRG
0 (0x2460)
0
PPGGRP3ETRG PPGGRP3_ETRG
1 (0x2462)
1
56
Shee t
Source for resource input
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
reserved
reserved
reserved
PORT_PIN
OCU16_OTD0 OCU16_OTD1 OCU17_OTD0 OCU17_OTD1
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
PORT_PIN
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
OCU16_OTD0 OCU16_OTD1 OCU17_OTD0 OCU17_OTD1
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RLT8_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
PORT_PIN
OCU0_OTD0
OCU0_OTD1
OCU1_OTD0
OCU1_OTD1
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
PORT_PIN
OCU0_OTD0
OCU0_OTD1
OCU1_OTD0
OCU1_OTD1
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
PORT_PIN
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
PORT_PIN
reserved
reserved
reserved
OCU16_OTD0 OCU16_OTD1 OCU17_OTD0 OCU17_OTD1
OCU16_OTD0 OCU16_OTD1 OCU17_OTD0 OCU17_OTD1
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RLT8_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
PORT_PIN
OCU0_OTD0
OCU0_OTD1
OCU1_OTD0
OCU1_OTD1
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
PORT_PIN
OCU0_OTD0
OCU0_OTD1
OCU1_OTD0
OCU1_OTD1
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Resource
Register
Input
RESSEL[3:0]/
PORTSEL[3:0]
RESSEL (0-7)
PPGGRP3ETRG PPGGRP3_ETRG
2 (0x2464)
2
PPGGRP3ETRG PPGGRP3_ETRG
3 (0x2466)
3
PPGGRP3RLTTR PPGGRP3_RLTTR
G1 (0x2468)
G1
Da ta
Sh eet
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
reserved
reserved
reserved
Source for resource input
PORT_PIN
OCU16_OTD0 OCU16_OTD1 OCU17_OTD0 OCU17_OTD1
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
PORT_PIN
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
OCU16_OTD0 OCU16_OTD1 OCU17_OTD0 OCU17_OTD1
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RLT8_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
January 30, 2015, MB9EF226_DS707-00004-2v1-E
57
Data
3.2.2.3
Register
CAN0RX
(0x0400)
CAN1RX
(0x0420)
FRT16TEXT
(0x0C00)
FRT17TEXT
(0x0C20)
FRT18TEXT
(0x0C40)
FRT19TEXT
(0x0C60)
ICU18IN0
(0x1040)
ICU18IN1
(0x1042)
ICU18FRTSEL
(0x1044)
58
Shee t
RICFG1
Resource
Input
CAN0_RX
CAN1_RX
RESSEL[3:0]/
Source for resource input
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
RESSEL (0-7)
CAN0_RX
CAN1_RX and
CAN1_TX
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P0_25
reserved
P0_42
P0_48
reserved
P1_34
P1_00
PORTSEL (8-15)
P2_41
reserved
reserved
reserved
P0_49
P2_48
P2_49
P2_50
RESSEL (0-7)
CAN0_RX
CAN1_RX and
CAN1_TX
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL[3:0]
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P0_24
reserved
P0_43
P0_48
reserved
P1_36
P1_02
PORTSEL (8-15)
P2_41
reserved
reserved
P0_42
P2_40
P2_49
P2_50
P2_51
RESSEL (0-7)
PORT_PIN
RLT2_TOT
RLT3_TOT
RLT6_TOT
PPG64_PPGB
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P0_44
P0_45
P0_47
P2_40
reserved
P2_51
FRT16_TEXT
PORTSEL (8-15)
P2_06
P2_14
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PORT_PIN
RLT2_TOT
RLT3_TOT
RLT7_TOT
PPG65_PPGB
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P0_45
P0_47
P2_41
reserved
P2_51
P2_07
PORTSEL (8-15)
P2_15
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PORT_PIN
RLT2_TOT
RLT3_TOT
RLT8_TOT
PPG66_PPGB
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
FRT17_TEXT
FRT18_TEXT
PORTSEL (0-7)
reserved
reserved
P0_45
P0_46
P0_47
P2_42
reserved
P2_51
PORTSEL (8-15)
P2_08
P2_16
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PORT_PIN
RLT2_TOT
RLT3_TOT
RLT9_TOT
PPG67_PPGB
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P0_45
P0_47
P2_43
reserved
P2_51
P2_09
PORTSEL (8-15)
P2_17
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
reserved
reserved
reserved
P1_43
P1_56
P0_46
PORTSEL (8-15)
P1_13
P1_18
P2_36
reserved
reserved
reserved
P2_48
P2_08
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
reserved
reserved
reserved
P1_44
P1_57
P0_41
FRT19_TEXT
ICU18_IN0
ICU18_IN1
PORTSEL (8-15)
P0_47
P2_37
reserved
reserved
reserved
P2_49
P2_09
reserved
RESSEL (0-7)
FRT18
FRT16
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
ICU18_FRTSEL
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Resource
Register
Input
ICU19IN0
(0x1060)
ICU19IN1
(0x1062)
ICU19FRTSEL
(0x1064)
RESSEL[3:0]/
PORTSEL[3:0]
Sh eet
Source for resource input
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
reserved
reserved
reserved
P1_45
P1_58
P0_42
PORTSEL (8-15)
P2_38
reserved
reserved
reserved
reserved
P2_24
P2_10
reserved
ICU19_IN0
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
reserved
reserved
P1_26
P1_46
P1_59
P1_14
PORTSEL (8-15)
P1_19
P2_39
reserved
reserved
reserved
reserved
P2_25
P2_11
RESSEL (0-7)
FRT19
FRT17
ICU18_TOUT0
reserved
reserved
reserved
reserved
reserved
ICU19_IN1
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
RLT4_TOT
RLT5_TOT
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
ICU19_FRTSEL
OCU16OTD0GAT OCU16_OTD0GAT
E (0x1400)
E
PORTSEL (8-15)
RESSEL (0-7)
OCU16OTD0GM
OCU16_OTD0GM
(0x1402)
OCU16OTD0GM
OCU16_OTD0GM
(0x1402)
-
-
-
reserved
reserved
reserved
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
RLT4_TOT
RLT6_TOT
reserved
reserved
RESSEL (8-15)
-
-
-
-
PPG64_PPGB PPG66_PPGB OCU17_OTD0 OCU17_OTD1
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
OCU16_CMP0
OCU17_MTRG
OUT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
RESSEL (0-7)
OCU17OTD0GAT OCU17_OTD0GAT
E (0x1424)
E
reserved
-
PORTSEL (8-15)
OCU17FRTSEL
OCU17_FRTSEL
(0x1422)
reserved
-
RESSEL (0-7)
OCU17CMP0EX OCU17_CMP0EX
T (0x1420)
T
reserved
RESSEL (8-15)
RESSEL (0-7)
OCU16OTD1GM
OCU16_OTD1GM
(0x1406)
SPECIAL0_GN SPECIAL0_VD
D
D
PPG64_PPGB PPG65_PPGB OCU17_OTD0 OCU17_OTD1
RESSEL (8-15)
FRT17_CNT_E FRT16_CNT_E
N
N
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
RLT4_TOT
RLT7_TOT
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
January 30, 2015, MB9EF226_DS707-00004-2v1-E
PPG64_PPGB PPG67_PPGB OCU16_OTD0 OCU16_OTD1
59
Data
Resource
Register
Input
RESSEL[3:0]/
PORTSEL[3:0]
RESSEL (0-7)
OCU17OTD0GM
OCU17_OTD0GM
(0x1426)
OCU17OTD1GAT OCU17_OTD1GAT
E (0x1428)
E
USART6SIN
(0x1C02)
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
reserved
reserved
reserved
reserved
reserved
reserved
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
RLT4_TOT
RLT8_TOT
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
SPECIAL0_GN SPECIAL0_VD
D
D
PPG64_PPGB PPG68_PPGB OCU16_OTD0 OCU16_OTD1
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P0_41
P0_46
P1_40
P1_13
reserved
reserved
PORTSEL (8-15)
P2_48
reserved
reserved
reserved
reserved
reserved
reserved
reserved
USART6_SCKI
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
reserved
P0_40
P0_45
P1_39
P0_47
P1_12
PORTSEL (8-15)
reserved
reserved
reserved
P2_50
reserved
reserved
reserved
reserved
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
USART6_SIN
PPG64PPGAGAT PPG64_PPGAGAT
E (0x2400)
E
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PPG64PPGAGM
PPG64_PPGAGM
(0x2402)
PPG64PPGBGAT PPG64_PPGBGAT
E (0x2404)
E
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
RESSEL (0-7)
PPG64PPGBGM
PPG64_PPGBGM
(0x2406)
PPG65PPGAGAT PPG65_PPGAGAT
E (0x2420)
E
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
PORTSEL (8-15)
60
Bit 1
RESSEL (8-15)
RESSEL (0-7)
USART6SCKI
(0x1C00)
Source for resource input
Bit 0
PORTSEL (0-7)
PORTSEL (8-15)
OCU17OTD1GM
OCU17_OTD1GM
(0x142A)
Shee t
RESSEL (8-15)
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Resource
Register
Input
RESSEL[3:0]/
PORTSEL[3:0]
RESSEL (0-7)
PPG65PPGAGM
PPG65_PPGAGM
(0x2422)
PPG65PPGBGAT PPG65_PPGBGAT
E (0x2424)
E
PPG66PPGBGAT PPG66_PPGBGAT
E (0x2444)
E
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
reserved
reserved
reserved
reserved
reserved
reserved
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
RESSEL (8-15)
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PPG67PPGBGAT PPG67_PPGBGAT
E (0x2464)
E
Bit 5
-
PORTSEL (8-15)
PPG67PPGAGM
PPG67_PPGAGM
(0x2462)
Bit 4
-
RESSEL (0-7)
PPG67PPGAGAT PPG67_PPGAGAT
E (0x2460)
E
Bit 3
-
PORTSEL (8-15)
PPG66PPGBGM
PPG66_PPGBGM
(0x2446)
Bit 2
-
RESSEL (0-7)
PPG66PPGAGM
PPG66_PPGAGM
(0x2442)
Bit 1
RESSEL (8-15)
RESSEL (0-7)
PPG66PPGAGAT PPG66_PPGAGAT
E (0x2440)
E
Source for resource input
Bit 0
PORTSEL (0-7)
PORTSEL (8-15)
PPG65PPGBGM
PPG65_PPGBGM
(0x2426)
Sh eet
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
January 30, 2015, MB9EF226_DS707-00004-2v1-E
61
Data
Resource
Register
Input
RESSEL[3:0]/
PORTSEL[3:0]
RESSEL (0-7)
PPG67PPGBGM
PPG67_PPGBGM
(0x2466)
PPG68PPGAGAT PPG68_PPGAGAT
E (0x2480)
E
PPG69PPGAGAT PPG69_PPGAGAT
E (0x24A0)
E
62
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
reserved
reserved
reserved
reserved
reserved
reserved
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
-
-
-
-
-
-
RESSEL (8-15)
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PPG70PPGAGAT PPG70_PPGAGAT
E (0x24C0)
E
Bit 5
-
PORTSEL (8-15)
PPG69PPGBGM
PPG69_PPGBGM
(0x24A6)
Bit 4
-
RESSEL (0-7)
PPG69PPGBGAT PPG69_PPGBGAT
E (0x24A4)
E
Bit 3
-
PORTSEL (8-15)
PPG69PPGAGM
PPG69_PPGAGM
(0x24A2)
Bit 2
-
RESSEL (0-7)
PPG68PPGBGM
PPG68_PPGBGM
(0x2486)
Bit 1
RESSEL (8-15)
RESSEL (0-7)
PPG68PPGBGAT PPG68_PPGBGAT
E (0x2484)
E
Source for resource input
Bit 0
PORTSEL (0-7)
PORTSEL (8-15)
PPG68PPGAGM
PPG68_PPGAGM
(0x2482)
Shee t
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Resource
Register
Input
RESSEL[3:0]/
PORTSEL[3:0]
RESSEL (0-7)
PPG70PPGAGM
PPG70_PPGAGM
(0x24C2)
PPG70PPGBGAT PPG70_PPGBGAT
E (0x24C4)
E
PPG71PPGBGAT PPG71_PPGBGAT
E (0x24E4)
E
PPGGRP16ETR PPGGRP16_ETR
G1 (0x2C02)
G1
PPGGRP16ETR PPGGRP16_ETR
G2 (0x2C04)
G2
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
reserved
reserved
reserved
reserved
reserved
reserved
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
SPECIAL0_GN SPECIAL0_VD
D
D
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
SPECIAL0_VD
D
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PPGGRP16ETR PPGGRP16_ETR
G0 (0x2C00)
G0
Bit 3
-
PORTSEL (8-15)
PPG71PPGBGM
PPG71_PPGBGM
(0x24E6)
Bit 2
-
RESSEL (0-7)
PPG71PPGAGM
PPG71_PPGAGM
(0x24E2)
Bit 1
RESSEL (8-15)
RESSEL (0-7)
PPG71PPGAGAT PPG71_PPGAGAT
E (0x24E0)
E
Source for resource input
Bit 0
PORTSEL (0-7)
PORTSEL (8-15)
PPG70PPGBGM
PPG70_PPGBGM
(0x24C6)
Sh eet
SPECIAL0_GN SPECIAL0_VD
D
D
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
PORT_PIN
OCU0_OTD0
OCU0_OTD1
OCU1_OTD0
OCU1_OTD1
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
PORT_PIN
OCU0_OTD0
OCU0_OTD1
OCU1_OTD0
OCU1_OTD1
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
PORT_PIN
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
January 30, 2015, MB9EF226_DS707-00004-2v1-E
OCU16_OTD0 OCU16_OTD1 OCU17_OTD0 OCU17_OTD1
63
Data
Resource
Register
Input
RESSEL[3:0]/
PORTSEL[3:0]
RESSEL (0-7)
PPGGRP16ETR PPGGRP16_ETR
G3 (0x2C06)
G3
PPGGRP16RLTT PPGGRP16_RLTT
RG1 (0x2C08)
RG1
PPGGRP17ETR PPGGRP17_ETR
G0 (0x2C20)
G0
PPGGRP17ETR PPGGRP17_ETR
G1 (0x2C22)
G1
PPGGRP17ETR PPGGRP17_ETR
G2 (0x2C24)
G2
PPGGRP17ETR PPGGRP17_ETR
G3 (0x2C26)
G3
PPGGRP17RLTT PPGGRP17_RLTT
RG1 (0x2C28)
RG1
64
Shee t
Source for resource input
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
reserved
reserved
reserved
PORT_PIN
OCU16_OTD0 OCU16_OTD1 OCU17_OTD0 OCU17_OTD1
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RLT8_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
PORT_PIN
OCU0_OTD0
OCU0_OTD1
OCU1_OTD0
OCU1_OTD1
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
PORT_PIN
OCU0_OTD0
OCU0_OTD1
OCU1_OTD0
OCU1_OTD1
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
PORT_PIN
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
OCU16_OTD0 OCU16_OTD1 OCU17_OTD0 OCU17_OTD1
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
PORT_PIN
reserved
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
OCU16_OTD0 OCU16_OTD1 OCU17_OTD0 OCU17_OTD1
PORTSEL (8-15)
-
-
-
-
-
-
-
-
RESSEL (0-7)
RLT1_TOT
RLT2_TOT
RLT3_TOT
RLT4_TOT
RLT5_TOT
RLT6_TOT
RLT7_TOT
RLT8_TOT
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
3.2.2.4
Register
RLT0TIN
(0x0800)
RICFG3
Resource
Input
RESSEL[3:0]/
RLT2TIN
(0x0840)
RLT3TIN
(0x0860)
RLT4TIN
(0x0880)
RLT5TIN
(0x08A0)
RLT6TIN
(0x08C0)
RLT7TIN
(0x08E0)
RLT8TIN
(0x0900)
Source for resource input
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
RESSEL (0-7)
PORT_PIN
RLT9_TOT
RLT9_UFSET
RLT1_TOT
PPG0_PPGA
RESSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (0-7)
reserved
P0_47
P2_22
P1_11
P2_43
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL[3:0]
SPECIAL0_MC SPECIAL0_RC
LKDIV4
CLKDIV4
-
RLT0_TIN
RESSEL (0-7)
RLT1TIN
(0x0820)
Sh eet
PORT_PIN
RLT0_TOT
RLT0_UFSET
RLT2_TOT
SPECIAL0_MC SPECIAL0_RC
PPG1_PPGA
LKDIV4
CLKDIV4
-
RESSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (0-7)
reserved
reserved
P2_23
P1_15
P2_39
reserved
P2_51
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RLT1_TIN
RESSEL (0-7)
PORT_PIN
RLT1_TOT
RLT1_UFSET
RLT3_TOT
RESSEL (8-15)
reserved
reserved
reserved
reserved
SPECIAL0_MC SPECIAL0_RC
PPG2_PPGA
LKDIV4
CLKDIV4
reserved
reserved
reserved
reserved
RLT2_TIN
PORTSEL (0-7)
reserved
P0_43
P2_24
P1_19
P2_35
reserved
P2_21
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PORT_PIN
RLT2_TOT
RLT2_UFSET
RLT4_TOT
PPG3_PPGA
RESSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (0-7)
reserved
P0_45
P1_30
P1_43
P1_08
reserved
P2_13
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PORT_PIN
RLT3_TOT
RLT3_UFSET
RLT5_TOT
PPG4_PPGA
SPECIAL0_MC SPECIAL0_RC
LKDIV4
CLKDIV4
-
RLT3_TIN
USART0_SOT USART6_SOT
-
RESSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (0-7)
reserved
P0_46
P1_31
P1_44
P1_09
reserved
P2_14
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PORT_PIN
RLT4_TOT
RLT4_UFSET
RLT6_TOT
PPG5_PPGA
RESSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (0-7)
reserved
P0_40
P1_39
P2_25
P1_12
reserved
reserved
P2_50
reserved
reserved
reserved
RLT4_TIN
USART0_SOT USART6_SOT
-
RLT5_TIN
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PORT_PIN
RLT5_TOT
RLT5_UFSET
RLT7_TOT
PPG6_PPGA
RESSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (0-7)
reserved
P0_41
P1_40
P1_13
reserved
P2_48
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PORT_PIN
RLT6_TOT
RLT6_UFSET
RLT8_TOT
PPG7_PPGA
RESSEL (8-15)
reserved
reserved
reserved
reserved
reserved
UDC0_UDOT0 UDC0_UDOT1
-
RLT6_TIN
UDC0_UDOT0 UDC0_UDOT1
reserved
reserved
reserved
RLT7_TIN
PORTSEL (0-7)
reserved
reserved
reserved
P2_38
reserved
P2_49
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PORT_PIN
RLT7_TOT
RLT7_UFSET
RLT9_TOT
PPG8_PPGA
RESSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (0-7)
reserved
reserved
reserved
P2_37
P2_41
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
UDC0_UDOT0 UDC0_UDOT1
-
RLT8_TIN
January 30, 2015, MB9EF226_DS707-00004-2v1-E
65
Data
Resource
Register
Input
RESSEL[3:0]/
PORTSEL[3:0]
RESSEL (0-7)
RLT9TIN
(0x0920)
UDC0AIN0
(0x1000)
UDC0AIN1
(0x1004)
UDC0BIN0
(0x1008)
UDC0BIN1
(0x100C)
UDC0ZIN0
(0x1010)
UDC0ZIN1
(0x1014)
66
Shee t
Source for resource input
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
PORT_PIN
RLT8_TOT
RLT8_UFSET
RLT0_TOT
PPG9_PPGA
UDC0_UDOT0 UDC0_UDOT1
-
RESSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (0-7)
reserved
reserved
reserved
P2_36
P2_42
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PORT_PIN
RLT0_TOT
RLT3_TOT
RLT7_TOT
-
-
-
-
RLT9_TIN
RESSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (0-7)
reserved
reserved
P1_34
P1_53
P0_44
P2_33
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PORT_PIN
RLT1_TOT
RLT4_TOT
RLT7_TOT
-
-
-
-
UDC0_AIN0
RESSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (0-7)
reserved
reserved
P1_43
P1_57
P0_48
P2_37
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PORT_PIN
RLT1_TOT
RLT4_TOT
RLT8_TOT
-
-
-
-
UDC0_AIN1
RESSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (0-7)
reserved
reserved
P1_35
P1_54
P0_45
P2_34
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PORT_PIN
RLT2_TOT
RLT5_TOT
RLT8_TOT
-
-
-
-
UDC0_BIN0
RESSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (0-7)
reserved
reserved
P1_44
P1_58
P0_49
P2_38
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PORT_PIN
RLT2_TOT
RLT5_TOT
RLT9_TOT
PPG0_PPGA
PPG1_PPGA
PPG2_PPGA
PPG3_PPGA
RESSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (0-7)
reserved
reserved
P1_36
P1_55
P0_46
P2_35
reserved
reserved
UDC0_BIN1
UDC0_ZIN0
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
PORT_PIN
RLT3_TOT
RLT6_TOT
RLT9_TOT
PPG0_PPGA
PPG1_PPGA
PPG2_PPGA
PPG3_PPGA
RESSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (0-7)
reserved
reserved
P1_45
P1_59
reserved
P2_39
reserved
reserved
PORTSEL (8-15)
reserved
P2_50
reserved
reserved
reserved
reserved
reserved
reserved
UDC0_ZIN1
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
3.2.2.5
Register
I2S0ECLK
(0x1000)
I2S0SCKI
(0x1004)
I2S0SDI
(0x1008)
I2S0WSI
(0x100C)
RICFG4
Resource
Input
RESSEL[3:0]/
PORTSEL[3:0]
I2S1SCKI
(0x1024)
I2S1SDI
(0x1028)
I2S1WSI
(0x102C)
SPI0CLKI
(0x1C00)
SPI0DATA0I
(0x1C04)
Source for resource input
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
RESSEL (0-7)
PORT_PIN
SPECIAL0_CLK
_PERI1
-
-
-
-
-
-
RESSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (0-7)
reserved
reserved
reserved
reserved
P2_32
P2_36
P2_40
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
reserved
P2_35
P2_39
P2_43
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
reserved
P2_33
P2_37
P2_41
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
reserved
P2_34
P2_38
P2_42
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORT_PIN
SPECIAL0_CLK
_PERI1
-
-
-
-
-
-
I2S0_ECLK
I2S0_SCKi
I2S0_SDi
I2S0_WSi
RESSEL (0-7)
I2S1ECLK
(0x1020)
Sh eet
RESSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (0-7)
reserved
reserved
reserved
reserved
P2_32
P2_36
reserved
reserved
PORTSEL (8-15)
P2_48
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
I2S1_ECLK
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P1_27
P2_35
P2_39
reserved
reserved
P2_51
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
I2S1_SCKi
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
reserved
P2_33
P2_37
reserved
reserved
P2_49
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
I2S1_SDi
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P1_26
P2_34
P2_38
reserved
reserved
P2_50
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
I2S1_WSi
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P0_47
P1_11
P2_35
P2_43
reserved
P2_22
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
SPI0_CLKi
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P0_46
P1_10
P2_34
P2_42
reserved
P2_24
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
SPI0_DATA0i
January 30, 2015, MB9EF226_DS707-00004-2v1-E
67
Data
Resource
Register
Input
SPI0DATA1I
(0x1C08)
SPI0SSI
(0x1C0C)
SPI1CLKI
(0x1C20)
SPI1DATA0I
(0x1C24)
SPI1DATA1I
(0x1C28)
SPI1SSI
(0x1C2C)
SPI2CLKI
(0x1C40)
SPI2DATA0I
(0x1C44)
SPI2DATA1I
(0x1C48)
SPI2DATA2I
(0x1C4C)
68
RESSEL[3:0]/
PORTSEL[3:0]
Shee t
Source for resource input
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P0_45
P1_09
P2_33
P2_41
reserved
P2_23
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
SPI0_DATA1i
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P0_44
P1_08
P2_32
P2_40
reserved
P2_25
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
SPI0_SSi
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
reserved
P1_15
P2_39
P2_43
reserved
P2_51
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
SPI1_CLKi
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
reserved
P1_14
P2_38
P2_42
reserved
P2_50
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
SPI1_DATA0i
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P0_49
P1_13
P2_37
P2_41
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
SPI1_DATA1i
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P0_48
P1_12
P2_36
P2_40
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
SPI1_SSi
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P0_43
P1_19
P2_35
P2_39
reserved
P2_21
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
SPI2_CLKi
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P0_42
P1_18
P2_34
P2_38
reserved
P2_20
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
SPI2_DATA0i
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P0_41
P1_17
P2_33
P2_37
reserved
P2_19
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
SPI2_DATA1i
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
reserved
P2_22
reserved
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
SPI2_DATA2i
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Resource
Register
Input
SPI2DATA3I
(0x1C50)
SPI2SSI
(0x1C58)
RESSEL[3:0]/
PORTSEL[3:0]
Sh eet
Source for resource input
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P0_45
reserved
P2_23
reserved
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
SPI2_DATA3i
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P0_40
P1_16
P2_32
P2_36
reserved
P2_18
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
SPI2_SSi
January 30, 2015, MB9EF226_DS707-00004-2v1-E
69
Data
3.2.2.6
Register
GFX0DCLKI
(0x0000)
EIC0INT00
(0x1000)
EIC0INT01
(0x1004)
EIC0INT02
(0x1008)
EIC0INT03
(0x100C)
EIC0INT04
(0x1010)
EIC0INT05
(0x1014)
EIC0INT06
(0x1018)
EIC0INT07
(0x101C)
EIC0INT08
(0x1020)
70
Shee t
RICFG7
Resource
Input
RESSEL[3:0]/
Source for resource input
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL[3:0]
GFX0_DCLKI
PORTSEL (0-7)
reserved
P1_30
P1_39
reserved
reserved
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
EIC0_INT00
PORTSEL (0-7)
reserved
P1_47
P0_63
P1_08
reserved
P1_60
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
EIC0_INT01
PORTSEL (0-7)
reserved
P1_33
P1_48
P1_09
reserved
P1_61
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
EIC0_INT02
PORTSEL (0-7)
reserved
P1_42
P1_49
P1_10
reserved
reserved
P1_62
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
EIC0_INT03
PORTSEL (0-7)
reserved
reserved
P0_44
P1_11
P1_08
P2_32
P2_40
reserved
PORTSEL (8-15)
P2_25
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
EIC0_INT04
PORTSEL (0-7)
reserved
reserved
P0_48
P1_12
P2_36
P2_40
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
EIC0_INT05
PORTSEL (0-7)
reserved
reserved
P0_40
P1_13
P1_16
P2_32
P2_36
reserved
PORTSEL (8-15)
P2_18
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
EIC0_INT06
PORTSEL (0-7)
reserved
reserved
reserved
P1_14
P2_34
P2_38
P2_42
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
EIC0_INT07
PORTSEL (0-7)
reserved
reserved
P1_26
P1_15
P2_34
P2_38
reserved
reserved
PORTSEL (8-15)
P2_50
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P0_25
reserved
P0_42
P0_48
reserved
P1_34
P1_00
PORTSEL (8-15)
P2_41
reserved
reserved
P2_48
P2_49
P2_50
reserved
reserved
EIC0_INT08
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Resource
Register
Input
EIC0INT09
(0x1024)
EIC0INT10
(0x1028)
EIC0INT11
(0x102C)
EIC0INT12
(0x1030)
EIC0INT13
(0x1034)
EIC0INT14
(0x1038)
EIC0INT15
(0x103C)
EIC0INT16
(0x1040)
EIC0INT17
(0x1044)
EIC0INT18
(0x1048)
RESSEL[3:0]/
PORTSEL[3:0]
Sh eet
Source for resource input
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P0_24
reserved
P0_43
P0_48
reserved
P1_36
P1_02
PORTSEL (8-15)
P2_41
reserved
reserved
P2_49
P2_50
P2_51
reserved
reserved
EIC0_INT09
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P0_24
reserved
P0_42
P0_49
reserved
P1_38
P1_16
PORTSEL (8-15)
P2_40
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EIC0_INT10
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
reserved
P0_40
P0_45
P1_30
P1_43
P0_42
PORTSEL (8-15)
P1_08
reserved
reserved
reserved
P2_50
P2_13
reserved
reserved
EIC0_INT11
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
reserved
P0_40
P0_45
P1_39
P0_47
P1_12
PORTSEL (8-15)
reserved
reserved
reserved
P2_50
reserved
reserved
reserved
reserved
EIC0_INT12
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P1_37
P1_02
P1_16
reserved
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EIC0_INT13
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P1_50
P1_17
P2_11
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EIC0_INT14
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P0_41
P1_51
P1_18
P2_12
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EIC0_INT15
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P0_46
P1_52
P1_19
P2_13
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EIC0_INT16
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P0_47
P1_53
P1_20
P2_14
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EIC0_INT17
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P1_54
P1_21
P2_15
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EIC0_INT18
January 30, 2015, MB9EF226_DS707-00004-2v1-E
71
Data
Resource
Register
Input
EIC0INT19
(0x104C)
EIC0INT20
(0x1050)
EIC0INT21
(0x1054)
EIC0INT22
(0x1058)
EIC0INT23
(0x105C)
EIC0INT24
(0x1060)
EIC0INT25
(0x1064)
EIC0INT26
(0x1068)
EIC0INT27
(0x106C)
EIC0INT28
(0x1070)
72
RESSEL[3:0]/
PORTSEL[3:0]
Shee t
Source for resource input
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P1_55
P1_22
P2_16
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EIC0_INT19
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
reserved
P1_56
P1_23
P2_17
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EIC0_INT20
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P1_27
P1_57
P2_00
P2_18
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EIC0_INT21
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P1_28
P1_58
P2_01
P2_19
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EIC0_INT22
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P1_29
P1_59
P2_02
P2_20
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EIC0_INT23
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P1_31
P0_62
P2_03
P2_21
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EIC0_INT24
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P1_32
P1_00
P2_04
P2_22
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EIC0_INT25
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P1_35
P1_01
P2_05
P2_23
P2_33
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EIC0_INT26
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P1_40
P1_03
P2_06
P2_24
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EIC0_INT27
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P1_41
P1_04
P2_07
P2_25
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EIC0_INT28
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Resource
Register
Input
EIC0INT29
(0x1074)
EIC0INT30
(0x1078)
EIC0INT31
(0x107C)
EIC0NMI
(0x1080)
3.2.2.7
Register
RESSEL[3:0]/
PORTSEL[3:0]
Sh eet
Source for resource input
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P1_44
P1_05
P2_08
P2_35
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EIC0_INT29
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P1_45
P1_06
P2_09
P2_37
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EIC0_INT30
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P1_46
P1_07
P2_10
P2_39
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EIC0_INT31
RESSEL (0-7)
-
-
-
-
-
-
-
-
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
reserved
P2_43
reserved
reserved
reserved
reserved
reserved
reserved
PORTSEL (8-15)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
RESSEL (0-7)
RLT0_TOT
RLT3_TOT
RLT6_TOT
RLT9_TOT
reserved
reserved
RESSEL (8-15)
-
-
-
-
-
-
-
-
PORTSEL (0-7)
-
-
-
-
-
-
-
-
PORTSEL (8-15)
-
-
-
-
-
-
-
-
EIC0_NMI
RICFG8
Resource
Input
HSSPI0MSTART
HSSPI0_MSTART
(0x0000)
RESSEL[3:0]/
PORTSEL[3:0]
Source for resource input
January 30, 2015, MB9EF226_DS707-00004-2v1-E
PPG64_PPGB OCU16_OTD0
73
Data
3.3
Shee t
I/O Pin Types
3.3.1
Pin Circuit type of QFP-240
Table 3-4: Pin Circuit type QFP-240
74
Pin No
IO_TYPE
Pin No
IO_TYPE
Pin No
IO_TYPE
1
MODE_IO
33
RSDS_IO
65
RSDS_IO
2
X1_IO
34
RSDS_IO
66
VDD33_IO
3
X0_IO
35
VSS33_IO
67
VDD33_IO
4
VSS50_IO
36
VSS33_IO
68
BIDI33_IO
5
VSS50_IO
37
BIDI33_IO
69
RSDS_IO
6
X0A_IO
38
RSDS_IO
70
RSDS_IO
7
X1A_IO
39
RSDS_IO
71
VSS33_IO
8
MODE_IO
40
VDD12L_IO
72
RSDS_IO
9
VDD50_IO
41
VDD12L_IO
73
RSDS_IO
10
VDD50_IO
42
RSDS_IO
74
VDD33_IO
11
VSS50_IO
43
RSDS_IO
75
VDD33_IO
12
VSS50_IO
44
VDD33_IO
76
BIDI33_IO
13
VDD33_IO
45
VDD33_IO
77
RSDS_IO
14
VDD33_IO
46
BIDI33_IO
78
RSDS_IO
15
BIDI33_IO
47
RSDS_IO
79
VDD12L_IO
16
BIDI33_IO
48
RSDS_IO
80
VDD12L_IO
17
BIDI33_IO
49
VSS33_IO
81
RSDS_IO
18
BIDI33_IO
50
VSS33_IO
82
RSDS_IO
19
BIDI33_IO
51
RSDS_IO
83
VSS33_IO
20
BIDI33_IO
52
RSDS_IO
84
VSS33_IO
21
BIDI33_IO
53
VDD33_IO
85
BIDI33_IO
22
BIDI33_IO
54
VDD33_IO
86
RSDS_IO
23
BIDI33_IO
55
RSDS_IO
87
RSDS_IO
24
BIDI33_IO
56
RSDS_IO
88
VDD33_IO
25
BIDI33_IO
57
VSS33_IO
89
VSS33_IO
26
BIDI33_IO
58
VSS33_IO
90
BIDI33_IO
27
BIDI33_IO
59
RSDS_IO
91
TTL33_IO
28
BIDI33_IO
60
RSDS_IO
92
TTL33_IO
29
VSS33_IO
61
VDD12L_IO
93
TTL33_IO
30
VSS33_IO
62
VDD12L_IO
94
TTL33_IO
31
VDD33_IO
63
BIDI33_IO
95
BIDI33_IO
32
VDD33_IO
64
RSDS_IO
96
TTL33_IO
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Pin No
IO_TYPE
Pin No
IO_TYPE
Pin No
IO_TYPE
97
TTL33_IO
131
VDD12L_IO
165
SMC_IO
98
VDD33_IO
132
VDD33_IO
166
SMC_IO
99
VSS33_IO
133
VDD33_IO
167
SMC_IO
100
BIDI33_IO
134
VSS33_IO
168
SMC_IO
101
TTL33_IO
135
VSS33_IO
169
SMC_IO
102
TTL33_IO
136
HVSS_IO
170
SMC_IO
103
TTL33_IO
137
HVSS_IO
171
SMC_IO
104
TTL33_IO
138
HVDD_IO
172
HVSS_IO
105
BIDI33_IO
139
HVDD_IO
173
HVDD_IO
106
TTL33_IO
140
SMC_IO
174
NA
107
TTL33_IO
141
SMC_IO
175
AVSS5_IO
108
VDD33_IO
142
SMC_IO
176
AVRL5_IO
109
BIDI33_IO
143
SMC_IO
177
AVRH5_IO
110
VSS33_IO
144
SMC_IO
178
AVCC5_IO
111
BIDI33_IO
145
SMC_IO
179
BIDI50_IO
112
BIDI33_IO
146
SMC_IO
180
VDD50_IO
113
BIDI33_IO
147
SMC_IO
181
VSS50_IO
114
BIDI33_IO
148
HVSS_IO
182
VSS50_IO
115
BIDI33_IO
149
HVSS_IO
183
BIDI50_IO
116
BIDI33_IO
150
HVDD_IO
184
BIDI50_IO
117
BIDI33_IO
151
HVDD_IO
185
BIDI50_IO
118
BIDI33_IO
152
SMC_IO
186
BIDI50_IO
119
BIDI33_IO
153
SMC_IO
187
VSS50_IO
120
BIDI33_IO
154
SMC_IO
188
VSS50_IO
121
NA
155
SMC_IO
189
VDD12H_IO
122
BIDI33_IO
156
SMC_IO
190
VDD12H_IO
123
BIDI33_IO
157
SMC_IO
191
BIDI50_IO
124
BIDI33_IO
158
SMC_IO
192
BIDI50_IO
125
BIDI33_IO
159
SMC_IO
193
NA
126
BIDI33_IO
160
HVSS_IO
194
BIDI50_IO
127
BIDI33_IO
161
HVSS_IO
195
BIDI50_IO
128
BIDI33_IO
162
HVDD_IO
196
BIDI50_IO
129
BIDI33_IO
163
HVDD_IO
197
BIDI50_IO
130
VDD12L_IO
164
SMC_IO
198
VSS50_IO
January 30, 2015, MB9EF226_DS707-00004-2v1-E
75
Data
76
Pin No
IO_TYPE
Pin No
IO_TYPE
199
VSS50_IO
233
I2C_IO
200
VDD50_IO
234
JTAGO
201
BIDI50_IO
235
JTAGIUP
202
BIDI50_IO
236
NA
203
BIDI50A_IO
237
NA
204
NA
238
JTAGIUP
205
BIDI50A_IO
239
JTAGIUP
206
BIDI50A_IO
240
JTAGIDN
207
BIDI50A_IO
208
BIDI50A_IO
209
BIDI50A_IO
210
VSS50_IO
211
VSS50_IO
212
VDD12H_IO
213
VDD12H_IO
214
NA
215
BIDI50A_IO
216
BIDI50A_IO
217
BIDI50_IO
218
BIDI50_IO
219
NA
220
BIDI50_IO
221
BIDI50_IO
222
BIDI50_IO
223
BIDI50_IO
224
VSS50_IO
225
VSS50_IO
226
VDD50_IO
227
NA
228
VDD50_IO
229
BIDI50_IO
230
NA
231
BIDI50_IO
232
I2C_IO
Shee t
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
3.3.2
Sh eet
Pin Circuit type of QFP-176
Table 3-5: Pin Circuit type of QFP-176
Pin No
IO_TYPE
1
2
3
Pin No
IO_TYPE
Pin No
IO_TYPE
MODE_IO
33
X1_IO
34
VDD33_IO
65
TTL33_IO
RSDS_IO
66
TTL33_IO
TTL33_IO
X0_IO
35
RSDS_IO
67
4
VSS50_IO
36
VSS33_IO
68
TTL33_IO
5
X0A_IO
37
RSDS_IO
69
TTL33_IO
6
X1A_IO
38
RSDS_IO
70
TTL33_IO
VDD33_IO
7
MODE_IO
39
VDD33_IO
71
8
VDD50_IO
40
RSDS_IO
72
VSS33_IO
9
VSS50_IO
41
RSDS_IO
73
TTL33_IO
VDD33_IO
42
VSS33_IO
74
TTL33_IO
TTL33_IO
10
11
BIDI33_IO
43
RSDS_IO
75
12
BIDI33_IO
44
RSDS_IO
76
TTL33_IO
13
BIDI33_IO
45
VDD12L_IO
77
TTL33_IO
14
BIDI33_IO
46
RSDS_IO
78
TTL33_IO
VDD33_IO
15
BIDI33_IO
47
RSDS_IO
79
16
BIDI33_IO
48
VDD33_IO
80
VSS33_IO
17
BIDI33_IO
49
RSDS_IO
81
BIDI33_IO
BIDI33_IO
50
RSDS_IO
82
BIDI33_IO
BIDI33_IO
18
19
BIDI33_IO
51
VSS33_IO
83
20
BIDI33_IO
52
RSDS_IO
84
BIDI33_IO
21
BIDI33_IO
53
RSDS_IO
85
BIDI33_IO
22
BIDI33_IO
54
VDD33_IO
86
BIDI33_IO
BIDI33_IO
23
VSS33_IO
55
RSDS_IO
87
24
VDD33_IO
56
RSDS_IO
88
BIDI33_IO
25
RSDS_IO
57
VDD12L_IO
89
BIDI33_IO
26
RSDS_IO
58
RSDS_IO
90
BIDI33_IO
BIDI33_IO
27
VSS33_IO
59
RSDS_IO
91
28
RSDS_IO
60
VSS33_IO
92
BIDI33_IO
29
RSDS_IO
61
RSDS_IO
93
BIDI33_IO
30
VDD12L_IO
62
RSDS_IO
94
VDD12L_IO
RSDS_IO
63
VDD33_IO
95
VDD33_IO
RSDS_IO
64
VSS33_IO
96
VSS33_IO
31
32
January 30, 2015, MB9EF226_DS707-00004-2v1-E
77
Data
78
Shee t
Pin No
IO_TYPE
Pin No
IO_TYPE
Pin No
IO_TYPE
97
HVSS_IO
131
AVCC5_IO
165
BIDI50_IO
98
HVDD_IO
132
VDD50_IO
166
VSS50_IO
99
SMC_IO
133
VSS50_IO
167
VDD50_IO
100
SMC_IO
134
BIDI50_IO
168
BIDI50_IO
101
SMC_IO
135
BIDI50_IO
169
BIDI50_IO
102
SMC_IO
136
BIDI50_IO
170
I2C_IO
103
SMC_IO
137
BIDI50_IO
171
I2C_IO
104
SMC_IO
138
VSS50_IO
172
JTAGO
105
SMC_IO
139
VDD12H_IO
173
JTAGIUP
106
SMC_IO
140
BIDI50_IO
174
JTAGIUP
107
HVSS_IO
141
BIDI50_IO
175
JTAGIUP
108
HVDD_IO
142
BIDI50_IO
176
JTAGIDN
109
SMC_IO
143
BIDI50_IO
110
SMC_IO
144
BIDI50_IO
111
SMC_IO
145
BIDI50_IO
112
SMC_IO
146
VSS50_IO
113
SMC_IO
147
VDD50_IO
114
SMC_IO
148
BIDI50_IO
115
SMC_IO
149
BIDI50_IO
116
SMC_IO
150
BIDI50A_IO
117
HVSS_IO
151
BIDI50A_IO
118
HVDD_IO
152
BIDI50A_IO
119
SMC_IO
153
BIDI50A_IO
120
SMC_IO
154
BIDI50A_IO
121
SMC_IO
155
BIDI50A_IO
122
SMC_IO
156
VSS50_IO
123
SMC_IO
157
VDD12H_IO
124
SMC_IO
158
BIDI50A_IO
125
SMC_IO
159
BIDI50A_IO
126
SMC_IO
160
BIDI50_IO
127
HVSS_IO
161
BIDI50_IO
128
HVDD_IO
162
BIDI50_IO
129
AVSS5_IO
163
BIDI50_IO
130
AVRH5_IO
164
BIDI50_IO
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
3.4
Sh eet
IO Circuit Types
Table 3-6: IO Circuit Type (1 / 5)
Type
Circuit
Remarks
High-speed oscillation circuit:
X1
MAINOSC
0
R
1
Xout
• Programmable between oscillation mode (external crystal or
resonator connected to X0/
X1pins) and Fast external Clock
Input (FCI) mode (external
clock connected to X0 pin
FCI
X0
FCI or osc disable
Low-speed oscillation circuit
X1A
Xout
R
SUBOSC
X0A
osc disable
R
JTAGIDN
JTAGIUP
Hysteresis
inputs
• TTL level input pin
• Pull-down resistor value: approx. 50 k
Pull−down
Resistor
• TTL level input pin
• Pull-up resistor value: approx.
50 k
Pull−up
Resistor
R
Hysteresis
inputs
• CMOS level output
• Output Driving strength is fixed:
Pout
JTAGO
Nout
January 30, 2015, MB9EF226_DS707-00004-2v1-E
IOL
+1 mA
IOH
-1mA
79
Data
Shee t
Table 3-6: IO Circuit Type (2 / 5)
Type
Circuit
Remarks
• A/D converter ref+ (AVRH5)
power supply input pin with protection circuit
• Flash devices do not have a
protection circuit against VDP5
for pins AVRH5
ANE
AVRH5
AVR
ANE
• CMOS Hysteresis input pin
MODE
R
Hysteresis
inputs
Pull−up control
Pout
• CMOS level output (programmable)
ODR[1:0]
IOL
IOH
00
+2mA
-2mA
01
+5mA
-5mA
10
+10mA
-10mA
11
+20mA
-20mA
Nout
Pull−down control
R
Standby control
for input shutdown
Standby control
for input shutdown
RSDS
Hysteresis input
TTL input
• Hysteresis input with input shutdown function
• TTL input with input shutdown
function
Pull−up control
PIL
Input buffer
Levels
Pout
00
Hysteresis
20% / 80%
10
TTL
0.8V / 2V
Nout
Pull−down control
• Programmable pull-up and pulldown resistor: 33k approx.
• RSDS differential output data
R
Standby control
for input shutdown
Standby control
for input shutdown
Hysteresis input
TTL input
BOOST
Id
0
+2mA
1
+4mA
RSDS mode control
RSDS output data
RSDS output enable
80
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 3-6: IO Circuit Type (3 / 5)
Type
Circuit
Remarks
Pull−up control
• CMOS level output (programmable)
ODR[1:0]
IOL
IOH
00
+1mA
-1mA
01
+2mA
-2mA
10
+5mA
-5mA
11
+2mA
-2mA
Pout
Nout
Pull−down control
R
BIDI50
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
Hysteresis input
Hysteresis input
Automotive input
TTL input
Analog input
•
Hysteresis input with input
shutdown function
• Automotive input with input
shutdown function
• TTL input with input shutdown
function
• CMOS input with input shutdown function
PIL
Input buffer
Levels
00
Hysteresis
20% / 80%
01
Automotive
50% / 80%
10
TTL
0.8V / 2V
11
CMOS
20% / 80%
• Programmable pull-up and pulldown resistor; 50k approx.
• Analog input
• CMOS level output
Pull−up control
Pout
Nout
BIDI33
Pull−down control
R
Standby control
for input shutdown
Standby control
for input shutdown
January 30, 2015, MB9EF226_DS707-00004-2v1-E
Hysteresis input
TTL input
ODR[1:0]
IOL
IOH
--
+12mA
-12mA
•
Hysteresis input with input
shutdown function
• TTL input with input shutdown
function
PIL
Input buffer
Levels
00
Hysteresis
20% / 80%
10
TTL
0.8V / 2V
• Programmable pull-up and pulldown resistor: 33k approx.
81
Data
Shee t
Table 3-6: IO Circuit Type (4 / 5)
Type
Circuit
Remarks
• CMOS level output (programmable)
Pull−up control
ODR[1:0]
IOL
IOH
00
+2mA
-2mA
01
+5mA
-5mA
10
+10mA
-10mA
11
+20mA
-20mA
Pout
Nout
•
TTL33
Pull−down control
R
Standby control
for input shutdown
Standby control
for input shutdown
Hysteresis input
TTL input
Hysteresis input with input
shutdown function
• TTL input with input shutdown
function
PIL
Input buffer
Levels
00
Hysteresis
20% / 80%
10
TTL
0.8V / 2V
• Programmable pull-up and pulldown resistor: 33k approx.
• CMOS level output (programmable)
Pull−up control
ODR[1:0]
IOL
IOH
00
+1mA
-1mA
01
+2mA
-2mA
10
+30mA
-30mA
11
+5mA
-5mA
Pout
Nout
•
Pull−down control
R
Standby control
for input shutdown
Hysteresis input
SMC
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
Hysteresis input
Automotive input
TTL input
Hysteresis input with input
shutdown function
• Automotive input with input
shutdown function
• TTL input with input shutdown
function
• CMOS input with input shutdown function
PIL
Input buffer
Levels
00
Hysteresis
20% / 80%
01
Automotive
50% / 80%
10
TTL
0.8V / 2V
11
CMOS
20% / 80%
• Programmable pull-up resistor
and pull down resistor: 50k
approx.
82
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 3-6: IO Circuit Type (5 / 5)
Type
Circuit
Remarks
• CMOS level output (programmable)
Pull−up control
ODR[1:0]
IIC_EN
IOL
IOH
00
0
+1mA
-1mA
01
0
+2mA
-2mA
10
0
+5mA
-5mA
11
0
+2mA
-2mA
+3mA
(Pse
udo
Open
Drain
)*1
Pout
Nout
Pull−down control
R
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
I2C
Hysteresis input
•
•
Automotive input
•
TTL input
I2C input
Standby control
for input shutdown
--
Hysteresis input
•
•
1
Hysteresis input with input
shutdown function
Automotive input with input
shutdown function
TTL input with input shutdown
function
CMOS input with input shutdown function
I2C_enable is high, when the
corresponding
PCFGRxxx_POF value is set to I2C function and the I2C interface module is enabled.
Note *1: For Pseudo Open Drain
output logic value 1, Push/
Pull CMOS driver is
switched to HIZ state.
• Programmable pull-up resistor
and pull-down resistor: 50k
approx.
PIL
Input buffer
Levels
00
Hysteresis
20% / 80%
01
Automotive
50% / 80%
10
TTL
0.8V / 2V
11
CMOS
20% / 80%
• Programmable pull-up resistor
and pull-down resistor: 50k
approx.
January 30, 2015, MB9EF226_DS707-00004-2v1-E
83
Data
3.5
Shee t
Package
Figure 3-3: QFP-240 Package Dimensions
240-pin plastic QFP
(FPT-240P-M06)
240-pin plastic QFP
(FPT-240P-M06)
Lead pitch
0.50 mm
Package width ×
package length
32.0 × 32.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
4.03 mm MAX
Weight
7.23 g
Code
(Reference)
P-FQFP240-32×32-0.50
Note 1) * : Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
34.60±0.20(1.362±.008)SQ
3.73±0.30
(Mounting height)
(.147±.012)
* 32.00±0.10(1.260±.004)SQ
180
121
+0.10
0.40 –0.15
+.004
181
.016 –.006
120
(Stand off)
0.08(.003)
INDEX
240
LEAD No.
"A"
61
1
Details of "A" part
60
0.50(.020)
0.22±0.05
(.009±.002)
0.08(.003)
M
0.145±0.055
(.006±.002)
0~8°
0.60±0.15
(.024±.006)
C
84
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F240015S-c-3-5
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Figure 3-4: QFP-176 Package Dimensions
176-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
24.0 × 24.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LQFP-0176-2424-0.50
(FPT-176P-M07)
176-pin plastic LQFP
(FPT-176P-M07)
Note 1) * : Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness
Note 3) Pins width do not include tie bar cutting remainder.
26.00±0.20(1.024±.008)SQ
*24.00±0.10(.945±.004)SQ
0.145±0.055
(.006±.002)
132
89
133
88
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
0°~8°
0.10±0.10
(.004±.004)
(Stand off)
INDEX
176
45
"A"
LEAD No.
1
44
0.50(.020)
C
0.22±0.05
(.009±.002)
2004-2010 FUJITSU SEMICONDUCTOR LIMITED F176013S-c-1-3
January 30, 2015, MB9EF226_DS707-00004-2v1-E
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
85
Data
86
Shee t
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
4
Sh eet
Interrupt / DMA
This section shows the allocation of interrupt and interrupt vector/interrupt register.
4.1
Interrupt table
Table 4-1: Interrupt Table (1 / 12)
Interrupt
Line No
Interrupt Name
Interrupt Description
0
SYSCIRQ
Status Interrupt from System Controller (SYSC_SYSSTSR:RUNDN is set when current RUN Profile was
successfully applied)
1
WDGIRQ
Watchdog pre-warning Interrupt
(WDG_INT:IRQ_FLAG is set when watchdog error condition
is detected (missing or wrong WDG clearing procedure))
15
MLB0CINT
MLB0 Channel Interrupt
(check MLBn_
CSCRn:[15:0] for detailed Channel interrupt cause)
16
MLB0SINT
MLB0 System Interrupt
(check MLB0_
SSCRn:[7:0] for detailed System interrupt cause)
GFXIRQ0
GFX Interrupt 0
(check GFXGCTR_IntStatus0, GFXGCTR_IntStatus1, GFXGCTR_IntMap0, GFXGCTR_IntMap1 for detailed GFX Interrupt 0 cause)
23
GFXIRQ1
GFX Interrupt 1
(check GFXGCTR_IntStatus0, GFXGCTR_IntStatus1, GFXGCTR_IntMap0, GFXGCTR_IntMap1 for detailed GFX Interrupt 1 cause)
30
ADC0IRQ
ADC0 Conversion End Interrupt
(ADC0_CS1:INT signals end of conversion for current channel (this flag is mirrored in ADC0_CS3:INT))
31
ADC0IRQ2
ADC0 Scan End Interrupt
(ADC0_CS3:INT2 is set when the current scan over selected
channels has finished)
32
ADC0IRQR
ADC0 Range Comparator Interrupt
(ADC0_RCOINT10~32:RCOINT[15:0] are set when corresponding ADC result is outside selected range (check
ADC0_RCOOF10~32:RCOOF[15:0] and the selected mode
ADC0_RCOIRS10~32:RCOIRS[15:0] for interrupt cause)
33
ADC0IRQP
ADC0 Pulse Detection Interrupt
(ADC0_PCZF10~32:CTPZF[15:0] are set when corresponding pulse counter becomes zero)
22
January 30, 2015, MB9EF226_DS707-00004-2v1-E
87
Data
Shee t
Table 4-1: Interrupt Table (2 / 12)
Interrupt
Line No
Interrupt Name
Interrupt Description
34
RRCFGIRQERR
Retention RAM Single Bit Error
(RRCFG_CSR:CEIF is set when a correctable error occurred
during any read access to Retention RAM)
35
SRCFGIRQERR
System RAM Single Bit Error
(SRCFG_ERRFLG:SECFLG is set when a correctable error
occurred during any read access to SRAM)
TCFCFGIRQ
Instruction Flash Write Completion Interrupt (TCFCFG_FSTATn:RDYINT is set on the rising edge of TCFCFG_FSTATn:RDY flag
Instruction Flash Hang Interrupt
(TCFCFG_FSTATn:HANGINT is set when a hang condition
occurs in Instruction Flash)
Instruction Flash Single Bit Error
(TCFCFG_FSECIR:SECINT is set when a correctable error
occurred during any read access to Instruction Flash)
37
EECFGIRQERR
Data Flash Error Interrupt
(EEFCFG_SR:ERRINT is set if the write command sequencer is disabled in ongoing operation or if any write error occurs
during ongoing transfer)
Data Flash Hang Interrupt
(EEFCFG_SR:HANGINT is set when a hang condition occurs in Data Flash)
38
IRQ0IRQERR
IUNIT Vector RAM Single Bit Error
(IRQ0_EEI:EEIS is set when a correctable error occurred
during any read access to Interrupt Controller RAM)
41
EECFGIRQ
Data Flash Write Completion Interrupt
(EEFCFG_SR:RDYINT is set on the rising edge of EEFCFG_SR:RDY flag)
Data Flash Single Bit Error
(EEFCFG_SECIR:SECINT is set when a correctable error
occurred during any read access to Data Flash)
42
EICU0IRQ
External Interrupt Capture Unit 0 Interrupt (EICU0_CNFGR:DATAVALID is set when 256 samples have been taken
at the selected external interrupt input pin)
43
HSSPI0IRQRX
HSSPI0 Receive Interrupt
(check HSSPI0_RXF:[6:0] for detailed RX interrupt cause)
44
HSSPI0IRQTX
HSSPI0 Transmit Interrupt
(check HSSPI0_TXF:[6:0] for detailed TX interrupt cause)
45
SHE
SHE Error Interrupt
(check SHE_IF_CFG_SHE_IRQ[23:16] for detailed SHE Error interrupt cause)
48
SHE
SHE General Interrupt
(check SHE_IF_CFG_SHE_IRQ[5:0] for detailed SHE General interrupt cause)
49
SPI0IRQRX
SPI0 Receive Interrupt
(check SPI0_RXF:[6:0] for detailed RX interrupt cause)
36
88
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 4-1: Interrupt Table (3 / 12)
Interrupt
Line No
Interrupt Name
Interrupt Description
50
SPI0IRQTX
SPI0 Transmit Interrupt
(check SPI0_TXF:[6:0] for detailed TX interrupt cause)
52
SPI1IRQRX
SPI1 Receive Interrupt
(check SPI1_RXF:[6:0] for detailed RX interrupt cause)
53
SPI1IRQTX
SPI1 Transmit Interrupt
(check SPI1_TXF:[6:0] for detailed TX interrupt cause)
55
SPI2IRQRX
SPI2 Receive Interrupt (check SPI2_RXF:[6:0] for detailed
RX interrupt cause)
56
SPI2IRQTX
SSPI2 Transmit Interrupt (check SPI2_TXF:[6:0] for detailed
TX interrupt cause)
CAN0IRQ
CAN0 Interrupt
(this interrupt is called depending on CTRLR0:EIE,
CTRLR0:SIE and the corresponding transmit/receive interrupt enable flags in the message objects TXE/RXE)
62
CAN1IRQ
CAN1 Interrupt
(this interrupt is called depending on CTRLR1:EIE,
CTRLR1:SIE and the corresponding transmit/receive interrupt enable flags in the message objects TXE/RXE)
69
EIC0IRQ0
External Interrupt 0
(EIC0_EIRR:ER0 is set when an interrupt condition is detected at the corresponding input pin)
70
EIC0IRQ1
External Interrupt 1
(EIC0_EIRR:ER1 is set when an interrupt condition is detected at the corresponding input pin)
71
EIC0IRQ2
External Interrupt 2
(EIC0_EIRR:ER2 is set when an interrupt condition is detected at the corresponding input pin)
72
EIC0IRQ3
External Interrupt 3
(EIC0_EIRR:ER3 is set when an interrupt condition is detected at the corresponding input pin)
73
EIC0IRQ4
External Interrupt 4
(EIC0_EIRR:ER4 is set when an interrupt condition is detected at the corresponding input pin)
74
EIC0IRQ5
External Interrupt 5
(EIC0_EIRR:ER5 is set when an interrupt condition is detected at the corresponding input pin)
75
EIC0IRQ6
External Interrupt 6
(EIC0_EIRR:ER6 is set when an interrupt condition is detected at the corresponding input pin)
76
EIC0IRQ7
External Interrupt 7
(EIC0_EIRR:ER7 is set when an interrupt condition is detected at the corresponding input pin)
61
January 30, 2015, MB9EF226_DS707-00004-2v1-E
89
Data
Shee t
Table 4-1: Interrupt Table (4 / 12)
90
Interrupt
Line No
Interrupt Name
Interrupt Description
77
EIC0IRQ8
External Interrupt 8
(EIC0_EIRR:ER8 is set when an interrupt condition is detected at the corresponding input pin)
78
EIC0IRQ9
External Interrupt 9
(EIC0_EIRR:ER9 is set when an interrupt condition is detected at the corresponding input pin)
79
EIC0IRQ10
External Interrupt 10
(EIC0_EIRR:ER10 is set when an interrupt condition is detected at the corresponding input pin)
80
EIC0IRQ11
External Interrupt 11
(EIC0_EIRR:ER11 is set when an interrupt condition is detected at the corresponding input pin)
81
EIC0IRQ12
External Interrupt 12
(EIC0_EIRR:ER12 is set when an interrupt condition is detected at the corresponding input pin)
82
EIC0IRQ13
External Interrupt 13
(EIC0_EIRR:ER13 is set when an interrupt condition is detected at the corresponding input pin)
83
EIC0IRQ14
External Interrupt 14
(EIC0_EIRR:ER14 is set when an interrupt condition is detected at the corresponding input pin)
84
EIC0IRQ15
External Interrupt 15
(EIC0_EIRR:ER15 is set when an interrupt condition is detected at the corresponding input pin)
85
EIC0IRQ16
External Interrupt 16
(EIC0_EIRR:ER16 is set when an interrupt condition is detected at the corresponding input pin)
86
EIC0IRQ17
External Interrupt 17
(EIC0_EIRR:ER17 is set when an interrupt condition is detected at the corresponding input pin)
87
EIC0IRQ18
External Interrupt 18
(EIC0_EIRR:ER18 is set when an interrupt condition is detected at the corresponding input pin)
88
EIC0IRQ19
External Interrupt 19
(EIC0_EIRR:ER19 is set when an interrupt condition is detected at the corresponding input pin)
89
EIC0IRQ20
External Interrupt 20
(EIC0_EIRR:ER20 is set when an interrupt condition is detected at the corresponding input pin)
90
EIC0IRQ21
External Interrupt 21
(EIC0_EIRR:ER21 is set when an interrupt condition is detected at the corresponding input pin)
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 4-1: Interrupt Table (5 / 12)
Interrupt
Line No
Interrupt Name
Interrupt Description
91
EIC0IRQ22
External Interrupt 22
(EIC0_EIRR:ER22 is set when an interrupt condition is detected at the corresponding input pin)
92
EIC0IRQ23
External Interrupt 23
(EIC0_EIRR:ER23 is set when an interrupt condition is detected at the corresponding input pin)
93
EIC0IRQ24
External Interrupt 24
(EIC0_EIRR:ER24 is set when an interrupt condition is detected at the corresponding input pin)
94
EIC0IRQ25
External Interrupt 25
(EIC0_EIRR:ER25 is set when an interrupt condition is detected at the corresponding input pin)
95
EIC0IRQ26
External Interrupt 26
(EIC0_EIRR:ER26 is set when an interrupt condition is detected at the corresponding input pin)
96
EIC0IRQ27
External Interrupt 27
(EIC0_EIRR:ER27 is set when an interrupt condition is detected at the corresponding input pin)
97
EIC0IRQ28
External Interrupt 28
(EIC0_EIRR:ER28 is set when an interrupt condition is detected at the corresponding input pin)
98
EIC0IRQ29
External Interrupt 29
(EIC0_EIRR:ER29 is set when an interrupt condition is detected at the corresponding input pin)
99
EIC0IRQ30
External Interrupt 30
(EIC0_EIRR:ER30 is set when an interrupt condition is detected at the corresponding input pin)
100
EIC0IRQ31
External Interrupt 31
(EIC0_EIRR:ER31 is set when an interrupt condition is detected at the corresponding input pin)
101
RTCIRQ
Real Time Clock Interrupt
(check RTC_WINS:[6:0] for detailed Real Time Clock interrupt cause)
102
SG0IRQ
Sound Generator 0 Interrupt
(SG0_CR1:ZAINT (zero amplitude interrupt),
SG0_CR1:TCINT (tone pulse count interrupt),
SG0_CR1:AMINT (amplitude match interrupt))
104
FRT0IRQ
Free Running Timer 0 Interrupt
(FRT0_TCCS:IVF (compare clear match/counter overflow),
FRT0_ETCCS:IRQZF (counter zero detection))
105
FRT1IRQ
Free Running Timer 1 Interrupt
(FRT1_TCCS:IVF (compare clear match/counter overflow),
FRT1_ETCCS:IRQZF (counter zero detection))
January 30, 2015, MB9EF226_DS707-00004-2v1-E
91
Data
Shee t
Table 4-1: Interrupt Table (6 / 12)
92
Interrupt
Line No
Interrupt Name
Interrupt Description
106
FRT2IRQ
Free Running Timer 2 Interrupt
(FRT2_TCCS:IVF (compare clear match/counter overflow),
FRT2_ETCCS:IRQZF (counter zero detection))
107
FRT3IRQ
Free Running Timer 3 Interrupt
(FRT3_TCCS:IVF (compare clear match/counter overflow),
FRT3_ETCCS:IRQZF (counter zero detection)
112
FRT16IRQ
Free Running Timer 16 Interrupt
(FRT16_TCCS:IVF (compare clear match/counter overflow),
FRT16_ETCCS:IRQZF (counter zero detection))
113
FRT17IRQ
Free Running Timer 17 Interrupt
(FRT17_TCCS:IVF (compare clear match/counter overflow),
FRT17_ETCCS:IRQZF (counter zero detection))
114
FRT18IRQ
Free Running Timer 18 Interrupt
(FRT0_TCCS:IVF (compare clear match/counter overflow),
FRT18_ETCCS:IRQZF (counter zero detection))
115
FRT19IRQ
Free Running Timer 19 Interrupt
(FRT19_TCCS:IVF (compare clear match/counter overflow),
FRT19_ETCCS:IRQZF (counter zero detection))
124
ICU2IRQ0
Input Capture Unit 2 channel 0 Interrupt (ICU2_ICEICS01:IDSE0)
125
ICU2IRQ1
Input Capture Unit 2 channel 1 Interrupt (ICU2_ICEICS01:IDSE1)
126
ICU3IRQ0
Input Capture Unit 3 channel 0 Interrupt (ICU3_ICEICS01:IDSE0)
127
ICU3IRQ1
Input Capture Unit 3 channel 1 Interrupt (ICU3_ICEICS01:IDSE1)
132
ICU18IRQ0
Input Capture Unit 18 channel 0 Interrupt (ICU18_ICEICS01:IDSE0)
133
ICU18IRQ1
Input Capture Unit 18 channel 1 Interrupt (ICU18_ICEICS01:IDSE1)
134
ICU19IRQ0
Input Capture Unit 19 channel 0 Interrupt (ICU19_ICEICS01:IDSE0)
135
ICU19IRQ1
Input Capture Unit 19 channel 1 Interrupt (ICU19_ICEICS01:IDSE1)
136
OCU0IRQ0
Output Compare Unit 1 channel 0 Interrupt
(OCU0_OSR01:ICP0)
137
OCU0IRQ1
Output Compare Unit 0 channel 1 Interrupt
(OCU0_OSR01:ICP1)
138
OCU1IRQ0
Output Compare Unit 1 channel 0 Interrupt
(OCU1_OSR01:ICP0)
139
OCU1IRQ1
Output Compare Unit 1 channel 1 Interrupt
(OCU1_OSR01:ICP1)
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 4-1: Interrupt Table (7 / 12)
Interrupt
Line No
Interrupt Name
Interrupt Description
144
OCU16IRQ0
Output Compare Unit 16 channel 0 Interrupt
(OCU16_OSR01:ICP0)
145
OCU16IRQ1
Output Compare Unit 16 channel 1 Interrupt
(OCU16_OSR01:ICP1)
146
OCU17IRQ0
Output Compare Unit 17 channel 0 Interrupt
(OCU17_OSR01:ICP0)
147
OCU17IRQ1
Output Compare Unit 17 channel 1 Interrupt
(OCU17_OSR01:ICP1)
USART0IRQRX
LIN USART 0 Receive Interrupt
(UART0_SSR:RDF (receive data full), USART0_ESR:RXHRI (automatic reception of LIN header completed))
USART0IRQTX
LIN USART 0 Transmit Interrupt
(UART0_SSR:TDRE (transmission data empty), USART0_ECCR:RBI = 1 and USART0_ECCR:TBI = 1 and USART0_ECCR:BIE = 1 (bus idle interrupt),
USART0_ESR:LBSOF (transmitted last bit in synchronous/
asynchronous mode), USART0_ESR:TXHRI (automatic
transmission of LIN header completed))
USART0IRQERR
LIN USART 0 Error Interrupt
(USART0_SSR:PE (parity error), USART0_SSR:ORE (overrun error), USART0_SSR:FRE (framing error), USART0_CSCR:CRCERR (error found in checksum validation),
USART0_ESR:SYNFE (sync field detection timeout), USART0_ESR:BUSERR (bus error occurred), USART0_ESR:PEFRD (parity error in received frame ID))
USART6IRQRX
LIN USART 6 Receive Interrupt
(UART6_SSR:RDF (receive data full), USART6_ESR:RXHRI (automatic reception of LIN header completed))
USART6IRQTX
LIN USART 6 Transmit Interrupt
(UART0_SSR:TDRE (transmission data empty), USART6_ECCR:RBI = 1 and USART6_ECCR:TBI = 1 and USART6_ECCR:BIE = 1 (bus idle interrupt),
USART0_ESR:LBSOF (transmitted last bit in synchronous/
asynchronous mode), USART0_ESR:TXHRI (automatic
transmission of LIN header completed))
160
USART6IRQERR
LIN USART 6 Error Interrupt
(USART0_SSR:PE (parity error), USART6_SSR:ORE (overrun error), USART6_SSR:FRE (framing error), USART6_CSCR:CRCERR (error found in checksum validation),
USART0_ESR:SYNFE (sync field detection timeout), USART0_ESR:BUSERR (bus error occurred), USART0_ESR:PEFRD (parity error in received frame ID))
164
DMA0IRQD0
DMA0 Completion Interrupt for channels 0 + 8*n (DMACDIRQ1:DIRQ[24, 16, 8, 0] and DMACDIRQ2:DIRQ[56, 48,
40, 32])
152
153
154
158
159
January 30, 2015, MB9EF226_DS707-00004-2v1-E
93
Data
Shee t
Table 4-1: Interrupt Table (8 / 12)
94
Interrupt
Line No
Interrupt Name
Interrupt Description
165
DMA0IRQD1
DMA0 Completion Interrupt for channels 1 + 8*n (DMACDIRQ1:DIRQ[25, 17, 9, 1] and DMACDIRQ2:DIRQ[57, 49,
41, 33])
166
DMA0IRQD2
DMA0 Completion Interrupt for channels 2 + 8*n (DMACDIRQ1:DIRQ[26, 18, 10, 2] and DMACDIRQ2:DIRQ[58,50,
42, 34])
167
DMA0IRQD3
DMA0 Completion Interrupt for channels 3 + 8*n (DMACDIRQ1:DIRQ[27, 19, 11, 3] and DMACDIRQ2:DIRQ[59, 51,
43, 35])
168
DMA0IRQD4
DMA0 Completion Interrupt for channels 4 + 8*n (DMACDIRQ1:DIRQ[28, 20, 12, 4] and DMACDIRQ2:DIRQ[60, 52,
44, 36])
169
DMA0IRQD5
DMA0 Completion Interrupt for channels 5 + 8*n (DMACDIRQ1:DIRQ[29, 21, 13, 5] and DMACDIRQ2:DIRQ[61, 53,
45, 37])
170
DMA0IRQD6
DMA0 Completion Interrupt for channels 6 + 8*n (DMACDIRQ1:DIRQ[30, 22, 14, 6] and DMACDIRQ2:DIRQ[62, 54,
46, 38])
171
DMA0IRQD7
DMA0 Completion Interrupt for channels 7 + 8*n (DMACDIRQ1:DIRQ[31, 23, 15, 7] and DMACDIRQ2:DIRQ[63, 55,
47, 39])
172
DMA0IRQERR
DMA0 Error Interrupt
(DMACEDIRQ1:EDIRQ[31:0] and
DMACEDIRQ2:EDIRQ[63:32])
173
MSCTIRQ
Main Source Clock Timer Interrupt (SYSC_MAINSCTSTATR:INTF is set when counter matches or is greater than
the corresponding compare register)
174
SSCTIRQ
Sub Source Clock Timer Interrupt (SYSC_SUBSCTSTATR:INTF is set when counter matches or is greater than
the corresponding compare register)
175
RCSCTIRQ
RC Source Clock Timer Interrupt (SYSC_RCSCTSTATR:INTF is set when counter matches or is greater than the corresponding compare register)
176
SRCSCTIRQ
Slow RC Source Clock Timer Interrupt (SYSC_SRCSCTSTATR:INTF is set when counter matches or is greater than
the corresponding compare register)
177
CORE0IRQ
CORTEX R4 Performance Monitor Interrupt
178
RLT0IRQ
Reload Timer 0 Interrupt
(RLT0_TMCSR:UF is set when reload timer counter underflows)
179
RLT1IRQ
Reload Timer 1 Interrupt
(RLT1_TMCSR:UF is set when reload timer counter underflows)
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 4-1: Interrupt Table (9 / 12)
Interrupt
Line No
Interrupt Name
Interrupt Description
180
RLT2IRQ
Reload Timer 2 Interrupt
(RLT2_TMCSR:UF is set when reload timer counter underflows)
181
RLT3IRQ
Reload Timer 3 Interrupt
(RLT3_TMCSR:UF is set when reload timer counter underflows)
182
RLT4IRQ
Reload Timer 4 Interrupt
(RLT4_TMCSR:UF is set when reload timer counter underflows)
183
RLT5IRQ
Reload Timer 5 Interrupt
(RLT5_TMCSR:UF is set when reload timer counter underflows)
184
RLT6IRQ
Reload Timer 6 Interrupt
(RLT6_TMCSR:UF is set when reload timer counter underflows)
185
RLT7IRQ
Reload Timer 7 Interrupt
(RLT7_TMCSR:UF is set when reload timer counter underflows)
186
RLT8IRQ
Reload Timer 8 Interrupt
(RLT8_TMCSR:UF is set when reload timer counter underflows)
187
RLT9IRQ
Reload Timer 9 Interrupt
(RLT9_TMCSR:UF is set when reload timer counter underflows)
194
UDC0IRQ0
Up/Down Counter 0 channel 0 Interrupt
(UDN0_CS0:OVFF (overflow), UDFF (underflow), CMPF
(compare match))
195
UDC0IRQ1
Up/Down Counter 0 channel 1 Interrupt
(UDN0_CS1:OVFF (overflow), UDFF (underflow), CMPF
(compare match))
198
I2S0IRQ
I2S0 Interrupt
(check I2S0_STATUS:[31:24], [19], [17:16] for detailed interrupt cause)
199
I2S1IRQ
I2S1 Interrupt
(check I2S1_STATUS:[31:24], [19], [17:16] for detailed interrupt cause)
I2C0IRQ
I2C0 Interrupt
(I2C0_IBCSR_INT (masked by I2C0_IBCSR_INTE) set after
end of 1 byte data transfer or reception including acknowledge bit (bus master, addressed as slave, GCA received, Arbitration lost),
I2C0_IBCSR_BER (masked by I2C0_IBCSR_BEIE) indicates bus error (Start- or Stop-Condition detected at wrong
places))
202
January 30, 2015, MB9EF226_DS707-00004-2v1-E
95
Data
Shee t
Table 4-1: Interrupt Table (10 / 12)
Interrupt
Line No
Interrupt Name
Interrupt Description
203
I2C0IRQERR
I2C0 Error Interrupt
(I2C0_IBCSR_BER (masked by I2C0_IEIER_BEREIE) indicates bus error (Start- or Stop-Condition detected at wrong
places), I2C0_IBCSR_AL (masked by I2C0_IEIER_ALEIE)
indicates arbitration lost)
206
CRC0IRQ
CRC0 Interrupt
(CRC0_CFG:CIRQ set after checksum is calculated and
available in register)
PPG0IRQ
Programmable Pulse Generator 0 Interrupt
(PPG0_PCN:IRQF set depending on PPG0_PCN:IRS[2:0],
PPG0_EPCN1:TRIG set when PWM output generation is
started, PPG0_EPCN2:[7:0] see detailed description in docu)
Programmable Pulse Generator 0 Interrupt
PPG1IRQ
Programmable Pulse Generator 1 Interrupt
(PPG1_PCN:IRQF set depending on PPG1_PCN:IRS[2:0],
PPG1_EPCN1:TRIG set when PWM output generation is
started, PPG1_EPCN2:[7:0] see detailed description in docu)
PPG2IRQ
Programmable Pulse Generator 2 Interrupt
(PPG2_PCN:IRQF set depending on PPG2_PCN:IRS[2:0],
PP2_EPCN1:TRIG set when PWM output generation is started, PPG2_EPCN2:[7:0] see detailed description in docu)
PPG3IRQ
Programmable Pulse Generator 3 Interrupt
(PPG3_PCN:IRQF set depending on PPG3_PCN:IRS[2:0],
PPG0_EPCN1:TRIG set when PWM output generation is
started, PPG3_EPCN2:[7:0] see detailed description in docu)
PPG4IRQ
Programmable Pulse Generator 4 Interrupt
(PPG4_PCN:IRQF set depending on PPG4_PCN:IRS[2:0],
PPG4_EPCN1:TRIG set when PWM output generation is
started, PPG4_EPCN2:[7:0] see detailed description in docu)
PPG5IRQ
Programmable Pulse Generator 5 Interrupt
(PPG5_PCN:IRQF set depending on PPG5_PCN:IRS[2:0],
PPG5_EPCN1:TRIG set when PWM output generation is
started, PPG5_EPCN2:[7:0] see detailed description in docu)
PPG6IRQ
Programmable Pulse Generator 6 Interrupt
(PPG6_PCN:IRQF set depending on PPG6_PCN:IRS[2:0],
PPG6_EPCN1:TRIG set when PWM output generation is
started, PPG6_EPCN2:[7:0] see detailed description in docu)
PPG7IRQ
Programmable Pulse Generator 7 Interrupt
(PPG7_PCN:IRQF set depending on PPG7_PCN:IRS[2:0],
PPG7_EPCN1:TRIG set when PWM output generation is
started, PPG7_EPCN2:[7:0] see detailed description in docu)
PPG8IRQ
Programmable Pulse Generator 8 Interrupt
(PPG8_PCN:IRQF set depending on PPG8_PCN:IRS[2:0],
PPG8_EPCN1:TRIG set when PWM output generation is
started, PPG8_EPCN2:[7:0] see detailed description in docu)
208
209
210
211
212
213
214
215
216
96
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 4-1: Interrupt Table (11 / 12)
Interrupt
Line No
217
218
219
220
221
222
223
232
233
Interrupt Name
Interrupt Description
PPG9IRQ
Programmable Pulse Generator 9 Interrupt
(PPG9_PCN:IRQF set depending on PPG9_PCN:IRS[2:0],
PPG9_EPCN1:TRIG set when PWM output generation is
started, PPG9_EPCN2:[7:0] see detailed description in docu)
PPG10IRQ
Programmable Pulse Generator 10 Interrupt
(PPG10_PCN:IRQF set depending on
PPG10_PCN:IRS[2:0], PPG10_EPCN1:TRIG set when
PWM output generation is started, PPG10_EPCN2:[7:0] see
detailed description in docu)
PPG11IRQ
Programmable Pulse Generator 11 Interrupt
(PPG11_PCN:IRQF set depending on
PPG11_PCN:IRS[2:0], PPG11_EPCN1:TRIG set when
PWM output generation is started, PPG11_EPCN2:[7:0] see
detailed description in docu)
PPG12IRQ
Programmable Pulse Generator 12 Interrupt
(PPG12_PCN:IRQF set depending on
PPG12_PCN:IRS[2:0], PPG12_EPCN1:TRIG set when
PWM output generation is started, PPG12_EPCN2:[7:0] see
detailed description in docu)
PPG13IRQ
Programmable Pulse Generator 13 Interrupt
(PPG13_PCN:IRQF set depending on
PPG13_PCN:IRS[2:0], PPG13_EPCN1:TRIG set when
PWM output generation is started, PPG13_EPCN2:[7:0] see
detailed description in docu)
PPG14IRQ
Programmable Pulse Generator 14 Interrupt
(PPG14_PCN:IRQF set depending on
PPG14_PCN:IRS[2:0], PPG14_EPCN1:TRIG set when
PWM output generation is started, PPG14_EPCN2:[7:0] see
detailed description in docu)
PPG15IRQ
Programmable Pulse Generator 15 Interrupt
(PPG15_PCN:IRQF set depending on
PPG15_PCN:IRS[2:0], PPG15_EPCN1:TRIG set when
PWM output generation is started, PPG15_EPCN2:[7:0] see
detailed description in docu)
PPG64IRQ
Programmable Pulse Generator 64 Interrupt
(PPG64_PCN:IRQF set depending on
PPG64_PCN:IRS[2:0], PPG64_EPCN1:TRIG set when
PWM output generation is started, PPG64_EPCN2:[7:0] see
detailed description in docu)
PPG65IRQ
Programmable Pulse Generator 65 Interrupt
(PPG65_PCN:IRQF set depending on
PPG65_PCN:IRS[2:0], PPG65_EPCN1:TRIG set when
PWM output generation is started, PPG65_EPCN2:[7:0] see
detailed description in docu)
January 30, 2015, MB9EF226_DS707-00004-2v1-E
97
Data
Shee t
Table 4-1: Interrupt Table (12 / 12)
Interrupt
Line No
234
235
236
237
238
239
98
Interrupt Name
Interrupt Description
PPG66IRQ
Programmable Pulse Generator 66 Interrupt
(PPG66_PCN:IRQF set depending on
PPG66_PCN:IRS[2:0], PPG66_EPCN1:TRIG set when
PWM output generation is started, PPG66_EPCN2:[7:0] see
detailed description in docu)
PPG67IRQ
Programmable Pulse Generator 67 Interrupt
(PPG67_PCN:IRQF set depending on
PPG67_PCN:IRS[2:0], PPG67_EPCN1:TRIG set when
PWM output generation is started, PPG67_EPCN2:[7:0] see
detailed description in docu)
PPG68IRQ
Programmable Pulse Generator 68 Interrupt
(PPG68_PCN:IRQF set depending on
PPG68_PCN:IRS[2:0], PPG68_EPCN1:TRIG set when
PWM output generation is started, PPG68_EPCN2:[7:0] see
detailed description in docu)
PPG69IRQ
Programmable Pulse Generator 69 Interrupt
(PPG69_PCN:IRQF set depending on
PPG69_PCN:IRS[2:0], PPG69_EPCN1:TRIG set when
PWM output generation is started, PPG69_EPCN2:[7:0] see
detailed description in docu)
PPG70IRQ
Programmable Pulse Generator 70 Interrupt
(PPG70_PCN:IRQF set depending on
PPG70_PCN:IRS[2:0], PPG70_EPCN1:TRIG set when
PWM output generation is started, PPG70_EPCN2:[7:0] see
detailed description in docu)
PPG71IRQ
Programmable Pulse Generator 71 Interrupt
(PPG71_PCN:IRQF set depending on
PPG71_PCN:IRS[2:0], PPG71_EPCN1:TRIG set when
PWM output generation is started, PPG71_EPCN2:[7:0] see
detailed description in docu)
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
4.2
Sh eet
NMI
Table 4-2: List of NMI
NMI Number
Source
Description
0
EIC0NMI
1
SYSCNMILVD
Low Voltage Detect NMI (check SYSC_SYSERRR:LVD12IF,
SYSC_SYSERRR:LVD33IF, SYSC_SYSERRR:LVD50IF for detailed
NMI cause)
2
SYSCNMIERR
System Controller Error NMI (check SYSC_SYSERRR:RUNERRIF,
SYSC_SYSERRR:RUNWKERRIF,
SYSC_SYSERRR:PSSERRIF,
SYSC_SYSERRR:TRGERRIF,
SYSC_SYSERRR:RUNTRGEIF,
SYSC_SYSERRR:MOMISSIF,
SYSC_SYSERRR:SOMISSIF,
SYSC_SYSERRR:MPMISSIF,
SYSC_SYSERRR:SPMISSIF,
SYSC_SYSERRR:GPMISSIF,
SYSC_SYSERRR:PSSENEIF for detailed NMI cause)
3
WDGNMI
Watchdog NMI (WDG_INT:NMI_FLAG is set on Watchdog error condition if WDG_INT:NMI_EN is '1')
4
TPU0NMI
Timing Protection Unit NMI (check TPU0TIR:IR[7:0] bits for detailed
NMI cause)
Note: The Timing Protection Unit NMI is maskable within the TPU but
non-maskable on system level.
5
MPUXDMA0NMI
MPU DMA0 Access Violation NMI (MPUXDMA0_CTRL0:NMI is set
when a memory protection violation by DMA0 is detected)
7
MPUXGFXNMI
MPU IRIS-SDL Access Violation NMI(MPUXGFX_CTRL0:NMI is set
when a memory protection violation by IRIS-SDL is detected)
8
MPUHMLB0NMI
MPU MLB0 Access Violation NMI(MPUHMLB0_CTRL0:NMI is set
when a memory protection violation by MLB0 is detected)
9
IRQ0NMIERR
IRQ Double Error NMI (IRQ0_EEI:EENS bit is set when a double bit
error is detected in the IRQ0 Interrupt Vector RAM)
11
BECU0NMI
BECU0 Access Violation NMI (BECU0_CTRL:NMI bit is set when a
bus error is detected on the Peripheral Group 0 bus)
12
BECU1NMI
BECU1 Access Violation NMI (BECU1_CTRL:NMI bit is set when a
bus error is detected on the Peripheral Group 1 bus)
13
BECU3NMI
BECU3 Access Violation NMI (BECU3_CTRL:NMI bit is set when a
bus error is detected on the Peripheral Group 3 bus)
14
GFXNMI
GFX Signature Unit NMI (GFXGCTR_NmiStatus:NmiStatus is set if
the number of error frames has exceeded the threshold value)
18
MPUSHE
MPU SHE Access Violation NMI(MPUXSHE0_CTRL0:NMI is set
when a memory protection violation by SHE is detected)
External Pin NMI (EIC0_NMIR:NMIINT)
January 30, 2015, MB9EF226_DS707-00004-2v1-E
99
Data
4.3
Shee t
DMA Overview
Table 4-3: Modules with DMA (1 / 6)
100
DMA Request
No
DMA Request
Name
DMA Request Description
0
EXTDMA0
External DMA Request 0 (external pin DMA0_DREQ0)
1
EXTDMA1
External DMA Request 1 (external pin DMA0_DREQ0)
8
EIC0DMA0
External Interrupt 0 DMA Request (EIC0_DRFR:DRF0)
9
EIC0DMA1
External Interrupt 1 DMA Request (EIC0_DRFR:DRF1)
10
EIC0DMA2
External Interrupt 2 DMA Request (EIC0_DRFR:DRF2)
11
EIC0DMA3
External Interrupt 3 DMA Request (EIC0_DRFR:DRF3)
12
EIC0DMA4
External Interrupt 4 DMA Request (EIC0_DRFR:DRF4)
13
EIC0DMA5
External Interrupt 5 DMA Request (EIC0_DRFR:DRF5)
14
EIC0DMA6
External Interrupt 6 DMA Request (EIC0_DRFR:DRF6)
15
EIC0DMA7
External Interrupt 7 DMA Request (EIC0_DRFR:DRF7)
16
EIC0DMA8
External Interrupt 8 DMA Request (EIC0_DRFR:DRF8)
17
EIC0DMA9
External Interrupt 9 DMA Request (EIC0_DRFR:DRF9)
18
EIC0DMA10
External Interrupt 10 DMA Request (EIC0_DRFR:DRF10)
19
EIC0DMA11
External Interrupt 11 DMA Request (EIC0_DRFR:DRF11)
20
EIC0DMA12
External Interrupt 12 DMA Request (EIC0_DRFR:DRF12)
21
EIC0DMA13
External Interrupt 13 DMA Request (EIC0_DRFR:DRF13)
22
EIC0DMA14
External Interrupt 14 DMA Request (EIC0_DRFR:DRF14)
23
EIC0DMA15
External Interrupt 15 DMA Request (EIC0_DRFR:DRF15)
24
EIC0DMA16
External Interrupt 16 DMA Request(EIC0_DRFR:DRF16)
25
EIC0DMA17
External Interrupt 17 DMA Request (EIC0_DRFR:DRF17)
26
EIC0DMA18
External Interrupt 18 DMA Request (EIC0_DRFR:DRF18)
27
EIC0DMA19
External Interrupt 19 DMA Request (EIC0_DRFR:DRF19)
28
EIC0DMA20
External Interrupt 20 DMA Request (EIC0_DRFR:DRF20)
29
EIC0DMA21
External Interrupt 21 DMA Request (EIC0_DRFR:DRF21)
30
EIC0DMA22
External Interrupt 22 DMA Request (EIC0_DRFR:DRF22)
31
EIC0DMA23
External Interrupt 23 DMA Request (EIC0_DRFR:DRF23)
32
EIC0DMA24
External Interrupt 24 DMA Request (EIC0_DRFR:DRF24)
33
EIC0DMA25
External Interrupt 25 DMA Request (EIC0_DRFR:DRF25)
34
EIC0DMA26
External Interrupt 26 DMA Request (EIC0_DRFR:DRF26)
35
EIC0DMA27
External Interrupt 27 DMA Request (EIC0_DRFR:DRF27)
36
EIC0DMA28
External Interrupt 28 DMA Request (EIC0_DRFR:DRF28)
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 4-3: Modules with DMA (2 / 6)
DMA Request
No
DMA Request
Name
DMA Request Description
37
EIC0DMA29
External Interrupt 29 DMA Request (EIC0_DRFR:DRF29)
38
EIC0DMA30
External Interrupt 30 DMA Request (EIC0_DRFR:DRF30)
39
EIC0DMA31
External Interrupt 31 DMA Request (EIC0_DRFR:DRF31)
40
SG0DMA
Sound Generator 0 DMA Request
(SG0_CR1:AMINT* (amplitude match flag)
SG0_CR1:TCINT* (tone pulse count match flag)
SG0_CR1:ZAINT* (zero amplitude flag))
44
HSSPI0DMARX
HSSPI0 Receive DMA Request
(HSSPI0_RXF:RFMTS*
(RX FIFO fill level more than threshold))
45
HSSPI0DMATX
HSSPI0 Transmit DMA Request
(HSSPI0_TXF:TFLETS*
(TX FIFO fill level less or equal to threshold))
48
FRT0DMA
Free Running Timer 0 DMA Request
(FRT0_TCCS:IVF* (compare clear flag);
FRT0_ETCCS:IRQZF* (zero detect flag))
49
FRT1DMA
FFree Running Timer 1 DMA Request
(FRT1_TCCS:IVF* (compare clear flag);
FRT1_ETCCS:IRQZF* (zero detect flag))
50
FRT2DMA
Free Running Timer 2 DMA Request
(FRT2_TCCS:IVF* (compare clear flag);
FRT2_ETCCS:IRQZF* (zero detect flag))
51
FRT3DMA
Free Running Timer 3 DMA Request
(FRT3_TCCS:IVF* (compare clear flag);
FRT3_ETCCS:IRQZF* (zero detect flag))
64
FRT16DMA
Free Running Timer 16 DMA Request
(FRT16_TCCS:IVF* (compare clear flag);
FRT16_ETCCS:IRQZF* (zero detect flag))
65
FRT17DMA
Free Running Timer 17 DMA Request
(FRT17_TCCS:IVF* (compare clear flag);
FRT17_ETCCS:IRQZF* (zero detect flag))
66
FRT18DMA
Free Running Timer 18 DMA Request
(FRT18_TCCS:IVF* (compare clear flag);
FRT18_ETCCS:IRQZF* (zero detect flag))
67
FRT19DMA
Free Running Timer 19 DMA Request
(FRT19_TCCS:IVF* (compare clear flag);
FRT19_ETCCS:IRQZF* (zero detect flag))
84
ICU2DMA0
Input Capture Unit 2 channel 0 DMA Request
(ICU2_ICEICS01:ICP0*)
85
ICU2DMA1
Input Capture Unit 2 channel 1 DMA Request
(ICU2_ICEICS01:ICP1*)
86
ICU3DMA0
Input Capture Unit 3 channel 0 DMA Request
(ICU2_ICEICS01:ICP0*)
January 30, 2015, MB9EF226_DS707-00004-2v1-E
101
Data
Shee t
Table 4-3: Modules with DMA (3 / 6)
102
DMA Request
No
DMA Request
Name
DMA Request Description
87
ICU3DMA1
Input Capture Unit 3 channel 1 DMA Request
(ICU2_ICEICS01:ICP1*)
116
ICU18DMA0
Input Capture Unit 18 channel 0 DMA Request
(ICU18_ICEICS01:ICP0*)
117
ICU18DMA1
Input Capture Unit 18 channel 1 DMA Request
(ICU18_ICEICS01:ICP1*)
118
ICU19DMA0
Input Capture Unit 19 channel 0 DMA Request
(ICU19_ICEICS01:ICP0*)
119
ICU19DMA1
Input Capture Unit 19 channel 1 DMA Request
(ICU19_ICEICS01:ICP1*)
144
OCU0DMA0
Output Compare Unit 0 channel 0 DMA Request
(OCU0_OSR01:ICP0*)
145
OCU0DMA1
Output Compare Unit 0 channel 1 DMA Request
(OCU0_OSR01:ICP1*)
146
OCU1DMA0
Output Compare Unit 1 channel 0 DMA Request
(OCU1_OSR01:ICP0*)
147
OCU1DMA1
Output Compare Unit 1 channel 1 DMA Request
(OCU1_OSR01:ICP1*)
176
OCU16DMA0
Output Compare Unit 16 channel 0 DMA Request
(OCU16_OSR01:ICP0*)
177
OCU16DMA1
Output Compare Unit 16 channel 1 DMA Request
(OCU16_OSR01:ICP1*)
178
OCU17DMA0
Output Compare Unit 17 channel 0 DMA Request
(OCU17_OSR01:ICP0*)
179
OCU17DMA1
Output Compare Unit 17 channel 1 DMA Request
(OCU17_OSR01:ICP1*)
208
USART0DMARX
LIN USART 0 Receive DMA Request
(USART0_SSR:RDRF* (RX data full flag))
209
USART0DMATX
LIN USART 0 Transmit DMA Request
(USART0_SSR:TDRE* (TX data empty flag))
220
USART6DMARX
LIN USART 6 Receive DMA Request
(USART6_SSR:RDRF* (RX data full flag))
221
USART6DMATX
LIN USART 6 Transmit DMA Request
(USART6_SSR:TDRE* (TX data empty flag))
232
I2C0DMARX
I2C0 Receive DMA Request (I2C0_IBCSR:INT*)
233
I2C0DMATX
I2C0 Transmit DMA Request (I2C0_IBCSR:INT*)
244
PPG0DMA
Programmable Pulse Generator 0 DMA Request
(PPG0_PCN:IRQF*)
245
PPG1DMA
Programmable Pulse Generator 1 DMA Request
(PPG1_PCN:IRQF*)
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 4-3: Modules with DMA (4 / 6)
DMA Request
No
DMA Request
Name
DMA Request Description
246
PPG2DMA
Programmable Pulse Generator 2 DMA Request
(PPG2_PCN:IRQF*)
247
PPG3DMA
Programmable Pulse Generator 3 DMA Request
(PPG3_PCN:IRQF*)
248
PPG4DMA
Programmable Pulse Generator 4 DMA Request
(PPG4_PCN:IRQF*)
249
PPG5DMA
Programmable Pulse Generator 5 DMA Request
(PPG5_PCN:IRQF*)
250
PPG6DMA
Programmable Pulse Generator 6 DMA Request
(PPG6_PCN:IRQF*)
251
PPG7DMA
Programmable Pulse Generator 7 DMA Request
(PPG7_PCN:IRQF*)
252
PPG8DMA
Programmable Pulse Generator 8 DMA Request
(PPG8_PCN:IRQF*)
253
PPG9DMA
Programmable Pulse Generator 9 DMA Request
(PPG9_PCN:IRQF*)
254
PPG10DMA
Programmable Pulse Generator 10 DMA Request
(PPG10_PCN:IRQF*)
255
PPG11DMA
Programmable Pulse Generator 11 DMA Request
(PPG11_PCN:IRQF*)
256
PPG12DMA
Programmable Pulse Generator 12 DMA Request
(PPG12_PCN:IRQF*)
257
PPG13DMA
Programmable Pulse Generator 13 DMA Request
(PPG13_PCN:IRQF*)
258
PPG14DMA
Programmable Pulse Generator 14 DMA Request
(PPG14_PCN:IRQF*)
259
PPG15DMA
Programmable Pulse Generator 15 DMA Request
(PPG15_PCN:IRQF*)
308
PPG64DMA
Programmable Pulse Generator 64 DMA Request
(PPG64_PCN:IRQF*)
309
PPG65DMA
Programmable Pulse Generator 65 DMA Request
(PPG65_PCN:IRQF*)
310
PPG66DMA
Programmable Pulse Generator 66 DMA Request
(PPG66_PCN:IRQF*)
311
PPG67DMA
Programmable Pulse Generator 67 DMA Request
(PPG67_PCN:IRQF*)
312
PPG68DMA
Programmable Pulse Generator68 DMA Request
(PPG68_PCN:IRQF*)
313
PPG69DMA
Programmable Pulse Generator 69 DMA Request
(PPG69_PCN:IRQF*)
January 30, 2015, MB9EF226_DS707-00004-2v1-E
103
Data
Shee t
Table 4-3: Modules with DMA (5 / 6)
104
DMA Request
No
DMA Request
Name
DMA Request Description
314
PPG70DMA
Programmable Pulse Generator 70 DMA Request
(PPG70_PCN:IRQF*)
315
PPG71DMA
Programmable Pulse Generator 71 DMA Request
(PPG71_PCN:IRQF*)
372
ADC0DMA
ADC0 Conversion End DMA Request
(ADC0_CS1:INT* (end of conversion flag))
373
ADC0DMA2
ADC0 Scan End DMA Request
(ADC0_CS3:INT2* (end of scan flag))
376
RLT0DMA
Reload Timer 0 DMA Request
(RTL0_TMCSR:UF* (underflow flag))
377
RLT1DMA
Reload Timer 1 DMA Request
(RTL1_TMCSR:UF* (underflow flag))
378
RLT2DMA
Reload Timer 2 DMA Request
(RTL2_TMCSR:UF* (underflow flag))
379
RLT3DMA
Reload Timer 3 DMA Request
(RTL3_TMCSR:UF* (underflow flag))
380
RLT4DMA
Reload Timer 4 DMA Request
(RTL4_TMCSR:UF* (underflow flag))
381
RLT5DMA
Reload Timer 5 DMA Request
(RTL5_TMCSR:UF* (underflow flag))
382
RLT6DMA
Reload Timer 6 DMA Request
(RTL6_TMCSR:UF* (underflow flag))
383
RLT7DMA
Reload Timer 7 DMA Request
(RTL7_TMCSR:UF* (underflow flag))
384
RLT8DMA
Reload Timer 8 DMA Request
(RTL8_TMCSR:UF* (underflow flag))
385
RLT9DMA
Reload Timer 9 DMA Request
(RTL9_TMCSR:UF* (underflow flag))
408
I2S0DMARX
I2S0 Receive DMA Request
(I2S0_STATUS:RXFI* (receive FIFO full))
409
I2S0DMATX
I2S0 Transmit DMA Request
(I2S0_STATUS:TXFI* (transmit FIFO empty))
410
I2S1DMARX
I2S0 Receive DMA Request
(I2S1_STATUS:RXFI* (receive FIFO full))
411
I2S1DMATX
I2S0 Transmit DMA Request
(I2S1_STATUS:TXFI* (transmit FIFO empty))
424
CRC0DMA
CRC0 DMA Request (CRC0_CFG:CIRQ* (CRC calculated flag))
426
SPI0DMARX
SPI0 Receive DMA Request
(SPI0_RXF:RFMTS* (RX FIFO fill level more than threshold))
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 4-3: Modules with DMA (6 / 6)
DMA Request
No
DMA Request
Name
DMA Request Description
427
SPI0DMATX
SPI0 Transmit DMA Request
(SPI0_TXF:TFLETS* (TX FIFO fill level less or equal to threshold))
428
SPI1DMARX
SPI1 Receive DMA Request
(SPI1_RXF:RFMTS* (RX FIFO fill level more than threshold))
429
SPI1DMATX
SPI1 Transmit DMA Request
(SPI1_TXF:TFLETS* (TX FIFO fill level less or equal to threshold))
430
SPI2DMARX
SPI2 Receive DMA Request
(SPI2_RXF:RFMTS* (RX FIFO fill level more than threshold))
431
SPI2DMATX
SPI2 Transmit DMA Request
(SPI2_TXF:TFLETS* (TX FIFO fill level less or equal to threshold))
450
EEFLASHDMA
EE Flash DMA Request (EEFCFG_WSR:ST[1:0])
467
PPUDMA
PPU DMA Request
(DMA is triggered by sucessful PPU UNLOCK (PPU0_UNLOCK)
indicated by PPU0_ST:LST = 0)
January 30, 2015, MB9EF226_DS707-00004-2v1-E
105
Data
4.4
Shee t
PPU
Table 4-4: List of PPU channels
SMC0
ADC0
SPI0
RLT0 USART0
FRT0
OCU0
PPCUSER
PPGGRP0
PPG0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PPG64
-
-
SMC1
SMC2
-
SPI1
SPI2
-
RLT1
RLT2
FRT2
FRT1
-
ICU2
-
OCU1
PPCPRIV
DBG0
PPGGRP2
PPGGRP1
PPG1
PPG2
-
PPG65
-
PPG66
-
-
SMC3
SMC4
-
-
-
RLT3
RLT4
-
FRT3
ICU3
-
WDG
MSCT
-
PPGGRP3
PPG3
PPG4
-
PPG67
-
PPG68
-
-
SMCTG0
SMC5
-
-
RLT5
RLT6 USART6
-
-
-
SSCT
RCSCT
-
PPG5
PPG6
-
PPG69
-
PPG70
-
-
-
I2C0
-
-
RLT7
RLT8
-
-
-
SRCSCT
GFXSPIMEM
-
PPG7
PPG8
-
-
-
PPG71
-
-
-
-
-
-
RLT9
-
-
-
GFXVRAM
GFXCFG
-
PPG9
PPG10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PPG11
PPG12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PPG13
PPG14
-
-
-
-
-
-
SG0
-
I2S0
HSSPI0
-
CAN0
-
-
FRT16
-
-
OCU16
-
-
PPGGRP16
-
PPG15
-
-
-
-
-
-
-
I2S1
-
CAN1
-
FRT17
-
ICU18 FRT18
-
OCU17
-
-
PPGGRP17
-
-
-
PPU0_PA15
PPU0_PR15
-
-
PPU0_PA14
PPU0_PR14
-
-
-
-
-
-
-
-
-
-
ICU19 FRT19
-
-
-
-
-
0
-
-
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
-
-
3
-
-
-
-
-
UDC0
-
-
-
-
-
-
-
CRC0
-
-
-
4
-
-
5
-
-
-
-
-
-
-
-
-
-
-
-
-
EICU0
-
-
-
6
-
-
7
-
-
-
-
-
-
-
MLB0
-
-
-
-
-
-
RTC
-
-
-
8
-
-
-
-
-
-
SHE
-
-
-
-
-
PPGGLC0
EEFCFG
-
-
-
9
-
PPU0_PA13
PPU0_PR13
-
PPU0_PA12
PPU0_PR12
-
PPU0_PA11
PPU0_PR11
-
PPU0_PA10
PPU0_PR10
-
PPU0_PA9
PPU0_PR9
-
PPU0_PA8
PPU0_PR8
-
PPU0_PA7
PPU0_PR7
-
PPU0_PA6
PPU0_PR6
-
PPU0_PA5
PPU0_PR5
PPGGLC1
PPU0_PA4
PPU0_PR4
-
PPU0_PA3
PPU0_PR3
-
PPU0_PA2
PPU0_PR2
-
PPU0_PA1
PPU0_PR1
-
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PPU0_PA0
PPU0_PR0
Note:
In general, a PPU channel controls the access in user mode to the corresponding peripheral.
However, there are a few exceptions:
— PPCPRIV controls the access to PPC in privileged mode
— PPCUSER controls the access to PPC in user mode
— MSCT, SSCT, RCSCT and SRCSCT control the access to the source clock timers within the System
Controller, i.e. the registers SYSC_MSCT*, SYSC_SSCT*, SYSC_RCSCT* and SYSC_SRCSCT,
after the corresponding source clock stabilization time has elapsed
— WDG controls the write access in user mode to the Watchdog trigger registers, so WDG has no read
attribute
106
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
— Read attribute for DBG0 is always enabled. Even privilege mode access for DBG0 needs PPU to be
enabled.
4.5
Master ID
Table 4-5: List of Master IDs used on MB9EF226 device
Master name
Master ID (USER signal values)
CPU_S0
0x04
DMA_SI
0x08
DAP_AHB
0x01
TIC_AHB
0x00
MLB0_AHB
0x02
SUBSYS (IRIS-SDL)
0x0C
SHE
0x10
January 30, 2015, MB9EF226_DS707-00004-2v1-E
107
Data
108
Shee t
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
5 I/O map
Table 5-1 Memory layout of HSSPI0 registers (1 / 4)
Offset
+3
+2
+1
+0
0xB0000000
HSSPI0_MCTRL
00000000 00000000 00000000 00000000
0xB0000004
HSSPI0_PCC0
00000000 00000001 00000000 00000000
0xB0000008
HSSPI0_PCC1
00000000 00000001 00000000 00000000
0xB000000C
HSSPI0_PCC2
00000000 00000001 00000000 00000000
0xB0000010
HSSPI0_PCC3
00000000 00000001 00000000 00000000
0xB0000014
HSSPI0_TXF
00000000 00000000 00000000 00000000
0xB0000018
HSSPI0_TXE
00000000 00000000 00000000 00000000
0xB000001C
HSSPI0_TXC
00000000 00000000 00000000 00000000
0xB0000020
HSSPI0_RXF
00000000 00000000 00000000 00000000
0xB0000024
HSSPI0_RXE
00000000 00000000 00000000 00000000
0xB0000028
HSSPI0_RXC
00000000 00000000 00000000 00000000
0xB000002C
HSSPI0_FAULTF
00000000 00000000 00000000 00000000
0xB0000030
HSSPI0_FAULTC
00000000 00000000 00000000 00000000
0xB0000034
0xB0000038
0xB000003C
read0
00000000 00000000
HSSPI0_DMTRP
00000000
HSSPI0_DMBCS
00000000 00000000
HSSPI0_DMCFG
00000001
HSSPI0_DMSTOP
00000000
HSSPI0_DMSTART
00000000
HSSPI0_DMBCC
00000000 00000000
HSSPI0_DMSTATUS
00000000 00000000 00000000 00000000
0xB0000040
0xB0000044
HSSPI0_DMPSEL
00000000
HSSPI0_DMDMAEN
00000000
read0
00000000 00000000
0xB0000048
January 30, 2015, MB9EF226_DS707-00004-2v1-E
HSSPI0_RXBITCNT
00000000
HSSPI0_TXBITCNT
00000000
HSSPI0_RXSHIFT
00000000 00000000 00000000 00000000
109
Data
Shee t
Table 5-1 Memory layout of HSSPI0 registers (2 / 4)
Offset
110
+3
+2
+1
0xB000004C
HSSPI0_FIFOCFG
00000000 00000000 00000000 01110111
0xB0000050
HSSPI0_TXFIFO0
00000000 00000000 00000000 00000000
0xB0000054
HSSPI0_TXFIFO1
00000000 00000000 00000000 00000000
0xB0000058
HSSPI0_TXFIFO2
00000000 00000000 00000000 00000000
0xB000005C
HSSPI0_TXFIFO3
00000000 00000000 00000000 00000000
0xB0000060
HSSPI0_TXFIFO4
00000000 00000000 00000000 00000000
0xB0000064
HSSPI0_TXFIFO5
00000000 00000000 00000000 00000000
0xB0000068
HSSPI0_TXFIFO6
00000000 00000000 00000000 00000000
0xB000006C
HSSPI0_TXFIFO7
00000000 00000000 00000000 00000000
0xB0000070
HSSPI0_TXFIFO8
00000000 00000000 00000000 00000000
0xB0000074
HSSPI0_TXFIFO9
00000000 00000000 00000000 00000000
0xB0000078
HSSPI0_TXFIFO10
00000000 00000000 00000000 00000000
0xB000007C
HSSPI0_TXFIFO11
00000000 00000000 00000000 00000000
0xB0000080
HSSPI0_TXFIFO12
00000000 00000000 00000000 00000000
0xB0000084
HSSPI0_TXFIFO13
00000000 00000000 00000000 00000000
0xB0000088
HSSPI0_TXFIFO14
00000000 00000000 00000000 00000000
0xB000008C
HSSPI0_TXFIFO15
00000000 00000000 00000000 00000000
0xB0000090
HSSPI0_RXFIFO0
00000000 00000000 00000000 00000000
0xB0000094
HSSPI0_RXFIFO1
00000000 00000000 00000000 00000000
0xB0000098
HSSPI0_RXFIFO2
00000000 00000000 00000000 00000000
0xB000009C
HSSPI0_RXFIFO3
00000000 00000000 00000000 00000000
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-1 Memory layout of HSSPI0 registers (3 / 4)
Offset
+3
+2
+1
+0
0xB00000A0
HSSPI0_RXFIFO4
00000000 00000000 00000000 00000000
0xB00000A4
HSSPI0_RXFIFO5
00000000 00000000 00000000 00000000
0xB00000A8
HSSPI0_RXFIFO6
00000000 00000000 00000000 00000000
0xB00000AC
HSSPI0_RXFIFO7
00000000 00000000 00000000 00000000
0xB00000B0
HSSPI0_RXFIFO8
00000000 00000000 00000000 00000000
0xB00000B4
HSSPI0_RXFIFO9
00000000 00000000 00000000 00000000
0xB00000B8
HSSPI0_RXFIFO10
00000000 00000000 00000000 00000000
0xB00000BC
HSSPI0_RXFIFO11
00000000 00000000 00000000 00000000
0xB00000C0
HSSPI0_RXFIFO12
00000000 00000000 00000000 00000000
0xB00000C4
HSSPI0_RXFIFO13
00000000 00000000 00000000 00000000
0xB00000C8
HSSPI0_RXFIFO14
00000000 00000000 00000000 00000000
0xB00000CC
HSSPI0_RXFIFO15
00000000 00000000 00000000 00000000
0xB00000D0
HSSPI0_CSCFG
00000000 00000000 00000000 00000000
0xB00000D4
HSSPI0_CSITIME
00000000 00000000 11111111 11111111
0xB00000D8
HSSPI0_CSAEXT
00000000 00000000 00000000 00000000
0xB00000DC
HSSPI0_RDCSDC1
00000000 00000000
HSSPI0_RDCSDC0
00000000 00000000
0xB00000E0
HSSPI0_RDCSDC3
00000000 00000000
HSSPI0_RDCSDC2
00000000 00000000
0xB00000E4
HSSPI0_RDCSDC5
00000000 00000000
HSSPI0_RDCSDC4
00000000 00000000
0xB00000E8
HSSPI0_RDCSDC7
00000000 00000000
HSSPI0_RDCSDC6
00000000 00000000
0xB00000EC
HSSPI0_WRCSDC1
00000000 00000000
HSSPI0_WRCSDC0
00000000 00000000
0xB00000F0
HSSPI0_WRCSDC3
00000000 00000000
HSSPI0_WRCSDC2
00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
111
Data
Shee t
Table 5-1 Memory layout of HSSPI0 registers (4 / 4)
Offset
+2
+1
+0
0xB00000F4
HSSPI0_WRCSDC5
00000000 00000000
HSSPI0_WRCSDC4
00000000 00000000
0xB00000F8
HSSPI0_WRCSDC7
00000000 00000000
HSSPI0_WRCSDC6
00000000 00000000
0xB00000FC
HSSPI0_MID
00000000 00000000 00000000 00000001
0xB0000100B0077FFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0078000
112
+3
read0
00000000 00000000
RICFG8_HSSPI0MSTART
00000000 00000000
0xB0078004B007FC00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB007FC04
BSU8_BTST
00000000 00000000 00000000 00000000
0xB007FC08B007FC0C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB007FC10
BSU8_PEN0
00000000 00000000 00000000 00000000
0xB007FC14B007FFFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-2 Memory layout of the MEMORY_CONFIG registers (1 / 25)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400000
IRQ0_NMIST
00000000 00000000 00001111 00100000
IRQ0_NMIVAS
00000000 00000000 00000000 00000000
0xB0400008
IRQ0_IRQST
00000000 00011111 00000010 00000000
IRQ0_IRQVAS
00000000 00000000 00000000 00000000
0xB0400010
IRQ0_NMIVA1
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_NMIVA0
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400018
IRQ0_NMIVA3
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_NMIVA2
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400020
IRQ0_NMIVA5
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_NMIVA4
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400028
IRQ0_NMIVA7
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400030
IRQ0_NMIVA9
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_NMIVA8
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400038
IRQ0_NMIVA11
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400040
IRQ0_NMIVA13
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_NMIVA12
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400048
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_NMIVA14
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400050
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400058
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_NMIVA18
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400060
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400068
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400070
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400078
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
113
Data
Shee t
Table 5-2 Memory layout of the MEMORY_CONFIG registers (2 / 25)
Offset
114
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400080
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400088
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400090
IRQ0_IRQVA1
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA0
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400098
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04000A0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04000A8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04000B0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04000B8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04000C0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04000C8
IRQ0_IRQVA15
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04000D0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQVA16
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04000D8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04000E0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04000E8
IRQ0_IRQVA23
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA22
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04000F0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04000F8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-2 Memory layout of the MEMORY_CONFIG registers (3 / 25)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400100
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400108
IRQ0_IRQVA31
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA30
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400110
IRQ0_IRQVA33
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA32
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400118
IRQ0_IRQVA35
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA34
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400120
IRQ0_IRQVA37
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA36
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400128
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQVA38
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400130
IRQ0_IRQVA41
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA40
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400138
IRQ0_IRQVA43
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA42
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400140
IRQ0_IRQVA45
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA44
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400148
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400150
IRQ0_IRQVA49
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA48
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400158
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQVA50
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400160
IRQ0_IRQVA53
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA52
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400168
IRQ0_IRQVA55
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400170
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQVA56
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400178
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
115
Data
Shee t
Table 5-2 Memory layout of the MEMORY_CONFIG registers (4 / 25)
Offset
116
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400180
IRQ0_IRQVA61
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400188
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQVA62
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400190
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400198
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04001A0
IRQ0_IRQVA69
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04001A8
IRQ0_IRQVA71
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA70
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04001B0
IRQ0_IRQVA73
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA72
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04001B8
IRQ0_IRQVA75
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA74
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04001C0
IRQ0_IRQVA77
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA76
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04001C8
IRQ0_IRQVA79
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA78
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04001D0
IRQ0_IRQVA81
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA80
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04001D8
IRQ0_IRQVA83
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA82
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04001E0
IRQ0_IRQVA85
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA84
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04001E8
IRQ0_IRQVA87
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA86
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04001F0
IRQ0_IRQVA89
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA88
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04001F8
IRQ0_IRQVA91
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA90
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-2 Memory layout of the MEMORY_CONFIG registers (5 / 25)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400200
IRQ0_IRQVA93
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA92
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400208
IRQ0_IRQVA95
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA94
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400210
IRQ0_IRQVA97
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA96
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400218
IRQ0_IRQVA99
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA98
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400220
IRQ0_IRQVA101
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA100
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400228
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQVA102
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400230
IRQ0_IRQVA105
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA104
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400238
IRQ0_IRQVA107
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA106
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400240
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400248
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400250
IRQ0_IRQVA113
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA112
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400258
IRQ0_IRQVA115
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA114
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400260
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400268
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400270
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400278
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
117
Data
Shee t
Table 5-2 Memory layout of the MEMORY_CONFIG registers (6 / 25)
Offset
118
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400280
IRQ0_IRQVA125
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA124
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400288
IRQ0_IRQVA127
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA126
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400290
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400298
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04002A0
IRQ0_IRQVA133
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA132
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04002A8
IRQ0_IRQVA135
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA134
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04002B0
IRQ0_IRQVA137
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA136
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04002B8
IRQ0_IRQVA139
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA138
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04002C0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04002C8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04002D0
IRQ0_IRQVA145
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA144
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04002D8
IRQ0_IRQVA147
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA146
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04002E0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04002E8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04002F0
IRQ0_IRQVA153
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA152
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04002F8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQVA154
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-2 Memory layout of the MEMORY_CONFIG registers (7 / 25)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400300
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400308
IRQ0_IRQVA159
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA158
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400310
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQVA160
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400318
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400320
IRQ0_IRQVA165
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA164
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400328
IRQ0_IRQVA167
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA166
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400330
IRQ0_IRQVA169
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA168
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400338
IRQ0_IRQVA171
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA170
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400340
IRQ0_IRQVA173
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA172
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400348
IRQ0_IRQVA175
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA174
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400350
IRQ0_IRQVA177
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA176
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400358
IRQ0_IRQVA179
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA178
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400360
IRQ0_IRQVA181
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA180
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400368
IRQ0_IRQVA183
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA182
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400370
IRQ0_IRQVA185
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA184
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400378
IRQ0_IRQVA187
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA186
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
January 30, 2015, MB9EF226_DS707-00004-2v1-E
119
Data
Shee t
Table 5-2 Memory layout of the MEMORY_CONFIG registers (8 / 25)
Offset
120
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400380
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400388
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400390
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400398
IRQ0_IRQVA195
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA194
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04003A0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04003A8
IRQ0_IRQVA199
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA198
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04003B0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04003B8
IRQ0_IRQVA203
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA202
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04003C0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04003C8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQVA206
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04003D0
IRQ0_IRQVA209
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA208
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04003D8
IRQ0_IRQVA211
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA210
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04003E0
IRQ0_IRQVA213
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA212
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04003E8
IRQ0_IRQVA215
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA214
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04003F0
IRQ0_IRQVA217
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA216
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB04003F8
IRQ0_IRQVA219
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA218
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-2 Memory layout of the MEMORY_CONFIG registers (9 / 25)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400400
IRQ0_IRQVA221
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA220
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400408
IRQ0_IRQVA223
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA222
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400410
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400418
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400420
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400428
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400430
IRQ0_IRQVA233
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA232
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400438
IRQ0_IRQVA235
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA234
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400440
IRQ0_IRQVA237
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA236
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400448
IRQ0_IRQVA239
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
IRQ0_IRQVA238
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX00
0xB0400450 0xB0400888
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400890
IRQ0_NMIPL1
00001111 00000000 00001111 00001111
IRQ0_NMIPL0
00001111 00001111 00001111 00000000
0xB0400898
IRQ0_NMIPL3
00000000 00001111 00001111 00001111
IRQ0_NMIPL2
00001111 00000000 00001111 00001111
0xB04008A0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_NMIPL4
00000000 00001111 00000000 00000000
0xB04008A8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04008B0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQPL0
00000000 00000000 00011111 00011111
January 30, 2015, MB9EF226_DS707-00004-2v1-E
121
Data
Shee t
Table 5-2 Memory layout of the MEMORY_CONFIG registers (10 / 25)
Offset
122
+7
+6
+5
+4
+3
+2
+1
+0
0xB04008B8
IRQ0_IRQPL3
00011111 00000000 00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04008C0
IRQ0_IRQPL5
00011111 00011111 00000000 00000000
IRQ0_IRQPL4
00000000 00000000 00000000 00011111
0xB04008C8
IRQ0_IRQPL7
00011111 00011111 00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04008D0
IRQ0_IRQPL9
00000000 00011111 00011111 00011111
IRQ0_IRQPL8
00011111 00011111 00011111 00011111
0xB04008D8
IRQ0_IRQPL11
00000000 00000000 00011111 00011111
IRQ0_IRQPL10
00011111 00011111 00011111 00011111
0xB04008E0
IRQ0_IRQPL13
00011111 00000000 00011111 00011111
IRQ0_IRQPL12
00000000 00011111 00011111 00011111
0xB04008E8
IRQ0_IRQPL15
00000000 00011111 00011111 00000000
IRQ0_IRQPL14
00000000 00000000 00000000 00011111
0xB04008F0
IRQ0_IRQPL17
00011111 00011111 00011111 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB04008F8
IRQ0_IRQPL19
00011111 00011111 00011111 00011111
IRQ0_IRQPL18
00011111 00011111 00011111 00011111
0xB0400900
IRQ0_IRQPL21
00011111 00011111 00011111 00011111
IRQ0_IRQPL20
00011111 00011111 00011111 00011111
0xB0400908
IRQ0_IRQPL23
00011111 00011111 00011111 00011111
IRQ0_IRQPL22
00011111 00011111 00011111 00011111
0xB0400910
IRQ0_IRQPL25
00000000 00011111 00011111 00011111
IRQ0_IRQPL24
00011111 00011111 00011111 00011111
0xB0400918
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQPL26
00011111 00011111 00011111 00011111
0xB0400920
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQPL28
00011111 00011111 00011111 00011111
0xB0400928
IRQ0_IRQPL31
00011111 00011111 00011111 00011111
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400930
IRQ0_IRQPL33
00011111 00011111 00011111 00011111
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-2 Memory layout of the MEMORY_CONFIG registers (11 / 25)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400938
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQPL34
00011111 00011111 00011111 00011111
0xB0400940
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQPL36
00011111 00011111 00011111 00011111
0xB0400948
IRQ0_IRQPL39
00011111 00011111 00000000 00000000
IRQ0_IRQPL38
00000000 00011111 00011111 00011111
0xB0400950
IRQ0_IRQPL41
00011111 00011111 00011111 00011111
IRQ0_IRQPL40
00000000 00000000 00000000 00011111
0xB0400958
IRQ0_IRQPL43
00011111 00011111 00011111 00011111
IRQ0_IRQPL42
00011111 00011111 00011111 00011111
0xB0400960
IRQ0_IRQPL45
00011111 00011111 00011111 00011111
IRQ0_IRQPL44
00011111 00011111 00011111 00011111
0xB0400968
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IRQ0_IRQPL46
00011111 00011111 00011111 00011111
0xB0400970
IRQ0_IRQPL49
00011111 00011111 00000000 00000000
IRQ0_IRQPL48
00011111 00011111 00000000 00000000
0xB0400978
IRQ0_IRQPL51
00000000 00011111 00000000 00000000
IRQ0_IRQPL50
00011111 00011111 00000000 00000000
0xB0400980
IRQ0_IRQPL53
00011111 00011111 00011111 00011111
IRQ0_IRQPL52
00011111 00011111 00011111 00011111
0xB0400988
IRQ0_IRQPL55
00011111 00011111 00011111 00011111
IRQ0_IRQPL54
00011111 00011111 00011111 00011111
0xB0400990
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400998
IRQ0_IRQPL59
00011111 00011111 00011111 00011111
IRQ0_IRQPL58
00011111 00011111 00011111 00011111
0xB04009A0 0xB0400AA8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400AB0
IRQ0_NMIR
00000000 00000000 00000000 00000000
IRQ0_NMIS
00000000 00000000 00000000 00000000
0xB0400AB8
read0
00000000 00000000 00000000 00000000
IRQ0_NMISIS
00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
123
Data
Shee t
Table 5-2 Memory layout of the MEMORY_CONFIG registers (12 / 25)
Offset
124
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400AC0
IRQ0_IRQS1
00000000 00000000 00000000 00000000
IRQ0_IRQS0
00000000 00000000 00000000 00000000
0xB0400AC8
IRQ0_IRQS3
00000000 00000000 00000000 00000000
IRQ0_IRQS2
00000000 00000000 00000000 00000000
0xB0400AD0
IRQ0_IRQS5
00000000 00000000 00000000 00000000
IRQ0_IRQS4
00000000 00000000 00000000 00000000
0xB0400AD8
IRQ0_IRQS7
00000000 00000000 00000000 00000000
IRQ0_IRQS6
00000000 00000000 00000000 00000000
0xB0400AE0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400AE8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400AF0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400AF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400B00
IRQ0_IRQR1
00000000 00000000 00000000 00000000
IRQ0_IRQR0
00000000 00000000 00000000 00000000
0xB0400B08
IRQ0_IRQR3
00000000 00000000 00000000 00000000
IRQ0_IRQR2
00000000 00000000 00000000 00000000
0xB0400B10
IRQ0_IRQR5
00000000 00000000 00000000 00000000
IRQ0_IRQR4
00000000 00000000 00000000 00000000
0xB0400B18
IRQ0_IRQR7
00000000 00000000 00000000 00000000
IRQ0_IRQR6
00000000 00000000 00000000 00000000
0xB0400B20
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400B28
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400B30
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400B38
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-2 Memory layout of the MEMORY_CONFIG registers (13 / 25)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400B40
IRQ0_IRQSIS1
00000000 00000000 00000000 00000000
IRQ0_IRQSIS0
00000000 00000000 00000000 00000000
0xB0400B48
IRQ0_IRQSIS3
00000000 00000000 00000000 00000000
IRQ0_IRQSIS2
00000000 00000000 00000000 00000000
0xB0400B50
IRQ0_IRQSIS5
00000000 00000000 00000000 00000000
IRQ0_IRQSIS4
00000000 00000000 00000000 00000000
0xB0400B58
IRQ0_IRQSIS7
00000000 00000000 00000000 00000000
IRQ0_IRQSIS6
00000000 00000000 00000000 00000000
0xB0400B60
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400B68
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400B70
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400B78
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400B80
IRQ0_IRQCES1
00000000 00000000 00000000 00000000
IRQ0_IRQCES0
00000000 00000000 00000000 00000000
0xB0400B88
IRQ0_IRQCES3
00000000 00000000 00000000 00000000
IRQ0_IRQCES2
00000000 00000000 00000000 00000000
0xB0400B90
IRQ0_IRQCES5
00000000 00000000 00000000 00000000
IRQ0_IRQCES4
00000000 00000000 00000000 00000000
0xB0400B98
IRQ0_IRQCES7
00000000 00000000 00000000 00000000
IRQ0_IRQCES6
00000000 00000000 00000000 00000000
0xB0400BA0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400BA8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400BB0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400BB8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
125
Data
Shee t
Table 5-2 Memory layout of the MEMORY_CONFIG registers (14 / 25)
Offset
126
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400BC0
IRQ0_IRQCEC1
00000000 00000000 00000000 00000000
IRQ0_IRQCEC0
00000000 00000000 00000000 00000000
0xB0400BC8
IRQ0_IRQCEC3
00000000 00000000 00000000 00000000
IRQ0_IRQCEC2
00000000 00000000 00000000 00000000
0xB0400BD0
IRQ0_IRQCEC5
00000000 00000000 00000000 00000000
IRQ0_IRQCEC4
00000000 00000000 00000000 00000000
0xB0400BD8
IRQ0_IRQCEC7
00000000 00000000 00000000 00000000
IRQ0_IRQCEC6
00000000 00000000 00000000 00000000
0xB0400BE0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400BE8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400BF0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400BF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400C00
IRQ0_IRQCE1
00000000 00000000 00000000 00000000
IRQ0_IRQCE0
00000000 00000000 00000000 00000000
0xB0400C08
IRQ0_IRQCE3
00000000 00000000 00000000 00000000
IRQ0_IRQCE2
00000000 00000000 00000000 00000000
0xB0400C10
IRQ0_IRQCE5
00000000 00000000 00000000 00000000
IRQ0_IRQCE4
00000000 00000000 00000000 00000000
0xB0400C18
IRQ0_IRQCE7
00000000 00000000 00000000 00000000
IRQ0_IRQCE6
00000000 00000000 00000000 00000000
0xB0400C20
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400C28
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400C30
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400C38
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-2 Memory layout of the MEMORY_CONFIG registers (15 / 25)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400C40
IRQ0_NMIHS
00000000 00000000 00000000 00000000
IRQ0_NMIHC
00000000 00000000 00000000 00000000
0xB0400C48
read0
00000000 00000000 00000000 00000000
IRQ0_IRQHC
00000000 00000000 00000000 00000000
0xB0400C50
IRQ0_IRQHS1
00000000 00000000 00000000 00000000
IRQ0_IRQHS0
00000000 00000000 00000000 00000000
0xB0400C58
IRQ0_IRQHS3
00000000 00000000 00000000 00000000
IRQ0_IRQHS2
00000000 00000000 00000000 00000000
0xB0400C60
IRQ0_IRQHS5
00000000 00000000 00000000 00000000
IRQ0_IRQHS4
00000000 00000000 00000000 00000000
0xB0400C68
IRQ0_IRQHS7
00000000 00000000 00000000 00000000
IRQ0_IRQHS6
00000000 00000000 00000000 00000000
0xB0400C70
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400C78
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400C80
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400C88
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400C90
read0
00000000 00000000 00000000 00000000
IRQ0_IRQPLM
00000000 00000000 00000000 00100000
0xB0400C98
read0
00000000 00000000 00000000 00000000
IRQ0_CSR
00000000 00000001 00000000 00000000
0xB0400CA0
read0
00000000 00000000 00000000 00000000
IRQ0_NESTL
00000000 00000000 00000000 00000000
0xB0400CA8
IRQ0_NMIPS
00000000 00000000 00000000 00000000
IRQ0_NMIRS
00000000 00000000 00000000 00000000
0xB0400CB0
IRQ0_IRQRS1
00000000 00000000 00000000 00000000
IRQ0_IRQRS0
00000000 00000000 00000000 00000000
0xB0400CB8
IRQ0_IRQRS3
00000000 00000000 00000000 00000000
IRQ0_IRQRS2
00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
127
Data
Shee t
Table 5-2 Memory layout of the MEMORY_CONFIG registers (16 / 25)
Offset
128
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400CC0
IRQ0_IRQRS5
00000000 00000000 00000000 00000000
IRQ0_IRQRS4
00000000 00000000 00000000 00000000
0xB0400CC8
IRQ0_IRQRS7
00000000 00000000 00000000 00000000
IRQ0_IRQRS6
00000000 00000000 00000000 00000000
0xB0400CD0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
read0
00000000 00000000 00000000 00000000
0xB0400CD8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400CE0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400CE8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400CF0
IRQ0_IRQPS1
00000000 00000000 00000000 00000000
IRQ0_IRQPS0
00000000 00000000 00000000 00000000
0xB0400CF8
IRQ0_IRQPS3
00000000 00000000 00000000 00000000
IRQ0_IRQPS2
00000000 00000000 00000000 00000000
0xB0400D00
IRQ0_IRQPS5
00000000 00000000 00000000 00000000
IRQ0_IRQPS4
00000000 00000000 00000000 00000000
0xB0400D08
IRQ0_IRQPS7
00000000 00000000 00000000 00000000
IRQ0_IRQPS6
00000000 00000000 00000000 00000000
0xB0400D10
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
read0
00000000 00000000 00000000 00000000
0xB0400D18
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400D20
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400D28
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0400D30
read0
00000000 00000000 00000000 00000000
IRQ0_UNLOCK
00000000 00000000 00000000 00000000
0xB0400D38
read0
00000000 00000000 00000000 00000000
IRQ0_MID
00000000 00000000 00000000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-2 Memory layout of the MEMORY_CONFIG registers (17 / 25)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0400D40
IRQ0_EAN
00000000 00000000 00000000 00000000
IRQ0_EEI
00000000 00000000 00000000 00000000
0xB0400D48
IRQ0_EEB0
00000000 00000000 00000000 00000000
IRQ0_ET
00000000 00000000 00000000 00000000
0xB0400D50
IRQ0_EEB2
00000000 00000000 00000000 00000000
IRQ0_EEB1
00000000 00000000 00000000 00000000
0xB0400D58B0407FF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0408000
TPU0_LST
00000000 00000000 00000000 00000001
TPU0_UNLOCK
00000000 00000000 00000000 00000000
0xB0408008
TPU0_TIR
00000000 00000000 00000000 00000000
TPU0_CFG
00000000 00000000 00000000 00000000
0xB0408010
TPU0_TIE
00000000 00000000 00000000 00000000
TPU0_TST
00000000 00000000 00000000 00000000
0xB0408018
read0
00000000 00000000 00000000 00000000
TPU0_MID
00000000 00000000 00000000 00000000
0xB0408020B0408028
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0408030
TPU0_TCN01
00000000 00000000 00000000 00000000
TPU0_TCN00
00000000 00000000 00000000 00000000
0xB0408038
TPU0_TCN03
00000000 00000000 00000000 00000000
TPU0_TCN02
00000000 00000000 00000000 00000000
0xB0408040
TPU0_TCN05
00000000 00000000 00000000 00000000
TPU0_TCN04
00000000 00000000 00000000 00000000
0xB0408048
TPU0_TCN07
00000000 00000000 00000000 00000000
TPU0_TCN06
00000000 00000000 00000000 00000000
0xB0408050
TPU0_TCN11
00000000 00000000 00000000 00000000
TPU0_TCN10
00000000 00000000 00000000 00000000
0xB0408058
TPU0_TCN13
00000000 00000000 00000000 00000000
TPU0_TCN12
00000000 00000000 00000000 00000000
0xB0408060
TPU0_TCN15
00000000 00000000 00000000 00000000
TPU0_TCN14
00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
129
Data
Shee t
Table 5-2 Memory layout of the MEMORY_CONFIG registers (18 / 25)
Offset
+6
+5
+4
+3
+2
+1
+0
0xB0408068
TPU0_TCN17
00000000 00000000 00000000 00000000
TPU0_TCN16
00000000 00000000 00000000 00000000
0xB0408070
TPU0_TCC1
00000000 00000000 00000000 00000000
TPU0_TCC0
00000000 00000000 00000000 00000000
0xB0408078
TPU0_TCC3
00000000 00000000 00000000 00000000
TPU0_TCC2
00000000 00000000 00000000 00000000
0xB0408080
TPU0_TCC5
00000000 00000000 00000000 00000000
TPU0_TCC4
00000000 00000000 00000000 00000000
0xB0408088
TPU0_TCC7
00000000 00000000 00000000 00000000
TPU0_TCC6
00000000 00000000 00000000 00000000
0xB0408090B040FFF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0410000
TRCFG_TCMCFG1
00000000 00000000 00000000 00000000
TRCFG_TCMCFG0
00000011 00000000 00000001 00000000
0xB0410008
read0
00000000 00000000 00000000 00000000
TRCFG_TCMUNLOCK
00000000 00000000 00000000 00000000
0xB0410010B0410FF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0411000
reserved
00000000 00000000 00000000 00000000
TCFCFG_FCPROTKEY
00000000 00000000 00000000 00000000
0xB0411008
reserved
00000000 00000000 00000000 00000000
TCFCFG_FCFGR
00000000 00000000 00000000 00000001
0xB0411010
reserved
00000000 00000000 00000000 00000000
TCFCFG_FECCCTRL
00000000 00000000 00000000 00000000
0xB0411018
TCFCFG_FECCEIR
00000000 00000000 00000000 00000000
TCFCFG_FDATEIR
00000000 00000000 00000000 00000000
0xB0411020
TCFCFG_FICTRL1
00000000 00000000 00000000 00000000
TCFCFG_FICTRL0
00000000 00000000 00000000 00000000
0xB0411028
TCFCFG_FICTRL3
00000000 00000000 00000000 00000000
TCFCFG_FICTRL2
00000000 00000000 00000000 00000000
0xB0411030
130
+7
reserved
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-2 Memory layout of the MEMORY_CONFIG registers (19 / 25)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0411038
TCFCFG_FSTAT1
00000000 00000000 00000000 00000000
TCFCFG_FSTAT0
00000000 00000000 00000000 00000000
0xB0411040
TCFCFG_FSTAT3
00000000 00000000 00000000 00000000
TCFCFG_FSTAT2
00000000 00000000 00000000 00000000
0xB0411048
reserved
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0411050
TCFCFG_FECCEAR
00000000 00000000 00000000 00000000
TCFCFG_FSECIR
00000000 00000000 00000000 00000000
0xB0411058
reserved
00000000 00000000 00000000 00000000
TCFCFG_FMIDR
00000000 00000000 00000000 00000000
0xB0411060
TCFCFG_FCAMHR0
00000000 00000000 000XXXXX XXXXXXXX
TCFCFG_FCAMLR0
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0411068
TCFCFG_FCAMHR1
00000000 00000000 000XXXXX XXXXXXXX
TCFCFG_FCAMLR1
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0411070
TCFCFG_FCAMHR2
00000000 00000000 000XXXXX XXXXXXXX
TCFCFG_FCAMLR2
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0411078
TCFCFG_FCAMHR3
00000000 00000000 000XXXXX XXXXXXXX
TCFCFG_FCAMLR3
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0411080B0411FF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0412000
reserved
00000000 00000000 00000000 00000000
EEFCFG_CPR
00000000 00000000 00000000 00000000
0xB0412008
EEFCFG_ECR
00000000 00000000 00000000 00000000
EEFCFG_CR
00000000 00000000 00000000 00000010
0xB0412010
EEFCFG_WSR
00000000 00000000 00000000 00000000
EEFCFG_WCR
00000000 00000000 00000000 00000000
0xB0412018
EEFCFG_EEIR
00000000 00000000 00000000 00000000
EEFCFG_DBEIR
00000000 00000000 00000000 00000000
0xB0412020
EEFCFG_ICR
00000000 00000000 00000000 00000000
reserved
00000000 00000000 00000000 00000000
0xB0412028
EEFCFG_SECIR
00000000 00000000 00000000 00000000
EEFCFG_SR
00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
131
Data
Shee t
Table 5-2 Memory layout of the MEMORY_CONFIG registers (20 / 25)
Offset
+6
+5
+4
+3
+2
+1
+0
0xB0412030
EEFCFG_MIR
00000000 00000000 00000000 00000000
EEFCFG_EEAR
00000000 00000000 00000000 00000000
0xB0412038
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EEFCFG_EMENR
00000000 00000000 00000000 00000000
0xB0412040
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0412048
EEFCFG_FCAMHR
00000000 00000000 000XXXXX XXXXXXXX
EEFCFG_FCAMLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0412050
EEFCFG_SEQCM
00000000 00000000 00000000 00000000
EEFCFG_SEQWM
00000000 00000000 00000000 00000000
0xB0412058
EEFCFG_ARBCLR
00000000 00000000 00000000 00000000
EEFCFG_ARBERR
00000000 00000000 00000000 00000000
0xB0412060
EEFCFG_BERRCLR
00000000 00000000 00000000 00000000
EEFCFG_BERR
00000000 00000000 00000000 00000000
0xB0412068
read0
00000000 00000000 00000000 00000000
EEFCFG_BLANK
00000000 00000000 00000000 00000000
0xB0412070B0412FF8
132
+7
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0413000
SHE_CMDCANCEL
00000000 00000000 00000000 00000000
SHE_CMD
00000000 00000000 00000000 00000000
0xB0413008
SHE_STATUS
XXXX0000 00000000 00000000 00000000
SHE_CLKCTRL
00000000 00000000 00000000 00000000
0xB0413010
SHE_CLKSTAT
00000000 00000000 00000000 00000000
SHE_ERC
00000000 00010000 00000000 00000000
0xB0413018
SHE_IRQ
00000000 00000000 00000000 00000000
SHE_MID
00000000 00000000 00000000 00000000
0xB0413020
SHE_IRQCLR
00000000 00000000 00000000 00000000
SHE_IRQEN
00000000 00000000 00000000 00000000
0xB0413028
SHE_OMSTADDR
00000000 00000000 00000000 00000000
SHE_IMSTADDR
00000000 00000000 00000000 00000000
0xB0413030
SHE_OMSTCNT
00000000 00000000 00000000 00000000
SHE_IMSTCNT
00000000 00000000 00000000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-2 Memory layout of the MEMORY_CONFIG registers (21 / 25)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB0413038
SHE_OMSTSTART
00000000 00000000 00000000 00000000
SHE_IMSTSTART
00000000 00000000 00000000 00000000
0xB0413040
SHE_OFIFOCFG
00000000 00000001 00000000 00000000
SHE_IFIFOCFG
00000000 00000001 00000000 00000000
0xB0413048
SHE_COMPARE1
00000111 11111111 11111111 11111111
SHE_COMPARE0
11111111 11111111 11111111 11111111
0xB0413050
SHE_MSTSTATUS
00000000 00000001 00000000 00000001
SHE_COMPACC
00000000 00000000 00000000 00000000
0xB0413058
SHE_OMSTERRADDR
00000000 00000000 00000000 00000000
SHE_IMSTERRADDR
00000000 00000000 00000000 00000000
0xB0413060
SHE_FIFOLOAD
00000000 00110000 00000000 00110000
SHE_FIFOSTATUS
00000000 00000000 00000000 00000000
0xB0413068
SHE_DATACNT1
00000000 00000000 00000000 00000000
SHE_DATACNT0
00000000 00000000 00000000 00000000
0xB0413070 0xB04130F8
read0
00000000 00000000 00000000 00000000
reserved
00000000 00000000 00000000 00000000
0xB0413100
SHE_IFIFOWRDATA1
00000000 00000000 00000000 00000000
SHE_IFIFOWRDATA0
00000000 00000000 00000000 00000000
0xB0413108
SHE_IFIFOWRDATA3
00000000 00000000 00000000 00000000
SHE_IFIFOWRDATA2
00000000 00000000 00000000 00000000
0xB0413110
SHE_IFIFOWRDATA5
00000000 00000000 00000000 00000000
SHE_IFIFOWRDATA4
00000000 00000000 00000000 00000000
0xB0413118
SHE_IFIFOWRDATA7
00000000 00000000 00000000 00000000
SHE_IFIFOWRDATA6
00000000 00000000 00000000 00000000
0xB0413120
SHE_IFIFOWRDATA9
00000000 00000000 00000000 00000000
SHE_IFIFOWRDATA8
00000000 00000000 00000000 00000000
0xB0413128
SHE_IFIFOWRDATA11
00000000 00000000 00000000 00000000
SHE_IFIFOWRDATA10
00000000 00000000 00000000 00000000
0xB0413130
SHE_IFIFOWRDATA13
00000000 00000000 00000000 00000000
SHE_IFIFOWRDATA12
00000000 00000000 00000000 00000000
0xB0413138
SHE_IFIFOWRDATA15
00000000 00000000 00000000 00000000
SHE_IFIFOWRDATA14
00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
133
Data
Shee t
Table 5-2 Memory layout of the MEMORY_CONFIG registers (22 / 25)
Offset
134
+7
+6
+5
+4
+3
+2
+1
+0
0xB0413140
SHE_IFIFOWRDATA17
00000000 00000000 00000000 00000000
SHE_IFIFOWRDATA16
00000000 00000000 00000000 00000000
0xB0413148
SHE_IFIFOWRDATA19
00000000 00000000 00000000 00000000
SHE_IFIFOWRDATA18
00000000 00000000 00000000 00000000
0xB0413150
SHE_IFIFOWRDATA21
00000000 00000000 00000000 00000000
SHE_IFIFOWRDATA20
00000000 00000000 00000000 00000000
0xB0413158
SHE_IFIFOWRDATA23
00000000 00000000 00000000 00000000
SHE_IFIFOWRDATA22
00000000 00000000 00000000 00000000
0xB0413160
SHE_IFIFOWRDATA25
00000000 00000000 00000000 00000000
SHE_IFIFOWRDATA24
00000000 00000000 00000000 00000000
0xB0413168
SHE_IFIFOWRDATA27
00000000 00000000 00000000 00000000
SHE_IFIFOWRDATA26
00000000 00000000 00000000 00000000
0xB0413170
SHE_IFIFOWRDATA29
00000000 00000000 00000000 00000000
SHE_IFIFOWRDATA28
00000000 00000000 00000000 00000000
0xB0413178
SHE_IFIFOWRDATA31
00000000 00000000 00000000 00000000
SHE_IFIFOWRDATA30
00000000 00000000 00000000 00000000
0xB0413180
SHE_OFIFORDDATA1
00000000 00000000 00000000 00000000
SHE_OFIFORDDATA0
00000000 00000000 00000000 00000000
0xB0413188
SHE_OFIFORDDATA3
00000000 00000000 00000000 00000000
SHE_OFIFORDDATA2
00000000 00000000 00000000 00000000
0xB0413190
SHE_OFIFORDDATA5
00000000 00000000 00000000 00000000
SHE_OFIFORDDATA4
00000000 00000000 00000000 00000000
0xB0413198
SHE_OFIFORDDATA7
00000000 00000000 00000000 00000000
SHE_OFIFORDDATA6
00000000 00000000 00000000 00000000
0xB04131A0
SHE_OFIFORDDATA9
00000000 00000000 00000000 00000000
SHE_OFIFORDDATA8
00000000 00000000 00000000 00000000
0xB04131A8
SHE_OFIFORDDATA11
00000000 00000000 00000000 00000000
SHE_OFIFORDDATA10
00000000 00000000 00000000 00000000
0xB04131B0
SHE_OFIFORDDATA13
00000000 00000000 00000000 00000000
SHE_OFIFORDDATA12
00000000 00000000 00000000 00000000
0xB04131B8
SHE_OFIFORDDATA15
00000000 00000000 00000000 00000000
SHE_OFIFORDDATA14
00000000 00000000 00000000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-2 Memory layout of the MEMORY_CONFIG registers (23 / 25)
Offset
+7
+6
+5
+4
+3
+2
+1
+0
0xB04131C0
SHE_OFIFORDDATA17
00000000 00000000 00000000 00000000
SHE_OFIFORDDATA16
00000000 00000000 00000000 00000000
0xB04131C8
SHE_OFIFORDDATA19
00000000 00000000 00000000 00000000
SHE_OFIFORDDATA18
00000000 00000000 00000000 00000000
0xB04131D0
SHE_OFIFORDDATA21
00000000 00000000 00000000 00000000
SHE_OFIFORDDATA20
00000000 00000000 00000000 00000000
0xB04131D8
SHE_OFIFORDDATA23
00000000 00000000 00000000 00000000
SHE_OFIFORDDATA22
00000000 00000000 00000000 00000000
0xB04131E0
SHE_OFIFORDDATA25
00000000 00000000 00000000 00000000
SHE_OFIFORDDATA24
00000000 00000000 00000000 00000000
0xB04131E8
SHE_OFIFORDDATA27
00000000 00000000 00000000 00000000
SHE_OFIFORDDATA26
00000000 00000000 00000000 00000000
0xB04131F0
SHE_OFIFORDDATA29
00000000 00000000 00000000 00000000
SHE_OFIFORDDATA28
00000000 00000000 00000000 00000000
0xB04131F8
SHE_OFIFORDDATA31
00000000 00000000 00000000 00000000
SHE_OFIFORDDATA30
00000000 00000000 00000000 00000000
0xB0413200B0413FF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0414000
MPUXSHE0_NMIEN
00000000 00000000 00000000 00000001
MPUXSHE0_CTRL0
00000000 00000000 00000001 00000000
0xB0414008
MPUXSHE0_WERRA
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MPUXSHE0_WERRC
00000000 00000000 00000XXX XXXXXXX0
0xB0414010
MPUXSHE0_RERRA
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MPUXSHE0_RERRC
00000000 00000000 00000XXX XXXXXXX0
0xB0414018
MPUXSHE0_SADDR1
00000000 00000000 00000000 00000000
MPUXSHE0_CTRL1
00000000 00000000 00000000 00000000
0xB0414020
MPUXSHE0_CTRL2
00000000 00000000 00000000 00000000
MPUXSHE0_EADDR1
00000000 00000000 00000000 01111111
0xB0414028
MPUXSHE0_EADDR2
00000000 00000000 00000000 01111111
MPUXSHE0_SADDR2
00000000 00000000 00000000 00000000
0xB0414030
MPUXSHE0_SADDR3
00000000 00000000 00000000 00000000
MPUXSHE0_CTRL3
00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
135
Data
Shee t
Table 5-2 Memory layout of the MEMORY_CONFIG registers (24 / 25)
Offset
+6
+5
+4
+3
+2
+1
+0
0xB0414038
MPUXSHE0_CTRL4
00000000 00000000 00000000 00000000
MPUXSHE0_EADDR3
00000000 00000000 00000000 01111111
0xB0414040
MPUXSHE0_EADDR4
00000000 00000000 00000000 01111111
MPUXSHE0_SADDR4
00000000 00000000 00000000 00000000
0xB0414048
MPUXSHE0_SADDR5
00000000 00000000 00000000 00000000
MPUXSHE0_CTRL5
00000000 00000000 00000000 00000000
0xB0414050
MPUXSHE0_CTRL6
00000000 00000000 00000000 00000000
MPUXSHE0_EADDR5
00000000 00000000 00000000 01111111
0xB0414058
MPUXSHE0_EADDR6
00000000 00000000 00000000 01111111
MPUXSHE0_SADDR6
00000000 00000000 00000000 00000000
0xB0414060
MPUXSHE0_SADDR7
00000000 00000000 00000000 00000000
MPUXSHE0_CTRL7
00000000 00000000 00000000 00000000
0xB0414068
MPUXSHE0_CTRL8
00000000 00000000 00000000 00000000
MPUXSHE0_EADDR7
00000000 00000000 00000000 01111111
0xB0414070
MPUXSHE0_EADDR8
00000000 00000000 00000000 01111111
MPUXSHE0_SADDR8
00000000 00000000 00000000 00000000
0xB0414078
MPUXSHE0_MID
00000000 00000000 00000000 00000000
MPUXSHE0_UNLOCK
00000000 00000000 00000000 00000000
0xB0414080B0417FF8
0xB0418000
0xB0418008B0418010
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSU6_BTST
00000000 00000000 00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0418018
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSU6_PEN2
00000000 00000000 00000001 00000000
0xB0418020
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSU6_PEN4
00000000 00000000 00000000 00000001
0xB0418028B0418038
0xB0418040
136
+7
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSU6_PEN12
00000000 00000000 00000000 00000001
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-2 Memory layout of the MEMORY_CONFIG registers (25 / 25)
Offset
0xB0418048B0418058
0xB0418060
0xB0418068B04FFFF8
+7
+6
+5
+4
+3
+2
+1
+0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSU6_PEN20
00000000 00000000 00000000 00000001
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
137
Data
Shee t
Table 5-3 Memory layout of the DEBUG_BUS registers (1 / 2)
Offset
138
+3
+2
+1
0xB0500000B050DFFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB050E000
MCFG_DTAR
000XXX0X 000000XX 00000000 00000000
0xB050E004
MCFG_TSR
00000000 00000000 00000000 00111011
0xB050E008B050F11C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB050F120
SCCFG_TCFPUSRKEY0
00000000 00000000 00000000 00000000
0xB050F124
SCCFG_TCFPUSRKEY1
00000000 00000000 00000000 00000000
0xB050F128
SCCFG_TCFPUSRKEY2
00000000 00000000 00000000 00000000
0xB050F12C
SCCFG_TCFPUSRKEY3
00000000 00000000 00000000 00000000
0xB050F130
SCCFG_EEFPUSRKEY0
00000000 00000000 00000000 00000000
0xB050F134
SCCFG_EEFPUSRKEY1
00000000 00000000 00000000 00000000
0xB050F138
SCCFG_EEFPUSRKEY2
00000000 00000000 00000000 00000000
0xB050F13C
SCCFG_EEFPUSRKEY3
00000000 00000000 00000000 00000000
0xB050F140B050F16C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB050F170
SCCFG_CTRL
00000000 00000000 00000000 00000000
0xB050F174
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB050F178
SCCFG_STAT0
00000000 00000000 00000000 00000000
0xB050F17C
SCCFG_STAT1
00000001 0000000X 00000000 00111111
0xB050F180
SCCFG_STAT2
00000000 00000000 00000000 00000101
0xB050F184B050F18C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB050F190
SCCFG_SECKEY0
00000000 00000000 00000000 00000000
0xB050F194
SCCFG_SECKEY1
00000000 00000000 00000000 00000000
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-3 Memory layout of the DEBUG_BUS registers (2 / 2)
Offset
+3
+2
+1
0xB050F198
SCCFG_SECKEY2
00000000 00000000 00000000 00000000
0xB050F19C
SCCFG_SECKEY3
00000000 00000000 00000000 00000000
0xB050F1A0
SCCFG_MODID
00000000 00000000 00000000 00000000
0xB050F1A4
SCCFG_UNLCK
00000000 00000000 00000000 00000000
0xB050F1A8
SCCFG_GPREG0
00000000 00000000 00000000 00000000
0xB050F1AC
SCCFG_GPREG1
00000000 00000000 00000000 00000000
0xB050F1B0B05FFFFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
139
Data
Shee t
Table 5-4 Memory layout of the MCU_CONFIG registers (1 / 11)
Offset
+2
+1
+0
0xB0600000
SYSC_PROTKEYR
00000000 00000000 00000000 00000000
0xB0600004B060007C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600080
SYSC_RUNCKSRER
00000000 00001110
SYSC_RUNPDCFGR
00000000 00001111
0xB0600084
SYSC_RUNCKSELR
00100011 00000000 00000000 00000000
0xB0600088
SYSC_RUNCKER
01110001 00111111 00001101 11110001
0xB060008C
SYSC_RUNCKDIVR0
00000000 00000000 00000000 00000000
0xB0600090
SYSC_RUNCKDIVR1
00000000 00000000 00000000 00000000
0xB0600094
SYSC_RUNCKDIVR2
00000000 00000000 00000000 00000000
0xB0600098
SYSC_RUNPLLCNTR
00000000 00001101 00000001 00000000
0xB060009C
SYSC_RUNSSCGCNTR0
00000001 00001101 00000001 00000000
0xB06000A0
SYSC_RUNSSCGCNTR1
00000000 00000000 00000000 00101001
0xB06000A4
SYSC_RUNGFXCNTR0
00000001 00001101 00000000 00000000
0xB06000A8
SYSC_RUNGFXCNTR1
00000000 00000000 00000000 00101001
0xB06000AC
SYSC_RUNLVDCFGR
00000000 00001011 00001110 00001111
0xB06000B0
0xB06000B4B06000FC
0xB0600100
140
+3
SYSC_TRGRUNCNTR
00000000 00000000
SYSC_RUNCSVCFGR
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
SYSC_PSSCKSRER
00000000 00001110
SYSC_PSSPDCFGR
00000000 00001111
0xB0600104
SYSC_PSSCKSELR
00100011 00000000 00000000 00000000
0xB0600108
SYSC_PSSCKER
01110001 00111110 00001101 11110001
0xB060010C
SYSC_PSSCKDIVR0
00000000 00000000 00000000 00000000
0xB0600110
SYSC_PSSCKDIVR1
00000000 00000000 00000000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-4 Memory layout of the MCU_CONFIG registers (2 / 11)
Offset
+3
+2
+1
+0
0xB0600114
SYSC_PSSCKDIVR2
00000000 00000000 00000000 00000000
0xB0600118
SYSC_PSSPLLCNTR
00000000 00001101 00000001 00000000
0xB060011C
SYSC_PSSSSCGCNTR0
00000001 00001101 00000001 00000000
0xB0600120
SYSC_PSSSSCGCNTR1
00000000 00000000 00000000 00101001
0xB0600124
SYSC_PSSGFXCNTR0
00000001 00001101 00000000 00000000
0xB0600128
SYSC_PSSGFXCNTR1
00000000 00000000 00000000 00101001
0xB060012C
SYSC_PSSLVDCFGR
00000000 00001011 00001110 00001111
0xB0600130
SYSC_PSSENR
00000000 00000000
0xB0600134B060017C
0xB0600180
SYSC_PSSCSVCFGR
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
SYSC_APPCKSRER
00000000 00001110
SYSC_APPPDCFGR
00000000 00001111
0xB0600184
SYSC_APPCKSELR
00100011 00000000 00000000 00000000
0xB0600188
SYSC_APPCKER
01110001 00111111 00001101 11110001
0xB060018C
SYSC_APPCKDIVR0
00000000 00000000 00000000 00000000
0xB0600190
SYSC_APPCKDIVR1
00000000 00000000 00000000 00000000
0xB0600194
SYSC_APPCKDIVR2
00000000 00000000 00000000 00000000
0xB0600198
SYSC_APPPLLCNTR
00000000 00001101 00000001 00000000
0xB060019C
SYSC_APPSSCGCNTR0
00000001 00001101 00000001 00000000
0xB06001A0
SYSC_APPSSCGCNTR1
00000000 00000000 00000000 00101001
0xB06001A4
SYSC_APPGFXCNTR0
00000001 00001101 00000000 00000000
0xB06001A8
SYSC_APPGFXCNTR1
00000000 00000000 00000000 00101001
0xB06001AC
SYSC_APPLVDCFGR
00000000 00001011 00001110 00001111
January 30, 2015, MB9EF226_DS707-00004-2v1-E
141
Data
Shee t
Table 5-4 Memory layout of the MCU_CONFIG registers (3 / 11)
Offset
0xB06001B0
0xB06001B4B06001FC
0xB0600200
+2
reserved
XXXXXXXX XXXXXXXX
+1
+0
SYSC_APPCSVCFGR
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
SYSC_CKSRESTSR
00000000 00001110
SYSC_PDSTSR
00000000 00001111
0xB0600204
SYSC_CKSELSTSR
00100011 00000000 00000000 00000000
0xB0600208
SYSC_CKESTSR
01110001 00111111 00001101 11110001
0xB060020C
SYSC_CKDIVSTSR0
00000000 00000000 00000000 00000000
0xB0600210
SYSC_CKDIVSTSR1
00000000 00000000 00000000 00000000
0xB0600214
SYSC_CKDIVSTSR2
00000000 00000000 00000000 00000000
0xB0600218
SYSC_PLLSTSR
00000000 00001101 00000001 00000000
0xB060021C
SYSC_SSCGSTSR0
00000001 00001101 00000001 00000000
0xB0600220
SYSC_SSCGSTSR1
00000000 00000000 00000000 00101001
0xB0600224
SYSC_GFXSTSR0
00000001 00001101 00000000 00000000
0xB0600228
SYSC_GFXSTSR1
00000000 00000000 00000000 00101001
0xB060022C
SYSC_LVDCFGSTSR
00000000 00101011 00101110 00101111
0xB0600230
142
+3
reserved
XXXXXXXX XXXXXXXX
SYSC_CSVCFGSTSR
00000000 00000000
0xB0600234B060027C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600280
SYSC_SYSIDR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600284
SYSC_SYSSTSR
00000000 00000000 00000100 00000000
0xB0600288
SYSC_SYSINTER
00000000 00000000 00000000 00000000
0xB060028C
SYSC_SYSICLR
00000000 00000000 00000000 00000000
0xB0600290
SYSC_SYSERRR
00000000 00000000 00000000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-4 Memory layout of the MCU_CONFIG registers (4 / 11)
Offset
+3
+2
+1
0xB0600294
SYSC_SYSERRICLR
00000000 00000000 00000000 00000000
0xB0600298B06002FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600300
SYSC_CSVMOCFGR
00000000 00000000 00000000 00000000
0xB0600304
SYSC_CSVSOCFGR
00000000 00000000 00000000 00000000
0xB0600308
SYSC_CSVMPCFGR
00000000 00000000 00000000 00000000
0xB060030C
SYSC_CSVSPCFGR
00000000 00000000 00000000 00000000
0xB0600310
SYSC_CSVGPCFGR
00000000 00000000 00000000 00000000
0xB0600314
SYSC_CSVTESTR
00000000 00000000 00000000 00000000
0xB0600318B060037C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600380
SYSC_RSTCNTR
00000000 00000000 00000000 00000000
0xB0600384
SYSC_RSTCAUSEUR
00011110 00000000 00000000 00000001
0xB0600388
SYSC_RSTCAUSEBT
X0011110 00000000 00000000 00000001
0xB060038CB06003FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600400
SYSC_SRCSCTTRG
00000000 00000000 00000000 00000000
0xB0600404
SYSC_SRCSCTCNTR
00000000 00000000 00000000 00000000
0xB0600408
SYSC_SRCSCTCPR
00000000 00000110 00000000 00000001
0xB060040C
SYSC_SRCSCTSTATR
00000000 00000000 00000000 00000000
0xB0600410
SYSC_SRCSCTINTER
00000000 00000000 00000000 00000000
0xB0600414
SYSC_SRCSCTICLR
00000000 00000000 00000000 00000000
0xB0600418B060047C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600480
SYSC_RCSCTTRG
00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
143
Data
Shee t
Table 5-4 Memory layout of the MCU_CONFIG registers (5 / 11)
Offset
144
+3
+2
+1
0xB0600484
SYSC_RCSCTCNTR
00000000 00000000 00000000 00000000
0xB0600488
SYSC_RCSCTCPR
00000000 00000110 00000000 00011110
0xB060048C
SYSC_RCSCTSTATR
00000000 00000000 00000000 00000000
0xB0600490
SYSC_RCSCTINTER
00000000 00000000 00000000 00000000
0xB0600494
SYSC_RCSCTICLR
00000000 00000000 00000000 00000000
0xB0600498B06004FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600500
SYSC_MAINSCTTRG
00000000 00000000 00000000 00000000
0xB0600504
SYSC_MAINSCTCNTR
00000000 00000000 00000000 00000000
0xB0600508
SYSC_MAINSCTCPR
00000000 00000110 00010000 00000000
0xB060050C
SYSC_MAINSCTSTATR
00000000 00000000 00000000 00000000
0xB0600510
SYSC_MAINSCTINTER
00000000 00000000 00000000 00000000
0xB0600514
SYSC_MAINSCTICLR
00000000 00000000 00000000 00000000
0xB0600518B060057C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600580
SYSC_SUBSCTTRG
00000000 00000000 00000000 00000000
0xB0600584
SYSC_SUBSCTCNTR
00000000 00000000 00000000 00000000
0xB0600588
SYSC_SUBSCTCPR
00000000 00000110 00000100 00000000
0xB060058C
SYSC_SUBSCTSTATR
00000000 00000000 00000000 00000000
0xB0600590
SYSC_SUBSCTINTER
00000000 00000000 00000000 00000000
0xB0600594
SYSC_SUBSCTICLR
00000000 00000000 00000000 00000000
0xB0600598B06005FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600600
SYSC_CKOTCFGR
00000000 00000000 00000000 00000111
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-4 Memory layout of the MCU_CONFIG registers (6 / 11)
Offset
+3
+2
+1
0xB0600604B060067C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600680
SYSC_SPCCFGR
00000000 000000X0 00000000 00000000
0xB0600684
SYSC_RCCFGR
00000000 00000000 00000001 11111111
0xB0600688
SYSC_TESTR0
00000000 00000000 00000000 00000000
0xB060068C
SYSC_TESTR1
00000000 00000000 00000000 00000000
0xB0600690
SYSC_TESTR2
00000000 00000000 00000000 00000000
0xB0600694B06006FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0600700
SYSC_JTAGDETECT
00000000 00000000 00000000 00000000
0xB0600704
SYSC_JTAGCNFG
00000000 00000000 00000000 00000001
0xB0600708
SYSC_JTAGWAKEUP
00000000 00000000 00000000 00000001
0xB060070CB0607FFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0608000
WDG_PROT
00000000 00000000 00000000 00000000
0xB0608004
reserved
00000000 00000000 00000000 00000000
0xB0608008
WDG_CNT
00000000 00000000 00000000 00000000
0xB060800C
WDG_RSTCAUSE
00000000 00000000 00000000 000XXXXX
0xB0608010
WDG_TRG0
00000000 00000000 00000000 00000000
0xB0608014
reserved
00000000 00000000 00000000 00000000
0xB0608018
WDG_TRG1
00000000 00000000 00000000 00000000
0xB060801C
reserved
00000000 00000000 00000000 00000000
0xB0608020
WDG_INT
00000000 00000000 00000000 00000000
0xB0608024
WDG_INTCLR
00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
145
Data
Shee t
Table 5-4 Memory layout of the MCU_CONFIG registers (7 / 11)
Offset
146
+3
+2
+1
0xB0608028
reserved
00000000 00000000 00000000 00000000
0xB060802C
WDG_TRG0CFG
00000000 00000000 00000000 00000000
0xB0608030
WDG_TRG1CFG
00000000 00000000 00000000 00000000
0xB0608034
WDG_RUNLL
00000000 00000000 00000000 00000000
0xB0608038
WDG_RUNUL
00000001 00000000 00000000 00000000
0xB060803C
WDG_PSSLL
00000000 00000000 00000000 00000000
0xB0608040
WDG_PSSUL
10000000 00000000 00000000 00000000
0xB0608044
WDG_RSTDLY
00000000 00000000 00000000 00000000
0xB0608048
WDG_CFG
00000000 00000000 00000000 00000011
0xB060804CB060FFFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0610000
RRCFG_UNLOCKR
00000000 00000000 00000000 00000000
0xB0610004
RRCFG_CSR
00001111 00000000 00000010 00000000
0xB0610008
RRCFG_EAN
00000000 00000000 00000000 00000000
0xB061000C
RRCFG_ERRMSKR0
00000000 00000000 00000000 00000000
0xB0610010
RRCFG_ERRMSKR1
00000000 00000000 00000000 00000000
0xB0610014
RRCFG_ECCEN
00000000 00000000 00000000 00000001
0xB0610018B0617FFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0618000
RTC_WTCR
00000000 00000000 00000000 00000000
0xB0618004
RTC_WTSR
00000000 00000000 00000000 00000000
0xB0618008
RTC_WINS
00000000 00000000 00000000 00000000
0xB061800C
RTC_WINE
00000000 00000000 00000000 00000000
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-4 Memory layout of the MCU_CONFIG registers (8 / 11)
Offset
+3
+2
+1
0xB0618010
RTC_WINC
00000000 00000000 00000000 00000000
0xB0618014
RTC_WTBR
00000000 00000000 00000000 00000000
0xB0618018
RTC_WRT
00000000 00000000 00000000 00000000
0xB061801C
RTC_CNTCAL
00000000 00000000 00000000 00000000
0xB0618020
RTC_CNTPCAL
00000000 00000000 00000000 00000000
0xB0618024
RTC_DURMW
00000000 00000000 00000000 00000000
0xB0618028
RTC_CALTRG
00000000 00000000 00000000 00000000
0xB061802C
RTC_DEBUG
00000000 00000000 00000000 00000000
0xB0618030B061FFFC
reserved
00000000 00000000 00000000 0000000X
0xB0620000
EIC0_ENIR
00000000 00000000 00000000 00000000
0xB0620004
EIC0_ENISR
00000000 00000000 00000000 00000000
0xB0620008
EIC0_ENICR
00000000 00000000 00000000 00000000
0xB062000C
EIC0_EIRR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0620010
EIC0_EIRCR
00000000 00000000 00000000 00000000
0xB0620014
EIC0_NFER
00000000 00000000 00000000 00000000
0xB0620018
EIC0_NFESR
00000000 00000000 00000000 00000000
0xB062001C
EIC0_NFECR
00000000 00000000 00000000 00000000
0xB0620020
EIC0_ELVR0
00000000 00000000 00000000 00000000
0xB0620024
EIC0_ELVR1
00000000 00000000 00000000 00000000
0xB0620028
EIC0_ELVR2
00000000 00000000 00000000 00000000
0xB062002C
EIC0_ELVR3
00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
147
Data
Shee t
Table 5-4 Memory layout of the MCU_CONFIG registers (9 / 11)
Offset
+2
+1
+0
0xB0620030
EIC0_NMIR
00000000 00000000 00000000 00000000
0xB0620034
EIC0_DRER
00000000 00000000 00000000 00000000
0xB0620038
EIC0_DRESR
00000000 00000000 00000000 00000000
0xB062003C
EIC0_DRECR
00000000 00000000 00000000 00000000
0xB0620040
EIC0_DRFR
00000000 00000000 00000000 00000000
0xB0620044B0627FFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0628000
EICU0_CNFGR
00000000 00000000 00000000 00000000
0xB0628004
EICU0_IRENR
00000000 00000000 00000000 00000000
0xB0628008
EICU0_SPLR0
00000000 00000000 00000000 00000000
0xB062800C
EICU0_SPLR1
00000000 00000000 00000000 00000000
0xB0628010
EICU0_SPLR2
00000000 00000000 00000000 00000000
0xB0628014
EICU0_SPLR3
00000000 00000000 00000000 00000000
0xB0628018
EICU0_SPLR4
00000000 00000000 00000000 00000000
0xB062801C
EICU0_SPLR5
00000000 00000000 00000000 00000000
0xB0628020
EICU0_SPLR6
00000000 00000000 00000000 00000000
0xB0628024
EICU0_SPLR7
00000000 00000000 00000000 00000000
0xB0628028B06F7FFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB06F8000
0xB06F8004B06F8FFC
148
+3
read0
00000000 00000000
RICFG7_GFX0DCLKI
00000000 00000000
reserved
00000000 00000000 00000000 00000000
0xB06F9000
read0
00000000 00000000
RICFG7_EIC0INT00
00000000 00000000
0xB06F9004
read0
00000000 00000000
RICFG7_EIC0INT01
00000000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-4 Memory layout of the MCU_CONFIG registers (10 / 11)
Offset
+3
+2
+1
+0
0xB06F9008
read0
00000000 00000000
RICFG7_EIC0INT02
00000000 00000000
0xB06F900C
read0
00000000 00000000
RICFG7_EIC0INT03
00000000 00000000
0xB06F9010
read0
00000000 00000000
RICFG7_EIC0INT04
00000000 00000000
0xB06F9014
read0
00000000 00000000
RICFG7_EIC0INT05
00000000 00000000
0xB06F9018
read0
00000000 00000000
RICFG7_EIC0INT06
00000000 00000000
0xB06F901C
read0
00000000 00000000
RICFG7_EIC0INT07
00000000 00000000
0xB06F9020
read0
00000000 00000000
RICFG7_EIC0INT08
00000000 00000000
0xB06F9024
read0
00000000 00000000
RICFG7_EIC0INT09
00000000 00000000
0xB06F9028
read0
00000000 00000000
RICFG7_EIC0INT10
00000000 00000000
0xB06F902C
read0
00000000 00000000
RICFG7_EIC0INT11
00000000 00000000
0xB06F9030
read0
00000000 00000000
RICFG7_EIC0INT12
00000000 00000000
0xB06F9034
read0
00000000 00000000
RICFG7_EIC0INT13
00000000 00000000
0xB06F9038
read0
00000000 00000000
RICFG7_EIC0INT14
00000000 00000000
0xB06F903C
read0
00000000 00000000
RICFG7_EIC0INT15
00000000 00000000
0xB06F9040
read0
00000000 00000000
RICFG7_EIC0INT16
00000000 00000000
0xB06F9044
read0
00000000 00000000
RICFG7_EIC0INT17
00000000 00000000
0xB06F9048
read0
00000000 00000000
RICFG7_EIC0INT18
00000000 00000000
0xB06F904C
read0
00000000 00000000
RICFG7_EIC0INT19
00000000 00000000
0xB06F9050
read0
00000000 00000000
RICFG7_EIC0INT20
00000000 00000000
0xB06F9054
read0
00000000 00000000
RICFG7_EIC0INT21
00000000 00000000
0xB06F9058
read0
00000000 00000000
RICFG7_EIC0INT22
00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
149
Data
Shee t
Table 5-4 Memory layout of the MCU_CONFIG registers (11 / 11)
Offset
150
+3
+2
+1
+0
0xB06F905C
read0
00000000 00000000
RICFG7_EIC0INT23
00000000 00000000
0xB06F9060
read0
00000000 00000000
RICFG7_EIC0INT24
00000000 00000000
0xB06F9064
read0
00000000 00000000
RICFG7_EIC0INT25
00000000 00000000
0xB06F9068
read0
00000000 00000000
RICFG7_EIC0INT26
00000000 00000000
0xB06F906C
read0
00000000 00000000
RICFG7_EIC0INT27
00000000 00000000
0xB06F9070
read0
00000000 00000000
RICFG7_EIC0INT28
00000000 00000000
0xB06F9074
read0
00000000 00000000
RICFG7_EIC0INT29
00000000 00000000
0xB06F9078
read0
00000000 00000000
RICFG7_EIC0INT30
00000000 00000000
0xB06F907C
read0
00000000 00000000
RICFG7_EIC0INT31
00000000 00000000
0xB06F9080
read0
00000000 00000000
RICFG7_EIC0NMI
00000000 00000000
0xB06F9084B06FFC00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB06FFC04
BSU7_BTST
00000000 00000000 00000000 00000000
0xB06FFC08B06FFC18
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB06FFC1C
BSU7_PEN3
00000000 00000000 00000000 00000000
0xB06FFC20
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB06FFC24
BSU7_PEN5
00000000 00000000 00000000 00000000
0xB06FFC28
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB06FFC2C
BSU7_PEN7
00000000 00000000 00000000 00000000
0xB06FFC30
BSU7_PEN8
00000000 00000000 00000000 00000000
0xB06FFC34B06FFFFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (1 / 51)
Offset
+1
+0
0xB0700000
ADC0_ER32
00000000 00000000
0xB0700002
ADC0_ER10
00000000 00000000
0xB0700004
ADC0_CS1
00000000
ADC0_CS0
00000000
0xB0700006
ADC0_CS3
00000000
ADC0_CS2
00000000
0xB0700008
ADC0_CSS1
00000000
reserved
XXXXXXXX
0xB070000A
ADC0_CSC1
00000000
reserved
XXXXXXXX
0xB070000C
ADC0_CSS3
00000000
reserved
XXXXXXXX
0xB070000E
ADC0_CSC3
00000000
reserved
XXXXXXXX
0xB0700010
ADC0_CR
000000XX XXXXXXXX
0xB0700012
reserved
XXXXXXXX
reserved
XXXXXXXX
0xB0700014
reserved
XXXXXXXX
reserved
XXXXXXXX
0xB0700016
reserved
XXXXXXXX
reserved
XXXXXXXX
0xB0700018
ADC0_CD0
000000XX XXXXXXXX
0xB070001A
ADC0_CD1
000000XX XXXXXXXX
0xB070001C
ADC0_CD2
000000XX XXXXXXXX
0xB070001E
ADC0_CD3
000000XX XXXXXXXX
0xB0700020
ADC0_CD4
000000XX XXXXXXXX
0xB0700022
ADC0_CD5
000000XX XXXXXXXX
0xB0700024
ADC0_CD6
000000XX XXXXXXXX
0xB0700026
ADC0_CD7
000000XX XXXXXXXX
0xB0700028
ADC0_CD8
000000XX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
151
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (2 / 51)
Offset
152
+1
+0
0xB070002A
ADC0_CD9
000000XX XXXXXXXX
0xB070002C
ADC0_CD10
000000XX XXXXXXXX
0xB070002E
ADC0_CD11
000000XX XXXXXXXX
0xB0700030
ADC0_CD12
000000XX XXXXXXXX
0xB0700032
ADC0_CD13
000000XX XXXXXXXX
0xB0700034
ADC0_CD14
000000XX XXXXXXXX
0xB0700036
ADC0_CD15
000000XX XXXXXXXX
0xB0700038
ADC0_CD16
000000XX XXXXXXXX
0xB070003A
ADC0_CD17
000000XX XXXXXXXX
0xB070003C
ADC0_CD18
000000XX XXXXXXXX
0xB070003E
ADC0_CD19
000000XX XXXXXXXX
0xB0700040
ADC0_CD20
000000XX XXXXXXXX
0xB0700042
ADC0_CD21
000000XX XXXXXXXX
0xB0700044
ADC0_CD22
000000XX XXXXXXXX
0xB0700046
ADC0_CD23
000000XX XXXXXXXX
0xB0700048
ADC0_CD24
000000XX XXXXXXXX
0xB070004A
ADC0_CD25
000000XX XXXXXXXX
0xB070004C
ADC0_CD26
000000XX XXXXXXXX
0xB070004E
ADC0_CD27
000000XX XXXXXXXX
0xB0700050
ADC0_CD28
000000XX XXXXXXXX
0xB0700052
ADC0_CD29
000000XX XXXXXXXX
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (3 / 51)
Offset
+1
+0
0xB0700054
ADC0_CD30
000000XX XXXXXXXX
0xB0700056
ADC0_CD31
000000XX XXXXXXXX
0xB0700058
reserved
XXXXXXXX
reserved
XXXXXXXX
0xB070005A
reserved
XXXXXXXX
reserved
XXXXXXXX
0xB070005C
reserved
XXXXXXXX
reserved
XXXXXXXX
ADC0_CT
00010000 00101100
0xB070005E
0xB0700060
ADC0_ECH
00000000
ADC0_SCH
00000000
0xB0700062
reserved
XXXXXXXX
ADC0_MAR
00000000
0xB0700064
reserved
XXXXXXXX
ADC0_MACR
00000000
0xB0700066
reserved
XXXXXXXX
ADC0_MASR
00000000
0xB0700068
ADC0_RCOH0
11111111
ADC0_RCOL0
00000000
0xB070006A
ADC0_RCOH1
11111111
ADC0_RCOL1
00000000
0xB070006C
ADC0_RCOH2
11111111
ADC0_RCOL2
00000000
0xB070006E
ADC0_RCOH3
11111111
ADC0_RCOL3
00000000
0xB0700070
ADC0_CC1
00000000
ADC0_CC0
00000000
0xB0700072
ADC0_CC3
00000000
ADC0_CC2
00000000
0xB0700074
ADC0_CC5
00000000
ADC0_CC4
00000000
0xB0700076
ADC0_CC7
00000000
ADC0_CC6
00000000
0xB0700078
ADC0_CC9
00000000
ADC0_CC8
00000000
0xB070007A
ADC0_CC11
00000000
ADC0_CC10
00000000
0xB070007C
ADC0_CC13
00000000
ADC0_CC12
00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
153
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (4 / 51)
154
Offset
+1
+0
0xB070007E
ADC0_CC15
00000000
ADC0_CC14
00000000
0xB0700080
ADC0_RCOIRS32
00000000 00000000
0xB0700082
ADC0_RCOIRS10
00000000 00000000
0xB0700084
ADC0_RCOOF32
00000000 00000000
0xB0700086
ADC0_RCOOF10
00000000 00000000
0xB0700088
ADC0_RCOINT32
00000000 00000000
0xB070008A
ADC0_RCOINT10
00000000 00000000
0xB070008C
ADC0_RCOINTC32
00000000 00000000
0xB070008E
ADC0_RCOINTC10
00000000 00000000
0xB0700090
ADC0_PCTNRL0
00000000
ADC0_PCTPRL0
00000000
0xB0700092
ADC0_PCTNCT0
00000000
ADC0_PCTPCT0
00000000
0xB0700094
ADC0_PCTNRL1
00000000
ADC0_PCTPRL1
00000000
0xB0700096
ADC0_PCTNCT1
00000000
ADC0_PCTPCT1
00000000
0xB0700098
ADC0_PCTNRL2
00000000
ADC0_PCTPRL2
00000000
0xB070009A
ADC0_PCTNCT2
00000000
ADC0_PCTPCT2
00000000
0xB070009C
ADC0_PCTNRL3
00000000
ADC0_PCTPRL3
00000000
0xB070009E
ADC0_PCTNCT3
00000000
ADC0_PCTPCT3
00000000
0xB07000A0
ADC0_PCTNRL4
00000000
ADC0_PCTPRL4
00000000
0xB07000A2
ADC0_PCTNCT4
00000000
ADC0_PCTPCT4
00000000
0xB07000A4
ADC0_PCTNRL5
00000000
ADC0_PCTPRL5
00000000
0xB07000A6
ADC0_PCTNCT5
00000000
ADC0_PCTPCT5
00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (5 / 51)
Offset
+1
+0
0xB07000A8
ADC0_PCTNRL6
00000000
ADC0_PCTPRL6
00000000
0xB07000AA
ADC0_PCTNCT6
00000000
ADC0_PCTPCT6
00000000
0xB07000AC
ADC0_PCTNRL7
00000000
ADC0_PCTPRL7
00000000
0xB07000AE
ADC0_PCTNCT7
00000000
ADC0_PCTPCT7
00000000
0xB07000B0
ADC0_PCTNRL8
00000000
ADC0_PCTPRL8
00000000
0xB07000B2
ADC0_PCTNCT8
00000000
ADC0_PCTPCT8
00000000
0xB07000B4
ADC0_PCTNRL9
00000000
ADC0_PCTPRL9
00000000
0xB07000B6
ADC0_PCTNCT9
00000000
ADC0_PCTPCT9
00000000
0xB07000B8
ADC0_PCTNRL10
00000000
ADC0_PCTPRL10
00000000
0xB07000BA
ADC0_PCTNCT10
00000000
ADC0_PCTPCT10
00000000
0xB07000BC
ADC0_PCTNRL11
00000000
ADC0_PCTPRL11
00000000
0xB07000BE
ADC0_PCTNCT11
00000000
ADC0_PCTPCT11
00000000
0xB07000C0
ADC0_PCTNRL12
00000000
ADC0_PCTPRL12
00000000
0xB07000C2
ADC0_PCTNCT12
00000000
ADC0_PCTPCT12
00000000
0xB07000C4
ADC0_PCTNRL13
00000000
ADC0_PCTPRL13
00000000
0xB07000C6
ADC0_PCTNCT13
00000000
ADC0_PCTPCT13
00000000
0xB07000C8
ADC0_PCTNRL14
00000000
ADC0_PCTPRL14
00000000
0xB07000CA
ADC0_PCTNCT14
00000000
ADC0_PCTPCT14
00000000
0xB07000CC
ADC0_PCTNRL15
00000000
ADC0_PCTPRL15
00000000
0xB07000CE
ADC0_PCTNCT15
00000000
ADC0_PCTPCT15
00000000
0xB07000D0
ADC0_PCTNRL16
00000000
ADC0_PCTPRL16
00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
155
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (6 / 51)
156
Offset
+1
+0
0xB07000D2
ADC0_PCTNCT16
00000000
ADC0_PCTPCT16
00000000
0xB07000D4
ADC0_PCTNRL17
00000000
ADC0_PCTPRL17
00000000
0xB07000D6
ADC0_PCTNCT17
00000000
ADC0_PCTPCT17
00000000
0xB07000D8
ADC0_PCTNRL18
00000000
ADC0_PCTPRL18
00000000
0xB07000DA
ADC0_PCTNCT18
00000000
ADC0_PCTPCT18
00000000
0xB07000DC
ADC0_PCTNRL19
00000000
ADC0_PCTPRL19
00000000
0xB07000DE
ADC0_PCTNCT19
00000000
ADC0_PCTPCT19
00000000
0xB07000E0
ADC0_PCTNRL20
00000000
ADC0_PCTPRL20
00000000
0xB07000E2
ADC0_PCTNCT20
00000000
ADC0_PCTPCT20
00000000
0xB07000E4
ADC0_PCTNRL21
00000000
ADC0_PCTPRL21
00000000
0xB07000E6
ADC0_PCTNCT21
00000000
ADC0_PCTPCT21
00000000
0xB07000E8
ADC0_PCTNRL22
00000000
ADC0_PCTPRL22
00000000
0xB07000EA
ADC0_PCTNCT22
00000000
ADC0_PCTPCT22
00000000
0xB07000EC
ADC0_PCTNRL23
00000000
ADC0_PCTPRL23
00000000
0xB07000EE
ADC0_PCTNCT23
00000000
ADC0_PCTPCT23
00000000
0xB07000F0
ADC0_PCTNRL24
00000000
ADC0_PCTPRL24
00000000
0xB07000F2
ADC0_PCTNCT24
00000000
ADC0_PCTPCT24
00000000
0xB07000F4
ADC0_PCTNRL25
00000000
ADC0_PCTPRL25
00000000
0xB07000F6
ADC0_PCTNCT25
00000000
ADC0_PCTPCT25
00000000
0xB07000F8
ADC0_PCTNRL26
00000000
ADC0_PCTPRL26
00000000
0xB07000FA
ADC0_PCTNCT26
00000000
ADC0_PCTPCT26
00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (7 / 51)
Offset
+1
+0
0xB07000FC
ADC0_PCTNRL27
00000000
ADC0_PCTPRL27
00000000
0xB07000FE
ADC0_PCTNCT27
00000000
ADC0_PCTPCT27
00000000
0xB0700100
ADC0_PCTNRL28
00000000
ADC0_PCTPRL28
00000000
0xB0700102
ADC0_PCTNCT28
00000000
ADC0_PCTPCT28
00000000
0xB0700104
ADC0_PCTNRL29
00000000
ADC0_PCTPRL29
00000000
0xB0700106
ADC0_PCTNCT29
00000000
ADC0_PCTPCT29
00000000
0xB0700108
ADC0_PCTNRL30
00000000
ADC0_PCTPRL30
00000000
0xB070010A
ADC0_PCTNCT30
00000000
ADC0_PCTPCT30
00000000
0xB070010C
ADC0_PCTNRL31
00000000
ADC0_PCTPRL31
00000000
0xB070010E
ADC0_PCTNCT31
00000000
ADC0_PCTPCT31
00000000
0xB0700110
ADC0_PCZF10
00000000 00000000
0xB0700112
ADC0_PCZF32
00000000 00000000
0xB0700114
ADC0_PCZFC10
00000000 00000000
0xB0700116
ADC0_PCZFC32
00000000 00000000
0xB0700118
ADC0_PCIE10
00000000 00000000
0xB070011A
ADC0_PCIE32
00000000 00000000
0xB070011C
ADC0_PCIES10
00000000 00000000
0xB070011E
ADC0_PCIES32
00000000 00000000
0xB0700120
ADC0_PCIEC10
00000000 00000000
0xB0700122
ADC0_PCIEC32
00000000 00000000
0xB0700124B0707FFE
reserved
XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
157
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (8 / 51)
Offset
+0
0xB0708000
FRT0_TCDT
00000000 00000000
0xB0708002
FRT0_CPCLRB
11111111 11111111
0xB0708004
FRT0_CPCLR
11111111 11111111
0xB0708006
FRT0_TCCS
00000000 00000000
0xB0708008
FRT0_TSTPTCLK
01000000 00000000
0xB070800A
FRT0_ETCCS
00000000 00000000
0xB070800C
FRT0_CIMSZIMS
00000000 00000000
0xB070800E
reserved
XXXXXXXX
FRT0_DMACFG
00000000
0xB0708010B07083FE
reserved
XXXXXXXX XXXXXXXX
0xB0708400
FRT1_TCDT
00000000 00000000
0xB0708402
FRT1_CPCLRB
11111111 11111111
0xB0708404
FRT1_CPCLR
11111111 11111111
0xB0708406
FRT1_TCCS
00000000 00000000
0xB0708408
FRT1_TSTPTCLK
01000000 00000000
0xB070840A
FRT1_ETCCS
00000000 00000000
0xB070840C
FRT1_CIMSZIMS
00000000 00000000
0xB070840E
158
+1
reserved
XXXXXXXX
FRT1_DMACFG
00000000
0xB0708410B07087FE
reserved
XXXXXXXX XXXXXXXX
0xB0708800
FRT2_TCDT
00000000 00000000
0xB0708802
FRT2_CPCLRB
11111111 11111111
0xB0708804
FRT2_CPCLR
11111111 11111111
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (9 / 51)
Offset
+1
+0
0xB0708806
FRT2_TCCS
00000000 00000000
0xB0708808
FRT2_TSTPTCLK
01000000 00000000
0xB070880A
FRT2_ETCCS
00000000 00000000
0xB070880C
FRT2_CIMSZIMS
00000000 00000000
0xB070880E
FRT2_DMACFG
00000000
reserved
XXXXXXXX
0xB0708810B0708BFE
reserved
XXXXXXXX XXXXXXXX
0xB0708C00
FRT3_TCDT
00000000 00000000
0xB0708C02
FRT3_CPCLRB
11111111 11111111
0xB0708C04
FRT3_CPCLR
11111111 11111111
0xB0708C06
FRT3_TCCS
00000000 00000000
0xB0708C08
FRT3_TSTPTCLK
01000000 00000000
0xB0708C0A
FRT3_ETCCS
00000000 00000000
0xB0708C0C
FRT3_CIMSZIMS
00000000 00000000
0xB0708C0E
reserved
XXXXXXXX
FRT3_DMACFG
00000000
0xB0708C10B07107FE
reserved
XXXXXXXX XXXXXXXX
0xB0710800
ICU2_IPC0
00000000 00000000
0xB0710802
ICU2_IPC1
00000000 00000000
0xB0710804
ICU2_ICC01
00000000 00000000
0xB0710806
ICU2_ICEICS01
00000000 00000000
0xB0710808
0xB071080AB0710BFE
January 30, 2015, MB9EF226_DS707-00004-2v1-E
ICU2_DEBUG01
00000000
ICU2_DMACFG01
00000000
reserved
XXXXXXXX XXXXXXXX
159
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (10 / 51)
Offset
+0
0xB0710C00
ICU3_IPC0
00000000 00000000
0xB0710C02
ICU3_IPC1
00000000 00000000
0xB0710C04
ICU3_ICC01
00000000 00000000
0xB0710C06
ICU3_ICEICS01
00000000 00000000
0xB0710C08
ICU3_DEBUG01
00000000
ICU3_DMACFG01
00000000
0xB0710C0AB0717FFE
reserved
XXXXXXXX XXXXXXXX
0xB0718000
OCU0_OCCP0
00000000 00000000
0xB0718002
OCU0_OCCP1
00000000 00000000
0xB0718004
OCU0_OCCPB0
00000000 00000000
0xB0718006
OCU0_OCCPB1
00000000 00000000
0xB0718008
OCU0_OCCPBD0
00000000 00000000
0xB071800A
OCU0_OCCPBD1
00000000 00000000
0xB071800C
OCU0_OCS01
00000000 00000000
0xB071800E
OCU0_OCSC01
00000000 00000000
0xB0718010
OCU0_OCSS01
00000000 00000000
0xB0718012
reserved
XXXXXXXX
OCU0_OSR01
00000000
0xB0718014
reserved
XXXXXXXX
OCU0_OSCR01
00000000
0xB0718016
160
+1
OCU0_EOCS01
00000000 00000000
0xB0718018
OCU0_EOCSSH01
00000000
reserved
XXXXXXXX
0xB071801A
OCU0_EOCSCH01
00000000
reserved
XXXXXXXX
0xB071801C
OCU0_DEBUG01
00000000
OCU0_DMACFG01
00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (11 / 51)
Offset
+1
+0
0xB071801E
OCU0_OCMCR01
00000000
reserved
XXXXXXXX
0xB0718020B07183FE
reserved
XXXXXXXX XXXXXXXX
0xB0718400
OCU1_OCCP0
00000000 00000000
0xB0718402
OCU1_OCCP1
00000000 00000000
0xB0718404
OCU1_OCCPB0
00000000 00000000
0xB0718406
OCU1_OCCPB1
00000000 00000000
0xB0718408
OCU1_OCCPBD0
00000000 00000000
0xB071840A
OCU1_OCCPBD1
00000000 00000000
0xB071840C
OCU1_OCS01
00000000 00000000
0xB071840E
OCU1_OCSC01
00000000 00000000
0xB0718410
OCU1_OCSS01
00000000 00000000
0xB0718412
reserved
XXXXXXXX
OCU1_OSR01
00000000
0xB0718414
reserved
XXXXXXXX
OCU1_OSCR01
00000000
0xB0718416
OCU1_EOCS01
00000000 00000000
0xB0718418
OCU1_EOCSSH01
00000000
reserved
XXXXXXXX
0xB071841A
OCU1_EOCSCH01
00000000
reserved
XXXXXXXX
0xB071841C
OCU1_DEBUG01
00000000
OCU1_DMACFG01
00000000
0xB071841E
OCU1_OCMCR01
00000000
reserved
XXXXXXXX
0xB0718420B071FFFE
reserved
XXXXXXXX XXXXXXXX
0xB0720000
I2C0_IBCSR
00000000 00000000
0xB0720002
I2C0_ITBA
00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
161
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (12 / 51)
Offset
+0
0xB0720004
I2C0_ITMK
00XXXX11 11111111
0xB0720006
I2C0_ISBMA
01111111 00000000
0xB0720008
reserved
XXXXXXXX
I2C0_IODAR
00000000
0xB072000A
reserved
XXXXXXXX
I2C0_ICCR
00111111
0xB072000C
I2C0_ICDIDAR
00000000 00000000
0xB072000E
I2C0_IEICR
00000000 00000000
0xB0720010
I2C0_DDMACFG
00000000 00000000
0xB0720012
0xB0720014B0727FFE
162
+1
reserved
XXXXXXXX
I2C0_IEIER
00000000
reserved
XXXXXXXX XXXXXXXX
0xB0728000
USART0_SCR
00000000
USART0_SMR
00000000
0xB0728002
USART0_SCSR
00000000
USART0_SMSR
00000000
0xB0728004
USART0_SCCR
00000000
reserved
XXXXXXXX
0xB0728006
USART0_SSR
00001000
USART0_TDR
00000000
0xB0728008
USART0_SSSR
00000000
USART0_RDR
00000000
0xB072800A
USART0_SSCR
00000000
reserved
XXXXXXXX
0xB072800C
USART0_ESCR
00000100
USART0_ECCR
000000XX
0xB072800E
USART0_ESCSR
00000000
USART0_ECCSR
00000000
0xB0728010
USART0_ESCCR
00000000
USART0_ECCCR
00000000
0xB0728012
USART0_EIER
00000000
USART0_ESIR
000010X0
0xB0728014
USART0_EIESR
00000000
USART0_ESISR
00000000
0xB0728016
USART0_EIECR
00000000
USART0_ESICR
00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (13 / 51)
Offset
+1
+0
0xB0728018
USART0_EFERH
00000000
USART0_EFERL
00000000
0xB072801A
USART0_TFCR
00000000
USART0_RFCR
00000000
0xB072801C
USART0_TFCSR
00000000
USART0_RFCSR
00000000
0xB072801E
USART0_TFCCR
00000000
USART0_RFCCR
00000000
0xB0728020
USART0_TFSR
00000000
USART0_RFSR
00000000
0xB0728022
USART0_ESR
00000000
USART0_CSCR
00000000
0xB0728024
reserved
XXXXXXXX
USART0_CSCSR
00000000
0xB0728026
USART0_ESCLR
00000000
USART0_CSCCR
00000000
0xB0728028
USART0_BGRLM
00000000
USART0_BGRLL
00000000
0xB072802A
reserved
XXXXXXXX
USART0_BGRLH
00000000
0xB072802C
USART0_BGRM
00000000
USART0_BGRL
00000000
0xB072802E
reserved
XXXXXXXX
USART0_BGRH
00000000
0xB0728030
USART0_SRXDR
00000000
USART0_STXDR
00000000
0xB0728032
USART0_SRXDSR
00000000
USART0_STXDSR
00000000
0xB0728034
USART0_SRXDCR
00000000
USART0_STXDCR
00000000
0xB0728036
read0
00000000
read0
00000000
0xB0728038
reserved
XXXXXXXX
read0
00000000
0xB072803A
reserved
XXXXXXXX
USART0_FIDR
00000000
0xB072803C
reserved
XXXXXXXX
USART0_DEBUG
00000000
0xB072803EB072FFFE
0xB0730000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX
SMC0_PWC
00000000
163
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (14 / 51)
Offset
+1
+0
0xB0730002
reserved
XXXXXXXX
SMC0_PWCS
00000000
0xB0730004
reserved
XXXXXXXX
SMC0_PWCC
00000000
0xB0730006
SMC0_PWC1
000000XX XXXXXXXX
0xB0730008
SMC0_PWC2
000000XX XXXXXXXX
0xB073000A
SMC0_PWS
00000000 00000000
0xB073000C
SMC0_PWSS
00000000 XXXXXXXX
0xB073000E
reserved
XXXXXXXX
SMC0_PTRGDL
00000000
0xB0730010
reserved
XXXXXXXX
SMC0_DEBUG
00000000
0xB0730012B07303FE
0xB0730400
reserved
XXXXXXXX
SMC1_PWC
00000000
0xB0730402
reserved
XXXXXXXX
SMC1_PWCS
00000000
0xB0730404
reserved
XXXXXXXX
SMC1_PWCC
00000000
0xB0730406
SMC1_PWC1
000000XX XXXXXXXX
0xB0730408
SMC1_PWC2
000000XX XXXXXXXX
0xB073040A
SMC1_PWS
00000000 00000000
0xB073040C
SMC1_PWSS
00000000 XXXXXXXX
0xB073040E
reserved
XXXXXXXX
SMC1_PTRGDL
00000000
0xB0730410
reserved
XXXXXXXX
SMC1_DEBUG
00000000
0xB0730412B07307FE
164
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
0xB0730800
reserved
XXXXXXXX
SMC2_PWC
00000000
0xB0730802
reserved
XXXXXXXX
SMC2_PWCS
00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (15 / 51)
Offset
+1
+0
0xB0730804
reserved
XXXXXXXX
SMC2_PWCC
00000000
0xB0730806
SMC2_PWC1
000000XX XXXXXXXX
0xB0730808
SMC2_PWC2
000000XX XXXXXXXX
0xB073080A
SMC2_PWS
00000000 00000000
0xB073080C
SMC2_PWSS
00000000 XXXXXXXX
0xB073080E
reserved
XXXXXXXX
SMC2_PTRGDL
00000000
0xB0730810
reserved
XXXXXXXX
SMC2_DEBUG
00000000
0xB0730812B0730BFE
reserved
XXXXXXXX XXXXXXXX
0xB0730C00
reserved
XXXXXXXX
SMC3_PWC
00000000
0xB0730C02
reserved
XXXXXXXX
SMC3_PWCS
00000000
0xB0730C04
reserved
XXXXXXXX
SMC3_PWCC
00000000
0xB0730C06
SMC3_PWC1
000000XX XXXXXXXX
0xB0730C08
SMC3_PWC2
000000XX XXXXXXXX
0xB0730C0A
SMC3_PWS
00000000 00000000
0xB0730C0C
SMC3_PWSS
00000000 XXXXXXXX
0xB0730C0E
reserved
XXXXXXXX
SMC3_PTRGDL
00000000
0xB0730C10
reserved
XXXXXXXX
SMC3_DEBUG
00000000
0xB0730C12B0730FFE
reserved
XXXXXXXX XXXXXXXX
0xB0731000
reserved
XXXXXXXX
SMC4_PWC
00000000
0xB0731002
reserved
XXXXXXXX
SMC4_PWCS
00000000
0xB0731004
reserved
XXXXXXXX
SMC4_PWCC
00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
165
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (16 / 51)
Offset
+0
0xB0731006
SMC4_PWC1
000000XX XXXXXXXX
0xB0731008
SMC4_PWC2
000000XX XXXXXXXX
0xB073100A
SMC4_PWS
00000000 00000000
0xB073100C
SMC4_PWSS
00000000 XXXXXXXX
0xB073100E
reserved
XXXXXXXX
SMC4_PTRGDL
00000000
0xB0731010
reserved
XXXXXXXX
SMC4_DEBUG
00000000
0xB0731012B07313FE
reserved
XXXXXXXX XXXXXXXX
0xB0731400
reserved
XXXXXXXX
SMC5_PWC
00000000
0xB0731402
reserved
XXXXXXXX
SMC5_PWCS
00000000
0xB0731404
reserved
XXXXXXXX
SMC5_PWCC
00000000
0xB0731406
SMC5_PWC1
000000XX XXXXXXXX
0xB0731408
SMC5_PWC2
000000XX XXXXXXXX
0xB073140A
SMC5_PWS
00000000 00000000
0xB073140C
SMC5_PWSS
00000000 XXXXXXXX
0xB073140E
reserved
XXXXXXXX
SMC5_PTRGDL
00000000
0xB0731410
reserved
XXXXXXXX
SMC5_DEBUG
00000000
0xB0731412B07317FE
reserved
XXXXXXXX XXXXXXXX
0xB0731800
SMCTG0_PTRGS
00000000 00000000
0xB0731802
166
+1
reserved
XXXXXXXX
SMCTG0_PTRG
00000000
0xB0731804B0737FFE
reserved
XXXXXXXX XXXXXXXX
0xB0738000
PPG0_PCN
00000000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (17 / 51)
Offset
+1
+0
0xB0738002
PPG0_SWTRIG
00000000
PPG0_IRQCLR
00000000
0xB0738004
PPG0_CNTEN
00000000
PPG0_OE
00000000
0xB0738006
PPG0_RMPCFG
00000000
PPG0_OPTMSK
00000000
0xB0738008
PPG0_TRIGCLR
00000000
PPG0_STRD
00000000
0xB073800A
PPG0_EPCN1
00000000 00000000
0xB073800C
PPG0_EPCN2
00000000 00000000
0xB073800E
PPG0_GCN3
00000000
PPG0_GCN1
00000000
0xB0738010
PPG0_GCN5
00000000
PPG0_GCN4
00000110
0xB0738012
PPG0_PCSR
XXXXXXXX XXXXXXXX
0xB0738014
PPG0_PDUT
XXXXXXXX XXXXXXXX
0xB0738016
PPG0_PTMR
11111111 11111111
0xB0738018
PPG0_PSDR
00000000 00000000
0xB073801A
PPG0_PTPC
00000000 00000000
0xB073801C
PPG0_PEDR
00000000 00000000
0xB073801E
PPG0_DEBUG
00000000
PPG0_DMACFG
00000000
0xB0738020B07383FE
reserved
XXXXXXXX XXXXXXXX
0xB0738400
PPG1_PCN
00000000 00000000
0xB0738402
PPG1_SWTRIG
00000000
PPG1_IRQCLR
00000000
0xB0738404
PPG1_CNTEN
00000000
PPG1_OE
00000000
0xB0738406
PPG1_RMPCFG
00000000
PPG1_OPTMSK
00000000
0xB0738408
PPG1_TRIGCLR
00000000
PPG1_STRD
00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
167
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (18 / 51)
Offset
+0
0xB073840A
PPG1_EPCN1
00000000 00000000
0xB073840C
PPG1_EPCN2
00000000 00000000
0xB073840E
PPG1_GCN3
00000000
PPG1_GCN1
00000000
0xB0738410
PPG1_GCN5
00000000
PPG1_GCN4
00000110
0xB0738412
PPG1_PCSR
XXXXXXXX XXXXXXXX
0xB0738414
PPG1_PDUT
XXXXXXXX XXXXXXXX
0xB0738416
PPG1_PTMR
11111111 11111111
0xB0738418
PPG1_PSDR
00000000 00000000
0xB073841A
PPG1_PTPC
00000000 00000000
0xB073841C
PPG1_PEDR
00000000 00000000
0xB073841E
168
+1
PPG1_DEBUG
00000000
PPG1_DMACFG
00000000
0xB0738420B07387FE
reserved
XXXXXXXX XXXXXXXX
0xB0738800
PPG2_PCN
00000000 00000000
0xB0738802
PPG2_SWTRIG
00000000
PPG2_IRQCLR
00000000
0xB0738804
PPG2_CNTEN
00000000
PPG2_OE
00000000
0xB0738806
PPG2_RMPCFG
00000000
PPG2_OPTMSK
00000000
0xB0738808
PPG2_TRIGCLR
00000000
PPG2_STRD
00000000
0xB073880A
PPG2_EPCN1
00000000 00000000
0xB073880C
PPG2_EPCN2
00000000 00000000
0xB073880E
PPG2_GCN3
00000000
PPG2_GCN1
00000000
0xB0738810
PPG2_GCN5
00000000
PPG2_GCN4
00000110
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (19 / 51)
Offset
+1
+0
0xB0738812
PPG2_PCSR
XXXXXXXX XXXXXXXX
0xB0738814
PPG2_PDUT
XXXXXXXX XXXXXXXX
0xB0738816
PPG2_PTMR
11111111 11111111
0xB0738818
PPG2_PSDR
00000000 00000000
0xB073881A
PPG2_PTPC
00000000 00000000
0xB073881C
PPG2_PEDR
00000000 00000000
0xB073881E
PPG2_DEBUG
00000000
PPG2_DMACFG
00000000
0xB0738820B0738BFE
reserved
XXXXXXXX XXXXXXXX
0xB0738C00
PPG3_PCN
00000000 00000000
0xB0738C02
PPG3_SWTRIG
00000000
PPG3_IRQCLR
00000000
0xB0738C04
PPG3_CNTEN
00000000
PPG3_OE
00000000
0xB0738C06
PPG3_RMPCFG
00000000
PPG3_OPTMSK
00000000
0xB0738C08
PPG3_TRIGCLR
00000000
PPG3_STRD
00000000
0xB0738C0A
PPG3_EPCN1
00000000 00000000
0xB0738C0C
PPG3_EPCN2
00000000 00000000
0xB0738C0E
PPG3_GCN3
00000000
PPG3_GCN1
00000000
0xB0738C10
PPG3_GCN5
00000000
PPG3_GCN4
00000110
0xB0738C12
PPG3_PCSR
XXXXXXXX XXXXXXXX
0xB0738C14
PPG3_PDUT
XXXXXXXX XXXXXXXX
0xB0738C16
PPG3_PTMR
11111111 11111111
0xB0738C18
PPG3_PSDR
00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
169
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (20 / 51)
Offset
+0
0xB0738C1A
PPG3_PTPC
00000000 00000000
0xB0738C1C
PPG3_PEDR
00000000 00000000
0xB0738C1E
PPG3_DEBUG
00000000
PPG3_DMACFG
00000000
0xB0738C20B0738FFE
reserved
XXXXXXXX XXXXXXXX
0xB0739000
PPG4_PCN
00000000 00000000
0xB0739002
PPG4_SWTRIG
00000000
PPG4_IRQCLR
00000000
0xB0739004
PPG4_CNTEN
00000000
PPG4_OE
00000000
0xB0739006
PPG4_RMPCFG
00000000
PPG4_OPTMSK
00000000
0xB0739008
PPG4_TRIGCLR
00000000
PPG4_STRD
00000000
0xB073900A
PPG4_EPCN1
00000000 00000000
0xB073900C
PPG4_EPCN2
00000000 00000000
0xB073900E
PPG4_GCN3
00000000
PPG4_GCN1
00000000
0xB0739010
PPG4_GCN5
00000000
PPG4_GCN4
00000110
0xB0739012
PPG4_PCSR
XXXXXXXX XXXXXXXX
0xB0739014
PPG4_PDUT
XXXXXXXX XXXXXXXX
0xB0739016
PPG4_PTMR
11111111 11111111
0xB0739018
PPG4_PSDR
00000000 00000000
0xB073901A
PPG4_PTPC
00000000 00000000
0xB073901C
PPG4_PEDR
00000000 00000000
0xB073901E
0xB0739020B07393FE
170
+1
PPG4_DEBUG
00000000
PPG4_DMACFG
00000000
reserved
XXXXXXXX XXXXXXXX
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (21 / 51)
Offset
0xB0739400
+1
+0
PPG5_PCN
00000000 00000000
0xB0739402
PPG5_SWTRIG
00000000
PPG5_IRQCLR
00000000
0xB0739404
PPG5_CNTEN
00000000
PPG5_OE
00000000
0xB0739406
PPG5_RMPCFG
00000000
PPG5_OPTMSK
00000000
0xB0739408
PPG5_TRIGCLR
00000000
PPG5_STRD
00000000
0xB073940A
PPG5_EPCN1
00000000 00000000
0xB073940C
PPG5_EPCN2
00000000 00000000
0xB073940E
PPG5_GCN3
00000000
PPG5_GCN1
00000000
0xB0739410
PPG5_GCN5
00000000
PPG5_GCN4
00000110
0xB0739412
PPG5_PCSR
XXXXXXXX XXXXXXXX
0xB0739414
PPG5_PDUT
XXXXXXXX XXXXXXXX
0xB0739416
PPG5_PTMR
11111111 11111111
0xB0739418
PPG5_PSDR
00000000 00000000
0xB073941A
PPG5_PTPC
00000000 00000000
0xB073941C
PPG5_PEDR
00000000 00000000
0xB073941E
PPG5_DEBUG
00000000
PPG5_DMACFG
00000000
0xB0739420B07397FE
reserved
XXXXXXXX XXXXXXXX
0xB0739800
PPG6_PCN
00000000 00000000
0xB0739802
PPG6_SWTRIG
00000000
PPG6_IRQCLR
00000000
0xB0739804
PPG6_CNTEN
00000000
PPG6_OE
00000000
0xB0739806
PPG6_RMPCFG
00000000
PPG6_OPTMSK
00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
171
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (22 / 51)
Offset
+1
+0
0xB0739808
PPG6_TRIGCLR
00000000
PPG6_STRD
00000000
0xB073980A
PPG6_EPCN1
00000000 00000000
0xB073980C
PPG6_EPCN2
00000000 00000000
0xB073980E
PPG6_GCN3
00000000
PPG6_GCN1
00000000
0xB0739810
PPG6_GCN5
00000000
PPG6_GCN4
00000110
0xB0739812
PPG6_PCSR
XXXXXXXX XXXXXXXX
0xB0739814
PPG6_PDUT
XXXXXXXX XXXXXXXX
0xB0739816
PPG6_PTMR
11111111 11111111
0xB0739818
PPG6_PSDR
00000000 00000000
0xB073981A
PPG6_PTPC
00000000 00000000
0xB073981C
PPG6_PEDR
00000000 00000000
0xB073981E
PPG6_DMACFG
00000000
0xB0739820B0739BFE
reserved
XXXXXXXX XXXXXXXX
0xB0739C00
PPG7_PCN
00000000 00000000
0xB0739C02
PPG7_SWTRIG
00000000
PPG7_IRQCLR
00000000
0xB0739C04
PPG7_CNTEN
00000000
PPG7_OE
00000000
0xB0739C06
PPG7_RMPCFG
00000000
PPG7_OPTMSK
00000000
0xB0739C08
PPG7_TRIGCLR
00000000
PPG7_STRD
00000000
0xB0739C0A
PPG7_EPCN1
00000000 00000000
0xB0739C0C
PPG7_EPCN2
00000000 00000000
0xB0739C0E
172
PPG6_DEBUG
00000000
PPG7_GCN3
00000000
PPG7_GCN1
00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (23 / 51)
Offset
+1
+0
0xB0739C10
PPG7_GCN5
00000000
PPG7_GCN4
00000110
0xB0739C12
PPG7_PCSR
XXXXXXXX XXXXXXXX
0xB0739C14
PPG7_PDUT
XXXXXXXX XXXXXXXX
0xB0739C16
PPG7_PTMR
11111111 11111111
0xB0739C18
PPG7_PSDR
00000000 00000000
0xB0739C1A
PPG7_PTPC
00000000 00000000
0xB0739C1C
PPG7_PEDR
00000000 00000000
0xB0739C1E
PPG7_DEBUG
00000000
PPG7_DMACFG
00000000
0xB0739C20B0739FFE
reserved
XXXXXXXX XXXXXXXX
0xB073A000
PPG8_PCN
00000000 00000000
0xB073A002
PPG8_SWTRIG
00000000
PPG8_IRQCLR
00000000
0xB073A004
PPG8_CNTEN
00000000
PPG8_OE
00000000
0xB073A006
PPG8_RMPCFG
00000000
PPG8_OPTMSK
00000000
0xB073A008
PPG8_TRIGCLR
00000000
PPG8_STRD
00000000
0xB073A00A
PPG8_EPCN1
00000000 00000000
0xB073A00C
PPG8_EPCN2
00000000 00000000
0xB073A00E
PPG8_GCN3
00000000
PPG8_GCN1
00000000
0xB073A010
PPG8_GCN5
00000000
PPG8_GCN4
00000110
0xB073A012
PPG8_PCSR
XXXXXXXX XXXXXXXX
0xB073A014
PPG8_PDUT
XXXXXXXX XXXXXXXX
0xB073A016
PPG8_PTMR
11111111 11111111
January 30, 2015, MB9EF226_DS707-00004-2v1-E
173
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (24 / 51)
Offset
+0
0xB073A018
PPG8_PSDR
00000000 00000000
0xB073A01A
PPG8_PTPC
00000000 00000000
0xB073A01C
PPG8_PEDR
00000000 00000000
0xB073A01E
PPG8_DEBUG
00000000
PPG8_DMACFG
00000000
0xB073A020B073A3FE
reserved
XXXXXXXX XXXXXXXX
0xB073A400
PPG9_PCN
00000000 00000000
0xB073A402
PPG9_SWTRIG
00000000
PPG9_IRQCLR
00000000
0xB073A404
PPG9_CNTEN
00000000
PPG9_OE
00000000
0xB073A406
PPG9_RMPCFG
00000000
PPG9_OPTMSK
00000000
0xB073A408
PPG9_TRIGCLR
00000000
PPG9_STRD
00000000
0xB073A40A
PPG9_EPCN1
00000000 00000000
0xB073A40C
PPG9_EPCN2
00000000 00000000
0xB073A40E
PPG9_GCN3
00000000
PPG9_GCN1
00000000
0xB073A410
PPG9_GCN5
00000000
PPG9_GCN4
00000110
0xB073A412
PPG9_PCSR
XXXXXXXX XXXXXXXX
0xB073A414
PPG9_PDUT
XXXXXXXX XXXXXXXX
0xB073A416
PPG9_PTMR
11111111 11111111
0xB073A418
PPG9_PSDR
00000000 00000000
0xB073A41A
PPG9_PTPC
00000000 00000000
0xB073A41C
PPG9_PEDR
00000000 00000000
0xB073A41E
174
+1
PPG9_DEBUG
00000000
PPG9_DMACFG
00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (25 / 51)
Offset
+1
+0
0xB073A420B073A7FE
reserved
XXXXXXXX XXXXXXXX
0xB073A800
PPG10_PCN
00000000 00000000
0xB073A802
PPG10_SWTRIG
00000000
PPG10_IRQCLR
00000000
0xB073A804
PPG10_CNTEN
00000000
PPG10_OE
00000000
0xB073A806
PPG10_RMPCFG
00000000
PPG10_OPTMSK
00000000
0xB073A808
PPG10_TRIGCLR
00000000
PPG10_STRD
00000000
0xB073A80A
PPG10_EPCN1
00000000 00000000
0xB073A80C
PPG10_EPCN2
00000000 00000000
0xB073A80E
PPG10_GCN3
00000000
PPG10_GCN1
00000000
0xB073A810
PPG10_GCN5
00000000
PPG10_GCN4
00000110
0xB073A812
PPG10_PCSR
XXXXXXXX XXXXXXXX
0xB073A814
PPG10_PDUT
XXXXXXXX XXXXXXXX
0xB073A816
PPG10_PTMR
11111111 11111111
0xB073A818
PPG10_PSDR
00000000 00000000
0xB073A81A
PPG10_PTPC
00000000 00000000
0xB073A81C
PPG10_PEDR
00000000 00000000
0xB073A81E
PPG10_DEBUG
00000000
PPG10_DMACFG
00000000
0xB073A820B073ABFE
reserved
XXXXXXXX XXXXXXXX
0xB073AC00
PPG11_PCN
00000000 00000000
0xB073AC02
PPG11_SWTRIG
00000000
PPG11_IRQCLR
00000000
0xB073AC04
PPG11_CNTEN
00000000
PPG11_OE
00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
175
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (26 / 51)
Offset
+1
+0
0xB073AC06
PPG11_RMPCFG
00000000
PPG11_OPTMSK
00000000
0xB073AC08
PPG11_TRIGCLR
00000000
PPG11_STRD
00000000
0xB073AC0A
PPG11_EPCN1
00000000 00000000
0xB073AC0C
PPG11_EPCN2
00000000 00000000
0xB073AC0E
PPG11_GCN3
00000000
PPG11_GCN1
00000000
0xB073AC10
PPG11_GCN5
00000000
PPG11_GCN4
00000110
0xB073AC12
PPG11_PCSR
XXXXXXXX XXXXXXXX
0xB073AC14
PPG11_PDUT
XXXXXXXX XXXXXXXX
0xB073AC16
PPG11_PTMR
11111111 11111111
0xB073AC18
PPG11_PSDR
00000000 00000000
0xB073AC1A
PPG11_PTPC
00000000 00000000
0xB073AC1C
PPG11_PEDR
00000000 00000000
0xB073AC1E
176
PPG11_DEBUG
00000000
PPG11_DMACFG
00000000
0xB073AC20B073AFFE
reserved
XXXXXXXX XXXXXXXX
0xB073B000
PPG12_PCN
00000000 00000000
0xB073B002
PPG12_SWTRIG
00000000
PPG12_IRQCLR
00000000
0xB073B004
PPG12_CNTEN
00000000
PPG12_OE
00000000
0xB073B006
PPG12_RMPCFG
00000000
PPG12_OPTMSK
00000000
0xB073B008
PPG12_TRIGCLR
00000000
PPG12_STRD
00000000
0xB073B00A
PPG12_EPCN1
00000000 00000000
0xB073B00C
PPG12_EPCN2
00000000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (27 / 51)
Offset
+1
+0
0xB073B00E
PPG12_GCN3
00000000
PPG12_GCN1
00000000
0xB073B010
PPG12_GCN5
00000000
PPG12_GCN4
00000110
0xB073B012
PPG12_PCSR
XXXXXXXX XXXXXXXX
0xB073B014
PPG12_PDUT
XXXXXXXX XXXXXXXX
0xB073B016
PPG12_PTMR
11111111 11111111
0xB073B018
PPG12_PSDR
00000000 00000000
0xB073B01A
PPG12_PTPC
00000000 00000000
0xB073B01C
PPG12_PEDR
00000000 00000000
0xB073B01E
PPG12_DEBUG
00000000
PPG12_DMACFG
00000000
0xB073B020B073B3FE
reserved
XXXXXXXX XXXXXXXX
0xB073B400
PPG13_PCN
00000000 00000000
0xB073B402
PPG13_SWTRIG
00000000
PPG13_IRQCLR
00000000
0xB073B404
PPG13_CNTEN
00000000
PPG13_OE
00000000
0xB073B406
PPG13_RMPCFG
00000000
PPG13_OPTMSK
00000000
0xB073B408
PPG13_TRIGCLR
00000000
PPG13_STRD
00000000
0xB073B40A
PPG13_EPCN1
00000000 00000000
0xB073B40C
PPG13_EPCN2
00000000 00000000
0xB073B40E
PPG13_GCN3
00000000
PPG13_GCN1
00000000
0xB073B410
PPG13_GCN5
00000000
PPG13_GCN4
00000110
0xB073B412
PPG13_PCSR
XXXXXXXX XXXXXXXX
0xB073B414
PPG13_PDUT
XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
177
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (28 / 51)
Offset
+0
0xB073B416
PPG13_PTMR
11111111 11111111
0xB073B418
PPG13_PSDR
00000000 00000000
0xB073B41A
PPG13_PTPC
00000000 00000000
0xB073B41C
PPG13_PEDR
00000000 00000000
0xB073B41E
178
+1
PPG13_DEBUG
00000000
PPG13_DMACFG
00000000
0xB073B420B073B7FE
reserved
XXXXXXXX XXXXXXXX
0xB073B800
PPG14_PCN
00000000 00000000
0xB073B802
PPG14_SWTRIG
00000000
PPG14_IRQCLR
00000000
0xB073B804
PPG14_CNTEN
00000000
PPG14_OE
00000000
0xB073B806
PPG14_RMPCFG
00000000
PPG14_OPTMSK
00000000
0xB073B808
PPG14_TRIGCLR
00000000
PPG14_STRD
00000000
0xB073B80A
PPG14_EPCN1
00000000 00000000
0xB073B80C
PPG14_EPCN2
00000000 00000000
0xB073B80E
PPG14_GCN3
00000000
PPG14_GCN1
00000000
0xB073B810
PPG14_GCN5
00000000
PPG14_GCN4
00000110
0xB073B812
PPG14_PCSR
XXXXXXXX XXXXXXXX
0xB073B814
PPG14_PDUT
XXXXXXXX XXXXXXXX
0xB073B816
PPG14_PTMR
11111111 11111111
0xB073B818
PPG14_PSDR
00000000 00000000
0xB073B81A
PPG14_PTPC
00000000 00000000
0xB073B81C
PPG14_PEDR
00000000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (29 / 51)
Offset
+1
+0
0xB073B81E
PPG14_DEBUG
00000000
PPG14_DMACFG
00000000
0xB073B820B073BBFE
reserved
XXXXXXXX XXXXXXXX
0xB073BC00
PPG15_PCN
00000000 00000000
0xB073BC02
PPG15_SWTRIG
00000000
PPG15_IRQCLR
00000000
0xB073BC04
PPG15_CNTEN
00000000
PPG15_OE
00000000
0xB073BC06
PPG15_RMPCFG
00000000
PPG15_OPTMSK
00000000
0xB073BC08
PPG15_TRIGCLR
00000000
PPG15_STRD
00000000
0xB073BC0A
PPG15_EPCN1
00000000 00000000
0xB073BC0C
PPG15_EPCN2
00000000 00000000
0xB073BC0E
PPG15_GCN3
00000000
PPG15_GCN1
00000000
0xB073BC10
PPG15_GCN5
00000000
PPG15_GCN4
00000110
0xB073BC12
PPG15_PCSR
XXXXXXXX XXXXXXXX
0xB073BC14
PPG15_PDUT
XXXXXXXX XXXXXXXX
0xB073BC16
PPG15_PTMR
11111111 11111111
0xB073BC18
PPG15_PSDR
00000000 00000000
0xB073BC1A
PPG15_PTPC
00000000 00000000
0xB073BC1C
PPG15_PEDR
00000000 00000000
0xB073BC1E
0xB073BC20B0747FFE
0xB0748000
0xB0748002B07483FE
January 30, 2015, MB9EF226_DS707-00004-2v1-E
PPG15_DEBUG
00000000
PPG15_DMACFG
00000000
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX
PPGGRP0_GCTRL
00000000
reserved
XXXXXXXX XXXXXXXX
179
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (30 / 51)
Offset
+1
+0
0xB0748400
reserved
XXXXXXXX
PPGGRP1_GCTRL
00000000
0xB0748402B07487FE
0xB0748800
0xB0748802B0748BFE
0xB0748C00
0xB0748C02B074BFFE
0xB074C000
180
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX
PPGGRP2_GCTRL
00000000
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX
PPGGRP3_GCTRL
00000000
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX
PPGGLC0_GCNR
00000000
0xB074C002B07E7FFE
reserved
XXXXXXXX XXXXXXXX
0xB07E8000
PPC_PCFGR000
0XX00000 00000000
0xB07E8002
PPC_PCFGR001
0XX00000 00000000
0xB07E8004
PPC_PCFGR002
0XX00000 00000000
0xB07E8006
PPC_PCFGR003
0XX00000 00000000
0xB07E8008
PPC_PCFGR004
0XX00000 00000000
0xB07E800A
PPC_PCFGR005
0XX00000 00000000
0xB07E800C
PPC_PCFGR006
0XX00000 00000000
0xB07E800E
PPC_PCFGR007
0XX00000 00000000
0xB07E8010
PPC_PCFGR008
0XX00000 00000000
0xB07E8012
PPC_PCFGR009
0XX00000 00000000
0xB07E8014
PPC_PCFGR010
0XX00000 00000000
0xB07E8016
PPC_PCFGR011
0XX00000 00000000
0xB07E8018
PPC_PCFGR012
0XX00000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (31 / 51)
Offset
+1
+0
0xB07E801A
PPC_PCFGR013
0XX00000 00000000
0xB07E801C
PPC_PCFGR014
0XX00000 00000000
0xB07E801E
PPC_PCFGR015
0XX00000 00000000
0xB07E8020
PPC_PCFGR016
0XX00000 00000000
0xB07E8022
PPC_PCFGR017
0XX00000 00000000
0xB07E8024
PPC_PCFGR018
0XX00000 00000000
0xB07E8026
PPC_PCFGR019
0XX00000 00000000
0xB07E8028
PPC_PCFGR020
0XX00000 00000000
0xB07E802A
PPC_PCFGR021
0XX00000 00000000
0xB07E802C
PPC_PCFGR022
0XX00000 00000000
0xB07E802E
PPC_PCFGR023
0XX00000 00000000
0xB07E8030
PPC_PCFGR024
0XX00000 00000000
0xB07E8032
PPC_PCFGR025
0XX00000 00000000
0xB07E8034
PPC_PCFGR026
0XX00000 00000000
0xB07E8036
PPC_PCFGR027
0XX00000 00000000
0xB07E8038
PPC_PCFGR028
0XX00000 00000000
0xB07E803A
PPC_PCFGR029
0XX00000 00000000
0xB07E803C
PPC_PCFGR030
0XX00000 00000000
0xB07E803E
PPC_PCFGR031
0XX00000 00000000
0xB07E8040
PPC_PCFGR032
0XX00000 00000000
0xB07E8042
PPC_PCFGR033
0XX00000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
181
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (32 / 51)
Offset
182
+1
+0
0xB07E8044
PPC_PCFGR034
0XX00000 00000000
0xB07E8046
PPC_PCFGR035
0XX00000 00000000
0xB07E8048
PPC_PCFGR036
0XX00000 00000000
0xB07E804A
PPC_PCFGR037
0XX00000 00000000
0xB07E804C
PPC_PCFGR038
0XX00000 00000000
0xB07E804E
PPC_PCFGR039
0XX00000 00000000
0xB07E8050
PPC_PCFGR040
0XX00000 00000000
0xB07E8052
PPC_PCFGR041
0XX00000 00000000
0xB07E8054
PPC_PCFGR042
0XX00000 00000000
0xB07E8056
PPC_PCFGR043
0XX00000 00000000
0xB07E8058
PPC_PCFGR044
0XX00000 00000000
0xB07E805A
PPC_PCFGR045
0XX00000 00000000
0xB07E805C
PPC_PCFGR046
0XX00000 00000000
0xB07E805E
PPC_PCFGR047
0XX00000 00000000
0xB07E8060
PPC_PCFGR048
0XX00000 00000000
0xB07E8062
PPC_PCFGR049
0XX00000 00000000
0xB07E8064
PPC_PCFGR050
0XX00000 00000000
0xB07E8066
PPC_PCFGR051
0XX00000 00000000
0xB07E8068
PPC_PCFGR052
0XX00000 00000000
0xB07E806A
PPC_PCFGR053
0XX00000 00000000
0xB07E806C
PPC_PCFGR054
0XX00000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (33 / 51)
Offset
+1
+0
0xB07E806E
PPC_PCFGR055
0XX00000 00000000
0xB07E8070
PPC_PCFGR056
0XX00000 00000000
0xB07E8072
PPC_PCFGR057
0XX00000 00000000
0xB07E8074
PPC_PCFGR058
0XX00000 00000000
0xB07E8076
PPC_PCFGR059
0XX00000 00000000
0xB07E8078
PPC_PCFGR060
0XX00000 00000000
0xB07E807A
PPC_PCFGR061
0XX00000 00000000
0xB07E807C
PPC_PCFGR062
0XX00000 00000000
0xB07E807E
PPC_PCFGR063
0XX00000 00000000
0xB07E8080
PPC_PCFGR100
0XX00000 00000000
0xB07E8082
PPC_PCFGR101
0XX00000 00000000
0xB07E8084
PPC_PCFGR102
0XX00000 00000000
0xB07E8086
PPC_PCFGR103
0XX00000 00000000
0xB07E8088
PPC_PCFGR104
0XX00000 00000000
0xB07E808A
PPC_PCFGR105
0XX00000 00000000
0xB07E808C
PPC_PCFGR106
0XX00000 00000000
0xB07E808E
PPC_PCFGR107
0XX00000 00000000
0xB07E8090
PPC_PCFGR108
0XX00000 00000000
0xB07E8092
PPC_PCFGR109
0XX00000 00000000
0xB07E8094
PPC_PCFGR110
0XX00000 00000000
0xB07E8096
PPC_PCFGR111
0XX00000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
183
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (34 / 51)
Offset
184
+1
+0
0xB07E8098
PPC_PCFGR112
0XX00000 00000000
0xB07E809A
PPC_PCFGR113
0XX00000 00000000
0xB07E809C
PPC_PCFGR114
0XX00000 00000000
0xB07E809E
PPC_PCFGR115
0XX00000 00000000
0xB07E80A0
PPC_PCFGR116
0XX00000 00000000
0xB07E80A2
PPC_PCFGR117
0XX00000 00000000
0xB07E80A4
PPC_PCFGR118
0XX00000 00000000
0xB07E80A6
PPC_PCFGR119
0XX00000 00000000
0xB07E80A8
PPC_PCFGR120
0XX00000 00000000
0xB07E80AA
PPC_PCFGR121
0XX00000 00000000
0xB07E80AC
PPC_PCFGR122
0XX00000 00000000
0xB07E80AE
PPC_PCFGR123
0XX00000 00000000
0xB07E80B0
PPC_PCFGR124
0XX00000 00000000
0xB07E80B2
PPC_PCFGR125
0XX00000 00000000
0xB07E80B4
PPC_PCFGR126
0XX00000 00000000
0xB07E80B6
PPC_PCFGR127
0XX00000 00000000
0xB07E80B8
PPC_PCFGR128
0XX00000 00000000
0xB07E80BA
PPC_PCFGR129
0XX00000 00000000
0xB07E80BC
PPC_PCFGR130
0XX00000 00000000
0xB07E80BE
PPC_PCFGR131
0XX00000 00000000
0xB07E80C0
PPC_PCFGR132
0XX00000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (35 / 51)
Offset
+1
+0
0xB07E80C2
PPC_PCFGR133
0XX00000 00000000
0xB07E80C4
PPC_PCFGR134
0XX00000 00000000
0xB07E80C6
PPC_PCFGR135
0XX00000 00000000
0xB07E80C8
PPC_PCFGR136
0XX00000 00000000
0xB07E80CA
PPC_PCFGR137
0XX00000 00000000
0xB07E80CC
PPC_PCFGR138
0XX00000 00000000
0xB07E80CE
PPC_PCFGR139
0XX00000 00000000
0xB07E80D0
PPC_PCFGR140
0XX00000 00000000
0xB07E80D2
PPC_PCFGR141
0XX00000 00000000
0xB07E80D4
PPC_PCFGR142
0XX00000 00000000
0xB07E80D6
PPC_PCFGR143
0XX00000 00000000
0xB07E80D8
PPC_PCFGR144
0XX00000 00000000
0xB07E80DA
PPC_PCFGR145
0XX00000 00000000
0xB07E80DC
PPC_PCFGR146
0XX00000 00000000
0xB07E80DE
PPC_PCFGR147
0XX00000 00000000
0xB07E80E0
PPC_PCFGR148
0XX00000 00000000
0xB07E80E2
PPC_PCFGR149
0XX00000 00000000
0xB07E80E4
PPC_PCFGR150
0XX00000 00000000
0xB07E80E6
PPC_PCFGR151
0XX00000 00000000
0xB07E80E8
PPC_PCFGR152
0XX00000 00000000
0xB07E80EA
PPC_PCFGR153
0XX00000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
185
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (36 / 51)
Offset
186
+1
+0
0xB07E80EC
PPC_PCFGR154
0XX00000 00000000
0xB07E80EE
PPC_PCFGR155
0XX00000 00000000
0xB07E80F0
PPC_PCFGR156
0XX00000 00000000
0xB07E80F2
PPC_PCFGR157
0XX00000 00000000
0xB07E80F4
PPC_PCFGR158
0XX00000 00000000
0xB07E80F6
PPC_PCFGR159
0XX00000 00000000
0xB07E80F8
PPC_PCFGR160
0XX00000 00000000
0xB07E80FA
PPC_PCFGR161
0XX00000 00000000
0xB07E80FC
PPC_PCFGR162
0XX00000 00000000
0xB07E80FE
PPC_PCFGR163
0XX00000 00000000
0xB07E8100
PPC_PCFGR200
0XX00000 00000000
0xB07E8102
PPC_PCFGR201
0XX00000 00000000
0xB07E8104
PPC_PCFGR202
0XX00000 00000000
0xB07E8106
PPC_PCFGR203
0XX00000 00000000
0xB07E8108
PPC_PCFGR204
0XX00000 00000000
0xB07E810A
PPC_PCFGR205
0XX00000 00000000
0xB07E810C
PPC_PCFGR206
0XX00000 00000000
0xB07E810E
PPC_PCFGR207
0XX00000 00000000
0xB07E8110
PPC_PCFGR208
0XX00000 00000000
0xB07E8112
PPC_PCFGR209
0XX00000 00000000
0xB07E8114
PPC_PCFGR210
0XX00000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (37 / 51)
Offset
+1
+0
0xB07E8116
PPC_PCFGR211
0XX00000 00000000
0xB07E8118
PPC_PCFGR212
0XX00000 00000000
0xB07E811A
PPC_PCFGR213
0XX00000 00000000
0xB07E811C
PPC_PCFGR214
0XX00000 00000000
0xB07E811E
PPC_PCFGR215
0XX00000 00000000
0xB07E8120
PPC_PCFGR216
0XX00000 00000000
0xB07E8122
PPC_PCFGR217
0XX00000 00000000
0xB07E8124
PPC_PCFGR218
0XX00000 00000000
0xB07E8126
PPC_PCFGR219
0XX00000 00000000
0xB07E8128
PPC_PCFGR220
0XX00000 00000000
0xB07E812A
PPC_PCFGR221
0XX00000 00000000
0xB07E812C
PPC_PCFGR222
0XX00000 00000000
0xB07E812E
PPC_PCFGR223
0XX00000 00000000
0xB07E8130
PPC_PCFGR224
0XX00000 00000000
0xB07E8132
PPC_PCFGR225
0XX00000 00000000
0xB07E8134
PPC_PCFGR226
0XX00000 00000000
0xB07E8136
PPC_PCFGR227
0XX00000 00000000
0xB07E8138
PPC_PCFGR228
0XX00000 00000000
0xB07E813A
PPC_PCFGR229
0XX00000 00000000
0xB07E813C
PPC_PCFGR230
0XX00000 00000000
0xB07E813E
PPC_PCFGR231
0XX00000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
187
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (38 / 51)
Offset
188
+1
+0
0xB07E8140
PPC_PCFGR232
0XX00000 00000000
0xB07E8142
PPC_PCFGR233
0XX00000 00000000
0xB07E8144
PPC_PCFGR234
0XX00000 00000000
0xB07E8146
PPC_PCFGR235
0XX00000 00000000
0xB07E8148
PPC_PCFGR236
0XX00000 00000000
0xB07E814A
PPC_PCFGR237
0XX00000 00000000
0xB07E814C
PPC_PCFGR238
0XX00000 00000000
0xB07E814E
PPC_PCFGR239
0XX00000 00000000
0xB07E8150
PPC_PCFGR240
0XX00000 00000000
0xB07E8152
PPC_PCFGR241
0XX00000 00000000
0xB07E8154
PPC_PCFGR242
0XX00000 00000000
0xB07E8156
PPC_PCFGR243
0XX00000 00000000
0xB07E8158
PPC_PCFGR244
0XX00000 00000000
0xB07E815A
PPC_PCFGR245
0XX00000 00000000
0xB07E815C
PPC_PCFGR246
0XX00000 00000000
0xB07E815E
PPC_PCFGR247
0XX00000 00000000
0xB07E8160
PPC_PCFGR248
0XX00000 00000000
0xB07E8162
PPC_PCFGR249
0XX00000 00000000
0xB07E8164
PPC_PCFGR250
0XX00000 00000000
0xB07E8166
PPC_PCFGR251
0XX00000 00000000
0xB07E8168
PPC_PCFGR252
0XX00000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (39 / 51)
Offset
+1
+0
0xB07E816A
PPC_PCFGR253
0XX00000 00000000
0xB07E816C
PPC_PCFGR254
0XX00000 00000000
0xB07E816E
PPC_PCFGR255
0XX00000 00000000
0xB07E8170
PPC_PCFGR256
0XX00000 00000000
0xB07E8172
PPC_PCFGR257
0XX00000 00000000
0xB07E8174
PPC_PCFGR258
0XX00000 00000000
0xB07E8176
PPC_PCFGR259
0XX00000 00000000
0xB07E8178
PPC_PCFGR260
0XX00000 00000000
0xB07E817A
PPC_PCFGR261
0XX00000 00000000
0xB07E817C
PPC_PCFGR262
0XX00000 00000000
0xB07E817E
PPC_PCFGR263
0XX00000 00000000
0xB07E8180
PPC_PCFGR300
0XX00000 00000000
0xB07E8182
PPC_PCFGR301
0XX00000 00000000
0xB07E8184
PPC_PCFGR302
0XX00000 00000000
0xB07E8186
PPC_PCFGR303
0XX00000 00000000
0xB07E8188
PPC_PCFGR304
0XX00000 00000000
0xB07E818A
PPC_PCFGR305
0XX00000 00000000
0xB07E818C
PPC_PCFGR306
0XX00000 00000000
0xB07E818E
PPC_PCFGR307
0XX00000 00000000
0xB07E8190
PPC_PCFGR308
0XX00000 00000000
0xB07E8192
PPC_PCFGR309
0XX00000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
189
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (40 / 51)
Offset
190
+1
+0
0xB07E8194
PPC_PCFGR310
0XX00000 00000000
0xB07E8196
PPC_PCFGR311
0XX00000 00000000
0xB07E8198
PPC_PCFGR312
0XX00000 00000000
0xB07E819A
PPC_PCFGR313
0XX00000 00000000
0xB07E819C
PPC_PCFGR314
0XX00000 00000000
0xB07E819E
PPC_PCFGR315
0XX00000 00000000
0xB07E81A0
PPC_PCFGR316
0XX00000 00000000
0xB07E81A2
PPC_PCFGR317
0XX00000 00000000
0xB07E81A4
PPC_PCFGR318
0XX00000 00000000
0xB07E81A6
PPC_PCFGR319
0XX00000 00000000
0xB07E81A8
PPC_PCFGR320
0XX00000 00000000
0xB07E81AA
PPC_PCFGR321
0XX00000 00000000
0xB07E81AC
PPC_PCFGR322
0XX00000 00000000
0xB07E81AE
PPC_PCFGR323
0XX00000 00000000
0xB07E81B0
PPC_PCFGR324
0XX00000 00000000
0xB07E81B2
PPC_PCFGR325
0XX00000 00000000
0xB07E81B4
PPC_PCFGR326
0XX00000 00000000
0xB07E81B6
PPC_PCFGR327
0XX00000 00000000
0xB07E81B8
PPC_PCFGR328
0XX00000 00000000
0xB07E81BA
PPC_PCFGR329
0XX00000 00000000
0xB07E81BC
PPC_PCFGR330
0XX00000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (41 / 51)
Offset
+1
+0
0xB07E81BE
PPC_PCFGR331
0XX00000 00000000
0xB07E81C0
PPC_PCFGR332
0XX00000 00000000
0xB07E81C2
PPC_PCFGR333
0XX00000 00000000
0xB07E81C4
PPC_PCFGR334
0XX00000 00000000
0xB07E81C6
PPC_PCFGR335
0XX00000 00000000
0xB07E81C8
PPC_PCFGR336
0XX00000 00000000
0xB07E81CA
PPC_PCFGR337
0XX00000 00000000
0xB07E81CC
PPC_PCFGR338
0XX00000 00000000
0xB07E81CE
PPC_PCFGR339
0XX00000 00000000
0xB07E81D0
PPC_PCFGR340
0XX00000 00000000
0xB07E81D2
PPC_PCFGR341
0XX00000 00000000
0xB07E81D4
PPC_PCFGR342
0XX00000 00000000
0xB07E81D6
PPC_PCFGR343
0XX00000 00000000
0xB07E81D8
PPC_PCFGR344
0XX00000 00000000
0xB07E81DA
PPC_PCFGR345
0XX00000 00000000
0xB07E81DC
PPC_PCFGR346
0XX00000 00000000
0xB07E81DE
PPC_PCFGR347
0XX00000 00000000
0xB07E81E0
PPC_PCFGR348
0XX00000 00000000
0xB07E81E2
PPC_PCFGR349
0XX00000 00000000
0xB07E81E4
PPC_PCFGR350
0XX00000 00000000
0xB07E81E6
PPC_PCFGR351
0XX00000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
191
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (42 / 51)
Offset
192
+1
+0
0xB07E81E8
PPC_PCFGR352
0XX00000 00000000
0xB07E81EA
PPC_PCFGR353
0XX00000 00000000
0xB07E81EC
PPC_PCFGR354
0XX00000 00000000
0xB07E81EE
PPC_PCFGR355
0XX00000 00000000
0xB07E81F0
PPC_PCFGR356
0XX00000 00000000
0xB07E81F2
PPC_PCFGR357
0XX00000 00000000
0xB07E81F4
PPC_PCFGR358
0XX00000 00000000
0xB07E81F6
PPC_PCFGR359
0XX00000 00000000
0xB07E81F8
PPC_PCFGR360
0XX00000 00000000
0xB07E81FA
PPC_PCFGR361
0XX00000 00000000
0xB07E81FC
PPC_PCFGR362
0XX00000 00000000
0xB07E81FE
PPC_PCFGR363
0XX00000 00000000
0xB07E8200B07EFFFE
reserved
XXXXXXXX XXXXXXXX
0xB07F0000
BECU0_CTRL
00000000 00000000
0xB07F0002
BECU0_CTRH
00000000 00000000
0xB07F0004
BECU0_ADDRL
00000000 00000000
0xB07F0006
BECU0_ADDRH
00000000 00000000
0xB07F0008
BECU0_DATALL
00000000 00000000
0xB07F000A
BECU0_DATALH
00000000 00000000
0xB07F000C
BECU0_DATAHL
00000000 00000000
0xB07F000E
BECU0_DATAHH
00000000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (43 / 51)
Offset
+1
+0
0xB07F0010
BECU0_MASTERID
00000000 00000000
0xB07F0012
BECU0_MIDL
XXXXXXXX XXXXXXXX
0xB07F0014
BECU0_MIDH
XXXXXXXX XXXXXXXX
0xB07F0016
reserved
00000000 00000000
0xB07F0018
BECU0_NMIEN
XXXXXXXX 00000001
0xB07F001AB07F7FFE
reserved
XXXXXXXX XXXXXXXX
0xB07F8000
RICFG0_ADC0AN26
00000000 XXXXXXXX
0xB07F8002
RICFG0_ADC0AN27
00000000 XXXXXXXX
0xB07F8004
RICFG0_ADC0AN28
00000000 XXXXXXXX
0xB07F8006
RICFG0_ADC0AN29
00000000 XXXXXXXX
0xB07F8008
RICFG0_ADC0AN30
00000000 XXXXXXXX
0xB07F800A
RICFG0_ADC0AN31
00000000 XXXXXXXX
0xB07F800C
RICFG0_ADC0EDGI
00000000 00000000
0xB07F800E
RICFG0_ADC0EDGIOCU0
XXXXXXXX 00000000
0xB07F8010B07F8014
reserved
XXXXXXXX XXXXXXXX
0xB07F8016
RICFG0_ADC0EDGIOCU4
XXXXXXXX 00000000
0xB07F8018B07F801C
reserved
XXXXXXXX XXXXXXXX
0xB07F801E
RICFG0_ADC0TIMI
XXXXXXXX 00000000
0xB07F8020
RICFG0_ADC0TIMIRLT
XXXXXXXX 00000000
0xB07F8022B07F803C
reserved
XXXXXXXX XXXXXXXX
0xB07F803E
RICFG0_ADC0ZPDEN
XXXXXXXX 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
193
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (44 / 51)
Offset
194
+1
+0
0xB07F8040B07F83FE
reserved
XXXXXXXX 00000000
0xB07F8400
RICFG0_FRT0TEXT
00000000 00000000
0xB07F8402B07F841E
reserved
XXXXXXXX 00000000
0xB07F8420
RICFG0_FRT1TEXT
00000000 00000000
0xB07F8422B07F843E
reserved
XXXXXXXX 00000000
0xB07F8440
RICFG0_FRT2TEXT
00000000 00000000
0xB07F8442B07F845E
reserved
XXXXXXXX 00000000
0xB07F8460
RICFG0_FRT3TEXT
00000000 00000000
0xB07F8462B07F883E
reserved
XXXXXXXX 00000000
0xB07F8840
RICFG0_ICU2IN0
00000000 XXXXXXXX
0xB07F8842
RICFG0_ICU2IN1
00000000 XXXXXXXX
0xB07F8844
RICFG0_ICU2FRTSEL
XXXXXXXX 00000000
0xB07F8846B07F885E
reserved
XXXXXXXX 00000000
0xB07F8860
RICFG0_ICU3IN0
00000000 XXXXXXXX
0xB07F8862
RICFG0_ICU3IN1
00000000 XXXXXXXX
0xB07F8864
RICFG0_ICU3FRTSEL
XXXXXXXX 00000000
0xB07F8866B07F8BFE
reserved
XXXXXXXX 00000000
0xB07F8C00
RICFG0_OCU0OTD0GATE
XXXXXXXX 00000000
0xB07F8C02
RICFG0_OCU0OTD0GM
XXXXXXXX 00000000
0xB07F8C04
RICFG0_OCU0OTD1GATE
XXXXXXXX 00000000
0xB07F8C06
RICFG0_OCU0OTD1GM
XXXXXXXX 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (45 / 51)
Offset
+1
+0
0xB07F8C08B07F8C1E
reserved
XXXXXXXX 00000000
0xB07F8C20
RICFG0_OCU1CMP0EXT
XXXXXXXX 00000000
0xB07F8C22
RICFG0_OCU1FRTSEL
XXXXXXXX 00000000
0xB07F8C24
RICFG0_OCU1OTD0GATE
XXXXXXXX 00000000
0xB07F8C26
RICFG0_OCU1OTD0GM
XXXXXXXX 00000000
0xB07F8C28
RICFG0_OCU1OTD1GATE
XXXXXXXX 00000000
0xB07F8C2A
RICFG0_OCU1OTD1GM
XXXXXXXX 00000000
0xB07F8C2CB07F93FE
reserved
XXXXXXXX 00000000
0xB07F9400
RICFG0_USART0SCKI
00000000 XXXXXXXX
0xB07F9402
RICFG0_USART0SIN
00000000 XXXXXXXX
0xB07F9404B07F9BFE
reserved
XXXXXXXX 00000000
0xB07F9C00
RICFG0_PPG0PPGAGATE
XXXXXXXX 00000000
0xB07F9C02
RICFG0_PPG0PPGAGM
XXXXXXXX 00000000
0xB07F9C04
RICFG0_PPG0PPGBGATE
XXXXXXXX 00000000
0xB07F9C06
RICFG0_PPG0PPGBGM
XXXXXXXX 00000000
0xB07F9C08B07F9C1E
reserved
XXXXXXXX 00000000
0xB07F9C20
RICFG0_PPG1PPGAGATE
XXXXXXXX 00000000
0xB07F9C22
RICFG0_PPG1PPGAGM
XXXXXXXX 00000000
0xB07F9C24
RICFG0_PPG1PPGBGATE
XXXXXXXX 00000000
0xB07F9C26
RICFG0_PPG1PPGBGM
XXXXXXXX 00000000
0xB07F9C28B07F9C3E
reserved
XXXXXXXX 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
195
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (46 / 51)
Offset
196
+1
+0
0xB07F9C40
RICFG0_PPG2PPGAGATE
XXXXXXXX 00000000
0xB07F9C42
RICFG0_PPG2PPGAGM
XXXXXXXX 00000000
0xB07F9C44
RICFG0_PPG2PPGBGATE
XXXXXXXX 00000000
0xB07F9C46
RICFG0_PPG2PPGBGM
XXXXXXXX 00000000
0xB07F9C48B07F9C5E
reserved
XXXXXXXX 00000000
0xB07F9C60
RICFG0_PPG3PPGAGATE
XXXXXXXX 00000000
0xB07F9C62
RICFG0_PPG3PPGAGM
XXXXXXXX 00000000
0xB07F9C64
RICFG0_PPG3PPGBGATE
XXXXXXXX 00000000
0xB07F9C66
RICFG0_PPG3PPGBGM
XXXXXXXX 00000000
0xB07F9C68B07F9C7E
reserved
XXXXXXXX 00000000
0xB07F9C80
RICFG0_PPG4PPGAGATE
XXXXXXXX 00000000
0xB07F9C82
RICFG0_PPG4PPGAGM
XXXXXXXX 00000000
0xB07F9C84
RICFG0_PPG4PPGBGATE
XXXXXXXX 00000000
0xB07F9C86
RICFG0_PPG4PPGBGM
XXXXXXXX 00000000
0xB07F9C88B07F9C9E
reserved
XXXXXXXX 00000000
0xB07F9CA0
RICFG0_PPG5PPGAGATE
XXXXXXXX 00000000
0xB07F9CA2
RICFG0_PPG5PPGAGM
XXXXXXXX 00000000
0xB07F9CA4
RICFG0_PPG5PPGBGATE
XXXXXXXX 00000000
0xB07F9CA6
RICFG0_PPG5PPGBGM
XXXXXXXX 00000000
0xB07F9CA8B07F9CBE
reserved
XXXXXXXX 00000000
0xB07F9CC0
RICFG0_PPG6PPGAGATE
XXXXXXXX 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (47 / 51)
Offset
+1
+0
0xB07F9CC2
RICFG0_PPG6PPGAGM
XXXXXXXX 00000000
0xB07F9CC4
RICFG0_PPG6PPGBGATE
XXXXXXXX 00000000
0xB07F9CC6
RICFG0_PPG6PPGBGM
XXXXXXXX 00000000
0xB07F9CC8B07F9CDE
reserved
XXXXXXXX 00000000
0xB07F9CE0
RICFG0_PPG7PPGAGATE
XXXXXXXX 00000000
0xB07F9CE2
RICFG0_PPG7PPGAGM
XXXXXXXX 00000000
0xB07F9CE4
RICFG0_PPG7PPGBGATE
XXXXXXXX 00000000
0xB07F9CE6
RICFG0_PPG7PPGBGM
XXXXXXXX 00000000
0xB07F9CE8B07F9CFE
reserved
XXXXXXXX 00000000
0xB07F9D00
RICFG0_PPG8PPGAGATE
XXXXXXXX 00000000
0xB07F9D02
RICFG0_PPG8PPGAGM
XXXXXXXX 00000000
0xB07F9D04
RICFG0_PPG8PPGBGATE
XXXXXXXX 00000000
0xB07F9D06
RICFG0_PPG8PPGBGM
XXXXXXXX 00000000
0xB07F9D08B07F9D1E
reserved
XXXXXXXX 00000000
0xB07F9D20
RICFG0_PPG9PPGAGATE
XXXXXXXX 00000000
0xB07F9D22
RICFG0_PPG9PPGAGM
XXXXXXXX 00000000
0xB07F9D24
RICFG0_PPG9PPGBGATE
XXXXXXXX 00000000
0xB07F9D26
RICFG0_PPG9PPGBGM
XXXXXXXX 00000000
0xB07F9D28B07F9D3E
reserved
XXXXXXXX 00000000
0xB07F9D40
RICFG0_PPG10PPGAGATE
XXXXXXXX 00000000
0xB07F9D42
RICFG0_PPG10PPGAGM
XXXXXXXX 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
197
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (48 / 51)
Offset
198
+1
+0
0xB07F9D44
RICFG0_PPG10PPGBGATE
XXXXXXXX 00000000
0xB07F9D46
RICFG0_PPG10PPGBGM
XXXXXXXX 00000000
0xB07F9D48B07F9D5E
reserved
XXXXXXXX 00000000
0xB07F9D60
RICFG0_PPG11PPGAGATE
XXXXXXXX 00000000
0xB07F9D62
RICFG0_PPG11PPGAGM
XXXXXXXX 00000000
0xB07F9D64
RICFG0_PPG11PPGBGATE
XXXXXXXX 00000000
0xB07F9D66
RICFG0_PPG11PPGBGM
XXXXXXXX 00000000
0xB07F9D68B07F9D7E
reserved
XXXXXXXX 00000000
0xB07F9D80
RICFG0_PPG12PPGAGATE
XXXXXXXX 00000000
0xB07F9D82
RICFG0_PPG12PPGAGM
XXXXXXXX 00000000
0xB07F9D84
RICFG0_PPG12PPGBGATE
XXXXXXXX 00000000
0xB07F9D86
RICFG0_PPG12PPGBGM
XXXXXXXX 00000000
0xB07F9D88B07F9D9E
reserved
XXXXXXXX 00000000
0xB07F9DA0
RICFG0_PPG13PPGAGATE
XXXXXXXX 00000000
0xB07F9DA2
RICFG0_PPG13PPGAGM
XXXXXXXX 00000000
0xB07F9DA4
RICFG0_PPG13PPGBGATE
XXXXXXXX 00000000
0xB07F9DA6
RICFG0_PPG13PPGBGM
XXXXXXXX 00000000
0xB07F9DA8B07F9DBE
reserved
XXXXXXXX 00000000
0xB07F9DC0
RICFG0_PPG14PPGAGATE
XXXXXXXX 00000000
0xB07F9DC2
RICFG0_PPG14PPGAGM
XXXXXXXX 00000000
0xB07F9DC4
RICFG0_PPG14PPGBGATE
XXXXXXXX 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (49 / 51)
Offset
+1
+0
0xB07F9DC6
RICFG0_PPG14PPGBGM
XXXXXXXX 00000000
0xB07F9DC8B07F9DDE
reserved
XXXXXXXX 00000000
0xB07F9DE0
RICFG0_PPG15PPGAGATE
XXXXXXXX 00000000
0xB07F9DE2
RICFG0_PPG15PPGAGM
XXXXXXXX 00000000
0xB07F9DE4
RICFG0_PPG15PPGBGATE
XXXXXXXX 00000000
0xB07F9DE6
RICFG0_PPG15PPGBGM
XXXXXXXX 00000000
0xB07F9DE8B07FA3FE
reserved
XXXXXXXX 00000000
0xB07FA400
RICFG0_PPGGRP0ETRG0
XXXXXXXX 00000000
0xB07FA402
RICFG0_PPGGRP0ETRG1
XXXXXXXX 00000000
0xB07FA404
RICFG0_PPGGRP0ETRG2
XXXXXXXX 00000000
0xB07FA406
RICFG0_PPGGRP0ETRG3
XXXXXXXX 00000000
0xB07FA408
RICFG0_PPGGRP0RLTTRG1
XXXXXXXX 00000000
0xB07FA40AB07FA41E
reserved
XXXXXXXX 00000000
0xB07FA420
RICFG0_PPGGRP1ETRG0
XXXXXXXX 00000000
0xB07FA422
RICFG0_PPGGRP1ETRG1
XXXXXXXX 00000000
0xB07FA424
RICFG0_PPGGRP1ETRG2
XXXXXXXX 00000000
0xB07FA426
RICFG0_PPGGRP1ETRG3
XXXXXXXX 00000000
0xB07FA428
RICFG0_PPGGRP1RLTTRG1
XXXXXXXX 00000000
0xB07FA42AB07FA43E
reserved
XXXXXXXX 00000000
0xB07FA440
RICFG0_PPGGRP2ETRG0
XXXXXXXX 00000000
0xB07FA442
RICFG0_PPGGRP2ETRG1
XXXXXXXX 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
199
Data
Shee t
Table 5-5 Memory layout of the PERI0_RBUS registers (50 / 51)
Offset
200
+1
+0
0xB07FA444
RICFG0_PPGGRP2ETRG2
XXXXXXXX 00000000
0xB07FA446
RICFG0_PPGGRP2ETRG3
XXXXXXXX 00000000
0xB07FA448
RICFG0_PPGGRP2RLTTRG1
XXXXXXXX 00000000
0xB07FA44AB07FA45E
reserved
XXXXXXXX 00000000
0xB07FA460
RICFG0_PPGGRP3ETRG0
XXXXXXXX 00000000
0xB07FA462
RICFG0_PPGGRP3ETRG1
XXXXXXXX 00000000
0xB07FA464
RICFG0_PPGGRP3ETRG2
XXXXXXXX 00000000
0xB07FA466
RICFG0_PPGGRP3ETRG3
XXXXXXXX 00000000
0xB07FA468
RICFG0_PPGGRP3RLTTRG1
XXXXXXXX 00000000
0xB07FA46AB07FFC02
reserved
XXXXXXXX XXXXXXXX
0xB07FFC04
BSU0_BTSTL
00000000 00000000
0xB07FFC06
BSU0_BTSTH
00000000 00000000
0xB07FFC08B07FFC0E
reserved
XXXXXXXX XXXXXXXX
0xB07FFC10
BSU0_PEN0L
XXXXXXXX 00000000
0xB07FFC12
reserved
XXXXXXXX XXXXXXXX
0xB07FFC14
BSU0_PEN1L
00000000 00000000
0xB07FFC16
reserved
XXXXXXXX XXXXXXXX
0xB07FFC18
BSU0_PEN2L
00000000 00000000
0xB07FFC1A
reserved
XXXXXXXX XXXXXXXX
0xB07FFC1C
BSU0_PEN3L
00000000 00000000
0xB07FFC1E
reserved
XXXXXXXX XXXXXXXX
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-5 Memory layout of the PERI0_RBUS registers (51 / 51)
Offset
+1
+0
0xB07FFC20
BSU0_PEN4L
XXXXXXXX 00000000
0xB07FFC22
reserved
XXXXXXXX XXXXXXXX
0xB07FFC24
BSU0_PEN5L
XXXXXXXX 00000000
0xB07FFC26
reserved
XXXXXXXX XXXXXXXX
0xB07FFC28
BSU0_PEN6L
XXXXXXXX 00000000
0xB07FFC2A
reserved
XXXXXXXX XXXXXXXX
0xB07FFC2C
BSU0_PEN7L
00000000 00000000
0xB07FFC2E
BSU0_PEN7H
00000000 00000000
0xB07FFC30
BSU0_PEN8L
00000000 00000000
0xB07FFC32
BSU0_PEN8H
00000000 00000000
0xB07FFC34
BSU0_PEN9L
00000000 00000000
0xB07FFC36
BSU0_PEN9H
XXXXXXXX 00000000
0xB07FFC38B07FFC3A
reserved
XXXXXXXX XXXXXXXX
0xB07FFC3C
BSU0_PEN11L
XXXXXXXX 00000000
0xB07FFC3EB07FFFFE
reserved
XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
201
Data
Shee t
Table 5-6 Memory layout of PERI1_RBUS registers (1 / 25)
Offset
0xB0800000
0xB0800002
+0
SG0_CR0
00000000 00000000
SG0_CR1
00000000
reserved
XXXXXXXX
0xB0800004
SG0_ECRL
00000000 00000000
0xB0800006
SG0_FRL
00000000 00000000
0xB0800008
SG0_ARL
00000000 00000000
0xB080000A
SG0_AR
00000000 00000000
0xB080000C
SG0_TARL
00000000 00000000
0xB080000E
SG0_TCRLIDRL
00000000 00000000
0xB0800010
202
+1
SG0_NRL
00000000
reserved
XXXXXXXX
0xB0800012
SG0_DER
00000000 00000000
0xB0800014
SG0_DMAR
00000000 00000000
0xB0800016B0807FFE
reserved
XXXXXXXX XXXXXXXX
0xB0808000
CAN0_CTRLR
XXXXXXXX 000X0001
0xB0808002
CAN0_STATR
XXXXXXXX 00000000
0xB0808004
CAN0_ERRCNT
00000000 00000000
0xB0808006
CAN0_BTR
X0100011 00000001
0xB0808008
CAN0_INTR
00000000 00000000
0xB080800A
CAN0_TESTR
XXXXXXXX 000000XX
0xB080800C
CAN0_BRPER
XXXXXXXX XXXX0000
0xB080800E
reserved
XXXXXXXX XXXXXXXX
0xB0808010
CAN0_IF1CREQ
0XXXXXXX 00000001
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-6 Memory layout of PERI1_RBUS registers (2 / 25)
Offset
+1
+0
0xB0808012
CAN0_IF1CMSK
XXXXXXXX 00000000
0xB0808014
CAN0_IF1MSK1
11111111 11111111
0xB0808016
CAN0_IF1MSK2
11X11111 11111111
0xB0808018
CAN0_IF1ARB1
00000000 00000000
0xB080801A
CAN0_IF1ARB2
00000000 00000000
0xB080801C
CAN0_IF1MCTR
00000000 0XXX0000
0xB080801E
reserved
XXXXXXXX XXXXXXXX
0xB0808020
CAN0_IF1DTA1
00000000 00000000
0xB0808022
CAN0_IF1DTA2
00000000 00000000
0xB0808024
CAN0_IF1DTB1
00000000 00000000
0xB0808026
CAN0_IF1DTB2
00000000 00000000
0xB0808028B080803E
reserved
XXXXXXXX XXXXXXXX
0xB0808040
CAN0_IF2CREQ
0XXXXXXX 00000001
0xB0808042
CAN0_IF2CMSK
XXXXXXXX 00000000
0xB0808044
CAN0_IF2MSK1
11111111 11111111
0xB0808046
CAN0_IF2MSK2
11X11111 11111111
0xB0808048
CAN0_IF2ARB1
00000000 00000000
0xB080804A
CAN0_IF2ARB2
00000000 00000000
0xB080804C
CAN0_IF2MCTR
00000000 00000000
0xB080804E
reserved
XXXXXXXX XXXXXXXX
0xB0808050
CAN0_IF2DTA1
00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
203
Data
Shee t
Table 5-6 Memory layout of PERI1_RBUS registers (3 / 25)
Offset
204
+1
+0
0xB0808052
CAN0_IF2DTA2
00000000 00000000
0xB0808054
CAN0_IF2DTB1
00000000 00000000
0xB0808056
CAN0_IF2DTB2
00000000 00000000
0xB0808058B080807E
reserved
XXXXXXXX XXXXXXXX
0xB0808080
CAN0_TREQR1
00000000 00000000
0xB0808082
CAN0_TREQR2
00000000 00000000
0xB0808084
CAN0_TREQR3
00000000 00000000
0xB0808086
CAN0_TREQR4
00000000 00000000
0xB0808088B080808E
reserved
XXXXXXXX XXXXXXXX
0xB0808090
CAN0_NEWDT1
00000000 00000000
0xB0808092
CAN0_NEWDT2
00000000 00000000
0xB0808094
CAN0_NEWDT3
00000000 00000000
0xB0808096
CAN0_NEWDT4
00000000 00000000
0xB0808098B080809E
reserved
XXXXXXXX XXXXXXXX
0xB08080A0
CAN0_INTPND1
00000000 00000000
0xB08080A2
CAN0_INTPND2
00000000 00000000
0xB08080A4
CAN0_INTPND3
00000000 00000000
0xB08080A6
CAN0_INTPND4
00000000 00000000
0xB08080A8B08080AE
reserved
XXXXXXXX XXXXXXXX
0xB08080B0
CAN0_MSGVAL1
00000000 00000000
0xB08080B2
CAN0_MSGVAL2
00000000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-6 Memory layout of PERI1_RBUS registers (4 / 25)
Offset
+1
+0
0xB08080B4
CAN0_MSGVAL3
00000000 00000000
0xB08080B6
CAN0_MSGVAL4
00000000 00000000
0xB08080B8B08080CC
reserved
XXXXXXXX XXXXXXXX
0xB08080CE
CAN0_COER
XXXXXXX0
reserved
00000000
0xB08080D0
CAN0_DEBUG
XXXXXXXX 00000000
0xB08080D2B08083FE
reserved
XXXXXXXX XXXXXXXX
0xB0808400
CAN1_CTRLR
XXXXXXXX 000X0001
0xB0808402
CAN1_STATR
XXXXXXXX 00000000
0xB0808404
CAN1_ERRCNT
00000000 00000000
0xB0808406
CAN1_BTR
X0100011 00000001
0xB0808408
CAN1_INTR
00000000 00000000
0xB080840A
CAN1_TESTR
XXXXXXXX 000000XX
0xB080840C
CAN1_BRPER
XXXXXXXX XXXX0000
0xB080840E
reserved
XXXXXXXX XXXXXXXX
0xB0808410
CAN1_IF1CREQ
0XXXXXXX 00000001
0xB0808412
CAN1_IF1CMSK
XXXXXXXX 00000000
0xB0808414
CAN1_IF1MSK1
11111111 11111111
0xB0808416
CAN1_IF1MSK2
11X11111 11111111
0xB0808418
CAN1_IF1ARB1
00000000 00000000
0xB080841A
CAN1_IF1ARB2
00000000 00000000
0xB080841C
CAN1_IF1MCTR
00000000 0XXX0000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
205
Data
Shee t
Table 5-6 Memory layout of PERI1_RBUS registers (5 / 25)
Offset
206
+1
+0
0xB080841E
reserved
XXXXXXXX XXXXXXXX
0xB0808420
CAN1_IF1DTA1
00000000 00000000
0xB0808422
CAN1_IF1DTA2
00000000 00000000
0xB0808424
CAN1_IF1DTB1
00000000 00000000
0xB0808426
CAN1_IF1DTB2
00000000 00000000
0xB0808428B080843E
reserved
XXXXXXXX XXXXXXXX
0xB0808440
CAN1_IF2CREQ
0XXXXXXX 00000001
0xB0808442
CAN1_IF2CMSK
XXXXXXXX 00000000
0xB0808444
CAN1_IF2MSK1
11111111 11111111
0xB0808446
CAN1_IF2MSK2
11X11111 11111111
0xB0808448
CAN1_IF2ARB1
00000000 00000000
0xB080844A
CAN1_IF2ARB2
00000000 00000000
0xB080844C
CAN1_IF2MCTR
00000000 00000000
0xB080844E
reserved
XXXXXXXX XXXXXXXX
0xB0808450
CAN1_IF2DTA1
00000000 00000000
0xB0808452
CAN1_IF2DTA2
00000000 00000000
0xB0808454
CAN1_IF2DTB1
00000000 00000000
0xB0808456
CAN1_IF2DTB2
00000000 00000000
0xB0808458B080847E
reserved
XXXXXXXX XXXXXXXX
0xB0808480
CAN1_TREQR1
00000000 00000000
0xB0808482
CAN1_TREQR2
00000000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-6 Memory layout of PERI1_RBUS registers (6 / 25)
Offset
+1
+0
0xB0808484
CAN1_TREQR3
00000000 00000000
0xB0808486
CAN1_TREQR4
00000000 00000000
0xB0808488B080848E
reserved
XXXXXXXX XXXXXXXX
0xB0808490
CAN1_NEWDT1
00000000 00000000
0xB0808492
CAN1_NEWDT2
00000000 00000000
0xB0808494
CAN1_NEWDT3
00000000 00000000
0xB0808496
CAN1_NEWDT4
00000000 00000000
0xB0808498B080849E
reserved
XXXXXXXX XXXXXXXX
0xB08084A0
CAN1_INTPND1
00000000 00000000
0xB08084A2
CAN1_INTPND2
00000000 00000000
0xB08084A4
CAN1_INTPND3
00000000 00000000
0xB08084A6
CAN1_INTPND4
00000000 00000000
0xB08084A8B08084AE
reserved
XXXXXXXX XXXXXXXX
0xB08084B0
CAN1_MSGVAL1
00000000 00000000
0xB08084B2
CAN1_MSGVAL2
00000000 00000000
0xB08084B4
CAN1_MSGVAL3
00000000 00000000
0xB08084B6
CAN1_MSGVAL4
00000000 00000000
0xB08084B8B08084CC
reserved
XXXXXXXX XXXXXXXX
0xB08084CE
reserved
00000000
CAN1_COER
XXXXXXX0
0xB08084D0
CAN1_DEBUG
XXXXXXXX 00000000
0xB08084D2B0817FFE
reserved
XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
207
Data
Shee t
Table 5-6 Memory layout of PERI1_RBUS registers (7 / 25)
Offset
+0
0xB0818000
FRT16_TCDT
00000000 00000000
0xB0818002
FRT16_CPCLRB
11111111 11111111
0xB0818004
FRT16_CPCLR
11111111 11111111
0xB0818006
FRT16_TCCS
00000000 00000000
0xB0818008
FRT16_TSTPTCLK
01000000 00000000
0xB081800A
FRT16_ETCCS
00000000 00000000
0xB081800C
FRT16_CIMSZIMS
00000000 00000000
0xB081800E
reserved
XXXXXXXX
FRT16_DMACFG
00000000
0xB0818010B08183FE
reserved
XXXXXXXX XXXXXXXX
0xB0818400
FRT17_TCDT
00000000 00000000
0xB0818402
FRT17_CPCLRB
11111111 11111111
0xB0818404
FRT17_CPCLR
11111111 11111111
0xB0818406
FRT17_TCCS
00000000 00000000
0xB0818408
FRT17_TSTPTCLK
01000000 00000000
0xB081840A
FRT17_ETCCS
00000000 00000000
0xB081840C
FRT17_CIMSZIMS
00000000 00000000
0xB081840E
208
+1
reserved
XXXXXXXX
FRT17_DMACFG
00000000
0xB0818410B08187FE
reserved
XXXXXXXX XXXXXXXX
0xB0818800
FRT18_TCDT
00000000 00000000
0xB0818802
FRT18_CPCLRB
11111111 11111111
0xB0818804
FRT18_CPCLR
11111111 11111111
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-6 Memory layout of PERI1_RBUS registers (8 / 25)
Offset
+1
+0
0xB0818806
FRT18_TCCS
00000000 00000000
0xB0818808
FRT18_TSTPTCLK
01000000 00000000
0xB081880A
FRT18_ETCCS
00000000 00000000
0xB081880C
FRT18_CIMSZIMS
00000000 00000000
0xB081880E
FRT18_DMACFG
00000000
reserved
XXXXXXXX
0xB0818810B0818BFE
reserved
XXXXXXXX XXXXXXXX
0xB0818C00
FRT19_TCDT
00000000 00000000
0xB0818C02
FRT19_CPCLRB
11111111 11111111
0xB0818C04
FRT19_CPCLR
11111111 11111111
0xB0818C06
FRT19_TCCS
00000000 00000000
0xB0818C08
FRT19_TSTPTCLK
01000000 00000000
0xB0818C0A
FRT19_ETCCS
00000000 00000000
0xB0818C0C
FRT19_CIMSZIMS
00000000 00000000
0xB0818C0E
reserved
XXXXXXXX
FRT19_DMACFG
00000000
0xB0818C10B08207FE
reserved
XXXXXXXX XXXXXXXX
0xB0820800
ICU18_IPC0
00000000 00000000
0xB0820802
ICU18_IPC1
00000000 00000000
0xB0820804
ICU18_ICC01
00000000 00000000
0xB0820806
ICU18_ICEICS01
00000000 00000000
0xB0820808
0xB082080AB0820BFE
January 30, 2015, MB9EF226_DS707-00004-2v1-E
ICU18_DEBUG01
00000000
ICU18_DMACFG01
00000000
reserved
XXXXXXXX XXXXXXXX
209
Data
Shee t
Table 5-6 Memory layout of PERI1_RBUS registers (9 / 25)
Offset
+0
0xB0820C00
ICU19_IPC0
00000000 00000000
0xB0820C02
ICU19_IPC1
00000000 00000000
0xB0820C04
ICU19_ICC01
00000000 00000000
0xB0820C06
ICU19_ICEICS01
00000000 00000000
0xB0820C08
ICU19_DEBUG01
00000000
ICU19_DMACFG01
00000000
0xB0820C0AB0827FFE
reserved
XXXXXXXX XXXXXXXX
0xB0828000
OCU16_OCCP0
00000000 00000000
0xB0828002
OCU16_OCCP1
00000000 00000000
0xB0828004
OCU16_OCCPB0
00000000 00000000
0xB0828006
OCU16_OCCPB1
00000000 00000000
0xB0828008
OCU16_OCCPBD0
00000000 00000000
0xB082800A
OCU16_OCCPBD1
00000000 00000000
0xB082800C
OCU16_OCS01
00000000 00000000
0xB082800E
OCU16_OCSC01
00000000 00000000
0xB0828010
OCU16_OCSS01
00000000 00000000
0xB0828012
reserved
XXXXXXXX
OCU16_OSR01
00000000
0xB0828014
reserved
XXXXXXXX
OCU16_OSCR01
00000000
0xB0828016
210
+1
OCU16_EOCS01
00000000 00000000
0xB0828018
OCU16_EOCSSH01
00000000
reserved
XXXXXXXX
0xB082801A
OCU16_EOCSCH01
00000000
reserved
XXXXXXXX
0xB082801C
OCU16_DEBUG01
00000000
OCU16_DMACFG01
00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-6 Memory layout of PERI1_RBUS registers (10 / 25)
Offset
+1
+0
0xB082801E
OCU16_OCMCR01
00000000
reserved
XXXXXXXX
0xB0828020B08283FE
reserved
XXXXXXXX XXXXXXXX
0xB0828400
OCU17_OCCP0
00000000 00000000
0xB0828402
OCU17_OCCP1
00000000 00000000
0xB0828404
OCU17_OCCPB0
00000000 00000000
0xB0828406
OCU17_OCCPB1
00000000 00000000
0xB0828408
OCU17_OCCPBD0
00000000 00000000
0xB082840A
OCU17_OCCPBD1
00000000 00000000
0xB082840C
OCU17_OCS01
00000000 00000000
0xB082840E
OCU17_OCSC01
00000000 00000000
0xB0828410
OCU17_OCSS01
00000000 00000000
0xB0828412
reserved
XXXXXXXX
OCU17_OSR01
00000000
0xB0828414
reserved
XXXXXXXX
OCU17_OSCR01
00000000
0xB0828416
OCU17_EOCS01
00000000 00000000
0xB0828418
OCU17_EOCSSH01
00000000
reserved
XXXXXXXX
0xB082841A
OCU17_EOCSCH01
00000000
reserved
XXXXXXXX
0xB082841C
OCU17_DEBUG01
00000000
OCU17_DMACFG01
00000000
0xB082841E
OCU17_OCMCR01
00000000
reserved
XXXXXXXX
0xB0828420B0837FFE
reserved
XXXXXXXX XXXXXXXX
0xB0838000
USART6_SCR
00000000
USART6_SMR
00000000
0xB0838002
USART6_SCSR
00000000
USART6_SMSR
00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
211
Data
Shee t
Table 5-6 Memory layout of PERI1_RBUS registers (11 / 25)
212
Offset
+1
+0
0xB0838004
USART6_SCCR
00000000
reserved
XXXXXXXX
0xB0838006
USART6_SSR
00001000
USART6_TDR
00000000
0xB0838008
USART6_SSSR
00000000
USART6_RDR
00000000
0xB083800A
USART6_SSCR
00000000
reserved
XXXXXXXX
0xB083800C
USART6_ESCR
00000100
USART6_ECCR
000000XX
0xB083800E
USART6_ESCSR
00000000
USART6_ECCSR
00000000
0xB0838010
USART6_ESCCR
00000000
USART6_ECCCR
00000000
0xB0838012
USART6_EIER
00000000
USART6_ESIR
000010X0
0xB0838014
USART6_EIESR
00000000
USART6_ESISR
00000000
0xB0838016
USART6_EIECR
00000000
USART6_ESICR
00000000
0xB0838018
USART6_EFERH
00000000
USART6_EFERL
00000000
0xB083801A
USART6_TFCR
00000000
USART6_RFCR
00000000
0xB083801C
USART6_TFCSR
00000000
USART6_RFCSR
00000000
0xB083801E
USART6_TFCCR
00000000
USART6_RFCCR
00000000
0xB0838020
USART6_TFSR
00000000
USART6_RFSR
00000000
0xB0838022
USART6_ESR
00000000
USART6_CSCR
00000000
0xB0838024
reserved
XXXXXXXX
USART6_CSCSR
00000000
0xB0838026
USART6_ESCLR
00000000
USART6_CSCCR
00000000
0xB0838028
USART6_BGRLM
00000000
USART6_BGRLL
00000000
0xB083802A
reserved
XXXXXXXX
USART6_BGRLH
00000000
0xB083802C
USART6_BGRM
00000000
USART6_BGRL
00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-6 Memory layout of PERI1_RBUS registers (12 / 25)
Offset
+1
+0
0xB083802E
reserved
XXXXXXXX
USART6_BGRH
00000000
0xB0838030
USART6_SRXDR
00000000
USART6_STXDR
00000000
0xB0838032
USART6_SRXDSR
00000000
USART6_STXDSR
00000000
0xB0838034
USART6_SRXDCR
00000000
USART6_STXDCR
00000000
0xB0838036
read0
00000000
read0
00000000
0xB0838038
reserved
XXXXXXXX
read0
00000000
0xB083803A
reserved
XXXXXXXX
USART6_FIDR
00000000
0xB083803C
reserved
XXXXXXXX
USART6_DEBUG
00000000
0xB083803EB0847FFE
reserved
XXXXXXXX XXXXXXXX
0xB0848000
PPG64_PCN
00000000 00000000
0xB0848002
PPG64_SWTRIG
00000000
PPG64_IRQCLR
00000000
0xB0848004
PPG64_CNTEN
00000000
PPG64_OE
00000000
0xB0848006
PPG64_RMPCFG
00000000
PPG64_OPTMSK
00000000
0xB0848008
PPG64_TRIGCLR
00000000
PPG64_STRD
00000000
0xB084800A
PPG64_EPCN1
00000000 00000000
0xB084800C
PPG64_EPCN2
00000000 00000000
0xB084800E
PPG64_GCN3
00000000
PPG64_GCN1
00000000
0xB0848010
PPG64_GCN5
00000000
PPG64_GCN4
00000110
0xB0848012
PPG64_PCSR
XXXXXXXX XXXXXXXX
0xB0848014
PPG64_PDUT
XXXXXXXX XXXXXXXX
0xB0848016
PPG64_PTMR
11111111 11111111
January 30, 2015, MB9EF226_DS707-00004-2v1-E
213
Data
Shee t
Table 5-6 Memory layout of PERI1_RBUS registers (13 / 25)
Offset
+0
0xB0848018
PPG64_PSDR
00000000 00000000
0xB084801A
PPG64_PTPC
00000000 00000000
0xB084801C
PPG64_PEDR
00000000 00000000
0xB084801E
PPG64_DEBUG
00000000
PPG64_DMACFG
00000000
0xB0848020B08483FE
reserved
XXXXXXXX XXXXXXXX
0xB0848400
PPG65_PCN
00000000 00000000
0xB0848402
PPG65_SWTRIG
00000000
PPG65_IRQCLR
00000000
0xB0848404
PPG65_CNTEN
00000000
PPG65_OE
00000000
0xB0848406
PPG65_RMPCFG
00000000
PPG65_OPTMSK
00000000
0xB0848408
PPG65_TRIGCLR
00000000
PPG65_STRD
00000000
0xB084840A
PPG65_EPCN1
00000000 00000000
0xB084840C
PPG65_EPCN2
00000000 00000000
0xB084840E
PPG65_GCN3
00000000
PPG65_GCN1
00000000
0xB0848410
PPG65_GCN5
00000000
PPG65_GCN4
00000110
0xB0848412
PPG65_PCSR
XXXXXXXX XXXXXXXX
0xB0848414
PPG65_PDUT
XXXXXXXX XXXXXXXX
0xB0848416
PPG65_PTMR
11111111 11111111
0xB0848418
PPG65_PSDR
00000000 00000000
0xB084841A
PPG65_PTPC
00000000 00000000
0xB084841C
PPG65_PEDR
00000000 00000000
0xB084841E
214
+1
PPG65_DEBUG
00000000
PPG65_DMACFG
00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-6 Memory layout of PERI1_RBUS registers (14 / 25)
Offset
+1
+0
0xB0848420B08487FE
reserved
XXXXXXXX XXXXXXXX
0xB0848800
PPG66_PCN
00000000 00000000
0xB0848802
PPG66_SWTRIG
00000000
PPG66_IRQCLR
00000000
0xB0848804
PPG66_CNTEN
00000000
PPG66_OE
00000000
0xB0848806
PPG66_RMPCFG
00000000
PPG66_OPTMSK
00000000
0xB0848808
PPG66_TRIGCLR
00000000
PPG66_STRD
00000000
0xB084880A
PPG66_EPCN1
00000000 00000000
0xB084880C
PPG66_EPCN2
00000000 00000000
0xB084880E
PPG66_GCN3
00000000
PPG66_GCN1
00000000
0xB0848810
PPG66_GCN5
00000000
PPG66_GCN4
00000110
0xB0848812
PPG66_PCSR
XXXXXXXX XXXXXXXX
0xB0848814
PPG66_PDUT
XXXXXXXX XXXXXXXX
0xB0848816
PPG66_PTMR
11111111 11111111
0xB0848818
PPG66_PSDR
00000000 00000000
0xB084881A
PPG66_PTPC
00000000 00000000
0xB084881C
PPG66_PEDR
00000000 00000000
0xB084881E
PPG66_DEBUG
00000000
PPG66_DMACFG
00000000
0xB0848820B0848BFE
reserved
XXXXXXXX XXXXXXXX
0xB0848C00
PPG67_PCN
00000000 00000000
0xB0848C02
PPG67_SWTRIG
00000000
PPG67_IRQCLR
00000000
0xB0848C04
PPG67_CNTEN
00000000
PPG67_OE
00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
215
Data
Shee t
Table 5-6 Memory layout of PERI1_RBUS registers (15 / 25)
Offset
+1
+0
0xB0848C06
PPG67_RMPCFG
00000000
PPG67_OPTMSK
00000000
0xB0848C08
PPG67_TRIGCLR
00000000
PPG67_STRD
00000000
0xB0848C0A
PPG67_EPCN1
00000000 00000000
0xB0848C0C
PPG67_EPCN2
00000000 00000000
0xB0848C0E
PPG67_GCN3
00000000
PPG67_GCN1
00000000
0xB0848C10
PPG67_GCN5
00000000
PPG67_GCN4
00000110
0xB0848C12
PPG67_PCSR
XXXXXXXX XXXXXXXX
0xB0848C14
PPG67_PDUT
XXXXXXXX XXXXXXXX
0xB0848C16
PPG67_PTMR
11111111 11111111
0xB0848C18
PPG67_PSDR
00000000 00000000
0xB0848C1A
PPG67_PTPC
00000000 00000000
0xB0848C1C
PPG67_PEDR
00000000 00000000
0xB0848C1E
216
PPG67_DEBUG
00000000
PPG67_DMACFG
00000000
0xB0848C20B0848FFE
reserved
XXXXXXXX XXXXXXXX
0xB0849000
PPG68_PCN
00000000 00000000
0xB0849002
PPG68_SWTRIG
00000000
PPG68_IRQCLR
00000000
0xB0849004
PPG68_CNTEN
00000000
PPG68_OE
00000000
0xB0849006
PPG68_RMPCFG
00000000
PPG68_OPTMSK
00000000
0xB0849008
PPG68_TRIGCLR
00000000
PPG68_STRD
00000000
0xB084900A
PPG68_EPCN1
00000000 00000000
0xB084900C
PPG68_EPCN2
00000000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-6 Memory layout of PERI1_RBUS registers (16 / 25)
Offset
+1
+0
0xB084900E
PPG68_GCN3
00000000
PPG68_GCN1
00000000
0xB0849010
PPG68_GCN5
00000000
PPG68_GCN4
00000110
0xB0849012
PPG68_PCSR
XXXXXXXX XXXXXXXX
0xB0849014
PPG68_PDUT
XXXXXXXX XXXXXXXX
0xB0849016
PPG68_PTMR
11111111 11111111
0xB0849018
PPG68_PSDR
00000000 00000000
0xB084901A
PPG68_PTPC
00000000 00000000
0xB084901C
PPG68_PEDR
00000000 00000000
0xB084901E
PPG68_DEBUG
00000000
PPG68_DMACFG
00000000
0xB0849020B08493FE
reserved
XXXXXXXX XXXXXXXX
0xB0849400
PPG69_PCN
00000000 00000000
0xB0849402
PPG69_SWTRIG
00000000
PPG69_IRQCLR
00000000
0xB0849404
PPG69_CNTEN
00000000
PPG69_OE
00000000
0xB0849406
PPG69_RMPCFG
00000000
PPG69_OPTMSK
00000000
0xB0849408
PPG69_TRIGCLR
00000000
PPG69_STRD
00000000
0xB084940A
PPG69_EPCN1
00000000 00000000
0xB084940C
PPG69_EPCN2
00000000 00000000
0xB084940E
PPG69_GCN3
00000000
PPG69_GCN1
00000000
0xB0849410
PPG69_GCN5
00000000
PPG69_GCN4
00000110
0xB0849412
PPG69_PCSR
XXXXXXXX XXXXXXXX
0xB0849414
PPG69_PDUT
XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
217
Data
Shee t
Table 5-6 Memory layout of PERI1_RBUS registers (17 / 25)
Offset
+0
0xB0849416
PPG69_PTMR
11111111 11111111
0xB0849418
PPG69_PSDR
00000000 00000000
0xB084941A
PPG69_PTPC
00000000 00000000
0xB084941C
PPG69_PEDR
00000000 00000000
0xB084941E
218
+1
PPG69_DEBUG
00000000
PPG69_DMACFG
00000000
0xB0849420B08497FE
reserved
XXXXXXXX XXXXXXXX
0xB0849800
PPG70_PCN
00000000 00000000
0xB0849802
PPG70_SWTRIG
00000000
PPG70_IRQCLR
00000000
0xB0849804
PPG70_CNTEN
00000000
PPG70_OE
00000000
0xB0849806
PPG70_RMPCFG
00000000
PPG70_OPTMSK
00000000
0xB0849808
PPG70_TRIGCLR
00000000
PPG70_STRD
00000000
0xB084980A
PPG70_EPCN1
00000000 00000000
0xB084980C
PPG70_EPCN2
00000000 00000000
0xB084980E
PPG70_GCN3
00000000
PPG70_GCN1
00000000
0xB0849810
PPG70_GCN5
00000000
PPG70_GCN4
00000110
0xB0849812
PPG70_PCSR
XXXXXXXX XXXXXXXX
0xB0849814
PPG70_PDUT
XXXXXXXX XXXXXXXX
0xB0849816
PPG70_PTMR
11111111 11111111
0xB0849818
PPG70_PSDR
00000000 00000000
0xB084981A
PPG70_PTPC
00000000 00000000
0xB084981C
PPG70_PEDR
00000000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-6 Memory layout of PERI1_RBUS registers (18 / 25)
Offset
+1
+0
0xB084981E
PPG70_DEBUG
00000000
PPG70_DMACFG
00000000
0xB0849820B0849BFE
reserved
XXXXXXXX XXXXXXXX
0xB0849C00
PPG71_PCN
00000000 00000000
0xB0849C02
PPG71_SWTRIG
00000000
PPG71_IRQCLR
00000000
0xB0849C04
PPG71_CNTEN
00000000
PPG71_OE
00000000
0xB0849C06
PPG71_RMPCFG
00000000
PPG71_OPTMSK
00000000
0xB0849C08
PPG71_TRIGCLR
00000000
PPG71_STRD
00000000
0xB0849C0A
PPG71_EPCN1
00000000 00000000
0xB0849C0C
PPG71_EPCN2
00000000 00000000
0xB0849C0E
PPG71_GCN3
00000000
PPG71_GCN1
00000000
0xB0849C10
PPG71_GCN5
00000000
PPG71_GCN4
00000110
0xB0849C12
PPG71_PCSR
XXXXXXXX XXXXXXXX
0xB0849C14
PPG71_PDUT
XXXXXXXX XXXXXXXX
0xB0849C16
PPG71_PTMR
11111111 11111111
0xB0849C18
PPG71_PSDR
00000000 00000000
0xB0849C1A
PPG71_PTPC
00000000 00000000
0xB0849C1C
PPG71_PEDR
00000000 00000000
0xB0849C1E
0xB0849C20B0857FFE
0xB0858000
0xB0858002B08583FE
January 30, 2015, MB9EF226_DS707-00004-2v1-E
PPG71_DEBUG
00000000
PPG71_DMACFG
00000000
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX
PPGGRP16_GCTRL
00000000
reserved
XXXXXXXX XXXXXXXX
219
Data
Shee t
Table 5-6 Memory layout of PERI1_RBUS registers (19 / 25)
Offset
+1
+0
0xB0858400
reserved
XXXXXXXX
PPGGRP17_GCTRL
00000000
0xB0858402B085BFFE
0xB085C000
220
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX
PPGGLC1_GCNR
00000000
0xB085C002B08EFFFE
reserved
XXXXXXXX XXXXXXXX
0xB08F0000
BECU1_CTRL
00000000 00000000
0xB08F0002
BECU1_CTRH
00000000 00000000
0xB08F0004
BECU1_ADDRL
00000000 00000000
0xB08F0006
BECU1_ADDRH
00000000 00000000
0xB08F0008
BECU1_DATALL
00000000 00000000
0xB08F000A
BECU1_DATALH
00000000 00000000
0xB08F000C
BECU1_DATAHL
00000000 00000000
0xB08F000E
BECU1_DATAHH
00000000 00000000
0xB08F0010
BECU1_MASTERID
00000000 00000000
0xB08F0012
BECU1_MIDL
XXXXXXXX XXXXXXXX
0xB08F0014
BECU1_MIDH
XXXXXXXX XXXXXXXX
0xB08F0016
reserved
00000000 00000000
0xB08F0018
BECU1_NMIEN
XXXXXXXX 00000001
0xB08F001AB08F83FE
reserved
XXXXXXXX XXXXXXXX
0xB08F8400
RICFG1_CAN0RX
00000000 00000000
0xB08F8402B08F841E
reserved
XXXXXXXX 00000000
0xB08F8420
RICFG1_CAN1RX
00000000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-6 Memory layout of PERI1_RBUS registers (20 / 25)
Offset
+1
+0
0xB08F8422B08F8BFE
reserved
XXXXXXXX 00000000
0xB08F8C00
RICFG1_FRT16TEXT
00000000 00000000
0xB08F8C02B08F8C1E
reserved
XXXXXXXX 00000000
0xB08F8C20
RICFG1_FRT17TEXT
00000000 00000000
0xB08F8C22B08F8C3E
reserved
XXXXXXXX 00000000
0xB08F8C40
RICFG1_FRT18TEXT
00000000 00000000
0xB08F8C42B08F8C5E
reserved
XXXXXXXX 00000000
0xB08F8C60
RICFG1_FRT19TEXT
00000000 00000000
0xB08F8C62B08F903E
reserved
XXXXXXXX 00000000
0xB08F9040
RICFG1_ICU18IN0
00000000 XXXXXXXX
0xB08F9042
RICFG1_ICU18IN1
00000000 XXXXXXXX
0xB08F9044
RICFG1_ICU18FRTSEL
XXXXXXXX 00000000
0xB08F9046B08F905E
reserved
XXXXXXXX 00000000
0xB08F9060
RICFG1_ICU19IN0
00000000 XXXXXXXX
0xB08F9062
RICFG1_ICU19IN1
00000000 XXXXXXXX
0xB08F9064
RICFG1_ICU19FRTSEL
XXXXXXXX 00000000
0xB08F9066B08F93FE
reserved
XXXXXXXX 00000000
0xB08F9400
RICFG1_OCU16OTD0GATE
XXXXXXXX 00000000
0xB08F9402
RICFG1_OCU16OTD0GM
XXXXXXXX 00000000
0xB08F9404
RICFG1_OCU16OTD1GATE
XXXXXXXX 00000000
0xB08F9406
RICFG1_OCU16OTD1GM
XXXXXXXX 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
221
Data
Shee t
Table 5-6 Memory layout of PERI1_RBUS registers (21 / 25)
Offset
222
+1
+0
0xB08F9408B08F941E
reserved
XXXXXXXX 00000000
0xB08F9420
RICFG1_OCU17CMP0EXT
XXXXXXXX 00000000
0xB08F9422
RICFG1_OCU17FRTSEL
XXXXXXXX 00000000
0xB08F9424
RICFG1_OCU17OTD0GATE
XXXXXXXX 00000000
0xB08F9426
RICFG1_OCU17OTD0GM
XXXXXXXX 00000000
0xB08F9428
RICFG1_OCU17OTD1GATE
XXXXXXXX 00000000
0xB08F942A
RICFG1_OCU17OTD1GM
XXXXXXXX 00000000
0xB08F942CB08F9BFE
reserved
XXXXXXXX 00000000
0xB08F9C00
RICFG1_USART6SCKI
00000000 XXXXXXXX
0xB08F9C02
RICFG1_USART6SIN
00000000 XXXXXXXX
0xB08F9C04B08FA3FE
reserved
XXXXXXXX 00000000
0xB08FA400
RICFG1_PPG64PPGAGATE
XXXXXXXX 00000000
0xB08FA402
RICFG1_PPG64PPGAGM
XXXXXXXX 00000000
0xB08FA404
RICFG1_PPG64PPGBGATE
XXXXXXXX 00000000
0xB08FA406
RICFG1_PPG64PPGBGM
XXXXXXXX 00000000
0xB08FA408B08FA41E
reserved
XXXXXXXX 00000000
0xB08FA420
RICFG1_PPG65PPGAGATE
XXXXXXXX 00000000
0xB08FA422
RICFG1_PPG65PPGAGM
XXXXXXXX 00000000
0xB08FA424
RICFG1_PPG65PPGBGATE
XXXXXXXX 00000000
0xB08FA426
RICFG1_PPG65PPGBGM
XXXXXXXX 00000000
0xB08FA428B08FA43E
reserved
XXXXXXXX 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-6 Memory layout of PERI1_RBUS registers (22 / 25)
Offset
+1
+0
0xB08FA440
RICFG1_PPG66PPGAGATE
XXXXXXXX 00000000
0xB08FA442
RICFG1_PPG66PPGAGM
XXXXXXXX 00000000
0xB08FA444
RICFG1_PPG66PPGBGATE
XXXXXXXX 00000000
0xB08FA446
RICFG1_PPG66PPGBGM
XXXXXXXX 00000000
0xB08FA448B08FA45E
reserved
XXXXXXXX 00000000
0xB08FA460
RICFG1_PPG67PPGAGATE
XXXXXXXX 00000000
0xB08FA462
RICFG1_PPG67PPGAGM
XXXXXXXX 00000000
0xB08FA464
RICFG1_PPG67PPGBGATE
XXXXXXXX 00000000
0xB08FA466
RICFG1_PPG67PPGBGM
XXXXXXXX 00000000
0xB08FA468B08FA47E
reserved
XXXXXXXX 00000000
0xB08FA480
RICFG1_PPG68PPGAGATE
XXXXXXXX 00000000
0xB08FA482
RICFG1_PPG68PPGAGM
XXXXXXXX 00000000
0xB08FA484
RICFG1_PPG68PPGBGATE
XXXXXXXX 00000000
0xB08FA486
RICFG1_PPG68PPGBGM
XXXXXXXX 00000000
0xB08FA488B08FA49E
reserved
XXXXXXXX 00000000
0xB08FA4A0
RICFG1_PPG69PPGAGATE
XXXXXXXX 00000000
0xB08FA4A2
RICFG1_PPG69PPGAGM
XXXXXXXX 00000000
0xB08FA4A4
RICFG1_PPG69PPGBGATE
XXXXXXXX 00000000
0xB08FA4A6
RICFG1_PPG69PPGBGM
XXXXXXXX 00000000
0xB08FA4A8B08FA4BE
reserved
XXXXXXXX 00000000
0xB08FA4C0
RICFG1_PPG70PPGAGATE
XXXXXXXX 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
223
Data
Shee t
Table 5-6 Memory layout of PERI1_RBUS registers (23 / 25)
Offset
224
+1
+0
0xB08FA4C2
RICFG1_PPG70PPGAGM
XXXXXXXX 00000000
0xB08FA4C4
RICFG1_PPG70PPGBGATE
XXXXXXXX 00000000
0xB08FA4C6
RICFG1_PPG70PPGBGM
XXXXXXXX 00000000
0xB08FA4C8B08FA4DE
reserved
XXXXXXXX 00000000
0xB08FA4E0
RICFG1_PPG71PPGAGATE
XXXXXXXX 00000000
0xB08FA4E2
RICFG1_PPG71PPGAGM
XXXXXXXX 00000000
0xB08FA4E4
RICFG1_PPG71PPGBGATE
XXXXXXXX 00000000
0xB08FA4E6
RICFG1_PPG71PPGBGM
XXXXXXXX 00000000
0xB08FA4E8B08FABFE
reserved
XXXXXXXX 00000000
0xB08FAC00
RICFG1_PPGGRP16ETRG0
XXXXXXXX 00000000
0xB08FAC02
RICFG1_PPGGRP16ETRG1
XXXXXXXX 00000000
0xB08FAC04
RICFG1_PPGGRP16ETRG2
XXXXXXXX 00000000
0xB08FAC06
RICFG1_PPGGRP16ETRG3
XXXXXXXX 00000000
0xB08FAC08
RICFG1_PPGGRP16RLTTRG1
XXXXXXXX 00000000
0xB08FAC0AB08FAC1E
reserved
XXXXXXXX 00000000
0xB08FAC20
RICFG1_PPGGRP17ETRG0
XXXXXXXX 00000000
0xB08FAC22
RICFG1_PPGGRP17ETRG1
XXXXXXXX 00000000
0xB08FAC24
RICFG1_PPGGRP17ETRG2
XXXXXXXX 00000000
0xB08FAC26
RICFG1_PPGGRP17ETRG3
XXXXXXXX 00000000
0xB08FAC28
RICFG1_PPGGRP17RLTTRG1
XXXXXXXX 00000000
0xB08FAC2AB08FFC02
reserved
XXXXXXXX XXXXXXXX
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-6 Memory layout of PERI1_RBUS registers (24 / 25)
Offset
+1
+0
0xB08FFC04
BSU1_BTSTL
00000000 00000000
0xB08FFC06
BSU1_BTSTH
00000000 00000000
0xB08FFC08B08FFC0E
reserved
XXXXXXXX XXXXXXXX
0xB08FFC10
BSU1_PEN0L
XXXXXXXX 00000000
0xB08FFC12
reserved
XXXXXXXX XXXXXXXX
0xB08FFC14
BSU1_PEN1L
XXXXXXXX 00000000
0xB08FFC16
reserved
XXXXXXXX XXXXXXXX
0xB08FFC18
BSU1_PEN2L
XXXXXXXX 00000000
0xB08FFC1A
reserved
XXXXXXXX XXXXXXXX
0xB08FFC1C
BSU1_PEN3L
00000000 00000000
0xB08FFC1E
reserved
XXXXXXXX XXXXXXXX
0xB08FFC20
BSU1_PEN4L
00000000 00000000
0xB08FFC22
reserved
XXXXXXXX XXXXXXXX
0xB08FFC24
BSU1_PEN5L
00000000 00000000
0xB08FFC26
reserved
XXXXXXXX XXXXXXXX
0xB08FFC28
BSU1_PEN6L
XXXXXXXX 00000000
0xB08FFC2A
reserved
XXXXXXXX XXXXXXXX
0xB08FFC2C
BSU1_PEN7L
XXXXXXXX 00000000
0xB08FFC2E
reserved
XXXXXXXX XXXXXXXX
0xB08FFC30
BSU1_PEN8L
XXXXXXXX 00000000
0xB08FFC32
reserved
XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
225
Data
Shee t
Table 5-6 Memory layout of PERI1_RBUS registers (25 / 25)
Offset
226
+1
+0
0xB08FFC34
BSU1_PEN9L
00000000 00000000
0xB08FFC36
BSU1_PEN9H
00000000 00000000
0xB08FFC38
BSU1_PEN10L
00000000 00000000
0xB08FFC3A
BSU1_PEN10H
00000000 00000000
0xB08FFC3C
BSU1_PEN11L
00000000 00000000
0xB08FFC3E
BSU1_PEN11H
XXXXXXXX 00000000
0xB08FFC40B09FFFFE
reserved
XXXXXXXX XXXXXXXX
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-7 Memory layout of the PERI3_ERBUS registers (1 / 10)
0xB0A00000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00008
PPU0_PRS3
00000000 00000000 00000000 00000000
PPU0_PRS2
00000000 00000000 00000000 00000000
0xB0A00010
PPU0_PRS5
00000000 00000000 00000000 00000000
PPU0_PRS4
00000000 00000000 00000000 00000000
0xB0A00018
PPU0_PRS7
00000000 00000000 00000000 00000000
PPU0_PRS6
00000000 00000000 00000000 00000000
0xB0A00020
PPU0_PRS9
00000000 00000000 00000000 00000000
PPU0_PRS8
00000000 00000000 00000000 00000000
0xB0A00028
PPU0_PRS11
00000000 00000000 00000000 00000000
PPU0_PRS10
00000000 00000000 00000000 00000000
0xB0A00030
PPU0_PRS13
00000000 00000000 00000000 00000000
PPU0_PRS12
00000000 00000000 00000000 00000000
0xB0A00038B0A00040
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00048
PPU0_PAS3
00000000 00000000 00000000 00000000
PPU0_PAS2
00000000 00000000 00000000 00000000
0xB0A00050
PPU0_PAS5
00000000 00000000 00000000 00000000
PPU0_PAS4
00000000 00000000 00000000 00000000
0xB0A00058
PPU0_PAS7
00000000 00000000 00000000 00000000
PPU0_PAS6
00000000 00000000 00000000 00000000
0xB0A00060
PPU0_PAS9
00000000 00000000 00000000 00000000
PPU0_PAS8
00000000 00000000 00000000 00000000
0xB0A00068
PPU0_PAS11
00000000 00000000 00000000 00000000
PPU0_PAS10
00000000 00000000 00000000 00000000
0xB0A00070
PPU0_PAS13
00000000 00000000 00000000 00000000
PPU0_PAS12
00000000 00000000 00000000 00000000
0xB0A00078
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00080
PPU0_GAS1
00000000 00000000 00000000 00000000
PPU0_GAS0
00000000 00000000 00000000 00000000
0xB0A00088
PPU0_GAS3
00000000 00000000 00000000 00000000
PPU0_GAS2
00000000 00000000 00000000 00000000
0xB0A00090
PPU0_GAS5
00000000 00000000 00000000 00000000
PPU0_GAS4
00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
227
Data
Shee t
Table 5-7 Memory layout of the PERI3_ERBUS registers (2 / 10)
228
0xB0A00098B0A000C0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A000C8
PPU0_PRC3
00000000 00000000 00000000 00000000
PPU0_PRC2
00000000 00000000 00000000 00000000
0xB0A000D0
PPU0_PRC5
00000000 00000000 00000000 00000000
PPU0_PRC4
00000000 00000000 00000000 00000000
0xB0A000D8
PPU0_PRC7
00000000 00000000 00000000 00000000
PPU0_PRC6
00000000 00000000 00000000 00000000
0xB0A000E0
PPU0_PRC9
00000000 00000000 00000000 00000000
PPU0_PRC8
00000000 00000000 00000000 00000000
0xB0A000E8
PPU0_PRC11
00000000 00000000 00000000 00000000
PPU0_PRC10
00000000 00000000 00000000 00000000
0xB0A000F0
PPU0_PRC13
00000000 00000000 00000000 00000000
PPU0_PRC12
00000000 00000000 00000000 00000000
0xB0A000F8B0A00100
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00108
PPU0_PAC3
00000000 00000000 00000000 00000000
PPU0_PAC2
00000000 00000000 00000000 00000000
0xB0A00110
PPU0_PAC5
00000000 00000000 00000000 00000000
PPU0_PAC4
00000000 00000000 00000000 00000000
0xB0A00118
PPU0_PAC7
00000000 00000000 00000000 00000000
PPU0_PAC6
00000000 00000000 00000000 00000000
0xB0A00120
PPU0_PAC9
00000000 00000000 00000000 00000000
PPU0_PAC8
00000000 00000000 00000000 00000000
0xB0A00128
PPU0_PAC11
00000000 00000000 00000000 00000000
PPU0_PAC10
00000000 00000000 00000000 00000000
0xB0A00130
PPU0_PAC13
00000000 00000000 00000000 00000000
PPU0_PAC12
00000000 00000000 00000000 00000000
0xB0A00138
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00140
PPU0_GAC1
00000000 00000000 00000000 00000000
PPU0_GAC0
00000000 00000000 00000000 00000000
0xB0A00148
PPU0_GAC3
00000000 00000000 00000000 00000000
PPU0_GAC2
00000000 00000000 00000000 00000000
0xB0A00150
PPU0_GAC5
00000000 00000000 00000000 00000000
PPU0_GAC4
00000000 00000000 00000000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-7 Memory layout of the PERI3_ERBUS registers (3 / 10)
0xB0A00158B0A00180
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00188
PPU0_PR3
00000000 00000000 00000000 00000000
PPU0_PR2
00000000 00000000 00000000 00000000
0xB0A00190
PPU0_PR5
00000000 00000000 00000000 00000000
PPU0_PR4
00000000 00000000 00000000 00000000
0xB0A00198
PPU0_PR7
00000000 00000000 00000000 00000000
PPU0_PR6
00000000 00000000 00000000 00000000
0xB0A001A0
PPU0_PR9
00000000 00000000 00000000 00000000
PPU0_PR8
00000000 00000000 00000000 00000000
0xB0A001A8
PPU0_PR11
00000000 00000000 00000000 00000000
PPU0_PR10
00000000 00000000 00000000 00000000
0xB0A001B0
PPU0_PR13
00000000 00000000 00000000 00000000
PPU0_PR12
00000000 00000000 00000000 00000000
0xB0A001B8B0A001C0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A001C8
PPU0_PA3
00000000 00000000 00000000 00000000
PPU0_PA2
00000000 00000000 00000000 00000000
0xB0A001D0
PPU0_PA5
00000000 00000000 00000000 00000000
PPU0_PA4
00000000 00000000 00000000 00000000
0xB0A001D8
PPU0_PA7
00000000 00000000 00000000 00000000
PPU0_PA6
00000000 00000000 00000000 00000000
0xB0A001E0
PPU0_PA9
00000000 00000000 00000000 00000000
PPU0_PA8
00000000 00000000 00000000 00000000
0xB0A001E8
PPU0_PA11
00000000 00000000 00000000 00000000
PPU0_PA10
00000000 00000000 00000000 00000000
0xB0A001F0
PPU0_PA13
00000000 00000000 00000000 00000000
PPU0_PA12
00000000 00000000 00000000 00000000
0xB0A001F8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00200
PPU0_GA1
00000000 00000000 00000000 00000000
PPU0_GA0
00000000 00000000 00000000 00000000
0xB0A00208
PPU0_GA3
00000000 00000000 00000000 00000000
PPU0_GA2
00000000 00000000 00000000 00000000
0xB0A00210
PPU0_GA5
00000000 00000000 00000000 00000000
PPU0_GA4
00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
229
Data
Shee t
Table 5-7 Memory layout of the PERI3_ERBUS registers (4 / 10)
0xB0A00218B0A00238
230
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A00240
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
PPU0_UNLOCK
00000000 00000000 00000000 00000000
0xB0A00248
PPU0_CTR
XXXXXXXX 00000001 00000000 00000000
PPU0_ST
XXXXXXXX XXXXXXXX 00000001 00000001
0xB0A00250B0A07FF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A08000
GPIO_POSR0
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08008
GPIO_POCR0
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08010
GPIO_DDSR0
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08018
GPIO_DDCR0
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08020
GPIO_POSR1
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08028
GPIO_POCR1
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08030
GPIO_DDSR1
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08038
GPIO_DDCR1
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08040
GPIO_POSR2
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08048
GPIO_POCR2
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08050
GPIO_DDSR2
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08058
GPIO_DDCR2
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08060
GPIO_POSR3
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08068
GPIO_POCR3
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-7 Memory layout of the PERI3_ERBUS registers (5 / 10)
0xB0A08070
GPIO_DDSR3
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08078
GPIO_DDCR3
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08080B0A081F8
reserved
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08200
GPIO_PODR0
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08208
GPIO_DDR0
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08210
GPIO_PODR1
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08218
GPIO_DDR1
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08220
GPIO_PODR2
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08228
GPIO_DDR2
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08230
GPIO_PODR3
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08238
GPIO_DDR3
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08240B0A082F8
reserved
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08300
GPIO_PIDR0
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A08308
GPIO_PIDR1
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A08310
GPIO_PIDR2
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A08318
GPIO_PIDR3
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A08320B0A08378
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A08380
GPIO_PPER0
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
231
Data
Shee t
Table 5-7 Memory layout of the PERI3_ERBUS registers (6 / 10)
0xB0A08388
GPIO_PPER1
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08390
GPIO_PPER2
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A08398
GPIO_PPER3
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0xB0A083A0B0A0FFF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A10000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT0_DMACFG
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
0xB0A10008
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT0_TMCSR
00000000 00000000 00000000 00000000
0xB0A10010
RLT0_TMR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT0_TMRLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A10018B0A103F8
0xB0A10400
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT1_DMACFG
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
0xB0A10408
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT1_TMCSR
00000000 00000000 00000000 00000000
0xB0A10410
RLT1_TMR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT1_TMRLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A10418B0A107F8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A10800
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT2_DMACFG
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
0xB0A10808
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT2_TMCSR
00000000 00000000 00000000 00000000
0xB0A10810
RLT2_TMR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT2_TMRLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A10818B0A10BF8
232
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A10C00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT3_DMACFG
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
0xB0A10C08
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT3_TMCSR
00000000 00000000 00000000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-7 Memory layout of the PERI3_ERBUS registers (7 / 10)
0xB0A10C10
0xB0A10C18B0A10FF8
RLT3_TMR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT3_TMRLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A11000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT4_DMACFG
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
0xB0A11008
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT4_TMCSR
00000000 00000000 00000000 00000000
0xB0A11010
RLT4_TMR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT4_TMRLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A11018B0A113F8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A11400
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT5_DMACFG
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
0xB0A11408
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT5_TMCSR
00000000 00000000 00000000 00000000
0xB0A11410
RLT5_TMR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT5_TMRLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A11418B0A117F8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A11800
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT6_DMACFG
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
0xB0A11808
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT6_TMCSR
00000000 00000000 00000000 00000000
0xB0A11810
RLT6_TMR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT6_TMRLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A11818B0A11BF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A11C00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT7_DMACFG
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
0xB0A11C08
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT7_TMCSR
00000000 00000000 00000000 00000000
0xB0A11C10
RLT7_TMR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT7_TMRLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A11C18B0A11FF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
233
Data
Shee t
Table 5-7 Memory layout of the PERI3_ERBUS registers (8 / 10)
0xB0A12000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT8_DMACFG
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
0xB0A12008
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT8_TMCSR
00000000 00000000 00000000 00000000
0xB0A12010
RLT8_TMR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT8_TMRLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A12018B0A123F8
0xB0A12400
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT9_DMACFG
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
0xB0A12408
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT9_TMCSR
00000000 00000000 00000000 00000000
0xB0A12410
RLT9_TMR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RLT9_TMRLR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A12418B0A1FFF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A20000
UDC0_ECC1
XXXXXXXX 00000000
UDC0_CC1
00000000 00000000
UDC0_ECC0
XXXXXXXX 00000000
UDC0_CC0
00000000 00000000
0xB0A20008
UDC0_TGL1
00000000 00000000
UDC0_TGL0
00000000 00000000
UDC0_CS1
00000000 00000000
UDC0_CS0
00000000 00000000
0xB0A20010
UDC0_RC
00000000 00000000 00000000 00000000
0xB0A20018
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0A20020B0AEFFF8
UDC0_CR
00000000 00000000 00000000 00000000
reserved
XXXXXXXX XXXXXXXX
UDC0_DBG
XXXXXXXX 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0AF0000
BECU3_ADDRH
00000000 00000000
BECU3_ADDRL
00000000 00000000
BECU3_CTRH
00000000 00000000
BECU3_CTRL
00000000 00000000
0xB0AF0008
BECU3_DATAHH
00000000 00000000
BECU3_DATAHL
00000000 00000000
BECU3_DATALH
00000000 00000000
BECU3_DATALL
00000000 00000000
0xB0AF0010
reserved
00000000 00000000
BECU3_MIDH
XXXXXXXX XXXXXXXX
BECU3_MIDL
XXXXXXXX XXXXXXXX
BECU3_MASTERID
00000000 00000000
0xB0AF0018
reserved
00000000 00000000
reserved
00000000 00000000
reserved
00000000 00000000
BECU3_NMIEN
XXXXXXXX 00000001
0xB0AF0020B0AF87F8
234
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-7 Memory layout of the PERI3_ERBUS registers (9 / 10)
0xB0AF8800
0xB0AF8808B0AF8818
0xB0AF8820
0xB0AF8828B0AF8838
0xB0AF8840
0xB0AF8848B0AF8858
0xB0AF8860
0xB0AF8868B0AF8878
0xB0AF8880
0xB0AF8888B0AF8898
0xB0AF88A0
0xB0AF88A8B0AF88B8
0xB0AF88C0
0xB0AF88C8B0AF88D8
0xB0AF88E0
0xB0AF88E8B0AF88F8
0xB0AF8900
0xB0AF8908B0AF8918
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
RICFG3_RLT0TIN
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
RICFG3_RLT1TIN
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
RICFG3_RLT2TIN
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
RICFG3_RLT3TIN
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
RICFG3_RLT4TIN
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
RICFG3_RLT5TIN
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
RICFG3_RLT6TIN
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
RICFG3_RLT7TIN
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
RICFG3_RLT8TIN
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
235
Data
Shee t
Table 5-7 Memory layout of the PERI3_ERBUS registers (10 / 10)
0xB0AF8920
0xB0AF8928B0AF8FF8
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX
RICFG3_RLT9TIN
00000000 00000000
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0AF9000
reserved
XXXXXXXX XXXXXXXX
RICFG3_UDC0AIN1
00000000 00000000
reserved
XXXXXXXX XXXXXXXX
RICFG3_UDC0AIN0
00000000 00000000
0xB0AF9008
reserved
XXXXXXXX XXXXXXXX
RICFG3_UDC0BIN1
00000000 00000000
reserved
XXXXXXXX XXXXXXXX
RICFG3_UDC0BIN0
00000000 00000000
0xB0AF9010
reserved
XXXXXXXX XXXXXXXX
RICFG3_UDC0ZIN1
00000000 00000000
reserved
XXXXXXXX XXXXXXXX
RICFG3_UDC0ZIN0
00000000 00000000
0xB0AF9018B0AFFBF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0AFFC00
BSU3_BTST
00000000 00000000 00000000 00000000
0xB0AFFC08B0AFFC10
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0AFFC18
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSU3_PEN2
00000000 00000000 00000000 00000000
0xB0AFFC20
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSU3_PEN4
XXXXXXXX XXXXXXXX XXXXXXXX 00000000
0xB0AFFC28B0AFFFF8
236
reserved
XXXXXXXX XXXXXXXX
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-8 Memory layout of the PERI4_SLAVE registers (1 / 16)
Offset
+3
+2
+1
0xB0B00000
MPUXGFX_CTRL0
00000000 00000000 00000001 00000000
0xB0B00004
MPUXGFX_NMIEN
00000000 00000000 00000000 00000001
0xB0B00008
MPUXGFX_WERRC
00000000 00000000 00000XXX XXXXXXX0
0xB0B0000C
MPUXGFX_WERRA
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0B00010
MPUXGFX_RERRC
00000000 00000000 00000XXX XXXXXXX0
0xB0B00014
MPUXGFX_RERRA
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0B00018
MPUXGFX_CTRL1
00000000 00000000 00000000 00000000
0xB0B0001C
MPUXGFX_SADDR1
00000000 00000000 00000000 00000000
0xB0B00020
MPUXGFX_EADDR1
00000000 00000000 00000000 01111111
0xB0B00024
MPUXGFX_CTRL2
00000000 00000000 00000000 00000000
0xB0B00028
MPUXGFX_SADDR2
00000000 00000000 00000000 00000000
0xB0B0002C
MPUXGFX_EADDR2
00000000 00000000 00000000 01111111
0xB0B00030
MPUXGFX_CTRL3
00000000 00000000 00000000 00000000
0xB0B00034
MPUXGFX_SADDR3
00000000 00000000 00000000 00000000
0xB0B00038
MPUXGFX_EADDR3
00000000 00000000 00000000 01111111
0xB0B0003C
MPUXGFX_CTRL4
00000000 00000000 00000000 00000000
0xB0B00040
MPUXGFX_SADDR4
00000000 00000000 00000000 00000000
0xB0B00044
MPUXGFX_EADDR4
00000000 00000000 00000000 01111111
0xB0B00048
MPUXGFX_CTRL5
00000000 00000000 00000000 00000000
0xB0B0004C
MPUXGFX_SADDR5
00000000 00000000 00000000 00000000
0xB0B00050
MPUXGFX_EADDR5
00000000 00000000 00000000 01111111
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
237
Data
Shee t
Table 5-8 Memory layout of the PERI4_SLAVE registers (2 / 16)
Offset
238
+3
+2
+1
0xB0B00054
MPUXGFX_CTRL6
00000000 00000000 00000000 00000000
0xB0B00058
MPUXGFX_SADDR6
00000000 00000000 00000000 00000000
0xB0B0005C
MPUXGFX_EADDR6
00000000 00000000 00000000 01111111
0xB0B00060
MPUXGFX_CTRL7
00000000 00000000 00000000 00000000
0xB0B00064
MPUXGFX_SADDR7
00000000 00000000 00000000 00000000
0xB0B00068
MPUXGFX_EADDR7
00000000 00000000 00000000 01111111
0xB0B0006C
MPUXGFX_CTRL8
00000000 00000000 00000000 00000000
0xB0B00070
MPUXGFX_SADDR8
00000000 00000000 00000000 00000000
0xB0B00074
MPUXGFX_EADDR8
00000000 00000000 00000000 01111111
0xB0B00078
MPUXGFX_UNLOCK
00000000 00000000 00000000 00000000
0xB0B0007C
MPUXGFX_MID
00000000 00000000 00000000 00000000
0xB0B00080B0B1FFFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0B20000
I2S0_RXFDAT0
00000000 00000000 00000000 00000000
0xB0B20004
I2S0_RXFDAT1
00000000 00000000 00000000 00000000
0xB0B20008
I2S0_RXFDAT2
00000000 00000000 00000000 00000000
0xB0B2000C
I2S0_RXFDAT3
00000000 00000000 00000000 00000000
0xB0B20010
I2S0_RXFDAT4
00000000 00000000 00000000 00000000
0xB0B20014
I2S0_RXFDAT5
00000000 00000000 00000000 00000000
0xB0B20018
I2S0_RXFDAT6
00000000 00000000 00000000 00000000
0xB0B2001C
I2S0_RXFDAT7
00000000 00000000 00000000 00000000
0xB0B20020
I2S0_RXFDAT8
00000000 00000000 00000000 00000000
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-8 Memory layout of the PERI4_SLAVE registers (3 / 16)
Offset
+3
+2
+1
0xB0B20024
I2S0_RXFDAT9
00000000 00000000 00000000 00000000
0xB0B20028
I2S0_RXFDAT10
00000000 00000000 00000000 00000000
0xB0B2002C
I2S0_RXFDAT11
00000000 00000000 00000000 00000000
0xB0B20030
I2S0_RXFDAT12
00000000 00000000 00000000 00000000
0xB0B20034
I2S0_RXFDAT13
00000000 00000000 00000000 00000000
0xB0B20038
I2S0_RXFDAT14
00000000 00000000 00000000 00000000
0xB0B2003C
I2S0_RXFDAT15
00000000 00000000 00000000 00000000
0xB0B20040
I2S0_TXFDAT0
00000000 00000000 00000000 00000000
0xB0B20044
I2S0_TXFDAT1
00000000 00000000 00000000 00000000
0xB0B20048
I2S0_TXFDAT2
00000000 00000000 00000000 00000000
0xB0B2004C
I2S0_TXFDAT3
00000000 00000000 00000000 00000000
0xB0B20050
I2S0_TXFDAT4
00000000 00000000 00000000 00000000
0xB0B20054
I2S0_TXFDAT5
00000000 00000000 00000000 00000000
0xB0B20058
I2S0_TXFDAT6
00000000 00000000 00000000 00000000
0xB0B2005C
I2S0_TXFDAT7
00000000 00000000 00000000 00000000
0xB0B20060
I2S0_TXFDAT8
00000000 00000000 00000000 00000000
0xB0B20064
I2S0_TXFDAT9
00000000 00000000 00000000 00000000
0xB0B20068
I2S0_TXFDAT10
00000000 00000000 00000000 00000000
0xB0B2006C
I2S0_TXFDAT11
00000000 00000000 00000000 00000000
0xB0B20070
I2S0_TXFDAT12
00000000 00000000 00000000 00000000
0xB0B20074
I2S0_TXFDAT13
00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
239
Data
Shee t
Table 5-8 Memory layout of the PERI4_SLAVE registers (4 / 16)
Offset
240
+3
+2
+1
0xB0B20078
I2S0_TXFDAT14
00000000 00000000 00000000 00000000
0xB0B2007C
I2S0_TXFDAT15
00000000 00000000 00000000 00000000
0xB0B20080
I2S0_CNTREG
00000000 00000000 00000000 01100000
0xB0B20084
I2S0_MCR0REG
00000000 00000000 00000000 00000000
0xB0B20088
I2S0_MCR1REG
00000000 00000000 00000000 00000000
0xB0B2008C
I2S0_MCR2REG
00000000 00000000 00000000 00000000
0xB0B20090
I2S0_OPRREG
00000000 00000000 00000000 00000000
0xB0B20094
I2S0_SRST
00000000 00000000 00000000 00000000
0xB0B20098
I2S0_INTCNT
01111111 00111111 00000000 00000000
0xB0B2009C
I2S0_STATUS
00000000 00000000 00000000 00000000
0xB0B200A0
I2S0_DMAACT
00000000 00000000 00000000 00000000
0xB0B200A4
I2S0_DEBUG
00000000 00000000 00000000 00000000
0xB0B200A8
I2S0_MIDREG
00000000 00000000 00000000 00000000
0xB0B200ACB0B203FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0B20400
I2S1_RXFDAT0
00000000 00000000 00000000 00000000
0xB0B20404
I2S1_RXFDAT1
00000000 00000000 00000000 00000000
0xB0B20408
I2S1_RXFDAT2
00000000 00000000 00000000 00000000
0xB0B2040C
I2S1_RXFDAT3
00000000 00000000 00000000 00000000
0xB0B20410
I2S1_RXFDAT4
00000000 00000000 00000000 00000000
0xB0B20414
I2S1_RXFDAT5
00000000 00000000 00000000 00000000
0xB0B20418
I2S1_RXFDAT6
00000000 00000000 00000000 00000000
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-8 Memory layout of the PERI4_SLAVE registers (5 / 16)
Offset
+3
+2
+1
0xB0B2041C
I2S1_RXFDAT7
00000000 00000000 00000000 00000000
0xB0B20420
I2S1_RXFDAT8
00000000 00000000 00000000 00000000
0xB0B20424
I2S1_RXFDAT9
00000000 00000000 00000000 00000000
0xB0B20428
I2S1_RXFDAT10
00000000 00000000 00000000 00000000
0xB0B2042C
I2S1_RXFDAT11
00000000 00000000 00000000 00000000
0xB0B20430
I2S1_RXFDAT12
00000000 00000000 00000000 00000000
0xB0B20434
I2S1_RXFDAT13
00000000 00000000 00000000 00000000
0xB0B20438
I2S1_RXFDAT14
00000000 00000000 00000000 00000000
0xB0B2043C
I2S1_RXFDAT15
00000000 00000000 00000000 00000000
0xB0B20440
I2S1_TXFDAT0
00000000 00000000 00000000 00000000
0xB0B20444
I2S1_TXFDAT1
00000000 00000000 00000000 00000000
0xB0B20448
I2S1_TXFDAT2
00000000 00000000 00000000 00000000
0xB0B2044C
I2S1_TXFDAT3
00000000 00000000 00000000 00000000
0xB0B20450
I2S1_TXFDAT4
00000000 00000000 00000000 00000000
0xB0B20454
I2S1_TXFDAT5
00000000 00000000 00000000 00000000
0xB0B20458
I2S1_TXFDAT6
00000000 00000000 00000000 00000000
0xB0B2045C
I2S1_TXFDAT7
00000000 00000000 00000000 00000000
0xB0B20460
I2S1_TXFDAT8
00000000 00000000 00000000 00000000
0xB0B20464
I2S1_TXFDAT9
00000000 00000000 00000000 00000000
0xB0B20468
I2S1_TXFDAT10
00000000 00000000 00000000 00000000
0xB0B2046C
I2S1_TXFDAT11
00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
241
Data
Shee t
Table 5-8 Memory layout of the PERI4_SLAVE registers (6 / 16)
Offset
242
+3
+2
+1
0xB0B20470
I2S1_TXFDAT12
00000000 00000000 00000000 00000000
0xB0B20474
I2S1_TXFDAT13
00000000 00000000 00000000 00000000
0xB0B20478
I2S1_TXFDAT14
00000000 00000000 00000000 00000000
0xB0B2047C
I2S1_TXFDAT15
00000000 00000000 00000000 00000000
0xB0B20480
I2S1_CNTREG
00000000 00000000 00000000 01100000
0xB0B20484
I2S1_MCR0REG
00000000 00000000 00000000 00000000
0xB0B20488
I2S1_MCR1REG
00000000 00000000 00000000 00000000
0xB0B2048C
I2S1_MCR2REG
00000000 00000000 00000000 00000000
0xB0B20490
I2S1_OPRREG
00000000 00000000 00000000 00000000
0xB0B20494
I2S1_SRST
00000000 00000000 00000000 00000000
0xB0B20498
I2S1_INTCNT
01111111 00111111 00000000 00000000
0xB0B2049C
I2S1_STATUS
00000000 00000000 00000000 00000000
0xB0B204A0
I2S1_DMAACT
00000000 00000000 00000000 00000000
0xB0B204A4
I2S1_DEBUG
00000000 00000000 00000000 00000000
0xB0B204A8
I2S1_MIDREG
00000000 00000000 00000000 00000000
0xB0B204ACB0B2FFFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0B30000
CRC0_POLY
00000100 11000001 00011101 10110111
0xB0B30004
CRC0_SEED
11111111 11111111 11111111 11111111
0xB0B30008
CRC0_FXOR
11111111 11111111 11111111 11111111
0xB0B3000C
CRC0_CFG
00000000 11100000 00000000 00000000
0xB0B30010
CRC0_WR
00000000 00000000 00000000 00000000
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-8 Memory layout of the PERI4_SLAVE registers (7 / 16)
Offset
+3
+2
+1
+0
0xB0B30014
CRC0_RD
00000000 00000000 00000000 00000000
0xB0B30018B0B37FFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0B38000
SPI0_MCTRL
00000000 00000000 00000000 00000000
0xB0B38004
SPI0_PCC0
00000000 00000001 00000000 00000000
0xB0B38008
SPI0_PCC1
00000000 00000001 00000000 00000000
0xB0B3800C
SPI0_PCC2
00000000 00000001 00000000 00000000
0xB0B38010
SPI0_PCC3
00000000 00000001 00000000 00000000
0xB0B38014
SPI0_TXF
00000000 00000000 00000000 00000000
0xB0B38018
SPI0_TXE
00000000 00000000 00000000 00000000
0xB0B3801C
SPI0_TXC
00000000 00000000 00000000 00000000
0xB0B38020
SPI0_RXF
00000000 00000000 00000000 00000000
0xB0B38024
SPI0_RXE
00000000 00000000 00000000 00000000
0xB0B38028
SPI0_RXC
00000000 00000000 00000000 00000000
0xB0B3802C
SPI0_FAULTF
00000000 00000000 00000000 00000000
0xB0B38030
SPI0_FAULTC
00000000 00000000 00000000 00000000
0xB0B38034
0xB0B38038
0xB0B3803C
read0
00000000 00000000
SPI0_DMTRP
00000000
SPI0_DMBCS
00000000 00000000
SPI0_DMCFG
00000001
SPI0_DMSTOP
00000000
SPI0_DMSTART
00000000
SPI0_DMBCC
00000000 00000000
SPI0_DMSTATUS
00000000 00000000 00000000 00000000
0xB0B38040
0xB0B38044
SPI0_DMPSEL
00000000
SPI0_DMDMAEN
00000000
read0
00000000 00000000
0xB0B38048
January 30, 2015, MB9EF226_DS707-00004-2v1-E
SPI0_RXBITCNT
00000000
SPI0_TXBITCNT
00000000
SPI0_RXSHIFT
00000000 00000000 00000000 00000000
243
Data
Shee t
Table 5-8 Memory layout of the PERI4_SLAVE registers (8 / 16)
Offset
244
+3
+2
+1
0xB0B3804C
SPI0_FIFOCFG
00000000 00000000 00000000 01110111
0xB0B38050
SPI0_TXFIFO0
00000000 00000000 00000000 00000000
0xB0B38054
SPI0_TXFIFO1
00000000 00000000 00000000 00000000
0xB0B38058
SPI0_TXFIFO2
00000000 00000000 00000000 00000000
0xB0B3805C
SPI0_TXFIFO3
00000000 00000000 00000000 00000000
0xB0B38060
SPI0_TXFIFO4
00000000 00000000 00000000 00000000
0xB0B38064
SPI0_TXFIFO5
00000000 00000000 00000000 00000000
0xB0B38068
SPI0_TXFIFO6
00000000 00000000 00000000 00000000
0xB0B3806C
SPI0_TXFIFO7
00000000 00000000 00000000 00000000
0xB0B38070
SPI0_TXFIFO8
00000000 00000000 00000000 00000000
0xB0B38074
SPI0_TXFIFO9
00000000 00000000 00000000 00000000
0xB0B38078
SPI0_TXFIFO10
00000000 00000000 00000000 00000000
0xB0B3807C
SPI0_TXFIFO11
00000000 00000000 00000000 00000000
0xB0B38080
SPI0_TXFIFO12
00000000 00000000 00000000 00000000
0xB0B38084
SPI0_TXFIFO13
00000000 00000000 00000000 00000000
0xB0B38088
SPI0_TXFIFO14
00000000 00000000 00000000 00000000
0xB0B3808C
SPI0_TXFIFO15
00000000 00000000 00000000 00000000
0xB0B38090
SPI0_RXFIFO0
00000000 00000000 00000000 00000000
0xB0B38094
SPI0_RXFIFO1
00000000 00000000 00000000 00000000
0xB0B38098
SPI0_RXFIFO2
00000000 00000000 00000000 00000000
0xB0B3809C
SPI0_RXFIFO3
00000000 00000000 00000000 00000000
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-8 Memory layout of the PERI4_SLAVE registers (9 / 16)
Offset
+3
+2
+1
0xB0B380A0
SPI0_RXFIFO4
00000000 00000000 00000000 00000000
0xB0B380A4
SPI0_RXFIFO5
00000000 00000000 00000000 00000000
0xB0B380A8
SPI0_RXFIFO6
00000000 00000000 00000000 00000000
0xB0B380AC
SPI0_RXFIFO7
00000000 00000000 00000000 00000000
0xB0B380B0
SPI0_RXFIFO8
00000000 00000000 00000000 00000000
0xB0B380B4
SPI0_RXFIFO9
00000000 00000000 00000000 00000000
0xB0B380B8
SPI0_RXFIFO10
00000000 00000000 00000000 00000000
0xB0B380BC
SPI0_RXFIFO11
00000000 00000000 00000000 00000000
0xB0B380C0
SPI0_RXFIFO12
00000000 00000000 00000000 00000000
0xB0B380C4
SPI0_RXFIFO13
00000000 00000000 00000000 00000000
0xB0B380C8
SPI0_RXFIFO14
00000000 00000000 00000000 00000000
0xB0B380CC
SPI0_RXFIFO15
00000000 00000000 00000000 00000000
0xB0B380D0B0B380F8
reserved
00000000 00000000 00000000 00000000
0xB0B380FC
SPI0_MID
00000000 00000000 00000000 00000001
0xB0B38100B0B383FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0B38400
SPI1_MCTRL
00000000 00000000 00000000 00000000
0xB0B38404
SPI1_PCC0
00000000 00000001 00000000 00000000
0xB0B38408
SPI1_PCC1
00000000 00000001 00000000 00000000
0xB0B3840C
SPI1_PCC2
00000000 00000001 00000000 00000000
0xB0B38410
SPI1_PCC3
00000000 00000001 00000000 00000000
0xB0B38414
SPI1_TXF
00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
245
Data
Shee t
Table 5-8 Memory layout of the PERI4_SLAVE registers (10 / 16)
Offset
+2
+1
+0
0xB0B38418
SPI1_TXE
00000000 00000000 00000000 00000000
0xB0B3841C
SPI1_TXC
00000000 00000000 00000000 00000000
0xB0B38420
SPI1_RXF
00000000 00000000 00000000 00000000
0xB0B38424
SPI1_RXE
00000000 00000000 00000000 00000000
0xB0B38428
SPI1_RXC
00000000 00000000 00000000 00000000
0xB0B3842C
SPI1_FAULTF
00000000 00000000 00000000 00000000
0xB0B38430
SPI1_FAULTC
00000000 00000000 00000000 00000000
0xB0B38434
0xB0B38438
0xB0B3843C
0xB0B38440
0xB0B38444
246
+3
read0
00000000 00000000
SPI1_DMTRP
00000000
SPI1_DMPSEL
00000000
SPI1_DMBCS
00000000 00000000
SPI1_DMDMAEN
00000000
SPI1_DMCFG
00000001
SPI1_DMSTOP
00000000
SPI1_DMSTART
00000000
SPI1_DMBCC
00000000 00000000
SPI1_DMSTATUS
00000000 00000000 00000000 00000000
read0
00000000 00000000
SPI1_RXBITCNT
00000000
0xB0B38448
SPI1_RXSHIFT
00000000 00000000 00000000 00000000
0xB0B3844C
SPI1_FIFOCFG
00000000 00000000 00000000 01110111
0xB0B38450
SPI1_TXFIFO0
00000000 00000000 00000000 00000000
0xB0B38454
SPI1_TXFIFO1
00000000 00000000 00000000 00000000
0xB0B38458
SPI1_TXFIFO2
00000000 00000000 00000000 00000000
0xB0B3845C
SPI1_TXFIFO3
00000000 00000000 00000000 00000000
0xB0B38460
SPI1_TXFIFO4
00000000 00000000 00000000 00000000
0xB0B38464
SPI1_TXFIFO5
00000000 00000000 00000000 00000000
0xB0B38468
SPI1_TXFIFO6
00000000 00000000 00000000 00000000
SPI1_TXBITCNT
00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-8 Memory layout of the PERI4_SLAVE registers (11 / 16)
Offset
+3
+2
+1
0xB0B3846C
SPI1_TXFIFO7
00000000 00000000 00000000 00000000
0xB0B38470
SPI1_TXFIFO8
00000000 00000000 00000000 00000000
0xB0B38474
SPI1_TXFIFO9
00000000 00000000 00000000 00000000
0xB0B38478
SPI1_TXFIFO10
00000000 00000000 00000000 00000000
0xB0B3847C
SPI1_TXFIFO11
00000000 00000000 00000000 00000000
0xB0B38480
SPI1_TXFIFO12
00000000 00000000 00000000 00000000
0xB0B38484
SPI1_TXFIFO13
00000000 00000000 00000000 00000000
0xB0B38488
SPI1_TXFIFO14
00000000 00000000 00000000 00000000
0xB0B3848C
SPI1_TXFIFO15
00000000 00000000 00000000 00000000
0xB0B38490
SPI1_RXFIFO0
00000000 00000000 00000000 00000000
0xB0B38494
SPI1_RXFIFO1
00000000 00000000 00000000 00000000
0xB0B38498
SPI1_RXFIFO2
00000000 00000000 00000000 00000000
0xB0B3849C
SPI1_RXFIFO3
00000000 00000000 00000000 00000000
0xB0B384A0
SPI1_RXFIFO4
00000000 00000000 00000000 00000000
0xB0B384A4
SPI1_RXFIFO5
00000000 00000000 00000000 00000000
0xB0B384A8
SPI1_RXFIFO6
00000000 00000000 00000000 00000000
0xB0B384AC
SPI1_RXFIFO7
00000000 00000000 00000000 00000000
0xB0B384B0
SPI1_RXFIFO8
00000000 00000000 00000000 00000000
0xB0B384B4
SPI1_RXFIFO9
00000000 00000000 00000000 00000000
0xB0B384B8
SPI1_RXFIFO10
00000000 00000000 00000000 00000000
0xB0B384BC
SPI1_RXFIFO11
00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
247
Data
Shee t
Table 5-8 Memory layout of the PERI4_SLAVE registers (12 / 16)
Offset
+2
+1
0xB0B384C0
SPI1_RXFIFO12
00000000 00000000 00000000 00000000
0xB0B384C4
SPI1_RXFIFO13
00000000 00000000 00000000 00000000
0xB0B384C8
SPI1_RXFIFO14
00000000 00000000 00000000 00000000
0xB0B384CC
SPI1_RXFIFO15
00000000 00000000 00000000 00000000
0xB0B384D0B0B384F8
reserved
00000000 00000000 00000000 00000000
0xB0B384FC
SPI1_MID
00000000 00000000 00000000 00000001
0xB0B38500B0B387FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0B38800
SPI2_MCTRL
00000000 00000000 00000000 00000000
0xB0B38804
SPI2_PCC0
00000000 00000001 00000000 00000000
0xB0B38808
SPI2_PCC1
00000000 00000001 00000000 00000000
0xB0B3880C
SPI2_PCC2
00000000 00000001 00000000 00000000
0xB0B38810
SPI2_PCC3
00000000 00000001 00000000 00000000
0xB0B38814
SPI2_TXF
00000000 00000000 00000000 00000000
0xB0B38818
SPI2_TXE
00000000 00000000 00000000 00000000
0xB0B3881C
SPI2_TXC
00000000 00000000 00000000 00000000
0xB0B38820
SPI2_RXF
00000000 00000000 00000000 00000000
0xB0B38824
SPI2_RXE
00000000 00000000 00000000 00000000
0xB0B38828
SPI2_RXC
00000000 00000000 00000000 00000000
0xB0B3882C
SPI2_FAULTF
00000000 00000000 00000000 00000000
0xB0B38830
SPI2_FAULTC
00000000 00000000 00000000 00000000
0xB0B38834
248
+3
read0
00000000 00000000
SPI2_DMDMAEN
00000000
+0
SPI2_DMCFG
00000001
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-8 Memory layout of the PERI4_SLAVE registers (13 / 16)
Offset
+3
+2
+1
+0
0xB0B38838
SPI2_DMTRP
00000000
SPI2_DMPSEL
00000000
SPI2_DMSTOP
00000000
SPI2_DMSTART
00000000
0xB0B3883C
SPI2_DMBCS
00000000 00000000
SPI2_DMSTATUS
00000000 00000000 00000000 00000000
0xB0B38840
0xB0B38844
SPI2_DMBCC
00000000 00000000
read0
00000000 00000000
SPI2_RXBITCNT
00000000
0xB0B38848
SPI2_RXSHIFT
00000000 00000000 00000000 00000000
0xB0B3884C
SPI2_FIFOCFG
00000000 00000000 00000000 01110111
0xB0B38850
SPI2_TXFIFO0
00000000 00000000 00000000 00000000
0xB0B38854
SPI2_TXFIFO1
00000000 00000000 00000000 00000000
0xB0B38858
SPI2_TXFIFO2
00000000 00000000 00000000 00000000
0xB0B3885C
SPI2_TXFIFO3
00000000 00000000 00000000 00000000
0xB0B38860
SPI2_TXFIFO4
00000000 00000000 00000000 00000000
0xB0B38864
SPI2_TXFIFO5
00000000 00000000 00000000 00000000
0xB0B38868
SPI2_TXFIFO6
00000000 00000000 00000000 00000000
0xB0B3886C
SPI2_TXFIFO7
00000000 00000000 00000000 00000000
0xB0B38870
SPI2_TXFIFO8
00000000 00000000 00000000 00000000
0xB0B38874
SPI2_TXFIFO9
00000000 00000000 00000000 00000000
0xB0B38878
SPI2_TXFIFO10
00000000 00000000 00000000 00000000
0xB0B3887C
SPI2_TXFIFO11
00000000 00000000 00000000 00000000
0xB0B38880
SPI2_TXFIFO12
00000000 00000000 00000000 00000000
0xB0B38884
SPI2_TXFIFO13
00000000 00000000 00000000 00000000
0xB0B38888
SPI2_TXFIFO14
00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
SPI2_TXBITCNT
00000000
249
Data
Shee t
Table 5-8 Memory layout of the PERI4_SLAVE registers (14 / 16)
Offset
+2
+1
+0
0xB0B3888C
SPI2_TXFIFO15
00000000 00000000 00000000 00000000
0xB0B38890
SPI2_RXFIFO0
00000000 00000000 00000000 00000000
0xB0B38894
SPI2_RXFIFO1
00000000 00000000 00000000 00000000
0xB0B38898
SPI2_RXFIFO2
00000000 00000000 00000000 00000000
0xB0B3889C
SPI2_RXFIFO3
00000000 00000000 00000000 00000000
0xB0B388A0
SPI2_RXFIFO4
00000000 00000000 00000000 00000000
0xB0B388A4
SPI2_RXFIFO5
00000000 00000000 00000000 00000000
0xB0B388A8
SPI2_RXFIFO6
00000000 00000000 00000000 00000000
0xB0B388AC
SPI2_RXFIFO7
00000000 00000000 00000000 00000000
0xB0B388B0
SPI2_RXFIFO8
00000000 00000000 00000000 00000000
0xB0B388B4
SPI2_RXFIFO9
00000000 00000000 00000000 00000000
0xB0B388B8
SPI2_RXFIFO10
00000000 00000000 00000000 00000000
0xB0B388BC
SPI2_RXFIFO11
00000000 00000000 00000000 00000000
0xB0B388C0
SPI2_RXFIFO12
00000000 00000000 00000000 00000000
0xB0B388C4
SPI2_RXFIFO13
00000000 00000000 00000000 00000000
0xB0B388C8
SPI2_RXFIFO14
00000000 00000000 00000000 00000000
0xB0B388CC
SPI2_RXFIFO15
00000000 00000000 00000000 00000000
0xB0B388D0B0B388F8
reserved
00000000 00000000 00000000 00000000
0xB0B388FC
SPI2_MID
00000000 00000000 00000000 00000001
0xB0B38900B0BF8FFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0BF9000
250
+3
read0
00000000 00000000
RICFG4_I2S0ECLK
00000000 00000000
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-8 Memory layout of the PERI4_SLAVE registers (15 / 16)
Offset
+3
+2
+1
+0
0xB0BF9004
read0
00000000 00000000
RICFG4_I2S0SCKI
00000000 00000000
0xB0BF9008
read0
00000000 00000000
RICFG4_I2S0SDI
00000000 00000000
0xB0BF900C
read0
00000000 00000000
RICFG4_I2S0WSI
00000000 00000000
0xB0BF9010B0BF901C
reserved
00000000 00000000 00000000 00000000
0xB0BF9020
read0
00000000 00000000
RICFG4_I2S1ECLK
00000000 00000000
0xB0BF9024
read0
00000000 00000000
RICFG4_I2S1SCKI
00000000 00000000
0xB0BF9028
read0
00000000 00000000
RICFG4_I2S1SDI
00000000 00000000
0xB0BF902C
read0
00000000 00000000
RICFG4_I2S1WSI
00000000 00000000
0xB0BF9030B0BF9BFC
reserved
00000000 00000000 00000000 00000000
0xB0BF9C00
read0
00000000 00000000
RICFG4_SPI0CLKI
00000000 00000000
0xB0BF9C04
read0
00000000 00000000
RICFG4_SPI0DATA0I
00000000 00000000
0xB0BF9C08
read0
00000000 00000000
RICFG4_SPI0DATA1I
00000000 00000000
0xB0BF9C0C
read0
00000000 00000000
RICFG4_SPI0MSTART
00000000 00000000
0xB0BF9C10
read0
00000000 00000000
RICFG4_SPI0SSI
00000000 00000000
0xB0BF9C14B0BF9C1C
reserved
00000000 00000000 00000000 00000000
0xB0BF9C20
read0
00000000 00000000
RICFG4_SPI1CLKI
00000000 00000000
0xB0BF9C24
read0
00000000 00000000
RICFG4_SPI1DATA0I
00000000 00000000
0xB0BF9C28
read0
00000000 00000000
RICFG4_SPI1DATA1I
00000000 00000000
0xB0BF9C2C
read0
00000000 00000000
RICFG4_SPI1MSTART
00000000 00000000
0xB0BF9C30
read0
00000000 00000000
RICFG4_SPI1SSI
00000000 00000000
0xB0BF9C34B0BF9C3C
January 30, 2015, MB9EF226_DS707-00004-2v1-E
reserved
00000000 00000000 00000000 00000000
251
Data
Shee t
Table 5-8 Memory layout of the PERI4_SLAVE registers (16 / 16)
Offset
252
+3
+2
+1
+0
0xB0BF9C40
read0
00000000 00000000
RICFG4_SPI2CLKI
00000000 00000000
0xB0BF9C44
read0
00000000 00000000
RICFG4_SPI2DATA0I
00000000 00000000
0xB0BF9C48
read0
00000000 00000000
RICFG4_SPI2DATA1I
00000000 00000000
0xB0BF9C4C
read0
00000000 00000000
RICFG4_SPI2DATA2I
00000000 00000000
0xB0BF9C50
read0
00000000 00000000
RICFG4_SPI2DATA3I
00000000 00000000
0xB0BF9C54
read0
00000000 00000000
RICFG4_SPI2MSTART
00000000 00000000
0xB0BF9C58
read0
00000000 00000000
RICFG4_SPI2SSI
00000000 00000000
0xB0BF9C5CB0BFFC00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0BFFC04
BSU4_BTST
00000000 00000000 00000000 00000000
0xB0BFFC08B0BFFC10
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0BFFC14
BSU4_PEN1
00000000 00000000 00000000 00000000
0xB0BFFC18
BSU4_PEN2
00000000 00000000 00000000 00000000
0xB0BFFC1C
BSU4_PEN3
00000000 00000000 00000000 00000000
0xB0BFFC20
BSU4_PEN4
00000000 00000000 00000000 00000000
0xB0BFFC24
BSU4_PEN5
00000000 00000000 00000000 00000000
0xB0BFFC28
BSU4_PEN6
00000000 00000000 00000000 00000000
0xB0BFFC2C
BSU4_PEN7
00000000 00000000 00000000 00000000
0xB0BFFC30
BSU4_PEN8
00000000 00000000 00000000 00000000
0xB0BFFC34B0BFFFFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (1 / 57)
Offset
+3
+2
+1
0xB0C00000
DMA0_A0
00000000 00001111 00000000 00000000
0xB0C00004
DMA0_B0
00000000 00000000 00110011 01111111
0xB0C00008
DMA0_SA0
00000000 00000000 00000000 00000000
0xB0C0000C
DMA0_DA0
00000000 00000000 00000000 00000000
0xB0C00010
DMA0_C0
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00014
DMA0_D0
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00018
DMA0_SASHDW0
00000000 00000000 00000000 00000000
0xB0C0001C
DMA0_DASHDW0
00000000 00000000 00000000 00000000
0xB0C00020B0C0003C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00040
DMA0_A1
00000000 00001111 00000000 00000000
0xB0C00044
DMA0_B1
00000000 00000000 00110011 01111111
0xB0C00048
DMA0_SA1
00000000 00000000 00000000 00000000
0xB0C0004C
DMA0_DA1
00000000 00000000 00000000 00000000
0xB0C00050
DMA0_C1
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00054
DMA0_D1
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00058
DMA0_SASHDW1
00000000 00000000 00000000 00000000
0xB0C0005C
DMA0_DASHDW1
00000000 00000000 00000000 00000000
0xB0C00060B0C0007C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00080
DMA0_A2
00000000 00001111 00000000 00000000
0xB0C00084
DMA0_B2
00000000 00000000 00110011 01111111
0xB0C00088
DMA0_SA2
00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
253
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (2 / 57)
Offset
254
+3
+2
+1
0xB0C0008C
DMA0_DA2
00000000 00000000 00000000 00000000
0xB0C00090
DMA0_C2
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00094
DMA0_D2
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00098
DMA0_SASHDW2
00000000 00000000 00000000 00000000
0xB0C0009C
DMA0_DASHDW2
00000000 00000000 00000000 00000000
0xB0C000A0B0C000BC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C000C0
DMA0_A3
00000000 00001111 00000000 00000000
0xB0C000C4
DMA0_B3
00000000 00000000 00110011 01111111
0xB0C000C8
DMA0_SA3
00000000 00000000 00000000 00000000
0xB0C000CC
DMA0_DA3
00000000 00000000 00000000 00000000
0xB0C000D0
DMA0_C3
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C000D4
DMA0_D3
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C000D8
DMA0_SASHDW3
00000000 00000000 00000000 00000000
0xB0C000DC
DMA0_DASHDW3
00000000 00000000 00000000 00000000
0xB0C000E0B0C000FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00100
DMA0_A4
00000000 00001111 00000000 00000000
0xB0C00104
DMA0_B4
00000000 00000000 00110011 01111111
0xB0C00108
DMA0_SA4
00000000 00000000 00000000 00000000
0xB0C0010C
DMA0_DA4
00000000 00000000 00000000 00000000
0xB0C00110
DMA0_C4
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00114
DMA0_D4
00000000 XXXXXXXX 00000000 XXXXXXXX
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (3 / 57)
Offset
+3
+2
+1
0xB0C00118
DMA0_SASHDW4
00000000 00000000 00000000 00000000
0xB0C0011C
DMA0_DASHDW4
00000000 00000000 00000000 00000000
0xB0C00120B0C0013C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00140
DMA0_A5
00000000 00001111 00000000 00000000
0xB0C00144
DMA0_B5
00000000 00000000 00110011 01111111
0xB0C00148
DMA0_SA5
00000000 00000000 00000000 00000000
0xB0C0014C
DMA0_DA5
00000000 00000000 00000000 00000000
0xB0C00150
DMA0_C5
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00154
DMA0_D5
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00158
DMA0_SASHDW5
00000000 00000000 00000000 00000000
0xB0C0015C
DMA0_DASHDW5
00000000 00000000 00000000 00000000
0xB0C00160B0C0017C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00180
DMA0_A6
00000000 00001111 00000000 00000000
0xB0C00184
DMA0_B6
00000000 00000000 00110011 01111111
0xB0C00188
DMA0_SA6
00000000 00000000 00000000 00000000
0xB0C0018C
DMA0_DA6
00000000 00000000 00000000 00000000
0xB0C00190
DMA0_C6
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00194
DMA0_D6
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00198
DMA0_SASHDW6
00000000 00000000 00000000 00000000
0xB0C0019C
DMA0_DASHDW6
00000000 00000000 00000000 00000000
0xB0C001A0B0C001BC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
255
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (4 / 57)
Offset
256
+3
+2
+1
0xB0C001C0
DMA0_A7
00000000 00001111 00000000 00000000
0xB0C001C4
DMA0_B7
00000000 00000000 00110011 01111111
0xB0C001C8
DMA0_SA7
00000000 00000000 00000000 00000000
0xB0C001CC
DMA0_DA7
00000000 00000000 00000000 00000000
0xB0C001D0
DMA0_C7
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C001D4
DMA0_D7
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C001D8
DMA0_SASHDW7
00000000 00000000 00000000 00000000
0xB0C001DC
DMA0_DASHDW7
00000000 00000000 00000000 00000000
0xB0C001E0B0C001FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00200
DMA0_A8
00000000 00001111 00000000 00000000
0xB0C00204
DMA0_B8
00000000 00000000 00110011 01111111
0xB0C00208
DMA0_SA8
00000000 00000000 00000000 00000000
0xB0C0020C
DMA0_DA8
00000000 00000000 00000000 00000000
0xB0C00210
DMA0_C8
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00214
DMA0_D8
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00218
DMA0_SASHDW8
00000000 00000000 00000000 00000000
0xB0C0021C
DMA0_DASHDW8
00000000 00000000 00000000 00000000
0xB0C00220B0C0023C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00240
DMA0_A9
00000000 00001111 00000000 00000000
0xB0C00244
DMA0_B9
00000000 00000000 00110011 01111111
0xB0C00248
DMA0_SA9
00000000 00000000 00000000 00000000
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (5 / 57)
Offset
+3
+2
+1
0xB0C0024C
DMA0_DA9
00000000 00000000 00000000 00000000
0xB0C00250
DMA0_C9
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00254
DMA0_D9
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00258
DMA0_SASHDW9
00000000 00000000 00000000 00000000
0xB0C0025C
DMA0_DASHDW9
00000000 00000000 00000000 00000000
0xB0C00260B0C0027C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00280
DMA0_A10
00000000 00001111 00000000 00000000
0xB0C00284
DMA0_B10
00000000 00000000 00110011 01111111
0xB0C00288
DMA0_SA10
00000000 00000000 00000000 00000000
0xB0C0028C
DMA0_DA10
00000000 00000000 00000000 00000000
0xB0C00290
DMA0_C10
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00294
DMA0_D10
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00298
DMA0_SASHDW10
00000000 00000000 00000000 00000000
0xB0C0029C
DMA0_DASHDW10
00000000 00000000 00000000 00000000
0xB0C002A0B0C002BC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C002C0
DMA0_A11
00000000 00001111 00000000 00000000
0xB0C002C4
DMA0_B11
00000000 00000000 00110011 01111111
0xB0C002C8
DMA0_SA11
00000000 00000000 00000000 00000000
0xB0C002CC
DMA0_DA11
00000000 00000000 00000000 00000000
0xB0C002D0
DMA0_C11
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C002D4
DMA0_D11
00000000 XXXXXXXX 00000000 XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
257
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (6 / 57)
Offset
258
+3
+2
+1
0xB0C002D8
DMA0_SASHDW11
00000000 00000000 00000000 00000000
0xB0C002DC
DMA0_DASHDW11
00000000 00000000 00000000 00000000
0xB0C002E0B0C002FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00300
DMA0_A12
00000000 00001111 00000000 00000000
0xB0C00304
DMA0_B12
00000000 00000000 00110011 01111111
0xB0C00308
DMA0_SA12
00000000 00000000 00000000 00000000
0xB0C0030C
DMA0_DA12
00000000 00000000 00000000 00000000
0xB0C00310
DMA0_C12
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00314
DMA0_D12
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00318
DMA0_SASHDW12
00000000 00000000 00000000 00000000
0xB0C0031C
DMA0_DASHDW12
00000000 00000000 00000000 00000000
0xB0C00320B0C0033C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00340
DMA0_A13
00000000 00001111 00000000 00000000
0xB0C00344
DMA0_B13
00000000 00000000 00110011 01111111
0xB0C00348
DMA0_SA13
00000000 00000000 00000000 00000000
0xB0C0034C
DMA0_DA13
00000000 00000000 00000000 00000000
0xB0C00350
DMA0_C13
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00354
DMA0_D13
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00358
DMA0_SASHDW13
00000000 00000000 00000000 00000000
0xB0C0035C
DMA0_DASHDW13
00000000 00000000 00000000 00000000
0xB0C00360B0C0037C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (7 / 57)
Offset
+3
+2
+1
0xB0C00380
DMA0_A14
00000000 00001111 00000000 00000000
0xB0C00384
DMA0_B14
00000000 00000000 00110011 01111111
0xB0C00388
DMA0_SA14
00000000 00000000 00000000 00000000
0xB0C0038C
DMA0_DA14
00000000 00000000 00000000 00000000
0xB0C00390
DMA0_C14
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00394
DMA0_D14
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00398
DMA0_SASHDW14
00000000 00000000 00000000 00000000
0xB0C0039C
DMA0_DASHDW14
00000000 00000000 00000000 00000000
0xB0C003A0B0C003BC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C003C0
DMA0_A15
00000000 00001111 00000000 00000000
0xB0C003C4
DMA0_B15
00000000 00000000 00110011 01111111
0xB0C003C8
DMA0_SA15
00000000 00000000 00000000 00000000
0xB0C003CC
DMA0_DA15
00000000 00000000 00000000 00000000
0xB0C003D0
DMA0_C15
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C003D4
DMA0_D15
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C003D8
DMA0_SASHDW15
00000000 00000000 00000000 00000000
0xB0C003DC
DMA0_DASHDW15
00000000 00000000 00000000 00000000
0xB0C003E0B0C003FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00400
DMA0_A16
00000000 00001111 00000000 00000000
0xB0C00404
DMA0_B16
00000000 00000000 00110011 01111111
0xB0C00408
DMA0_SA16
00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
259
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (8 / 57)
Offset
260
+3
+2
+1
0xB0C0040C
DMA0_DA16
00000000 00000000 00000000 00000000
0xB0C00410
DMA0_C16
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00414
DMA0_D16
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00418
DMA0_SASHDW16
00000000 00000000 00000000 00000000
0xB0C0041C
DMA0_DASHDW16
00000000 00000000 00000000 00000000
0xB0C00420B0C0043C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00440
DMA0_A17
00000000 00001111 00000000 00000000
0xB0C00444
DMA0_B17
00000000 00000000 00110011 01111111
0xB0C00448
DMA0_SA17
00000000 00000000 00000000 00000000
0xB0C0044C
DMA0_DA17
00000000 00000000 00000000 00000000
0xB0C00450
DMA0_C17
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00454
DMA0_D17
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00458
DMA0_SASHDW17
00000000 00000000 00000000 00000000
0xB0C0045C
DMA0_DASHDW17
00000000 00000000 00000000 00000000
0xB0C00460B0C0047C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00480
DMA0_A18
00000000 00001111 00000000 00000000
0xB0C00484
DMA0_B18
00000000 00000000 00110011 01111111
0xB0C00488
DMA0_SA18
00000000 00000000 00000000 00000000
0xB0C0048C
DMA0_DA18
00000000 00000000 00000000 00000000
0xB0C00490
DMA0_C18
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00494
DMA0_D18
00000000 XXXXXXXX 00000000 XXXXXXXX
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (9 / 57)
Offset
+3
+2
+1
0xB0C00498
DMA0_SASHDW18
00000000 00000000 00000000 00000000
0xB0C0049C
DMA0_DASHDW18
00000000 00000000 00000000 00000000
0xB0C004A0B0C004BC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C004C0
DMA0_A19
00000000 00001111 00000000 00000000
0xB0C004C4
DMA0_B19
00000000 00000000 00110011 01111111
0xB0C004C8
DMA0_SA19
00000000 00000000 00000000 00000000
0xB0C004CC
DMA0_DA19
00000000 00000000 00000000 00000000
0xB0C004D0
DMA0_C19
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C004D4
DMA0_D19
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C004D8
DMA0_SASHDW19
00000000 00000000 00000000 00000000
0xB0C004DC
DMA0_DASHDW19
00000000 00000000 00000000 00000000
0xB0C004E0B0C004FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00500
DMA0_A20
00000000 00001111 00000000 00000000
0xB0C00504
DMA0_B20
00000000 00000000 00110011 01111111
0xB0C00508
DMA0_SA20
00000000 00000000 00000000 00000000
0xB0C0050C
DMA0_DA20
00000000 00000000 00000000 00000000
0xB0C00510
DMA0_C20
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00514
DMA0_D20
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00518
DMA0_SASHDW20
00000000 00000000 00000000 00000000
0xB0C0051C
DMA0_DASHDW20
00000000 00000000 00000000 00000000
0xB0C00520B0C0053C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
261
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (10 / 57)
Offset
262
+3
+2
+1
0xB0C00540
DMA0_A21
00000000 00001111 00000000 00000000
0xB0C00544
DMA0_B21
00000000 00000000 00110011 01111111
0xB0C00548
DMA0_SA21
00000000 00000000 00000000 00000000
0xB0C0054C
DMA0_DA21
00000000 00000000 00000000 00000000
0xB0C00550
DMA0_C21
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00554
DMA0_D21
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00558
DMA0_SASHDW21
00000000 00000000 00000000 00000000
0xB0C0055C
DMA0_DASHDW21
00000000 00000000 00000000 00000000
0xB0C00560B0C0057C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00580
DMA0_A22
00000000 00001111 00000000 00000000
0xB0C00584
DMA0_B22
00000000 00000000 00110011 01111111
0xB0C00588
DMA0_SA22
00000000 00000000 00000000 00000000
0xB0C0058C
DMA0_DA22
00000000 00000000 00000000 00000000
0xB0C00590
DMA0_C22
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00594
DMA0_D22
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00598
DMA0_SASHDW22
00000000 00000000 00000000 00000000
0xB0C0059C
DMA0_DASHDW22
00000000 00000000 00000000 00000000
0xB0C005A0B0C005BC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C005C0
DMA0_A23
00000000 00001111 00000000 00000000
0xB0C005C4
DMA0_B23
00000000 00000000 00110011 01111111
0xB0C005C8
DMA0_SA23
00000000 00000000 00000000 00000000
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (11 / 57)
Offset
+3
+2
+1
0xB0C005CC
DMA0_DA23
00000000 00000000 00000000 00000000
0xB0C005D0
DMA0_C23
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C005D4
DMA0_D23
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C005D8
DMA0_SASHDW23
00000000 00000000 00000000 00000000
0xB0C005DC
DMA0_DASHDW23
00000000 00000000 00000000 00000000
0xB0C005E0B0C005FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00600
DMA0_A24
00000000 00001111 00000000 00000000
0xB0C00604
DMA0_B24
00000000 00000000 00110011 01111111
0xB0C00608
DMA0_SA24
00000000 00000000 00000000 00000000
0xB0C0060C
DMA0_DA24
00000000 00000000 00000000 00000000
0xB0C00610
DMA0_C24
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00614
DMA0_D24
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00618
DMA0_SASHDW24
00000000 00000000 00000000 00000000
0xB0C0061C
DMA0_DASHDW24
00000000 00000000 00000000 00000000
0xB0C00620B0C0063C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00640
DMA0_A25
00000000 00001111 00000000 00000000
0xB0C00644
DMA0_B25
00000000 00000000 00110011 01111111
0xB0C00648
DMA0_SA25
00000000 00000000 00000000 00000000
0xB0C0064C
DMA0_DA25
00000000 00000000 00000000 00000000
0xB0C00650
DMA0_C25
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00654
DMA0_D25
00000000 XXXXXXXX 00000000 XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
263
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (12 / 57)
Offset
264
+3
+2
+1
0xB0C00658
DMA0_SASHDW25
00000000 00000000 00000000 00000000
0xB0C0065C
DMA0_DASHDW25
00000000 00000000 00000000 00000000
0xB0C00660B0C0067C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00680
DMA0_A26
00000000 00001111 00000000 00000000
0xB0C00684
DMA0_B26
00000000 00000000 00110011 01111111
0xB0C00688
DMA0_SA26
00000000 00000000 00000000 00000000
0xB0C0068C
DMA0_DA26
00000000 00000000 00000000 00000000
0xB0C00690
DMA0_C26
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00694
DMA0_D26
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00698
DMA0_SASHDW26
00000000 00000000 00000000 00000000
0xB0C0069C
DMA0_DASHDW26
00000000 00000000 00000000 00000000
0xB0C006A0B0C006BC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C006C0
DMA0_A27
00000000 00001111 00000000 00000000
0xB0C006C4
DMA0_B27
00000000 00000000 00110011 01111111
0xB0C006C8
DMA0_SA27
00000000 00000000 00000000 00000000
0xB0C006CC
DMA0_DA27
00000000 00000000 00000000 00000000
0xB0C006D0
DMA0_C27
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C006D4
DMA0_D27
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C006D8
DMA0_SASHDW27
00000000 00000000 00000000 00000000
0xB0C006DC
DMA0_DASHDW27
00000000 00000000 00000000 00000000
0xB0C006E0B0C006FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (13 / 57)
Offset
+3
+2
+1
0xB0C00700
DMA0_A28
00000000 00001111 00000000 00000000
0xB0C00704
DMA0_B28
00000000 00000000 00110011 01111111
0xB0C00708
DMA0_SA28
00000000 00000000 00000000 00000000
0xB0C0070C
DMA0_DA28
00000000 00000000 00000000 00000000
0xB0C00710
DMA0_C28
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00714
DMA0_D28
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00718
DMA0_SASHDW28
00000000 00000000 00000000 00000000
0xB0C0071C
DMA0_DASHDW28
00000000 00000000 00000000 00000000
0xB0C00720B0C0073C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00740
DMA0_A29
00000000 00001111 00000000 00000000
0xB0C00744
DMA0_B29
00000000 00000000 00110011 01111111
0xB0C00748
DMA0_SA29
00000000 00000000 00000000 00000000
0xB0C0074C
DMA0_DA29
00000000 00000000 00000000 00000000
0xB0C00750
DMA0_C29
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00754
DMA0_D29
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00758
DMA0_SASHDW29
00000000 00000000 00000000 00000000
0xB0C0075C
DMA0_DASHDW29
00000000 00000000 00000000 00000000
0xB0C00760B0C0077C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00780
DMA0_A30
00000000 00001111 00000000 00000000
0xB0C00784
DMA0_B30
00000000 00000000 00110011 01111111
0xB0C00788
DMA0_SA30
00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
265
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (14 / 57)
Offset
266
+3
+2
+1
0xB0C0078C
DMA0_DA30
00000000 00000000 00000000 00000000
0xB0C00790
DMA0_C30
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00794
DMA0_D30
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00798
DMA0_SASHDW30
00000000 00000000 00000000 00000000
0xB0C0079C
DMA0_DASHDW30
00000000 00000000 00000000 00000000
0xB0C007A0B0C007BC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C007C0
DMA0_A31
00000000 00001111 00000000 00000000
0xB0C007C4
DMA0_B31
00000000 00000000 00110011 01111111
0xB0C007C8
DMA0_SA31
00000000 00000000 00000000 00000000
0xB0C007CC
DMA0_DA31
00000000 00000000 00000000 00000000
0xB0C007D0
DMA0_C31
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C007D4
DMA0_D31
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C007D8
DMA0_SASHDW31
00000000 00000000 00000000 00000000
0xB0C007DC
DMA0_DASHDW31
00000000 00000000 00000000 00000000
0xB0C007E0B0C007FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00800
DMA0_A32
00000000 00001111 00000000 00000000
0xB0C00804
DMA0_B32
00000000 00000000 00110011 01111111
0xB0C00808
DMA0_SA32
00000000 00000000 00000000 00000000
0xB0C0080C
DMA0_DA32
00000000 00000000 00000000 00000000
0xB0C00810
DMA0_C32
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00814
DMA0_D32
00000000 XXXXXXXX 00000000 XXXXXXXX
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (15 / 57)
Offset
+3
+2
+1
0xB0C00818
DMA0_SASHDW32
00000000 00000000 00000000 00000000
0xB0C0081C
DMA0_DASHDW32
00000000 00000000 00000000 00000000
0xB0C00820B0C0083C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00840
DMA0_A33
00000000 00001111 00000000 00000000
0xB0C00844
DMA0_B33
00000000 00000000 00110011 01111111
0xB0C00848
DMA0_SA33
00000000 00000000 00000000 00000000
0xB0C0084C
DMA0_DA33
00000000 00000000 00000000 00000000
0xB0C00850
DMA0_C33
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00854
DMA0_D33
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00858
DMA0_SASHDW33
00000000 00000000 00000000 00000000
0xB0C0085C
DMA0_DASHDW33
00000000 00000000 00000000 00000000
0xB0C00860B0C0087C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00880
DMA0_A34
00000000 00001111 00000000 00000000
0xB0C00884
DMA0_B34
00000000 00000000 00110011 01111111
0xB0C00888
DMA0_SA34
00000000 00000000 00000000 00000000
0xB0C0088C
DMA0_DA34
00000000 00000000 00000000 00000000
0xB0C00890
DMA0_C34
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00894
DMA0_D34
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00898
DMA0_SASHDW34
00000000 00000000 00000000 00000000
0xB0C0089C
DMA0_DASHDW34
00000000 00000000 00000000 00000000
0xB0C008A0B0C008BC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
267
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (16 / 57)
Offset
268
+3
+2
+1
0xB0C008C0
DMA0_A35
00000000 00001111 00000000 00000000
0xB0C008C4
DMA0_B35
00000000 00000000 00110011 01111111
0xB0C008C8
DMA0_SA35
00000000 00000000 00000000 00000000
0xB0C008CC
DMA0_DA35
00000000 00000000 00000000 00000000
0xB0C008D0
DMA0_C35
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C008D4
DMA0_D35
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C008D8
DMA0_SASHDW35
00000000 00000000 00000000 00000000
0xB0C008DC
DMA0_DASHDW35
00000000 00000000 00000000 00000000
0xB0C008E0B0C008FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00900
DMA0_A36
00000000 00001111 00000000 00000000
0xB0C00904
DMA0_B36
00000000 00000000 00110011 01111111
0xB0C00908
DMA0_SA36
00000000 00000000 00000000 00000000
0xB0C0090C
DMA0_DA36
00000000 00000000 00000000 00000000
0xB0C00910
DMA0_C36
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00914
DMA0_D36
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00918
DMA0_SASHDW36
00000000 00000000 00000000 00000000
0xB0C0091C
DMA0_DASHDW36
00000000 00000000 00000000 00000000
0xB0C00920B0C0093C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00940
DMA0_A37
00000000 00001111 00000000 00000000
0xB0C00944
DMA0_B37
00000000 00000000 00110011 01111111
0xB0C00948
DMA0_SA37
00000000 00000000 00000000 00000000
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (17 / 57)
Offset
+3
+2
+1
0xB0C0094C
DMA0_DA37
00000000 00000000 00000000 00000000
0xB0C00950
DMA0_C37
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00954
DMA0_D37
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00958
DMA0_SASHDW37
00000000 00000000 00000000 00000000
0xB0C0095C
DMA0_DASHDW37
00000000 00000000 00000000 00000000
0xB0C00960B0C0097C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00980
DMA0_A38
00000000 00001111 00000000 00000000
0xB0C00984
DMA0_B38
00000000 00000000 00110011 01111111
0xB0C00988
DMA0_SA38
00000000 00000000 00000000 00000000
0xB0C0098C
DMA0_DA38
00000000 00000000 00000000 00000000
0xB0C00990
DMA0_C38
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00994
DMA0_D38
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00998
DMA0_SASHDW38
00000000 00000000 00000000 00000000
0xB0C0099C
DMA0_DASHDW38
00000000 00000000 00000000 00000000
0xB0C009A0B0C009BC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C009C0
DMA0_A39
00000000 00001111 00000000 00000000
0xB0C009C4
DMA0_B39
00000000 00000000 00110011 01111111
0xB0C009C8
DMA0_SA39
00000000 00000000 00000000 00000000
0xB0C009CC
DMA0_DA39
00000000 00000000 00000000 00000000
0xB0C009D0
DMA0_C39
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C009D4
DMA0_D39
00000000 XXXXXXXX 00000000 XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
269
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (18 / 57)
Offset
270
+3
+2
+1
0xB0C009D8
DMA0_SASHDW39
00000000 00000000 00000000 00000000
0xB0C009DC
DMA0_DASHDW39
00000000 00000000 00000000 00000000
0xB0C009E0B0C009FC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00A00
DMA0_A40
00000000 00001111 00000000 00000000
0xB0C00A04
DMA0_B40
00000000 00000000 00110011 01111111
0xB0C00A08
DMA0_SA40
00000000 00000000 00000000 00000000
0xB0C00A0C
DMA0_DA40
00000000 00000000 00000000 00000000
0xB0C00A10
DMA0_C40
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00A14
DMA0_D40
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00A18
DMA0_SASHDW40
00000000 00000000 00000000 00000000
0xB0C00A1C
DMA0_DASHDW40
00000000 00000000 00000000 00000000
0xB0C00A20B0C00A3C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00A40
DMA0_A41
00000000 00001111 00000000 00000000
0xB0C00A44
DMA0_B41
00000000 00000000 00110011 01111111
0xB0C00A48
DMA0_SA41
00000000 00000000 00000000 00000000
0xB0C00A4C
DMA0_DA41
00000000 00000000 00000000 00000000
0xB0C00A50
DMA0_C41
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00A54
DMA0_D41
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00A58
DMA0_SASHDW41
00000000 00000000 00000000 00000000
0xB0C00A5C
DMA0_DASHDW41
00000000 00000000 00000000 00000000
0xB0C00A60B0C00A7C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (19 / 57)
Offset
+3
+2
+1
0xB0C00A80
DMA0_A42
00000000 00001111 00000000 00000000
0xB0C00A84
DMA0_B42
00000000 00000000 00110011 01111111
0xB0C00A88
DMA0_SA42
00000000 00000000 00000000 00000000
0xB0C00A8C
DMA0_DA42
00000000 00000000 00000000 00000000
0xB0C00A90
DMA0_C42
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00A94
DMA0_D42
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00A98
DMA0_SASHDW42
00000000 00000000 00000000 00000000
0xB0C00A9C
DMA0_DASHDW42
00000000 00000000 00000000 00000000
0xB0C00AA0B0C00ABC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00AC0
DMA0_A43
00000000 00001111 00000000 00000000
0xB0C00AC4
DMA0_B43
00000000 00000000 00110011 01111111
0xB0C00AC8
DMA0_SA43
00000000 00000000 00000000 00000000
0xB0C00ACC
DMA0_DA43
00000000 00000000 00000000 00000000
0xB0C00AD0
DMA0_C43
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00AD4
DMA0_D43
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00AD8
DMA0_SASHDW43
00000000 00000000 00000000 00000000
0xB0C00ADC
DMA0_DASHDW43
00000000 00000000 00000000 00000000
0xB0C00AE0B0C00AFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00B00
DMA0_A44
00000000 00001111 00000000 00000000
0xB0C00B04
DMA0_B44
00000000 00000000 00110011 01111111
0xB0C00B08
DMA0_SA44
00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
271
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (20 / 57)
Offset
272
+3
+2
+1
0xB0C00B0C
DMA0_DA44
00000000 00000000 00000000 00000000
0xB0C00B10
DMA0_C44
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00B14
DMA0_D44
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00B18
DMA0_SASHDW44
00000000 00000000 00000000 00000000
0xB0C00B1C
DMA0_DASHDW44
00000000 00000000 00000000 00000000
0xB0C00B20B0C00B3C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00B40
DMA0_A45
00000000 00001111 00000000 00000000
0xB0C00B44
DMA0_B45
00000000 00000000 00110011 01111111
0xB0C00B48
DMA0_SA45
00000000 00000000 00000000 00000000
0xB0C00B4C
DMA0_DA45
00000000 00000000 00000000 00000000
0xB0C00B50
DMA0_C45
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00B54
DMA0_D45
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00B58
DMA0_SASHDW45
00000000 00000000 00000000 00000000
0xB0C00B5C
DMA0_DASHDW45
00000000 00000000 00000000 00000000
0xB0C00B60B0C00B7C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00B80
DMA0_A46
00000000 00001111 00000000 00000000
0xB0C00B84
DMA0_B46
00000000 00000000 00110011 01111111
0xB0C00B88
DMA0_SA46
00000000 00000000 00000000 00000000
0xB0C00B8C
DMA0_DA46
00000000 00000000 00000000 00000000
0xB0C00B90
DMA0_C46
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00B94
DMA0_D46
00000000 XXXXXXXX 00000000 XXXXXXXX
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (21 / 57)
Offset
+3
+2
+1
0xB0C00B98
DMA0_SASHDW46
00000000 00000000 00000000 00000000
0xB0C00B9C
DMA0_DASHDW46
00000000 00000000 00000000 00000000
0xB0C00BA0B0C00BBC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00BC0
DMA0_A47
00000000 00001111 00000000 00000000
0xB0C00BC4
DMA0_B47
00000000 00000000 00110011 01111111
0xB0C00BC8
DMA0_SA47
00000000 00000000 00000000 00000000
0xB0C00BCC
DMA0_DA47
00000000 00000000 00000000 00000000
0xB0C00BD0
DMA0_C47
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00BD4
DMA0_D47
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00BD8
DMA0_SASHDW47
00000000 00000000 00000000 00000000
0xB0C00BDC
DMA0_DASHDW47
00000000 00000000 00000000 00000000
0xB0C00BE0B0C00BFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00C00
DMA0_A48
00000000 00001111 00000000 00000000
0xB0C00C04
DMA0_B48
00000000 00000000 00110011 01111111
0xB0C00C08
DMA0_SA48
00000000 00000000 00000000 00000000
0xB0C00C0C
DMA0_DA48
00000000 00000000 00000000 00000000
0xB0C00C10
DMA0_C48
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00C14
DMA0_D48
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00C18
DMA0_SASHDW48
00000000 00000000 00000000 00000000
0xB0C00C1C
DMA0_DASHDW48
00000000 00000000 00000000 00000000
0xB0C00C20B0C00C3C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
273
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (22 / 57)
Offset
274
+3
+2
+1
0xB0C00C40
DMA0_A49
00000000 00001111 00000000 00000000
0xB0C00C44
DMA0_B49
00000000 00000000 00110011 01111111
0xB0C00C48
DMA0_SA49
00000000 00000000 00000000 00000000
0xB0C00C4C
DMA0_DA49
00000000 00000000 00000000 00000000
0xB0C00C50
DMA0_C49
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00C54
DMA0_D49
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00C58
DMA0_SASHDW49
00000000 00000000 00000000 00000000
0xB0C00C5C
DMA0_DASHDW49
00000000 00000000 00000000 00000000
0xB0C00C60B0C00C7C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00C80
DMA0_A50
00000000 00001111 00000000 00000000
0xB0C00C84
DMA0_B50
00000000 00000000 00110011 01111111
0xB0C00C88
DMA0_SA50
00000000 00000000 00000000 00000000
0xB0C00C8C
DMA0_DA50
00000000 00000000 00000000 00000000
0xB0C00C90
DMA0_C50
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00C94
DMA0_D50
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00C98
DMA0_SASHDW50
00000000 00000000 00000000 00000000
0xB0C00C9C
DMA0_DASHDW50
00000000 00000000 00000000 00000000
0xB0C00CA0B0C00CBC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00CC0
DMA0_A51
00000000 00001111 00000000 00000000
0xB0C00CC4
DMA0_B51
00000000 00000000 00110011 01111111
0xB0C00CC8
DMA0_SA51
00000000 00000000 00000000 00000000
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (23 / 57)
Offset
+3
+2
+1
0xB0C00CCC
DMA0_DA51
00000000 00000000 00000000 00000000
0xB0C00CD0
DMA0_C51
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00CD4
DMA0_D51
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00CD8
DMA0_SASHDW51
00000000 00000000 00000000 00000000
0xB0C00CDC
DMA0_DASHDW51
00000000 00000000 00000000 00000000
0xB0C00CE0B0C00CFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00D00
DMA0_A52
00000000 00001111 00000000 00000000
0xB0C00D04
DMA0_B52
00000000 00000000 00110011 01111111
0xB0C00D08
DMA0_SA52
00000000 00000000 00000000 00000000
0xB0C00D0C
DMA0_DA52
00000000 00000000 00000000 00000000
0xB0C00D10
DMA0_C52
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00D14
DMA0_D52
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00D18
DMA0_SASHDW52
00000000 00000000 00000000 00000000
0xB0C00D1C
DMA0_DASHDW52
00000000 00000000 00000000 00000000
0xB0C00D20B0C00D3C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00D40
DMA0_A53
00000000 00001111 00000000 00000000
0xB0C00D44
DMA0_B53
00000000 00000000 00110011 01111111
0xB0C00D48
DMA0_SA53
00000000 00000000 00000000 00000000
0xB0C00D4C
DMA0_DA53
00000000 00000000 00000000 00000000
0xB0C00D50
DMA0_C53
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00D54
DMA0_D53
00000000 XXXXXXXX 00000000 XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
275
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (24 / 57)
Offset
276
+3
+2
+1
0xB0C00D58
DMA0_SASHDW53
00000000 00000000 00000000 00000000
0xB0C00D5C
DMA0_DASHDW53
00000000 00000000 00000000 00000000
0xB0C00D60B0C00D7C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00D80
DMA0_A54
00000000 00001111 00000000 00000000
0xB0C00D84
DMA0_B54
00000000 00000000 00110011 01111111
0xB0C00D88
DMA0_SA54
00000000 00000000 00000000 00000000
0xB0C00D8C
DMA0_DA54
00000000 00000000 00000000 00000000
0xB0C00D90
DMA0_C54
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00D94
DMA0_D54
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00D98
DMA0_SASHDW54
00000000 00000000 00000000 00000000
0xB0C00D9C
DMA0_DASHDW54
00000000 00000000 00000000 00000000
0xB0C00DA0B0C00DBC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00DC0
DMA0_A55
00000000 00001111 00000000 00000000
0xB0C00DC4
DMA0_B55
00000000 00000000 00110011 01111111
0xB0C00DC8
DMA0_SA55
00000000 00000000 00000000 00000000
0xB0C00DCC
DMA0_DA55
00000000 00000000 00000000 00000000
0xB0C00DD0
DMA0_C55
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00DD4
DMA0_D55
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00DD8
DMA0_SASHDW55
00000000 00000000 00000000 00000000
0xB0C00DDC
DMA0_DASHDW55
00000000 00000000 00000000 00000000
0xB0C00DE0B0C00DFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (25 / 57)
Offset
+3
+2
+1
0xB0C00E00
DMA0_A56
00000000 00001111 00000000 00000000
0xB0C00E04
DMA0_B56
00000000 00000000 00110011 01111111
0xB0C00E08
DMA0_SA56
00000000 00000000 00000000 00000000
0xB0C00E0C
DMA0_DA56
00000000 00000000 00000000 00000000
0xB0C00E10
DMA0_C56
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00E14
DMA0_D56
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00E18
DMA0_SASHDW56
00000000 00000000 00000000 00000000
0xB0C00E1C
DMA0_DASHDW56
00000000 00000000 00000000 00000000
0xB0C00E20B0C00E3C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00E40
DMA0_A57
00000000 00001111 00000000 00000000
0xB0C00E44
DMA0_B57
00000000 00000000 00110011 01111111
0xB0C00E48
DMA0_SA57
00000000 00000000 00000000 00000000
0xB0C00E4C
DMA0_DA57
00000000 00000000 00000000 00000000
0xB0C00E50
DMA0_C57
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00E54
DMA0_D57
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00E58
DMA0_SASHDW57
00000000 00000000 00000000 00000000
0xB0C00E5C
DMA0_DASHDW57
00000000 00000000 00000000 00000000
0xB0C00E60B0C00E7C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00E80
DMA0_A58
00000000 00001111 00000000 00000000
0xB0C00E84
DMA0_B58
00000000 00000000 00110011 01111111
0xB0C00E88
DMA0_SA58
00000000 00000000 00000000 00000000
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
277
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (26 / 57)
Offset
278
+3
+2
+1
0xB0C00E8C
DMA0_DA58
00000000 00000000 00000000 00000000
0xB0C00E90
DMA0_C58
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00E94
DMA0_D58
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00E98
DMA0_SASHDW58
00000000 00000000 00000000 00000000
0xB0C00E9C
DMA0_DASHDW58
00000000 00000000 00000000 00000000
0xB0C00EA0B0C00EBC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00EC0
DMA0_A59
00000000 00001111 00000000 00000000
0xB0C00EC4
DMA0_B59
00000000 00000000 00110011 01111111
0xB0C00EC8
DMA0_SA59
00000000 00000000 00000000 00000000
0xB0C00ECC
DMA0_DA59
00000000 00000000 00000000 00000000
0xB0C00ED0
DMA0_C59
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00ED4
DMA0_D59
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00ED8
DMA0_SASHDW59
00000000 00000000 00000000 00000000
0xB0C00EDC
DMA0_DASHDW59
00000000 00000000 00000000 00000000
0xB0C00EE0B0C00EFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00F00
DMA0_A60
00000000 00001111 00000000 00000000
0xB0C00F04
DMA0_B60
00000000 00000000 00110011 01111111
0xB0C00F08
DMA0_SA60
00000000 00000000 00000000 00000000
0xB0C00F0C
DMA0_DA60
00000000 00000000 00000000 00000000
0xB0C00F10
DMA0_C60
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00F14
DMA0_D60
00000000 XXXXXXXX 00000000 XXXXXXXX
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (27 / 57)
Offset
+3
+2
+1
0xB0C00F18
DMA0_SASHDW60
00000000 00000000 00000000 00000000
0xB0C00F1C
DMA0_DASHDW60
00000000 00000000 00000000 00000000
0xB0C00F20B0C00F3C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00F40
DMA0_A61
00000000 00001111 00000000 00000000
0xB0C00F44
DMA0_B61
00000000 00000000 00110011 01111111
0xB0C00F48
DMA0_SA61
00000000 00000000 00000000 00000000
0xB0C00F4C
DMA0_DA61
00000000 00000000 00000000 00000000
0xB0C00F50
DMA0_C61
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00F54
DMA0_D61
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00F58
DMA0_SASHDW61
00000000 00000000 00000000 00000000
0xB0C00F5C
DMA0_DASHDW61
00000000 00000000 00000000 00000000
0xB0C00F60B0C00F7C
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C00F80
DMA0_A62
00000000 00001111 00000000 00000000
0xB0C00F84
DMA0_B62
00000000 00000000 00110011 01111111
0xB0C00F88
DMA0_SA62
00000000 00000000 00000000 00000000
0xB0C00F8C
DMA0_DA62
00000000 00000000 00000000 00000000
0xB0C00F90
DMA0_C62
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00F94
DMA0_D62
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00F98
DMA0_SASHDW62
00000000 00000000 00000000 00000000
0xB0C00F9C
DMA0_DASHDW62
00000000 00000000 00000000 00000000
0xB0C00FA0B0C00FBC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
279
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (28 / 57)
Offset
280
+3
+2
+1
0xB0C00FC0
DMA0_A63
00000000 00001111 00000000 00000000
0xB0C00FC4
DMA0_B63
00000000 00000000 00110011 01111111
0xB0C00FC8
DMA0_SA63
00000000 00000000 00000000 00000000
0xB0C00FCC
DMA0_DA63
00000000 00000000 00000000 00000000
0xB0C00FD0
DMA0_C63
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C00FD4
DMA0_D63
00000000 XXXXXXXX 00000000 XXXXXXXX
0xB0C00FD8
DMA0_SASHDW63
00000000 00000000 00000000 00000000
0xB0C00FDC
DMA0_DASHDW63
00000000 00000000 00000000 00000000
0xB0C00FE0B0C00FFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C01000
DMA0_R
01000000 XXXXXXXX XXXXXXXX 00000001
0xB0C01004
DMA0_DIRQ1
00000000 00000000 00000000 00000000
0xB0C01008
DMA0_DIRQ2
00000000 00000000 00000000 00000000
0xB0C0100C
DMA0_EDIRQ1
00000000 00000000 00000000 00000000
0xB0C01010
DMA0_EDIRQ2
00000000 00000000 00000000 00000000
0xB0C01014
DMA0_ID
00000000 00000000 00000000 00000000
0xB0C01018B0C01FFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02000
DMA0_CMECIC0
00000000 00000000 XXXXXXXX 00000000
0xB0C02004
DMA0_CMECIC1
00000000 00000000 XXXXXXXX 00000000
0xB0C02008
DMA0_CMECIC2
00000000 00000000 XXXXXXXX 00000000
0xB0C0200C
DMA0_CMECIC3
00000000 00000000 XXXXXXXX 00000000
0xB0C02010
DMA0_CMECIC4
00000000 00000000 XXXXXXXX 00000000
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (29 / 57)
Offset
+3
+2
+1
0xB0C02014
DMA0_CMECIC5
00000000 00000000 XXXXXXXX 00000000
0xB0C02018
DMA0_CMECIC6
00000000 00000000 XXXXXXXX 00000000
0xB0C0201C
DMA0_CMECIC7
00000000 00000000 XXXXXXXX 00000000
0xB0C02020
DMA0_CMICIC0
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02024
DMA0_CMICIC1
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02028
DMA0_CMICIC2
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0202C
DMA0_CMICIC3
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02030
DMA0_CMICIC4
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02034
DMA0_CMICIC5
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02038
DMA0_CMICIC6
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0203C
DMA0_CMICIC7
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02040
DMA0_CMICIC8
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02044
DMA0_CMICIC9
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02048
DMA0_CMICIC10
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0204C
DMA0_CMICIC11
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02050
DMA0_CMICIC12
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02054
DMA0_CMICIC13
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02058
DMA0_CMICIC14
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0205C
DMA0_CMICIC15
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02060
DMA0_CMICIC16
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02064
DMA0_CMICIC17
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
281
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (30 / 57)
Offset
282
+3
+2
+1
0xB0C02068
DMA0_CMICIC18
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0206C
DMA0_CMICIC19
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02070
DMA0_CMICIC20
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02074
DMA0_CMICIC21
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02078
DMA0_CMICIC22
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0207C
DMA0_CMICIC23
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02080
DMA0_CMICIC24
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02084
DMA0_CMICIC25
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02088
DMA0_CMICIC26
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0208C
DMA0_CMICIC27
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02090
DMA0_CMICIC28
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02094
DMA0_CMICIC29
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02098
DMA0_CMICIC30
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0209C
DMA0_CMICIC31
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020A0
DMA0_CMICIC32
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020A4
DMA0_CMICIC33
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020A8
DMA0_CMICIC34
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020AC
DMA0_CMICIC35
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020B0
DMA0_CMICIC36
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020B4
DMA0_CMICIC37
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020B8
DMA0_CMICIC38
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (31 / 57)
Offset
+3
+2
+1
0xB0C020BC
DMA0_CMICIC39
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020C0
DMA0_CMICIC40
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020C4
DMA0_CMICIC41
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020C8
DMA0_CMICIC42
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020CC
DMA0_CMICIC43
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020D0
DMA0_CMICIC44
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020D4
DMA0_CMICIC45
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020D8
DMA0_CMICIC46
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020DC
DMA0_CMICIC47
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020E0
DMA0_CMICIC48
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020E4
DMA0_CMICIC49
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020E8
DMA0_CMICIC50
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020EC
DMA0_CMICIC51
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020F0
DMA0_CMICIC52
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020F4
DMA0_CMICIC53
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020F8
DMA0_CMICIC54
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C020FC
DMA0_CMICIC55
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02100
DMA0_CMICIC56
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02104
DMA0_CMICIC57
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02108
DMA0_CMICIC58
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0210C
DMA0_CMICIC59
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
283
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (32 / 57)
Offset
284
+3
+2
+1
0xB0C02110
DMA0_CMICIC60
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02114
DMA0_CMICIC61
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02118
DMA0_CMICIC62
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0211C
DMA0_CMICIC63
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02120
DMA0_CMICIC64
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02124
DMA0_CMICIC65
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02128
DMA0_CMICIC66
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0212C
DMA0_CMICIC67
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02130
DMA0_CMICIC68
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02134
DMA0_CMICIC69
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02138
DMA0_CMICIC70
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0213C
DMA0_CMICIC71
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02140
DMA0_CMICIC72
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02144
DMA0_CMICIC73
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02148
DMA0_CMICIC74
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0214C
DMA0_CMICIC75
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02150
DMA0_CMICIC76
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02154
DMA0_CMICIC77
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02158
DMA0_CMICIC78
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0215C
DMA0_CMICIC79
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02160
DMA0_CMICIC80
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (33 / 57)
Offset
+3
+2
+1
0xB0C02164
DMA0_CMICIC81
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02168
DMA0_CMICIC82
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0216C
DMA0_CMICIC83
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02170
DMA0_CMICIC84
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02174
DMA0_CMICIC85
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02178
DMA0_CMICIC86
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0217C
DMA0_CMICIC87
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02180
DMA0_CMICIC88
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02184
DMA0_CMICIC89
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02188
DMA0_CMICIC90
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0218C
DMA0_CMICIC91
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02190
DMA0_CMICIC92
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02194
DMA0_CMICIC93
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02198
DMA0_CMICIC94
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0219C
DMA0_CMICIC95
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021A0
DMA0_CMICIC96
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021A4
DMA0_CMICIC97
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021A8
DMA0_CMICIC98
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021AC
DMA0_CMICIC99
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021B0
DMA0_CMICIC100
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021B4
DMA0_CMICIC101
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
285
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (34 / 57)
Offset
286
+3
+2
+1
0xB0C021B8
DMA0_CMICIC102
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021BC
DMA0_CMICIC103
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021C0
DMA0_CMICIC104
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021C4
DMA0_CMICIC105
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021C8
DMA0_CMICIC106
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021CC
DMA0_CMICIC107
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021D0
DMA0_CMICIC108
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021D4
DMA0_CMICIC109
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021D8
DMA0_CMICIC110
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021DC
DMA0_CMICIC111
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021E0
DMA0_CMICIC112
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021E4
DMA0_CMICIC113
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021E8
DMA0_CMICIC114
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021EC
DMA0_CMICIC115
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021F0
DMA0_CMICIC116
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021F4
DMA0_CMICIC117
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021F8
DMA0_CMICIC118
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C021FC
DMA0_CMICIC119
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02200
DMA0_CMICIC120
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02204
DMA0_CMICIC121
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02208
DMA0_CMICIC122
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (35 / 57)
Offset
+3
+2
+1
0xB0C0220C
DMA0_CMICIC123
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02210
DMA0_CMICIC124
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02214
DMA0_CMICIC125
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02218
DMA0_CMICIC126
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0221C
DMA0_CMICIC127
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02220
DMA0_CMICIC128
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02224
DMA0_CMICIC129
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02228
DMA0_CMICIC130
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0222C
DMA0_CMICIC131
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02230
DMA0_CMICIC132
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02234
DMA0_CMICIC133
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02238
DMA0_CMICIC134
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0223C
DMA0_CMICIC135
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02240
DMA0_CMICIC136
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02244
DMA0_CMICIC137
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02248
DMA0_CMICIC138
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0224C
DMA0_CMICIC139
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02250
DMA0_CMICIC140
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02254
DMA0_CMICIC141
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02258
DMA0_CMICIC142
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0225C
DMA0_CMICIC143
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
287
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (36 / 57)
Offset
288
+3
+2
+1
0xB0C02260
DMA0_CMICIC144
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02264
DMA0_CMICIC145
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02268
DMA0_CMICIC146
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0226C
DMA0_CMICIC147
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02270
DMA0_CMICIC148
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02274
DMA0_CMICIC149
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02278
DMA0_CMICIC150
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0227C
DMA0_CMICIC151
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02280
DMA0_CMICIC152
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02284
DMA0_CMICIC153
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02288
DMA0_CMICIC154
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0228C
DMA0_CMICIC155
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02290
DMA0_CMICIC156
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02294
DMA0_CMICIC157
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02298
DMA0_CMICIC158
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0229C
DMA0_CMICIC159
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022A0
DMA0_CMICIC160
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022A4
DMA0_CMICIC161
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022A8
DMA0_CMICIC162
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022AC
DMA0_CMICIC163
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022B0
DMA0_CMICIC164
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (37 / 57)
Offset
+3
+2
+1
0xB0C022B4
DMA0_CMICIC165
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022B8
DMA0_CMICIC166
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022BC
DMA0_CMICIC167
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022C0
DMA0_CMICIC168
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022C4
DMA0_CMICIC169
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022C8
DMA0_CMICIC170
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022CC
DMA0_CMICIC171
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022D0
DMA0_CMICIC172
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022D4
DMA0_CMICIC173
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022D8
DMA0_CMICIC174
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022DC
DMA0_CMICIC175
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022E0
DMA0_CMICIC176
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022E4
DMA0_CMICIC177
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022E8
DMA0_CMICIC178
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022EC
DMA0_CMICIC179
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022F0
DMA0_CMICIC180
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022F4
DMA0_CMICIC181
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022F8
DMA0_CMICIC182
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C022FC
DMA0_CMICIC183
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02300
DMA0_CMICIC184
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02304
DMA0_CMICIC185
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
289
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (38 / 57)
Offset
290
+3
+2
+1
0xB0C02308
DMA0_CMICIC186
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0230C
DMA0_CMICIC187
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02310
DMA0_CMICIC188
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02314
DMA0_CMICIC189
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02318
DMA0_CMICIC190
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0231C
DMA0_CMICIC191
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02320
DMA0_CMICIC192
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02324
DMA0_CMICIC193
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02328
DMA0_CMICIC194
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0232C
DMA0_CMICIC195
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02330
DMA0_CMICIC196
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02334
DMA0_CMICIC197
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02338
DMA0_CMICIC198
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0233C
DMA0_CMICIC199
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02340
DMA0_CMICIC200
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02344
DMA0_CMICIC201
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02348
DMA0_CMICIC202
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0234C
DMA0_CMICIC203
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02350
DMA0_CMICIC204
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02354
DMA0_CMICIC205
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02358
DMA0_CMICIC206
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (39 / 57)
Offset
+3
+2
+1
0xB0C0235C
DMA0_CMICIC207
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02360
DMA0_CMICIC208
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02364
DMA0_CMICIC209
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02368
DMA0_CMICIC210
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0236C
DMA0_CMICIC211
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02370
DMA0_CMICIC212
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02374
DMA0_CMICIC213
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02378
DMA0_CMICIC214
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0237C
DMA0_CMICIC215
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02380
DMA0_CMICIC216
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02384
DMA0_CMICIC217
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02388
DMA0_CMICIC218
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0238C
DMA0_CMICIC219
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02390
DMA0_CMICIC220
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02394
DMA0_CMICIC221
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02398
DMA0_CMICIC222
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0239C
DMA0_CMICIC223
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023A0
DMA0_CMICIC224
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023A4
DMA0_CMICIC225
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023A8
DMA0_CMICIC226
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023AC
DMA0_CMICIC227
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
291
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (40 / 57)
Offset
292
+3
+2
+1
0xB0C023B0
DMA0_CMICIC228
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023B4
DMA0_CMICIC229
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023B8
DMA0_CMICIC230
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023BC
DMA0_CMICIC231
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023C0
DMA0_CMICIC232
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023C4
DMA0_CMICIC233
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023C8
DMA0_CMICIC234
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023CC
DMA0_CMICIC235
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023D0
DMA0_CMICIC236
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023D4
DMA0_CMICIC237
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023D8
DMA0_CMICIC238
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023DC
DMA0_CMICIC239
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023E0
DMA0_CMICIC240
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023E4
DMA0_CMICIC241
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023E8
DMA0_CMICIC242
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023EC
DMA0_CMICIC243
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023F0
DMA0_CMICIC244
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023F4
DMA0_CMICIC245
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023F8
DMA0_CMICIC246
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C023FC
DMA0_CMICIC247
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02400
DMA0_CMICIC248
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (41 / 57)
Offset
+3
+2
+1
0xB0C02404
DMA0_CMICIC249
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02408
DMA0_CMICIC250
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0240C
DMA0_CMICIC251
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02410
DMA0_CMICIC252
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02414
DMA0_CMICIC253
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02418
DMA0_CMICIC254
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0241C
DMA0_CMICIC255
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02420
DMA0_CMICIC256
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02424
DMA0_CMICIC257
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02428
DMA0_CMICIC258
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0242C
DMA0_CMICIC259
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02430
DMA0_CMICIC260
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02434
DMA0_CMICIC261
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02438
DMA0_CMICIC262
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0243C
DMA0_CMICIC263
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02440
DMA0_CMICIC264
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02444
DMA0_CMICIC265
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02448
DMA0_CMICIC266
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0244C
DMA0_CMICIC267
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02450
DMA0_CMICIC268
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02454
DMA0_CMICIC269
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
293
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (42 / 57)
Offset
294
+3
+2
+1
0xB0C02458
DMA0_CMICIC270
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0245C
DMA0_CMICIC271
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02460
DMA0_CMICIC272
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02464
DMA0_CMICIC273
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02468
DMA0_CMICIC274
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0246C
DMA0_CMICIC275
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02470
DMA0_CMICIC276
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02474
DMA0_CMICIC277
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02478
DMA0_CMICIC278
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0247C
DMA0_CMICIC279
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02480
DMA0_CMICIC280
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02484
DMA0_CMICIC281
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02488
DMA0_CMICIC282
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0248C
DMA0_CMICIC283
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02490
DMA0_CMICIC284
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02494
DMA0_CMICIC285
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02498
DMA0_CMICIC286
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0249C
DMA0_CMICIC287
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024A0
DMA0_CMICIC288
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024A4
DMA0_CMICIC289
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024A8
DMA0_CMICIC290
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (43 / 57)
Offset
+3
+2
+1
0xB0C024AC
DMA0_CMICIC291
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024B0
DMA0_CMICIC292
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024B4
DMA0_CMICIC293
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024B8
DMA0_CMICIC294
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024BC
DMA0_CMICIC295
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024C0
DMA0_CMICIC296
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024C4
DMA0_CMICIC297
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024C8
DMA0_CMICIC298
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024CC
DMA0_CMICIC299
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024D0
DMA0_CMICIC300
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024D4
DMA0_CMICIC301
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024D8
DMA0_CMICIC302
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024DC
DMA0_CMICIC303
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024E0
DMA0_CMICIC304
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024E4
DMA0_CMICIC305
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024E8
DMA0_CMICIC306
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024EC
DMA0_CMICIC307
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024F0
DMA0_CMICIC308
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024F4
DMA0_CMICIC309
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024F8
DMA0_CMICIC310
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C024FC
DMA0_CMICIC311
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
295
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (44 / 57)
Offset
296
+3
+2
+1
0xB0C02500
DMA0_CMICIC312
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02504
DMA0_CMICIC313
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02508
DMA0_CMICIC314
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0250C
DMA0_CMICIC315
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02510
DMA0_CMICIC316
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02514
DMA0_CMICIC317
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02518
DMA0_CMICIC318
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0251C
DMA0_CMICIC319
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02520
DMA0_CMICIC320
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02524
DMA0_CMICIC321
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02528
DMA0_CMICIC322
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0252C
DMA0_CMICIC323
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02530
DMA0_CMICIC324
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02534
DMA0_CMICIC325
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02538
DMA0_CMICIC326
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0253C
DMA0_CMICIC327
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02540
DMA0_CMICIC328
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02544
DMA0_CMICIC329
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02548
DMA0_CMICIC330
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0254C
DMA0_CMICIC331
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02550
DMA0_CMICIC332
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (45 / 57)
Offset
+3
+2
+1
0xB0C02554
DMA0_CMICIC333
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02558
DMA0_CMICIC334
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0255C
DMA0_CMICIC335
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02560
DMA0_CMICIC336
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02564
DMA0_CMICIC337
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02568
DMA0_CMICIC338
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0256C
DMA0_CMICIC339
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02570
DMA0_CMICIC340
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02574
DMA0_CMICIC341
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02578
DMA0_CMICIC342
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0257C
DMA0_CMICIC343
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02580
DMA0_CMICIC344
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02584
DMA0_CMICIC345
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02588
DMA0_CMICIC346
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0258C
DMA0_CMICIC347
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02590
DMA0_CMICIC348
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02594
DMA0_CMICIC349
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02598
DMA0_CMICIC350
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0259C
DMA0_CMICIC351
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025A0
DMA0_CMICIC352
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025A4
DMA0_CMICIC353
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
297
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (46 / 57)
Offset
298
+3
+2
+1
0xB0C025A8
DMA0_CMICIC354
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025AC
DMA0_CMICIC355
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025B0
DMA0_CMICIC356
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025B4
DMA0_CMICIC357
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025B8
DMA0_CMICIC358
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025BC
DMA0_CMICIC359
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025C0
DMA0_CMICIC360
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025C4
DMA0_CMICIC361
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025C8
DMA0_CMICIC362
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025CC
DMA0_CMICIC363
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025D0
DMA0_CMICIC364
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025D4
DMA0_CMICIC365
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025D8
DMA0_CMICIC366
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025DC
DMA0_CMICIC367
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025E0
DMA0_CMICIC368
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025E4
DMA0_CMICIC369
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025E8
DMA0_CMICIC370
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025EC
DMA0_CMICIC371
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025F0
DMA0_CMICIC372
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025F4
DMA0_CMICIC373
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C025F8
DMA0_CMICIC374
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (47 / 57)
Offset
+3
+2
+1
0xB0C025FC
DMA0_CMICIC375
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02600
DMA0_CMICIC376
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02604
DMA0_CMICIC377
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02608
DMA0_CMICIC378
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0260C
DMA0_CMICIC379
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02610
DMA0_CMICIC380
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02614
DMA0_CMICIC381
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02618
DMA0_CMICIC382
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0261C
DMA0_CMICIC383
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02620
DMA0_CMICIC384
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02624
DMA0_CMICIC385
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02628
DMA0_CMICIC386
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0262C
DMA0_CMICIC387
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02630
DMA0_CMICIC388
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02634
DMA0_CMICIC389
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02638
DMA0_CMICIC390
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0263C
DMA0_CMICIC391
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02640
DMA0_CMICIC392
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02644
DMA0_CMICIC393
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02648
DMA0_CMICIC394
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0264C
DMA0_CMICIC395
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
299
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (48 / 57)
Offset
300
+3
+2
+1
0xB0C02650
DMA0_CMICIC396
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02654
DMA0_CMICIC397
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02658
DMA0_CMICIC398
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0265C
DMA0_CMICIC399
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02660
DMA0_CMICIC400
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02664
DMA0_CMICIC401
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02668
DMA0_CMICIC402
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0266C
DMA0_CMICIC403
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02670
DMA0_CMICIC404
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02674
DMA0_CMICIC405
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02678
DMA0_CMICIC406
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0267C
DMA0_CMICIC407
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02680
DMA0_CMICIC408
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02684
DMA0_CMICIC409
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02688
DMA0_CMICIC410
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0268C
DMA0_CMICIC411
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02690
DMA0_CMICIC412
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02694
DMA0_CMICIC413
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02698
DMA0_CMICIC414
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0269C
DMA0_CMICIC415
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026A0
DMA0_CMICIC416
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (49 / 57)
Offset
+3
+2
+1
0xB0C026A4
DMA0_CMICIC417
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026A8
DMA0_CMICIC418
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026AC
DMA0_CMICIC419
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026B0
DMA0_CMICIC420
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026B4
DMA0_CMICIC421
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026B8
DMA0_CMICIC422
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026BC
DMA0_CMICIC423
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026C0
DMA0_CMICIC424
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026C4
DMA0_CMICIC425
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026C8
DMA0_CMICIC426
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026CC
DMA0_CMICIC427
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026D0
DMA0_CMICIC428
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026D4
DMA0_CMICIC429
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026D8
DMA0_CMICIC430
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026DC
DMA0_CMICIC431
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026E0
DMA0_CMICIC432
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026E4
DMA0_CMICIC433
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026E8
DMA0_CMICIC434
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026EC
DMA0_CMICIC435
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026F0
DMA0_CMICIC436
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026F4
DMA0_CMICIC437
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
301
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (50 / 57)
Offset
302
+3
+2
+1
0xB0C026F8
DMA0_CMICIC438
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C026FC
DMA0_CMICIC439
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02700
DMA0_CMICIC440
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02704
DMA0_CMICIC441
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02708
DMA0_CMICIC442
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0270C
DMA0_CMICIC443
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02710
DMA0_CMICIC444
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02714
DMA0_CMICIC445
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02718
DMA0_CMICIC446
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0271C
DMA0_CMICIC447
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02720
DMA0_CMICIC448
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02724
DMA0_CMICIC449
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02728
DMA0_CMICIC450
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0272C
DMA0_CMICIC451
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02730
DMA0_CMICIC452
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02734
DMA0_CMICIC453
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02738
DMA0_CMICIC454
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0273C
DMA0_CMICIC455
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02740
DMA0_CMICIC456
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02744
DMA0_CMICIC457
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02748
DMA0_CMICIC458
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (51 / 57)
Offset
+3
+2
+1
0xB0C0274C
DMA0_CMICIC459
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02750
DMA0_CMICIC460
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02754
DMA0_CMICIC461
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02758
DMA0_CMICIC462
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0275C
DMA0_CMICIC463
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02760
DMA0_CMICIC464
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02764
DMA0_CMICIC465
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02768
DMA0_CMICIC466
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0276C
DMA0_CMICIC467
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02770
DMA0_CMICIC468
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02774
DMA0_CMICIC469
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02778
DMA0_CMICIC470
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0277C
DMA0_CMICIC471
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02780
DMA0_CMICIC472
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02784
DMA0_CMICIC473
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02788
DMA0_CMICIC474
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0278C
DMA0_CMICIC475
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02790
DMA0_CMICIC476
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02794
DMA0_CMICIC477
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02798
DMA0_CMICIC478
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C0279C
DMA0_CMICIC479
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
303
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (52 / 57)
Offset
304
+3
+2
+1
0xB0C027A0
DMA0_CMICIC480
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027A4
DMA0_CMICIC481
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027A8
DMA0_CMICIC482
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027AC
DMA0_CMICIC483
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027B0
DMA0_CMICIC484
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027B4
DMA0_CMICIC485
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027B8
DMA0_CMICIC486
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027BC
DMA0_CMICIC487
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027C0
DMA0_CMICIC488
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027C4
DMA0_CMICIC489
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027C8
DMA0_CMICIC490
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027CC
DMA0_CMICIC491
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027D0
DMA0_CMICIC492
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027D4
DMA0_CMICIC493
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027D8
DMA0_CMICIC494
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027DC
DMA0_CMICIC495
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027E0
DMA0_CMICIC496
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027E4
DMA0_CMICIC497
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027E8
DMA0_CMICIC498
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027EC
DMA0_CMICIC499
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027F0
DMA0_CMICIC500
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (53 / 57)
Offset
+3
+2
+1
0xB0C027F4
DMA0_CMICIC501
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027F8
DMA0_CMICIC502
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C027FC
DMA0_CMICIC503
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C02800
DMA0_CMCHIC0
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02804
DMA0_CMCHIC1
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02808
DMA0_CMCHIC2
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C0280C
DMA0_CMCHIC3
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02810
DMA0_CMCHIC4
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02814
DMA0_CMCHIC5
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02818
DMA0_CMCHIC6
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C0281C
DMA0_CMCHIC7
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02820
DMA0_CMCHIC8
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02824
DMA0_CMCHIC9
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02828
DMA0_CMCHIC10
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C0282C
DMA0_CMCHIC11
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02830
DMA0_CMCHIC12
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02834
DMA0_CMCHIC13
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02838
DMA0_CMCHIC14
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C0283C
DMA0_CMCHIC15
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02840
DMA0_CMCHIC16
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02844
DMA0_CMCHIC17
XXXXXXXX XXXXXXXX 00000000 00000010
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
305
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (54 / 57)
Offset
306
+3
+2
+1
0xB0C02848
DMA0_CMCHIC18
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C0284C
DMA0_CMCHIC19
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02850
DMA0_CMCHIC20
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02854
DMA0_CMCHIC21
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02858
DMA0_CMCHIC22
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C0285C
DMA0_CMCHIC23
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02860
DMA0_CMCHIC24
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02864
DMA0_CMCHIC25
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02868
DMA0_CMCHIC26
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C0286C
DMA0_CMCHIC27
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02870
DMA0_CMCHIC28
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02874
DMA0_CMCHIC29
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02878
DMA0_CMCHIC30
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C0287C
DMA0_CMCHIC31
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02880
DMA0_CMCHIC32
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02884
DMA0_CMCHIC33
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02888
DMA0_CMCHIC34
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C0288C
DMA0_CMCHIC35
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02890
DMA0_CMCHIC36
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02894
DMA0_CMCHIC37
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02898
DMA0_CMCHIC38
XXXXXXXX XXXXXXXX 00000000 00000010
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (55 / 57)
Offset
+3
+2
+1
0xB0C0289C
DMA0_CMCHIC39
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028A0
DMA0_CMCHIC40
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028A4
DMA0_CMCHIC41
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028A8
DMA0_CMCHIC42
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028AC
DMA0_CMCHIC43
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028B0
DMA0_CMCHIC44
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028B4
DMA0_CMCHIC45
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028B8
DMA0_CMCHIC46
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028BC
DMA0_CMCHIC47
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028C0
DMA0_CMCHIC48
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028C4
DMA0_CMCHIC49
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028C8
DMA0_CMCHIC50
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028CC
DMA0_CMCHIC51
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028D0
DMA0_CMCHIC52
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028D4
DMA0_CMCHIC53
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028D8
DMA0_CMCHIC54
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028DC
DMA0_CMCHIC55
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028E0
DMA0_CMCHIC56
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028E4
DMA0_CMCHIC57
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028E8
DMA0_CMCHIC58
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028EC
DMA0_CMCHIC59
XXXXXXXX XXXXXXXX 00000000 00000010
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
307
Data
Shee t
Table 5-9 Memory layout of the PERI5_AHB registers (56 / 57)
Offset
308
+3
+2
+1
0xB0C028F0
DMA0_CMCHIC60
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028F4
DMA0_CMCHIC61
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028F8
DMA0_CMCHIC62
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C028FC
DMA0_CMCHIC63
XXXXXXXX XXXXXXXX 00000000 00000010
0xB0C02900B0C07FFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C08000
MPUXDMA0_CTRL0
00000000 00000000 00000001 00000000
0xB0C08004
MPUXDMA0_NMIEN
XXXXXXXX XXXXXXXX XXXXXXXX 00000001
0xB0C08008
MPUXDMA0_WERRC
XXXXXXXX XXXXXXXX 00000XXX XXXXXXX0
0xB0C0800C
MPUXDMA0_WERRA
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C08010
MPUXDMA0_RERRC
XXXXXXXX XXXXXXXX 00000XXX XXXXXXX0
0xB0C08014
MPUXDMA0_RERRA
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xB0C08018
MPUXDMA0_CTRL1
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C0801C
MPUXDMA0_SADDR1
00000000 00000000 00000000 00000000
0xB0C08020
MPUXDMA0_EADDR1
00000000 00000000 00000000 01111111
0xB0C08024
MPUXDMA0_CTRL2
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C08028
MPUXDMA0_SADDR2
00000000 00000000 00000000 00000000
0xB0C0802C
MPUXDMA0_EADDR2
00000000 00000000 00000000 01111111
0xB0C08030
MPUXDMA0_CTRL3
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C08034
MPUXDMA0_SADDR3
00000000 00000000 00000000 00000000
0xB0C08038
MPUXDMA0_EADDR3
00000000 00000000 00000000 01111111
0xB0C0803C
MPUXDMA0_CTRL4
XXXXXXXX XXXXXXXX 00000000 00000000
+0
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-9 Memory layout of the PERI5_AHB registers (57 / 57)
Offset
+3
+2
+1
0xB0C08040
MPUXDMA0_SADDR4
00000000 00000000 00000000 00000000
0xB0C08044
MPUXDMA0_EADDR4
00000000 00000000 00000000 01111111
0xB0C08048
MPUXDMA0_CTRL5
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C0804C
MPUXDMA0_SADDR5
00000000 00000000 00000000 00000000
0xB0C08050
MPUXDMA0_EADDR5
00000000 00000000 00000000 01111111
0xB0C08054
MPUXDMA0_CTRL6
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C08058
MPUXDMA0_SADDR6
00000000 00000000 00000000 00000000
0xB0C0805C
MPUXDMA0_EADDR6
00000000 00000000 00000000 01111111
0xB0C08060
MPUXDMA0_CTRL7
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C08064
MPUXDMA0_SADDR7
00000000 00000000 00000000 00000000
0xB0C08068
MPUXDMA0_EADDR7
00000000 00000000 00000000 01111111
0xB0C0806C
MPUXDMA0_CTRL8
XXXXXXXX XXXXXXXX 00000000 00000000
0xB0C08070
MPUXDMA0_SADDR8
00000000 00000000 00000000 00000000
0xB0C08074
MPUXDMA0_EADDR8
00000000 00000000 00000000 01111111
0xB0C08078
MPUXDMA0_UNLOCK
00000000 00000000 00000000 00000000
0xB0C0807C
MPUXDMA0_MID
00000000 00000000 00000000 00000000
0xB0C08080B0CFFC00
reserved
XXXXXXXX XXXXXXXX XXXXXXXX 0000000X
0xB0CFFC04
BSU5_BTST
00000000 00000000 00000000 00000000
0xB0CFFC08B0CFFFFC
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
January 30, 2015, MB9EF226_DS707-00004-2v1-E
+0
309
Data
Shee t
Table 5-10 Memory layout for the SYSTEM_RAM_CONFIG registers
Offset
310
+7
+6
+5
+4
+3
+2
+1
+0
0xB0D00000
SRCFG_CFG1
00000000 00000000 00000000 00000000
SRCFG_CFG0
00000011 00000011 00000001 00000000
0xB0D00008
SRCFG_KEY
00000000 00000000 00000000 00000000
SRCFG_CFG2
00000000 00000000 00000000 00000000
0xB0D00010
SRCFG_INTE
00000000 00000000 00000000 00000000
SRCFG_ERRFLG
00000000 00000000 00000000 00000000
0xB0D00018
read0
00000000 00000000 00000000 00000000
SRCFG_ECCE
00000000 00000000 00000000 00000001
0xB0D00020
SRCFG_MID
00000000 00000000 00000000 00000000
SRCFG_ERRADR
00000000 00000000 00000000 00000000
0xB0D00028B0D00FF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 5-11 Memory layout of the EXCFG registers
Offset
0xFFFEF000FFFEFF50
_7
+6
+5
+4
+3
+2
+1
+0
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xFFFEFF58
read0
00000000 00000000 00000000 00000000
EXCFG_UNLOCK
00000000 00000000 00000000 00000000
0xFFFEFF60
read0
00000000 00000000 00000000 00000000
EXCFG_CNFG
00000000 00000000 00000000 00000001
0xFFFEFF68FFFEFF78
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xFFFEFF80
EXCFG_UNDEFINACT
11111111 11111111 00000000 00100100
read0
00000000 00000000 00000000 00000000
0xFFFEFF88
EXCFG_PABORTINACT
11111111 11111111 00000000 00101100
EXCFG_SVCINACT
11111111 11111111 00000000 00101000
0xFFFEFF90
read0
00000000 00000000 00000000 00000000
EXCFG_DABORTINACT
11111111 11111111 00000000 00110000
0xFFFEFF98
read0
00000000 00000000 00000000 00000000
EXCFG_IRQINACT
11111111 11111111 00000000 00111000
0xFFFEFFA0FFFEFFB8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0xFFFEFFC0
EXCFG_UNDEFACT
11111111 11111111 00000000 00100100
read0
00000000 00000000 00000000 00000000
0xFFFEFFC8
EXCFG_PABORTACT
11111111 11111111 00000000 00101100
EXCFG_SVCACT
11111111 11111111 00000000 00101000
0xFFFEFFD0
read0
00000000 00000000 00000000 00000000
EXCFG_DABORTACT
11111111 11111111 00000000 00110000
0xFFFEFFD8
read0
00000000 00000000 00000000 00000000
EXCFG_IRQACT
11111111 11111111 00000000 00111000
0xFFFEFFE0FFFEFFF8
reserved
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
:Note:
•
SYSC_SPCCFGR:FASTON register bit is reserved and should be always written as ’0’, since this device
does not support "Fast Power domain control" feature.
•
SCCFG_STAT1:EEFCEEN and SCCFG_STAT1:TCFCEEN register bits are read-1 (write has no impact
and read always returns ’1’) in this device.
•
SCCFG_STAT1:FPPEN and SCCFG_STAT1:SCMEN register bits are read-0 (write has no impact and read
always returns ’0’) in this device.
January 30, 2015, MB9EF226_DS707-00004-2v1-E
311
Data
312
Shee t
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
6 Electrical characteristics
6.1
Absolute Maximum Ratings
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Table 6-1: Absolute Maximum Ratings (1 / 6)
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VDP5
VSS - 0.3
VSS + 6.0
V
VDP3
VSS - 0.3
VSS + 4.0
V
VDD
VSS - 0.3
VSS + 1.8
V
AVDD5
AVSS5 - 0.3
AVSS5 + 6.0
V
VDP5 = AVDD5 *1
AVRH5
AVSS5 - 0.3
AVSS5 + 6.0
V
AVDD5 AVRH5, AVRH5 AVSS5
See *4 VDP5 = AVDD5 = DVCC
when ZPD functionality is
used
Power supply voltage
AD Converter voltage references
SMC Power supply
DVCC
DVSS - 0.3
DVSS + 6.0
V
Analog input voltage
VIA
AVSS5 - 0.3
AVDD5 + 0.3
V
VSS - 0.3
VDP5 + 0.3
V
VSS - 0.3
VDP3 + 0.3
V
DVSS - 0.3
DVCC + 0.3
V
VSS - 0.3
VDP5 + 0.3
V
VSS - 0.3
VDP3 + 0.3
V
DVSS - 0.3
DVCC + 0.3
V
Input voltage
Output voltage
VI
VO
VI  DVCC,VDP5 + 0.3V *2
VO  DVCC,VDP5 + 0.3V *2
Maximum Clamp Current
ICLAMP
-4
+4
mA
Applicable to general purpose I/O pins *3
Total Maximum Clamp Current
|ICLAMP|
-
20
mA
Applicable to general purpose I/O pins *3
January 30, 2015, MB9EF226_DS707-00004-2v1-E
313
Data
Shee t
Table 6-1: Absolute Maximum Ratings (2 / 6)
Rating
Parameter
“L” level maximum output
current
“L” level maximum overall
output current
314
Symbol
Unit
Remarks
2
mA
Normal outputs (BIDI50) with
driving strength set to 1mA
-
4
mA
Normal outputs (BIDI50) with
driving strength set to 2mA
IOL5
-
10
mA
Normal outputs (BIDI50) with
driving strength set to 5mA
IOLI2C
-
6
mA
I2C outputs (I2C) with driving
strength set to 3mA
IOLHSIO
-
24
mA
High Speed outputs (BIDI33)
with driving strength set to
12mA
IOLSMC
-
40
mA
SMC outputs(SMC) with driving strength set to 30mA
IOLTTL2
-
4
mA
TTL outputs (TTL33, RSDS)
with
driving strength set to 2mA
IOLTTL5
-
10
mA
TTL outputs (TTL33, RSDS)
with
driving strength set to 5mA
IOLTTL10
-
20
mA
TTL outputs (TTL33, RSDS)
with
driving strength set to 10mA
IOLTTL20
-
40
mA
TTL outputs (TTL33, RSDS)
with
driving strength set to 20mA
IOLVDP5
-
100
mA
-
IOLVDP3
-
100
mA
-
IOLDVCC
-
360
mA
-
Min
Max
IOL1
-
IOL2
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 6-1: Absolute Maximum Ratings (3 / 6)
Rating
Parameter
“L” level average output current
“L” level average overall output current
Symbol
Unit
Remarks
1
mA
Normal outputs (BIDI50) with
driving strength set to 1mA
-
2
mA
Normal outputs (BIDI50) with
driving strength set to 2mA
IOLAV5
-
5
mA
Normal outputs (BIDI50) with
driving strength set to 5mA
IOLAVI2C
-
3
mA
I2C outputs (I2C) with driving
strength set to 3mA
IOLAVHSIO
-
12
mA
High Speed outputs (BIDI33)
with driving strength set to
12mA
IOLAVSMC
-
30
mA
SMC outputs (SMC) with
driving strength set to 30mA
IOLAVTTL2
-
2
mA
TTL outputs (TTL33, RSDS)
with
driving strength set to 2mA
IOLAVTTL5
-
5
mA
TTL outputs (TTL33, RSDS)
with
driving strength set to 5mA
IOLAVTTL10
-
10
mA
TTL outputs (TTL33, RSDS)
with
driving strength set to 10mA
IOLAVTTL20
-
20
mA
TTL outputs (TTL33, RSDS)
with
driving strength set to 20mA
IOLAVDP5
-
50
mA
-
IOLAVDP3
-
50
mA
-
IOLADVCC
-
230
mA
-
Min
Max
IOLAV1
-
IOLAV2
January 30, 2015, MB9EF226_DS707-00004-2v1-E
315
Data
Shee t
Table 6-1: Absolute Maximum Ratings (4 / 6)
Rating
Parameter
“H” level maximum output
current
“H” level maximum overall
output current
316
Symbol
Unit
Remarks
-2
mA
Normal outputs (BIDI50) with
driving strength set to 1mA
-
-4
mA
Normal outputs (BIDI50) with
driving strength set to 2mA
IOH5
-
-10
mA
Normal outputs (BIDI50) with
driving strength set to 5mA
IOHI2C
-
-6
mA
I2C outputs (I2C) with driving
strength set to 3mA
IOHHSIO
-
-24
mA
High Speed outputs (BIDI33)
with driving strength set to
12mA
IOHSMC
-
-40
mA
SMC outputs (SMC) with
driving strength set to 30mA
IOHTTL2
-
-4
mA
TTL outputs (TTL33, RSDS)
with
driving strength set to 2mA
IOHTTL5
-
-10
mA
TTL outputs (TTL33, RSDS)
with
driving strength set to 5mA
IOHTTL10
-
-20
mA
TTL outputs (TTL33, RSDS)
with
driving strength set to 10mA
IOHTTL20
-
-40
mA
TTL outputs (TTL33, RSDS)
with
driving strength set to 20mA
IOHVDP5
-
-100
mA
-
IOHVDP3
-
-100
mA
-
IOHDVCC
-
-360
mA
-
Min
Max
IOH1
-
IOH2
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 6-1: Absolute Maximum Ratings (5 / 6)
Rating
Parameter
“H” level average output current
“H” level average overall output current
Symbol
Unit
Remarks
-1
mA
Normal outputs (BIDI50) with
driving strength set to 1mA
-
-2
mA
Normal outputs (BIDI50) with
driving strength set to 2mA
IOHAV5
-
-5
mA
Normal outputs (BIDI50) with
driving strength set to 5mA
IOHAVI2C
-
-3
mA
I2C outputs (I2C) with driving
strength set to 3mA
IOHAVHSIO
-
-12
mA
High Speed outputs (BIDI33)
with driving strength set to
12mA
IOHAVSMC
-
-30
mA
SMC outputs (SMC) with
driving strength set to 30mA
IOHAVTTL2
-
-2
mA
TTL outputs (TTL33, RSDS)
with
driving strength set to 2mA
IOHAVTTL5
-
-5
mA
TTL outputs (TTL33, RSDS)
with
driving strength set to 5mA
IOHAVTTL10
-
-10
mA
TTL outputs (TTL33, RSDS)
with
driving strength set to 10mA
IOHAVTTL20
-
-20
mA
TTL outputs (TTL33, RSDS)
with
driving strength set to 20mA
IOHAVDP5
-
-50
mA
-
IOHAVDP3
-
-50
mA
-
IOHADVCC
-
-230
mA
-
IODHRSDS0
-
4
mA
RSDS outputs (RSDS) with
RSDS BOOST = 0
IODHRSDS1
-
8
mA
RSDS outputs (RSDS) with
RSDS BOOST = 1
IODHVDP3
-
100
mA
IODAVRSDS0
2
mA
RSDS outputs (RSDS) with
RSDS BOOST = 0
IODAVRSDS1
4
mA
RSDS outputs (RSDS) with
RSDS BOOST = 1
Min
Max
IOHAV1
-
IOHAV2
Differential maximum output
current
Differential maximum output
current overall output current
Differential average output
current
January 30, 2015, MB9EF226_DS707-00004-2v1-E
317
Data
Shee t
Table 6-1: Absolute Maximum Ratings (6 / 6)
Rating
Parameter
Symbol
Unit
Min
Differential average output
current overall output current
IODAVVDP3
Power consumption
PTOT
Operating ambient temperature
Storage temperature
318
Remarks
Max
50
mA
-
2000
mW
-
TA
-40
105
C
-
TSTG
-55
150
C
-
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
*1: AVDD5 and VDP5 must be set to the same voltage. It is required that AVDD5 does not exceed VDP5 and that the
voltage at the analog inputs does not exceed AVDD5 neither when the power is switched on.
*2: VI and VO should not exceed VDP5 + 0.3 V. VI should also not exceed the specified ratings. However if the
maximum current to/from a input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. Input/output voltages of standard ports depend on VDP5.
*3:
•
•
•
•
•
•
•
•
•
Applicable to all general purpose I/O pins (Pi_jj)
Use within recommended operating conditions.
Use at DC voltage (current)
The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
The value of the limiting resistance should be set so that when the +B signal is applied the input current
to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VDP5 pin, and this may
affect other devices.
Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the Power reset (except devices with persistent
low voltage reset in internal vector mode).
Sample recommended circuits:
Protection Diode
Vcc
P−ch
+B input (0V to 16V)
Limiting
resistance
N−ch
R
*4: DVCC, AVDD5 and VDP5 must be set to the same voltage during zero point detection (ZPD) on any of the SMC
ports. If zero point detection is not required on any of the SMC ports, then DVCC can have any value with-in
absolute rating, provided switches are disabled by RICFG0_ADC0ZPDEN:ZPDEN register. Note, for ZPD,
conversion time will be more and accuracy of measurement will be low.
January 30, 2015, MB9EF226_DS707-00004-2v1-E
319
Data
6.2
Shee t
Recommended operating conditions
Table 6-2: Recommended operating conditions
Value
Parameter
Symbol
Unit
Min
Typ
Max
Remarks
5V power supply voltage
VDP5
3.0
3.3/5.0
5.5
V
3.3V power supply voltage
VDP3
3.0
3.3
3.6
V
1.2V power supply voltage
VDD
1.1
1.2
1.3
V
DVCC
4.5
5.0
5.5
V
If used as SMC
DVCC
3.0
3.3/5.0
5.5
V
If used as GPIO
Analog power supply voltage
AVDD5
3.0
3.3/5.0
5.5
V
AD Converter voltage reference
AVRH5
AVDD5 - 0.5
-
AVDD5
V
Operation ambient temparature
TOP
-40
-
105
C
SMC power supply voltage
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the devices electrical characteristics are guaranteed when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operating outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
320
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
6.3
Sh eet
DC Characteristics
(TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-3: DC characteristics (1 / 7)
Value
Parameter
Symbol
Pin
Condition
BIDI50 / SMC
CMOS
BIDI50 / SMC
Hysteresis
VIH
Port
inputs
Pi_jj
BIDI50 / SMC / I2C
AUTOMOTIVE
BIDI50 / SMC / I2C
TTL
I2C
CMOS
I2C
Hysteresis
VIH
X0
Unit
Remarks
VDP5
V
4.5V  VDP5  5.5V
-
VDP5
V
3.0V  VDP5  3.6V
0.8 x VDP5
-
VDP5
V
4.5V  VDP5  5.5V
0.8 x VDP5
-
VDP5
V
3.0V  VDP5  3.6V
0.8 x VDP5
-
VDP5
V
4.5V  VDP5  5.5V
0.8 x VDP5
-
VDP5
V
3.0V  VDP5  3.6V
2.0
-
VDP5
V
4.5V  VDP5  5.5V
2.0
-
VDP5
V
3.0V  VDP5  3.6V
0.7 x VDP5
-
VDP5
V
4.5V  VDP5  5.5V
0.7 x VDP5
-
VDP5
V
3.0V  VDP5  3.6V
0.7 x VDP5
-
VDP5
V
4.5V  VDP5  5.5V
0.7 x VDP5
-
VDP5
V
3.0V  VDP5  3.6V
0.8 x VDP5
-
VDP3
V
4.5V  VDP5  5.5V
VDP5
V
3.0V  VDP5  3.6V
VDP5
V
4.5V  VDP5  5.5V
VDP5
V
3.0V  VDP5  3.6V
VDP5
V
4.5V  VDP5  5.5V
VDP5
V
3.0V  VDP5  3.6V
VDP5
V
4.5V  VDP5  5.5V
VDP5
V
3.0V  VDP5  3.6V
Min
Typ
Max
0.8 x VDP5
-
0.8 x VDP5
4 MHz Oscillator
0.8 x VDP5
Input “H“ voltage
0.8 x VDP5
VIH
X0A
-
32 KHz Oscillator
0.8 x VDP5
VIHXDF
VIHXOS
VIHR
VIHM
VIHHSIO
External clock
in"Fast Clock Input
mode"
0.7 x VDP5
X0,X1,
X0A,X1A
External clock in
"oscillation mode"
0.8 x VDP5
RSTX
MODE/RSTX
CMOS Hysteresis
X0
MODE
MODE/RSTX
CMOS Hysteresis
-
0.7 x VDP5
-
0.8 x VDP5
0.7 x VDP5
-
VDP5
V
4.5V  VDP5  5.5V
0.7 x VDP5
-
VDP5
V
3.0V  VDP5  3.6V
0.7 x VDP5
-
VDP5
V
4.5V  VDP5  5.5V
0.7 x VDP5
-
VDP5
V
3.0V  VDP5  3.6V
BIDI33 / TTL33 /
RSDS
Hysteresis
0.7 x VDP3
VDP3
V
3.0V  VDP3  3.6V
BIDI33 / TTL33 /
RSDS
TTL
2
VDP3
V
3.0V  VDP3  3.6V
pi_jj
January 30, 2015, MB9EF226_DS707-00004-2v1-E
321
Data
Shee t
(TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-3: DC characteristics (2 / 7)
Value
Parameter
Symbol
Pin
Condition
BIDI50 / SMC
CMOS
BIDI50 / SMC
Hysteresis
VIL
Port inputs
pi_jj
BIDI50 / SMC / I2C
AUTOMOTIVE
BIDI50 / SMC / I2C
TTL
I2C
CMOS
I2C
Hysteresis
VIL
X0
Unit
Remarks
0.2 x VDP5
V
4.5V  VDP5  5.5V
-
0.2 x VDP5
V
3.0V  VDP5  3.6V
VSS
-
0.2 x VDP5
V
4.5V  VDP5  5.5V
VSS
-
0.2 x VDP5
V
3.0V  VDP5  3.6V
VSS
-
0.5 x VDP5
V
4.5V  VDP5  5.5V
VSS
-
0.3 x VDP5
V
3.0V  VDP5  3.6V
VSS
-
0.8
V
4.5V  VDP5  5.5V
VSS
-
0.8
V
3.0V  VDP5  3.6V
VSS
-
0.3 x VDP5
V
4.5V  VDP5  5.5V
VSS
-
0.2 x VDP5
V
3.0V  VDP5  3.6V
VSS
-
0.3 x VDP5
V
4.5V  VDP5  5.5V
VSS
-
0.2 x VDP5
V
3.0V  VDP5  3.6V
VSS
-
0.2 x VDP5
V
4.5V  VDP5  5.5V
0.2 x VDP5
V
3.0V  VDP5  3.6V
0.2 x VDP5
V
4.5V  VDP5  5.5V
0.2 x VDP5
V
3.0V  VDP5  3.6V
0.3 x VDP5
V
4.5V  VDP5  5.5V
0.3 x VDP5
V
3.0V  VDP5  3.6V
0.2 x VDP5
V
4.5V  VDP5  5.5V
0.2 x VDP5
V
3.0V  VDP5  3.6V
Min
Typ
Max
VSS
-
VSS
4 MHz Oscillator
VSS
Input “L“ voltage
VSS
VIL
X0A
-
32 KHz Oscillator
VSS
VILX0F
VILX0S
VILR
VILM
VILHSIO
322
External clock
in"Fast Clock Input
mode"
VSS
X0,X1,
X0A,X1A
External clock in
"oscillation mode"
VSS
MODE/RSTX
CMOS Hysteresis
VSS
-
0.3 x VDP5
V
4.5V  VDP5  5.5V
RSTX
VSS
-
0.3 x VDP5
V
3.0V  VDP5  3.6V
VSS
-
0.3 x VDP5
V
4.5V  VDP5  5.5V
VSS
-
0.3 x VDP5
V
3.0V  VDP5  3.6V
BIDI33 / TTL33 /
RSDS
Hysteresis
VSS
-
0.2 x VDP3
V
3.0V  VDP3  3.6V
BIDI33 / TTL33 /
RSDS
TTL
VSS
-
0.8
V
3.0V  VDP3  3.6V
X0
MODE
MODE/RSTX
CMOS Hysteresis
-
VSS
-
VSS
pi_jj
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
(TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-3: DC characteristics (3 / 7)
Value
Parameter
Symbol
Pin
Condition
BIDI50 / SMC
CMOS
BIDI50 / SMC
Hysteresis
Port
inputs
pi_jj
BIDI50 / SMC / I2C
AUTOMOTIVE
BIDI50 / SMC / I2C
TTL
I2C
CMOS
I2C
Hysteresis
X0
Unit
Remarks
-
V
4.5V  VDP5  5.5V
-
-
V
3.0V  VDP5  3.6V
0.05 x VDP5
-
-
V
4.5V  VDP5  5.5V
0.05 x VDP5
-
-
V
3.0V  VDP5  3.6V
0.35
-
-
V
4.5V  VDP5  5.5V
0.35
-
-
V
3.0V  VDP5  3.6V
0.1
-
-
V
4.5V  VDP5  5.5V
0.1
-
-
V
3.0V  VDP5  3.6V
-
-
-
V
4.5V  VDP5  5.5V
-
-
-
V
3.0V  VDP5  3.6V
0.05 x VDP5
-
-
V
4.5V  VDP5  5.5V
0.05 x VDP5
-
-
V
3.0V  VDP5  3.6V
0.05 x VDP5
-
-
V
4.5V  VDP5  5.5V
-
V
3.0V  VDP5  3.6V
-
V
4.5V  VDP5  5.5V
V
3.0V  VDP5  3.6V
-
V
4.5V  VDP5  5.5V
-
V
3.0V  VDP5  3.6V
-
V
4.5V  VDP5  5.5V
V
3.0V  VDP5  3.6V
Min
Typ
Max
-
-
-
4 MHz Oscillator
0.05 x VDP5
Hysteresis
VHYS
0.05 x VDP5
X0A
-
32 KHz Oscillator
0.05 x VDP5
External clock
in"Fast Clock
Input mode"
0.05 x VDP5
X0,X1,
X0A,X1A
External clock in
"oscillation mode"
0.05 x VDP5
MODE/RSTX
CMOS Hysteresis
0.05 x VDP5
-
-
V
4.5V  VDP5  5.5V
RSTX
0.05 x VDP5
-
-
V
3.0V  VDP5  3.6V
0.05 x VDP5
-
-
V
4.5V  VDP5  5.5V
0.05 x VDP5
-
-
V
3.0V  VDP5  3.6V
BIDI33 / TTL33 /
RSDS
Hysteresis
0.05 x VDP3
-
-
V
3.0V  VDP3  3.6V
BIDI33 / TTL33 /
RSDS
TTL
0.1
-
-
V
3.0V  VDP3  3.6V
X0
MODE
MODE/RSTX
CMOS Hysteresis
-
0.05 x VDP5
-
0.05 x VDP5
pi_jj
January 30, 2015, MB9EF226_DS707-00004-2v1-E
323
Data
Shee t
(TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-3: DC characteristics (4 / 7)
Value
Parameter
Output “H“
voltage
Output “H“
voltage
324
Symbol
Pin
VOH1
BIDI50 /
SMC / I2C
outputs
(VDP5)
VOH2
BIDI50 /
SMC / I2C
outputs
(VDP5)
VOH5
BIDI50 /
SMC / I2C
outputs
(VDP5)
VOH3
I2C
outputs
(VDP5)
VOHSMC
SMC
outputs
(DVCC)
VOH3X
32 KHz
oscillator
outputs
(VDP5)
VOH4X
4 MHz oscillator
outputs
(VDP5)
VOH12
BIDI33
outputs
(VDP3)
Condition
Unit
Remarks
-
V
Driving strength
set to 1mA
-
-
V
Driving strength
set to 2mA
VDP5 - 0.5
-
-
V
Driving strength
set to 5mA
-
-
-
V
Pseudo Open
Drain (HIZ for logic
value 1 )
Min
Typ
Max
VDP5 - 0.5
-
VDP5 - 0.5
4.5V  VDP5  5.5V
IOH = -1mA
3.0V  VDP5  3.6V
IOH = -0.8mA
4.5V  VDP5  5.5V
IOH = -2mA
3.0V  VDP5  3.6V
IOH = -1.5mA
4.5V  VDP5  5.5V
IOH = -5mA
3.0V  VDP5  3.6V
IOH = -3mA
4.5V  VDP5  5.5V
3.0V  VDP5  3.6V
4.5V  VDP5  5.5V
IOH = -30mA
3.0V  VDP5  3.6V
IOH = -20mA
Driving strength
set to 30mA
DVCC - 0.5
-
DVCC
V
Driving strength
set to 30mA
4.5V  VDP5  5.5V
IOH = -20uA
VDP5 - 1.3
-
VDP5
V
VDP5 - 0.9
-
VDP5
V
3.0V  VDP3  3.6V
IOH = -11mA
VDP3 - 0.5
-
VDP3
V
Driving strength
set to 12mA
VOH2
RSDS /
TTL33
outputs
(VDP3)
3.0V  VDP3  3.6V
IOH = -2mA
VDP3 - 0.5
-
VDP3
V
Driving strength
set to 2mA
VOH5
RSDS /
TTL33
outputs
(VDP3)
3.0V  VDP3  3.6V
IOH = -5mA
VDP3 - 0.5
-
VDP3
V
Driving strength
set to 5mA
VOH10
RSDS /
TTL33
outputs
(VDP3)
3.0V  VDP3  3.6V
IOH = -10mA
VDP3 - 0.6
-
VDP3
V
Driving strength
set to 10mA
VOH20
RSDS /
TTL33
outputs
(VDP3)
3.0V  VDP3  3.6V
IOH = -20mA
VDP3 - 0.5
-
VDP3
V
Driving strength
set to 20mA
3.0V  VDP5  3.6V
IOH = -11uA
4.5V  VDP5  5.5V
IOH = -200uA
3.0V  VDP5  3.6V
IOH = -115uA
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
(TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-3: DC characteristics (5 / 7)
Value
Parameter
Symbol
Pin
VOL1
BIDI50 /
SMC / I2C
outputs
(VDP5)
VOL2
BIDI50 /
SMC / I2C
outputs
(VDP5)
VOL5
BIDI50 /
SMC / I2C
outputs
(VDP5)
VOL3
I2C
outputs
(VDP5)
VOLSMC
SMC
outputs
(DVCC)
Output “L“
voltage
Output “L“
voltage
VOL3X
32 KHz
oscillator
outputs
(VDP5)
VOL4X
4 MHz
oscillator
outputs
(VDP5)
VOL12
Normal
outputs
(VDP3)
VOL2
Condition
Unit
Remarks
0.4
V
Driving strength
set to 1mA
-
0.4
V
Driving strength
set to 2mA
VSS
-
0.4
V
Driving strength
set to 5mA
VSS
-
0.4
V
Driving strength
set to 3mA
Min
Typ
Max
VSS
-
VSS
4.5V  VDP5  5.5V
IOL = +1mA
3.0V  VDP5  3.6V
IOL = +0.8mA
4.5V  VDP5  5.5V
IOL = +2mA
3.0V  VDP5  3.6V
IOL = +1.5mA
4.5V  VDP5  5.5V
IOL = +5mA
3.0V  VDP5  3.6V
IOL = +3mA
4.5V  VDP5  5.5V
IOL = +3mA
3.0V  VDP5  3.6V
IOL = +1.7mA
4.5V  VDP5  5.5V
IOH = +30mA
3.0V  VDP5  3.6V
IOH = +20mA
Driving strength
set to 30mA
DVSS
-
0.5
V
Driving strength
set to 30mA
4.5V  VDP5  5.5V
IOH = +20uA
VSS
-
1.2
V
VSS
-
1.2
V
3.0V  VDP3  3.6V
IOL = +11mA
VSS
-
0.4
V
Driving strength
set to 12mA
RSDS
outputs
(VDP3)
3.0V  VDP3  3.6V
IOH = +2mA
VSS
-
0.4
V
Driving strength
set to 2mA
VOL5
RSDS /
TTL33
outputs
(VDP3)
3.0V  VDP3  3.6V
IOH = +5mA
VSS
-
0.5
V
Driving strength
set to 5mA
VOL10
RSDS /
TTL33
outputs
(VDP3)
3.0V  VDP3  3.6V
IOH = +10mA
VSS
-
0.55
V
Driving strength
set to 10mA
VOL20
RSDS /
TTL33
outputs
(VDP3)
3.0V  VDP3  3.6V
IOH = +20mA
VSS
-
0.5
V
Driving strength
set to 20mA
3.0V  VDP5  3.6V
IOH = +11uA
4.5V  VDP5  5.5V
IOH = +200uA
3.0V  VDP5  3.6V
IOH = +115uA
January 30, 2015, MB9EF226_DS707-00004-2v1-E
325
Data
Shee t
(TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-3: DC characteristics (6 / 7)
Value
Parameter
Symbol
Pin
Condition
Min
Output differential
voltage amplitute
Output
common
voltage
Unit
Remarks
1) BOOST = 1,
RL=50
2) BOOST = 0,
RL= 100
Max
VOD
RSDS
outputs
(VDP3)
3.0V  VDP3  3.6V
100
-
600
mV
VOCM
RSDS
outputs
(VDP3)
3.0V  VDP3  3.6V
0.5
-
1.5
V
-
-1
-
+1
A
TA = 25°C
-
-3
-
+3
A
TA = 105°C
-
-1
-
+1
A
TA = 25°C
-
-3
-
+3
A
TA = 105°C
-
-
15
A
i = number of IO
= 30 GPIO (in
VDP5 IO domain)
-
-
30
A
i = number of IO
= 63 GPIO (in
VDP3 IO domain)
-
-
15
A
i = number of IO
= 24 GPIO (in
DVCC IO domain)
4.5V  VDP5  5.5V
25
50
100
k
3.0V  VDP5  3.6V
25
50
200
k
3.0V  VDP3  3.6V
15
33
80
k
4.5V  VDP5  5.5V
25
50
100
k
3.0V  VDP5  3.6V
25
50
200
k
3.0V  VDP3  3.6V
15
33
80
k
-
-
30
80
A
Operational
-
0.008
5
A
Standby
pi_jj
(GPIO)
Input leak
current
Typ
IIL
pi_jj
(ANIN)
VDP5 VIN  VSS
AVDD5 VIN  AVSS5
pi_jj
(GPIO,
ANIN)
(1 to n) [max (|ILHi|,|ILLi|)]
ILH: leakage at high level
input
ILL: leakage at low level
input
Total input
leakage current
VDP3 VIN  VSS
IIL
(1 to n) [max(|ILHi|,|ILLi|)]
pi_jj
(GPIO)
ILH: leakage at high level
input
ILL: leakage at low level
input
DVCC  VIN  VSS
pi_jj
(GPIO)
pi_jj,
(BIDI50/
SMC/I2C)
Pull-up
resistance
RUP
pi_jj,
(BIDI33 /
TTL33 /
RSDS )
pi_jj,
(BIDI50/
SMC/I2C)
Pull-down
resistance
Low voltage
detection current
326
RDN
ILYDETI
pi_jj,
(BIDI33 /
TTL33 /
RSDS )
(1 to n) [max(|ILHi|,|ILLi|)]
ILH: leakage at high level
input
ILL: leakage at low level
input
(VDP5)
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
(TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-3: DC characteristics (7 / 7)
Value
Parameter
Main oscillator
current (4
MHz)
Symbol
Pin
Condition
Unit
Remarks
300
A
Operational@
4MHz
load = 10pF
-
5
A
Standby
-
10
25
A
Operational
-
-
-
3
A
Standby
-
-
2
6
A
Operational
-
-
-
0.1
A
Standby
(VDD)
-
-
7
11
A
Operational
(average with
trimming)
(VDP5)
-
-
305
700
A
Operational
(average with
trimming)
(VDD)
-
-
0.01
3
A
Standby
(VDP5)
-
-
0.003
3
A
Standby
(VDD)
-
-
11
16
A
Operational
(average with
trimming)
(VDP5)
-
-
416
1050
A
Operational
(average with
trimming)
(VDD)
-
-
0.01
3
A
Standby
(VDP5)
-
-
0.003
3
A
Standby
-
-
-
5
15
pF
Other than supply
pins
IMOSCR
Slow RC oscillator current
(100kHz)
Fast RC oscillator
current (8
MHz)
Fast RC oscillator
current (12
MHz)
Input
capacitance
Typ
Max
-
-
160
-
-
-
(VDP5)
IMOSCS
Sub oscillator
current (32
kHz)
Min
ISOSCR
(VDP5)
ISOSCS
IRCS
IRFC8
IRFC12
CIN
(VDD)
January 30, 2015, MB9EF226_DS707-00004-2v1-E
327
Data
Shee t
(TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 3.0V to 5.5V
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-4: DC characteristics
Value
Parameter
Symbol
Pin
(VDD)
Power supply
current in RUN
mode
(VDD)
ICCPSS
(VDD)
(VDD)
ICCTMAIN
ICCTRCH
(VDD)
(VDD)
Power supply
current in Timer
mode
ICCTRCL
ICCTSUB
TCFLASH
Read current
(64 MHz)
ICCTCFLASHRD
TCFLASH
Program/Erase
current
ICCTCFLASHPE
TCFLASH
Sleep current
ICCTCFLASHSB
EEFLASH
Read current
ICCTCFLASHRD
EEFLASH
Program/Erase
current
ICCEEFLASHPE
EEFLASH
Sleep current
ICCEEFLASHSB
Power
consumption
POP
328
Temp
Remarks
25°C
with all clocks at max
frequency, Includes
leakage of respective PD
Typ
Max
-
175
-
255
105°C
-
2
25°C
-
2.8
Leakage current of
PD1
-
0.4
-
3.75
Leakage current of
PD2
-
7.2
RUN mode current
of PD1+PD2
Unit
mA
ICCRUN
(VDD)
Power supply
current in PSS
mode
Condition
(VDD)
(VDD)
RUN mode current
of PD4
Leakage current of
PD4
mA
105°C
25°C
mA
105°C
25°C
-
mA
-
96
-
0.1
105°C
25°C
-
mA
-
0.8
Main Timer mode
with CLKMC =
4MHz
-
0.66
-
4.1
RC Timer mode
with CLKRC =
12MHz
-
0.6
-
3.95
Main Timer mode
with CLKSRC =
100kHz
-
0.57
-
3.92
Sub Timer mode
with CLKSC =
32kHz
-
0.56
105°C
25°C
mA
105°C
25°C
mA
105°C
25°C
mA
105°C
25°C
mA
105°C
-
3.91
(VDD)
-
32.9
mA
105°C
(VDP5)
-
21
mA
105°C
-
1.8
mA
105°C
-
11.3
mA
105°C
(VDD)
-
412
A
105°C
(VDP5)
-
11.3
A
105°C
(VDD)
-
28.1
mA
105°C
(VDP5)
-
21
mA
105°C
-
1.8
mA
105°C
-
11.3
mA
105°C
(VDD)
-
236
A
105°C
(VDP5)
-
11
A
105°C
-
1250
mW
-
(VDD)
(VDP5)
(VDD)
(VDP5)
-
Current for one
Instruction Flash
module
Current for one
Data Flash module
-
with all clocks at max
frequency, Includes
leakage of respective PD
with PD2, PD4,
switched off
with PD2, PD4,
switched off
with PD2, PD4,
switched off
with PD2, PD4,
switched off
Only applicable if
PD2 is ON
Only applicable if
PD2 is ON
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
6.4
Sh eet
AC Characteristics
6.4.1
Source Clock timing
(TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 3.0V to 5.5V,
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-5: Source Clock timing
Value
Parameter
Oscillator
Clock frequency
Oscillator
Clock frequency
Oscillator
Clock frequency
Slow Clock
frequency
Fast RCO
clock
frequency
Fast RCO
clock
stability
PLL Clock
frequency
Symbol
fc
fFCI
fCL
fCRS
Pin
Unit
Remarks
5
MHz
When using a crystal oscillator, PLL off
-
MHz
When using an opposite phase external
clock, PLL off
Min
Typ
Max
3
4
-
4
X0,X1
-
4
-
MHz
When using a crystal oscillator or opposite phase external clock, PLL on.
PLL input clock divider (PLLDIVL) must
be greater than 1 since PLL does not support input clock freq more than 16MHz
0
-
62.5
MHz
When using a single phase external clock
in “Fast Clock Input mode”, PLL off
4
-
62.5
MHz
When using a single phase external clock
in Fast Clock Input mode, PLL on
PLL input clock divider (PLLDIVL) must
be greater than 1 since PLL does not support
input clock freq more than 16MHz
X0
32
32.768
100
kHz
When using an oscillation circuit
X0A,
X1A
0
-
100
kHz
When using a opposite phase external
clock
X0A
0
-
50
kHz
When using a single phase external clock
-
50
100
150
kHz
When using slow frequency of RC oscillator
6.3
7.9
10.1
MHz
When using fast frequency of RC oscillator (8MHz mode) and
SYSC_RCCFGR:TRM[7:0] = 0x7F
9.3
11.6
14.6
MHz
When using fast frequency of RC oscillator (12MHz mode) and
SYSC_RCCFGR:TRM[7:0] = 0x7F
-2
-
+2
%
TA = 0..70C
-6
-
+6
%
TA = -40..105C
MHz
Permitted VCO output frequency of PLL
(CLKVCO)
Please also see limitation for fPLLVCO input
frequency
fCRF
fPRCF
fCLKVCO
-
-
200
January 30, 2015, MB9EF226_DS707-00004-2v1-E
-
400
329
Data
Shee t
Table 6-5: Source Clock timing
Value
Parameter
Symbol
Pin
Min
Typ
Unit
Remarks
Max
PLL input
frequency
(after DIVL)
fPLLVCO
-
4
-
16
MHz
Input frequency of PLL after PLLDIVL divider.
PLL input clock divider (PLLDIVL) must
be greater than 1, if the frequency at the
Clock input exceeds 16MHz
PLL Phase
jitter
TPSKEW
-
-5
-
5
ns
For CLKMC (PLL input clock) - 4 MHz, jitter coming from external oscillator, crystal
or resonator is not yet recovered
Input clock
pulse width
PWH, PWL
X0, X1
8
-
-
ns
Duty ratio is about 30% to 70%
Input clock
pulse width
PWHL,
PWLL
X0A,
X1A
5
-
-
ns
Figure 6-1: Source Clock timing
t CYL
V IH
X0
V IL
P WH
P WL
t CYLL
V IH
X0A
V IL
P WHL
330
P WLL
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
6.4.2
Sh eet
Internal Clock timing
(TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 3.0V to 5.5V,
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-6: Internal Clock timing
Parameter
Symbol
Min
Max
Unit
CLK_SYS_PD3
fCLK_SYS_PD3
0
128
MHz
CLK_DBG_PD2
fCLK_DBG_PD2
0
128
MHz
CLK_DBG_PD3
fCLK_DBG_PD3
0
128
MHz
CLK_TRACE_PD2
fCLK_TRACE_PD2
0
128
MHz
CLK_TRACE_PD3
fCLK_TRACE_PD3
0
128
MHz
CLK_HPM_PD2
fCLK_HPM_PD2
0
128
MHz
CLK_HPM_PD3
fCLK_HPM_PD3
0
128
MHz
CLK_CFG_PD4
fCLK_CFG_PD4
0
64
MHz
CLK_DMA_PD2
fCLK_DMA_PD2
0
128
MHz
CLK_MEM_I_PD3
fCLK_MEM_I_PD3
0
128
MHz
CLK_MEM_E_PD3
fCLK_MEM_E_PD3
0
128
MHz
CLK_CFG_PD1
fCLK_CFG_PD1
0
64
MHz
CLK_PERI4_PD2
fCLK_PERI4_PD21
0
128
MHz
CLK_GFX_PD5
fCLK_GFX_PD5
128
MHz
CLK_PERI0_PD2
fCLK_PERI0_PD2
0
64
MHz
CLK_PERI1_PD2
fCLK_PERI1_PD2
0
32
MHz
CLK_PERI3_PD2
fCLK_PERI3_PD2
0
64
MHz
CLK_SPI_PD5
fCLK_SPI_PD5
128
MHz
CLK_PIX_PD5
fCLK_PIX_PD5
400
MHz
CLK_SPI_PD3
fCLK_SPI_PD3
0
128
MHz
CKOT, CKOTX
fCKOT, fCKOTX
0
128
MHz
Remarks
internal clock, set
clock divider >4
for output
Note 1:
If MediaLB is used, a minimum CLK_PERI4_PD2 value of 50 MHz is required.
In addition, the system must be able to handle 6MByte/sec on the bus. This means that depending on the bus
traffic, as well as access to system RAM by other masters, higher CLK_PERI4_PD2 values are required.
January 30, 2015, MB9EF226_DS707-00004-2v1-E
331
Data
6.4.3
Shee t
External Reset timing
(TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 3.0V to 5.5V,
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-7: External Reset timing
Value
Parameter
Reset input time
Symbol
tRSTL
Pin
RSTX
Unit
Min
Typ
Max
500
-
-
Remarks
ns
Figure 6-2: External Reset timing
t RSTL
RSTX
0.2VDP5
332
0.2VDP5
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
6.4.4
Sh eet
External Input timing
(TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 3.0V to 5.5V,
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-8: External Input timing
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
200
-
EIC0_INTk
Input pulse
width
tINH
tINL
Used Pin input
function
External Interrupt
ns
NMI
NMI
Pi_jj
General purpose
IO
RLTn_TIN
Reload Timer
PPG_ETRGx
PPG Trigger input
ADCn_EDGI
AD Converter
Trigger
-2*tCLK_PER + tNF
(*1*2)
-
ns
FRTn_FRCK
Free Running
Timer external
clock
ICUn_INm
Input Capture
UDCn_AIN,
UDCn_BIN,
UDCn_ZIN
Up/Down Counter
*1 tCLK_PER is the period of the corresponding peripheral clock.
*2 tNF is 200ns, if noise filter is enabled and 0ns, if noise filter is bypassed.
Figure 6-3: External Input timing
External Pin input
VIH
VIH
VIL
tINH
January 30, 2015, MB9EF226_DS707-00004-2v1-E
VIL
t INL
333
Data
6.4.5
Shee t
Slew Rate High Current Outputs
(TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 3.0V to 5.5V,
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-9: Slew Rate High Current Outputs
Value
Parameter
Output rise/
fall time
Symbol
tR30
tF30
Pin
Condition
I/O circuit
type SMC
Unit
Output driving
strength set to
“30mA”
Min
Max
15 @
CLOAD=0pF
-
Remarks
ns
Figure 6-4: Slew Rate High Current Output timing
Slew rate output timing
VH
VH = 0.9 x DVCC
VL = 0.1 x DVCC
VH
VL
VL
t R30
334
t F30
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
6.4.6
Sh eet
USART timing
Note: The values given below are for an I/O drive strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum
output timing described in the different tables must be increased by 10ns.
(TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = 3.0V to 5.5V,
DVCC = 3.0V to 5.5V, VSS = 0V, IOdrive = 5mA, CL = 50pF)
Table 6-10: USART timing
VDP5 = 4.5V to 5.5V
Parameter
Symbol
Pin
Unit
Min
Serial clock
cycle time
tSCYCI
SCK
SCK SOT
delay time
tSLOVI
SCK,
SOT
SOT SCK
delay time
tOVSHI
SCK,
SOT
Valid SIN
SCK
tIVSHI
SCK,
SIN
SCK Valid
SIN hold
time
tSHIXI
Serial clock
“L” pulse
width
VDP5 = 3.0V to 4.5V
Condition
4*tCLK_PERI0_P
D2
Max
-
Min
4*tCLK_PERI0_P
D2
Max
-
ns
-20
+20
-30
+30
ns
N*tCLK_PERI0_PD
*1
2 – 20
-
N*tCLK_PERI0_PD
*1
2 – 30
-
ns
tCLK_PERI0_PD2
+ 45
-
tCLK_PERI0_PD2
+ 55
-
ns
SCK,
SIN
0
-
0
-
ns
tSLBHE
SCK
tCLK_PERI0_PD2
+ 10
-
tCLK_PERI0_PD2
+ 10
-
ns
Serial clock
“H” pulse
width
tSHSLE
SCK
tCLK_PERI0_PD2
+ 10
-
tCLK_PERI0_PD2
+ 10
-
ns
SCK SOT
delay time
tSLOVE
SCK,
SOT
-
2
tCLK_PERI0_PD
2 +45
-
2
tCLK_PERI0_PD
2 +45
ns
Valid SIN
SCK
tIVSHE
SCK,
SIN
tCLK_PERI0_PD2/
2 + 10
-
tCLK_PERI0_PD2/
2 + 10
-
ns
SCK Valid
SIN hold
time
tSHIXE
SCK,
SIN
tCLK_PERI0_PD2
+ 10
-
tCLK_PERI0_PD2
+ 10
-
ns
SCK fall
time
tFE
SCK
-
20
-
20
ns
SCK rise
time
tRE
SCK
-
20
-
20
ns
Internal
Shift Clock
Mode
External
Shift Clock
Mode
January 30, 2015, MB9EF226_DS707-00004-2v1-E
335
Data
Shee t
Figure 6-5: USART timing
t SCYCI
0.8*VDP5
SCK for
ESCR:SCES =0
SCK for
ESCR:SCES = 1
0.2*VDP5
0.2*VDP5
0.8*VDP5
0.8*VDP5
t SLOVI
0.2*VDP5
t OVSHI
0.8*VDP5
SOT
0.2*VDP5
t IVSHI
SIN
t SHIXI
V IH
V IH
V IL
V IL
Internal Shift Clock Mode
t SLSHE
V IH
SCK for
ESCR:SCES =0
V IL
t SLOVE
V IL
V IL
t RE
0.8*VDP5
0.2*VDP5
t IVSHE
SIN
V IH
V IH
V IL
t FE
V IH
V IL
V IH
SCK for
ESCR:SCES = 1
SOT
t SHSLE
t SHIXE
V IH
V IH
V IL
V IL
External Shift Clock Mode
336
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Notes:
AC characteristic in CLK synchronized mode.
CL is the load capacity value of pins when testing.
Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some
parameters.
tCLK_PERI0_PD2 is the cycle time of the clock (CLK_PERI0_PD2), Unit: ns
*1: Parameter N depends on tSCYCI and can be calculated as follows:
• if tSCYCI = 2*k*tCLK_PERI0_PD2, then N = k, where k is an integer > 2
• if tSCYCI = (2*k+1)*tCLK_PERI0_PD2, then N = k+1, where k is an integer > 1
Examples:
tSCYCI
N
4*tCLK_PERI0_PD2
2
5*tCLK_PERI0_PD2, 6*tCLK_PERI0_PD2
3
7*tCLK_PERI0_PD2,
8*tCLK_PERI0_PD2
4
….
….
January 30, 2015, MB9EF226_DS707-00004-2v1-E
337
Data
6.4.7
Shee t
I2C timing
(TA = -40C to 105C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 4.5V to 5.5V*4,
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-11: I2C Timing
Standard-mode
Parameter
Fast-mode
Symbol
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
0
100
0
400
kHz
Hold time (repeated) START condition
SDASCL
tHDSTA
4.0
-
0.6
-
s
“L” width of the SCL clock
tLOW
4.7
-
1.3
-
s
“H” width of the SCL clock
tHIGH
4.0
-
0.6
-
s
Set-up time for a repeated START
condition
SCLSDA
tSUSTA
4.7
-
0.6
-
s
Data hold time
SCLSDA
tHDDAT
0
3.45
0
0.9
s
Data set-up time
SDASCL
tSUDAT
250
-
100
-
ns
Set-up time for STOP condition
SCLSDA
tSUSTO
4
-
0.6
-
s
Bus free time between a STOP
and START condition
tBUS
4.7
-
1.3
-
s
Output fall time from 0.7*VDP5 to
0.3*VDP5 with a bus capacitance
from 10pF to 400pF
tof
20 +
0.1*Cb *2
250
20 +
0.1*Cb *2
250
ns
Capacitive load for each bus line
Cb
-
400
-
400
pF
Pulse width of spikes which will be
suppressed by input noise filter
tSP
n/a
n/a
0
1*tCLK_PERI0_PD2 *3
ns
*1: For use at over 100 kHz, set the CLK_PERI0_PD2 to at least 6 MHz.
*2: Cb = capacitance of one bus line in pF.
*3: tCLK_PERI0_PD2 is the cycle time of the peripheral clock CLK_PERI0_PD2
*4: I2C spec only guaranteed at VDP5 = 4.5V to 5.5V.
338
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Figure 6-6: I2C timing
SDA
t LOW
t SUDAT
t BUS
t HDSTA
SCL
t HDSTA
t HDDAT
t HIGH
January 30, 2015, MB9EF226_DS707-00004-2v1-E
t SUSTA
t SUSTO
339
Data
6.4.8
Shee t
HSSPI timing
(TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 3.0V to 5.5V,
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-12: HSSPI Interface timing (Master Mode,)
Value
Parameter
Symbol
HSSPI clock frequency
340
Units
Remarks
Min
Typ
Max
-
-
64
MHz
12.1
-
-
ns
no clock retiming
5.6
-
-
ns
with clock retiming
0
-
-
ns
no clock retiming
1.5
-
-
ns
with clock retiming
Input setup time
(HSSPIn_DATAi)
TIS,DATA
Input hold time
(HSSPIn_DATAi)
TIH,DATA
Output delay time
(HSSPIn_DATAo)
TOD,DATA
-
-
3.8
ns
Output hold time
(HSSPIn_DATAo)
TOH,DATA
5
-
-
ns
Output delay time
(HSSPIn_SSELo)
TOD,SSEL
-
-
5.05
ns
Output hold time
(HSSPIn_SSELo)
TOH,SSEL
0
-
-
ns
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Figure 6-7: HSSPI Interface timing
HSSPIn_CLK
T IS,DATA T IH,DATA
HSSPIn_DATAi
T IS,SSEL T IH,SSEL
HSSPIn_SSELi
TOD,DATA
T OH,DATA
TOD,SSEL
T OH,SSEL
HSSPIn_DATAo
HSSPIn_SSELo
Table 6-13: HSSPI Interface timing (Slave Mode)
Value
Parameter
Symbol
Units
Min
Typ
Max
-
-
25
MHz
HSSPI clock frequency
Input setup time
(HSSPIn_DATAi)
TIS,DATA
5
-
-
ns
Input hold time
(HSSPIn_DATAi)
TIH,DATA
0
-
-
ns
Input setup time
(HSSPIn_SSELi)
TIS,SSEL
8.2
-
-
ns
Input hold time
(HSSPIn_SSELi)
TIH,SSEL
2
-
-
ns
Output delay time
(HSSPIn_DATAo)
TOD,DATA
-
-
15.5
ns
Output hold time
(HSSPIn_SSELo)
TOH,DATA
0
-
-
ns
January 30, 2015, MB9EF226_DS707-00004-2v1-E
Remarks
341
Data
6.4.9
Shee t
SPI timing
(TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 3.0V to 5.5V,
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
For each SPI module, several combinations of I/O pins can be chosen for each SPI signal. The timing depends
on the actual combination and is given below as separate values for each possible type of I/O-cell. When I/O/
cells of different types are mixed, the worst case table, called “OVERALL SPI Interface timing” must be used.
In Master Mode, using the clock retiming function improves the setup and hold times for input data.
The usable maximum clock frequency depends on the transmission mode (Master to Slave / Slave to Master,
using clock-retiming or not). An example for caculation is given below each table.
Table 6-14: OVERALL SPI Interface timing
Parameter
Symbol
Master Mode,
Master Mode,
non-retimed clock
retimed clock
Slave Mode
Min
Max
Min
Max
Min
Max
Unit
Input setup time
(SPIn_DATAi)
TIS,DATA
24.9
-
9.9
-
9.8
-
ns
Input hold time
(SPIn_DATAi)
TIH,DATA
-6.1 *1
-
9.9
-
9.8
-
ns
Output delay time
(SPIn_DATAo)
TOD,DATA
-
12.2
-
12.2
-
41.5
ns
Output hold time
(SPIn_DATAo)
TOH,DATA
-5.3 *1
-
-5.3 *1
-
6.3
-
ns
Input setup time
(SPIn_SSELi)
TIS,SSEL
-
-
-
-
11.9
-
ns
Input hold time
(SPIn_SSELi)
TIH,SSEL
-
-
-
-
7.9
-
ns
Output delay time
(SPIn_SSELo)
TOD,SSEL
-
12.1
-
12.1
-
-
ns
Output hold time
(SPIn_SSELo)
TOH,SSEL
-4.6 *1
-
-4.6 *1
-
-
-
ns
Example for calculation of max. frequencies for communication of Master (retimed mode) and Slave:
Transmission
Half Period Time
Max. Frequency
Unit
From Master to Slave
T/2 = TOD,DATA (Master) + TIS,DATA (Slave)
20.8
MHz
From Slave to Master
T/2 = TOD,DATA (Slave) + TIS,DATA (Master)
10.5
MHz
Note: *1 : A negative hold time implies that the clock edge output is delayed with respect to data output. In any
case, an external device that will receive data, must use a sampling point that is outside the time interval
given by Output hold time and Output delay time.
342
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 6-15: SPI Interface timing for all cells of type RSDS
Parameter
Symbol
Master Mode,
Master Mode,
non-retimed clock
retimed clock
Slave Mode
Min
Max
Min
Max
Min
Max
Unit
Input setup time
(SPIn_DATAi)
TIS,DATA
23.8
-
3.1
-
3.0
-
ns
Input hold time
(SPIn_DATAi)
TIH,DATA
-7.0 *1
-
8.4
-
8.3
-
ns
Output delay time
(SPIn_DATAo)
TOD,DATA
-
11.6
-
11.6
-
41.5
ns
Output hold time
(SPIn_DATAo)
TOH,DATA
-4.1 *1
-
-4.1 *1
-
7.6
-
ns
Input setup time
(SPIn_SSELi)
TIS,SSEL
-
-
-
-
7.8
-
ns
Input hold time
(SPIn_SSELi)
TIH,SSEL
-
-
-
-
3.8
-
ns
Output delay time
(SPIn_SSELo)
TOD,SSEL
-
11.5
-
11.5
-
-
ns
Output hold time
(SPIn_SSELo)
TOH,SSEL
2.6
-
2.6
-
-
-
ns
Example for calculation of max. frequencies for communication of Master (retimed mode) and Slave:
Transmission
Half Period Time
Max. Frequency
Unit
From Master to Slave
T/2 = TOD,DATA (Master) + TIS,DATA (Slave)
25.9
MHz
From Slave to Master
T/2 = TOD,DATA (Slave) + TIS,DATA (Master)
11.2
MHz
Note: *1 : A negative hold time implies that the clock edge output is delayed with respect to data output. In any
case, an external device that will receive data, must use a sampling point that is outside the time interval
given by Output hold time and Output delay time.
January 30, 2015, MB9EF226_DS707-00004-2v1-E
343
Data
Shee t
Table 6-16: SPI Interface timing for all cells of type BIDI50
Parameter
Symbol
Master Mode,
Master Mode,
non-retimed clock
retimed clock
Slave Mode
Min
Max
Min
Max
Min
Max
Unit
Input setup time
(SPIn_DATAi)
TIS,DATA
24.4
-
5.5
-
5.2
-
ns
Input hold time
(SPIn_DATAi)
TIH,DATA
-6.1*1
-
5.4
-
5.3
-
ns
Output delay time
(SPIn_DATAo)
TOD,DATA
-
9.2
-
9.2
-
30.2
ns
Output hold time
(SPIn_DATAo)
TOH,DATA
-4.7*1
-
-4.7*1
-
6.4
-
ns
Input setup time
(SPIn_SSELi)
TIS,SSEL
-
-
-
-
8.3
-
ns
Input hold time
(SPIn_SSELi)
TIH,SSEL
-
-
-
-
2.2
-
ns
Output delay time
(SPIn_SSELo)
TOD,SSEL
-
7.4
-
7.4
-
-
ns
Output hold time
(SPIn_SSELo)
TOH,SSEL
0.3
-
0.3
-
-
-
ns
Example for calculation of max. frequencies for communication of Master (retimed mode) and Slave:
Transmission
Half Period Time
Max. Frequency
Unit
From Master to Slave
T/2 = TOD,DATA (Master) + TIS,DATA (Slave)
31.8
MHz
From Slave to Master
T/2 = TOD,DATA (Slave) + TIS,DATA (Master)
14.0
MHz
Note: *1 : A negative hold time implies that the clock edge output is delayed with respect to data output. In any
case, an external device that will receive data, must use a sampling point that is outside the time interval
given by Output hold time and Output delay time.
344
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 6-17: SPI Interface timing for all cells of type SMC
Parameter
Symbol
Master Mode,
Master Mode,
non-retimed clock
retimed clock
Slave Mode
Min
Max
Min
Max
Min
Max
Unit
Input setup time
(SPIn_DATAi)
TIS,DATA
24.9
-
4.4
-
4.3
-
ns
Input hold time
(SPIn_DATAi)
TIH,DATA
-6.8*1
-
5.3
-
5.2
-
ns
Output delay time
(SPIn_DATAo)
TOD,DATA
-
8.9
-
8.9
-
32.1
ns
Output hold time
(SPIn_DATAo)
TOH,DATA
-0.8*1
-
-0.8*1
-
7.7
-
ns
Input setup time
(SPIn_SSELi)
TIS,SSEL
-
-
-
-
6.7
-
ns
Input hold time
(SPIn_SSELi)
TIH,SSEL
-
-
-
-
3.1
-
ns
Output delay time
(SPIn_SSELo)
TOD,SSEL
-
7.4
-
7.4
-
-
ns
Output hold time
(SPIn_SSELo)
TOH,SSEL
1.8
-
1.8
-
-
-
ns
Example for calculation of max. frequencies for communication of Master (retimed mode) and Slave:
Transmission
Half Period Time
Max. Frequency
Unit
From Master to Slave
T/2 = TOD,DATA (Master) + TIS,DATA (Slave)
35.4
MHz
From Slave to Master
T/2 = TOD,DATA (Slave) + TIS,DATA (Master)
13.6
MHz
*1 : A negative hold time implies that the clock edge output is delayed with respect to data output. In any case,
an external device that will receive data, must use a sampling point that is outside the time interval given by
Output hold time and Output delay time.
January 30, 2015, MB9EF226_DS707-00004-2v1-E
345
Data
Shee t
Figure 6-8: SPI Interface timing
SPIn_CLK
T IS,DATA T IH,DATA
SPIn_DATAi
T IS,SSEL
T IH,SSEL
SPIn_SSELi
TOD,DATA
T OH,DATA
TOD,SSEL
T OH,SSEL
SPIn_DATAo
SPIn_SSELo
346
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
6.5
Sh eet
Analog Digital Converter
(TA = -40°C to 105°C, 3.0V - AVRH5, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V,
VDP5 = AVDD5 = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-18: Analog Digital Converter
Value
Parameter
Symbol
Pin
Unit
Min
Typ
Max
Remarks
Resolution
-
-
-
-
10
bit
Total error
-
-
-3
-
+3
LSB
Nonlinearity
error
-
-
-2.5
-
+2.5
LSB
Differential
nonlinearity
error
-
-
-1.9
-
+1.9
LSB
Full scale
transition
voltage
VFST
ANi
Typ
- 20
AVRH5 - 1.5
LSB
Typ
+ 20
mV
between 1022 and
1023
Zero Transition
Voltage
VZT
ANi
Typ
- 20
AVSS5 + 0.5
LSB
Typ
+ 20
mV
between 0 and 1
Conversion
Rate
TS
353
-
1186
KS/s
646.8
-
-
ns
Fclk=17MHz,
Tclk=58.8ns * 11
clocks
ns
AVDD5 =
4.5V...5.5V,
Fclk=4MHz,
Tclk=250ns * 11
clocks
Comparison
Time
pi_jj(A
NIN)
TCOMP
-
2750
-
-
-
1837
ns
AVDD5 =
3.0V...4.5V,
Fclk=6MHz,
Tclk=167ns * 11
clocks
-1
-
+1
A
TA  25C,
AVSS5 < VI < AVDD5,
AVRH5
-3
-
+3
A
TA  105C,
AVSS5 < VI < AVDD5,
AVRH5
Analog input
leakage
current (during
conversion)
IAIN
Analog input
voltage range
VAIN
ANn
AVSS5
-
AVRH5
V
Reference
voltage range
AVRH5
AVRH5
AVDD5 - 0.5
-
AVDD5
V
ANn
January 30, 2015, MB9EF226_DS707-00004-2v1-E
347
Data
Shee t
Table 6-18: Analog Digital Converter
Value
Parameter
Symbol
IA
Power supply
current
Reference
voltage current
Offset between
input channels
IAH
Pin
AVDD5
Unit
Remarks
3.4
mA
A/D Converter active
-
6
A
25°C,
A/D Converter not
operated
-
-
11
A
105°C,
A/D Converter not
operated
Min
Typ
Max
-
2
AVDD5
IR
AVRH5
-
0.6
1
mA
A/D Converter active
IRH
AVRH5
-
-
0.6
A
A/D Converter not
operated
-
ANn
-
-
4
LSB
Note:The accuracy gets worse as |AVRH5 | becomes smaller.
Minimum Sampling Time
The minimum sampling time can be calculated from the following formula:
For pins ADC0_AN0..25:
Tsamp = 7.63 x [ Rext x ( Cext + 16pF ) + ( Rext + 1.78kOhm ) x 18.7pF ]
For Pins ADC0_AN26..31:
Tsamp = 7.63 x [ Rext x ( Cext + 16pF ) + ( Rext + 1.78kOhm ) x 2.6pF + (Rext + 3.55 kOhm ) x 18.7pF ]
Definition of A/D Converter Terms
Resolution: Analog variation that is recognized by an A/D converter.
Total error: Difference between the actual value and the ideal value. The total error includes zero transition error, full-scale transition error and nonlinearity error.
Nonlinearity error: Deviation between a line across zero-transition line (00 0000 0000 <--> 00 0000 0001) and
full-scale transition line (11 1111 1110 <--> 11 1111 1111) and actual conversion characteristics.
Differential linearity error: Deviation of input voltage, which is required for changing output code by 1 LSB, from
an ideal value.
Zero reading voltage: Input voltage which results in the minimum conversion value.
Full scale reading voltage: Input voltage which results in the maximum conversion value.
348
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Total error
3FF
1.5 LSB
3FE
Actual conversion
characteristics
3FD
Digital output
{1 LSB X (N−1) + 0.5 LSB}
004
V NT
(Actually−measured value)
003
Actual conversion
characteristics
002
Ideal characteristics
001
0.5 LSB
AVRH
0
Analog input
Total error of digital output "N" =
1 LSB = (Ideal value)
V NT − {1 LSB X (N−1) + 0.5 LSB}
AVRH
1024
1 LSB
[LSB]
[V]
N : A/D converter digital output value
V OT (Ideal value) = 0 + 0.5 LSB [V]
V FST (Ideal value) = AVRH − 1.5LB [V]
V NT : A voltage at which digital output transition from (N−1) to N.
January 30, 2015, MB9EF226_DS707-00004-2v1-E
349
Data
6.6
Shee t
FLASH memory program/erase characteristics
(TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 3.0V to 5.5V,
DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V)
Table 6-19: Program/erase time for TCFLASH and EEFLASH
Value
Parameter
Sector Erase Time
Macro Erase Time
Unit
Min
Typ*1
Max
Small Sector
-
0.3
1.1
s
Large Sector
-
0.7
3.7
s
TCFLASH
-
13.6
68
s
EEFLASH
-
2.4
8.8
s
-
12
384
s
Word Programming Time
Remarks
The internal programming
time before the erase procedure starts is included.
Note:
*1: Typical definition: TA=25°C / VDD=1.2V / Program/Erase cycle = Immediately after shipment.
Table 6-20: Program/Erase cycle and Data Retention time*2
Program/Erase cycle at
each sector
Data Retention time
Min Value
Unit
Min Value
Unit
1000
cycles
20
years
10000
cycles
10
years
100000
cycles
5
years
Note:
*2: These values were converted from the technology qualification using Arrhenius equation to translate high
temperature measurements into normalized values at + 85°C.
Table 6-21: Execution Time Limit
Parameter
Value
Unit
1.3
ms
TCFLASH
187.2
s
EEFLASH
63
s
7.8
s
Program Execution Time limit*3
Macro Erase Execution Time limit
Sector Erase Execution Time limit*4
Note:.
*3: This is the time it takes for the macro to detect a Hang up 1 error when 1 is to be programmed to a memory
cell whose memory value is either 0 or X.
*4: See the Hardware Manual for an explanation about Flash Timing Limit Exceeded Flags. The time during
Sector Erase Suspend (period from Suspend Command Write Cycle to Resume Command Write Cycle)
is not included.
350
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
6.7
Sh eet
RC Oscillator Frequency
This chapter provides reference values for the RC Configuration Register (SYSC_RCCFGR) settings. The corresponding oscillator is commoly referred to as the “12 MHz RC Oscillator”, because its typical frequency at
the central setting is about 12 MHz, with the SYSC_RCCFGR:SFREQ bit set to “1”.
When the SYSC_RCCFGR:SFREQ bit is set to “0”, the central setting corresponds to about 8 MHz.
The default value of SYSC_RCCFGR:SFREQ is “1” and the default value of SYSC_RCCFGR:TRM[7:0] is
“0xFF”, so the default frequency setting is 16.9 MHz (typical value).
Figure 6-9: RC Oscillator frequency at SYSC_RCCFGR:SFREQ = 0
MHz
RC Oscillator frequency
14.7
11.6
10.1
9.3
7.9
6.3
5.2
4.1
3.3
0x00
0x7F
0xFF
SYSC_RCCFGR:TRM[7:0] setting
Note: The provided function values are not guaranteed and can serve for reference, only. Guaranteed values
are listed in Table 6-5 on page 329.
January 30, 2015, MB9EF226_DS707-00004-2v1-E
351
Data
Shee t
Figure 6-10: RC Oscillator frequency at SYSC_RCCFGR:SFREQ = 1
MHz
21.3
RC Oscillator frequency
16.9
14.6
13.4
11.6
9.3
7.7
6.1
4.9
0x00
0x7F
0xFF
SYSC_RCCFGR:TRM[7:0] setting
Note: The provided function values are not guaranteed and can serve for reference, only. Guaranteed values
are listed in Table 6-5 on page 329.
352
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
7 Procedures
7.1
Boundary scan
Boundary scan is supported using standard 1EEE 1149.1 JTAG interface. A 5-pin JTAG connection is available
on QFP-176 (production variant), as well as QFP-240 (bond-out variant). Instruction register supported is 6bits wide, and the standard instructions listed In Table 7-1 are supported. Any other value of instruction register
is reserved, and should not be entered. Entering reserved values can result in indeterminate operation.
Boundary scan mode may be entered by setting pins MODE = “1” and MD[0] = “0”.
Table 7-1: Standard Instructions
Instruction Code
(in binary)
Instruction
Accessible Data Register
‘000000’
EXTEST
Boundary scan chain
‘000001’
SAMPLE
Boundary scan chain
‘000010’
PRELOAD
Boundary scan chain
‘000011’
IDCODE
Device ID code register
For MB9EF226, IDCODE
is 0x0F159009
‘000100’
USERCODE
Device user code register
For MB9EF226, USERCODE is 32-bits long, and
is 0xC4202012
‘000101’
HIGHZ
Boundary scan chain
‘000110’
CLAMP
Boundary scan chain
‘010001’
IO_CNTRL
IO Control register
‘111111’
BYPASS
Bypass register
January 30, 2015, MB9EF226_DS707-00004-2v1-E
Remarks
Command must be followed by 16bit data value:
0x04pp,
where pp is a pin control
setting from table Table 72
353
Data
Shee t
Table 7-2: IO Control (IO_CNTRL) register
IO_CNTRL
reserved
reserved
reserved
DCPDN
DCPUP
OUTDR[1]
OUTDR[0]
PITILS[1]
PITILS[0]
R0W0
R0W0
RW
RW
RW
RW
RW
RW
0
R0W0
1
I2C
2
RW
3
SEL
4
RW
5
reserved
6
R0W0
7
reserved
8
R0W0
9
reserved
10
R0W0
11
reserved
12
R0W0
13
reserved
14
R0W0
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 7-3: IO Control (IO_CNTRL) register bits
Bit Position
Bit FieldName
Bit Description
[15:11]
reserved
Reserved. Always write 0 to these bits.
[10]
SEL
Selection of DCPDN, DCPUP, OUTDR and PITILS
"0": IO_CNTRL[5:0] are disabled. Input buffers are disabled.
"1": IO_CNTRL[5:0] will control IO pads
[9]
I2C
Extends IO_CNTRL[3:2], but for I2C IO cell only (see below)
"0” : set I2C cell to value selected by IO_CNTRL[3:2]
"1" : set I2C cell to "pseudo open drain"
[8:6]
reserved
Reserved. Always write 0 to these bits.
[5]
DCPDN
Control all pull-down resistors of the IOs
Valid if bit [10] is "1"
"0” : All pull-downs are disabled
"1” : All pull-downs are enabled
[4]
DCPUP
Control all pull-up resistors of the IOs
Valid if bit [10] is "1"
"0” : All pull-uos are disabled
"1” : All pull-ups are enabled
[3:2]
OUTDR
Output driver strength
Valid if bit 10 is "1"
Bit selection depends on IO cell type (See "IO Circuit Type" on page 79.)
OUTDR[1:0]
354
BIDI50
BIDI33
SMC
I2C
RSDS/
TTL33
“00”
5mA
12mA
5mA
5mA
5mA
“01”
2mA
12mA
2mA
2mA
2mA
“10”
1mA
12mA
1mA
1mA
10mA
“11”


30mA

20mA
x + bit[9] = “1”



pseudo
open drain
-
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Bit Position
Bit FieldName
[1:0]
PITILS
Sh eet
Bit Description
Pin Input Test Input Level Select
Valid if bit 10 is "1"
"00”: Hysteresis
"01”: Automotive
"10”: TTL
"11”: CMOS
Note: When Bit[10] = “0”, all input buffers are disabled in Boundary Scan mode. Then, input of data via external
pins to the BSR (Boundary Scan Register) is impossible. Therefore, the minimum setting to allow input
to the BSR is 0x0400.
Procedure for Configuration for Port Input
1. MODE clipped to ’1’ and MD[0] clipped to ’0’.
2. release JTAG_NRST and RSTX.
3. JTAG-Instruction IO_CNTRL (010001)
4. set IO_CNTRL-reg 10th bit: (e.g. 0000010000000000)
5. JTAG-Instruction SAMPLE. -> Port Input
The serial chain starts with the I/O closest to JTAG_TDI pin, and ends with the I/O closest to the JTAG_TDO
pin. Details may be obtained from BSDL files (see http://mcu.emea.fujitsu.com/mcu_portal.htm) released per
package.
January 30, 2015, MB9EF226_DS707-00004-2v1-E
355
Data
7.2
Shee t
Flash Parallel Programming
Flash Parallel Programming (FPP) mode is supported to allow for quick programming/erase of embedded
flashes. In this mode program or erase of flash is done using a flash memory programmer directly via external
pins. Flash programming is done either in 8-bit or 16-bit mode through the command sequence. Refer Section
4 of Tightly Coupled Flash Chapter of HWM for details of Flash program/erase command sequence. Flash addressing in this mode is direct physical addressing, with higher order bits used for flash macro selection.
In MB9EF226 device, there are 2 flash macros of 1MB+64KB size and 1 flash macro of 64KB. Details about
flash macro sectoring are shown in Table 7-4
Table 7-4: Flash sector information
Flash Macro
Macro size
Small Sectors Large sectors
(8KB/sector) (64KB/sector)
TCFLASH macro 0
1MB + 64KB
8
16
TCFLASH macro 1
1MB + 64KB
8
16
EEFLASH macro
64KB
8
Not Available
Details about mapping of flash pins to external pins are presented in Table 7-5.
Table 7-5: Flash pin mapping to external pins (1 / 3)
External Pin External Pin
External Pin
Number
Number
Name
(QFP-240)
(QFP-176)
Flash macro pin
Function
Flash select signal. Refer Table 7-11 for
additional details regarding use of DFSEL.
93
128
P1_47
DFSEL
3
3
X0
FCLK
Flash clock
1
1
MODE
MODE
Mode pin to enter test mode (MODE = ‘1’)
7
8
RSTX
RSTX
Device Reset pin
11
15
P1_30
SMD[0]
Set to ‘1’ when entering FPP mode.
12
16
P1_31
SMD[1]
Set to ‘1’ when entering FPP mode.
13
17
P1_32
MD[0]
Set to ‘1’ when entering FPP mode.
14
18
P1_33
MD[1]
Set to ‘1’ when entering FPP mode.
15
19
P1_34
MD[2]
Set to ‘1’ when entering FPP mode.
External flash reset pin
16
21
P1_35
FRSTX
‘0’ : Reset
‘1’ : Normal operation
17
22
P1_36
FRSTRX
External power enable to flash macro at
5V
‘0’ : Reset
‘1’ : Normal operation
Flash macro enable
99
140
P1_00
CEX
‘0’ : Macro recognizes read/write commands
‘1’ : Neither read operation nor write operation is executed
356
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 7-5: Flash pin mapping to external pins (2 / 3)
External Pin External Pin
External Pin
Number
Number
Name
(QFP-176)
(QFP-240)
Flash macro pin
Function
Write enable
20
26
P1_61
WEX
‘0’ : Macro recognizes read commands
‘1’ : Macro recognizes write commands
Byte access enable
21
27
P1_62
BYTEX
‘0’ : 8-bit write mode
‘1’ : 16-bit write mode
Direction control signal for shared pins
like data and ECC data
‘0’ : Shared data/ECC data pins are in
output mode
136
185
P0_40
OEX
‘1’ : Shared data/ECC data pins are in input mode
limitation applies for read (output) data
(they appear as logical ORed of all
FLASHs)
100
141
P1_01
FA[00]
101
142
P1_02
FA[01]
102
143
P1_03
FA[02]
103
144
P1_04
FA[03]
104
145
P1_05
FA[04]
105
146
P1_06
FA[05]
106
147
P1_07
FA[06]
109
152
P1_08
FA[07]
110
153
P1_09
FA[08]
111
154
P1_10
FA[09]
112
155
P1_11
FA[10]
113
156
P1_12
FA[11]
114
157
P1_13
FA[12]
115
158
P1_14
FA[13]
116
159
P1_15
FA[14]
119
164
P1_16
FA[15]
120
165
P1_17
FA[16]
121
166
P1_18
FA[17]
122
167
P1_19
FA[18]
123
168
P1_20
FA[19]
124
169
P1_21
FA[20]
125
170
P1_22
FA[21]
126
171
P1_23
FA[22]
January 30, 2015, MB9EF226_DS707-00004-2v1-E
Flash address. Refer Table 7-8 for additional details regarding use of FA[21].
357
Data
Shee t
Table 7-5: Flash pin mapping to external pins (3 / 3)
External Pin External Pin
External Pin
Number
Number
Name
(QFP-176)
(QFP-240)
Flash macro pin
150
203
P2_32
DIN[00]/DOR[00]
151
204
P2_33
DIN[01]/DOR[01]
152
206
P2_34
DIN[02]/DOR[02]
153
207
P2_35
DIN[03]/DOR[03]
154
208
P2_36
DIN[04]/DOR[04]
155
209
P2_37
DIN[05]/DOR[05]
158
215
P2_38
DIN[06]/DOR[06]
159
216
P2_39
DIN[07]/DOR[07]
160
217
P2_40
DIN[08]/DOR[08]
161
218
P2_41
DIN[09]/DOR[09]
162
220
P2_42
DIN[10]/DOR[10]
163
221
P2_43
DIN[11]/DOR[11]
164
222
P2_48
DIN[12]/DOR[12]
165
223
P2_49
DIN[13]/DOR[13]
168
229
P2_50
DIN[14]/DOR[14]
169
230
P2_51
DIN[15]/DOR[15]
141
192
P0_43
EDIN[00]/EDOR[00]
142
194
P0_44
EDIN[01]/EDOR[01]
143
195
P0_45
EDIN[02]/EDOR[02]
144
196
P0_46
EDIN[03]/EDOR[03]
145
197
P0_47
EDIN[04]/EDOR[04]
148
201
P0_48
EDIN[05]/EDOR[05]
149
202
P0_49
EDIN[06]/EDOR[06]
Function
Shared data input/output
Refer Section 7.2.1.2 / 7.2.1.3
Shared ECC data input/output
Refer Section 7.2.1.2 / 7.2.1.3
ECC write access enable
137
186
P0_41
ECCA
‘0’ : ECC write disable
‘1’ : ECC write enable
Internal voltage ready/busy flag at 5V
134
183
P0_24
RDYR
‘0’ : Busy
‘1’ : Ready
FLASH internal state at PPROGRAM,
ERASE and power on
0: busy
140
191
P0_42
RDY
1: ready
Output behaves as open drain (needs
pull-up) to support programming multiple
devicves at once.
64-bit read enable
135
184
P0_25
RD64
0 : 32-bit read mode
1 : 64-bit read mode
358
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Timing requirements for flash signals are provided in Figure 7-1:"Flash timing parameters" and Table 76:"Flash timing requirements".
Figure 7-1: Flash timing parameters
RDYR /
January 30, 2015, MB9EF226_DS707-00004-2v1-E
359
Data
Shee t
Table 7-6: Flash timing requirements
Parameter
Symbol
Cycle Time
Value
Unit
tCY
min
100
ns
Clock High Time
tCWH
min
25
ns
Clock Low Time
tCWL
min
25
ns
CEX setup
tSCE
min
20
ns
CEX hold
tHCE
min
20
ns
WEX setup
tSWE
min
20
ns
WEX hold
tHWE
min
20
ns
RD64 setup
tSRD
min
20
ns
RD64 hold
tHRD
min
20
ns
BYTEX setup
tSBW
min
20
ns
BYTEX hold
tHBW
min
20
ns
ECCA setup
tSEC
min
20
ns
ECCA hold
tHEC
min
20
ns
OEX setup
tSOE
min
20
ns
OEX hold
tHOE
min
20
ns
DFSEL setup
tSDF
min
20
ns
DFSEL hold
tHDF
min
20
ns
FA setup
tSA
min
20
ns
FA hold
tHA
min
20
ns
DIN/EDIN setup
tSI
min
20
ns
DIN/EDIN hold
tHI
min
20
ns
RDY output delay
tACY
min
80
ns
DOR/EDOR
put delay
tACC
min
80
ns
tHD
min
5
ns
out-
DOR/EDOR hold
Note:
360
•
Input Data should change at falling edge of X0 clock.
•
Output data should be sampled at next rising edge of X0 clock.
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
7.2.1
Sh eet
Memory Map
This flash memory consists of 16 sectors of 64k byte (large sector) and 8 sectors of 8k byte (small sector).
A large sector is composed of 16k word, and a small sector is composed of 2k word. 1word data width is 39bit
(regular bit: 32bit + ECC parity bit: 7bit) for both large sector and small sector.
7.2.1.1
Address Space & Memory Cell Select Address Assignment
The select address assignment is listed below. The assignment in the large sector and that in the small sector
differ.
When the small sector (FA[20]=0) is selected, no matter what the values (1/0) of FA[19:16] are, the memory
cell to be used is determined according to the values of FA[15:0].

Large Sector (0x100000 ~ 0x1FFFFF)
Table 7-7: Large Sector (0x100000 ~ 0x1FFFFF)
• In read or program mode, an address pin input is ignored as shown below. Apply a given value (1/0) to
the corresponding pin. For the correspondence between data output pins and data input pins, see section
7.2.1.2 and section 7.2.1.3.
8bit program mode (BYTEX=0) : Ignore none of FA[20:0] and input 8bit selected in FA[20:0].
16bit program mode (BYTEX=1) : Ignore FA[0] and input 16bit.
•
FPP mode can only output 8 or 16 bit.
•
RD64 should always be kept 0.
•
BYTEX=0: DQ[7:0] is used
•
BYTEX=1: DQ[15:0] is used

Small Sector (0x0*0000 ~ 0x0*FFFF)
Table 7-8: Small Sector (0x0*0000 ~ 0x0*FFFF)
The left asterisk mark in the value indicates a given value (except an indeterminate value).
• When small sector is selected (FA[20]=0), input a given value (1/0) to FA[19:16] pins.
• In read or program mode, an address pin input is ignored as shown below. Apply a given value (1/0) to
the corresponding pin. For the correspondence between data output pins and data input pins, see section
7.2.1.2 and section 7.2.1.3.
8bit program mode (BYTEX=0) : Ignore none of FA[20,15:0] and input 8bit selected in FA[20,15:0].
16bit program mode (BYTEX=1) : Ignore FA[0] and input 16bit.
•
FPP mode can only output 8 or 16 bit.
•
RD64 should always be kept 0.
•
BYTEX=0: DQ[7:0] is used
•
BYTEX=1: DQ[15:0] is used
January 30, 2015, MB9EF226_DS707-00004-2v1-E
361
Data
7.2.1.2
Shee t
Output Data Table
In 32bit read mode, the data is output to different output pins based on the sector-selected lowest address
values as shown in Table 7-9:.
Table 7-9: Data Output Correspondence Table in Read Bit Modes
• FA[#] indicates the lowest bit of sector-selected address, i.e. FA[16] when the large sector is
selected (FA[n]=1), and FA[13] when the small sector is selected (FA[n]=0).
• Even Sector indicates an even-number-th sector (large sector FA[16]=0 / small sector FA[13]=0). Odd
Sector indicates an odd-number-th sector (larget sector FA[16]=1 / small sector FA[13]=1) "even-numberth" and "odd-number-th" respectively indicate the even number and odd number in Sector No. values
shown in Section 7.2.1"Memory Map".
7.2.1.3
Input Data Table
In 8bit program mode, the data of the different input pins based on the FA[0] values is programmed as
shown in the Table 7-10:.
When ECCA=1 is input at the program data input, the data is written to ECC parity bit as well as Regular bit.
When ECCA=0 is input at the program data input, the data is written only to Regular bit. In this case, EDIN[6:0]
input value is "don’t care," and regardless of the value, no value is written to ECC parity bit. In the case of erase
operation, regardless of input values to ECCA, both Regular bit and ECC parity bit are erased together.
362
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Table 7-10: Correspondence Table of Data Input and Memory Cell Bit in Program Bit Modes
• "Any" a value of either 1 or 0.
• FA[#] indicates the lowest bit of sector-selected address, i.e. FA[16] when the large sector is
selected (FA[n]=1), and FA[13] when the small sector is selected (FA[n]=0). When programming, in both
8bit mode and 16bit mode, program/erase operation is executed per one sector specified by the selected
addresses.
• Program Data Input means the 4th write cycle of a program command in the normal operation state and
the 2nd write cycle of a program command in the Unlock-bypass state.
• Command Data Input means the write cycles in the write command sequence other than those
mentioned above in which program data is input.
January 30, 2015, MB9EF226_DS707-00004-2v1-E
363
Data
7.2.2
Shee t
Flash macro selection and address mapping in FPP
The TC-Flash macro can be accessed using the address decoding scheme as mentioned in Table 7-11.
Table 7-11: Flash macro selection
DFSEL
FA[21]
Flash Macro selection
0
0
TCFLASH macro 0
0
1
TCFLASH macro 1
However, device level memory map differs from actual physical address to flash macro. Hence, it is expected
that the flash parallel programmer must translate CPU mode addressing to actual physical address to flash.
Hence, CPU execution code must be located at physical addresses that are mapped to the CPU mode addresses.
Translation of CPU mode address to actual physical address differs based on whether small or large sectors
are accessed. Address translation for small sectors of TCFLASH macro 0 and 1 is as shown in Table 7-12.
Table 7-12: TCFlash small sectors address translation
Flash Address Bit
CPU Address Bit
FA[21]
0
FA[20]
0
FA[19]
0
FA[18]
0
FA[17]
0
FA[16]
0
FA[15]
ADDR[15]
FA[14]
ADDR[14]
FA[13]
ADDR[02]
FA[12]
ADDR[13]
FA[11]
ADDR[12]
FA[10]
ADDR[11]
FA[09]
ADDR[10]
FA[08]
ADDR[09]
FA[07]
ADDR[08]
FA[06]
ADDR[07]
FA[05]
ADDR[06]
FA[04]
ADDR[05]
FA[03]
ADDR[04]
FA[02]
ADDR[03]
FA[01]
ADDR[01]
FA[00]
ADDR[00]
Note: Small sectors are interleaved (even and odd sectors). Even numbered sectors provide lower 4 byte and
odd numbered sectors provide upper 4 byte of a 64 bit FLASH line.
364
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
Address translation for large sectors of TCFlash is shown in Table 7-13.
Table 7-13: TCFlash large sectors address translation
Flash Address Bit
CPU Address Bit
FA[21]
ADDR[03]
FA[20]
1
FA[19]
ADDR[20]
FA[18]
ADDR[19]
FA[17]
ADDR[18]
FA[16]
ADDR[02]
FA[15]
ADDR[17]
FA[14]
ADDR[16]
FA[13]
ADDR[15]
FA[12]
ADDR[14]
FA[11]
ADDR[13]
FA[10]
ADDR[12]
FA[09]
ADDR[11]
FA[08]
ADDR[10]
FA[07]
ADDR[09]
FA[06]
ADDR[08]
FA[05]
ADDR[07]
FA[04]
ADDR[06]
FA[03]
ADDR[05]
FA[02]
ADDR[04]
FA[01]
ADDR[01]
FA[00]
ADDR[00]
Note:
•
Large sectors of TCFLASH are 4-times interleaved for best read performance (see also HW/Manual fig. 9.32 TCFLASH sector/address mapping - CPU mode).
•
Large sectors are interleaved (even and odd numbered sectors). Even numbered sectores provide lower 4
byte and odd numbered sectors provide upper 4 byte of a 64 bit FLASH line.
•
Address space is interleaved between TCFLASH0 and TCFLASH1. TCFLASH0 keeps lower 8 byte and TCFLASH1 keeps upper 8 byte of a 128 bit FLASH line (2 FLASHs are read in parallel).
January 30, 2015, MB9EF226_DS707-00004-2v1-E
365
Data
Shee t
The EEFlash macro can not be programed in FPP mode with respect to SHE security.
7.2.3
Flash Power On Sequence
Prior to entering flash parallel programming mode, the sequence mentioned below must be followed:
1. Apply following constant pin setting: MODE = 1 and MD[2:0] = 111. The pins for MD[2:0]
have pull-up, thus can be left open.
2. Assert RSTX = 0 and JTAG_nTRST = 0. The pin JTAG_nTRST has pull-down, so it will be
kept in reset by the device if it is left open. Asserting FRSTX = 0 and FRSTRX = 0 is optional.
This is done internally at device startup.
3. Ramp up the power supply (please refer to device specific datasheet for power supply
sequence) and wait till all power suppliess (VDP5, VDP3 & VDD) are stable
4.
Wait for at least 500ns after all power supplies are stable.
5. De-assert RSTX= 1, also deassert FRSTX = 1 and FRSTRX = 1 if those were asserted
before.
6. Wait until Flash Parallel Programming mode is entered by the bootROM program (boot
time). Wait time should be >=2.5 ms after RSTX release. Note that the wait time is necessary
because RDY pin is High-Z before FPP mode is entered. Looking at RDY (which has pull-up)
alone would cause mis-interpretation before that time is elapsed.
7. Flash access is possible after RDY pin goes to “1” . Clock supply is needed for monitoring
RDY.
RDY pin is pseudo open drain and thus needs a pull-up resistor. That makes it possible to program multiple
devices at once by using wired-AND of the RDY outputs, to detect when slowest device becomes ready.
Failure to follow the above sequence can result in indeterminate behavior. Once the above sequence is completed, flash parallel programming mode may be entered.
Flash parallel programming mode standard usage:
Entering FPP by releasing RSTX while keeping
•
MODE = ‘1’
•
MD[1] = ‘1’ , MD[0] = ‘1’
•
SMD[2] = ‘1’ , SMD[1] = ‘1’ , SMD[0] = ‘1’
Furthermore, Flash parallel programming mode may be entered using 2 options:
1.
Setting MCFG_DTAR:FPPREQ
2.
Setting MCFG_TSR:MD= ’XXX111’, and MCFG_TSR:SMD= ’11111’
Once flash parallel mode is requested, the bit SYSC_MCR:FPPEN is set, which enables entry to FPP mode.
However, it must be noted that FPP access must also be enabled in Security Description Record (SDR) (see
HWM).
The external programmer must also take care to program ECC bits for flash data contents. This also applies
to flash erase, where bit flipping (XOR with 0x73) is to be performed to handle ECC checking for erased flash.
Figure 7-2: Power On Sequence
366
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
VDP5
tRP
RSTX
VDD
XTAL0 / FCLK
tHCE
CEX
WEX,FA[n:0],ECCA
RD64,RD32,BYTEX
DIN[15:0],EDIN[6:0]
valid
tREGRDYR
tARYR
RDYR
RDY
tARY
tACY
tREGRDY
DQ[15:0],EDQ[6:0]
Recommendation: FRSTX = FRSTRX = ’1’
Table 7-14: Timing parameters related to Power ON Sequence
Value
Parameter
Symbol
Unit
Min
Max
Hardware Reset(FRSTX=0) period
tRP
440
-
ns
Hardware Reset(RSTX=0) period
tRP
500
-
ns
FRSTRX fall to RDYR fall access
tARYR
-
80
ns
FRSTX fall to RDY reset
tARY
-
80
ns
FRSTRX rise to RDYR rise access
tREGRDYR
-
80
ns
FRSTRX rise to RDY rise access
tREGRDY
-
80
ns
January 30, 2015, MB9EF226_DS707-00004-2v1-E
367
Data
7.3
Shee t
Debug and Trace
A standard 5-pin JTAG interface is supported for debug and trace. Conventional debug (core halted, and invasive) as well as trace debug (core not halted and non-invasive) are supported. The procedures for debug and
trace rely on ARM Coresight technology. The salient features for debug are:
•
Secure mode entry for debugger
•
Up to 8 breakpoints, or 8 watchpoints
Tracing support is provided on both packages as shown below:
•
QFP-176: 4-bit and 8-bit trace data shared with resources.
•
QFP-240: 4-bit, 8-bit and 16-bit trace data with dedicated trace pins
Trace port to pin mapping in QFP-176 and QFP-240 packages is shown in Table 7-15.
Table 7-15: Trace port to external pin mapping
External
Pin
Number
(QFP-176)
External
Pin
Number
(QFP-240)
External Pin
Name
Trace Port
-
95
TRACECTL
CTL
-
100
TRACECLK
CLK
-
20
TRACE[00]
TRACE[00]
-
25
TRACE[01]
TRACE[01]
-
37
TRACE[02]
TRACE[02]
-
46
TRACE[03]
TRACE[03]
-
63
TRACE[04]
TRACE[04]
-
68
TRACE[05]
TRACE[05]
-
76
TRACE[06]
TRACE[06]
-
85
TRACE[07]
TRACE[07]
-
90
TRACE[08]
TRACE[08]
-
105
TRACE[09]
TRACE[09]
-
109
TRACE[10]
TRACE[10]
-
113
TRACE[11]
TRACE[11]
-
118
TRACE[12]
TRACE[12]
-
123
TRACE[13]
TRACE[13]
-
126
TRACE[14]
TRACE[14]
-
129
TRACE[15]
TRACE[15]
Package QFP-176 has no dedicated trace pins. Please see the Port Pin Multiplexing table in Chapter 3.2.1 for
relevant pins and the corresponding settings for their activation.
In general, additional information regarding debug and trace methodology can be obtained from Coresight
TRM provided by ARM Limited. However, an additional characteristic is the support of security feature to prevent unauthorized access through the debug port. At the time of initiating the debugger access, it depends on
the security configuration of the device, whether it is necessary to transmit a security key. The security key can
368
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
only be transmitted once after reset. If a wrong key is entered, further accesses are disabled, and the only
method to regain access is through application of external reset.
In the device, trace support is provided for the following components/busses:
1.
Embedded Trace Macro (ETM) and Instrumentation Trace Macro (ITM) for processor core
2.
Independent AHB bus trace macro (HTM) for up to 8 busses. Refer Table 7-16 for details
Further, Cross Trigger Interface (CTI) macros are included to support cross triggering among all the above
macros.
Table 7-16: HTM trace sources
Bus
Width (bits)
Source ID
DMA master
64
1
PERI4 master
32
2
MEMORY_CONFIG slave
64
3
MCU_CONFIG slave
32
4
PERI5 slave
32
5
PERI3 slave
64
6
PERI4 slave
32
7
HSSPI slave
32
8
Power domain on/off status information can be obtained through debug port by accessing register on memory
mapped address 0xB0509400. This provides an easy method to obtain information on current state of power
domains, without the need to access device level internal registers. Refer Table 7-17 for details.
Table 7-17: Power domain status information for debugger
Bit Number
31:3
Function
Reserved
PD4 on/off status
2
‘0’ : Power domain is off
‘1’ : Power domain is on
PD3 on/off status
1
‘0’ : Power domain is off
‘1’ : Power domain is on
PD2 on/off status
0
‘0’ : Power domain is off
‘1’ : Power domain is on
In the QFP-240 pin package, trace data width settings are configurable on the non-shared pins through register
at memory mapped address 0xB0509404. This is highlighted in Table 7-18.
Table 7-18: Trace width setting on QFP-240 package
Bit Number
31:7
Function
Reserved
6
’1’ : Trace clock (CLK) is driven on pin
5
’1’ : Trace control (CTL) is driven on pin
January 30, 2015, MB9EF226_DS707-00004-2v1-E
369
Data
Shee t
Table 7-18: Trace width setting on QFP-240 package
Bit Number
370
Function
4
’0’ : reserved
3
’1’ : bits 15 to 8 of trace data are driven on pins
2
’1’ : bits 7 to 4 of trace data are driven on pins
1
’1’ : bits 3 to 2 of trace data are driven on pins
0
’1’ : bits 1 to 0 of trace data are driven on pins
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
8 Handling Devices
8.1
Preventing Latch-up
Latch-up may occur in a CMOS IC if a voltage higher than (VDD, VDP3 or VDP5) or less than (VSS) is applied to an
input or output pin or if a voltage exceeding the rating is applied between the power supply pins and ground
pins. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown
of the device. Therefore, be very careful not to apply voltages in excess of the absolute maximum ratings.
8.2
Handling of unused input pins
If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected
to pull-up or pull-down resistor (2K to 10K) or enable internal pullup or pulldown resistors (PUE/PDE) before
the input enable (PIE) is activated by software. The pins of circuit type MODE can be connected to VSS or VDP5
directly.
8.3
Power supply pins
In FCR4 series, devices including multiple power supply pins and ground pins are designed as follows: pins
necessary to be at the same potential are interconnected internally to prevent malfunctions such as latch-up.
All of the power supply pins and ground pins must be externally connected to the power supply and ground
respectively in order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground
level rising and to follow the total output current ratings. Furthermore, the power supply pins and ground pins
of the FCR4 series must be connected to the current supply source via a low impedance.
It is also recommended to connect a ceramic capacitor of approximately 0.1 F as a bypass capacitor between
power supply pin and ground pin near this device.
If DVCC is not set to the same voltage level as AVDD5, the ZPD functionality of SMC pins cannot be used.
8.4
Power on sequence
At any time, the difference between the power supply pins belonging to the same voltage level must not exceed
0.5V. This especially applies to the power on sequence. Otherwise, the risk of latchup will increase. Figure 81 shows the power on sequence and the groups of power supply that might be used, depending on the actual
application.
Furthermore, VDP5 supply must be switched on before any other power supply or at least at the same time. The
following conditions must be fulfilled at any moment:
1. The voltage of VDP5 must be higher or equal than the voltage on AVDD5 and AVRH5.
2. The voltage of VDP3 must be higher or equal than the voltage on VDD. In particular, VDP3 must not be
switched off for saving power.
2. The supply voltage for MODE and RSTX pins must reach the minimum operational value before switching
on core voltage suppy.
January 30, 2015, MB9EF226_DS707-00004-2v1-E
371
Data
Shee t
Figure 8-1: Power on sequence
V
5.5V
5V
AVRH5 = AVDD5 = DVCC = VDP5
0.5V
3.6V
3.3V
VDP3
3.0V
VDP5
0.5V
1.3V
1.2V
VDD
1.1V
0.5V
t
RSTX pin
Internal RSTX
undefined
MODE pin
internal MODE
8.5
undefined
Pin State while Power-On-Reset
The following table shows the state of output/bidirectional pins during Power-On-Reset. For subsequent reset
or power saving states, the pin state can be programmed according to the possibilities listed in HWM. Before
software execution is started, however, the user must pay attention to the listed behavior.
Table 8-1: Pin state during active Power-On-Reset
372
Pin type
Reset state
JTAGO
HIZ
BIDI50
HIZ
BIDI33
HIZ
SMC
HIZ
I2C
HIZ
RSDS
HIZ
TTL33
HIZ
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
8.6
Sh eet
Crystal oscillator circuit
Noise in proximity to the X0/X0A and X1/X1A pins can cause the device to operate abnormally. Printed circuit
boards should be designed so that the X0/X0A and X1/X1A pins, and crystal oscillator, as well as bypass capacitors connected to ground, are located near the device and ground.
It is recommended that the printed circuit board layout be designed such that the X0/X0A and X1/X1A pins are
surrounded by ground plane for the stable operation.
Please request the oscillator manufacturer to evaluate the related characteristics of the crystal and this device.
8.7
8.7.1
Notes on using external clock
Opposite phase clock supply: Oscillation Mode
When using the external clock, it is possible to simultaneously supply the X0/X0A and X1/X1A pins. In the described combination X0/X0A should be supplied with a clock signal which has the opposite phase to the X1/
X1A pins. However, in this case the stop mode (oscillation stop mode) must not be used (This is because the
X1/X1A pin stops at ”H” output in STOP mode).
With opposite phase supply at X0 and X1, a frequency up to 16 MHz is possible.
Figure 8-2: Example of using opposite phase supply
X0 (X0A)
X1 (X1A)
8.7.2
Single phase clock supply
For lower frequencies, up to 4 MHz, it is possible to supply a single phase clock at X0.
Figure 8-3: Example of using single phase supply
X0 (X0A)
X1 (X1A)
January 30, 2015, MB9EF226_DS707-00004-2v1-E
373
Data
8.7.3
Shee t
Single phase clock supply: Fast Clock Input Mode
When a high frequency clock needs to be fed, it is possible to directly supply a single phase clock at X0. For
this mode:
• SYSC_SPCCFGR:FCIMEN bit must be set to “1”.
• the input clock must have 50% duty cycle.
Figure 8-4: Example of using Fast Clock Input Mode
X0
X1
8.8
Unused sub clock signal
If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A
pin and the X1A pin must be left open.
374
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta
Sh eet
9 Ordering Information
Part number
Package
Remarks
MB9EF226PMC-GSE2
176-pin plastic LQFP
FPT-176-M07
Lead-free package
4 SMC variant
MB9EF226EPMC-GSE2
176-pin plastic LQFP
FPT-176-M07
Lead-free package
6 SMC variant
MB9EF226LPMC-GSE2
176-pin plastic LQFP
FPT-176-M07
Lead-free package
4 SMC variant
w/o graphic subsystem
MB9EF226PSC-ESE2
240-pin plastic QFP
FPT-240P-M06
Trace variant
Lead-free package
January 30, 2015, MB9EF226_DS707-00004-2v1-E
375
Data
376
Shee t
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Da ta

Sh eet
REVISION HISTORY
Version
Date
Remark
0.01
2012-07-27
Initial draft
0.02
2012-09-06
corrected pinout for 176pin and 240pin variant
0.03
2012-11-19
updated electrical characteristics, procedures, io map. added device handling, order information
0.04
2013-02-07
New IO Map tables included; Corrections to RICFG tables
1.0
2013-11-19
updated part numbers, removed preliminary
2.0
2013-12-20
added MB9EF226L part number for non graphics variant
2.1
2015-01-30
updated IO Map tables
corrected addresses 0xb0400aa8 0xb070005c-0xb0707ffe 0xb07fa46a0xb07ffffe 0xb0c02900-0xb0cffffc 0xfffef000-0xfffefff8
corrected default values of IRQ0_NMIPL0, IRQ0_IRQPL0,
IRQ0_IRQPL12, IRQ0_IRQPL13, EECFG_EMENR
January 30, 2015, MB9EF226_DS707-00004-2v1-E
377
Data
Shee t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed,
developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high
safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical
damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport
control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is
intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third
party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices
have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety
design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels
and other abnormal operating conditions. If any products described in this document represent goods or technologies subject
to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration
Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be
required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion
product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without
notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy,
completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other
warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of
the information in this document.
Copyright  2012-2015 Spansion. All rights reserved. Spansion, the Spansion logo, MirrorBit, MirrorBit EclipseTM,
ORNANDTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and
other countries. Other names used are for informational purposes only and may be trademarks of their respective owners.
378
MB9EF226_DS707-00004-2v1-E, January 30, 2015
Similar pages