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The following document contains information on Cypress products.
FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
CM71-10136-2E
FR60Lite
32-BIT MICROCONTROLLER
MB91245/S Series
HARDWARE MANUAL
FR60Lite
32-BIT MICROCONTROLLER
MB91245/S Series
HARDWARE MANUAL
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system
development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU MICROELECTRONICS LIMITED
PREFACE
■ Purpose of This Document and Intended Reader
We sincerely thank you for your continued use of Fujitsu microelectronics products.
The FR family is a line of single-chip microcontrollers based on a 32-bit high-performance
RISC CPU and integrating a variety of I/O resources for embedded control applications
which require high - performance, high-speed CPU processing.
The MB91245/S series is designed to be best suited for embedded applications which require
high-performance processing power of the CPU, such as DVD players, printers, TV sets, and
the PDP control.
The MB91245/S series is a line of CPUs in the FR60Lite implemented by FR family.
This manual describes the functions and operations of the MB91245/S series for engineers
who develop products using the MB91245/S series. Please read through this manual.
Note: FR, the abbreviation of FUJITSU RISC controller, is a line of products of Fujitsu
Microelectronics Limited.
■ Trademark
The company names and brand names herein are the trademarks or registered trademarks of
their respective owners.
■ Organization of This Manual
This manual consists of the following 29 chapters and appendix.
CHAPTER 1 OVERVIEW
This chapter provides basic information for understanding the MB91245/S series as a
whole, covering its features, block diagram, and functions.
CHAPTER 2 HANDLING DEVICES
This chapter provides precautions on using the MB91245/S series.
CHAPTER 3 CPU AND CONTROL BLOCK
This chapter provides the basic information required to understand FR60Lite's functions,
such as its architecture, specifications and instructions.
CHAPTER 4 I/O PORT
This chapter outlines the I/O ports and describes the configuration and functions of their
registers.
CHAPTER 5 INTERRUPT CONTROLLER
This chapter outlines the interrupt controller, describes its register configuration/functions
and its operations.
i
CHAPTER 6 EXTERNAL INTERRUPT CONTROLLER
This chapter outlines the external interrupt controller and describes its register
configuration/functions and its operation.
CHAPTER 7 REALOS-RELATED HARDWARE
A REALOS-related hardware is used by a Realtime OS, therefore, when using with
REALOS, it cannot be used by user programs. This chapter outlines the delay interrupt
module and the bit search module and also describes their register configurations, functions
and operations.
CHAPTER 8 16-BIT RELOAD TIMER
This chapter describes the 16-bit reload timer, the configuration and functions of registers,
and 16-bit reload timer operation.
CHAPTER 9 PPG
This chapter describes the overview of the PPG (Programmable Pulse Generator), the
configuration and functions of registers, and the operation of the PPG.
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
This chapter explains the overview of the pulse width counter (PWC), the register
configuration and functions and the counter operation.
CHAPTER 11 MAIN OSCILLATION STABILIZATION WAIT TIMER
This chapter gives an overview of the main oscillation stabilization wait timer and
describes its register configuration, functions, and operations.
CHAPTER 12 16-BIT FREE-RUN TIMER
This chapter explains the overview of the 16-bit free-run timer, the register configuration
and functions, and the timer operation.
CHAPTER 13 INPUT CAPTURE
This chapter describes the overview of the input capture, the configuration and functions of
registers, and the operation of the input capture.
CHAPTER 14 OUTPUT COMPARE
This chapter describes the overview of the output compare, the configuration and functions
of registers, and the operation of the output compare.
CHAPTER 15 U-TIMER
This chapter describes the U-TIMER, the configuration and functions of registers, and
U-TIMER operation.
CHAPTER 16 EXTERNAL BUS INTERFACE
The external bus interface controls the internal bus and external memory as well as I/O
device interface.
ii
CHAPTER 17 DMAC (DMA CONTROLLER)
This chapter explains the overview of the DMAC, the configuration and functions of
registers, and DMAC operation.
CHAPTER 18 STEPPER MOTOR CONTROLLER
This chapter outlines the stepper motor controller and describes its register configuration,
functions and operations.
CHAPTER 19 SOUND GENERATOR
This chapter outlines the sound generator and describes its register configuration, functions
and operations.
CHAPTER 20 REAL TIME CLOCK
This chapter outlines the real time clock and describes its register configuration, functions
and operations
CHAPTER 21 UART
This chapter describes the overview of the UART, the configuration and functions of
registers, and UART operation.
CHAPTER 22 LIN-UART
This chapter describes the overview of the LIN-UART, the configuration and functions of
registers, and LIN-UART operation.
CHAPTER 23 A/D CONVERTER
This chapter describes the overview of the A/D converter, the configuration and functions
of registers, and A/D converter operation.
CHAPTER 24 C_CAN
This chapter describes functions and operations of the C_CAN.
CHAPTER 25 LCD CONTROLLER (LCDC)
This chapter outlines the LCD controller/driver (LCDC) and describes its register
configuration, functions and operations.
CHAPTER 26 32 kHz CLOCK CORRECTION UNIT
This chapter outlines the 32 kHz clock correction unit and describes its register
configuration and functions.
CHAPTER 27 CPU OPERATION DETECTION RESET CIRCUIT
This chapter describes the functions and operation of the CPU operation detection reset
circuit.
CHAPTER 28 FLASH MEMORY
This chapter gives an overview of flash memory and describes its register configuration/
functions and operations.
iii
CHAPTER 29 EXAMPLE OF SERIAL WRITING CONNECTION
This chapter describes the basic serial writing structure, pins used for serial on-board
writing, example connection for serial writing, and the system configuration of the Flash
microcontroller programmer.
APPENDIX
This appendix includes I/O maps, vector tables, status of each pin, notes when little endian
area is used, instruction lists, and precautions on handling.
•
•
•
•
•
•
•
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU
MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of
such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any thirdparty's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no
liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright© 2007-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
iv
CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
CHAPTER 2
2.1
OVERVIEW ................................................................................................... 1
Features of MB91245/S Series ........................................................................................................... 2
Components of Each Product ............................................................................................................. 4
Block Diagram .................................................................................................................................... 5
Package Dimension ............................................................................................................................ 6
Pin Assignment ................................................................................................................................... 7
Pin Descriptions .................................................................................................................................. 8
Input-Output Circuit Types ................................................................................................................ 16
HANDLING DEVICES ................................................................................ 19
Handling Devices .............................................................................................................................. 20
CHAPTER 3
CPU AND CONTROL BLOCK ................................................................... 23
3.1
Memory Space ..................................................................................................................................
3.2
Memory Map .....................................................................................................................................
3.3
Internal Architecture ..........................................................................................................................
3.4
Programming Model .........................................................................................................................
3.4.1
Register .......................................................................................................................................
3.5
Data Structure ...................................................................................................................................
3.6
Word Alignment ................................................................................................................................
3.7
Memory Map .....................................................................................................................................
3.8
Branch Instruction .............................................................................................................................
3.9
EIT (Exception, Interrupt, and Trap) .................................................................................................
3.9.1
Interrupt Level ..............................................................................................................................
3.9.2
ICR (Interrupt Control Register) ...................................................................................................
3.9.3
SSP (System Stack Pointer) ........................................................................................................
3.9.4
TBR (Table Base Register) .........................................................................................................
3.9.5
Multiple EIT Processing ...............................................................................................................
3.9.6
Operation of EIT ..........................................................................................................................
3.10 Operation Mode ................................................................................................................................
3.11 Reset (Device Initialization) ..............................................................................................................
3.11.1 Reset Factor and Oscillation Stabilization Wait Time ..................................................................
3.11.2 Reset Level ..................................................................................................................................
3.11.3 External Reset Pin .......................................................................................................................
3.11.4 Reset Operation ..........................................................................................................................
3.11.5 Reset Factor Bit ...........................................................................................................................
3.11.6 Oscillation Stabilization Waiting Factor .......................................................................................
3.12 Clock Generation Control .................................................................................................................
3.12.1 Selecting a Source Clock ............................................................................................................
3.12.2 PLL Control ..................................................................................................................................
3.12.3 Oscillation Stabilization Wait/PLL Lock Wait Time ......................................................................
3.12.4 Clock Distribution .........................................................................................................................
3.12.5 Clock Division ..............................................................................................................................
v
24
25
28
33
34
41
42
43
44
47
48
50
51
52
56
58
62
65
67
69
71
72
74
77
78
79
80
82
84
85
3.12.6 Block Diagram of Clock Generation Control Unit ........................................................................ 86
3.12.7 Detailed Description of Register of Clock Generation Control Unit ............................................. 87
3.12.8 Peripheral Circuit of Clock Control Unit ..................................................................................... 103
3.13 Device Status Control ..................................................................................................................... 106
CHAPTER 4
4.1
4.2
4.3
I/O PORT .................................................................................................. 113
Overview of the I/O Port ................................................................................................................. 114
Registers of I/O port ........................................................................................................................ 117
I/O Expansion Functions ................................................................................................................. 128
CHAPTER 5
INTERRUPT CONTROLLER ................................................................... 131
5.1
Overview of Interrupt Controller ......................................................................................................
5.2
Register List of Interrupt Controller .................................................................................................
5.2.1
Interrupt Control Register (ICR) ................................................................................................
5.3
Operation of Interrupt Controller .....................................................................................................
CHAPTER 6
EXTERNAL INTERRUPT CONTROLLER ............................................... 147
6.1
Overview of External Interrupt Controller ........................................................................................
6.2
Registers of External Interrupt Controller .......................................................................................
6.2.1
Interrupt Enabled Register (ENIR: ENable Interrupt Request Register) ....................................
6.2.2
External Interrupt Source Register (EIRR: External Interrupt Request Register) ......................
6.2.3
External Interrupt Request Level Setting Register (ELVR: External LeVel Register) ................
6.3
External Interrupt Control Operation ...............................................................................................
CHAPTER 7
7.1
7.2
REALOS-RELATED HARDWARE .......................................................... 157
16-BIT RELOAD TIMER ........................................................................... 167
Overview of 16-bit Reload Timer ....................................................................................................
Block Diagram ................................................................................................................................
Registers of 16-bit Reload Timer ....................................................................................................
Operation of Reload Timer .............................................................................................................
CHAPTER 9
9.1
9.2
9.3
9.4
148
149
150
151
152
153
Delay Interrupt Module ................................................................................................................... 158
Bit Search Module .......................................................................................................................... 160
CHAPTER 8
8.1
8.2
8.3
8.4
132
133
136
138
168
169
170
174
PPG .......................................................................................................... 179
Overview of PPG ............................................................................................................................
PPG Block Diagram ........................................................................................................................
PPG Register ..................................................................................................................................
Operation of PPG ...........................................................................................................................
180
183
186
190
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) ....................... 195
10.1
10.2
10.3
Overview of PWC ........................................................................................................................... 196
PWC Registers ............................................................................................................................... 198
Operation Description of PWC ........................................................................................................ 204
vi
CHAPTER 11 MAIN OSCILLATION STABILIZATION WAIT TIMER ............................. 217
11.1
11.2
11.3
11.4
Overview of Main Oscillation Stabilization Wait Timer ....................................................................
Block Diagram of Main Oscillation Stabilization Wait Timer ...........................................................
Register of Main Oscillation Stabilization Wait Timer .....................................................................
Operations of Main Oscillation Stabilization Wait Interrupt .............................................................
218
219
220
222
CHAPTER 12 16-BIT FREE-RUN TIMER ....................................................................... 225
12.1
12.2
12.3
Overview of 16-bit Free-run Timer .................................................................................................. 226
Register of 16-bit Free-run Timer ................................................................................................... 228
Description of 16-bit Free-run Timer Operation .............................................................................. 232
CHAPTER 13 INPUT CAPTURE ..................................................................................... 235
13.1
13.2
13.3
Overview of Input Capture .............................................................................................................. 236
Registers of Input Capture .............................................................................................................. 239
Operation of Input Capture ............................................................................................................. 241
CHAPTER 14 OUTPUT COMPARE ................................................................................ 243
14.1
14.2
14.3
Overview of Output Compare ......................................................................................................... 244
Register of Output Compare ........................................................................................................... 246
Operation of Output Compare ........................................................................................................ 249
CHAPTER 15 U-TIMER ................................................................................................... 253
15.1
15.2
15.3
Overview of U-Timer ....................................................................................................................... 254
Register of U-Timer ........................................................................................................................ 256
Operation of U-Timer ...................................................................................................................... 259
CHAPTER 16 EXTERNAL BUS INTERFACE ................................................................ 261
16.1
16.2
16.3
16.4
16.5
16.6
Overview of External Bus Interface ................................................................................................
Register of External Bus Interface ..................................................................................................
Endian and Bus Access of External Bus Interface .........................................................................
Normal Bus Interface of External Bus Interface ..............................................................................
Register Setting Procedure of External Bus Interface ....................................................................
Notes on Using External Bus Interface ...........................................................................................
262
265
276
284
291
292
CHAPTER 17 DMAC (DMA CONTROLLER) .................................................................. 293
17.1 Overview of DMAC .........................................................................................................................
17.2 Detailed Explanation of the Register of DMAC ...............................................................................
17.3 Description of DMAC Operation .....................................................................................................
17.3.1 Operation of DMAC ...................................................................................................................
17.3.2 Configuration for Transfer Request ...........................................................................................
17.3.3 Transfer Sequence ....................................................................................................................
17.3.4 DMA Transfer in General ...........................................................................................................
17.3.5 Addressing Mode .......................................................................................................................
17.3.6 Type of Data ..............................................................................................................................
17.3.7 Transfer Count Control ..............................................................................................................
17.3.8 CPU Control ..............................................................................................................................
vii
294
297
312
313
315
316
318
320
321
322
323
17.3.9 Start Operation ..........................................................................................................................
17.3.10 Accept and Transfer the Transfer Request ...............................................................................
17.3.11 Peripheral Interrupt Clearing by DMA ........................................................................................
17.3.12 Pause ........................................................................................................................................
17.3.13 Operation Complete/Stop ..........................................................................................................
17.3.14 Stop Caused by Error ................................................................................................................
17.3.15 DMAC Interrupt Control .............................................................................................................
17.3.16 DMA Transfer During Sleep ......................................................................................................
17.3.17 Channel Selection and Control ..................................................................................................
17.4 Operation Flow of DMAC ................................................................................................................
17.5 Data Path of DMAC ........................................................................................................................
324
325
326
327
328
329
330
331
332
334
336
CHAPTER 18 STEPPER MOTOR CONTROLLER ......................................................... 339
18.1 Overview of the Stepper Motor Controller ......................................................................................
18.2 Stepper Motor Controller Register ..................................................................................................
18.2.1 PWM Control Register ...............................................................................................................
18.2.2 PWM1 and PWM2 Compare Registers .....................................................................................
18.2.3 PWM1 and PWM2 Selection Register .......................................................................................
18.3 Precautions when Using Stepper Motor Controller .........................................................................
340
341
342
343
345
347
CHAPTER 19 SOUND GENERATOR ............................................................................. 349
19.1 Overview of Sound Generator ........................................................................................................
19.2 Sound Generator Registers ............................................................................................................
19.2.1 Sound Control Register .............................................................................................................
19.2.2 Amplitude Data Register ............................................................................................................
19.2.3 Frequency Data Register ...........................................................................................................
19.2.4 Tone Count Register .................................................................................................................
19.2.5 Decrement Grade Register ........................................................................................................
19.2.6 Sound Disable Register .............................................................................................................
350
351
352
354
355
356
357
358
CHAPTER 20 REAL TIME CLOCK ................................................................................. 359
20.1
20.2
20.3
Overview of Real Time Clock ......................................................................................................... 360
Register of Real Time Clock ........................................................................................................... 361
Real Time Clock Operation ............................................................................................................. 366
CHAPTER 21 UART ........................................................................................................ 367
21.1 Overview of UART ..........................................................................................................................
21.2 Register of UART ............................................................................................................................
21.3 Operation of UART .........................................................................................................................
21.3.1 Asynchronous (Start-stop Synchronization) Mode ....................................................................
21.3.2 Clock Synchronous Mode ..........................................................................................................
21.3.3 Interrupt Generation and Flag Set Timings ...............................................................................
21.4 Application Example of UART ........................................................................................................
368
369
376
377
378
380
383
CHAPTER 22 LIN-UART ................................................................................................. 385
22.1
22.2
Overview of LIN-UART ................................................................................................................... 386
Register List of LIN-UART .............................................................................................................. 388
viii
22.2.1 Baud Rate / Reload Counter Register (BGR) ............................................................................
22.3 Detecting Baud Rates with the Input Capture .................................................................................
22.3.1 Baud Rate for UART ..................................................................................................................
22.3.2 Setting Baud Rate .....................................................................................................................
22.4 Operation of LIN-UART ..................................................................................................................
22.4.1 Operations in Asynchronous Mode (Operation Modes 0 and 1) ...............................................
22.4.2 Operations in Synchronous (Mode 2) Mode ..............................................................................
22.4.3 Operations with LIN Functions (Mode 3) ...................................................................................
22.4.4 Direct Access to the Serial Pin ..................................................................................................
22.4.5 Data Format Setting ..................................................................................................................
22.4.6 Overview of the Register/Flag Bits ............................................................................................
22.5 UART Interrupts ..............................................................................................................................
22.5.1 Software Reset ..........................................................................................................................
22.6 Clock Synchronization of LIN-UART ...............................................................................................
22.7 Flag Set Timing ...............................................................................................................................
22.8 Special Specifications of LIN-UART ...............................................................................................
22.9 LIN Communication Operation .......................................................................................................
22.10 Overview of Changes from Normal UART ......................................................................................
22.11 Restrictions .....................................................................................................................................
395
396
397
398
401
402
404
406
408
409
410
411
414
415
416
420
422
426
427
CHAPTER 23 A/D CONVERTER .................................................................................... 429
23.1
23.2
23.3
Overview of the A/D Converter ....................................................................................................... 430
A/D Converter Register List ............................................................................................................ 433
A/D Converter Operations .............................................................................................................. 444
CHAPTER 24 C_CAN ...................................................................................................... 447
24.1 Features of the C_CAN ..................................................................................................................
24.2 C_CAN Register Function ..............................................................................................................
24.2.1 Total Control Register ................................................................................................................
24.2.2 Message Interface Register .......................................................................................................
24.2.3 Message Handler Register ........................................................................................................
24.2.4 CAN Prescaler Register (CANPRE) ..........................................................................................
24.3 C_CAN Function .............................................................................................................................
448
450
458
470
490
498
499
CHAPTER 25 LCD CONTROLLER (LCDC) ................................................................... 517
25.1
25.2
25.3
Overview of LCD Controller ............................................................................................................ 518
LCD Controller Registers ................................................................................................................ 520
Operation of LCD Controller ........................................................................................................... 527
CHAPTER 26 32 kHz CLOCK CORRECTION UNIT ...................................................... 535
26.1
26.2
26.3
Overview of 32 kHz Clock Correction Unit ...................................................................................... 536
Register of 32 kHz Clock Correction Unit ....................................................................................... 538
Application Notes ............................................................................................................................ 543
CHAPTER 27 CPU OPERATION DETECTION RESET CIRCUIT .................................. 545
27.1
27.2
Overview of CPU Operation Detection Reset Circuit ...................................................................... 546
Registers in the CPU Operation Detection Reset Circuit ................................................................ 548
ix
27.3
27.4
CPU Operation Detection Reset Circuit Operation ......................................................................... 550
Notes on Using the CPU Operation Detection Reset Circuit .......................................................... 551
CHAPTER 28 FLASH MEMORY ..................................................................................... 553
28.1 Overview of FLASH Memory ..........................................................................................................
28.2 FLASH Memory Register ................................................................................................................
28.3 FLASH Memory Access Modes ......................................................................................................
28.4 Auto Algorithm Activation Method ...................................................................................................
28.5 Execution Status of Auto Algorithm ................................................................................................
28.6 Details on Writing/Erasing FLASH Memory ....................................................................................
28.6.1 Notes on Using the FLASH Memory .........................................................................................
28.7 Sector Protecting Operations ..........................................................................................................
554
564
568
571
575
581
587
588
CHAPTER 29 EXAMPLE OF SERIAL WRITING CONNECTION ................................... 593
29.1
29.2
Example of Serial Writing Connection in the MB91F24x/S ............................................................. 594
Example of MB91F24x/S Serial Writing (Asynchronous) Connection ............................................ 605
APPENDIX ......................................................................................................................... 609
APPENDIX A
APPENDIX B
APPENDIX C
APPENDIX D
APPENDIX E
APPENDIX F
I/O Map ................................................................................................................................
Vector Table .........................................................................................................................
Status of Each Pin due to Reset ..........................................................................................
Notes when Little Endian Area is Used ................................................................................
Instruction Lists ....................................................................................................................
Notes on Handling ...............................................................................................................
610
624
627
633
640
655
INDEX................................................................................................................................... 659
x
Main changes in this edition
Page
Changes (For details, refer to main body.)
-
-
Added the product B91F249/S.
-
-
Changed the term.
(MOD0 to MOD2 → MD0 to MD2)
-
-
Changed the term.
(single clock products → products with S suffix)
2
1.1 Features of MB91245/S Series
Changed "■ Internal Peripheral Functions".
4
1.2 Components of Each Product
Changed Table 1.2-1.
5
1.3 Block Diagram
Changed Figure 1.3-1.
17
1.7 Input-Output Circuit Types
Changed "Remarks" for "Category E" in Table 1.7-1 of "■ InputOutput Circuit Types".
(ADER bit → ADE bit)
21
2.1 Handling Devices
Changed Figure 2.1-1.
Changed "• About Crystal Oscillation Circuit".
(Added the sentence "Please ask the crystal maker to evaluate the
oscillational characteristics of the crystal and this device.".)
25 to 27
68
3.2 Memory Map
Changed Figure 3.2-1.
3.11.1 Reset Factor and Oscillation
Stabilization Wait Time
Changed "■ Concerning the Oscillation Stabilization Wait Time
at the Time of Power-on".
Deleted "■ Concerning Recovery by External Interrupt during Stop
Mode".
81
3.12.2 PLL Control
Changed "● PLL Multiplier".
86
3.12.6 Block Diagram of Clock
Generation Control Unit
Changed Figure 3.12-1.
128
4.3 I/O Expansion Functions
Changed "■ Port Input Level Select Register (PILR)".
(PILRxy → PILRx)
169
8.2 Block Diagram
Changed Figure 8.2-1.
(TOE0 to TOE2 Bits in PFRK → Bits in PFR)
172
8.3 Registers of 16-bit Reload Timer
Changed "[bit4] RELD" in "■ Control Status Register (TMCSR)"
( "(TOEx)" → "(PFR/EPFR)"
"TOEx represents TOE0 to TOE2 in the port function register (PFR)."→
"The PFR/EPFR indicates the value of the corresponding bit in
the PFR/EPFR register.")
214
10.3 Operation Description of PWC
Changed "● Notes concerning register rewrite".
(Deleted "[bit5, bit4] PIS1, PIS0: Input signal selection bits".)
xiii
Page
Changes (For details, refer to main body.)
222
11.4 Operations of Main Oscillation
Stabilization Wait Interrupt
Changed "■ Main Oscillation Stabilization Wait Operations".
("(WPCR: WCL=1)" → "(OSCR: WCL=1)")
223
11.4 Operations of Main Oscillation
Stabilization Wait Interrupt
Changed "■ Clock Supply Function Operations".
(WT1, WT0 → WS1, WS0
OSCCR bit0: OCSDS1=1 write → OSCCR bit0: OCSDS1=0 write)
231
12.2 Register of 16-bit Free-run
Timer
Changed "[bit1, bit0] CLK1, CLK0".
( φ → fccp
F → fccp
Count clock (φ) → Count clock
φ : Resource clock → fccp : Peripheral clock frequency )
237
13.1 Overview of Input Capture
Changed Figure 13.1-1.
(Added the figure to ICS23.)
240
13.2 Registers of Input Capture
Changed Figure 13.2-2.
( Added the figure for ICS23.
[bit7, bit6] ICP1, ICP0 → [bit7, bit6] ICP3, ICP2 (ICP1, ICP0)
[bit5, bit4] ICE1, ICE0 → [bit5, bit4] ICE3, ICE2 (ICE1, ICE0)
[bit3 to bit0] EG11, EG10, EG01, EG00 →
[bit3 to bit0] EG31, EG30, EG21, EG20 (EG11, EG10, EG01,
EG00) )
251
14.3 Operation of Output Compare
Changed "< Compare match, Interrupt timing >".
255
15.1 Overview of U-Timer
Changed Figure 15.1-2 in "■ Block Diagram of U-Timer".
(UTIMER (reload register) → UTIMR (reload register))
265
16.2 Register of External Bus
Interface
Changed "[bit7 to bit0] A23 to A16" in "■ ASR0 to ASR3 (Area
Select Register)".
(Reserved → A23 to A16)
269
Changed "[bit3 to bit0] TYP3, TYP2, TYP1, TYP0 = TYPe select".
(TYPE[3:0] → TYP[3:0])
341
18.2 Stepper Motor Controller
Register
Changed Figure 18.2-1.
("bit 7 6 5 4 3 2 1 0" → "bit 15 14 13 12 11 10 9 8")
360
20.1 Overview of Real Time Clock
Changed Figure 20.1-1.
389
22.2 Register List of LIN-UART
Changed "*1" in Figure 22.2-1.
426
22.10 Overview of Changes from
Normal UART
Changed "■ Overview of Changes from Normal UART".
((SIN, SOUT) → (SIN, SOT))
435
23.2 A/D Converter Register List
Changed "■ Analog Input Enable Registers".
(ADER bit → ADE bit)
441
Changed "■ A/D Conversion Time Setting Register (ADCT0, ADCT1)".
( Added "• It is prohibited to set the following values to ST9 to ST0;
"0000000010"(02H), "0000000001" (01H), "0000000000"(00H).
Always set the value to 3 or more.")
xiv
Page
Changes (For details, refer to main body.)
451
24.2 C_CAN Register Function
Changed Table 24.2-1.
(Int-Id → IntId)
477
24.2.2 Message Interface Register
Changed "[bit2] TxRqst/NewDat: Data update bit" in "■ IFx
Command Mask Register (IFxCMSK)".
495
24.2.3 Message Handler Register
Changed "IntPnd32 to IntPnd1: Interrupt pending bits" in "■ CAN
Interrupt Pending Register (INTPND1, INTPND2)".
499
24.3 C_CAN Function
Changed "■ Message Object".
521
25.2 LCD Controller Registers
Changed "[bit11 to bit8] COM3 to COM0: Common pin enable bits".
537
26.1 Overview of 32 kHz Clock
Correction Unit
Changed Figure 26.1-2.
(RUNS (4 kHz) → RUNS (4 MHz))
554
28.1 Overview of FLASH Memory
Changed the summary of "28.1 Overview of FLASH Memory".
Changed "■ Overview of FLASH Memory".
555
Changed "■ Writing from a ROM Writer".
(FLASH memory product MBM29LV400C →
FLASH memory product MBM29LV200TC/MBM29LV400TC)
Changed Figure 28.1-1.
(Added "(MB91F248/S)".)
556
Changed Figure 28.1-2.
(Added "(MB91F248/S)".)
557
Changed Table 28.1-1.
(Added "(MB91F248/S)")
558
Added Figure 28.1-3.
Added Figure 28.1-4.
559
Added Table 28.1-2.
560
Changed Figure 28.1-5.
(Added "(MB91F248/S)")
561
Changed Table 28.1-3
(Added "(MB91F248/S)")
562
Added Figure 28.1-6.
563
Added Table 28.1-4.
567
28.2 FLASH Memory Register
Changed "[bit2 to bit0] WTC2 to WTC0: Wait cycle control bits"
in "■ FLASH Wait Register (FLWC)".
( Read → Flash Read
Write → Flash Write )
xv
Page
569
Changes (For details, refer to main body.)
28.3 FLASH Memory Access
Modes
570
Changed "■ FLASH Memory Mode".
(2 Mbit FLASH memory → 2 Mbit/4 Mbit FLASH memory)
Changed "■ Relationship between the MBM29LV400C and
the FLASH Memory Control Signals".
587
28.6.1 Notes on Using the FLASH
Memory
Changed the summary of "28.6.1 Notes on Using the FLASH
Memory".
(MB91F248 → MB91F248/MB91F249)
589
28.7 Sector Protecting Operations
Changed "■ Enable Sector Protection".
CHAPTER 29 EXAMPLE OF
SERIAL WRITING CONNECTION
Changed CHAPTER 29
(MB91F248/S → MB91F24x/S)
29.2 Example of MB91F24x/S
Serial Writing (Asynchronous)
Connection
Changed "■ Timing Chart of Each Pin".
APPENDIX A I/O Map
Changed Table A-1.
APPENDIX C Status of Each Pin
due to Reset
Changed "■ Status of Pin During Reset".
(● When setting internal vector mode
"(M2, M1, M0=000B)" → "(MD2, MD1, MD0=000B)"
593 to 608
608
611 to 623
627
● When setting external vector mode
"(M2, M1, M0=001B)" → "(MD2, MD1, MD0=001B)" )
629
APPENDIX C Status of Each Pin
due to Reset
Changed Table C-1.
( P60 to P77/AN0 to AN7 → P60 to P67/AN0 to AN7
PG0/(WOT)/PPG0 → PG0/PPG0)
632
Changed Table C-2
(PG0/(WOT)/PPG0 → PG0/PPG0)
The vertical lines marked in the left side of the page show the changes.
xvi
CHAPTER 1
OVERVIEW
This chapter provides basic information for
understanding the MB91245/S series as a whole,
covering its features, block diagram, and functions.
1.1
Features of MB91245/S Series
1.2
Components of Each Product
1.3
Block Diagram
1.4
Package Dimension
1.5
Pin Assignment
1.6
Pin Descriptions
1.7
Input-Output Circuit Types
1
CHAPTER 1 OVERVIEW
1.1
Features of MB91245/S Series
The MB91245/S series is a general-purpose 32-bit RISC microcontroller from Fujitsu
designed for embedded control application requiring high-speed real-time processing
as on domestic equipment/appliances. The CPU used is the FR60Lite, which is
compatible with the FR family.
This microcontroller includes an LCD controller and a stepper motor controller.
■ FR60Lite CPU
• 32-bit RISC, load/store architecture, 5-stage pipeline
• Maximum operating frequency: 32 MHz (original oscillation frequency of 4 MHz is multiplied by 8
(PLL clock multiplication))
• 16-bit fixed length instructions (basic instructions)
• Instruction execution speed: 1 instruction per cycle
Instructions suitable for embedded control such as memory-to-memory transfer, bit processing, barrel
shift, and other instructions
• Function entry/exit instructions, multiple-register load/store instructions, instructions available for C
language
• Register interlock function: Designed for easy assembly language coding
• Built-in multiplier / instruction level support
- Signed 32-bit multiplication: 5 cycles
- Signed 16-bit multiplication: 3 cycles
• Interrupts (PC and PS saving): 6 cycles (16 priority levels)
• Harvard architecture for simultaneous program access and data access
• Instruction compatibility with the FR family
■ Internal Peripheral Functions
• Internal ROM size and type
Mask ROM: 256 Kbytes (MB91248/S) or 128 Kbytes (MB91247/S)
Flash memory: 512 Kbytes (MB91F249/S) or 256 Kbytes (MB91F248/S)
• Internal RAM size: 24 Kbytes (MB91F249/S), 16 Kbytes (MB91248/S, MB91F248/S),
8 Kbytes (MB91247/S) or 32 Kbytes (MB91V245A)
• General-purpose ports: Maximum 120 ports (4 out of the 120 ports are for input only)
• A/D converter (successive approximation type)
10-bit resolution: 32 or 24 channels
Conversion time: 3 μs (at 16 MHz/32 MHz)
To achieve the above conversion time, set the PLL multiplier and peripheral clock division ratio as
follows.
32 MHz: The original oscillation frequency of 4 MHz is multiplied by 8 and divided by 1
16 MHz: The original oscillation frequency is multiplied by 8 and divided by 2
• External interrupt input: 8 channels
• Bit search module (REALOS used)
Function for searching for the first 1-to-0 change bit position from MSB (upper bit) in each word.
2
CHAPTER 1 OVERVIEW
• UART (full-duplex double buffer): 1 channel
With or without parity selectable
Asynchronous (asynchronous communication) or clock synchronized communication selectable
Each channel includes a dedicated baud rate timer (U-Timer).
An external clock can be used as the transfer clock.
Functions used to detect parity, frame, and overrun errors.
• LIN-UART (full-duplex double buffer): 3 channels
Clock-synchronized or asynchronous communication selectable
Synch-break detection
Dedicated baud rate generator included
• Stepper motor controller: 6 channels
Four 8-bit PWM high-current output channels
• 8 or 16-bit PPG timer: 8 or 4 channels
• 16-bit reload timer: 3 channels
• 16-bit free-run timer: 2 channels (linked with ICU/OCU)
• 16-bit pulse width counter: 1 channel
• Input capture: 4 channels (linked with free-run timer channels 0 and 1)
Ch.0 is linked with PWC.
• Output compare: 2 channels (linked with free-run timer channel 0)
• LCD controller: SEG0 to SEG31, COM0 to COM3 (used also as ports)
• 16-bit time-base and watchdog timer
• Sound generator
• Real-time clock
• 32-kHz sub clock (sub clock is not supported by products with S suffix.)
• C-CAN: 2 channels
• Low-power consumption modes: sleep, stop, and watch modes
• Package: LQFP-144 (FPT-144P-M08)
• CMOS 0.35 μm technology
• Power supply: 5 V (used for I/O 5.0 V and lowered to 3.3 V for internal circuit by a step-down circuit)
3
CHAPTER 1 OVERVIEW
1.2
Components of Each Product
Table 1.2-1 shows the features of each product of the MB91245/S series. The built-in
peripheral function not described in the table is a common function.
■ Components of Each Product
Table 1.2-1 shows the features of each product of the MB91245/S series.
Table 1.2-1 Features of Each Product of MB91245/S Series
4
MB91V245A
MB91F249/S
MB91F248/S
MB91248/S
MB91247/S
ROM/Flash capacity
External SRAM
Flash memory
512 Kbytes
256 Kbytes
←
128 Kbytes
RAM capacity
32 Kbytes
24 Kbytes
16 Kbytes
←
8 Kbytes
External interrupts
8 channels
←
←
←
←
DMA
5 channels
←
←
←
←
A/D converter
32 channels
←
←
←
←
UART
1 channel
←
←
←
←
LIN-UART
3 channels
←
←
←
←
Stepper motor controller
6 channels
←
←
←
←
8-bit or 16-bit PPG timer
8 or 4 channels
←
←
←
←
16-bit reload timer
3 channels
←
←
←
←
16-bit free-run timer
2 channels
←
←
←
←
16-bit pulse width counter
1 channel
←
←
←
←
Input capture unit
4 channels
←
←
←
←
Output compare unit
2 channels
←
←
←
←
LCD controller
4 COMs and
32 SEGs
←
←
←
←
Sound generator
1 channel
←
←
←
←
Real-time clock
Yes
←
←
←
←
32 kHz sub clock
Yes
External bus
Address 16 bits,
data 16 bits
←
←
←
←
Others
Evaluation
product
Flash memory
product
←
Mask ROM
product
←
On-chip debug support unit
DSU4
No
No
No
No
C-CAN unit
2 channels
32-message
buffer
←
←
←
←
Yes:MB91F249 Yes:MB91F248 Yes:MB91248
No:MB91F249S No:MB91F248S No:MB91248S
Yes:MB91247
No:MB91247S
CHAPTER 1 OVERVIEW
1.3
Block Diagram
This section shows a block diagram of the MB91245/S series.
■ Block Diagram
Figure 1.3-1 Block Diagram of MB91245/S Series
FR 60Lite
CPU Core
32
DSU*
32
DMAC 5 channels
Bit search
32
ROM 256 Kbytes/
128 Kbytes/
Flash 512 Kbytes/
256 Kbytes
Bus
Converter
RAM 24Kbytes/
16Kbytes/8Kbytes
X0, X1
X0A, X1A
MD0 to MD2
INITX
32 to16
Adapter
Clock
control
2 channels
C-CAN
16
PORT I/F
Interrupt
controller
INT0 to INT7
SIN0
SOT0
SCK0
3 channels
reload timer
8 channels
external interrupt
1 channel
PWC timer
1 channel
UART
4 channels
(16-bit mode)
8/16-bit PPG timer
1 channel U-Timer
IN0 to IN3
OUT0, OUT1
CK0, CK1
SGA
SGO
ATGX
AVCC/AVSS
AVRH
AN0 to AN31
SIN3 to SIN5
SOT3 to SOT5
SCK3 to SCK5
4 channels
input
capture
ICU2
ICU3
ICU0
ICU1
2 channels
output compare
OCU0
OCU1
2 channels
free-run timer
PORT
TIN0 to TIN2
TOT0 to TOT2
PWC0
PPG0 to PPG7
Real Time Clock
CPU Detect Reset
FRT0
FRT1
6 channels
Stepper Motor Controller
Sound Generator
32 channels input
8/10-bit A/D converter
3 channels
LIN-UART
RX0, RX1
TX0, TX1
PWM1P0 PWM1P3
PWM1M0 PWM1M3
PWM2P0 PWM2P3
PWM2M0 PWM2M3
PWM1P1 PWM1P4
PWM1M1 PWM1M4
PWM2P1 PWM2P4
PWM2M1 PWM2M4
PWM1P2 PWM1P5
PWM2P2 PWM2P5
PWM2M2 PWM2M5
PWM1M2 PWM1M5
COM0 to COM3
32seg x 4COM
LCD Controller
SEG0 to SEG31
* : Products without S suffix only
*: DSU is built into the MB91V245A only.
Note:
Products with S suffix do not support the sub-block.
5
CHAPTER 1 OVERVIEW
1.4
Package Dimension
This section shows the package dimension.
■ Package Dimension
Figure 1.4-1 Package Dimensions
144-pin plastic LQFP
(FPT-144P-M08)
144-pin plastic LQFP
(FPT-144P-M08)
0.50 mm
Package width ×
package length
20.0 × 20.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
1.20g
Code
(Reference)
P-LFQFP144-20×20-0.50
Note 1) *:Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
22.00±0.20(.866±.008)SQ
* 20.00±0.10(.787±.004)SQ
108
Lead pitch
0.145±0.055
(.006±.002)
73
109
72
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
0˚~8˚
INDEX
144
37
"A"
LEAD No.
1
36
0.50(.020)
0.22±0.05
(.009±.002)
0.08(.003)
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
M
©2003-2008
FUJITSU MICROELECTRONICS LIMITED F144019S-c-4-7
C
2003 FUJITSU LIMITED F144019S-c-4-6
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
6
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
(Mounting height)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
CHAPTER 1 OVERVIEW
1.5
Pin Assignment
This section shows the pin assignment of the MB91245/S series.
■ Pin Assignment
Figure 1.5-1 shows the pin assignment of the MB91245/S series (LQFP-144).
Figure 1.5-1 LQPF-144 Pin Assignment of MB91245/S Series
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
P23/SEG3/A03
P22/SEG2/A02
P21/SEG1/A01
P20/SEG0/A00
PD7/COM3/PPG7
PD6/COM2/PPG5
PD5/COM1/PPG3
PD4/COM0/PPG1
PD3/IN3
PD2/TIN2/IN2
PD1/TIN1/IN1
PD0/TIN0/IN0/PWC0
PG3/TOT2/PPG6
PG2/TOT1/PPG4
PG1/TOT0/PPG2
X0
X1
VSS
VCC
PG0/PPG0
P47/SGO/SYSCLK
P46/SGA/ASX
P57/OUT1/RDY
P56/OUT0/WR1X
P55/SCK5/WR0X
P54/SOT5/RDX
P53/SIN5/CK1/CS3X
P52/SCK4/CS2X
P51/SOT4/CS1X
P50/SIN4/CK0/CS0X
P45/SCK3
P44/SOT3
P43/SIN3
P42/SCK0
P41/SOT0
P40/SIN0
Top View
A04/SEG4/P24
A05/SEG5/P25
A06/SEG6/P26
A07/SEG7/P27
A08/SEG8/P30
A09/SEG9/P31
A10/SEG10/P32
A11/SEG11/P33
A12/SEG12/P34
A13/SEG13/P35
A14/SEG14/P36
A15/SEG15/P37
D08/SEG16/P10
D09/SEG17/P11
D10/SEG18/P12
X0A
X1A
VCC
VSS
VCC3C
D11/SEG19/P13
D12/SEG20/P14
D13/SEG21/P15
D14/SEG22/P16
D15/SEG23/P17
D00/INT0/SEG24/P00
D01/INT1/SEG25/P01
D02/INT2/SEG26/P02
D03/INT3/SEG27/P03
D04/INT4/SEG28/P04
D05/INT5/SEG29/P05
D06/SEG30/P06
D07/ATGX/SEG31/P07
RX0/INT6/P70
TX0/P71
RX1/INT7/P72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108 INITX
107 MD0
106 MD1
105 MD2
104 DVSS
103 DVCC
102 PE7/PWM2M5
101 PE6/PWM2P5
100 PE5/PWM1M5
99 PE4/PWM1P5
98 PE3/PWM2M4
97 PE2/PWM2P4
96 PE1/PWM1M4
95 PE0/PWM1P4
94 PA3/PWM2M3
93 PA2/PWM2P3
92 PA1/PWM1M3
91 PA0/PWM1P3
90 DVSS
89 DVCC
88 PF7/AN15
87 PF6/AN14
86 PF5/AN13
85 PF4/AN12
84 PF3/AN11
83 PF2/AN10
82 PF1/AN9
81 PF0/AN8
80 P67/AN7
79 P66/AN6
78 P65/AN5
77 P64/AN4
76 P63/AN3
75 P62/AN2
74 P61/AN1
73 P60/AN0
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
AVSS/AVRL
AVRH
AVCC
P80/AN16
P81/AN17
P82/AN18
P83/AN19
P84/AN20
P85/AN21
P86/AN22
P87/AN23
P90/AN24
P91/AN25
P92/AN26
P93/AN27
P94/AN28
P95/AN29
P96/AN30
P97/AN31
DVSS
DVCC
PC3/PWM2M2
PC2/PWM2P2
PC1/PWM1M2
PC0/PWM1P2
PB7/PWM2M1
PB6/PWM2P1
PB5/PWM1M1
PB4/PWM1P1
PB3/PWM2M0
PB2/PWM2P0
PB1/PWM1M0
PB0/PWM1P0
DVSS
DVCC
P73/TX1
FPT-144P-M08
7
CHAPTER 1 OVERVIEW
1.6
Pin Descriptions
This section shows the pin description of the MB91245/S series.
■ Pin Descriptions
Table 1.6-1 shows the pin description of the MB91F249/S, MB91F248/S, MB91248/S, MB91247/S.
Table 1.6-1 Pin Descriptions (1 / 7)
Pin No.
Pin name
I/O circuit
type
P20 to P23
141 to 144
1 to 4
5 to 12
13 to 15
SEG0 to SEG3
General-purpose I/O ports
F
LCDC SEG outputs
A00 to A03
External address bus bits 00 to 03
P24 to P27
General-purpose I/O ports
SEG4 to SEG7
F
LCDC SEG outputs
A04 to A07
External address bus bits 04 to 07
P30 to P37
General-purpose I/O ports
SEG8 to SEG15
F
LCDC SEG outputs
A08 to A15
External address bus bits 08 to 15
P10 to P12
General-purpose I/O ports
SEG16 to SEG18
G
D08 to D10
LCDC SEG outputs
External data bus bits 08 to 10
16
X0A
B
Clock (oscillator) input. Sub clock.
17
X1A
B
Clock (oscillator) output. Sub clock.
P13 to P17
21 to 25
SEG19 to SEG23
General-purpose I/O ports
G
External data bus bits 11 to 15
P00 to P05
General-purpose I/O ports
26 to 31
LCDC SEG outputs
G
INT 0 to INT 5
D00 to D05
SEG30
D06
External interrupt input. Since those inputs are occasionally used while the pertinent
external interrupt is enabled, the port outputs need to be disabled except when they are
used intentionally.
External data bus bits 11 to 15
P06
32
LCDC SEG outputs
D11 to D15
SEG24 to SEG29
8
Function
General-purpose I/O port
G
LCDC SEG outputs
External data bus bit 06
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Descriptions (2 / 7)
Pin No.
Pin name
I/O circuit
type
P07
General-purpose I/O port
SEG31
33
LCDC SEG outputs
G
ATGX
34
This pin is used to accept an external trigger when the A/D converter is used.
D07
External data bus bit 07
P07
General-purpose I/O port
INT6
I
RX0
External interrupt input. Since this input is occasionally used while the pertinent external
interrupt is enabled, the pot output need to be disabled except when it is used
intentionally.
RX0 input pin for CAN0
P71
35
36
Function
General-purpose I/O port
I
TX0
TX0 output pin for CAN0
P72
General-purpose I/O port
INT7
I
RX1
RX1 input pin for CAN1
P73
37
External interrupt input. Since this input is occasionally used while the pertinent external
interrupt is enabled, the pot output need to be disabled except when it is used
intentionally.
General-purpose I/O port
I
TX1
TX1 output pin for CAN1
PB0
40
General-purpose I/O port
H
PWM1P0
Stepper motor controller PWM output pin
PB1
41
General-purpose I/O port
H
PWM1M0
Stepper motor controller PWM output pin
PB2
42
General-purpose I/O port
H
PWM2P0
Stepper motor controller PWM output pin
PB3
43
General-purpose I/O port
H
PWM2M0
Stepper motor controller PWM output pin
PB4
44
General-purpose I/O port
H
PWM1P1
Stepper motor controller PWM output pin
PB5
45
General-purpose I/O port
H
PWM1M1
Stepper motor controller PWM output pin
PB6
46
General-purpose I/O port
H
PWM2P1
Stepper motor controller PWM output pin
PB7
47
General-purpose I/O port
H
PWM2M1
Stepper motor controller PWM output pin
9
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Descriptions (3 / 7)
Pin No.
Pin name
I/O circuit
type
PC0
48
General-purpose I/O port
H
PWM1P2
Stepper motor controller PWM output pin
PC1
49
General-purpose I/O port
H
PWM1M2
Stepper motor controller PWM output pin
PC2
50
General-purpose I/O port
H
PWM2P2
Stepper motor controller PWM output pin
PC3
51
General-purpose I/O port
H
PWM2M2
Stepper motor controller PWM output pin
P97 to P90
General-purpose I/O ports. Each function is enabled when analog input is configured to
be forbidden.
54 to 61
E
AN31 to AN24
A/D converter analog inputs. Each input is enabled when analog input is selected in the
ADER register.
P87 to P80
General-purpose I/O ports. Each function is enabled when analog input is configured to
be forbidden.
62 to 69
E
AN23 to AN16
A/D converter analog inputs. Each input is enabled when analog input is selected in the
ADER register.
P60 to P67
General-purpose I/O ports. Each function is enabled when analog input is configured to
be forbidden.
73 to 80
E
AN0 to AN7
A/D converter analog inputs. Each input is enabled when analog input is selected in the
ADER register.
PF0 to PF7
General-purpose I/O ports. Each function is enabled when analog input is configured to
be forbidden.
81 to 88
E
A/D converter analog inputs. Each input is enabled when analog input is selected in the
ADER register.
AN8 to AN15
PA0
91
General-purpose I/O port
H
PWM1P3
Stepper motor controller PWM output pin
PA1
92
General-purpose I/O port
H
PWM1M3
Stepper motor controller PWM output pin
PA2
93
General-purpose I/O port
H
PWM2P3
Stepper motor controller PWM output pin
PA3
94
General-purpose I/O port
H
PWM2M3
Stepper motor controller PWM output pin
PE0
95
General-purpose I/O port
H
PWM1P4
10
Function
Stepper motor controller PWM output pin
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Descriptions (4 / 7)
Pin No.
Pin name
I/O circuit
type
PE1
96
Function
General-purpose I/O port
H
PWM1M4
Stepper motor controller PWM output pin
PE2
97
General-purpose I/O port
H
PWM2P4
Stepper motor controller PWM output pin
PE3
98
General-purpose I/O port
H
PWM2M2
Stepper motor controller PWM output pin
PE4
99
General-purpose I/O port
H
PWM1P5
Stepper motor controller PWM output pin
PE5
100
General-purpose I/O port
H
PWM1M5
Stepper motor controller PWM output pin
PE6
101
General-purpose I/O port
H
PWM2P5
Stepper motor controller PWM output pin
PE7
102
General-purpose I/O port
H
PWM2M5
Stepper motor controller PWM output pin
105
MD2
D
Mode pin 2. The setting on this pin determines the basic operation mode. Connect it to
VCC or VSS.
106
MD1
D
Mode pin 1. The setting on this pin determines the basic operation mode. Connect it to
VCC or VSS.
107
MD0
D
Mode pin 0. The setting on this pin determines the basic operation mode. Connect it to
VCC or VSS.
108
INITX
C
External reset input
General-purpose I/O port. This port is enabled when the data input specification on
UART0 is configured to be forbidden.
P40
109
I
SIN0
UART0 data input. Since this input is occasionally used while UART0 is used for input
operation, the port output needs to be disabled except when it is used intentionally.
P41
General-purpose I/O port. This port is enabled when the data output specification on
UART0 is configured to be forbidden.
110
I
UART0 data output. This function is enabled when the data output specification on
UART0 is configured to be permitted.
SOT0
General-purpose I/O port. This port is enabled when the clock output specification on
UART0 is configured to be forbidden.
P42
111
I
SCK0
UART0 clock input/output. This function is enabled when the clock output specification
on UART0 is "permitted".
P43
General-purpose I/O port. This port is enabled when the data input specification on LINUART0 is "forbidden".
112
I
SIN3
LIN-UART0 data input. Since this input is occasionally used while LIN-UART0 is
used for input operation, the port output needs to be disabled except when it is
used intentionally.
11
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Descriptions (5 / 7)
Pin No.
Pin name
I/O circuit
type
General-purpose I/O port. This port is enabled when the data output specification on LINUART0 is "forbidden".
P44
113
I
SOT3
LIN-UART0 data output. This function is enabled when the data output specification on
LIN-UART0 is "permitted".
P45
General-purpose I/O port. This function is enabled when the clock output specification on
LIN-UART0 is "forbidden".
114
I
LIN-UART0 clock input/output. This function is enabled when the clock output
specification on LIN-UART0 is "permitted".
SCK3
P50
General-purpose I/O port
SIN4
LIN-UART1 data input. Since this input is occasionally used while LIN-UART1 is used
for input operation, the port output needs to be disabled except when it is used
intentionally.
115
I
CK0
External clock input for free-run timer 0
CS0X
Chip select 0 output. This output is enabled in external bus mode.
P51
116
SOT4
General-purpose I/O port
I
P52
SCK4
General-purpose I/O port
I
P53
General-purpose I/O port
SIN5
LIN-UART2 data input. Since this input is occasionally used while LIN-UART2 is used
for input operation, the port output needs to be disabled except when it is used
intentionally.
118
I
CK1
External clock input for free-run timer 1
CS3X
Chip select 3 output. This function is enabled when the output specification on chip select
3 is "permitted".
P54
SOT5
RDX
12
LIN-UART1 clock input/output. This function is enabled when the clock output
specification on LIN-UART1 is "permitted".
Chip select 2 output. This function is enabled when the output specification on chip select
2 is "permitted".
CS2X
119
LIN-UART1 data output. This function is enabled when the data output specification on
LIN-UART1 is "permitted".
Chip select 1 output. This function is enabled when the output specification on chip select
1 is "permitted".
CS1X
117
Function
General-purpose I/O port
I
LIN-UART2 data output. This function is enabled when the data output specification on
LIN-UART2 is "permitted".
External bus read strobe output. This output is enabled in external bus mode.
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Descriptions (6 / 7)
Pin No.
Pin name
I/O circuit
type
P55
120
SCK5
General-purpose I/O port
I
P56
OUT0
General-purpose I/O port
I
P57
123
OUT1
Output compare output
External bus write strobe output. This output is enabled when the WR1X output is
permitted in external bus mode.
WR1X
122
LIN-UART2 clock input/output. This function is enabled when the clock output
specification on LIN-UART2 is "permitted".
External bus write strobe output. This output is enabled when the WR0X output is
permitted in external bus mode.
WR0X
121
Function
General-purpose I/O port
J
Output compare output
RDY
External ready input. This function is enabled when the external ready input specification
is "permitted".
P46
General-purpose I/O port
SGA
I
Sound generator pin
ASX
Address strobe output. This function is enabled when the address strobe output is
"permitted".
P47
General-purpose I/O port
SGO
124
Sound generator pin
I
SYSCLK
PG0
125
System clock output. This function is enabled when the system clock output specification
is "permitted". A clock with the same frequency as that external bus operation frequency
is output at this pin (Clock output stops at transition to the STOP state).
General-purpose I/O port
I
PPG timer 0 output. This function is enabled when the output specification on PPG timer
0 is "permitted".
PPG0
128
X1
A
Main clock (oscillator) output. Main clock.
129
X0
A
Main clock (oscillator) input. Main clock.
PG1
130
131
TOT0
General-purpose I/O port
I
External timer output for reload timer 0
PPG2
PPG timer 2 output. This function is enabled when the output specification on PPG timer
2 is "permitted".
PG2
General-purpose I/O port
TOT1
PPG4
I
External timer output for reload timer 1
PPG timer 4 output. This function is enabled when the output specification on PPG timer
4 is "permitted".
13
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Descriptions (7 / 7)
Pin No.
Pin name
I/O circuit
type
PG3
132
133
TOT2
General-purpose I/O port
I
PPG timer 6 output. This function is enabled when the output specification on PPG timer
6 is "permitted".
PD0
General-purpose input port
TIN0
External event input pin for reload timer 0
IN0
K
Trigger input for input capture 0. This input is enabled when input capture trigger
input is "permitted" and an input port is specified. If this pin is selected for input
capture input, it is occasionally used for input. Therefore the port output needs to
be disabled except when it is used intentionally.
PWC0 pulse width counter 0 input. This function is enabled when the PWC0 pulse width
counter 0 input is "permitted".
PD1
General-purpose input port
TIN1
External event input pin for reload timer 1
134
K
IN1
Trigger input for input capture 1. This input is enabled when input capture trigger input is
"permitted" and an input port is specified. If this pin is selected for input capture input, it
is occasionally used for input. Therefore the port output needs to be disabled except when
it is used intentionally.
PD2
General-purpose input port
TIN2
External event input pin for reload timer 2
135
K
IN2
Trigger input for input capture 2. This input is enabled when input capture trigger input is
"permitted" and an input port is specified. If this pin is selected for input capture input, it
is occasionally used for input. Therefore the port output needs to be disabled except when
it is used intentionally.
PD3
General-purpose input port
136
K
IN3
PD4 to PD7
COM0 to COM3
PPG1, PPG3,
PPG5, PPG7
14
External timer output for reload timer 2
PPG6
PWC0
137 to 140
Function
Trigger input for input capture 3. This input is enabled when input capture trigger input is
"permitted" and an input port is specified. If this pin is selected for input capture input, it
is occasionally used for input. Therefore the port output needs to be disabled except when
it is used intentionally.
General-purpose I/O ports
F
LCDC outputs COM0 to COM3
PPG timers 1, 3, 5, and 7 output. Each function is enabled when the corresponding output
on PPG timers 1, 3, 5, and 7 is configured to be permitted.
CHAPTER 1 OVERVIEW
[Power supply and GND pins]
Pin No.
Pin name
Function
19, 127
VSS
GND pins. The potentials of these pins must be equal.
18, 126
VCC
Power supply pins. The potentials of these pins must be equal.
70
AVCC
Analog power supply pin for A/D converter
71
AVRH
Analog reference power supply pin for A/D converter
72
AVSS/AVRL
20
VCC3C
Capacitor coupling pin for internal regulator
38, 52, 89, 103
DVCC
Power supply pins for SMC
39, 53, 90, 104
DVSS
GND pins for SMC
Analog GND or analog reference power supply pin for A/D converter
15
CHAPTER 1 OVERVIEW
1.7
Input-Output Circuit Types
This section shows Input-Output circuit types.
■ Input-Output Circuit Types
Table 1.7-1 I/O Output Types (1 / 3)
Category
A
Circuit type
Remarks
Clock input
Oscillation feedback resistor for high-speed (main clock
original oscillation): Approx. 1 MΩ
Clock input
Oscillation feedback resistor for low-speed (sub clock
original oscillation): Approx. 7 MΩ
X1
X0
STANDBY
CONTROL
B
X1A
X0A
STANDBY
CONTROL
C
P-ch
Hysteresis input
•
With pull-up resistor
Pull-up resistor = approx. 50 kΩ (Typical)
•
No standby control
P-ch
R
Digital input
16
•
CHAPTER 1 OVERVIEW
Table 1.7-1 I/O Output Types (2 / 3)
Category
Circuit type
Remarks
Mask ROM product •
Hysteresis input
D
Mask ROM product
Hysteresis input
Only MD2 and MD1 are fitted with pull-down resistor.
•
Flash memory product
Hysteresis input
High-voltage control for Flash tests.
•
CMOS output (4 mA)
•
•
Hysteresis (automotive level) input (with standby
control)
Analog input
(If an ADE bit is "1", the corresponding analog input is
enabled.)
•
•
CMOS output (4 mA)
LCDC output
•
Hysteresis (automotive level) input (with standby
control)
CMOS output (4 mA)
LCDC output
Hysteresis (automotive level) input (with standby
control)
Hysteresis (CMOS level) input
(with standby control)
Flash memory product
Control
Mode input
Diffused resistor
E
P-ch
N-ch
Digital output
Digital output
R
Digital input
STANDBY CONTROL
Analog input
F
P-ch
Digital output
N-ch
Digital output
R
LCDC output
R
Hysteresis input
STANDBY CONTROL
P-ch
Digital output
•
•
N-ch
Digital output
•
G
R
•
LCDC output
R
R
Hysteresis input
(Automotive Level)
Hysteresis input
(CMOS Level)
STANDBY CONTROL
17
CHAPTER 1 OVERVIEW
Table 1.7-1 I/O Output Types (3 / 3)
Category
Circuit type
Remarks
H
P-ch
N-ch
•
CMOS output
High-current output for PWM (30 mA)
•
Hysteresis (automotive level) input (with standby
control)
•
CMOS output (4 mA)
•
Hysteresis (automotive level) input (with standby
control)
CMOS output (4 mA)
Hysteresis (automotive level) input (with standby
control)
Hysteresis (CMOS level) input
(with standby control)
Digital output
Digital output
R
Digital input
STANDBY CONTROL
I
P-ch
Digital output
N-ch
Digital output
R
Digital input
STANDBY CONTROL
P-ch
Digital output
•
•
N-ch
Digital output
•
J
R
R
Hysteresis input
(Automotive Level)
Hysteresis input
(CMOS Level)
STANDBY CONTROL
K
•
Hysteresis input
(automotive level)
•
With standby control
P-ch
N-ch
R
Digital input
STANDBY CONTROL
18
CHAPTER 2
HANDLING DEVICES
This chapter provides precautions on using the
MB91245/S series.
2.1 Handling Devices
19
CHAPTER 2 HANDLING DEVICES
2.1
Handling Devices
This section explains prevention of latch-up, treatment of pins and so on.
■ Handling Devices
● Preventing Latch-up
A CMOS IC may encounter latch-up when a voltage that is higher than VCC or lower than VSS is applied
to an input or output pin or when a voltage that exceeds the rating is applied between the VCC and VSS
pins. Latch up causes the supply current to increase abruptly and may lead to thermal breakdown of the
device. Therefore, be careful to prevent any voltage from exceeding the maximum rating.
● Treatment of Unused Pins
If unused input pins are left open, they may cause malfunction or latch-up that will lead to permanent
breakdown. Therefore, pull up or down the voltage between the unused input pins by connecting a resistor
of 2 kΩ or higher.
For unused I/O pins, set them as output state and open them, or keeping them in input state, treat them as if
they were input pins.
● About Power Supply Pins
The device is designed to ensure that if the device contains multiple VCC or VSS pins, the pins that should
be at the same potential are interconnected to prevent latch-up or other malfunctions. Further, connect these
pins to an external power source or ground to reduce unwanted radiation, prevent strobe signals from
malfunctioning due to a raised ground level, and fulfill the total output current standard, etc. Also, pay
consideration to ensure that the VCC and VSS pins of this device are connected to the power source with
the lowest possible impedance.
It is also advisable to connect a ceramic capacitor of approximately 0.1μF near this device between the
VCC and VSS pins as a bypass capacitor.
This device includes a regulator. When a 5V power supply is used for this device, supply the 5V power to
the VCC pin and be sure to connect a capacitor of at least 1μF to the VCC3C pin for the regulator.
20
Figure 2.1-1 Power Source Connection Example
5V
5V
5V
VCC
DVCC
AVCC
AVRH
AVSS
VSS
DVSS
VCC3C
1μF
GND
● About Crystal Oscillation Circuit
If a noise source exists near the X0, X1, X0A, or X1A pin, it may cause this device to malfunction. Design
the PC board ensuring that the bypass capacitors connected to X0/X1, X0A/X1A, the crystal oscillator (or
ceramic oscillator) and ground are located as close to the device as possible. When the X0 and X1 signal
lines need to be routed, shield them to use on the board. Especially, care is needed when you use a pin that
is adjacent to X0.
A PC board artwork layout such that the X0, X1, X0A, and X1A pins are surrounded by ground is strongly
recommended because this layout is likely to ensure stable operation.
If you plan to use a dual clock product as products with S suffix, the sub clock is still required.
If you use an MB91F249S, MB91F248S, MB91248S, or MB91247S, connect the X0A pin to ground and
leave the X1A pin open.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
● About Mode Pins (MD0 to MD2)
Connect these pins directly to the VCC or VSS pin. To prevent noise-induced malfunction, the pattern
between the power supply for VCC pin and that for VSS pin must be as short as possible and the
impedance of the connection should be as low as possible.
● About Power-on
Immediately after power-on, be sure to apply the setting initialization reset (INIT) via the INITX pin.
Immediately after power-on, retain the INITX pin at the "L" level for the time period required for the
oscillator circuit to become stable to secure the oscillation stabilization wait time period for the oscillator
circuit
(Power-on reset initializes the oscillation stabilization wait time to the minimum value).
● About Source Oscillation Input at Power-on
After power-on, be sure to continue a clock input until the oscillation stabilization wait time is released.
● Treatment of A/D Converter Power Supply Pins
Even when the A/D converter is not used, connect the A/D converter power supply pins to ensure AVCC =
AVRH = VCC and AVSS = VSS.
21
CHAPTER 2 HANDLING DEVICES
● A/D Converter analog Power Supply Input Sequence
Be sure to turn on the power (AVCC, AVRH) to the A/D converter and apply analog inputs (AN0 to
AN31) after turning on the digital power (VCC). For power-off, turn off the digital power (VCC) after
turning off the power to the A/D converter and turning off the analog inputs. At power-on and power-off,
be sure that AVRH does not exceed AVCC. When using a pin designed also for an analog input as an input
port, be sure that the input voltage does not exceed AVCC.
● Handling Power for the High-current Output Buffer Pins (DVCC, DVSS)
Apply power for the high-current output buffer pin (DVCC) after turning on the digital power (VCC). For
power-off, turn off the digital power (VCC) after turning off power for the high-current output buffer pin.
If a high-current output buffer pin is used as a general-purpose port, apply power for the high-current
output buffer pin (DVCC).
Use potential at GND pins for the high-current output buffer pin (DVSS) as same as that of digital GND
(VSS).
● Notes on Changing Main Mode to Sub-mode or STOP Mode
After transition from main mode to sub-mode or STOP mode, stop the main clock. When returning from
sub-mode or STOP mode to main mode, wait until the oscillator is stabilized.
● About Writing to Flash
Note that writing to a Flash is now allowed in sub-mode.
● Pin Handling When LCD is Not Used
Leave pins COM0 to COM3 and SEG0 to SEG31 open.
22
CHAPTER 3
CPU AND CONTROL BLOCK
This chapter provides the basic information required to
understand FR60Lite's functions, such as its
architecture, specifications and instructions.
3.1
Memory Space
3.2
Memory Map
3.3
Internal Architecture
3.4
Programming Model
3.5
Data Structure
3.6
Word Alignment
3.7
Memory Map
3.8
Branch Instruction
3.9
EIT (Exception, Interrupt, and Trap)
3.10 Operation Mode
3.11 Reset (Device Initialization)
3.12 Clock Generation Control
3.13 Device Status Control
23
CHAPTER 3 CPU AND CONTROL BLOCK
3.1
Memory Space
MB91245/S series logical address space is 4 Gbytes (expressing by 232 addresses). It is
linearly accessed by the CPU.
■ Direct Addressing Area
The following areas in the address space are used for I/O.
This areas are referred to as the direct addressing areas. They can be designated by an address that is
directly specified in an instruction operand.
The direct addressing areas are as follows depending on the size of the data to be accessed:
24
• byte data access
: 000H to 0FFH
• half word data access
: 000H to 1FFH
• word data access
: 000H to 3FFH
CHAPTER 3 CPU AND CONTROL BLOCK
3.2
Memory Map
The memory map of each product is shown below.
■ Memory Map of MB91245/S Series
Figure 3.2-1 Memory Map of MB91245/S Series
Memory map of MB91V245A
Single-chip mode
Internal-ROM,
external-bus mode
External-ROM,
external-bus mode
I/O
I/O
I/O
I/O
I/O
I/O
Access inhibited
Access inhibited
Access inhibited
I/O(C-CAN)
I/O(C-CAN)
I/O(C-CAN)
Access inhibited
Access inhibited
Access inhibited
Built-in RAM,
32 Kbytes
Built-in RAM,
32 Kbytes
Built-in RAM,
32 Kbytes
Access inhibited
Access inhibited
Emulation
SRAM area
Emulation
SRAM area
Access inhibited
External area
0000 0000H
Direct
addressing area
0000 0400H
0001 0000H
0002 0000H
0002 01B4H
0003 8000H
0004 0000H
See the I/O map.
Access inhibited
0005 0000H
0008 0000H
External area
0010 0000H
FFFF FFFFH
Memory map of MB91F249/S
Single-chip mode
Internal-ROM,
external-bus mode
External-ROM,
external-bus mode
I/O
I/O
I/O
I/O
I/O
I/O
Access inhibited
Access inhibited
Access inhibited
I/O(C-CAN)
I/O(C-CAN)
I/O(C-CAN)
Access inhibited
Access inhibited
Access inhibited
Built-in RAM,
24 Kbytes
Built-in RAM,
24 Kbytes
Built-in RAM,
24 Kbytes
Access inhibited
Access inhibited
Access inhibited
Flash memory
area
512Kbytes
Flash memory
area
512Kbytes
External area
Access inhibited
External area
0000 0000H
Direct
addressing area
0000 0400H
0001 0000H
0002 0000H
0002 01B4H
0003 A000H
0004 0000H
See the I/O map.
0005 0000H
0008 0000H
0010 0000H
FFFF FFFFH
Each mode is set when the pertinent mode vector is fetched after INITX is negated.
(For information on mode setting, refer to "■Setting the Mode" of section "3.10 Operation Mode").
(Continued)
25
CHAPTER 3 CPU AND CONTROL BLOCK
(Continued)
Memory map of MB91F248/S
Single-chip mode
Internal-ROM,
external-bus mode
External-ROM,
external-bus mode
I/O
I/O
I/O
I/O
I/O
I/O
Access inhibited
Access inhibited
Access inhibited
I/O(C-CAN)
I/O(C-CAN)
I/O(C-CAN)
Access inhibited
Access inhibited
Access inhibited
Built-in RAM,
16 Kbytes
Built-in RAM,
16 Kbytes
Built-in RAM,
16 Kbytes
Access inhibited
Access inhibited
Access inhibited
Flash memory
area
256Kbytes
Flash memory
area
256Kbytes
External area
Access inhibited
External area
0000 0000H
Direct
addressing area
0000 0400H
0001 0000H
0002 0000H
0002 01B4H
0003 C000H
0004 0000H
See the I/O map.
0005 0000H
000C 0000H
0010 0000H
FFFF FFFFH
Memory map of MB91248/S
Single-chip mode
Internal-ROM,
external-bus mode
External-ROM,
external-bus mode
I/O
I/O
I/O
Direct
addressing area
I/O
I/O
I/O
See the I/O map.
Access inhibited
Access inhibited
Access inhibited
0000 0000H
0000 0400H
0001 0000H
0002 0000H
0002 01B4H
0003 C000H
0004 0000H
I/O(C-CAN)
I/O(C-CAN)
I/O(C-CAN)
Access inhibited
Access inhibited
Access inhibited
Built-in RAM,
16 Kbytes
Built-in RAM,
16 Kbytes
Built-in RAM,
16 Kbytes
Access inhibited
Access inhibited
Access inhibited
0005 0000H
000C 0000H
MASK ROM
area
256Kbytes
MASK ROM
area
256Kbytes
External area
0010 0000H
Access inhibited
External area
FFFF FFFFH
Each mode is set when the pertinent mode vector is fetched after INITX is negated.
(For information on mode setting, refer to "■Setting the Mode" of section "3.10 Operation Mode").
(Continued)
26
CHAPTER 3 CPU AND CONTROL BLOCK
(Continued)
Memory map of MB91247/S
Single-chip mode
Internal-ROM,
external-bus mode
External-ROM,
external-bus mode
I/O
I/O
I/O
Direct
addressing area
da
I/O
da
I/O
da
I/O
See the I/O map.
Access inhibited
Access inhibited
Access inhibited
I/O(C-CAN)
I/O(C-CAN)
I/O(C-CAN)
Access inhibited
Access inhibited
Access inhibited
Built-in RAM,
8 Kbytes
Built-in RAM,
8 Kbytes
Access inhibited
Access inhibited
MASK ROM
area
128Kbytes
MASK ROM
area
128Kbytes
External area
Access inhibited
External area
0000 0000H
0000 0400H
0001 0000H
0002 0000H
0002 01B4H
0003 E000H
0004 0000H
Built-in RAM,
8 Kbytes
Access inhibited
0005 0000H
000E 0000H
0010 0000H
FFFF FFFFH
The configurations of each mode are determined by a pertinent mode vector fetch after INITX is negated.
(For information on mode setting, refer to "■Setting the Mode" of section "3.10 Operation Mode").
27
CHAPTER 3 CPU AND CONTROL BLOCK
3.3
Internal Architecture
The MB91245/S series CPU is a high performance core based on the RISC architecture
while incorporating high-level function instructions for embedded applications.
■ Features
● Employing the RISC architecture
Basic instruction: 1 instruction 1 cycle
● 32-bit architecture
General register: 32-bit × 16
● Linear memory space of 4 Gbytes
● Equipped with multiplier
32-bit × 32-bit multiplication, 5 cycles
16-bit × 16-bit multiplication, 3 cycles
● Enhanced interrupt processing feature
Fast response rate (6 cycles)
Multiple interrupt supported
Level mask feature (16 levels)
● Enhanced I/O operation instruction
Memory to memory transfer instruction
Bit processing instruction
● Effective coding
Basic instruction word length: 16-bit
● Low-power consumption
Sleep mode/Stop mode
● Clock division ratio setting feature
28
CHAPTER 3 CPU AND CONTROL BLOCK
■ Internal Architecture
The Harvard architecture, in which the instruction bus is separated from the data bus, is employed for
the FR family CPU.
32-bit ↔ 16-bit bus converter is connected to the 32-bit bus (F-bus) to realize the interface between the
CPU and the peripheral resources. Harvard↔Princeton bus converter is connected both to the I-bus
and D-bus to realize the interface the interface between the CPU and the bus controller.
Figure 3.3-1 Internal Architecture
FR CPU
I-bus
Built-in
RAM
Built-in
ROM
D-bus
32
32
32
32
Harvard←
→Princeton
Bus converter
F-bus
32
32
32 X-bus
32
External bus
16
Address
32 bit←→16 bit
Bus converter
Bus controller
Data
16
16
R-bus
Peripheral/Port
Note:
For MB91245/S series, available address width when using the external bus interface is up to 16
bits.
29
CHAPTER 3 CPU AND CONTROL BLOCK
■ CPU
The CPU is a compact implementation of the FR architecture of the 32-bit RISC.
It uses a 5-stage instruction pipeline scheme in order to execute one instruction per cycle. The pipeline
consists of following stages.
• Instruction fetch (IF)
...
• Instruction decode (ID) ...
• Execute (EX)
...
Outputs the instruction address and fetches the instruction.
Decodes the fetched instruction. Registers are also read.
Executes operations.
• Memory access (MA) ...
Accesses the memory for loading or storing.
• Write back (WB)
Writes the operation result (or loaded memory data) in the register.
...
Figure 3.3-2 Instruction Pipeline
CLK
Instruction 1
WB
Instruction 2
MA
WB
Instruction 3
EX
MA
WB
Instruction 4
ID
EX
MA
WB
Instruction 5
IF
ID
EX
MA
WB
IF
ID
EX
MA
Instruction 6
WB
Instructions are never executed in random order. That is, when instruction A enters the pipeline before
instruction B does, instruction A reaches the write back stage before instruction B does.
In default, the execution is performed at the rate of one instruction per cycle. However, load/store
instructions with memory wait, branch instructions without a delay slot, and multiple cycle instructions
need multiple cycles to execute one instruction. In addition, the execution rate of instruction slows
down when the instruction delivery is slow.
■ 32-bit ↔ 16-bit Bus Converter
It carries out an interface between F-bus, that is fast accessed with 32-bit width and R-bus, that is
accessed with 16-bit width, to realize a data access from the CPU to built-in peripheral circuits.
If accessed with a 32-bit width from the CPU, this bus converter converts it to two 16-bit width
accesses to R-bus. Some of the built-in peripheral circuits have limitations on access width.
30
CHAPTER 3 CPU AND CONTROL BLOCK
■ Harvard ↔ Princeton Bus Converter
It retains consistency between the CPU instruction accesses and data accesses to realize the smooth
interface with the external bus.
The Harvard architecture, in which the instruction bus is separated from the data bus, is employed for
the CPU. For the bus controller, that controls the external bus, the Princeton architecture with a single
bus is employed. This bus converter prioritizes the CPU instruction accesses and data accesses to
control accesses to the bus controller. This function optimizes the order of accesses to the external bus
all the time.
■ Outline of Instructions
The FR family supports, in addition to a general RISC instruction system, the logical operations, bit
manipulations and direct addressing instructions optimized for embedded use. Each instruction is 16-bit
long (some are 32-bit or 48-bit long), achieving a high efficiency of memory use.
The instruction set can be divided into following function groups:
• Arithmetic operation instructions
• Load and store instructions
• Branch instructions
• Logical operation and bit manipulation instructions
• Direct addressing instructions
• Other Instructions
● Arithmetic Operation Instructions
Arithmetic operation instructions include standard arithmetic operation instructions (addition,
subtraction, and comparison) and shift instructions (logical shift and arithmetic shift). For addition and
subtraction operations, operations with a carry used in multiword-length operations, and operations
without changing the flag value, which are useful for address calculations, are also supported.
Furthermore, 32 × 32 bits and 16 × 16 bits multiplication instructions and 32 bits divided by 32 bits step
division instruction are available. The FR family also supports immediate value transfer instructions
which allow immediate data to be set in registers, and inter-register transfer instructions.
Every arithmetic operation instruction performs an operation using the general-purpose registers and
multiplication/division registers in the CPU.
● Load and Store Instructions
Load and store instructions are used to read data from and write data to external memory respectively.
They are also used to read from or write in the peripheral resource circuits (I/O) inside the chip.
Load and store instructions use three types of access data length; byte-length, half word-length, and
word-length. The FR family supports not only general register-indirect-memory-addressing but also, for
some instructions, register-indirect-memory-addressing with displacement or with register increment/
decrement.
● Branch Instructions
The branch instruction group includes branch, call, interrupt, and recovery instructions. There are two
types of branch instructions, and one has a delay slot and the other does not. They can seek optimization
for each application. Refer to section "3.8 Branch Instruction" for details.
31
CHAPTER 3 CPU AND CONTROL BLOCK
● Logical Operation and Bit Manipulation Instructions
Logical operation instructions can execute AND, OR, or EOR logical operations between generalpurpose registers or between a general-purpose register and memory (and I/O). A bit manipulation
instruction can directly manipulate the contents of memory (and I/O). These instructions use general
register-indirect-memory-addressing.
● Direct Addressing Instructions
The direct addressing instructions are used for accesses between an I/O and a general-purpose register
or between an I/O and memory. Specifying an I/O address directly in an instruction, not via a register,
enables a high-speed and highly efficient access. For some instructions, register-indirect-memoryaddressing with register increment/decrement is also available.
● Other Instructions
Other instructions are available for flag setting in PS register, stack operations, and sign/zero extension.
The FR family also supports function entry/exit compliant with high-level languages and multipleregister load/store instructions.
Note:
The setting of flash memory weight register (FLWC) influences the CPU processing performance.
Adjust the setting of the register to the optimal value before using. refer to "28.2 FLASH Memory
Register".
32
CHAPTER 3 CPU AND CONTROL BLOCK
3.4
Programming Model
This section explains the basic programming model and each register.
■ Basic Programming Model
Figure 3.4-1 Basic Programming Model
32 bits
[Initial value]
R0
XXXX XXXXH
R1
General-purpose
registers
R12
R13
AC
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Program counter
PC
Program status
PS
Table base register
TBR
Return pointer
RP
System stack pointer
SSP
User stack pointer
USP
Multiplication/division
result register
ILM
SCR
CCR
MDH
MDL
33
CHAPTER 3 CPU AND CONTROL BLOCK
3.4.1
Register
This section explains each register.
■ General-purpose Registers
Figure 3.4-2 General-purpose Registers
32 bits
[Initial value]
R0
R1
XXXX XXXXH
......
AC
FP
SP
......................
......
R12
R13
R14
R15
XXXX XXXXH
0000 0000H
Registers R0 to R15 are general-purpose registers. They are used as accumulators for various types of
operations or memory access pointers.
In the 16 registers, the following registers are provided for special applications, with some enhanced
instructions.
R13: Virtual accumulator (AC)
R14: Frame pointer (FP)
R15: Stack pointer (SP)
The initial values of R0 to R14 after resetting are undefined. The initial value of R15 is "00000000H"
(SSP value).
■ PS (Program Status)
The program status register holds the program status in three parts, ILM, SCR, and CCR.
The undefined bits in the diagram are all reserved. When the register is read, "0" is always read from
these bits. Writing to this register will have no effect.
bit 31
20
16
ILM
34
10
SCR
87
0
CCR
CHAPTER 3 CPU AND CONTROL BLOCK
■ CCR (Condition Code Register)
bit
7
----
6
----
5
S
4
I
3
N
2
Z
1
V
0
C
[Initial value]
--00XXXXB
[bit5] S: Stack flag
This bit specifies the stack pointer used as R15.
Value
Description
0
SSP is used as R15.
The bit is automatically set to "0" when EIT occurs
(The value saved to the stack is one before the bit has been cleared).
1
USP is used as R15.
This bit is cleared to "0" by resetting.
Set the bit to "0" when the RETI instruction is executed.
[bit4] I: Interrupt enable flag
This bit enables or disables a user interrupt request.
Value
Description
0
Disables user interrupts.
This bit is cleared to "0" when INT instruction is executed.
(The value saved to the stack is one before the bit has been cleared).
1
Enables user interrupts.
The masking of user interrupt requests is controlled by the value held in ILM.
This bit is cleared to "0" by resetting.
[bit3] N: Negative flag
This bit indicates a sign applicable when the operation result is assumed to be an integer that is
represented in two's complement.
Value
Description
0
Indicates that the operation result is a positive value.
1
Indicates that the operation result is a negative value.
The initial value after resetting is undefined.
35
CHAPTER 3 CPU AND CONTROL BLOCK
[bit2] Z: Zero flag
This bit indicates whether the operation result is "0".
Value
Description
0
Indicates that the operation result is a value other than "0".
1
Indicates that the operation result is "0".
The initial value after resetting is undefined.
[bit1] V: Overflow flag
This bit assumes that the operand used for the operation is an integer represented in two's complement
and indicates whether an overflow occurred as the result of the operation.
Value
Description
0
Indicates that no overflow occurred as the result of operation.
1
Indicates that an overflow occurred as the result of operation.
The initial value after resetting is undefined.
[bit0] C: Carry flag
This bit indicates whether a carry or a borrow from the most significant bit occurred during the
operation.
Value
Description
0
Indicates that neither a carry nor a borrow occurred.
1
Indicates that either a carry or a borrow occurred.
The initial value after resetting is undefined.
36
CHAPTER 3 CPU AND CONTROL BLOCK
■ SCR (System Condition Code Register)
bit
10
D1
9
D0
8
T
[Initial value]
XX0B
[bit10, bit9] D1, D0: Step division flag
These bits hold intermediate data for the time of an execution of step division.
They must not be changed during an execution of step division.
When another processing is performed during the execution of a step division, the step division is
guaranteed to resume by saving and restoring the value in the PS register.
The initial value after resetting is undefined.
Those values are set by a DIV0S instruction with the references of the dividend and the divisor.
Execution of the DIV0U instruction forcibly clears the bits.
[bit8] T: Step-trace-trap flag
This flag specifies whether to enable step-trace-trap.
Value
Description
0
Disables step-trace-trap.
1
Enables step-trace-trap.
Setting the bit to 1 inhibits all user NMIs and user interrupts.
This flag is initialized to "0" by resetting.
The step-trace-trap function is used by an emulator. It cannot be used in user programs while it is used
by the emulator.
37
CHAPTER 3 CPU AND CONTROL BLOCK
■ ILM
bit
20
ILM4
19
ILM3
18
ILM2
17
ILM1
16
ILM0
[Initial value]
01111B
The ILM register holds an interrupt level mask value. The value held by the ILM register is used for
level masking.
Over the interrupt requests input to the CPU, only those with higher interrupt levels than the level
indicated by this ILM are accepted.
The values take 0 (00000B) for the maximum and 31 (11111B) for the minimum.
There are following restrictions for this value that a program can set.
When the original value is in the range from 16 to 31
A new value can be set within the range from 16 to 31. If an instruction that specifies a value in the
range from 0 to 15 is executed, a value (specified value + 16) is transferred.
When the original value is in the range from 0 to 15
A desired value from 0 to 31 can be set.
This flag is initialized to 15 (01111B) by resetting.
■ Notes on PS Register
Since some instructions write the information to PS register early time, the following exception
operations may cause a break to occur in an interrupt processing routine when using the debugger or the
updating of the PS flag. In either case, the processing is conducted properly again after return from an
EIT, the operations before and after the EIT are designed to perform as specified.
• The following operations may be performed when the instruction immediately followed by a
DIV0U/DIV0S instruction results in (a) acceptance of a user interrupt, (b) single-stepping, or (c) a
break in response to a data event or emulator menu:
(1) D0 and D1 flags are updated in advance.
(2) An EIT handling routine (user interrupt, NMI, or emulator) is executed.
(3) Upon returning from the EIT, the DIV0U/DIV0S instructions are executed and the D0/D1 flags
are updated back to the original value held before step (1).
• When a user interrupt source exists, executing either of the OR CCR, ST LIM and MOV Ri and PS
instructions to enable the interrupt results in the following operations:
(1) The PS register is updated in advance.
(2) An EIT handling routine (user interrupt) is executed.
(3) Upon returning from the EIT, the above instructions are executed and the PS registers are
updated back to the original value held before step (1).
38
CHAPTER 3 CPU AND CONTROL BLOCK
■ PC (Program Counter)
bit
31
0
PC
[Initial value]
XXXXXXXXH
[bit31 to bit0]
The program counter indicates the address of the instruction being executed.
Bit0 is set to "0" when the PC is updated according to instruction execution. Bit0 may be set to "1" only
when an odd-numbered address is specified for the branch destination address. Even at this event, bit0
has no effect and an instruction must be put at an address starting from a multiple of two.
The initial value after resetting is undefined.
■ TBR (Table Base Register)
bit
31
0
TBR
[Initial value]
000FFC00H
The table base register holds the first address of the vector table used for EIT processing.
The initial value after resetting is "000FFC00H".
■ RP (Return Pointer)
bit
31
0
RP
[Initial value]
XXXXXXXXH
The return pointer register holds the address to which control returns from a subroutine.
When the CALL instruction is executed, the PC value is transferred to this RP.
When the RET instruction is executed, the contents of RP are transferred to the PC.
The initial value after resetting is undefined.
■ SSP (System Stack Pointer)
bit
31
SSP
0
[Initial value]
00000000H
SSP stands for system stack pointer.
When the S flag is "0", the SSP functions as R15.
The SSP can be specified explicitly. It can also be used as a stack pointer to specify the stack for saving
the PS and PC when EIT occurs.
The initial value after resetting is "00000000H".
39
CHAPTER 3 CPU AND CONTROL BLOCK
■ USP (User Stack Pointer)
bit
31
0
USP
[Initial value]
XXXXXXXXH
USP stands for user stack pointer.
When the S flag is "1", the USP functions as R15.
The USP can be specified explicitly.
The initial value after resetting is undefined.
The USP cannot be used for the RETI instruction.
■ Multiply and Divide Register
bit
31
0
MDH
MDL
The MDH and MDL are registers for multiply/divide operations, with 32 bits long each.
The initial values after resetting are undefined.
Multiplication
In a 32-bit × 32-bit multiplication, the resultant 64-bit data is stored in the multiply and divide
register in a distribution below:
MDH: Upper 32 bits
MDL: Lower 32 bits
In a 16-bit × 16-bit multiplication, the resultant data is stored in the multiply and divide register in a
distribution below:
MDH: Undefined
MDL: Resultant 32-bits
Division
When a calculation begins, the dividend is stored in the MDL.
The result of the division by DIV0S/DIV0U, DIV1, DIV2, DIV3, or DIV4S instruction is stored in
MDL and MDH as follows:
MDH: Remainder
MDL: Quotient
40
CHAPTER 3 CPU AND CONTROL BLOCK
3.5
Data Structure
The FR family uses the following two data ordering methods:
• Bit ordering
• Byte ordering
■ Bit Ordering
The FR family uses little endian for bit ordering.
Figure 3.5-1 Bit Configuration of Bit Ordering
bit 31
29
30
27
28
25
26
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
MSB
0
LSB
■ Byte Ordering
The FR family uses big endian for byte ordering.
Figure 3.5-2 Bit Configuration of Byte Ordering
Memory
bit
7
MSB
LSB
bit31
23
15
7
0
10101010B 11001100B 11111111B 00010001B
0
10101010B
Address n
11001100B
Address (n + 1)
11111111B
Address (n + 2)
00010001B
Address (n + 3)
41
CHAPTER 3 CPU AND CONTROL BLOCK
3.6
Word Alignment
Since instruction and data are accessed in byte units, the addresses to be placed
depend on the instruction length and data width.
■ Program Access
A program running in the FR family must be placed at an address space starting at a multiple of two.
Bit0 of the program counter (PC) is set to "0" when the PC is updated according to the instruction
execution. Bit0 may be set to "1" only when an odd-numbered address is specified for a branch
destination address.
Even at such event, bit0 has no effect, therefore an instruction must always be placed at an address of a
multiple of two.
No exception with an odd-numbered address occurs.
■ Data Access
When data access is made in the FR family, address alignment is performed forcibly in accordance with
access width as follows:
• Word access:
Address are aligned in multiples of four (the two least significant bits are forcibly
set to "00B").
• half word access: Address are aligned in multiples of two (the least significant bit is forcibly set to
0).
• Byte access:
Any address is used
Some bits are forcibly set to 0 when a word or half word data access is made, but this is applicable only
to the calculation result of an effective address. For instance, in @(R13, Ri) addressing mode, the
register before addition is used as it is for calculation (even if the least significant bit is "1"), and the
least significant bit of the result of addition is masked. Thus, the register before calculation is not
masked.
[Example] LD @ (R13, R2), R0
R13
00002222H
R2
00000003H
+)
Addition result 0 0 0 0 2 2 2 5 H
Lower two bits are forcibly masked
Address pin
42
00002224H
CHAPTER 3 CPU AND CONTROL BLOCK
3.7
Memory Map
This section shows the memory map of the MB91245/S series.
■ Memory Map
Figure 3.7-1 shows the memory map.
Figure 3.7-1 Memory Map
0000 0000H
0000 0100H
0000 0200H
Byte data
Half word data
Direct
addressing area
Word data
0000 0400H
000F FC00H
Vector table
000F FFFFH
FFFF FFFFH
■ Direct Addressing Area
The following areas in the address space are used for I/O. This area can directly specify the operand
addresses in the instruction using the direct addressing.
The size of the direct addressing area varies depending on data length.
• Byte data (8 bits):
000H to 0FFH
• half word data (16 bits): 000H to 1FFH
• Word data (32 bits):
000H to 3FFH
■ Initial Vector Table Area
The area ranging from "000FFC00H" to "000FFFFFH" is the EIT vector table initial area.
The vector table used for EIT processing can be mapped to a desired address by rewriting TBR. The
table is placed to this address space by an initialization due to a resetting.
43
CHAPTER 3 CPU AND CONTROL BLOCK
3.8
Branch Instruction
A branch instruction can be set operation with or without a delay slot in the FR family.
■ Operation with Delay Slot
● Instruction
The following instructions execute a branch operation with a delay slot:
JMP:D
@Ri
CALL:D label12
CALL:D @Ri
RET:D
BRA:D
label9
BNO:D
label9
BEQ:D
label9
BNE:D
label9
BC:D
label9
BNC:D
label9
BN:D
label9
BP:D
label9
BV:D
label9
BNV:D
label9
BLT:D
label9
BGE:D
label9
BLE:D
label9
BGT:D
label9
BLS:D
label9
BHI:D
label9
● Operation explanation
An operation with a delay slot executes the instruction which is placed immediately after the branch
instruction (called a delay slot) then branches, before executing the instruction at the branch destination.
Since a delay slot instruction is executed before branching, the execution speed seems one cycle. When
a valid instruction cannot be put at the delay slot, an NOP instruction must be placed.
[Example]
;
Instruction list
ADD
R1, R2
;
BRA:D
LABEL
; Branch instruction
MOV
R2, R3
; Delay slot......The instruction is executed before branching.
...
LABEL:
ST
R3,@R4 ; Branch destination
In a conditional branch instruction, the instruction placed at the delay slot is executed regardless the
branch condition is satisfied.
For delayed branch instructions, the execution order of some instructions seems to be reversed,
however, this only applies to PC update operations, and other operations (register updating and
referencing, etc.) are executed in the order of the code.
Specific examples are shown below.
1. Ri that is referenced by the JMP:[email protected] or CALL:[email protected] instruction is not affected even when the
instruction in the delay slot updates the Ri.
[Example]
LDI:32
#Label,
JMP:D
@R0
LDI:8
#0,
...
44
R0
; Branches to Label
R0
; Does not affect the branch destination address.
CHAPTER 3 CPU AND CONTROL BLOCK
2. RP that is referenced by a RET:D instruction is not affected even when the instruction in the delay
slot updates RP.
[Example]
RET:D
MOV
; Branches to the address specified by RP that is set previously.
R8,
RP
; Does not affect the return operation.
...
3. The flag that is referenced by the Bcc:D rel instruction is not affected by the instruction in the delay
slot.
[Example]
ADD
#1,
R0
; Changes the flag.
BC:D
Overflow
; Branches according to the execution result of the above
instruction.
AND CCR
#0
; The updated flag will not be referenced by the above branch
instruction.
...
4. When RP is referenced by the instruction in the delay slot of the CALL:D instruction, the data
updated by the CALL:D instruction is read.
[Example]
CALL:D
Label
MOV
RP,
; Updates RP and branches.
R0
; Transfers the RP; the execution result of the above CALL:D
instruction.
...
● Restrictions
1. Instructions that can be placed in delay slots
An instruction that can be executed in a delay slot must satisfy all the following conditions:
•
One-cycle instruction
•
Non-branch instruction
•
Instruction whose operation is not affected even when the execution order changes
One-cycle instructions are instructions for which "1", "a", "b", "c", or "d" is indicated in the cycle
count column in the instruction list.
2. Step trace trap
No step trace trap is generated between a delay slot and the execution of the branch instruction
having the delay slot.
3. Interrupt /NMI
No interrupt/NMI is accepted between a delay slot and the execution of the branch instruction
having the delay slot.
4. Undefined-instruction exception
Even if an undefined instruction is placed in a delay slot, no undefined-instruction exception occurs.
The undefined instruction works as an NOP instruction.
45
CHAPTER 3 CPU AND CONTROL BLOCK
■ Operation without Delay Slots
● Instruction
Following instructions execute a branch operation without a delay slot:
JMP
@Ri
CALL label12
CALL @Ri
RET
BRA label9
BNO
label9
BEQ
label9
BNE
label9
BC
label9
BNC
label9
BN
label9
BP
label9
BV
label9
BNV
label9
BLT
label9
BGE
label9
BLE label9
BGT
label9
BLS
label9
BHI
label9
● Operation explanation
In operation without a delay slot, the instructions are executed in the order in which they are specified.
The instruction placed immediately after the branch instruction is not executed before branching.
[Example]
;
Instruction list
ADD
R1, R2
;
BRA
LABEL ; Branch instruction (without a delay slot)
MOV
R2, R3
; Not executed
...
LABEL:
ST
R3,@R4 ; Branch destination
The number of execution cycles for a branch instruction without a delay slot is two when it branches,
and one when it does not.
Since no dummy instruction is placed in the delay slot, the instruction coding efficiency is better than
that of a branch instruction with a delay slot containing a NOP instruction.
Selecting an operation with a delay slot when an effective instruction can be placed in the delay slot and
selecting an operation without a delay slot otherwise can satisfy both execution speeds and coding
efficiency.
46
CHAPTER 3 CPU AND CONTROL BLOCK
3.9
EIT (Exception, Interrupt, and Trap)
EIT indicates that a program being executed is interrupted by an event and another
program is executed. EIT is a generic name for the words "exception", "interrupt", and
"trap".
■ EIT (Exception, Interrupt, and Trap)
An exception is an event that occurs in connection with the context of the current execution. The
process resumes from the instruction that has caused the exception.
An interrupt is an event that occurs regardless of the context of the current execution. The event is
caused by hardware.
A trap is an event that occurs in connection with the context of the current execution. Some traps such
as a system call are invoked by a program. The process resumes from the instruction following one that
has caused the trap.
■ EIT Characteristics
• Support of multiple interrupts
• Interrupt level mask function (The user can use 15 levels).
• Trap instruction (INT)
• EIT for emulator activation (hardware and software)
■ EIT Factors
The EIT factors are as follows:
• Reset
• User interrupt (internal resource or external interrupt)
• NMI
• Delayed interrupt
• Undefined-instruction exception
• Trap instruction (INT)
• Trap instruction (INTE)
• Step trace trap
• Coprocessor absent trap
• Coprocessor error trap
■ Return from EIT
The REIT instruction is used for the return from EIT.
47
CHAPTER 3 CPU AND CONTROL BLOCK
3.9.1
Interrupt Level
Interrupt level ranges from 0 to 31, and is managed using five bits.
■ Interrupt Level of EIT
The assignment of interrupt level is shown as follows:
Table 3.9-1 Interrupt Level
Level
Interrupt Factor
Binary
Decimal
00000B
...
00011B
0
...
3
(System reserved)
...
(System reserved)
00100B
4
INTE instruction
Step trace trap
00101B
...
01110B
5
...
14
(System reserved)
...
(System reserved)
01111B
15
NMI (for the user)
10000B
16
Interrupt
10001B
...
11110B
17
...
30
Interrupt
...
Interrupt
11111B
31
Notes
When the original value of ILM is in between 16
and 31, no value within this range can be set in
ILM by a program.
When ILM is set, user interrupts are forbidden.
-
-
When ICR is set, interrupts are forbidden.
Operation can be performed on level 16 to 31.
Undefined-instruction exceptions, coprocessor absent traps, coprocessor error traps, and INT
instructions are not affected by interrupt levels. Neither is ILM.
■ I Flag
The I flag specifies whether to enable or disable interrupts. It is provided as bit4 of CCR in the PS
register.
Value
48
Description
0
Disables interrupts.
This bit is cleared to "0" when INT instruction is executed
(The value before the bit is cleared is saved to the stack).
1
Enables interrupts.
The masking of an interrupt request is controlled according to the value held in ILM.
CHAPTER 3 CPU AND CONTROL BLOCK
■ Interrupt Level Mask (ILM)
ILM is a part of PS register (bit20 to bit16) and holds an interrupt level mask value.
Over the interrupt requests input to the CPU, only those with higher interrupt levels than the level
indicated by this ILM are accepted.
The values take 0 (00000B) for the maximum and 31 (11111B) for the minimum.
There are following restrictions for this value that a program can set. When the original value is in the
range from 16 to 31, a new value can be set within the range from 16 to 31. If an instruction that
specifies a value in the range from 0 to 15 is executed, a value (specified value + 16) is transferred.
When the original value is in the range from 0 to 15, any value from 0 to 31 can be set. Use an STILM
instruction to set the level to ILM register.
■ Level Mask for Interrupt/NMI
When an NMI or interrupt request is issued, the interrupt level (Table 3.9-1) of the interrupt factor is
compared with the level mask value of ILM. The interrupt request is masked and not accepted if the
following condition is satisfied:
Interrupt level held by the factor ≥ Level mask value.
49
CHAPTER 3 CPU AND CONTROL BLOCK
3.9.2
ICR (Interrupt Control Register)
The interrupt level for each interrupt request is set in the register within the interrupt
controller. ICRs are available for each interrupt request input. The ICR is mapped in the
I/O space and accessed via the bus from the CPU.
■ Interrupt Control Register (ICR)
Figure 3.9-1 shows the bit configuration of interrupt control register (ICR).
Figure 3.9-1 Bit Configuration of ICR
bit
7
-------
6
-------
5
-------
4
ICR4
R
3
ICR3
R/W
2
ICR2
R/W
1
ICR1
R/W
0
ICR0
R/W
Initial value
---11111B
[bit4] ICR4
This bit is always "1".
[bit3 to bit0] ICR3 to ICR0
The lower four bits of the interrupt level of the corresponding interrupt factor. The bits can be read and
written.
With those bits including bit4, ICR can express values ranging from 16 to 31.
■ ICR Mapping
Table 3.9-2 Interrupt Factor, Interrupt Control Register, and Interrupt Vector
Corresponding interrupt vector
Interrupt factor
Interrupt control register
Number
Address
Hexadecimal
Decimal
IRQ00
ICR00
00000440H
10H
16
TBR + 3BCH
IRQ01
ICR01
00000441H
11H
17
TBR + 3B8H
IRQ02
ICR02
00000442H
12H
18
TBR + 3B4H
...
...
...
...
...
...
...
...
...
...
...
...
IRQ45
ICR45
0000046DH
3DH
61
TBR + 308H
IRQ46
ICR46
0000046EH
3EH
62
TBR + 304H
IRQ47
ICR47
0000046FH
3FH
63
TBR + 300H
TBR initial value: 000F FC00H
Note: Refer to "CHAPTER 5 INTERRUPT CONTROLLER" for more details.
50
CHAPTER 3 CPU AND CONTROL BLOCK
3.9.3
SSP (System Stack Pointer)
The system stack pointer (SSP) is used to point to the stack to save and restore data
when EIT is accepted or a return operation occurs.
■ System Stack Pointer (SSP)
The system stack pointer (SSP) consists of 32 bits.
Figure 3.9-2 shows the bit configuration of system stack pointer (SSP).
Figure 3.9-2 Bit Configuration of SSP
bit
31
0
SSP
[Initial value]
00000000H
8 is subtracted from the stack pointer at the EIT processing, and 8 is added back to it at the returning
from the EIT in an RETI instruction execution.
The initial value after resetting is "00000000H".
SSP also functions as general-purpose register R15 when the S flag of the CCR is "0".
■ Interrupt Stack
The interrupt stack is the area specified by SSP. The PC and PS values are saved to it or restored from
it. After an interrupt is caused, the PC value is stored at the address indicated by the SSP, and the PS
value is stored at the address "SSP + 4".
Figure 3.9-3 Interrupt Stack
[Example]
SSP
[Before interrupt]
80000000H
[After interrupt]
SSP
7FFFFFF8H
Memory
80000000H
7FFFFFFCH
7FFFFFF8H
80000000H
7FFFFFFCH
7FFFFFF8H
PS
PC
51
CHAPTER 3 CPU AND CONTROL BLOCK
3.9.4
TBR (Table Base Register)
A register indicates the first address of the vector table for an EIT.
■ Table Base Register (TBR)
The table base register (TBR) consists of 32 bits.
Figure 3.9-4 shows the bit configuration of table base register (TBR).
Figure 3.9-4 Bit Configuration of TBR
bit
31
TBR
0
[Initial value]
000FFC00H
The address obtained by adding the offset value defined for each EIT factor and the TBR is the vector
address.
The initial value after resetting is "000FFC00H".
■ EIT Vector Table
The 1 Kbyte area beginning from the address indicated by TBR is EIT vector area.
Four bytes are assigned to each vector, and the relationship between the vector number and the vector
address is described below.
vctadr
= TBR + vctofs
= TBR + (3FCH - 4 × vct)
vctadr
: vector address
vctofs
: vector offset
vct
: vector number
The two lower bits of the addition result are always treated as "00B".
The area ranging from "000FFC00H" to "000FFFFFH" is the initial area of the vector table after
resetting.
Special functions are assigned to some vectors. Table 3.9-3 is the vector table in the architecture.
52
CHAPTER 3 CPU AND CONTROL BLOCK
Table 3.9-3 Vector Table (1 / 3)
Interrupt number
Interrupt factor
Interrupt level
Offset
TBR default address
00
----
3FCH
000FFFFCH
1
01
----
3F8H
000FFFF8H
System reserved
2
02
----
3F4H
000FFFF4H
System reserved
3
03
----
3F0H
000FFFF0H
System reserved
4
04
----
3ECH
000FFFECH
System reserved
5
05
----
3E8H
000FFFE8H
System reserved
6
06
----
3E4H
000FFFE4H
Coprocessor absent trap
7
07
----
3E0H
000FFFE0H
Coprocessor error trap
8
08
----
3DCH
000FFFDCH
INTE instruction
9
09
----
3D8H
000FFFD8H
System reserved
10
0A
----
3D4H
000FFFD4H
System reserved
11
0B
----
3D0H
000FFFD0H
Step trace trap
12
0C
----
3CCH
000FFFCCH
NMI request (tool)
13
0D
----
3C8H
000FFFC8H
Undefined-instruction exception
14
0E
----
3C4H
000FFFC4H
NMI request
15
0F
15 (FH) fixed
3C0H
000FFFC0H
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
Reload timer 0
24
18
ICR08
39CH
000FFF9CH
Reload timer 1
25
19
ICR09
398H
000FFF98H
Reload timer 2
26
1A
ICR10
394H
000FFF94H
UART0 (receive)
27
1B
ICR11
390H
000FFF90H
UART0 (send)
28
1C
ICR12
38CH
000FFF8CH
Maskable interrupt factor *2
29
1D
ICR13
388H
000FFF88H
Maskable interrupt factor *2
30
1E
ICR14
384H
000FFF84H
Maskable interrupt factor *2
31
1F
ICR15
380H
000FFF80H
Maskable interrupt factor *2
32
20
ICR16
37CH
000FFF7CH
Maskable interrupt factor *2
33
21
ICR17
378H
000FFF78H
Maskable interrupt factor *2
34
22
ICR18
374H
000FFF74H
Decimal
Hexadecimal
Reset *1
0
Mode vector *1
53
CHAPTER 3 CPU AND CONTROL BLOCK
Table 3.9-3 Vector Table (2 / 3)
Interrupt number
Interrupt factor
54
Interrupt level
Offset
TBR default address
23
ICR19
370H
000FFF70H
36
24
ICR20
36CH
000FFF6CH
Maskable interrupt factor *2
37
25
ICR21
368H
000FFF68H
Maskable interrupt factor *2
38
26
ICR22
364H
000FFF64H
Maskable interrupt factor *2
39
27
ICR23
360H
000FFF60H
Maskable interrupt factor *2
40
28
ICR24
35CH
000FFF5CH
Maskable interrupt factor *2
41
29
ICR25
358H
000FFF58H
Maskable interrupt factor *2
42
2A
ICR26
354H
000FFF54H
Maskable interrupt factor *2
43
2B
ICR27
350H
000FFF50H
Maskable interrupt factor *2
44
2C
ICR28
34CH
000FFF4CH
Maskable interrupt factor *2
45
2D
ICR29
348H
000FFF48H
Maskable interrupt factor *2
46
2E
ICR30
344H
000FFF44H
Time-base timer overflow
47
2F
ICR31
340H
000FFF40H
Maskable interrupt factor *2
48
30
ICR32
33CH
000FFF3CH
Maskable interrupt factor *2
49
31
ICR33
338H
000FFF38H
Maskable interrupt factor *2
50
32
ICR34
334H
000FFF34H
Maskable interrupt factor *2
51
33
ICR35
330H
000FFF30H
Maskable interrupt factor *2
52
34
ICR36
32CH
000FFF2CH
Maskable interrupt factor *2
53
35
ICR37
328H
000FFF28H
Maskable interrupt factor *2
54
36
ICR38
324H
000FFF24H
Maskable interrupt factor *2
55
37
ICR39
320H
000FFF20H
Maskable interrupt factor *2
56
38
ICR40
31CH
000FFF1CH
Maskable interrupt factor *2
57
39
ICR41
318H
000FFF18H
Maskable interrupt factor *2
58
3A
ICR42
314H
000FFF14H
Maskable interrupt factor *2
59
3B
ICR43
310H
000FFF10H
Maskable interrupt factor *2
60
3C
ICR44
30CH
000FFF0CH
Maskable interrupt factor *2
61
3D
ICR45
308H
000FFF08H
Maskable interrupt factor *2
62
3E
ICR46
304H
000FFF04H
Delay interrupt factor bit
63
3F
ICR47
300H
000FFF00H
System reserved (Used for REALOS)
64
40
----
2FCH
000FFEFCH
System reserved (Used for REALOS)
65
41
----
2F8H
000FFEF8H
System reserved
66
42
----
2F4H
000FFEF4H
System reserved
67
43
----
2F0H
000FFEF0H
System reserved
68
44
----
2ECH
000FFEECH
System reserved
69
45
----
2E8H
000FFEE8H
System reserved
70
46
----
2E4H
000FFEE4H
Decimal
Hexadecimal
Maskable interrupt factor *2
35
Maskable interrupt factor *2
CHAPTER 3 CPU AND CONTROL BLOCK
Table 3.9-3 Vector Table (3 / 3)
Interrupt number
Interrupt factor
Interrupt level
Offset
TBR default address
47
----
2E0H
000FFEE0H
72
48
----
2DCH
000FFEDCH
System reserved
73
49
----
2D8H
000FFED8H
System reserved
74
4A
----
2D4H
000FFED4H
System reserved
75
4B
----
2D0H
000FFED0H
System reserved
76
4C
----
2CCH
000FFECCH
System reserved
77
4D
----
2C8H
000FFEC8H
System reserved
78
4E
----
2C4H
000FFEC4H
System reserved
79
4F
----
2C0H
000FFEC0H
Used by INT instruction
80
to
255
50
to
FF
----
2BCH
to
000H
000FFEBCH
to
000FFC00H
Decimal
Hexadecimal
System reserved
71
System reserved
*1: Fixed addresses of "000FFFFCH" and "000FFFF8H" are always used for the reset vector and mode vector
respectively even when the TBR value is changed.
*2: The maskable interrupt factor is defined by each product model.
See "APPENDIX B Vector Table" for the vector table for this product model.
55
CHAPTER 3 CPU AND CONTROL BLOCK
3.9.5
Multiple EIT Processing
When multiple EIT factors occur concurrently, the CPU selects one EIT factor, accepts
it, executes the EIT sequence, and then detects next EIT factor. It repeats this operation
for all EIT factors.
When no more acceptable EIT factor is detected, the CPU executes the instruction of
the handler for the EIT factor accepted last. When multiple EIT factors occur
concurrently, the execution order of the handlers of individual factors is determined
according to the following two conditions:
• Priority for EIT factor acceptance
• Mode of masking other EIT factors after one is accepted
■ Priority for EIT Factor Acceptance
The priority of EIT factor acceptance is the order for selecting the factor executing an EIT sequence that
saves the PS and PC, updates the PC (on demand), and executes mask processing for other factors. The
handler of an EIT factor accepted earlier is not always executed in earlier time.
Table 3.9-4 lists the priority levels for acceptance of individual EIT factors.
Table 3.9-4 Priority for EIT Factor Acceptance and Masking Other Factors
Acceptance priority
Masking other event factors
1
Reset
The other factors are discarded.
2
Undefined-instruction exception
Cancel
INTE instruction
ILM = 4
The other factors are discarded.
4
INT instruction
I flag = 0
5
Coprocessor absent trap
Coprocessor error trap
6
User interrupt
ILM = Level of accepted factor
7
NMI (for user)
ILM = 15
8
NMI (for emulator)
ILM = 4
9
Step trace trap
ILM = 4
3
56
EIT factor
----
CHAPTER 3 CPU AND CONTROL BLOCK
With a consideration of mask processing for other factors after an EIT factor is accepted, the execution
order of handlers of the concurrent EIT factors is described as shown in Table 3.9-5.
Table 3.9-5 EIT Handler Execution Order
Handler execution order
Factor
1
Reset *
2
Undefined-instruction exception
3
INTE instruction *
4
Step trace trap
5
NMI (for user)
6
INT instruction
7
User interrupt
8
Coprocessor absent trap, coprocessor error trap
*: Other factors are discarded.
[Example]
Figure 3.9-5 Multiple EIT Processing
Main routine
NMI handler
INT instruction
handler
Priority
(High) NMI occurrence
(Low) INT instruction execution
(1) Executed first
(2) Executed next
57
CHAPTER 3 CPU AND CONTROL BLOCK
3.9.6
Operation of EIT
This section explains the operation of EIT.
■ Operation of EIT
The transfer source "PC" appearing in the following explanation indicates the address of the instruction
that has detected an EIT factor.
"Next instruction address" is defined according to the instruction that detected EIT as follows:
• LDI: 32 ...... PC + 6
• LDI: 20, COPOP, COPLD, COPST, COPSV ...... PC +4
• Other instructions ...... PC + 2
● Operation for User Interrupt and NMI
When a user interrupt or user NMI interrupt request has been issued, the system determines whether to
accept the request in the following order:
[Checking whether to accept an interrupt request]
(1) The interrupt levels of the requests issued concurrently are compared, and the request having the
highest level (smallest numeric value) is selected. For maskable interrupts, the values held by the
corresponding ICRs are used for the level comparison. For NMI, the constants defined in
advance are used.
(2) When multiple interrupt requests have the same level, the interrupt request having the smallest
interrupt number is selected.
(3) When the interrupt level equals or exceeds the level mask value, the interrupt request is masked
and not accepted.
When the interrupt level is less than the level mask value, proceed to step (4).
(4) If the I flag is "0" and the selected interrupt request is a maskable interrupt, the interrupt request
is masked and not accepted. If the I flag is "1", proceed to step (5). When the selected interrupt
request is an NMI, proceed to step (5) regardless of the I flag value.
(5) If the above conditions are satisfied, the interrupt request is accepted at the end of the current
instruction operation.
If a user interrupt or NMI request is accepted when an EIT request is detected, the CPU, using the
interrupt number corresponding to the accepted interrupt request, operates as follows:
( ) in [Operation] represent the address indicated by the register.
[Operation]
58
(1) SSP - 4
→
SSP
(2) PS
→
(SSP)
(3) SSP - 4
→
SSP
(4) Next instruction address
→
(SSP)
(5) Interrupt level of accepted request
→
ILM
CHAPTER 3 CPU AND CONTROL BLOCK
→
(6) "0"
(7) (TBR + vector offset of accepted interrupt request) →
S flag
PC
Before executing the first instruction of the handler after the end of an interrupt sequence, the CPU tries
to detect another EIT. If another acceptable EIT is detected, the CPU proceeds to an EIT processing
sequence.
● Operation for INT Instruction
INT #u8
The process branches to the interrupt handler of the vector indicated by u8.
[Operation]
(1) SSP - 4
→
SSP
(2) PS
→
(SSP)
(3) SSP - 4
→
SSP
(4) PC + 2
→
(SSP)
(5) "0"
→
I flag
(6) "0"
→
S flag
(7) (TBR + 3FCH - 4 × u8)
→
PC
● Operation for INTE Instruction
INTE
The process branches to the interrupt handler for the vector with vector number #9.
[Operation]
(1) SSP - 4
→
SSP
(2) PS
→
(SSP)
(3) SSP - 4
→
SSP
(4) PC + 2
→
(SSP)
(5) "00100B"
→
ILM
(6) "0"
→
S flag
(7) (TBR + 3D8H)
→
PC
Avoid to use an INTE instruction in another INTE instruction or a step trace trap processing routine.
INTE does not generate EIT during the step execution.
● Operation for Step Trace Trap
When T flag of the SCR in the PS is set to enable step trace functions, a trap occurs every time an
instruction is executed, resulting in a break.
[Conditions under which a step trace trap is detected]
(1) T flag = 1
(2) Instruction other than a delayed branch instruction
59
CHAPTER 3 CPU AND CONTROL BLOCK
(3) During an execution of processing routine other than an INTE instruction or a step trace trap.
(4) If the above conditions are satisfied, a break occurs at the end of the current instruction
operation.
[Operation]
(1) SSP - 4
→
SSP
(2) PS
→
(SSP)
(3) SSP - 4
→
SSP
(4) Next instruction address
→
(SSP)
(5) "00100B"
→
ILM
(6) "0"
→
S flag
(7) (TBR + 3CCH)
→
PC
After the T flag is set to enable the step trace trap, user NMIs and user interrupts are forbidden. The
INTE instruction does not generate EIT, either.
For the FR family, a trap occurs from the next instruction on which the T flag is set.
● Operation for Undefined Instruction Exception
If undefined instruction is found during instruction decoding, an undefined instruction exception occurs.
[Conditions under which the undefined instruction exception is detected]
• The instruction is found undefined during instruction decoding.
• The instruction is placed at a location other than a delay slot (Not immediately after a delayed
branch instruction).
• If the above conditions are satisfied, an undefined instruction exception occurs and results in a break.
[Operation]
(1) SSP - 4
→
SSP
(2) PS
→
(SSP)
(3) SSP - 4
→
SSP
(4) PC
→
(SSP)
(5) "0"
→
S flag
(6) (TBR + 3C4H)
→
PC
The value saved to PC is the address of the instruction that has detected the undefined-instruction exception.
● Coprocessor Absent Trap
If a coprocessor instruction that attempts to use a coprocessor that is not installed is executed, a
coprocessor absent trap occurs.
[Operation]
60
(1) SSP - 4
→
SSP
(2) PS
→
(SSP)
(3) SSP - 4
→
SSP
CHAPTER 3 CPU AND CONTROL BLOCK
(4) Next instruction address
→
(SSP)
(5) "0"
→
S flag
(6) (TBR + 3E0H)
→
PC
● Coprocessor Error Trap
If an error occurs while a coprocessor is used, a coprocessor error trap occurs at the execution of a next
coprocessor-instruction that uses the coprocessor.
[Operation]
(1) SSP - 4
→
SSP
(2) PS
→
(SSP)
(3) SSP - 4
→
SSP
(4) Next instruction address
→
(SSP)
(5) "0"
→
S flag
(6) (TBR + 3DCH)
→
PC
● Operation for RETI Instruction
The RETI instruction is used to return from the EIT processing routine.
[Operation]
(1) (R15)
→
PC
(2) R15 + 4
→
R15
(3) (R15)
→
PS
(4) R15 + 4
→
R15
The RETI instruction must be executed while the S flag is "0".
■ Note on Delayed Slot
The delayed slot for branch instruction has restrictions related with EIT.
Refer to section "3.8 Branch Instruction of the CHAPTER 3 CPU AND CONTROL BLOCK".
61
CHAPTER 3 CPU AND CONTROL BLOCK
3.10
Operation Mode
Operation modes of the MB91245/S series are divided into bus modes and access
modes.
■ Operation Mode
Two operation modes, bus mode and access mode, are available.
Bus mode
Access mode
Single chip
Internal ROM external bus
External ROM external bus
16-bit bus width
8-bit bus width
● Bus Mode
In bus mode, the operations of internal ROM and external access functions are controlled. The mode
pins (MD2, MD1, and MD0), and contents of the ROMA bit in the mode data are used for the control of
this mode.
● Access Mode
In access mode, external data bus width is controlled. The WTH1 and WTH0 bits in the mode data and
DBW1 and DBW0 bits in the ACR0 to ACR3 (Area Configuration Register) are used for the control of
this mode.
■ Bus Mode
For the FR family, the following three bus modes are available.
Refer to section "3.2 Memory Map" for details.
● Bus Mode 0 (Single Chip Mode)
The mode in which the accesses to the internal I/O, internal RAM, and internal ROM are enabled and
those to others are disabled. The external pins are served as peripheral resources or general-purpose
ports. They do not function as bus pins.
● Bus Mode 1 (Internal - ROM - External Bus Mode)
The mode in which the accesses to the internal I/O, internal RAM, and internal ROM are valid and the
accesses to those areas accessible to the external area become accesses to the external spaces. Some of
the external pins function as bus pins.
● Bus Mode 2 (External - ROM - External Bus Mode)
The mode in which the accesses to the internal ROM is invalid and the internal I/O and internal RAM
are valid, and the accesses to those areas accessible to the external area and internal ROM area become
accesses to the external spaces.
Some of the external pins function as bus pins.
62
CHAPTER 3 CPU AND CONTROL BLOCK
■ Setting the Mode
For the FR family, operation mode is selected by setting the mode pins (MD2, MD1, and MD0) and
mode data.
● Mode Pins
Use three pins (MD2, MD1, and MD0) to set for the mode vector and reset vector fetch.
The configuration other than those shown in the table are forbidden.
Mode pins
MD2, MD1, MD0
Mode name
Reset vector
access area
0 0 0B
Internal ROM mode vector
Internal
0 0 1B
External ROM mode vector
External
● Mode Data
Data that the CPU writes in the mode register (MODR) by mode vector fetch (Refer to section "3.11.4
Reset Operation in the 3.11 Reset (Device Initialization)" for details) is called mode data.
After mode data is set to this register, the CPU operates based on the mode set to the register.
Mode data can be set based on all the reset factors. It cannot be set from the user program.
Figure 3.10-1 Detailed Explanation of Mode Data
bit
31
30
29
28
27
26
25
24
0
0
0
0
0
ROMA
WTH1
WTH0
Operation mode setting bits
[bit31 to bit27] reserved bits
Be sure to set these bits to "00000B". Otherwise, the operation is not guaranteed.
[bit26] ROMA (Internal ROM enabling bit)
This bit specifies whether to enable internal ROM area.
ROMA
0
1
Function
Remarks
External ROM mode
Internal F-bus RAM is enabled, and the internal ROM area (80000H to
100000H) becomes an external area.
Internal ROM mode
Internal ROM area is enabled.
63
CHAPTER 3 CPU AND CONTROL BLOCK
[bit25, bit24] WTH1, WTH0 (bus width setting bits)
Specify the bus width for the external bus mode.
In the external bus mode, this value is set to DBW1 and DBW0 bits in ACR0 (CS0 area).
WTH1
WTH0
Function
0
0
8-bit bus width
0
1
16-bit bus width
1
0
----
1
1
Single chip mode
Note:
Mode data to be set to the mode vector must be placed in "000FFFF8H" as byte data. Since big
endian is used for byte endian in the FR family, mode data should be placed in the most significant
byte, from bit31 to bit24 as shown in the diagram below.
Figure 3.10-2 Note on Mode Data
bit
24
23
16
15
8
7
0
000FFFF8H
XXXXXXXX
XXXXXXXX
XXXXXXXX
Mode Data
Correct
000FFFF8H
Mode Data
XXXXXXXX
XXXXXXXX
XXXXXXXX
000FFFFCH
64
31
Wrong
Reset Vector
CHAPTER 3 CPU AND CONTROL BLOCK
3.11
Reset (Device Initialization)
When reset occurs, the CPU immediately suspends the active process and stands by
for reset cancellation. After reset is canceled, the process starts from the address
specified by the reset vector.
There are 4 factors that cause reset.
• Watchdog timer overflow
• CPU operation detection function counter overflow
• Reset request from external reset pin
• Software reset request
Table 3.11-1 shows the reset factors.
Table 3.11-1 Reset Factor
Wait for oscillation stabilization
Reset
Factor
Internal
generation
timing
Reset
level
Main
oscillation
stop
Stop
mode
Others
External pin
Input "L" to INITX pin
Synchronization
Setting
initialization reset
(INIT)
Yes
Yes
No
Software
reset
Write "0" in the SRST bit of
the standby control register
(STCR)
Synchronization
Setting
initialization reset
(INIT)
Yes
-
No
Watchdog timer
Watchdog timer overflow
Synchronization
Setting
initialization reset
(INIT)
Yes
-
No
CPU operation
detection
CPU operation detection
counter overflow
Synchronization
Setting
initialization reset
(INIT)
Yes
-
No
When a reset factor occurs, the oscillation clock frequency divided by two is used as the machine clock frequency.
65
CHAPTER 3 CPU AND CONTROL BLOCK
● External reset
In the case of an external reset, a reset occurs when "L" level is input into the external reset (INITX) pin.
When turning on the power supply, set the INITX pin input level at "L" to perform a setting initialization
reset (INITX). In addition, immediately after turning on the power, in order to secure an oscillation
stabilization wait time for the oscillation circuit, continue a "L" level input to the INITX pin for the length
of stabilization wait time required by the oscillation circuit.
● Software reset
In the case of a software reset, an internal reset occurs when "0" is written in the SRST bit of the standby
control register (STCR).
● Watchdog reset
In the case of the watchdog reset, if "A5H" and "5AH" are not written continuously into the watchdog reset
generation delay register (WPR) within the designated time after the watchdog timer is started, a watchdog
reset occurs due to a watchdog timer overflow.
● CPU operation detection reset
In the case of the CPU operation detection reset, after power is turned on, if "0" is not written on the CL bit
of the low voltage/CPU operation detection reset control register (LVRC) within the designated time, a
reset occurs due to a CPU operation detection counter overflow.
Note:
When turning on a power supply, for reset factors other than those caused by a drop in voltage, if the
reset factor occurs during the write operation (during a transfer instruction execution), upon
completion of the instruction it stands by for reset cancellation. For this reason, even if a reset was
input during a write operation, it is completed properly. However, Load-multi (LDM), Store-multi
(STM) instructions accept a reset before the transfer of the designated register is completed,
therefore it is not guaranteed that all of the data will be transferred.
66
CHAPTER 3 CPU AND CONTROL BLOCK
3.11.1
Reset Factor and Oscillation Stabilization Wait Time
There are 4 types of reset factor, and the oscillation stabilization wait time differs
depending on the reset factor.
■ Reset Factor and Oscillation Stabilization Wait Time
The reset factors and the oscillation stabilization wait time are shown in Table 3.11-2.
Table 3.11-2 Reset Factor and Oscillation Stabilization Wait Time
Oscillation stabilization wait time
Reset
Factor
Main oscillation stop
Stop mode
Others
External pin
Input "L" to INITX pin
OS bit setting value
OS bit setting value
No
Software
reset
Write "0" in the SRST bit of the
standby control register (STCR)
OS bit setting value
-
No
Watchdog timer
Watchdog timer overflow
OS bit setting value
-
No
CPU operation detection
CPU operation detection counter
overflow
OS bit setting value
-
No
The oscillation stabilization wait time is secured by setting the OS (Oscillation Stabilization time select)
bits in the standby control register (STCR).
Setting for OS1, OS0 and the oscillation stabilization wait time are shown in Table 3.11-3.
Table 3.11-3 Oscillation Stabilization Wait Time on the Setting of the Standby Control Register (STCR)
OS1
OS0
Oscillation stabilization wait
time
When main oscillation is
4MHz
When sub-oscillation is
32.768kHz
(φ/2 cycle)
0
0
φ × 21 [Initial value]
1μs
61μs
0
1
φ × 211
1.024ms
62.5ms
1
0
φ × 216
32.768ms
2s
1
1
φ × 214
8.192ms
0.5s
Definition of clock φ: internal base clock cycle, and also two times of the main oscillation cycle
Note:
Oscillators made of ceramic, crystal, etc. require an oscillation stabilization wait time from a few
milliseconds to some tens of milliseconds in general after starting oscillation, to stabilize itself on its
inherent oscillation frequency. Therefore, set the value in accordance to the oscillator used.
Products with S suffix do not support sub clock.
67
CHAPTER 3 CPU AND CONTROL BLOCK
■ Concerning the Oscillation Stabilization Wait Time at the Time of Power-on
Upon power-on, set the input level of the INITX pin to "L". Ensure that the following is achieved: "L"level input period upon power-on ≥ (Oscillation time of oscillator) + (10 × base clock) + 12μs
(Stabilization wait time of internal voltage step-down circuit). As a result, the above settings ensure the
power-onstabilization wait time (217 × base clock) for the internal circuit automatically. Then, the
device sets the value in the OS bit as the oscillation stabilization wait time.
Figure 3.11-1 Dependency Diagram of External Reset and Internal Operations
(Power-on wait time > INITX "L" period (recommended))
Vcc
CLK
INITX
a
b
CPU operation
a : Oscillation time of oscillator
b : 10 x base clock + 12μs
Power on
stabilization
wait time
Oscillation
stabilization
wait time
Figure 3.11-2 Dependency Diagram of External Reset and Internal Operations
(Power-on wait time > INITX "L" period (recommended))
Vcc
CLK
INITX
a
b
CPU operation
a : Oscillation time of oscillator
b : 10 x base clock + 12μs
Power on
stabilization
wait time
Oscillation
stabilization
wait time
■ Concerning Recovery by the INITX Pin during Stop Mode
In the case of recovery by the INITX pin during stop mode, be sure that the "L" level input time to the
INITX pin is 12μs or more (After the reset is canceled, it will wait the length of time set on the OS bit
before recovering).
68
CHAPTER 3 CPU AND CONTROL BLOCK
3.11.2
Reset Level
The reset operations of FR60Lite devices are divided into two levels, each of which has
different generation triggers and initialization processes. This section describes each
reset level.
■ Setting Initialization Reset (INIT)
This is the highest-level reset that initializes all configuration.
Reset by an external pin input, a watchdog reset, a software reset, and a CPU operation detection have the
reset level of setting initialization reset (INIT). When a setting initialization reset (INIT) occurs, an
operation initialization reset (RST) also occurs at the same time.
A setting initialization reset (INIT) initializes the following.
• Operation mode of the device (bus mode and external bus width setting)
• Configuration for clock generation/control
- Clock source selection (CLKS: main clock frequency divided by two)
- Clock division setting (peripheral: × 4, CPU: × 1, external bus: × 1)
- Watchdog timer interval (WT1, WT0: 216 × base clock interval)*1
- Oscillation stabilization wait time (OS1, OS0: 21 × base clock interval)*2
- Oscillation stopped during stop (OSCD1: main clock oscillation is stopped during stop)
- Time-base timer interrupt (TBIE: disabled)
- Main PLL multiplication rate (PLL1S: × 1)
- PLL operation permission (PLL1E: PLL stopped)
• All configuration related to the CS0 area of the external bus
- Area selection register (ASR0: start address "0")
- Area size (ASZ: 512 Kbytes)
- Data bus width (The value of the mode data will be reflected).
- Write enabled (WEN: write protect)
- Access type (TYP: Normal access, use WR0X, WR1X pin as write strobe, WRX is fixed at "H", and WAIT
insertion by the RDY pin has no effect)
• The pin status control bit during stop is HIZ=1: Hi-Z state.
• All the setting initialized by an operation initialization reset (RST)
*1: Setting initialization reset (INIT) generation causes the watchdog timer to stop and it will not function
until it is started again by program operation.
*2: It is only initialized during power-on.
69
CHAPTER 3 CPU AND CONTROL BLOCK
■ Operation Initialization Reset (RST)
The normal level reset that initializes the program operation is called the operation initialization reset
(RST).
When a setting initialization reset (INIT) occurs, an operation initialization reset (RST) also occurs at the
same time.
An operation initialization reset (RST) initializes the following.
• Program operation
• CPU and internal bus
• Configuration for clock generation/control
- Watchdog timer interval (WT1, WT0: 216 × base clock interval)
- Time-base timer interrupt (TBIE: disabled)
• Register setting value of the peripheral circuit
• I/O port setting
• Operation mode of the device (bus mode and external bus width setting)
70
CHAPTER 3 CPU AND CONTROL BLOCK
3.11.3
External Reset Pin
The external reset pin (INITX pin) is a pin dedicated to reset an input and an internal
reset occurs when "L" level is input to this pin. Reset is conducted in synchronization
with the machine clock; however, the external pin is reset asynchronously.
■ Block Diagram of External Reset Pin
Figure 3.11-3 Block Diagram of Internal Reset
Machine clock
(PLL multiplication circuit, HCLK divided by two)
INITX
P-ch
Pin
P-ch
Synchronization
circuit
N-ch
Clock synchronized
Internal reset signal
Input buffer
In order to prevent a memory corruption due to a reset during a write operation, the initialization
operation of the internal circuit by the INITX pin input is conducted at a cycle that does not corrupt the
memory. In addition, the clock is necessary to initialize the internal circuit. In order to operate with the
external clock, the clock input is necessary during a reset input.
■ External Pin Reset Timing
Each external pin is reset asynchronously for the external reset INITX pin input.
71
CHAPTER 3 CPU AND CONTROL BLOCK
3.11.4
Reset Operation
When a reset is canceled, the mode data and reset vector are read from the location
specified by the mode pin setting, and a mode fetch will be conducted. With the mode
fetch, the CPU operation mode and the execution start address after the reset operation
are determined. After power is turned on, recovery from stop by reset conducts a mode
fetch after the oscillation stabilization wait time has elapsed.
■ Overview of Reset Operation
The reset operation flow is shown in Figure 3.11-4.
Figure 3.11-4 Reset Operation Flow
External reset at power-on
External reset
Software reset
Watchdog timer reset
CPU operation detection reset
During reset
Stop
Main oscillation
Oscillation stabilization wait
reset status
Operation
Mode data fetch
Mode fetch
(Reset Operation)
Normal operation
(RUN status)
72
Reset vector fetch
Read the instruction code from the address designated
by the reset vector and execute command.
CHAPTER 3 CPU AND CONTROL BLOCK
■ Mode Pins
Mode pins (MD0 to MD2) designate the import method for the reset vector and mode data. The reset vector
and mode data import are conducted in a reset sequence. Refer to section "■Setting the Mode" for details
concerning mode pins.
■ Mode Fetch
When a reset is canceled, the CPU imports the reset vector and mode data into the relevant register within
the CPU core. The reset vector and mode data are allocated to "FFFFCH" and "FFFF8H" respectively. The
CPU outputs these addresses to the internal bus immediately after reset is canceled and imports the reset
vector and mode data. With this mode fetch, the CPU starts the process from the address designated by the
reset vector.
73
CHAPTER 3 CPU AND CONTROL BLOCK
3.11.5
Reset Factor Bit
Reset generation factors can be identified by reading the watchdog timer control
register (RSRR).
■ Reset
There is a flip-flop that corresponds to each reset factor, as shown in Figure 3.11-5. These contents can be
obtained by reading the watchdog timer control register (RSRR). If it is necessary to identify the reset
generation factor after a reset cancellation, be sure to process the read value of the watchdog timer control
register (RSRR) by software and branch to the appropriate program.
Figure 3.11-5 Block Diagram of Reset Factor Bit
No periodic clear
CPU operation
detection reset
request detection circuit
INITX pin
RST bit set
No periodic clear
External reset
request
detection circuit
Watchdog
timer control
register
(RSRR)
System base
clock
D
Q
F/F
CL
CK
D
CL
F/F
Q CK
Watchdog
timer reset
detection circuit
RST bit
write detection
circuit
D
CL
F/F
Q
CK
Q
D
PR
Power-on
reset
F/F
CK
Watchdog timer
control register
(RSRR) read
Internal data bus
74
CHAPTER 3 CPU AND CONTROL BLOCK
■ Correspondence between Reset Factor Bit and Reset Factor
The configuration of bits of the watchdog timer control register (RSRR) is shown in Figure 3.11-6 and the
correspondence of the bit value to the reset factor is shown in Table 3.11-4. For more information, refer to
section "3.12 Clock Generation Control".
Figure 3.11-6 Configuration of Reset Factor Bit (Standby Control Register)
Address
0000480H
R
-
bit15
bit14
PON
R
---R
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
WDOG ERST
R
R
SRST
R
---R
WT1
R
WT0
R
10000000B
: Read only
: Undefined bit
Table 3.11-4 Correspondence between Reset Factor Bit Contents and Reset Factor
Reset factor
PON
WDOG
ERST
SRST
Reset factors from power-on reset
1
*1
*1
*1
Generation of reset request due to watchdog timer overflow
*1
1
*1
*1
External reset request from INITX pin,
Generation of the CPU operation detection reset request*2
*1
*1
1
*1
Generation of software reset request
*1
*1
*1
1
*1 : Retains the previous status
*2 : If CPU operation detection reset request occurs, CPUF bit of CPU operation detection reset control
register (LVRC) is set to "1".
75
CHAPTER 3 CPU AND CONTROL BLOCK
■ Notes on Reset Factor Bit
● If several reset factors occur
If several reset factors occur, each corresponding reset factor bit of the watchdog timer control register
(RSRR) is set to "1". For example, if the generation of external reset request from the INITX pin and a
watchdog timer overflow occur at the same time, both the ERST bit and the WDOG bit are set to "1".
● Clear reset factor bit
The reset factor bit is cleared only when the watchdog timer control register (RSRR) is read. The flag bit
corresponding to each reset factor is not cleared even when another reset occurs from some other factor (it
remains set to "1").
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CHAPTER 3 CPU AND CONTROL BLOCK
3.11.6
Oscillation Stabilization Waiting Factor
This section describes the oscillation stabilization waiting factors.
■ During Reset (INIT) Cancellation
Immediately after the reset caused by various factors is canceled, it transits to the oscillation stabilization
waiting state.
In the initial time during PON, the oscillation stabilization wait time is set to the minimum value, therefore
a sufficient stabilization wait time should be secured by the input width of the INITX pin. In addition, a
watchdog reset for when the main oscillation is not stopped during main run or sub run does not require an
oscillation stabilization wait time. An oscillation stabilization wait time is required in a watchdog reset only
"■ When Watchdog Reset Occurs while Main Oscillation is Stopped in Sub Run".
■ During Recovery from Stop Mode
Immediately after a stop mode is canceled, it transits to an oscillation stabilization waiting state.
However, if it is canceled due to a reset (INIT) request, it transits to a reset (INIT) state and after the reset
(INIT) is canceled, it transits to the oscillation stabilization waiting state.
After the oscillation stabilization wait time has elapsed, it transits to the state that corresponds to the factor
that canceled the stop mode.
During recovery caused by the generation of valid external interrupt request input or main oscillation
stabilization waiting timer interrupt, it transits to a normal operation state.
■ During Recovery from Abnormal State when Selecting PLL
When PLL is operating as the source clock, if some kind of error (*) occurs in the PLL control, an
oscillation stabilization wait time is necessary to secure the PLL lock time. Please deal with this using
software.
After the oscillation stabilization wait time has passed, it transits to the normal operation state.
*: Multiplication rate change during use of PLL, generation of PLL operation enable bit error, etc.
■ When Watchdog Reset Occurs while Main Oscillation is Stopped in Sub Run
When the sub clock is operating as the source clock and a watchdog reset occurs while the main oscillation
is stopped by the bit0: OSCDS1 bit of the OSCCR (main oscillation control register), it transits to
oscillation stabilization wait state immediately after reset (INIT) is canceled. After the oscillation
stabilization wait time (*) has elapsed, it transits to normal operation state.
*: The setting of the oscillation stabilization wait time is not initialized and is conducted at the set value.
Products with S suffix do not support sub clock.
77
CHAPTER 3 CPU AND CONTROL BLOCK
3.12
Clock Generation Control
The generation and control of each type of clock signal are described below.
■ Clock Generation Control
Internal operation clocks of this product class are generated in the following manners.
• Generating a base clock:
Divide the source clock by two or use the PLL oscillation to generate a
base clock.
• Generating internal clocks: Divide the base clock to generate the operating clock to be supplied to
various parts of the device.
The generation and control of these clocks are described as follows.
For the detailed explanation of registers and flags in each description, refer to section "3.12.6 Block
Diagram of Clock Generation Control Unit" and section "3.12.7 Detailed Description of Register of Clock
Generation Control Unit".
78
CHAPTER 3 CPU AND CONTROL BLOCK
3.12.1
Selecting a Source Clock
This section explains the selection of a source clock.
■ Selecting a Source Clock
An oscillator is connected to the external oscillation pins (X0/X1 and X0A/X1A), and the source oscillation
generated in the internal oscillation circuit is used as the source clock.
All the clock sources including the external bus clock constitute this product class itself.
Two types of clocks i.e. the main clock and the sub clock are available for an external oscillation pin and
the internal oscillation circuit, and they can be used by arbitrarily switching over during the operation.
•
Main clock: Generated from the X0/X1 pin input and designed to be used as a high speed clock.
•
Sub clock:
Generated from the X0A/X1A pin input and designed to be used as a low speed clock.
Generate the system base clock using either of the following source clocks.
• Main clock divided by two
• Main clock multiplied by PLL
• Sub clock itself
The source clock selection control is conducted according to the setting of CLKR (clock source control
register).
Note:
Products with S suffix do not support sub clock.
79
CHAPTER 3 CPU AND CONTROL BLOCK
3.12.2
PLL Control
With the PLL oscillation circuit for the main clock, it is possible to enable/disable the
operation (oscillation) and control the multiplication ratio setting.
Each control is conducted according to the setting of CLKR (clock source control
register).
Each control details are described as follows.
■ Enable PLL Operation
Enabling/disabling the main PLL oscillation operation is conducted according to the setting of bit10
(PLL1EN bit) of CLKR (clock source control register).
● PLL Control
The PLL1EN bit is initialized to "0" after the setting initialization reset (INIT), and the oscillation operation
of the main PLL is stopped. While it is stopped, the main PLL output cannot be selected as the source
clock.
After starting the program operation, first set the multiplication ratio of the main PLL that is used as the
clock source and enable the operation, and then switch over the source clock after the PLL lock wait time
has elapsed. For the PLL lock wait time in this case, it is recommended that you use a time-base timer
interrupt.
While selecting the main PLL output as the source clock, you cannot stop PLL. Writing into the register is
disabled. When you want to stop PLL when transiting to the stop mode, stop PLL after having the source
clock reselected to be the main clock divided by two.
If the oscillation during the stop mode is set to be stopped with bit0 (OSCD1 bit) of STCR (standby control
register), it is not necessary specifically to set the stop of operation because PLL automatically stops when
transiting to the stop mode. Then, while returning from the stop mode, PLL automatically starts the
oscillation operation.
80
CHAPTER 3 CPU AND CONTROL BLOCK
■ PLL Multiplier
The main PLL multiplier is set according to bit14 to bit12 (PLL1S2 to PLL1S0) bit of CLKR (clock source
control register).
● PLL Multiplier
All bits are initialized to "0" after the setting initialization reset (INIT).
To change the PLL multiplier setting from the initial value, set it before or simultaneously with enabling
the operation of PLL after starting the program operation. Once you have changed the multiplier ratio,
switch over the source clock after the lock wait time has elapsed. For the PLL lock wait time in this case, it
is recommended that you use the time-base timer interrupt.
To change the PLL multiplier setting during the operation, change it after switching the source clock to one
other than PLL. Once you have changed the multiplier ratio, switch over the source clock after the lock
wait time has elapsed as described above.
81
CHAPTER 3 CPU AND CONTROL BLOCK
3.12.3
Oscillation Stabilization Wait/PLL Lock Wait Time
If the clock you select as the source clock is not in the state of operational stability,
waiting the oscillation stabilization time is required (Refer to section "3.11.6 Oscillation
Stabilization Waiting Factor").
For PLL, after the activation of the operation, a lock wait time is required in order that
the output stabilizes enough to meet the set frequency.
■ Oscillation Stabilization Wait/Main PLL Lock Wait Time
The wait time for each case is described as follows.
● Wait time after power on
After power on, the oscillation stabilization wait time for oscillation circuit for the main clock will be
first required.
Since the setting for the oscillation stabilization wait time is initialized to the maximum value when
power is on, the oscillation stabilization wait time for the oscillation circuit for the main clock is
secured.
The operation for PLL is not enabled in this status, so it is not necessary to take into account the lock
wait time here.
● Wait time after the setting initialization
Once the setting initialization reset (INIT) is canceled, it transits to the oscillation stabilization wait
status. Here the set oscillation stabilization wait time is generated internally.
The operation for PLL is not enabled in this status, so it is not necessary to take into account the lock
wait time here.
● Wait time after enabling the PLL operation
If you enable the operation for PLL while it is in stop state after the program operation starts, do not use
the PLL output unless the lock wait time has elapsed.
If the main PLL is not selected as the source clock, the program operation is executable even during the
lock wait time. For the PLL lock wait time in this case, it is recommended that you use the time-base
timer interrupt.
● Wait time after changing PLL multiplier
Even if you change the setting of the multiplier of PLL which was in operating state after the program
operation started, do not use the PLL output unless the lock wait time has elapsed.
If the main PLL is not selected as the source clock, program operations are executable even during the
lock wait time. For the PLL lock wait time in this case, it is recommended that you use time-base timer
interrupt.
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CHAPTER 3 CPU AND CONTROL BLOCK
● Wait time after returning from the stop mode
During the return from the stop mode after the program started, the oscillation stabilization wait time set
by the program is generated internally.
In the case of the setting where you stop the oscillation circuit for the clock that is selected as the source
clock during the stop mode, you will need the oscillation stabilization wait time for that oscillation
circuit or the lock wait time for the PLL you are using, whichever is longer. Before transiting to the stop
mode, be sure to set the oscillation stabilization wait time which is longer than the other.
83
CHAPTER 3 CPU AND CONTROL BLOCK
3.12.4
Clock Distribution
Generates the operation clocks respectively for each function based on the base clock
generated from the source clock.
There are three types of internal operation clock in total, and each can set a division
ratio independently.
Each internal operation clock is described as follows.
■ CPU Clock (CLKB)
This clock is used for the CPU, the internal memory and the internal bus.
Circuits that use this clock include the following items.
• CPU
• Built-in RAM, Built-in ROM
• Bit search module
• I-bus, D-bus, F-bus, X-bus
• DMA controller
• On chip Debug Support Unit (DSU)
Do not set a combination of a multiplication ratio and a division ratio that brings a frequency exceeding the
maximum operable frequency.
■ Peripheral Clock (CLKP)
This clock is used for peripheral resources and the peripheral bus.
Circuits that use this clock include the following items.
• Peripheral bus
• Clock control unit (bus interface part only)
• Interrupt controller
• I/O port
• Peripheral resource such as external interrupt input, UART, 16-bit timer
Do not set the combination of a multiplication ratio and a division ratio that brings a frequency exceeding
the maximum operable frequency.
■ External Bus Clock (CLKT)
This clock is used for the external expansion bus interface.
Circuits that use this clock include the following items.
• External expansion bus interface
• External CLK output
Do not set the combination of a multiplication ratio and a division ratio that brings a frequency exceeding
the maximum operable frequency.
84
CHAPTER 3 CPU AND CONTROL BLOCK
3.12.5
Clock Division
Each internal operation clock can independently set a division ratio from the base clock.
This function allows you to set the optimal operation frequency for each circuit.
■ Clock Division
The division ratio is set by DIVR0 (base clock division setting register 0) and DIVR1 (base clock division
setting register 1). Each register has four bits corresponding to each clock as the setting bits, and (register
set value + 1) is the division ratio for the base clock of the clock. Even if the division ratio setting is odd
number, the duty ratio is always 50%.
If a setting value is changed, the division ratio changed from the rising of the next clock pulse after the
setting will be valid.
The division ratio setting is not initialized in the occurrence of an operation initialization reset (RST) and
the setting before the reset occurrence will be retained. It is only initialized by the occurrence of the setting
initialization reset (INIT). Be sure to set the division ratio before changing the source clock from the initial
state to the high speed one.
In the combination of source clock selections, the main PLL multiplier setting and the division ratio setting,
if it is configured in such a way that brings a frequency exceeding the maximum operable frequency, the
operation will not be guaranteed (Please be especially careful in the relative order with modifying the
source clock selection).
85
CHAPTER 3 CPU AND CONTROL BLOCK
3.12.6
Block Diagram of Clock Generation Control Unit
This section provides a block diagram of the clock generation control unit.
■ Block Diagram of Clock Generation Control Unit
The following figure shows the block diagram of the clock generation control unit. For detailed
descriptions of registers in the figure, refer to section "3.12.7 Detailed Description of Register of Clock
Generation Control Unit".
[Clock generation unit]
Oscillation
circuit
X0A*
Oscillation
circuit
Main oscillation
Stop control
External bus
clock division
CLKR
register
Peripheral clock
External bus clock
PLL
1/2
X1A*
Peripheral
clock division
CPU clock
Sub oscillation
Selector
X0
X1
Selector
Main oscillation
stabilization wait timer
(For the case of selecting sub)
CPU clock division
Selector
DIVR0, DIVR1
registers
Selector
R-bus
Figure 3.12-1 Block Diagram of Clock Generation Control Unit
[Stop/Sleep control block]
Internal interrupt
Stopped status
State transition
control circuit
STGR register
Internal reset
SLEEP status
Reset occurrence
FF
Reset occurrence
FF
Internal reset
(RST)
Internal reset
(INIT)
[
[Reset
factor circuit]
INITX pin
RSRR register
[Watchdog control block]
WPR register
CTBR register
Watchdog
FF
Counter clock
Time-base
counter
Selector
TBCR register
Enable interrupts
* : Products without S suffix only
Note:
Products with S suffix do not support sub clock.
86
Overflow
detection FF
Time-base timer
interrupt request
CHAPTER 3 CPU AND CONTROL BLOCK
3.12.7
Detailed Description of Register of Clock Generation
Control Unit
This section describes the function of the registers to be used in the clock generation
control unit.
■ RSRR: Reset Factor Register/Watchdog Timer Control Register
Figure 3.12-2 Reset Factor Register/Watchdog Timer Control Register (RSRR)
bit
Address: 00000480H
Power-on
Initial value (INIT)
Initial value (RST)
R:
*:
x:
15
14
13
12
11
10
9
8
PON
R
1
*
x
---R
0
*
x
WDOG
R
0
*
x
ERST
R
0
x
*
SRST
R
0
x
*
---R
0
*
x
WT1
R
0
0
0
WT0
R
0
0
0
Read only
Changes with factor.
Not initialized.
This register retains the reset factor generated right before, sets the period for watchdog timer and controls
the activation.
By reading this register, the retained reset factor will be cleared after the read. If the reset occurs more than
once by the time it is read, the reset factor flags will be accumulated and multiple flags will be set.
By writing into this register, the watchdog timer will be started. Thereafter, the watchdog timer continues to
operate until a reset (RST) occurs.
[bit15] PON (Power On Reset occurred)
Indicates whether a power on reset (INIT) has occurred or not.
0
Power on INIT has not occurred.
1
Power on INIT has occurred.
• It is initialized to "0" when power is on or immediately after the read.
• A read is allowed and a write does not affect the bit value.
[bit14] (reserved bit)
This bit is the reserved bit.
[bit13] WDOG (WatchDOG reset occurred)
Indicates whether a watchdog timer reset (INIT) has occurred or not.
0
Watchdog timer INIT has not occurred.
1
Watchdog timer INIT has occurred.
• It is initialized to "0" when power is on or immediately after the read.
• A read is allowed and a write does not affect the bit value.
87
CHAPTER 3 CPU AND CONTROL BLOCK
[bit12] ERST (External ReSeT occurred)
Indicates whether reset (INIT) from the INITX pin input and the CPU operation detection has occurred
or not.
0
The INIT from INITX pin input and the CPU operation detection has not occurred.
1
The INIT from INITX pin input and the CPU operation detection has occurred.
• It is initialized to "0" when power is on or immediately after the read.
• A read is allowed and a write does not affect the bit value.
[bit11] SRST (Software ReSeT occurred)
Indicates whether a reset (INIT) caused by a SRST bit write (software reset) in the STCR register has
occurred or not.
0
The software reset INIT has not occurred.
1
The software reset INIT has occurred.
• It is initialized to "0" when power is on or immediately after the read.
• A read is allowed and a write does not affect the bit value.
[bit10] (reserved bit)
This bit is reserved.
[bit9, bit8] WT1, WT0 (Watchdog interval Time select)
Sets a period for the watchdog timer.
According to the value that is written into these bits, they select the period for the watchdog timer from
the four types shown in the following table.
WT1
Write interval into WPR
WT0 minimally required for preventing watchdog
reset occurrence
Time between final 5AH write into WPR and
watchdog reset occurrence
0
0
φ × 216 [Initial value]
φ × 216 to φ × 217
0
1
φ × 218
φ × 218 to φ × 219
1
0
φ × 220
φ × 220 to φ × 221
1
1
φ × 222
φ × 222 to φ × 223
(φ is the period for an internal base clock).
• It is initialized to "00B" by a reset (RST).
• A read is allowed, a write is valid only once after a reset (RST) and any write thereafter will be
invalid.
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CHAPTER 3 CPU AND CONTROL BLOCK
■ STCR: Standby Control Register
Figure 3.12-3 Bit Configuration of Standby Control Register (STCR)
bit
7
STOP
R/W
Power-on
0
Initial value (INIT)
0
Initial value (RST)
0
Address: 00000481H
6
SLEEP
R/W
0
0
0
5
HIZ
R/W
1
1
x
4
SRST
R/W
1
1
1
3
OS1
R/W
0
x
x
2
OS0
R/W
0
x
x
1
0
OSCD2 OSCD1
R/W
R/W
1
1
1
1
x
x
R/W: Readable/writable
x:
Not initialized.
This register controls the operation mode of the device.
As well as transiting to 2 standby modes (stop, sleep) and controlling the pin and the oscillation stop during
the stop mode, it sets the oscillation stabilization wait time and a issues software reset.
Note:
When it is possible to enter a standby mode, use the synchronous standby mode (set with the
bit8:SYNCS bit in the TBCR (time-base counter control register)) and then use the following
sequence:
(LDI
#value_of_standby, R0) ; value_of_standby is write data to STCR.
(LDI
#_STCR, R12)
; _STCR is the STCR address (481H).
R0, @R12
; Write to standby control register (STCR).
STB
LDUB
@R12, R0
; STCR read for synchronous standby
LDUB
@R12, R0
; Dummy re-read of STCR
NOP
; Timing adjustment NOPx5
NOP
NOP
NOP
NOP
The function of each bit of the standby control register (STCR) is described as follows.
[bit7] STOP (STOP mode)
Indicates the transition to the stop mode. If it writes "1" both to bit6 (SLEEP bit) and to this bit, this bit
will have a priority over the other and will transit to the stop mode.
0
Does not transit to the stop mode. [Initial value]
1
Transits to the stop mode.
• It is initialized to "0" by a reset (RST) and a stop return factor.
• Read and write are allowed.
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CHAPTER 3 CPU AND CONTROL BLOCK
[bit6] SLEEP (SLEEP mode)
Indicates the transition to the sleep mode. If it writes "1" both to bit7 (STOP bit) and to this bit, bit7
(STOP bit) will have a priority over this bit and will transit to the stop mode.
0
Does not transit to the sleep mode. [Initial value]
1
Transits to the sleep mode.
• It is initialized to "0" by reset (RST) and sleep return factor.
• Read and write are allowed.
[bit5] HIZ (HIZ mode)
Controls the pin status during the stop mode.
0
Retains the pin status before the transition to the stop mode.
1
Puts the pin output into a high impedance status during the stop mode. [Initial value]
• It is initialized to "1" by a reset (INIT).
• Read and write are allowed.
[bit4] SRST (Software ReSeT)
Indicates the issue of a software reset (INIT).
0
Issues the software reset.
1
Does not issue the software reset. [Initial value]
• It is initialized to "1" by reset (RST).
• Read and write are allowed. The read value is always "1".
[bit3, bit2] OS1, OS0 (Oscillation Stabilization time select)
Sets the oscillation stabilization wait time for after the reset (INIT), the stop mode return, etc.
According to the value that is written into these bits, they select the oscillation stabilization wait time
from the four types shown in the following table.
OS1
OS0
Oscillation stabilization wait time
Main oscillation for 4MHz
0
0
φ × 21 [Initial value]
1.0 μs
0
1
φ × 211
1.0 ms
1
0
φ × 216
32.7 ms
1
1
φ × 214
8.0 ms
(φ is the period for internal base clock, the period twice as large as the main oscillation)
• It is initialized to "00B" by INITX pin input reset (INIT).
• Read and write are allowed.
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CHAPTER 3 CPU AND CONTROL BLOCK
[bit1] OSCD2 (Oscillation Disable mode for XIN2)
Controls the oscillation stop during the stop mode in sub oscillation input (X0A, X1A).
0
Does not stop the sub oscillation even during the stop mode.
1
Stops sub oscillation during the stop mode. [Initial value]
• It is initialized to "1" by a reset (INIT).
• Read and write are allowed.
Note:
Products with S suffix disable to write to this bit. The read value is always "1".
[bit0] OSCD1 (Oscillation Disable mode for XIN1)
Controls the oscillation stop during the stop mode in the main oscillation input (X0, X1).
0
Does not stop main oscillation even during the stop mode.
1
Stops main oscillation during the stop mode. [Initial value]
• It is initialized to "1" by a reset (INIT).
• Read and write are allowed.
■ TBCR: Time-base Counter Control Register
bit
Address: 00000482H
Initial value (INIT)
Initial value (RST)
15
14
13
12
11
10
9
8
TBIF
R/W
0
0
TBIE
R/W
0
0
TBC2
R/W
x
x
TBC1
R/W
x
x
TBC0
R/W
x
x
R/W
x
x
R/W
1
x
R/W
1
x
R/W: Readable/writable
x:
Not initialized.
This register controls the time-base timer interrupt, etc.
As well as enabling the time-base timer interrupt and selecting the interrupt interval time, it sets optional
functions for reset operations.
The function of each bit for the time-base counter control register (TBCR) is described as follows.
[bit15] TBIF (Time-Base timer Interrupt Flag)
This is the time-base timer interrupt flag.
It indicates that the time-base counter has elapsed the set interval time (set with bit13 to bit11:TBC2 to
TBC0 bits).
If this bit becomes "1" while interrupt occurrence is enabled (TBIE=1) by bit14 (TBIE bit), a time-base
timer interrupt request occurs.
Clear factor
Set factor
Writes "0" by instruction
Elapse of the set interval time (Falling edge detection of time-base counter output)
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CHAPTER 3 CPU AND CONTROL BLOCK
• It is initialized to "0" by reset (RST).
• Read and write are allowed. However, a write with only "0" is allowed, and a write with "1" does not
change the bit value.
And the read value is always "1" in read-modify-write (RMW) instructions.
[bit14] TBIE (Time-Base timer Interrupt Enable)
This is a time-base timer interrupt request output permission bit.
Controls the interrupt request output from the interval time lapse of the time-base counter. If bit15
(TBIF bit) becomes "1" when this bit is "1", a time-base timer interrupt request will occur.
0
Disables the time-base timer interrupt request output [Initial value]
1
Enables the time-base timer interrupt request output
• It is initialized to "0" by reset (RST).
• Read and write are allowed.
[bit13 to bit11] TBC2 to TBC0 (Time-Base timer Counting time select)
Sets the interval time of the time-base counter that is used with a time-base timer.
According to the value that is written into these bits, they select the interval time from the eight types
shown in the following table.
TBC2
TBC1
TBC0
Timer interval time
For source oscillation 4MHz and
PLL multiplied by 8
0
0
0
φ × 211
64 μs
0
0
1
φ × 212
128 μs
0
1
0
φ × 213
256 μs
0
1
1
φ × 222
131 ms
1
0
0
φ × 223
262 ms
1
0
1
φ × 224
524 ms
1
1
0
φ × 225
1048 ms
1
1
1
φ × 226
2097 ms
(φ is the period for internal base clock, the output period of the main PLL)
• The initial value is indeterminate. Be sure to set the value before enabling an interrupt.
• Read and write are allowed.
[bit10] (reserved bit)
This is a reserved bit. The read value is indeterminate, and a write does not affect the operation.
[bit9, bit8] (reserved bits)
These bits are reserved bits. The read value is always "1", and a write does not affect the operation.
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CHAPTER 3 CPU AND CONTROL BLOCK
■ CTBR: Time-base Counter Clear Register
bit
Address: 00000483H
Initial value (INIT)
Initial value (RST)
W:
x:
7
6
5
4
3
2
1
0
D7
W
x
x
D6
W
x
x
D5
W
x
x
D4
W
x
x
D3
W
x
x
D2
W
x
x
D1
W
x
x
D0
W
x
x
Write only
Not initialized.
This is the register to initialize the time-base counter.
Writing "A5H", "5AH" sequentially to this register will cause the time-base counter to clear all the bits
to "0" just after writing "5AH". There is no time restriction between write "A5H" and write "5AH",
however, if you write data other than "5AH" after writing "A5H", the operation for clearing will not be
performed unless you write "A5H" again, even if you write "5AH".
The read value of this register is indeterminate.
Note:
If you clear the time-base counter with this register, the oscillation stabilization wait interval,
watchdog timer period and the timer-base timer period will temporarily fluctuate.
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CHAPTER 3 CPU AND CONTROL BLOCK
■ CLKR: Clock Source Control Register
bit
Address: 00000484H
Initial value (INIT)
Initial value (RST)
15
---R/W
0
x
14
13
12
11
10
9
PLL1S2 PLL1S1 PLL1S0 PLL2EN PLL1EN CLKS1
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
x
x
x
x
x
x
8
CLKS0
R/W
0
x
R/W: Readable/writable
x:
Not initialized.
This is the register to select a clock source as the internal base clock and to control the main PLL.
Use this register to select the clock source. Also use it to control enabling the main PLL operation and
selecting the multiplier.
[bit15] (reserved bit)
This is a reserved bit. For this product class, always write "0" to this bit.
[bit14 to bit12] PLL1S2 to PLL1S0 (PLL1 ratio Select 2 to 0)
These are the main PLL multiplier selection bits.
Use these bits to select the main PLL multiplier among all the combinations shown below.
These bits disable the rewrite while the main PLL is selected as the clock source.
Do not set a ratio that brings a frequency exceeding the maximum operable frequency.
PLL1S2
PLL1S1
PLL1S0
Main PLL multiplier ratio
For main oscillation 4MHz
0
0
0
× 1 (equimultiple)
Unsupported on this product class
0
0
1
× 2 (multiplied by 2)
Unsupported on this product class
0
1
0
× 3 (multiplied by 3)
Unsupported on this product class
0
1
1
× 4 (multiplied by 4)
Unsupported on this product class
1
0
0
× 5 (multiplied by 5)
Unsupported on this product class
1
0
1
× 6 (multiplied by 6)
Unsupported on this product class
1
1
0
× 7 (multiplied by 7)
Unsupported on this product class
1
1
1
× 8 (multiplied by 8)
φ=31.25 [ns](at 32 MHz)
(φ is the period for internal base clock).
• It is initialized to "000B" by a reset (INIT).
• Read and write are allowed.
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CHAPTER 3 CPU AND CONTROL BLOCK
[bit11] PLL2EN (PLL2 ENable)
This is a sub clock selection enabling bit.
This bit disables the rewrite while the sub clock is selected as the clock source. This bit also disables
selecting the sub clock as the clock source while the bit is set to "0".
(See the setting of bit9, bit8 (CLKS1, CLKS0 bits)).
When bit1 (OSCD2) of STCR is "1", the sub clock stops during the stop mode even if this bit is "1". It
resumes enabling the operation after returning from the stop mode.
0
Disables selecting the 0 sub clock [Initial value]
1
Enables the 1 sub clock operation
• It is initialized to "0" by a reset (INIT).
• Read and write are allowed.
Note:
Products with S suffix disable to write to this bit. The read value is always "0".
[bit10] PLL1EN (PLL1 ENable)
This is the main PLL operation enabling bit.
This bit disables the rewrite while the main PLL is selected as the clock source. It also disables selecting
the main PLL as the clock source while this bit is "0".
(See the setting of bit9, bit8 (CLKS1, CLKS bits)).
When bit0 (OSCD1) of STCR is "1", the main PLL stops during the stop mode even if this bit is "1". It
resumes enabling the operation after returning from the stop mode.
0
Stops the main PLL [Initial value]
1
Enable the main PLL operation
• It is initialized to "0" by a reset (INIT).
• Read and write are allowed.
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CHAPTER 3 CPU AND CONTROL BLOCK
[bit9, bit8] CLKS1, CLKS0 (CLocK source Select)
Sets the clock source to be used.
According to the value to be written into these bits, they select the clock source from the three types
shown in the following table.
CLKS1
CLKS0
Clock source setting
0
0
Source oscillation input from X0/X1 divided by two [Initial value]
0
1
Source oscillation input from X0/X1 divided by two
1
0
Main PLL
1
1
sub clock
• It is initialized to "00B" by a reset (INIT).
• Read and write are allowed.
Note:
While bit9 (CLKS1) is "1", the value of bit8 (CLKS0) cannot be changed.
Products with S suffix disable to write to bit8 (CLKS0). The read value is always "0".
[Unmodifiable combination]
[Modifiable combination]
"00B" → "11B"
"00B" → "01B" or "10B"
"01B" → "10B"
"01B" → "11B" or "00B"
"10B" → "01B" or "11B"
"10B" → "00B"
"11B" → "00B" or "10B"
"11B" → "01B"
When transiting to the stop mode, make sure that you set the clock source to the source oscillation input
divided by two.
96
CHAPTER 3 CPU AND CONTROL BLOCK
■ WPR: Watchdog Reset Occurrence Postponing Register
bit
Address: 00000485H
Initial value (INIT)
Initial value (RST)
W:
x:
7
6
5
4
3
2
1
0
D7
R/W
x
x
D6
R/W
x
x
D5
R/W
x
x
D4
R/W
x
x
D3
R/W
x
x
D2
R/W
x
x
D1
R/W
x
x
D0
R/W
x
x
Write only
Not initialized.
This is the register to postpone the occurrence of watchdog reset.
Writing "A5H", "5AH" sequentially to this register will clear FF for a watchdog timer detection just after
writing "5AH" and postpone the occurrence of watchdog reset. There is no time restriction between write
"A5H" and write "5AH", however, if you write data other than "5AH" after writing "A5H", the operation for
clearing will not be performed unless you write "A5H" again, even if you write "5AH". Failure to complete
writing both data within the time specified in the following table will result in the occurrence of watchdog
reset.
The read value of this register is indeterminate.
Depending on the status of WT1 (bit9), WT0 (bit8) of the RSRR register, the value changes as shown in the
following table.
WT1
WT0
Time interval to write into WPR
minimally required for preventing RSRR
watchdog reset occurrence
Time between final 5AH write into WPR and
watchdog reset occurrence
0
0
φ × 216 [Initial value]
φ × 216 to φ × 217
0
1
φ × 218
φ × 218 to φ × 219
1
0
φ × 220
φ × 220 to φ × 221
1
1
φ × 222
φ × 222 to φ × 223
(φ is the period for system base clock, WT1, WT0 sets the watchdog timer period by bit9, bit8 of RSRR)
The register automatically clears while CPU is not operating in such cases where it is in stopped position,
sleeping status, DMA transfer, etc., therefore, if these conditions occur, the watchdog reset will
automatically be postponed.
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CHAPTER 3 CPU AND CONTROL BLOCK
■ DIVR0: Base Clock Divide Setting Register 0
bit
Address: 00000486H
Initial value (INIT)
Initial value (RST)
15
14
13
12
11
10
9
8
B3
R/W
0
x
B2
R/W
0
x
B1
R/W
0
x
B0
R/W
0
x
P3
R/W
0
x
P2
R/W
0
x
P1
R/W
1
x
P0
R/W
1
x
R/W: Readable/writable
x:
Not initialized.
This is the register to control the division ratio of each internal clock to the base clock.
This register configures the configuration for the division ratio of the CPU and the internal bus clock
(CLKB) and of the peripheral circuitry and peripheral bus clock (CLKP).
Note:
In the combination of a source clock selection, the main PLL multiplier setting and the division ratio
setting, if it is configured in such a way that brings a frequency exceeding the maximum operable
frequency, the operation will not be guaranteed. Please pay a careful attention to this. Please be
especially careful in the relative order with modifying the source clock selection.
If the setting of this register is changed, the division ratio changed from the clock rate next after the
setting will be valid.
[bit15 to bit12] B3 to B0 (clkB divide select 3 to 0)
These are CPU clock (CLKB) clock division ratio setting bits.
Sets the clock division ratio of the CPU, the internal memory and internal bus clock (CLKB).
According to the value to be written into these bits, they select the division ratio (clock frequency) for
the base clock of CPU and internal bus clock from the sixteen types shown in the following table.
Do not set a division ratio that brings a frequency exceeding the maximum operable frequency.
B3
B2
B1
B0
Clock divide ratio
Clock frequency: For source oscillation 4MHz
and main PLL multiplied by 8
0
0
0
0
φ
32 MHz [Initial value]
0
0
0
1
φ × 2 (divided by 2)
16 MHz
0
0
1
0
φ × 3 (divided by 3)
10.7 MHz
0
0
1
1
φ × 4 (divided by 4)
8 MHz
0
1
0
0
φ × 5 (divided by 5)
6.4 MHz
0
1
0
1
φ × 6 (divided by 6)
5.33 MHz
0
1
1
0
φ × 7 (divided by 7)
4.57 MHz
0
1
1
1
φ × 8 (divided by 8)
4 MHz
...
...
...
...
...
...
1
1
1
1
φ × 16 (divided by 16)
2 MHz
(φ is the period for internal base clock).
• It is initialized to "0000B" by a reset (INIT).
• Read and write are allowed.
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CHAPTER 3 CPU AND CONTROL BLOCK
[bit11 to bit8] P3 to P0 (clkP divide select 3 to 0)
These are the peripheral clock (CLKP) clock division ratio setting bits.
Sets the clock division ratio of peripheral circuit and peripheral bus clock (CLKP).
According to the value to be written into these bits, they select the division ratio (clock frequency) for
the base clock of peripheral circuitry and peripheral bus clock from the sixteen types shown in the
following table.
Do not set a division ratio that brings a frequency exceeding the maximum operable frequency.
P3
P2
P1
P0
Clock divide ratio
Clock frequency: For source oscillation 4MHz
and main PLL multiplied by 8
0
0
0
0
φ
32 MHz
0
0
0
1
φ × 2 (divided by 2)
16 MHz
0
0
1
0
φ × 3 (divided by 3)
10.7 MHz
0
0
1
1
φ × 4 (divided by 4)
8 MHz [Initial value]
0
1
0
0
φ × 5 (divided by 5)
6.4 MHz
0
1
0
1
φ × 6 (divided by 6)
5.33 MHz
0
1
1
0
φ × 7 (divided by 7)
4.57 MHz
0
1
1
1
φ × 8 (divided by 8)
4 MHz
...
...
...
...
...
...
1
1
1
1
φ × 16 (divided by 16)
2 MHz
(φ is the period for system base clock).
• It is initialized to "0011B" by a reset (INIT).
• Read and write are allowed.
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CHAPTER 3 CPU AND CONTROL BLOCK
■ DIVR1: Base Clock Divide Setting Register 1
bit
Address: 00000487H
Initial value (INIT)
Initial value (RST)
7
6
5
4
3
2
1
0
T3
R/W
0
x
T2
R/W
0
x
T1
R/W
0
x
T0
R/W
0
x
---R/W
0
x
---R/W
0
x
---R/W
0
x
---R/W
0
x
R/W: Readable/writable
x:
Not initialized.
This is the register to control the division ratio of each internal clock to base clock.
This register sets the division ratio of the external bus interface clock (CLKT).
Note:
In the combination of a source clock selection, the main PLL multiplier setting and the division ratio
setting, if it is configured in such a way that brings a frequency exceeding the maximum operable
frequency, the operation will not be guaranteed. Please pay a careful attention to this. Please be
especially careful in the relative order with modifying the source clock selection.
If the setting of this register is changed, the division ratio changed from the clock rate next after the
setting will be valid.
[bit7 to bit4] T3 to T0 (clkT divide select 3 to 0)
These are the external bus clock (CLKT) clock division ratio setting bits.
Sets the clock division ratio of the external bus interface clock (CLKT).
According to the value to be written into these bits, they select the division ratio (clock frequency) for
the base clock of external expansion bus interface clock from the six-teen types shown in the following
table.
Since the maximum operable frequency is 16MHz, do not set a division ratio that exceeds 16MHz.
T3
T2
T1
T0
Clock divide ratio
Clock frequency:
For source oscillation 4MHz and
main PLL multiplied by 8
0
0
0
0
φ
32 MHz [Initial value]
0
0
0
1
φ × 2 (divided by 2)
16 MHz
0
0
1
0
φ × 3 (divided by 3)
10.7 MHz
0
0
1
1
φ × 4 (divided by 4)
8 MHz
0
1
0
0
φ × 5 (divided by 5)
6.4 MHz
0
1
0
1
φ × 6 (divided by 6)
5.33 MHz
0
1
1
0
φ × 7 (divided by 7)
4.57 MHz
0
1
1
1
φ × 8 (divided by 8)
4 MHz
...
...
...
...
...
...
1
1
1
1
φ × 16 (divided by 16)
2 MHz
(φ is the period for system base clock).
• It is initialized to "0000B" by a reset (INIT).
• Read and write are allowed.
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CHAPTER 3 CPU AND CONTROL BLOCK
If you do not use the external bus interface, it is recommended to set it to "1111B"(divided by sixteen).
[bit3 to bit0] (reserved bits)
• It is initialized to "0000B" by a reset (INIT).
• For writing into this bit, always write "0000B ".
■ OSCCR: Oscillation Control Register
bit
Address: 0000048AH
Initial value (INIT)
Initial value (RST)
7
6
5
4
3
2
1
0
------x
x
---R/W
0
x
---R/W
0
x
RTCSRC
R/W
0
x
------x
x
------x
x
------x
x
OSCDS1
R/W
0
0
R/W: Readable/writable
x:
Not initialized.
This is the register to control the main oscillation during the operation of sub clock.
[bit7 to bit5] (reserved bits)
These are reserved bits. For this product class, always write "0" to these bits.
[bit4] RTCSRC: RTC Source Clock Select
This is the bit to select the source clock to RTC.
0
Main clock (4 MHz) [Initial value]
1
sub clock (32 kHz)
Notes:
• Once you write "1", it can only be initialized to "0" by INIT reset.
• If you expect RTC operation, it is subject to the fact that the clock to be distributed to RTC is not
at a stop.
• For products with S suffix, do not set "1".
[bit3 to bit0] (reserved bits)
These are reserved bits. For this product class, always write "0" to these bits.
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CHAPTER 3 CPU AND CONTROL BLOCK
[bit0] OSCDS1 (OSCillation Disable on Sub Clock for XIN1)
This is the main oscillation stopping bit while sub clock is selected.
0
Does not stop the main oscillation while implementing sub clock. [Initial value]
1
Stops the main oscillation while implementing sub clock.
• It is initialized to "0" by a reset (INIT).
• Read and write are allowed.
Writing "1" into this bit while selecting the sub clock as the clock source will cause the main oscillation to
be stopped.
It is disabled to write "1" into this bit while selecting the main clock.
This bit disables selecting the main clock while it is "1". Set this bit to "0" and wait for the stabilization of
the main oscillation, and then change to the main clock. At this time, secure the oscillation stabilization
wait time using the main oscillation stabilization wait timer. If the clock source is changed to the main
clock by INIT with the main oscillation stopped by this bit, the main oscillation stabilization wait time will
also be required. At this time, if the setting for bit3, bit2 (OS1, OS0) of STCR (standby control register)
does not satisfy the main oscillation stabilization wait time, the operation after the return will not be
guaranteed.
In such a case, for STCR (OS1, OS0 bits), set the value that satisfies the main oscillation stabilization wait
time.
During INIT by INITX pins, you must continue to input "L" to INITX pins until the main oscillation
stabilizes.
For the oscillation stabilization wait, see also the section for clock generation control "3.12.3 Oscillation
Stabilization Wait/PLL Lock Wait Time".
Note:
For products with S suffix, a write into this bit does not affect the operation.
102
CHAPTER 3 CPU AND CONTROL BLOCK
3.12.8
Peripheral Circuit of Clock Control Unit
Peripheral circuit function of clock control unit is described as follows.
■ Time-base Counter
The clock control unit has the 26 bit long time-base counter, which operates with the internal base clock.
The time-base counter is used for the following purposes including the measuring of oscillation
stabilization wait time (Refer to section "3.11.6 Oscillation Stabilization Waiting Factor of the 3.11 Reset
(Device Initialization)").
• Watchdog timer
Measures the watchdog timer for detecting the runaway of system using the bit output of time-base
counter.
• Time-base timer
Generates interval interrupts using the time-base counter output.
These functions are described as follows.
● Watchdog Timer
The watchdog timer is the timer for detecting the runaway with use of the time-base counter output. When
the watchdog reset occurrence postponing operation is not conducted between the set intervals due to the
runaway of program, etc., it generates the setting initialization reset (INIT) request as the watchdog reset.
[Starting the watchdog timer and setting the period]
The watchdog timer starts with the first write operation into RSRR (reset factor register/watchdog timer
control register) after the reset (RST). At this time, set the interval time for the watchdog timer with
bit9, bit8 (WT1, WT0 bits). In the interval time setting, only the interval time that is set in this first write
will be valid, any write thereafter will all be ignored.
[Postponing the watchdog reset occurrence]
Once you start the watchdog timer, you must periodically write the data into WPR (watchdog reset
occurrence postponing register) in the order of "A5H", "5AH" by the program. This operation will
initialize the flag for the watchdog reset occurrence.
[Generating the watchdog reset]
The flag for the watchdog reset occurrence is set up by the falling edge of the time-base counter output
for the set interval. If the flag is set up at the time of detection of the second falling edge, it will generate
the setting initialization reset (INIT) request as the watchdog reset.
[Stopping watchdog timer]
Once you have started the watchdog timer, you cannot stop it until the operation initialization reset
(RST) occurs.
Under the following states where the operation initialization reset (RST) occurs, the watchdog timer
stops and does not function until it is restarted by the program operation.
• Operation initialization reset (RST) state
• Setting initialization reset (RST) state
• Oscillation stabilization wait reset (RST) state
103
CHAPTER 3 CPU AND CONTROL BLOCK
[Pause of watchdog timer (automatic occurrence postponement)]
The watchdog timer once initializes the flag for the watchdog reset occurrence while the program
operation of the CPU is stopped, and postpones the occurrence of watchdog reset. The stop of program
operation specifically means the following operations.
• Sleep state
• Stop state
• Oscillation stabilization wait RUN state
• During DMA transfer to D-bus (data bus)
• During the break while emulator debugger is used
Clearing the time-base counter will cause the flag for the watchdog reset occurrence to be initialized in
parallel, and the occurrence of watchdog reset will be postponed.
● Time-base Timer
The time-base timer is the timer for generating interval interrupts with the use of the time-base counter
output. It is suitable for use of timekeeping of a relatively long time up to base clock × 227 cycle such as the
main PLL lock wait time and the oscillation stabilization wait time of sub clock, etc.
Detecting the falling edge of the time-base counter output for the set interval will cause the time-base timer
interrupt request.
[Starting time-base timer and setting the interval]
The time-base timer sets the interval time with bit13 to bit11 (TBC2 to TBC0 bits) of TBCR (time-base
counter control register).
Since the falling edge of the time-base counter output for the set interval is constantly detected, once
you have set the interval time, first clear bit15 (TBIF bit) and set bit14 (TBIE bit) to "1", and then
enable the interrupt request output.
When you change the interval time, disable the interrupt request output by setting bit14 (TBIE bit) to
"0" beforehand.
Since the time-base counter constantly conducts the count operation not being affected by these
configuration, clear the time-base counter before enabling the interrupt in order to get the exact interval
interrupt time. Otherwise, an interrupt request may occur immediately after enabling the interrupt.
[Clearing time-base counter by program]
Writing the data into CTBR (time-base counter clear register) in the order of "A5H", "5AH" will cause
the time-base counter to clear all the bits to "0" just after writing "5AH". There is no time restriction
between write "A5H" and write "5AH", however, if you write data other than "5AH" after writing "A5H",
the operation for clearing will not be performed unless you write "A5H" again, even if you write "5AH".
Clearing the time-base counter will cause the flag for the watchdog reset occurrence to be initialized in
parallel, and the occurrence of watchdog reset will be postponed for once.
[Clearing time-base counter according to device status]
All the bits for the time-base counter will be cleared to "0" simultaneously with the transition to the
following device statuses.
• Stopped
• Setting initialization reset (INIT) status
Particularly while being stopped, the time-base counter is used for timekeeping of the oscillation
stabilization wait time, so the interval interrupt of the time-base timer may occur unintentionally.
Therefore, before setting up the stop mode, disable the time-base timer interrupt and do not use the time104
CHAPTER 3 CPU AND CONTROL BLOCK
base timer.
For the other statuses, the operation initialization reset (RST) occurs, and therefore the time-base timer
interrupt will automatically be disabled.
● Main Oscillation Stabilization Wait Timer
This is the 26-bit timer that counts up synchronous with main clock not being affected by the selection of
source clock or divide setting.
It is used for timekeeping of the main oscillation stabilization wait time while sub clock is operating.
While you can control the main oscillation with bit0:OSCDS1 bit in the OSCCR (oscillation control
register) during the operation with sub clock, you use this timer to time the oscillation stabilization wait
time when you start the oscillation again after stopping the main oscillation.
When you change to the main clock from the sub clock operational state where the main clock is stopped,
follow the procedures below.
• Clear the main oscillation stabilization wait timer.
• Set bit0:OSCDS1 bit of OSCCR (oscillation control register) to "0" and start the main oscillation.
• With the main oscillation stabilization wait timer, wait until the main clock stabilizes.
• After the main clock stabilizes, change from the sub clock to the main clock with bit9, bit8 (CLKS1,
CLKS0 bits) of CLKR (clock source register).
To change to the main clock without waiting the stabilization, unstable clock will be distributed and the
subsequent operation will not be guaranteed, so make sure you change to the main clock after waiting the
stabilization.
For details of main oscillation stabilization wait timer, refer to "CHAPTER 11 MAIN OSCILLATION
STABILIZATION WAIT TIMER".
Note:
Products with S suffix do not support sub clock.
105
CHAPTER 3 CPU AND CONTROL BLOCK
3.13
Device Status Control
This section describes each status of the MB91245/S series and its control.
■ Device Statuses and Individual Transitions
Figure 3.13-1 shows a transitional diagram of the status of the MB91245/S series.
Figure 3.13-1 Transitional Diagram of Status of MB91245/S Series
1
2
3
4
5
6
7
8
9
10
INITX pin=0(INIT)
INITX pin=1(INIT cancellation)
End of oscillation stabilization wait
Reset (RST) cancellation
Software reset (RST)
Sleep (instruction writing)
Stop (instruction writing)
Interrupt
External interrupt not requiring clocks
Switching from the main clock mode to
sub clock mode (instruction writing)
11 Switching from the sub clock mode to
main clock mode (instruction writing)
12 Watchdog reset (INIT)
13 Sub-sleep (instruction writing)
Priorities of transition requests
Highest
↓
↓
↓
↓
Lowest
Power-on
1
Setting initialization reset (INIT)
End of oscillation stabilization wait
Operation initialization reset (RST)
Interrupt request
Stop
Sleep
Setting initialization
(INIT)
2
Main clock mode
1
Main oscillation
stabilization reset
Main stop
9
1
3
1
Oscillation
stabilization
wait RUN
Program reset
(RST)
3
7
1
6
Main sleep
5
1
4
12
Main RUN
8
1
10
Sub clock mode
Sub-sleep
Oscillation
stabilization
wait RUN
12
Sub-RUN
13
3
1
1
11
8
1
7
5
1
4
Program reset
(RST)
1
9
Sub-stop
(Clock status*2)
Notes:
•
•
•
106
To switch the clock source from the main clock mode to sub clock mode or vice versa, switch bit1 (CLKS1) and
bit0 (CLKS0) of the clock source register (CLKR) with the switched clocks stably supplied in the RUN status.
To stop the circuits other than the watch timer (watch status), set bit1 (OSCD2) of the standby control register
(STCR) to "0" and bit0 (OSCD1) to "1" in the sub-RUN status and enter the stop mode (Simultaneous writing is
possible).
Products with S suffix do not support the sub clock mode.
CHAPTER 3 CPU AND CONTROL BLOCK
The MB91245/S series has the following operating states.
• RUN Status (Normal Operation)
• Sleep Status
• Stop Status
• Oscillation Stabilization Wait RUN Status
• Oscillation Stabilization Wait Reset (RST) Status
• Operation Initialization Reset (RST) Status
• Setting Initialization Reset (INIT) Status
The following describes each operation status.
● RUN Status (Normal Operation)
Programs are in execution.
All internal clocks are supplied and all circuits are operable.
However, only for the 16-bit peripheral bus, only the bus clocks stop while no access is made.
● Sleep Status
Programs are stopped. This status makes a transition according to program operation.
Only CPU' s program execution stops and the peripheral circuits are operable. The various types of built-in
memory, internal buses, and the external buses stop as long as the DMA controller issues no request.
This status is canceled when a valid interrupt request occurs, and transits to the RUN status (normal
operation).
When a setting initialization reset (INIT) request occurs, this status transits to the setting initialization reset
(INIT) status.
When an operation initialization reset (RST) request occurs, this status transits to the operation
initialization reset (RST) status.
● Stop Status
Devices are stopped. This status makes a transition according to program operation.
All internal circuits stop. All internal clocks stop. The oscillation circuit and the main PLL can be stopped
according to the setting.
Moreover, the external pins can be evenly put into a high impedance status according to the setting (Some
pins are excluded).
This status transits to the oscillation stabilization wait RUN status when a specific (clocks not required)
valid interrupt request occurs or a main oscillation stabilization wait timer interrupt request occurs during
oscillation.
When a setting initialization reset (INIT) request occurs, this status transits to the setting initialization reset
(INIT) status.
When an operation initialization reset (RST) request occurs, this status transits to the oscillation
stabilization wait reset (RST) status.
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CHAPTER 3 CPU AND CONTROL BLOCK
● Oscillation Stabilization Wait RUN Status
Devices are stopped. This status makes a transition after return from the stop status.
All internal circuits stop, excluding the clock generation control units (time-base counter and device status
control unit). All internal clocks stop. However, the oscillation circuit and the main PLL allowed to operate
are running.
High-impedance control on the external pins in the stop status and other statuses is canceled.
This status transits to the RUN status (normal operation) as the specified oscillation stabilization wait time
progresses.
When a setting initialization reset (INIT) request occurs, this status transits to the setting initialization reset
(INIT) status.
When an operation initialization reset (RST) request occurs, this status transits to the oscillation
stabilization wait reset (RST) status.
● Oscillation Stabilization Wait Reset (RST) Status
Devices are stopped. This status makes a transition after return from the stop status or setting initialization
reset (INIT) status.
All internal circuits stop, excluding the clock generation control units (time-base counter and device status
control unit). All internal clocks stop. However, the oscillation circuit and the main PLL allowed to operate
are running.
High-impedance control on the external pins in the stop status and other statuses is canceled.
The operation initialization reset (RST) is output to internal circuits.
The device status transits to the oscillation stabilization wait reset (RST) status as the specified oscillation
stabilization wait time progresses.
When a setting initialization reset (INIT) request occurs, this status transits to the setting initialization reset
(INIT) status.
● Operation Initialization Reset (RST) Status
Programs are initialized. This status makes a transition when an operation initialization reset (RST) request
is accepted or the oscillation stabilization wait reset (RST) status ends.
CPU's program execution stops and the program counter is initialized. The peripheral circuits, excluding
some of them, are initialized. All internal clocks, the oscillation circuit, and the main PLL allowed to
operate are running.
The operation initialization reset (RST) is output to internal circuits.
When the operation initialization reset (RST) request disappears, this status transits to the RUN status
(normal operation) and the operation initialization reset sequence is executed. Upon returning from the
setting initialization reset (INIT) status, the setting initialization reset sequence is executed.
When a setting initialization reset (INIT) request occurs, this status transits to the setting initialization reset
(INIT) status.
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CHAPTER 3 CPU AND CONTROL BLOCK
● Setting Initialization Reset (INIT) Status
All configuration are initialized. This status makes a transition when a setting initialization reset (INIT)
request is accepted.
CPU's program execution stops and the program counter is initialized. All peripheral circuits are initialized.
The oscillation circuit operates but the main PLL stops. All internal clocks stop while reset factors are
input; however, they operate in other cases.
The setting initialization reset (INIT) and operation initialization reset (RST) are output to internal circuits.
When the setting initialization reset (INIT) request disappears, this status is canceled and transits to the
oscillation stabilization wait reset (RST) status. Afterwards, the operation initialization reset (RST) status
elapses and the setting initialization reset sequence is executed.
● Priorities of Individual Transition Requests
Even in any status, the status transition requests conform to the priorities listed below. However, some
requests occurring only in specific statuses are valid only in those specific statuses.
[Highest] Setting initialization reset (INIT) request
↓
End of the oscillation stabilization wait time (occurring only for the oscillation stabilization
wait reset status and oscillation stabilization wait RUN status)
↓
Operation initialization reset (RST) request
↓
Valid interrupt request (occurring only in the RUN, sleep, and stop statuses)
↓
Stop mode request (write to registers) (generated only for the RUN status)
[Lowest] Sleep mode request (write to registers) (generated only for the RUN status)
■ Low-power Consumption Mode
The following describes the standby mode (low-power consumption mode) among all the modes of
MB91245/S series and how to use them.
The low-power consumption modes of MB91245/S series are as follows:
•
Sleep mode
transits the device to the sleep status by register writing.
•
Stop mode
transits the device to the stop status by register writing.
Each mode is explained below.
● Sleep Mode
Writing "1" to bit6 (SLEEP bit) of the standby control register (STCR) leads to the sleep mode and makes
the device status transit to the sleep status. Afterwards, the sleep status is retained until a return factor from
the sleep status occurs.
For the sleep status, refer to "● Sleep Status" fo "■ Device Statuses and Individual Transitions".
[Transition to the sleep mode]
To enter the sleep mode, be sure to use the following sequence:
(LDI
#value_of_sleep, R0)
; value_of_sleep is write data to STCR.
(LDI
#_STCR, R12)
; _STCR is the STCR address (481H).
STB
R0, @R12
; Write to the standby control register (STCR)
LDUB
@R12, R0
; STCR read for synchronous standby
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CHAPTER 3 CPU AND CONTROL BLOCK
LDUB
@R12, R0
NOP
; Dummy re-read of STCR
; Timing adjustment NOP × 5
NOP
NOP
NOP
NOP
If "1" is written both to bit7 (STOP bit) and this bit6 of the standby control register (STCR), the priority
is placed on bit7 (STOP bit), meaning that the sleep mode transits to the stop mode.
[Circuits that stop in the sleep mode]
•
CPU's program execution
The following run when DMA transfer has occurred:
•
Bit search module
•
Various types of built-in memory
•
Internal and external buses
[Circuits that do not stop in the sleep mode]
•
Oscillation circuit
•
Main PLL allowed to operate
•
Clock generation control unit
•
Interrupt controller
•
Peripheral circuits
•
Main oscillation stabilization wait timer
•
Watch timer
•
DMA controller
•
On chip Debug Support Unit (DSU)
[Return factors from the sleep status]
•
Generation of a valid interrupt request
If an interrupt request occurs for which the ICR (Interrupt Control) register indicates that the
interrupt is not disabled (1111B), the sleep mode is canceled and the device status transits to the
RUN status (normal operation).
The sleep mode is not canceled even if an interrupt request occurs for which the ICR (Interrupt
Control) register indicates that the interrupt is disabled (1111B).
•
Generation of a setting initialization reset (INIT) request
When a setting initialization reset (INIT) request occurs, the device status unconditionally transits to
the setting initialization reset (INIT) status.
Note:
For the priorities of the return factors, refer to "● Priorities of Individual Transition Requests" of
"■ Device Statuses and Individual Transitions".
110
CHAPTER 3 CPU AND CONTROL BLOCK
[Synchronous standby operation]
Use of only the write to the SLEEP bit does not allow the device status to transit to the sleep status.
Afterwards, reading the STCR (Standby Control) register enables the device status to transit to the sleep
status.
To use the sleep mode, be sure to use the sequence given in [Transition to the sleep mode].
● Stop Mode
Writing "1" to bit7 (STOP bit) of the standby control register (STCR) leads to the stop mode and makes the
device status transit to the stop status. Afterwards, the stop status is retained until a return factor from the
stop status occurs. However, stop the main oscillation in the stop mode.
For the stop status, refer to "● Stop Status" of "■ Device Statuses and Individual Transitions".
[Transition to the stop mode]
To enter the stop mode, be sure to use the following sequence:
(LDI
#value_of_stop, R0)
; value_of_stop is write data to STCR.
(LDI
#_STCR, R12)
; _STCR is the STCR address (481H).
STB
R0, @R12
; Write to the standby control register (STCR)
LDUB
@R12, R0
; STCR read for synchronous standby
LDUB
@R12, R0
; Dummy re-read of STCR
NOP
; Timing adjustment NOP × 5
NOP
NOP
NOP
NOP
If "1" is written both to bit6 (SLEEP bit) and this bit7 of the standby control register (STCR), priority is
placed on bit7 (STOP bit), meaning that the sleep mode transits to the stop mode.
[Circuits that stop in the stop mode]
•
The oscillation circuit must stop.
•
Bit0 (OSCD1 bit) of the standby control register (STCR) must be set to "1".
[High-impedance control on pins in the stop status]
If bit5 (HIZ bit) of the standby control register (STCR) is "1", the pin output in the stop status is put into
a high impedance status. For the pins to be subjected to this control, refer to "APPENDIX C Status of
Each Pin due to Reset"
If bit5 (HIZ bit) of the standby control register (STCR) is "0", the pin output in the stop status retains
values it had before transition to the stop status. For details, refer to "APPENDIX C Status of Each Pin
due to Reset"
111
CHAPTER 3 CPU AND CONTROL BLOCK
[Return factors from the stop status]
•
Generation of a specific (clocks not required) valid interrupt request
Some external interrupts are valid.
If an interrupt request occurs for which the ICR (Interrupt Control) register indicates that the
interrupt is not disabled (1111B), the stop mode is canceled and the device status transits to the
oscillation stabilization wait RUN status.
The stop mode is not canceled even if an interrupt request occurs for which the ICR (Interrupt
Control) register indicates that the interrupt is disabled (1111B).
•
Generation of a setting initialization reset (INIT) request
When a setting initialization reset (INIT) request occurs, the device status unconditionally transits to
the setting initialization reset (INIT) status.
Note:
For the priorities of the return factors, refer to "● Priorities of Individual Transition Requests" of
"■ Device Statuses and Individual Transitions".
[Clock source selection in the stop mode]
In the self-excited oscillation mode, before setting the stop mode, make a selection so that the source
clock is obtained by dividing the main clock by two. For details, refer to section "3.12.2 PLL Control".
The restrictions on the division ratio setting are the same as in the normal operation.
[Synchronous standby operation]
Use of only the write to the STOP bit does not allow the device status to transit to the stop status.
Afterwards, reading the STCR (Standby Control) register enables the device status to transit to the stop
status.
To use the stop mode, be sure to use the sequence given in [Transition to the stop mode].
112
CHAPTER 4
I/O PORT
This chapter outlines the I/O ports and describes the
configuration and functions of their registers.
4.1
Overview of the I/O Port
4.2
Registers of I/O port
4.3
I/O Expansion Functions
113
CHAPTER 4 I/O PORT
4.1
Overview of the I/O Port
This section describes the port configuration.
■ Basic Block Diagram of the Port
MB91245/S series can be used as an I/O port when it is configured that each pin is not used as a peripheral
I/O.
The ports are configured using the following registers.
• PDR (Port Data Register)
• DDR (Port Direction Register)
• PFR (Port Function Register)
The basic configurations of the I/O ports are described below.
Figure 4.1-1 I/O Port Block Diagram
Peripheral input
R-bus
PDR read
0
*
1
Peripheral output
PDR
PFR
1
0
Stop mode
P-ch
N-ch
DDR
*: If reading while performing a read-modify-write (RMW) instruction to
the PDR register, "1" will always be selected.
DDR: Data Direction Register
PDR: Port Data Register
PFR: Port Function Register
114
Pin
CHAPTER 4 I/O PORT
Figure 4.1-2 Port Block Diagram Jointly Used for Analog Inputs
Analog input
Peripheral input
R-bus
PDR read
0
*
1
Stop mode
PDR
P-ch
Pin
1
N-ch
PFR
0
DDR
*: If reading while performing a read-modify-write (RMW) instruction to
the PDR register, "1" will always be selected.
DDR: Data Direction Register
PDR: Port Data Register
PFR: Port Function Register
Figure 4.1-3 Port Block Diagram Jointly Used for Analog Outputs
Peripheral input
R-bus
PDR read
0
*
1
Stop mode
PDR
P-ch
Pin
1
PFR
N-ch
0
Analog output
DDR
*: If reading while performing a read-modify-write (RMW) instruction to
the PDR register, "1" will always be selected.
DDR: Data Direction Register
PDR: Port Data Register
PFR: Port Function Register
115
CHAPTER 4 I/O PORT
■ Operating Modes
• During port input mode (PFR=0 & DDR=0)
- PDR read:
The corresponding external pin level is read.
- PDR write:
The set value is written to PDR. The PDR value, however, is not applied in the
corresponding external pins.
- Reading using read-modify-write (RMW) instruction:
The PDR value is read.
• During port output mode (PFR=0 & DDR=1)
- PDR read:
The PDR value is read.
- PDR write:
The set value is written to PDR, and output to the external pins corresponding to the
PDR value.
- Reading using read-modify-write (RMW) instruction:
The PDR value is read.
• During peripheral output mode (PFR=1)
- PDR read:
The corresponding external pin level is read.
- PDR write:
The set value is written to PDR. The PDR value, however, is not applied in the
corresponding external pins.
- Reading using read-modify-write (RMW) instruction:
The corresponding peripheral output value is read.
Notes:
• If using the pins as an input resource, make sure that PFR=0 and DDR=0 (port input mode).
• There is no register switched between general-purpose port input and peripheral input. The value
input via an external pin is always passed to the general-purpose port and peripheral circuit.
Even with the DDR output setting, the value output to the outside is always propagated to the
general-purpose port and peripheral circuit.
For use as a peripheral input, use DDR input and enable each peripheral's input signal.
116
CHAPTER 4 I/O PORT
4.2
Registers of I/O port
This section explains the configuration and the function of registers which are used in
I/O ports.
■ Port Data Register (PDR:PDR0 to PDRG)
PDR0
bit 7
Address: 00000000H
P07
Read/Write (R/W)
Initial value
(X)
6
5
4
3
2
1
0
P06
(R/W)
(X)
P05
(R/W)
(X)
P04
(R/W)
(X)
P03
(R/W)
(X)
P02
(R/W)
(X)
P01
(R/W)
(X)
P00
(R/W)
(X)
PDR1
bit 7
Address: 00000001H
P17
Read/Write (R/W)
Initial value
(X)
6
5
4
3
2
1
0
P16
(R/W)
(X)
P15
(R/W)
(X)
P14
(R/W)
(X)
P13
(R/W)
(X)
P12
(R/W)
(X)
P11
(R/W)
(X)
P10
(R/W)
(X)
PDR2
bit 7
Address: 00000002H
P27
Read/Write (R/W)
Initial value
(0)
6
5
4
3
2
1
0
P26
(R/W)
(0)
P25
(R/W)
(0)
P24
(R/W)
(0)
P23
(R/W)
(0)
P22
(R/W)
(0)
P21
(R/W)
(0)
P20
(R/W)
(0)
PDR3
bit 7
Address: 00000003H
P37
Read/Write (R/W)
Initial value
(X)
6
5
4
3
2
1
0
P36
(R/W)
(X)
P35
(R/W)
(X)
P34
(R/W)
(X)
P33
(R/W)
(0)
P32
(R/W)
(0)
P31
(R/W)
(0)
P30
(R/W)
(0)
PDR4
bit 7
Address: 00000004H
P47
Read/Write (R/W)
Initial value
(X)
6
5
4
3
2
1
0
P46
(R/W)
(X)
P45
(R/W)
(X)
P44
(R/W)
(X)
P43
(R/W)
(X)
P42
(R/W)
(X)
P41
(R/W)
(X)
P40
(R/W)
(X)
PDR5
bit 7
Address: 00000005H
P57
Read/Write (R/W)
Initial value
(X)
6
5
4
3
2
1
0
P56
(R/W)
(X)
P55
(R/W)
(X)
P54
(R/W)
(X)
P53
(R/W)
(X)
P52
(R/W)
(X)
P51
(R/W)
(X)
P50
(R/W)
(X)
6
5
4
3
2
1
0
P66
(R/W)
(X)
P65
(R/W)
(X)
P64
(R/W)
(X)
P63
(R/W)
(X)
P62
(R/W)
(X)
P61
(R/W)
(X)
P60
(R/W)
(X)
6
5
4
3
2
1
0
(-)
(-)
(-)
(-)
(-)
(-)
P73
(R/W)
(X)
P72
(R/W)
(X)
P71
(R/W)
(X)
P70
(R/W)
(X)
6
5
4
3
2
1
0
P86
(R/W)
(X)
P85
(R/W)
(X)
P84
(R/W)
(X)
P83
(R/W)
(X)
P82
(R/W)
(X)
P81
(R/W)
(X)
P80
(R/W)
(X)
PDR6
bit 7
Address: 00000006H
P67
Read/Write (R/W)
Initial value
(X)
PDR7
bit 7
Address: 00000007H
Read/Write
(-)
Initial value
(-)
PDR8
bit 7
Address: 00000008H
P87
Read/Write (R/W)
Initial value
(X)
(Continued)
117
CHAPTER 4 I/O PORT
(Continued)
PDR9
bit 7
Address: 00000009H
P97
Read/Write (R/W)
Initial value
(X)
PDRA
bit 7
Address: 0000000AH
Read/Write
(-)
Initial value
(-)
PDRB
bit 7
Address: 0000000BH
PB7
Read/Write (R/W)
Initial value
(X)
PDRC
bit 7
Address: 0000000CH
Read/Write
(-)
Initial value
(-)
PDRD
bit 7
Address: 0000000DH
PD7
Read/Write (R/W)
Initial value
(0)
PDRE
bit 7
Address: 0000000EH
PE7
Read/Write (R/W)
Initial value
(X)
PDRF
bit 7
Address: 0000000FH
PF7
Read/Write (R/W)
Initial value
(X)
PDRG
bit 7
Address: 00000010H
Read/Write
(-)
Initial value
(-)
6
5
4
3
2
1
0
P96
(R/W)
(X)
P95
(R/W)
(X)
P94
(R/W)
(X)
P93
(R/W)
(X)
P92
(R/W)
(X)
P91
(R/W)
(X)
P90
(R/W)
(X)
6
5
4
3
2
1
0
(-)
(-)
(-)
(-)
(-)
(-)
PA3
(R/W)
(X)
PA2
(R/W)
(X)
PA1
(R/W)
(X)
PA0
(R/W)
(X)
6
5
4
3
2
1
0
PB6
(R/W)
(X)
PB5
(R/W)
(X)
PB4
(R/W)
(X)
PB3
(R/W)
(X)
PB2
(R/W)
(X)
PB1
(R/W)
(X)
PB0
(R/W)
(X)
6
5
4
3
2
1
0
(-)
(-)
(-)
(-)
(-)
(-)
PC3
(R/W)
(X)
PC2
(R/W)
(X)
PC1
(R/W)
(X)
PC0
(R/W)
(X)
6
5
4
3
2
1
0
PD6
(R/W)
(0)
PD5
(R/W)
(0)
PD4
(R/W)
(0)
PD3
(R/W)
(X)
PD2
(R/W)
(X)
PD1
(R/W)
(X)
PD0
(R/W)
(X)
6
5
4
3
2
1
0
PE6
(R/W)
(X)
PE5
(R/W)
(X)
PE4
(R/W)
(X)
PE3
(R/W)
(X)
PE2
(R/W)
(X)
PE1
(R/W)
(X)
PE0
(R/W)
(X)
6
5
4
3
2
1
0
PF6
(R/W)
(X)
PF5
(R/W)
(X)
PF4
(R/W)
(X)
PF3
(R/W)
(X)
PF2
(R/W)
(X)
PF1
(R/W)
(X)
PF0
(R/W)
(X)
6
5
4
3
2
1
0
(-)
(-)
(-)
(-)
(-)
(-)
PG3
(R/W)
(X)
PG2
(R/W)
(X)
PG1
(R/W)
(X)
PG0
(R/W)
(X)
PDR0 to PDRG are I/O data registers of the I/O port.
These are controlled for input/output by their respective DDR0 to DDRG, PFR0 to PFRG.
118
CHAPTER 4 I/O PORT
■ Data Direction Register (DDR:DDR0 to DDRG)
Figure 4.2-1 Configuration of Data Direction Register (DDR)
DDR0
bit 7
Address: 00000400H
P07
Read/Write (R/W)
Initial value
(0)
DDR1
bit 7
Address: 00000401H
P17
Read/Write (R/W)
Initial value
(0)
DDR2
bit 7
Address: 00000402H
P27
Read/Write (R/W)
Initial value
(1)
DDR3
bit 7
Address: 00000403H
P37
Read/Write (R/W)
Initial value
(0)
DDR4
bit 7
Address: 00000404H
P47
Read/Write (R/W)
Initial value
(0)
DDR5
bit 7
Address: 00000405H
P57
Read/Write (R/W)
Initial value
(0)
DDR6
bit 7
Address: 00000406H
P67
Read/Write (R/W)
Initial value
(0)
DDR7
bit 7
Address: 00000407H
Read/Write
(-)
Initial value
(-)
DDR8
bit 7
Address: 00000408H
P87
Read/Write (R/W)
Initial value
(0)
6
5
4
3
2
1
0
P06
(R/W)
(0)
P05
(R/W)
(0)
P04
(R/W)
(0)
P03
(R/W)
(0)
P02
(R/W)
(0)
P01
(R/W)
(0)
P00
(R/W)
(0)
6
5
4
3
2
1
0
P16
(R/W)
(0)
P15
(R/W)
(0)
P14
(R/W)
(0)
P13
(R/W)
(0)
P12
(R/W)
(0)
P11
(R/W)
(0)
P10
(R/W)
(0)
6
5
4
3
2
1
0
P26
(R/W)
(1)
P25
(R/W)
(1)
P24
(R/W)
(1)
P23
(R/W)
(1)
P22
(R/W)
(1)
P21
(R/W)
(1)
P20
(R/W)
(1)
6
5
4
3
2
1
0
P36
(R/W)
(0)
P35
(R/W)
(0)
P34
(R/W)
(0)
P33
(R/W)
(1)
P32
(R/W)
(1)
P31
(R/W)
(1)
P30
(R/W)
(1)
6
5
4
3
2
1
0
P46
(R/W)
(0)
P45
(R/W)
(0)
P44
(R/W)
(0)
P43
(R/W)
(0)
P42
(R/W)
(0)
P41
(R/W)
(0)
P40
(R/W)
(0)
6
5
4
3
2
1
0
P56
(R/W)
(0)
P55
(R/W)
(0)
P54
(R/W)
(0)
P53
(R/W)
(0)
P52
(R/W)
(0)
P51
(R/W)
(0)
P50
(R/W)
(0)
6
5
4
3
2
1
0
P66
(R/W)
(0)
P65
(R/W)
(0)
P64
(R/W)
(0)
P63
(R/W)
(0)
P62
(R/W)
(0)
P61
(R/W)
(0)
P60
(R/W)
(0)
6
5
4
3
2
1
0
(-)
(-)
(-)
(-)
(-)
(-)
P73
(R/W)
(0)
P72
(R/W)
(0)
P71
(R/W)
(0)
P70
(R/W)
(0)
6
5
4
3
2
1
0
P86
(R/W)
(0)
P85
(R/W)
(0)
P84
(R/W)
(0)
P83
(R/W)
(0)
P82
(R/W)
(0)
P81
(R/W)
(0)
P80
(R/W)
(0)
(Continued)
119
CHAPTER 4 I/O PORT
(Continued)
DDR9
bit 7
Address: 00000409H
P97
Read/Write (R/W)
Initial value
(0)
DDRA
bit 7
Address: 0000040AH
Read/Write
(-)
Initial value
(-)
DDRB
bit 7
Address: 0000040BH
PB7
Read/Write (R/W)
Initial value
(0)
DDRC
bit 7
Address: 0000040CH
Read/Write
(-)
Initial value
(-)
DDRD
bit 7
Address: 0000040DH
PD7
Read/Write (R/W)
Initial value
(1)
6
5
4
3
2
1
0
P96
(R/W)
(0)
P95
(R/W)
(0)
P94
(R/W)
(0)
P93
(R/W)
(0)
P92
(R/W)
(0)
P91
(R/W)
(0)
P90
(R/W)
(0)
6
5
4
3
2
1
0
(-)
(-)
(-)
(-)
(-)
(-)
PA3
(R/W)
(0)
PA2
(R/W)
(0)
PA1
(R/W)
(0)
PA0
(R/W)
(0)
6
5
4
3
2
1
0
PB6
(R/W)
(0)
PB5
(R/W)
(0)
PB4
(R/W)
(0)
PB3
(R/W)
(0)
PB2
(R/W)
(0)
PB1
(R/W)
(0)
PB0
(R/W)
(0)
6
5
4
3
2
1
0
(-)
(-)
(-)
(-)
(-)
(-)
PC3
(R/W)
(0)
PC2
(R/W)
(0)
PC1
(R/W)
(0)
PC0
(R/W)
(0)
6
5
4
3
2
1
0
PD6
(R/W)
(1)
PD5
(R/W)
(1)
PD4
(R/W)
(1)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
DDRE
bit 7
Address: 0000040EH
PE7
Read/Write (R/W)
Initial value
(0)
6
5
4
3
2
1
0
PE6
(R/W)
(0)
PE5
(R/W)
(0)
PE4
(R/W)
(0)
PE3
(R/W)
(0)
PE2
(R/W)
(0)
PE1
(R/W)
(0)
PE0
(R/W)
(0)
DDRF
bit 7
Address: 0000040FH
PF7
Read/Write (R/W)
Initial value
(0)
6
5
4
3
2
1
0
PF6
(R/W)
(0)
PF5
(R/W)
(0)
PF4
(R/W)
(0)
PF3
(R/W)
(0)
PF2
(R/W)
(0)
PF1
(R/W)
(0)
PF0
(R/W)
(0)
6
5
4
3
2
1
0
(-)
(-)
(-)
(-)
(-)
(-)
PG3
(R/W)
(0)
PG2
(R/W)
(0)
PG1
(R/W)
(0)
PG0
(R/W)
(0)
DDRG
bit 7
Address: 00000410H
Read/Write
(-)
Initial value
(-)
DDR0 to DDRG control the I/O direction of the corresponding I/O ports in bits.
If PFR=0, DDR=0: Port input and peripheral input.
DDR=1: Port output.
If PFR=1, the value is the direction is peripheral output regardless of the DDR setting.
120
CHAPTER 4 I/O PORT
■ Port Function Register (PFR, EPFR)
PFR0 to PFR5, PFR7, PFRA to PFRE, PFRG, EPFR2 to EPFR5, EPFRD, EPFRG control the
corresponding peripheral outputs by bit.
Make sure to write "0" to unused bits in PFR and EPFR. If there is no particular entry, pins are set to
peripheral output using PFR=1.
When reading, the value written previously is read.
● PFR0 (P07 to P00)
PFR0
bit
Address: 00000420H
Read/Write
Initial value
7
6
5
4
3
2
1
0
P07
(R/W)
(0)
P06
(R/W)
(0)
P05
(R/W)
(0)
P04
(R/W)
(0)
P03
(R/W)
(0)
P02
(R/W)
(0)
P01
(R/W)
(0)
P00
(R/W)
(0)
If the single chip mode or the external bus 8-bit mode is used
Peripheral outputs
P07
P06
P05
P04
P03
P02
P01
P00
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
D03
D02
D01
D00
If the external bus 16-bit mode is used (PFR0 is not affected)
External data bus
D07
D06
D05
D04
If performing an external interrupt (INT5 to INT0) and a recovery from the STOP mode, set the port PFR
bit corresponding to the external interrupt to "0".
Further, if using the external bus 16-bit mode, inputs are normally enabled, so mask the corresponding bits
using the corresponding the external interrupt permission register.
● PFR1 (P17 to P10)
PFR1
bit
Address: 00000421H
Read/Write
Initial value
7
6
5
4
3
2
1
0
P17
(R/W)
(0)
P16
(R/W)
(0)
P15
(R/W)
(0)
P14
(R/W)
(0)
P13
(R/W)
(0)
P12
(R/W)
(0)
P11
(R/W)
(0)
P10
(R/W)
(0)
Using the single-chip mode
Peripheral outputs
P17
P16
P15
P14
P13
P12
P11
P10
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
D13
D12
D11
D10
D09
D08
Using an external bus (PFR1 is not affected)
External data bus
D15
D14
121
CHAPTER 4 I/O PORT
● PFR2 (P27 to P20) / EPFR2 (P27 to P20)
PFR2
bit
Address: 00000422H
Read/Write
Initial value
7
6
5
4
3
2
1
0
P27
(R/W)
(0)
P26
(R/W)
(0)
P25
(R/W)
(0)
P24
(R/W)
(0)
P23
(R/W)
(0)
P22
(R/W)
(0)
P21
(R/W)
(0)
P20
(R/W)
(0)
EPFR2
bit
Address: 00000602H
Read/Write
Initial value
7
6
5
4
3
2
1
0
P27
(R/W)
(0)
P26
(R/W)
(0)
P25
(R/W)
(0)
P24
(R/W)
(0)
P23
(R/W)
(0)
P22
(R/W)
(0)
P21
(R/W)
(0)
P20
(R/W)
(0)
Using the single-chip mode (EPFR2 is not affected)
P27
P26
P25
P24
P23
P22
P21
P20
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
PFR2, EPFR2 = 00B
A7
A6
A5
A4
A3
A2
A1
A0
01B
Prohibited
Prohibited
Prohibited
Prohibited
Prohibited
Prohibited
Prohibited
Prohibited
10B
A7
A6
A5
A4
A3
A2
A1
A0
11B
Prohibited
Prohibited
Prohibited
Prohibited
Prohibited
Prohibited
Prohibited
Prohibited
Peripheral outputs
Using an external bus
● PFR3 (P37 to P30) / EPFR3 (P37 to P30)
PFR3
bit
Address: 00000423H
Read/Write
Initial value
EPFR3
bit
Address: 00000603H
Read/Write
Initial value
7
6
5
4
3
2
1
0
P37
(R/W)
(0)
P36
(R/W)
(0)
P35
(R/W)
(0)
P34
(R/W)
(0)
P33
(R/W)
(0)
P32
(R/W)
(0)
P31
(R/W)
(0)
P30
(R/W)
(0)
7
6
5
4
3
2
1
0
P37
(R/W)
(0)
P36
(R/W)
(0)
P35
(R/W)
(0)
P34
(R/W)
(0)
P33
(R/W)
(0)
P32
(R/W)
(0)
P31
(R/W)
(0)
P30
(R/W)
(0)
Using the single-chip mode (EPFR3 is not affected)
P37
P36
P35
P34
P33
P32
P31
P30
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
PFR3, EPFR3 = 00B
A15
A14
A13
A12
A11
A10
A9
A8
01B
Prohibited
Prohibited
Prohibited
Prohibited
Prohibited
Prohibited
Prohibited
Prohibited
10B
A15
A14
A13
A12
A11
A10
A9
A8
11B
Prohibited
Prohibited
Prohibited
Prohibited
Prohibited
Prohibited
Prohibited
Prohibited
Peripheral outputs
Using an external bus
122
CHAPTER 4 I/O PORT
● PFR4 (P47 to P40) / EPFR4 (P47 to P40)
PFR4
bit
Address: 00000424H
Read/Write
Initial value
7
6
5
4
3
2
1
0
P47
(R/W)
(0)
P46
(R/W)
(0)
P45
(R/W)
(0)
P44
(R/W)
(0)
P43
(R/W)
(0)
P42
(R/W)
(0)
P41
(R/W)
(0)
P40
(R/W)
(0)
EPFR4
bit
Address: 00000604H
Read/Write
Initial value
7
6
5
4
3
2
1
0
P47
(R/W)
(0)
P46
(R/W)
(0)
P45
(R/W)
(0)
P44
(R/W)
(0)
P43
(R/W)
(0)
P42
(R/W)
(0)
P41
(R/W)
(0)
P40
(R/W)
(0)
Using the single-chip mode (EPFR4 is not affected)
P47
P46
P45
P44
P43
P42
P41
P40
SGO
SGA
SCK3
SOT3
-
SCK0
SOT0
-
PFR4, EPFR4 = 00B
SYSCLK
ASX
-
-
-
-
-
-
01B
P47
P46
P45
P44
P43
P42
P41
P40
10B
SYSCLK
ASX
Prohibited
Prohibited
Prohibited
Prohibited
Prohibited
Prohibited
11B
SGO
SGA
SCK3
SOT3
-
SCK0
SOT0
-
Peripheral outputs
Using an external bus
● PFR5 (P57 to P50) / EPFR5 (P57 to P50)
PFR5
bit
Address: 00000425H
Read/Write
Initial value
EPFR5
bit
Address: 00000605H
Read/Write
Initial value
7
6
5
4
3
2
1
0
P57
(R/W)
(0)
P56
(R/W)
(0)
P55
(R/W)
(0)
P54
(R/W)
(0)
P53
(R/W)
(0)
P52
(R/W)
(0)
P51
(R/W)
(0)
P50
(R/W)
(0)
7
6
5
4
3
2
1
0
P57
(R/W)
(0)
P56
(R/W)
(0)
P55
(R/W)
(0)
P54
(R/W)
(0)
P53
(R/W)
(0)
P52
(R/W)
(0)
P51
(R/W)
(0)
P50
(R/W)
(0)
Using the single-chip mode (EPFR5 is not affected)
P57
P56
P55
P54
P53
P52
P51
P50
OUT1
OUT0
SCK5
SOT5
-
SCK4
SOT4
-
PFR5, EPFR5 = 00B
RDY
WR1X
WR0X
RDX
CS3X
CS2X
CS1X
CS0X
01B
P57
P56
P55
P54
P53
P52
P51
P50
10B
RDY
WR1X
WR0X
RDX
CS3X
CS2X
CS1X
CS0X
11B
OUT1
OUT0
SCK5
SOT5
-
SCK4
SOT4
-
Peripheral outputs
Using an external bus
123
CHAPTER 4 I/O PORT
● PFR6 (P67 to P60)
The PFR register corresponding to this port does not exist. If using as a general-purpose port, make sure to
set the bit corresponding to the ADER register to "0" (See "CHAPTER 23 A/D CONVERTER" for
details).
● PFR7 (P73 to P70)
PFR7
bit
Address: 00000427H
Read/Write
Initial value
Peripheral outputs
7
6
5
4
3
2
1
0
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
P73
(R/W)
(0)
P72
(R/W)
(0)
P71
(R/W)
(0)
P70
(R/W)
(0)
-
-
-
-
P73
P72
P71
P70
-
-
-
-
TX1
--
TX0
-
If performing an external interrupt (INT7/INT6) and a recovery from the STOP mode, set the port PFR bit
corresponding to the external interrupt to "1".
● PFR8 (P87 to P80)
The PFR register corresponding to this port does not exist. If using as a general-purpose port, make sure to
set the bit corresponding to the ADER register to "0" (See "CHAPTER 23 A/D CONVERTER" for
details).
● PFR9 (P97 to P90)
The PFR register corresponding to this port does not exist. If using as a general-purpose port, make sure to
set the bit corresponding to the ADER register to "0" (See "CHAPTER 23 A/D CONVERTER" for
details).
● PFRA (PA3 to PA0)
PFRA
bit
Address: 0000042AH
Read/Write
Initial value
Peripheral outputs
124
7
6
5
4
3
2
1
0
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
PA3
(R/W)
(0)
PA2
(R/W)
(0)
PA1
(R/W)
(0)
PA0
(R/W)
(0)
-
-
-
-
PA3
PA2
PA1
PA0
-
-
-
-
PWM2M3
PWM2P3
PWM1M3
PWM1P3
CHAPTER 4 I/O PORT
● PFRB (PB7 to PB0)
PFRB
bit
Address: 0000042BH
Read/Write
Initial value
Peripheral outputs
7
6
5
4
3
2
1
0
PB7
(R/W)
(0)
PB6
(R/W)
(0)
PB5
(R/W)
(0)
PB4
(R/W)
(0)
PB3
(R/W)
(0)
PB2
(R/W)
(0)
PB1
(R/W)
(0)
PB0
(R/W)
(0)
PB7
PB6
PB6
PB5
PB3
PB2
PB1
PB0
PWM2M1
PWM2P1
PWM1M1
PWM1P1
PWM2M0
PWM2P0
PWM1M0
PWM1P0
● PFRC (PC3 to PC0)
PFRC
bit
Address: 0000042CH
Read/Write
Initial value
Peripheral outputs
7
6
5
4
3
2
1
0
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
PC3
(R/W)
(0)
PC2
(R/W)
(0)
PC1
(R/W)
(0)
PC0
(R/W)
(0)
-
-
-
-
PC3
PC2
PC1
PC0
-
-
-
-
PWM2M2
PWM2P2
PWM1M2
PWM1P2
125
CHAPTER 4 I/O PORT
● PFRD (PD7 to PD0)/EPFRD (PD7 to PD0)
PFRD
bit
Address: 0000042DH
Read/Write
Initial value
EPFRD
bit
Address: 0000060DH
Read/Write
Initial value
7
6
5
4
3
2
1
0
PD7
(R/W)
(0)
PD6
(R/W)
(0)
PD5
(R/W)
(0)
PD4
(R/W)
(0)
PD3
(R/W)
(0)
PD2
(R/W)
(0)
PD1
(R/W)
(0)
PD0
(R/W)
(0)
7
6
5
4
3
2
1
0
PD7
(R/W)
(0)
PD6
(R/W)
(0)
PD5
(R/W)
(0)
PD4
(R/W)
(0)
PD3
(R/W)
(0)
PD2
(R/W)
(0)
PD1
(R/W)
(0)
PD0
(R/W)
(0)
PFRD, EPFRD = 00B
PD7
PD6
PD5
PD4
01B
PPG7
PPG5
PPG3
PPG1
10B
Prohibited
Prohibited
Prohibited
Prohibited
11B
COM3
COM2
COM1
COM0
PD2*1
PD1*1
PD0*1
Prohibited
Prohibited
Prohibited
LIN2*2
LIN1*2
LIN0*2
Prohibited
Prohibited
Prohibited
PD3
Prohibited
*1: PD2 is input to ICU2, PD1 is input to ICU1, and PD0 is input to ICU0.
*2: LIN2 is input to ICU2, LIN1 is input to ICU1, and LIN0 is input to ICU0.
Note: Do not set any of EPFRD bit3 to bit0 to "1".
● PFRE (PE7 to PE0)
PFRE
bit
Address: 0000042EH
Read/Write
Initial value
Peripheral outputs
7
6
5
4
3
2
1
0
PE7
(R/W)
(0)
PE6
(R/W)
(0)
PE5
(R/W)
(0)
PE4
(R/W)
(0)
PE3
(R/W)
(0)
PE2
(R/W)
(0)
PE1
(R/W)
(0)
PE0
(R/W)
(0)
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PWM2M5
PWM2P5
PWM1M5
PWM1P5
PWM2M4
PWM2P4
PWM1M4
PWM1P4
● PFRF (PF6 to PF0)
The PFR register corresponding to this port does not exist. If using as a general-purpose port, make sure to
set the bit corresponding to the ADER register to "0" (See "CHAPTER 23 A/D CONVERTER" for
details).
126
CHAPTER 4 I/O PORT
● PFRG (PG3 to PG0) / EPFRG (PG3 to PG0)
PFRG
bit
Address: 00000430H
Read/Write
Initial value
EPFRG
bit
Address: 0000060DH
Read/Write
Initial value
7
6
5
4
3
2
1
0
(R/W)
(R/W)
-
(R/W)
-
(R/W)
-
PG3
(R/W)
(0)
PG2
(R/W)
(0)
PG1
(R/W)
(0)
PG0
(R/W)
(0)
7
6
5
4
3
2
1
0
(R/W)
-
(R/W)
-
(R/W)
-
(R/W)
-
PG3
(R/W)
(0)
PG2
(R/W)
(0)
PG1
(R/W)
(0)
PG0
(R/W)
(0)
PFRG, EPFRG = 00B
-
-
-
-
PG3
PG2
PG1
PG0
01B
-
-
-
-
PPG6
PPG4
PPG2
PPG0
10B
-
-
-
-
Prohibited
Prohibited
Prohibited
Prohibited
11B
-
-
-
-
TOT2
TOT1
TOT0
Prohibited
127
CHAPTER 4 I/O PORT
4.3
I/O Expansion Functions
This product has the following I/O port expansion functions:
• Port Input Level Select Register (PILR)
• Port State Control Register (PSCR)
Rewriting PILR values is possible only after accessing for a specific writing to PSCR.
Reading is possible at any time.
This expansion function can be performed with byte access only.
■ Port Input Level Select Register (PILR)
Figure 4.3-1 Bit Configuration of Port Input Level Select Register (PILR)
PILR0
bit
Address: 00000540H
Read/Write
Initial value
7
6
5
4
3
2
1
0
P07
(R/W)
(0)
P06
(R/W)
(0)
P05
(R/W)
(0)
P04
(R/W)
(0)
P03
(R/W)
(0)
P02
(R/W)
(0)
P01
(R/W)
(0)
P00
(R/W)
(0)
PILR1
bit
Address: 00000541H
Read/Write
Initial value
7
6
5
4
3
2
1
0
P17
(R/W)
(0)
P16
(R/W)
(0)
P15
(R/W)
(0)
P14
(R/W)
(0)
P13
(R/W)
(0)
P12
(R/W)
(0)
P11
(R/W)
(0)
P10
(R/W)
(0)
PILR5
bit
Address: 00000545H
Read/Write
Initial value
7
6
5
4
3
2
1
0
P57
(R/W)
(0)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
PILR is the register for switching pin input levels. The corresponding bit input level can be set to either
CMOS automotive schmitt-trigger (VIH/VIL=0.8/0.5 Vcc) or CMOS schmitt-trigger (VIH/VIL=0.7/0.3 VCC)
by setting this register.
PILRx
Name
VIH
VIL
0
CMOS automotive schmitt-trigger
0.8 × Vcc
0.5 × Vcc
1
CMOS schmitt-trigger
0.7 × Vcc
0.3 × Vcc
The pins in this product are normally CMOS Automotive Schmitt-Trigger.
128
CHAPTER 4 I/O PORT
■ Port Status Control Register (PSCR)
Figure 4.3-2 Bit Configuration of Port State Control Register (PSCR)
PSCR
bit
Address: 000004FCH
Read/Write
Initial value
7
6
5
4
3
2
1
0
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
PSCR is the register that controls PILR rewriting. This register is enabled for byte write access only. It
cannot be read. When reading, an unspecified value will be read.
For details, see "●Rewriting of port expansion function registers".
● Rewriting of port expansion function registers
Before rewriting the values in the PPER, PPCR, and PILR registers, implement write-access in the order
"A5H" to "5AH" for PSCR (000004FCH). An example of the assembler code is shown below.
ldi #0x000004fc, r0
// r0=PSCR address
ldi:8 #0xA5, r1
// r1=A5
ldi:8 #0x5A, r2
// r2=5A
stb r1, @r0
// write A5 to PSCR
stb r2, @r0
// write 5A to PSCR
ldub @r0, r0
// dummy read
The PSCR register is write-only. Consequently, if the register status is not known, make sure to insert a
dummy-write other than "A5H" or "5AH" once before write-access.
PILR register rewrite is possible only once for each register after the write sequence described above has
been performed. If implementing an rewrite again after the register has been refreshed, it is necessary to
perform the write sequence again.
129
CHAPTER 4 I/O PORT
Figure 4.3-3 Write-access Sequence to PSCR Register
Write prohibited
Write access to
PSCR
A5H ?
NO
YES
Write access to
PSCR
5AH ?
NO
YES
Read access to
PSCR
Write enabled
authorized
permitted
Write access to
PSCR
Read access to
PSCR
● Notes for Use
If changing the values of the input selection register PILR, make sure first to disable the functions for the
resource that is inputting to the relevant pins.
130
CHAPTER 5
INTERRUPT CONTROLLER
This chapter outlines the interrupt controller, describes
its register configuration/functions and its operations.
5.1
Overview of Interrupt Controller
5.2
Register List of Interrupt Controller
5.3
Operation of Interrupt Controller
131
CHAPTER 5 INTERRUPT CONTROLLER
5.1
Overview of Interrupt Controller
The interrupt controller controls interrupt reception and arbitration processing.
■ Hardware Components of Interrupt Controller
The interrupt controller consists of the following register and circuit:
• ICR registers
• Interrupt priority judgment circuit
• Interrupt level and interrupt number (vector) generator
• Hold request cancellation request generator
■ Major Functions of Interrupt Controller
The interrupt controller provides the following functions:
• NMI request/interrupt request detection
• Priority judgment (based on the level and number)
• Transmission of judgment result representing the interrupt level of the interrupt cause (to the CPU)
• Transmission of judgment result representing the interrupt number of the interrupt cause (to the
CPU)
• Instruction for return from STOP mode due to an interrupt at an NMI/interrupt level that is not
"11111B" (to the CPU)
Note:
MB91245/S series do not support NMIs.
132
CHAPTER 5 INTERRUPT CONTROLLER
5.2
Register List of Interrupt Controller
This section explains the configuration and the function of the register used by the
interrupt controller.
■ Register List of Interrupt Controller
Figure 5.2-1 Register List of Interrupt Controller
bit
Address: 00000440H
7
-
6
-
5
-
4
ICR4
3
ICR3
2
ICR2
1
ICR1
0
ICR0
ICR00
Address: 00000441H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR01
Address: 00000442H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR02
Address: 00000443H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR03
Address: 00000444H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR04
Address: 00000445H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR05
Address: 00000446H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR06
Address: 00000447H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR07
Address: 00000448H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR08
Address: 00000449H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR09
Address: 0000044AH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR10
Address: 0000044BH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR11
Address: 0000044CH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR12
Address: 0000044DH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR13
Address: 0000044EH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR14
Address: 0000044FH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR15
Address: 00000450H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR16
Address: 00000451H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR17
Address: 00000452H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR18
Address: 00000453H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR19
Address: 00000454H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR20
Address: 00000455H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR21
Address: 00000456H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR22
Address: 00000457H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR23
Address: 00000458H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR24
Address: 00000459H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR25
Address: 0000045AH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR26
Address: 0000045BH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR27
Address: 0000045CH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR28
Address: 0000045DH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR29
Address: 0000045EH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR30
Address: 0000045FH
-
-
-
ICR4
R/W
ICR3
R/W
ICR2
R/W
ICR1
R/W
ICR0
R/W
ICR31
(Continued)
133
CHAPTER 5 INTERRUPT CONTROLLER
(Continued)
134
bit
Address: 00000460H
7
-
6
-
5
-
4
ICR4
3
ICR3
2
ICR2
1
ICR1
0
ICR0
ICR32
Address: 00000461H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR33
Address: 00000462H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR34
Address: 00000463H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR35
Address: 00000464H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR36
Address: 00000465H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR37
Address: 00000466H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR38
Address: 00000467H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR39
Address: 00000468H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR40
Address: 00000469H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR41
Address: 0000046AH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR42
Address: 0000046BH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR43
Address: 0000046CH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR44
Address: 0000046DH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR45
Address: 0000046EH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR46
Address: 0000046FH
-
-
-
-
-
-
ICR3
R/W
LVL3
R/W
ICR2
R/W
LVL2
R/W
ICR1
R/W
LVL1
R/W
ICR0
R/W
LVL0
R/W
ICR47
Address: 00000045H
ICR4
R/W
LVL4
R/W
HRCL
CHAPTER 5 INTERRUPT CONTROLLER
■ Block Diagram of Interrupt Controller
Figure 5.2-2 Block Diagram of Interrupt Controller
UNMI
WAKEUP ("1" when LEVEL is unequal to 11111B)
Priority judgment
NMI
NMI
processing
LEVEL4 to LEVEL0
5
/
LEVEL judgment
LEVEL,
VECTOR
generated
ICR00
RI00
VECTOR
judgment
6
/
HLDREQ
withdrawal
request
MHALTI
VCT5 to VCT0
ICR47
RI47
(DLYIRQ)
R-bus
135
CHAPTER 5 INTERRUPT CONTROLLER
5.2.1
Interrupt Control Register (ICR)
One ICR (Interrupt Control Register) is provided for each interrupt input. It sets an
interrupt level for each interrupt request.
■ Bit Configuration of Interrupt Control Register (ICR)
Figure 5.2-3 Bit Configuration of Interrupt Control Register (ICR)
Address:
ch.00 000440H to
bit
7
-
6
-
5
-
ch.47 00046FH
4
ICR4
3
ICR3
2
ICR2
1
ICR1
0
ICR0
R/W
R/W
R/W
R/W
R/W
Initial value
---11111B
This is an interrupt control register. One ICR is provided for each interrupt input. It sets an interrupt level
for each interrupt request.
[bit4 to bit0] ICR4 to ICR0
These bits, which are the interrupt level setting bits, represent the interrupt level that is set for the
interrupt request.
If the interrupt level that is set on this register is equal to or higher than the level mask value that is set
on the ILM register in the CPU, the CPU masks the interrupt request.
Upon reset, the interrupt level is initialized to "11111B". Table 5.2-1 indicates the Relationship between
Possible Interrupt Level Setting Bits and the Interrupt Levels.
Table 5.2-1 Relationship between Possible Interrupt Level Setting Bits and the Interrupt Levels.
ICR4
0
ICR3
0
ICR2
0
ICR1
0
ICR0
0
0
0
1
1
1
0
14
0
1
1
1
1
15
NMI
1
0
0
0
0
16
Highest level that can be set
1
0
0
0
1
17
(High)
1
0
0
1
0
18
1
0
0
1
1
19
1
0
1
0
0
20
1
0
1
0
1
21
1
0
1
1
0
22
1
0
1
1
1
23
1
1
0
0
0
24
1
1
0
0
1
25
1
1
0
1
0
26
1
1
0
1
1
27
1
1
1
0
0
28
1
1
1
0
1
29
1
1
1
1
0
30
1
1
1
1
1
31
Note: ICR4 is always set to "1" and cannot write "0".
136
Interrupt level
System reserved
(Low)
Interrupt disabled
CHAPTER 5 INTERRUPT CONTROLLER
■ HRCL (Hold Request Cancel Level Register)
bit
Address: 00000045H
7
-
6
-
5
-
4
LVL4
R/W
3
LVL3
R/W
2
LVL2
R/W
1
LVL1
R/W
0
LVL0
R/W
Initial value
0--11111B
This register is used to set a level for holding request withdrawal request generation.
[bit7 to bit5] reserved bits
[bit4 to bit0] LVL4 to LVL0
These bits specify an interrupt level that is used when issuing a holding request cancellation request to
the bus master.
If an interrupt request whose level is higher than the interrupt level set on this register is generated, a
holding request cancellation request is issued to the bus master.
The LVL4 bit is always set to "1" and cannot write "0".
137
CHAPTER 5 INTERRUPT CONTROLLER
5.3
Operation of Interrupt Controller
This section explains operations of interrupt controller including the following.
• Priority evaluation
• Hold request cancel/request
• Returning from standby mode (Stop/sleep)
■ Priority Judgment
If multiple interrupts have occurred at the same time, an interrupt controller identifies the interrupt factor
with the highest priority and sends its interrupt level and number to the CPU.
The criteria for judging the priorities of interrupt causes are as follows:
(1) NMI
(2) Interrupt cause that satisfies the following conditions:
• The interrupt level value is not 31 (31 indicates disabling of interrupts).
• The interrupt level value is the lowest (Cause1)
• The interrupt number is the smallest in the Cause 1.
If no interrupt cause is identified based on the above criteria, an interrupt level of 31 (11111B) is issued. In
this event, the interrupt number is indefinite.
Table 5.3-1 indicates how the interrupt causes relate to the interrupt numbers and interrupt levels.
138
CHAPTER 5 INTERRUPT CONTROLLER
Table 5.3-1 Vector Table (1 / 3)
Interrupt
number
Interrupt cause
Interrupt level
Offset
TBR default
address
DMA
activation
trigger
Decimal
Hexadecimal
Reset
0
00
-
3FCH
000FFFFCH
-
Mode vector
1
01
-
3F8H
000FFFF8H
-
System reserved
2
02
-
3F4H
000FFFF4H
-
System reserved
3
03
-
3F0H
000FFFF0H
-
System reserved
4
04
-
3ECH
000FFFECH
-
System reserved
5
05
-
3E8H
000FFFE8H
-
System reserved
6
06
-
3E4H
000FFFE4H
-
Coprocessor absent trap
7
07
-
3E0H
000FFFE0H
-
Coprocessor error trap
8
08
-
3DCH
000FFFDCH
-
INTE instruction
9
09
-
3D8H
000FFFD8H
-
System reserved
10
0A
-
3D4H
000FFFD4H
-
System reserved
11
0B
-
3D0H
000FFFD0H
-
Step trace trap
12
0C
-
3CCH
000FFFCCH
-
NMI request (tool)
13
0D
-
3C8H
000FFFC8H
-
000FFFC4H
-
Undefined-instruction exception
14
0E
-
3C4H
NMI request
15
0F
Always 15 (FH)
3C0H
000FFFC0H
-
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
6
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
7
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
-
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
-
000FFFACH
-
External interrupt 4
20
14
ICR04
3ACH
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
-
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
-
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
-
Reload timer 0 underflow
24
18
ICR08
39CH
000FFF9CH
8
Reload timer 1 underflow
25
19
ICR09
398H
000FFF98H
9
Reload timer 2 underflow
26
1A
ICR10
394H
000FFF94H
10
UART0 (reception completed, reception error)
27
1B
ICR11
390H
000FFF90H
0
UART0 (transmission completed)
28
1C
ICR12
38CH
000FFF8CH
3
LIN-UART0
(reception completed, reception error,
LIN Synch break, bus idle)
29
1D
ICR13
388H
000FFF88H
1
LIN-UART0 (transmission completed)
30
1E
ICR14
384H
000FFF84H
4
LIN-UART1 (reception completed, reception
error, LIN Synch break, bus idle)
31
1F
ICR15
380H
000FFF80H
2
139
CHAPTER 5 INTERRUPT CONTROLLER
Table 5.3-1 Vector Table (2 / 3)
Interrupt
number
Interrupt cause
Interrupt level
Offset
TBR default
address
DMA
activation
trigger
Decimal
Hexadecimal
LIN-UART1 (transmission completed)
32
20
ICR16
37CH
000FFF7CH
5
LIN-UART2
(reception completed, reception error,
LIN Synch break, bus idle)
33
21
ICR17
378H
000FFF78H
-
LIN-UART2 (transmission completed)
34
22
ICR18
374H
000FFF74H
-
CAN0 reception/transmission completed,
node status transition
35
23
ICR19
370H
000FFF70H
-
CAN1 reception/transmission completed,
node status transition
36
24
ICR20
36CH
000FFF6CH
-
System reserved
37
25
ICR21
368H
000FFF68H
-
System reserved
38
26
ICR22
364H
000FFF64H
-
System reserved
39
27
ICR23
360H
000FFF60H
-
PWC measurement completed
40
28
ICR24
35CH
000FFF5CH
-
PWC overflow
41
29
ICR25
358H
000FFF58H
-
DMAC transfer completed, transfer error
42
2A
ICR26
354H
000FFF54H
-
A/D Converter
43
2B
ICR27
350H
000FFF50H
14
Real-time clock
Hour/minute/second overflow, correction
completed
44
2C
ICR28
34CH
000FFF4CH
-
System reserved
45
2D
ICR29
348H
000FFF48H
-
Main oscillator stabilization wait timer
46
2E
ICR30
344H
000FFF44H
-
Time-base timer overflow
47
2F
ICR31
340H
000FFF40H
-
PPG0/1 underflow
48
30
ICR32
33CH
000FFF3CH
-
PPG2/3 underflow
49
31
ICR33
338H
000FFF38H
-
000FFF34H
-
PPG4/5 underflow
50
32
ICR34
334H
PPG6/7 underflow
51
33
ICR35
330H
000FFF30H
-
16-bit free-run timer 0 overflow
and OCU0 compare match clear
52
34
ICR36
32CH
000FFF2CH
-
16-bit free-run timer 1 overflow
53
35
ICR37
328H
000FFF28H
-
000FFF24H
-
ICU0 (fetch)
54
36
ICR38
324H
ICU1 (fetch)
55
37
ICR39
320H
000FFF20H
-
ICU2 (fetch)
56
38
ICR40
31CH
000FFF1CH
-
ICU3 (fetch)
57
39
ICR41
318H
000FFF18H
-
OCU0 (match)
58
3A
ICR42
314H
000FFF14H
-
OCU1 (match)
59
3B
ICR43
310H
000FFF10H
-
000FFF0CH
-
System reserved
60
3C
ICR44
30CH
System reserved
61
3D
ICR45
308H
000FFF08H
-
Sound generator designation counting completed
62
3E
ICR46
304H
000FFF04H
-
140
CHAPTER 5 INTERRUPT CONTROLLER
Table 5.3-1 Vector Table (3 / 3)
Interrupt
number
Interrupt cause
Interrupt level
Offset
TBR default
address
DMA
activation
trigger
Decimal
Hexadecimal
Delay interrupt factor bit
63
3F
ICR47
300H
000FFF00H
-
System reserved (used by REALOS)
64
40
-
2FCH
000FFEFCH
-
System reserved (used by REALOS)
65
41
-
2F8H
000FFEF8H
-
System reserved
66
42
-
2F4H
000FFEF4H
-
System reserved
67
43
-
2F0H
000FFEF0H
-
System reserved
68
44
-
2ECH
000FFEECH
-
System reserved
69
45
-
2E8H
000FFEE8H
-
System reserved
70
46
-
2E4H
000FFEE4H
-
System reserved
71
47
-
2E0H
000FFEE0H
-
System reserved
72
48
-
2DCH
000FFEDCH
-
System reserved
73
49
-
2D8H
000FFED8H
-
System reserved
74
4A
-
2D4H
000FFED4H
-
System reserved
75
4B
-
2D0H
000FFED0H
-
System reserved
76
4C
-
2CCH
000FFECCH
-
System reserved
77
4D
-
2C8H
000FFEC8H
-
System reserved
78
4E
-
2C4H
000FFEC4H
-
System reserved
79
4F
-
2C0H
000FFEC0H
-
-
2BCH
to
000H
000FFEBCH
to
000FFC00H
-
Used by INT Instruction
80
to
255
50
to
FF
Note: This product does not support NMIs.
■ Hold Request Cancel Request
When a high-priority interrupt needs to be serviced when the CPU has been put on hold (during DMA
transfer), it is necessary to request the hold request issuer to cancel the hold request. Use the HRCL
register to set the interrupt level as the reference level for generating the hold request cancel request.
● Conditions for generating a hold request cancel request
A hold request cancel request is issued to the DMAC when an interrupt source of a higher interrupt level
than that set in the HRCL register occurs.
Interrupt level set in the HRCL register > Interrupt level after priority evaluation → Cancel request
generated
Interrupt level set in the HRCL register ≤ Interrupt level after priority evaluation → No cancel request
Once issued, the cancel request remains in effect until the interrupt source causing that request is cleared,
accordingly leaving DMA transfer prevented from being executed. Therefore, be sure to clear the relevant
interrupt source.
141
CHAPTER 5 INTERRUPT CONTROLLER
● Interrupt levels available
The HRCL register accepts a value from "10000B" to "11111B" like the ICR register.
If the HRCL register is set to "11111B", a cancel request is generated for every level of interrupt. If it is set
to "10000B", a cancel request is generated for NMIs only.
Table 5.3-2 lists the interrupt levels for which a hold request cancel request is generated.
Table 5.3-2 Setting Interrupt Level to Generate Hold Request Cancel Request
HRCL Register
Interrupt Level for Which Cancel Request Is Generated
16
NMI only
17
NMI or interrupt level 16
18
NMI or interrupt levels 16/17
–
–
31
NMI or interrupt levels 16 to 30 [initial value]
After reset, DMA transfer is suppressed for any level of interrupt. Since DMA transfer is not executed with
an interrupt generated, set the HRCL register to an appropriate value.
142
CHAPTER 5 INTERRUPT CONTROLLER
■ Return from Standby Mode (Stop/Sleep)
This module provides a function used to return to ordinary mode from the stop mode when an interrupt
request is generated.
When at least one interrupt request, including an NMI, (whose interrupt level is not "11111B") is generated
from a peripheral device, a request to return from stop mode is issued to the clock controller.
Since the priority judgment circuit resumes its operation when it is supplied with the clock after return from
stop mode, the CPU will continue to execute the current instructions until the judgment result comes from
the priority judgment circuit.
The register in the interrupt controller can be accessed even in the sleep mode.
Note:
If you do not want a particular interrupt cause to be a trigger of return from stop/sleep mode, set the
level of this interrupt cause to "11111B" on the control register corresponding to the pertinent
peripheral device.
■ Example of Using the Hold Request Cancel Register (HRCL)
To execute a high-priority process during DMA transfer, the CPU must request the DMA controller to
cancel the hold request for releasing itself from the hold status. That is, the HRCL can use an interrupt to
make the DMA controller to cancel a hold request, or to give priority to the CPU.
● Control registers
Hold request cancel level (HRCL) register: interrupt controller
If an interrupt of a higher level than that set in this register is generated, a hold request cancel request is
issued to the DMA controller. This register is used to set that reference level.
Interrupt control register (ICR): interrupt controller
A higher level than that in the HRCL register is set in the ICR register corresponding to the interrupt
source to be used.
● Hardware configuration
The flow of each signal for the hold request is illustrated below.
Figure 5.3-1 Flow of Each Signal of Hold Request
This module
IRQ
Bus access request
DHREQ: D bus hold request
DHREQ
MHALTI
DHACK: D bus hold acknowledge
I-unit
DMA
B-unit
CPU
(ICR)
IRQ: Interrupt request
MHALTI: Hold request cancel request
DHACK
(HRCL)
● Sequence
Figure 5.3-2 shows the INTC-2 interrupt level that is higher than the level set in the HRCL register.
143
CHAPTER 5 INTERRUPT CONTROLLER
Figure 5.3-2 Interrupt Level: HRCL < ICR (LEVEL)
RUN
Bus hold
Interrupt handling
1)
CPU
Bus hold (DMA transfer)
Example of interrupt routine
2)
Bus access request
1)Clearing of interrupt source
DHREQ
to
DHACK
2)RETI
IRQ
LEVEL
MHALTI
If an interrupt request is generated and the interrupt level becomes higher than that set in the HRCL
register, MHALTI becomes active to the DMA controller. Then the DMA controller cancels the access
request, allowing the CPU to return from the hold status for servicing the interrupt.
Given below shows the INTC-2 interrupt level for multiple interrupts.
Figure 5.3-3 INTC-3 Interrupt Level: HRCL < ICR (Interrupt I) < ICR (Interrupt II)
RUN
CPU
Bus access request
DHREQ
DHACK
IRQ1
IRQ2
LEVEL
MHALTI
144
Bus hold
Interrupt I
Interrupt handling II
3)
4)
Interrupt handling I
1)
2)
Bus hold (DMA transfer)
CHAPTER 5 INTERRUPT CONTROLLER
Example of interrupt routine
1), 3) Interrupt source clear
to
2), 4) RETI
In the above example, an interrupt of a higher priority occurs during execution of interrupt routine I.
DHREQ remains low when an interrupt of a higher level than the interrupt level set in the HRCL register
has been generated.
Note:
Pay due attention to the relationships between the interrupt levels set in the HRCL and ICR
registers.
145
CHAPTER 5 INTERRUPT CONTROLLER
146
CHAPTER 6
EXTERNAL INTERRUPT
CONTROLLER
This chapter outlines the external interrupt controller
and describes its register configuration/functions and
its operation.
6.1
Overview of External Interrupt Controller
6.2
Registers of External Interrupt Controller
6.3
External Interrupt Control Operation
147
CHAPTER 6 EXTERNAL INTERRUPT CONTROLLER
6.1
Overview of External Interrupt Controller
The external interrupt controller is a block that controls external interrupt requests
which are given to INT0 to INT7.
External interrupt inputs can be selected from "H", "L", "rising edge", or "falling edge"
as the request levels to be detected.
■ Register List of External Interrupt Controller
Following figure shows the register list of the external interrupt controller.
Figure 6.1-1 Register List of the External Interrupt Controller
bit
EIRR0 address: 00000040H
15
ER7
14
ER6
13
ER5
12
ER4
11
ER3
10
ER2
9
ER1
8
ER0
Initial value
00000000B
[R/W]
bit
ENIR0 address: 00000041H
7
EN7
6
EN6
5
EN5
4
EN4
3
EN3
2
EN2
1
EN1
0
EN0
bit
ELVR0 address: 00000042H
15
LB7
14
LA7
13
LB6
12
LA6
11
LB5
10
LA5
9
LB4
8
LA4
Initial value
00000000B
[R/W]
Initial value
00000000B
[R/W]
bit
ELVR0 address: 00000043H
7
LB3
6
LA3
5
LB2
4
LA2
3
LB1
2
LA1
1
LB0
0
LA0
Initial value
00000000B
[R/W]
■ Block Diagram of External Interrupt Controller
Figure 6.1-2 shows a block diagram for external interrupt controller.
Figure 6.1-2 Block Diagram of External Interrupt Controller
R-bus
16
Interrupt
request
16
16
16
148
Interrupt enabled register
Gate
Source F/F
Interrupt source register
Request level setting register
Edge detection
circuit
8
INT0 to
INT7
CHAPTER 6 EXTERNAL INTERRUPT CONTROLLER
6.2
Registers of External Interrupt Controller
This section describes the register configuration and functions of the external interrupt
control block.
■ Details of Registers in External Interrupt Control Block
The following three registers are available in the external interrupt control block.
• Interrupt Enabled Register (ENIR: ENable Interrupt Request Register)
• External Interrupt Source Register (EIRR: External Interrupt Request Register)
• External Interrupt Request Level setting Register (ELVR: External LeVel Register)
149
CHAPTER 6 EXTERNAL INTERRUPT CONTROLLER
6.2.1
Interrupt Enabled Register
(ENIR: ENable Interrupt Request Register)
This section describes the bit configuration and functions of the interrupt enabled
register (ENIR).
■ Interrupt Enabled Register (ENIR: ENable Interrupt Request Register)
Figure 6.2-1 Bit Configuration of Interrupt Enabled Register (ENIR)
bit
ENIR0 address: 00000041H
7
EN7
6
EN6
5
EN5
4
EN4
3
EN3
2
EN2
1
EN1
0
EN0
Initial value
00000000B
[R/W]
Each interrupt request outputs corresponding to the bit that was written as "1" to this register is enabled
(EN0 controls INT0 enable), and the request is output to the interrupt controller. The pin corresponding to
the bit that has been written as "0" stores the interrupt source, but this request is not sent to the interrupt
controller.
150
CHAPTER 6 EXTERNAL INTERRUPT CONTROLLER
6.2.2
External Interrupt Source Register
(EIRR: External Interrupt Request Register)
This section describes the bit configuration and functions of the external interrupt
source register (EIRR).
■ External Interrupt Request Register (EIRR: External Interrupt Request Register)
Figure 6.2-2 Bit Configuration of External Interrupt Source Register (EIRR)
bit
EIRR0 address: 00000040H
15
ER7
14
ER6
13
ER5
12
ER4
11
ER3
10
ER2
9
ER1
8
ER0
Initial value
00000000B
[R/W]
If this EIRR register is "1" when read, an external interrupt request has been sent to the pin corresponding
to that bit.
Further, if "0" is written to this register, the flip-flop request of the corresponding bit will be cleared.
Writing "1" is disabled.
When reading during a read-modify-write (RMW) instruction, "1" is read.
151
CHAPTER 6 EXTERNAL INTERRUPT CONTROLLER
6.2.3
External Interrupt Request Level Setting Register
(ELVR: External LeVel Register)
This section describes the bit configuration and functions of the external interrupt
request level setting register (ELVR).
■ External Interrupt Request Level Setting Register (ELVR: External LeVel Register)
Figure 6.2-3 Bit Configuration of External Interrupt Request Level Setting Register (ELVR)
bit
ELVR0 address: 00000042H
15
LB7
14
LA7
13
LB6
12
LA6
11
LB5
10
LA5
9
LB4
8
LA4
Initial value
00000000B
[R/W]
bit
ELVR0 address: 00000043H
7
LB3
6
LA3
5
LB2
4
LA2
3
LB1
2
LA1
1
LB0
0
LA0
Initial value
00000000B
[R/W]
Two bits each are allocated to INT0 to INT7 to make the following configuration. For the request input
level, if the inputs are active level, the relevant bit is reset even if the EIRR bits are cleared.
To use recovery from stop mode, set to either "H" level or "L" level requests.
Table 6.2-1 ELVR Allocation Table
LBx
LAx
Operation
0
0
"L"-level request
0
1
"H"-level request
1
0
Rising edge request
1
1
Falling edge request
Note:
Changing the external interrupt request level may cause an interrupt source internally. After
changing the external interrupt request level, therefore, clear the external interrupt source register
(EIRR).
Before writing to clear the external interrupt source register, read external interrupt request level
register once.
152
CHAPTER 6 EXTERNAL INTERRUPT CONTROLLER
6.3
External Interrupt Control Operation
This section describes the external interrupt operations.
■ External Interrupt Operations
After setting the request level and enable register, if a request that has been set using the ELVR register is
sent to the corresponding pin, this module sends an interrupt request signal to the interrupt controller. As a
result of identifying the interrupt priority created within the interrupt controller at the same time, if the
interrupt from this resource is the highest priority, the relevant interrupt will be created.
Figure 6.3-1 External Interrupt Operations
CPU
Interrupt controller
External interrupt
Resource request
ELVR
EIRR
ENIR
IL
ICR y y
CMP
ICR x x
CMP
ILM
Souece
■ Recovery from Standby
If an external interrupt is used on recovery from standby in the clock stop mode, set the input requests to
"H" level or "L" level requests.
With the edge requests, recovery from a stop in clock stop mode cannot be performed.
Make sure to disable unused channels before entering the standby mode.
■ Operation Procedure of External Interrupt
To set each register existing in the external interrupt block, take the following steps:
1. Set that general-purpose I/O port as an input port which also serves as a pin to be used as an external
interrupt input.
2. Set the relevant bit in the interrupt enable register (ENIR) to disable interrupts.
3. Set the relevant bit in the external interrupt request level setting register (ELVR).
4. Read the external interrupt request level setting register (ELVR).
5. Clear the relevant bit in the external interrupt source register (EIRR).
6. Set the relevant bit in the interrupt enable register (ENIR) to enable interrupts.
In steps 5 and 6, data can be written simultaneously in 16 bits.
When setting the registers in this module, make sure to disable the interrupt enabled register first. Further,
before enabling the enable register, make sure to clear the source registers. This is to avoid interrupt
sources being sent by mistake during a register setting or an interrupt enable.
153
CHAPTER 6 EXTERNAL INTERRUPT CONTROLLER
■ External Interrupt Request Levels
• When the request level is edge requests, the pulse width requires three machine cycles minimum
(peripheral clock machine cycles) to detect the edge.
• When the request input level is a level setting, the required pulse width is a minimum of 3 machine
cycles. While the interrupt input pin is holding its active level, the interrupt request to the interrupt
controller keeps on being generated even with the external interrupt source register cleared.
• If setting the request input level, the request input will be sent from outside and then even if
abandoned, the input will be stored in the internal source storage circuit, so requests to the interrupt
controller will still be active.
To cancel requests to the interrupt controller, it is necessary to clear the source register.
Figure 6.3-2 Clearing the Source Storage Circuit During Level Configuration
Interrupt input
Level
detection
Source F/F
(Souece storage circuit)
Enable gate
Interrupt controller
Continues to store source until cleared
Figure 6.3-3 Interrupt Source during Interrupt Enable, and Interrupt Requests to the Interrupt Controller
"H" level
Interrupt input
Interrupt request to
interrupt controller
Inactive due to source F/F
Notes:
• Interrupt inputs require three machine cycles minimum.
• If HIZ of bit5 of the STCR (Standby Control Register) in the external pin is set to "1" in STOP and
a high impedance pin output is performed, inputs will be enabled by INT0 to INT5 setting PFR0
(Port Function 0 Register) bit5 to bit0 to "0", and INT6, INT7 setting PFR7 register bit0, bit2 to "1".
154
CHAPTER 6 EXTERNAL INTERRUPT CONTROLLER
■ Notes If Restoring from STOP Status Performed Using an External Interrupt
During STOP status, external interrupt signals that are first entered to the INT pin are entered
asynchronously, to enable recovery from the STOP status. The period from that STOP being released to the
passage of oscillation stabilization wait time, however, there is a period during which other external
interrupt signal inputs cannot be identified (Period b+c+d for Figure 6.3-4). To synchronize external input
signals after the STOP has been released with the internal clock, while the clock is not stable, interrupt
sources cannot be stored.
Consequently, if sending external interrupt inputs after the STOP has been released, input external interrupt
signals after the oscillation stabilization wait time has elapsed.
Figure 6.3-4 Recovery Operation Sequence Using External Interrupts from STOP Status
INT1
INT0
Internal
STOP
Regulator
12μs
"H"
"L"
Internal
operation
(RUN)
Implement command (RUN)
X0
Internal
clock
Interrupt flag clear
INTR0
INTE0
"1" (Set to enable before switching to STOP mode)
INTR1
INTE1
"1" enable (Set before switching to STOP mode)
(e)RUN
(a) STOP (b) Regulator stabilization wait time (d) Oscillation stabilization wait time
(c) Oscillator oscillation time
155
CHAPTER 6 EXTERNAL INTERRUPT CONTROLLER
■ Recovery Operations from STOP Status
The STOP recovery operation using external interrupts from existing circuits is performed as described
below.
● Processing before transiting to STOP
External Interrupt Configuration
It is necessary to permit the interrupt input path in STOP status before the device transits to STOP
status. These configuration are made using the PFR (Port Function Register). Under normal conditions
(i.e., any status other than STOP), the interrupt input path is permitted, so there is no need for special
recognition. In STOP status, however, the input path is controlled by the PFR register value.
Pin name
Configuration during recovery from STOP status using external interrupts
P70/(RX1)/INT7
Set PFR7 bit2 to "1".
P72/(RX0)/INT6
Set PFR7 bit0 to "1".
P05/SEG29/INT5/D05
Set PFR0 bit5 to "0".
P04/SEG28/INT4/D04
Set PFR0 bit4 to "0".
P03/SEG27/INT3/D03
Set PFR0 bit3 to "0".
P02/SEG26/INT2/D02
Set PFR0 bit2 to "0".
P01/SEG25/INT1/D01
Set PFR0 bit1 to "0".
P00/SEG24/INT0/D00
Set PFR0 bit0 to "0".
External Interrupt Inputs
If recovering from STOP status, the external interrupt signals send an input signal asynchronously.
When this interrupt input is asserted, the internal STOP signal is immediately turned OFF. At the same
time, the external interrupt circuit is switched so as to synchronize other level interrupt inputs.
● Regulator Stabilization Wait Time
When the internal STOP signal is turned OFF, the switching operation from the regulator on STOP to
the regulator on RUN will start. If the internal operations start before the voltage output of the regulator
on RUN has stabilized, stabilization wait time for the internal outputs voltage will be required due to
operational instability, and approx. 12μs will be set aside as regulator stabilization wait time. During
this time, the clock will stop.
● Oscillator Oscillation Time
After the regulator stabilization wait time has ended, the clock will start to oscillate. The oscillator
oscillation time depends on the oscillator used.
● Oscillation Stabilization Wait Time
After the oscillator oscillation time, an oscillation stabilization wait time is taken inside the device. The
oscillation stabilization wait time is specified by bits OS1 and OS0 on the standby control register. After
the oscillation stabilization wait time has ended, the internal clock is supplied, and in addition to the
activation of interrupt instruction operations from the external interrupt, it also becomes possible to
receive external interrupt sources other than the recovery from STOP request.
156
CHAPTER 7
REALOS-RELATED
HARDWARE
A REALOS-related hardware is used by a Realtime OS,
therefore, when using with REALOS, it cannot be used
by user programs.
This chapter outlines the delay interrupt module and the
bit search module and also describes their register
configurations, functions and operations.
7.1
Delay Interrupt Module
7.2
Bit Search Module
157
CHAPTER 7 REALOS-RELATED HARDWARE
7.1
Delay Interrupt Module
The delay interrupt module is a module that generates interrupts for switching tasks.
Using this module, it is possible to generate and cancel interrupt requests to the CPU
using software.
■ Register List
DICR
bit
Address: 00000044H
7
-
6
-
5
-
4
-
3
-
2
-
1
-
■ Block Diagram
Figure 7.1-1 Block Diagram
R-bus
DLYI
Interrupt request
158
0
DLYI
Initial value
-------0B
[R/W]
CHAPTER 7 REALOS-RELATED HARDWARE
■ Detailed Explanation of the Register
● DICR (Delayed Interrupt Control Register)
bit
7
6
5
4
3
2
1
0
Address: 00000044H
-
-
-
-
-
-
-
DLYI
Initial value
-------0B
[R/W]
This is the register to control delayed interrupts.
[bit0] DLYI
DLYI
Explanation
0
No delayed interrupt trigger or cancellation [Initial value]
1
Generating delayed interrupt triggers
This bit controls the generation and cancellation of the relevant interrupt triggers.
■ Operation
Delayed interrupts generate interrupts for task switching. Using this function, it is possible to generate and
cancel interrupt requests to the CPU using software.
● Interrupt Number
Delayed interrupts are allocated to the interrupt trigger corresponding to the greatest interrupt number.
This product allocates the delayed interrupt to interrupt number 63 (3FH).
● DLYI Bit of DICR
A delayed interrupt trigger is generated by writing "1" to this bit. Further, the delayed interrupt trigger is
canceled by writing "0" to this bit.
Since this bit is the same as the interrupt trigger flag in general interrupts, be sure to clear this bit in the
interrupt routine and to switch tasks at the same time.
159
CHAPTER 7 REALOS-RELATED HARDWARE
7.2
Bit Search Module
Searches for "0", "1", or the change point in the data written to the input register and
returns the position of the detected bit.
■ Register List
bit
Address: 000003F0H
Address: 000003F4H
Address: 000003F8H
Address: 000003FCH
31
0
BSD0
BSD1
BSDC
BSRR
0-detect data register
1-detect data register
Change point detection data register
Detection result register
■ Block Diagram
Figure 7.2-1 Block Diagram
D-bus
Input latch
Address decoder
Detection
mode
"1" detection data coding
Bit search circuit
Search results
160
CHAPTER 7 REALOS-RELATED HARDWARE
■ Detailed Explanation of the Register
● Data Register for Detecting 0 (BSD0)
bit
Address 000003F0H
31
0
Read/Write→ Write only
Initial value→ Undefined
Detects "0" for the written value.
The initial value is indeterminate due to a reset. The read value is indeterminate.
When transferring data, use 32-bit long data transfer instructions.
(Do not use 8-bit or 16-bit long data transfer instructions).
● Data Register for Searching 1 (BSD1)
bit
Address 000003F4H
31
0
Read/Write→ Readable/writable
Initial value→ Undefined
When transferring data, use 32-bit long data transfer instructions.
(Do not use 8-bit or 16-bit long data transfer instructions).
• Writing
Detects "1" for the written value.
• Reading
Save data of the internal state in the bit search module is read. This register is used to save or restore
the original state when the bit search module is used by, for example, an interrupt handler.
Ever though data is written to the 0-detect or change point detection data, register, data can be saved
or restored only by using the 1-detect data register.
Initial value is indeterminate due to a reset.
161
CHAPTER 7 REALOS-RELATED HARDWARE
● Data Register for Change Point Detection (BSDC)
bit
Address 000003F8H
31
0
Read/Write→ Write only
Initial value→ Undefined
Detects the change point for the written value.
The initial value is indeterminate due to a reset.
Read value is indeterminate.
When transferring data, use 32-bit long data transfer instructions.
(Do not use 8-bit or 16-bit long data transfer instructions).
● Detection Results Register (BSRR)
bit
Address 000003FCH
31
Read/Write→ Read only
Initial value→ Undefined
The results of 0 detection, 1 detection, or change point detection are read.
Which detection result is read is determined by the data register written last.
162
0
CHAPTER 7 REALOS-RELATED HARDWARE
■ Operation
● 0 Detection
The data written to the data register for a 0 detection is scanned from MSB to LSB, and the position of the
first "0" detected is returned.
Detection results are obtained by reading the detection results register.
The relation between the detected positions and the returned values is described in Table 7.2-1.
If there is no "0" (i.e. FFFFFFFFH), 32 is returned as the search result.
[Implementation Example]
Write data
Read value (decimal)
11111111111111111111000000000000B (FFFFF000 H)
→
20
11111000010010011110000010101010B (F849E0AAH)
→
5
10000000000000101010101010101010B (8002AAAAH)
→
1
11111111111111111111111111111111B (FFFFFFFFH)
→
32
● 1 Detection
The data written to the data register for 1 detection is scanned from MSB to LSB, and the position of the
first "1" detected is returned.
Detection results are obtained by reading the detection results register.
The relation between the detected positions and the returned values is described in Table 7.2-1.
If there is no "1" (i.e. the value is 00000000H), 32 is returned as the search result.
[Implementation Example]
Write data
Read value (decimal)
00100000000000000000000000000000B (20000000H)
→
2
00000001001000110100010101100111B (01234567H)
→
7
00000000000000111111111111111111B (0003FFFFH)
→
14
00000000000000000000000000000001B (00000001H)
→
31
00000000000000000000000000000000B (00000000H)
→
32
163
CHAPTER 7 REALOS-RELATED HARDWARE
● Change Point Detection
The data written to the data register for change point detection is scanned from bit30 to LSB, and compared
to the MSB value. The first position with a value different from the MSB value is returned.
Detection results are obtained by reading the detection results register.
The relation between the detected positions and the returned values is described in Table 7.2-1.
If there is no change point, 32 is returned.
In change point detection, 0 cannot be returned as the result.
[Implementation Example]
Write data
Read value (decimal)
00100000000000000000000000000000B (20000000H)
→
2
00000001001000110100010101100111B (01234567H)
→
7
00000000000000111111111111111111B (0003FFFFH)
→
14
00000000000000000000000000000001B (00000001H)
→
31
00000000000000000000000000000000B (00000000H)
→
32
11111111111111111111000000000000B (FFFFF000 H)
→
20
11111000010010011110000010101010B (F849E0AAH)
→
5
10000000000000101010101010101010B (8002AAAAH)
→
1
11111111111111111111111111111111B (FFFFFFFFH)
→
32
Table 7.2-1 Bit Position and Returned Value (decimal)
Detected
Bit position
Returned
value
Detected
Bit position
Returned
value
Detected
Bit position
Returned
value
Detected
Bit position
Returned
value
31
0
23
8
15
16
7
24
30
1
22
9
14
17
6
25
29
2
21
10
13
18
5
26
28
3
20
11
12
19
4
27
27
4
19
12
11
20
3
28
26
5
18
13
10
21
2
29
25
6
17
14
9
22
1
30
24
7
16
15
8
23
0
31
Does not exist
32
164
CHAPTER 7 REALOS-RELATED HARDWARE
■ Saved and Restoration Processing
If it is necessary to save and restore the internal status of the bit search module, as the case of using the bit
search module in the interrupt handler, follow the procedure described below.
(1) Read the data register for 1 detection, and save the contents (i.e., save).
(2) Use the bit search module.
(3) Write the data saved in step (1) to the data register for 1 detection (i.e., restore).
Using the operation described above, the value obtained when next reading the detection results register
will correspond to the contents written to the bit search module before step (1). Even if using the 0detection or change point detection data registers that were last written to, data will be correctly restored
using the procedure described above.
165
CHAPTER 7 REALOS-RELATED HARDWARE
166
CHAPTER 8
16-BIT RELOAD TIMER
This chapter describes the 16-bit reload timer, the
configuration and functions of registers, and 16-bit
reload timer operation.
8.1
Overview of 16-bit Reload Timer
8.2
Block Diagram
8.3
Registers of 16-bit Reload Timer
8.4
Operation of Reload Timer
167
CHAPTER 8 16-BIT RELOAD TIMER
8.1
Overview of 16-bit Reload Timer
The 16-bit reload timer consists of the 16-bit down counter, 16-bit reload register,
internal count clock creation prescaler, and control register.
A clock source can be selected from three types of internal clocks (obtained by dividing
the machine clock by 2, 8, and 32) and an external trigger.
■ Register List of Reload Timer
Figure 8.1-1 Register List of 16-bit Reload Timer
Control status register (TMCSR)
Address
bit
ch.0 0000004EH
ch.1 00000056H
ch.2 0000005EH
15
----
14
----
13
----
12
----
11
CSL1
10
CSL0
7
MOD0
6
----
5
OUTL
4
RELD
3
INTE
2
UF
9
8
MOD2 MOD1
1
CNTE
0
TRG
16-bit timer register (TMR)
Address
bit
ch.0 0000004AH
ch.1 00000052H
ch.2 0000005AH
15
0
16-bit reload register (TMRLR)
Address
bit
ch.0 00000048H
ch.1 00000050H
ch.2 00000058H
168
15
0
CHAPTER 8 16-BIT RELOAD TIMER
8.2
Block Diagram
A block diagram of the reload timer is shown below.
Figure 8.2-1 Block Diagram of Reload Timer
16-bit reload register
(TMRLR)
Reload
RELD
OUTL
INTE
UF
CNTE
TRG
R-bus
16-bit timer register (TMR)
UF
OUT
CTL
Count
enable
Clock
selector
Prescaler
CSL1
CSL0
EXCK
Prescaler
clear
IRQ
External timer
output
IN CTL
CSL1
CSL0
Bits in PFR
External
trigger selection
External trigger input
169
CHAPTER 8 16-BIT RELOAD TIMER
8.3
Registers of 16-bit Reload Timer
This section describes the configuration and functions of 16-bit reload timer registers.
■ Control Status Register (TMCSR)
Figure 8.3-1 Control Status Register (TMCSR)
TMCSR
Address
ch.0 0000004EH
ch.1 00000056H
ch.2 0000005EH
bit
Read/Write
Initial value
15
-
bit
7
MOD0
Read/Write R/W
Initial value
0
14
-
13
-
12
-
11
CSL1
R/W
-
10
CSL0
R/W
-
9
MOD2
R/W
-
8
MOD1
R/W
-
6
0
5
OUTL
R/W
0
4
RELD
R/W
0
3
INTE
R/W
0
2
UF
R/W
0
1
CNTE
R/W
0
0
TRG
R/W
0
R/W: Readable/writable
This register controls the 16-bit timer operation mode and interrupts.
Rewriting bits other than UF, CNTE, and TRG bits needs to be performed only when CNTE is "0".
[bit15 to bit12] Unused bits
These bits are always "0" when read.
[bit11, bit10] CSL1, CSL0 (Count source select)
Used as the count source select bits. The internal clocks and external event can be selected as the count
sources. The following lists the selectable count sources:
φ = 32MHz
φ = 16MHz
Internal clock φ/21 [Initial value]
62.5ns
125ns
1
Internal clock φ/23
250ns
0.5μs
1
0
Internal clock φ/25
1.0μs
2.0μs
1
1
External event
-
-
CSL1
CSL0
0
0
0
Count source (φ: Machine clock)
The configuration not listed above is prohibited.
If the external event is set as the count source, the count enable edge is set by the MOD1 and MOD0
bits.
The minimum pulse width required for the external clock is 2 × T (T: machine clock cycle).
170
CHAPTER 8 16-BIT RELOAD TIMER
[bit9 to bit7] MOD2 to MOD0 (Mode)
Used to select an operation mode. The function of the bits depends on whether an internal or external
clock is used as the count source, as follows:
Internal clock mode: Reload trigger is set.
External clock mode: Count enable edge is set.
Be sure to set MOD2 to "0".
[Setting the reload trigger at selection of the internal clock]
An internal clock is selected as the count source, the value of the reload register is loaded to continue
the count operation when the enable edge is input by setting the bits MOD2 to MOD0.
MOD2
MOD1
MOD0
Enable edge
0
0
0
Software trigger [Initial value]
0
0
1
External trigger (Rising edge)
0
1
0
External trigger (Falling edge)
0
1
1
External trigger (Both edges)
1
X
X
Setting disabled
X: Undefined
[Setting the enable edge at external clock selection]
If the external clock event is set as the count source, the event will be counted when the enable edge is
input by the bits MOD2 to MOD0.
MOD2
MOD1
MOD0
Enable edge
X
0
0
-
X
0
1
External trigger (Rising edge)
X
1
0
External trigger (Falling edge)
X
1
1
External trigger (Both edges)
X
X
X
Setting disabled
X: Undefined
A reload operation for the external event is generated by an underflow and a software trigger.
[bit6] Unused bit
This bit is always "0" when read.
[bit5] OUTL
Used to set the external timer output level. The output level is reversed when this bit toggles between
"0" and "1".
171
CHAPTER 8 16-BIT RELOAD TIMER
[bit4] RELD
Used as the reload enable bit. When this bit is "1", it turns to the reload mode, where at the same time of
an underflow of the counter value from "0000H" to "FFFFH", the setting of the reload register is loaded
to the counter to continue the count operation.
When this bit is "0", it turns to the oneshot mode where the counter value underflows from "0000H" to
"FFFFH" and the count operation stops.
PFR/EPFR
OUTL
RELD
Output wave form
0
X
X
Output disabled
1
0
0
Rectangular wave whose value is "H" during counting
1
1
0
Rectangular wave whose value is "L" during counting
1
0
1
Toggle output whose value is "L" during counting
1
1
1
Toggle output whose value is "H" during counting
X: Undefined
The PFR/EPFR indicates the value of the corresponding bit in the PFR/EPFR register.
[bit3] INTE
Used as the interrupt request enable bit. If this bit is "1", an interrupt request will occur when the UF bit
turns to "1". When this bit is "0", no interrupt request will occur.
[bit2] UF
Used as the timer interrupt request flag. This flag is set to "1" when the counter value underflows from
"0000H" to "FFFFH". This bit is cleared when "0" is written to it.
Writing "1" to this bit has no effect.
This flag is "1" when read with a read-modify-write (RMW) instruction.
[bit1] CNTE
Used as the timer count enable bit. If "1" is written to this bit, a start trigger is awaited. Writing "0"
stops the count operation.
[bit0] TRG
Used as the software trigger bit. If "1" is written to this bit, a software trigger is applied and the setting
of the reload register is loaded to the counter to start the count operation.
Writing "0" to this bit has no effect. This bit is always "0" when read.
A trigger input by this register is valid only when CNTE is "1". Nothing happens when CNTE is "0".
172
CHAPTER 8 16-BIT RELOAD TIMER
■ 16-bit Timer Register (TMR)
Figure 8.3-2 16-bit Timer Register (TMR)
TMR
Address
ch.0 0000004AH
ch.1 00000052H
ch.2 0000005AH
bit
15
14
13
12
11
10
9
8
Read/Write
Initial value
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
bit
7
6
5
4
3
2
1
0
Read/Write
Initial value
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R: Read only
X: Undefined
This register can read the count values of the 16-bit timer. The initial value is indeterminate. Be sure to
read this register using the 16-bit data transfer instruction.
■ 16-bit Reload Register (TMRLR)
Figure 8.3-3 16-bit Reload Register (TMRLR)
TMRLR
Address
ch.0 00000048H
ch.1 00000050H
ch.2 00000058H
bit
15
14
13
12
11
10
9
8
Read/Write
Initial value
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
bit
7
6
5
4
3
2
1
0
Read/Write
Initial value
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W: Write only
X: Undefined
This register is used to hold the initial value of counting. The initial value is indeterminate. Be sure to
read this register using the 16-bit data transfer instruction.
173
CHAPTER 8 16-BIT RELOAD TIMER
8.4
Operation of Reload Timer
This section shows following operations of the reload timer.
• Internal clock operations
• Underflow operation
■ Internal Clock Operations
When operating the timer using the clock obtained by dividing the internal clock, you can select the
count source from among the clocks obtained by dividing the machine clock by 2, 8, and 32.
To start the count operation simultaneously with count enabling, write "1" both to the CNTE and TRG
bits of the control status register.
If the timer is ready to start (CNTE=1), the trigger input with the TRG bit is always valid, regardless of
the operation mode.
The T (peripheral clock machine cycle) time is required after the counter start trigger is input until the
reload register data is loaded to the counter.
Figure 8.4-1 Start and Operations of the Counter
Count clock
Counter
Reload data
Data load
CNTE (register)
TRG (register)
T
174
-1
-1
-1
CHAPTER 8 16-BIT RELOAD TIMER
■ Underflow Operation
Underflow is defined as the time when the counter value changes from "0000H" to "FFFFH". Therefore,
the underflow will occur when [reload register setting value +1] counts.
At an occurrence of underflow, when the RELD bit of the control register is "1", the setting of the
reload register is loaded to the counter to continue the count operation. If the RELD bit is "0", the
counter will stop when the counter value becomes "FFFFH".
Figure 8.4-2 Underflow Operation
Count clock
0000H
Counter
Reload data
-1
-1
-1
Data load
Underflow set
[RELD=1]
Count clock
0000H
Counter
FFFFH
Underflow set
[RELD=0]
175
CHAPTER 8 16-BIT RELOAD TIMER
■ Output Pin Function
In the reload mode, the TOT0 to TOT2 output pins function as toggle outputs that are inverted by the
underflow. In the oneshot mode, these pins function as pulse outputs that indicate that counting is in
progress. The output polarity can be set with the OUTL bit of the register. If OUTL is "0", the initial
value of the toggle output is "0", and the one-shot pulse output is "1" during counting. If OUTL is set to
"1", the output wave form will be inverted.
Figure 8.4-3 Output Pin Function [RELD=1, OUTL=0]
Count start
Underflow
TOT0 to
TOT2
Inverted for OUTL=1
General-purpose port
CNTE
Start trigger
Figure 8.4-4 Output Pin Function [RELD=0, OUTL=0]
Count start
Underflow
TOT0 to
TOT2
Inverted for
OUTL=1
General-purpose port
CNTE
Start trigger
Start trigger wait status
176
CHAPTER 8 16-BIT RELOAD TIMER
■ Counter Operation Statuses
The counter status is determined by the CNTE bit of the control register and the WAIT internal signal.
The following counter statuses are settable: stop status (STOP status) indicated with CNTE=0,
WAIT=1, start trigger wait status (WAIT status) indicated with CNTE=1, WAIT=1, and operation
status (RUN status) indicated with CNTE=1, WAIT=0.
Figure 8.4-5 Counter Status Transitions
Status transition by hardware
Reset
Status transition by register access
STOP CNTE=0,WAIT=1
Counter: The values at last
stop are retained. Intermediate
immediately after reset.
CNTE=1
TRG=1
CNTE=1
TRG=0
RUN CNTE=1,WAIT=0
WAIT CNTE=1,WAIT=1
Counter: The values at stop
are retained.
Counter: Operation
RELD/UF
Intermediate immediately
after reset until they are
loaded.
TRG=1
TRG=1
LOAD CNTE=1,WAIT=0
The setting of the reload
register is loaded to the
counter.
RELD/UF
End of load
■ Others
The TOT2 output of ch.2 of the reload timer is connected to the A/D converter inside LSI. Therefore, A/D
conversion can start in the cycle specified in the reload register.
■ Notes
• The internal prescaler becomes operable when a trigger (software or external trigger) is applied in the state
that bit1 (CNTE for timer enabling) of the control status register is "1".
• If the interrupt request flag set timing and the clear timing overlap, the flag set operation is given
priority and the clear operation has no effect.
• If a write to the 16-bit timer reload register and the reload timing overlap, old data will be loaded to the
counter. New data is loaded to the counter when the next reloading occurs.
• For the 16-bit timer register, if a load timing and a count timings overlap, the load (reload) operation
will be given priority.
177
CHAPTER 8 16-BIT RELOAD TIMER
178
CHAPTER 9
PPG
This chapter describes the overview of the PPG
(Programmable Pulse Generator), the configuration and
functions of registers, and the operation of the PPG.
9.1
Overview of PPG
9.2
PPG Block Diagram
9.3
PPG Register
9.4
Operation of PPG
179
CHAPTER 9 PPG
9.1
Overview of PPG
PPG is an 8-bit reload timer module, and PPG output is performed by pulse output
control compliant with timer operations.
The hardware consists of eight 8-bit down counters, sixteen 8-bit reload registers, a
control register, eight external pulse outputs, and four interrupt outputs.
The MB91245/S series are loaded with 8 channels as an 8-bit PPG and 4 channels as a
16-bit PPG.
■ PPG Functions
• 8-bit PPG output independent operating mode
8 channels independent PPG output operations are possible.
Note: When using LCDC with this product, the output of an odd-numbered channel (PPG1, PPG3,
PPG5, PPG7) cannot be used.
• 16-bit PPG output operating mode
4 channels 16-bit PPG output operations are possible.
• 8+8-bit PPG output operating mode
An 8-bit PPG output of any cycle is made possible by making the ch (n+1) output the ch (n) clock
input (n=0, 2, 4, 6).
• 16+16-bit PPG output operating mode
This mode makes the ch.(n+3) + ch.(n+2) 16-bit prescaler output the ch.(n+1) + ch.(n) 16-bit PPG
clock input (n=0, 4).
• PPG output operations
This outputs a pulse wave with any cycle and duty ratio.
It can also be used as a D/A converter by an external circuit.
• Output inversion function
It is possible to invert the PPG output value.
180
CHAPTER 9 PPG
■ Register List of PPG
Figure 9.1-1 Register List of PPG
PPG activation register (TRG)
Address:
0001B1H
Read/Write→
Initial value→
Output inversion register (REVC)
Address:
0001B3H
Read/Write→
Initial value→
bit7
PEN07
R/W
(0)
bit6
PEN06
R/W
(0)
bit5
PEN05
R/W
(0)
bit4
PEN04
R/W
(0)
bit3
PEN03
R/W
(0)
bit2
PEN02
R/W
(0)
bit1
PEN01
R/W
(0)
bit0
PEN00
R/W
(0)
bit7
REV07
R/W
(0)
bit6
REV06
R/W
(0)
bit5
REV05
R/W
(0)
bit4
REV04
R/W
(0)
bit3
REV03
R/W
(0)
bit2
REV02
R/W
(0)
bit1
REV01
R/W
(0)
bit0
REV00
R/W
(0)
PPG0 to PPG7operation mode control register (PPGC0 to PPGC7)
Address:
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ch.0: 0001BCH
PIEn
PUFn
INTMn
PCS1
PCS0
MD1*
MD0*
ch.1: 0001BDH
Read/Write→
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ch.2: 0001BEH
Initial value→
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(X)
ch.3: 0001BFH
ch.4: 0001C8H
n=0 to 7
MD1 and MD0 only exist in even-numbered channels; they do
ch.5: 0001C9H
not exist in odd-numbered channels.
ch.6: 0001CAH
The initial value of an odd-numbered channel is indeterminate.
ch.7: 0001CBH
Write has no effect.
R/W: Readable/writable
X : Undefined
● Reload register: 8-bit PPG mode
Reload register H (PRLH0 to PRLH7)
Address:
bit15
ch.0: 0001B4H
ch.1: 0001B6H
Read/Write→
R/W
ch.2: 0001B8H
Initial value→
(X)
ch.3: 0001BAH
ch.4: 0001C0H
ch.5: 0001C2H
ch.6: 0001C4H
ch.7: 0001C6H
Reload register L (PRLL0 to PRLL7)
Address:
ch.0: 0001B5H
ch.1: 0001B7H
Read/Write→
ch.2: 0001B9H
Initial value→
ch.3: 0001BBH
ch.4: 0001C1H
ch.5: 0001C3H
ch.6: 0001C5H
ch.7: 0001C7H
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W: Readable/writable
X : Undefined
181
CHAPTER 9 PPG
● Reload register: 16-bit PPG mode
Reload register H (PRLH0, PRLH2, PRLH4, PRLH6)
Address:
ch.0: 0001B4H
ch.2: 0001B8H
ch.4: 0001C0H
ch.6: 0001C4H
Read/Write→
Initial value→
Read/Write→
Initial value→
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
Reload register L (PRLL0, PRLL2, PRLL4, PRLL6)
Address:
ch.0: 0001B5H
ch.2: 0001B9H
ch.4: 0001C1H
ch.6: 0001C5H
Read/Write→
Initial value→
Read/Write→
Initial value→
R/W: Readable/writable
X : Undefined
182
CHAPTER 9 PPG
9.2
PPG Block Diagram
This section shows the PPG block diagram.
■ 8-bit PPG ch.0, ch.2, ch.4, ch.6 Block Diagram
Figure 9.2-1 8-bit PPG ch.0, ch.2, ch.4, ch.6 Block Diagram
ch (n+1) borrow
Machine clock divided by 64
Machine clock divided by 16
Machine clock divided by 4
Machine clock
To the port
PPG
output latch
Invert
Clear
PEN(n+1)
Count clock
selection
S
R Q
PCNT (down counter)
IRQn
Reload
"H"/"L" selection
"H"/"L" selector
PRLLn
PIEn
PRLHn
PUFn
"L" side data bus
"H" side data bus
PPGCn / TRG
n = 0,2,4,6
Operation mode
(Control)
183
CHAPTER 9 PPG
■ 8-bit PPG ch.1, ch.5 Block Diagram
Figure 9.2-2 8-bit PPG ch.1, ch.5 Block Diagram
ch (n+1) borrow
Machine clock divided by 64
Machine clock divided by 16
Machine clock divided by 4
Machine clock
To the port
PPG
output latch
Invert
Clear
PENn
S
R Q
Count clock
selection
IRQn
PCNT (down counter)
ch(n-1)
borrow
Reload
"H"/"L" selection
"H"/"L" selector
PUFn
PRLLn
PIEn
PRLHn
"L" side data bus
"H" side data bus
PPGCn / TRG
n = 1,5
184
Operation mode
(Control)
CHAPTER 9 PPG
■ 8-bit PPG ch.3, ch.7 Block Diagram
To the port
Machine clock divided by 64
Machine clock divided by 16
Machine clock divided by 4
Machine clock
PPG
output latch
Invert
Clear
PENn
S
R Q
Count clock
selection
IRQn
PCNT (down counter)
ch (n-1)
borrow
Reload
"H"/"L" selection
"H"/"L" selector
PUFn
PRLLn
PIEn
PRLHn
"L" side data bus
"H" side data bus
PPGCn / TRG
n = 3,7
Operation mode
(Control)
185
CHAPTER 9 PPG
9.3
PPG Register
The PPG registers are explained in detail.
■ PPGCn Register (PPGn Operation Mode Control Register) n=0, 1, 2, 3, 4, 5, 6, 7
PPG0 to PPG7 operation mode control register (PPGC0 to PPGC7)
Address:
ch.0: 0001BCH
ch.1: 0001BDH
ch.2: 0001BEH
ch.3: 0001BFH
ch.4: 0001C8H
ch.5: 0001C9H
ch.6: 0001CAH
ch.7: 0001CBH
Read/Write→
Initial value→
bit7
PIEn
R/W
(0)
bit6
PUFn
R/W
(0)
n=0 to 7
bit5
INTMn
R/W
(0)
bit4
PCS1
R/W
(0)
bit3
PCS0
R/W
(0)
bit2
MD1 *
R/W
(0)
bit1
MD0 *
R/W
(0)
bit0
--------(X)
*: MD1 and MD2 exist only for even-numbered channels;
neither exists for any odd-numbered channel. The initial
values of odd-numbered channels are undefined. Writing is
meaningless.
R/W : Readable/writable
X
: Undefined
[bit7] PIEn (Ppg Interrupt Enable): PPG interrupt enable bit
The PPG interrupt enable is controlled as follows.
0
Interrupt disabled
1
Interrupt enabled
• When this bit is "1", PUFn becomes "1" and an interrupt request is generated.
• When this bit is "0", no interrupt request is generated.
• It is initialized to "0" by reset.
• Can be read and written.
[bit6] PUFn (Ppg Underflow Flag): PPG counter underflow bit
The PPG counter underflow bit is controlled as follows.
0
PPG counter underflow is not detected.
1
PPG counter underflow has been detected.
• In the 8-bit PPG 2 channels mode and the 8-bit prescaler + 8-bit PPG mode, it is set to "1" by an
underflow when the count value of ch.0 has become "FFH" from "00H".
• In the 16-bit PPG 1 channel mode, it is set to "1" by the underflow when the count value of ch.1/ch.0
has become "FFFFH" from "0000H".
• It turns "0" by a write of "0".
• A write of "1" to this bit has no effect.
• When reading by the read-modify-write (RMW) instruction, "1" is read.
• It is initialized to "0" by reset.
• Can be read and written.
186
CHAPTER 9 PPG
[bit5] INTMn (Interrupt Mode): interrupt mode bit
It is possible to restrict detection of the PUFn bit to only when there is underflow from PRLHn.
0
Set PUFn to "1" during an underflow.
1
Set PUFn to "1" only during an underflow from PRLHn.
• It is initialized to "0" by reset.
• Can be read and written.
• By setting this bit to "1", it is possible to set an interrupt during one cycle of the PPG output wave
form.
• Do not rewrite this bit while interrupts are enabled.
[bit4, bit3] PCS1/PCS0 (Ppg Count Select): count clock selection bits
Select the operation clock of the down counter as follows.
PCS1
PCS0
Operation mode
0
0
Machine clock (62.5ns machine clock at 16MHz)
0
1
Machine clock/4 (250ns machine clock at 16MHz)
1
0
Machine clock/16 (1μs machine clock at 16MHz)
1
1
Machine clock/64 (4μs machine clock at 16MHz)
• It is initialized to "00B" by reset.
• Can be read and written.
[bit2, bit1] MD1/MD0 (Ppg count MoDe): operation mode selection bits
Select the PPG timer operation mode as follows.
MD1
MD0
Operation mode
0
0
8-bit PPG 2 channels independent mode
0
1
8-bit prescaler + 8-bit PPG mode
1
0
16-bit PPG mode
1
1
16-bit prescaler + 16-bit PPG mode
• It is initialized to "00B" by reset.
• Can be read and written.
• Those bits only exist on even-numbered channels.
[bit0] reserved bit
This is a reserved bit. When writing, write "0" ("1" write disabled).
The read value is indeterminate.
187
CHAPTER 9 PPG
■ PRLL/PRLH Register (Reload Register:PRLL0 to PRLL7/PRLH0 to PRLH7)
Reload register H (PRLH0 to PRLH7)
Address:
bit15
ch.0: 0001B4H
ch.1: 0001B6H
Read/Write→
R/W
ch.2: 0001B8H
Initial value→
(X)
ch.3: 0001BAH
ch.4: 0001C0H
ch.5: 0001C2H
ch.6: 0001C4H
ch.7: 0001C6H
Reload register L (PRLL0 to PRLL7)
Address:
ch.0: 0001B5H
ch.1: 0001B7H
Read/Write→
ch.2: 0001B9H
Initial value→
ch.3: 0001BBH
ch.4: 0001C1H
ch.5: 0001C3H
ch.6: 0001C5H
ch.7: 0001C7H
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W: Readable/writable
X : Undefined
These registers retain the reload values to the down counter PCNT. Their roles are described
respectively.
Register name
Function
PRLL
Retains "L"-side reload value
PRLH
Retains "H"-side reload value
Can be read and written for each register
Note:
When used in the 8-bit prescaler + 8-bit PPG mode or the 16-bit prescaler + 16-bit PPG mode, the
PPG wave form may change with each cycle if different values are set for the prescaler side PRLL
and PRLH. It is therefore recommended that the same values be set for the prescaler side PRLL and
PRLH.
When used in the 16-bit PPG, for example, if ch.0 + ch.1 are used, the "H" side address of the reload
address is 1B4H+1B5H, and the "L" side address is 1B6H+1B7H. Consequently, when "H" count
value= 1234H, "L" count value= 5678H, it becomes
188
1B4H: 00010010B
1B5H: 00110100B
1B6H: 01010110B
1B7H: 01111000B.
CHAPTER 9 PPG
■ PPG Activation Register (TRG)
PPG activation register (TRG)
Address:
0001B1H
Read/Write→
Initial value→
bit7
PEN07
R/W
(0)
bit6
PEN06
R/W
(0)
bit5
PEN05
R/W
(0)
bit4
PEN04
R/W
(0)
bit3
PEN03
R/W
(0)
bit2
PEN02
R/W
(0)
bit1
PEN01
R/W
(0)
bit0
PEN00
R/W
(0)
R/W : Readable/writable
[bit7 to bit0] PEN07 to PEN00 (Ppg ENable): PPG launch enable bits
Select the PPG operation start and the operation mode as follows.
PEN07 to PEN00
Operational status
0
Operation stopped (retain "L" level output)
1
PPG operations enabled
• It is initialized to "0" by reset.
• Can be read and written.
• When using the 16-bit PPG, it is necessary to establish the same configuration for the corresponding
PEN bits, both odd and even-numbered. When setting the register, enable/disable both the even and
odd-numbered at the same time.
■ Output Inversion Register (REVC)
Output inversion register (REVC)
Address:
0001B3H
Read/Write→
Initial value→
bit7
REV07
R/W
(0)
bit6
REV06
R/W
(0)
bit5
REV05
R/W
(0)
bit4
REV04
R/W
(0)
bit3
REV03
R/W
(0)
bit2
REV02
R/W
(0)
bit1
REV01
R/W
(0)
bit0
REV00
R/W
(0)
R/W : Readable/writable
[bit7 to bit0] REV07 to REV00: output inversion bits
Invert PPG output values, including the initial level.
REV07 to REV00
Output level
0
Normal
1
Inversion
• It is initialized to "0" by reset.
• Can be read and written.
• As it simply inverts PPG output, the initial level is also inverted.
In addition, the relationship between the reload register "L" and "H" is also reversed.
• When using the 16-bit PPG, the same wave form is output by both the PPG (m) pin and the PPG
(m+1) pin, therefore, it is sufficient to simply set the REVXX of the pin to be used, however setting
both with the same value is also fine.
189
CHAPTER 9 PPG
9.4
Operation of PPG
The PPG consists of eight 8-bit PPG units and can be used in four different mode. In
addition to independent mode, these consists of the 9-bit prescaler + 8-bit PPG mode,
16-bit PPG 1 channel mode, and 16-bit prescaler + 16-bit PPG mode in which PPGs are
linked together.
For each 8-bit length PPG unit, there are two 8-bit length reload registers, the "L" side and the "H" side
(PRLL and PRLH). The values written into these registers are reloaded alternately into the 8-bit down
counter (PCNT) "L" side/"H" side, counted down along with the count clock, and during the reload the
borrow generated by the counter inverts the values of the pin output (PPG). This operation makes the
pin output (PPG) pulse output with "L" width / "H" width corresponding to the reload register value.
Start/restart depends on the bit writing of the register.
The relationship between the reload operation and the pulse output is as follows.
Reload operations
Pin output change
PRLH → PCNT
PPGn [0 → 1]
PRLL → PCNT
PPGn [1 → 0]
n=0 to 7
In addition, when bit7: PIEn of the PPGCn register is "1", an interrupt request is output by the the
borrow for "00H" to "FFH" of the counter (in the case of the 16-bit PPG mode, the borrow for "0000H"
to "FFFFH" of the counter).
● Operating mode
This block has a total of 4 operating modes: independent mode, 8-bit prescaler + 8-bit PPG mode, 16bit PPG 1 channel mode, and 16-bit prescaler + 16-bit PPG mode.
• The independent mode performs independent operations as an 8-bit PPG. The PPG output of ch (n)
is connected to the PPG (n) pin (n=0 to 7).
• The 8-bit prescaler + 8-bit PPG mode makes 1 channel operate as an 8-bit prescaler, counts its
borrow output, and then allows the 8-bit PPG wave form in any cycle to be output. For example, the
prescaler output of ch.1 is connected to the PPG1 pin, and the PPG output of ch.0 is connected to the
PPG0 pin.
• The 16-bit PPG 1 channel mode links 2 channels and operates as a 16-bit PPG. For example, if ch.0
and ch.1 are linked, 16-bit PPG output is connected both to the PPG0 pin and the PPG1 pin.
• The "16-bit prescaler + 16-bit PPG" mode is an operation mode which activates two channels
coupled into a 16-bit PPG and the other two channels coupled into a 16-bit prescaler.
190
CHAPTER 9 PPG
● PPG output operations
In this block, the PPG is started by setting the bit of each channel of the TRG register (PPG activation
register) to "1", and the count begins. After the operation has started, the count may be stopped by
writing "0" into each channel bit of the TRG register. After it is stopped, the pulse output retains "L"
level.
In the 8-bit prescaler + 8-bit PPG mode and the 16-bit prescaler + 16-bit PPG mode, please do not set
the PPG channels to operational status when the prescaler channels are in stopped status.
In the 16-bit PPG mode, perform the start/stop controls at the same time for the TRG register's PENn
for each channel (n=0 to 7).
PPG output operations are explained below.
In PPG operations, pulse wave output of the any frequency/any duty ratio (the ratio of the pulse wave is
"H" level period to "L" level period) is output consecutively. Once the PPG starts pulse wave output it
does not stop until an operational stop is set.
Figure 9.4-1 PPG output operation Output wave form
PENn
Operation
started by PENn
(from the "L"
side)
Output pin
PPG
T x (L+1)
L: PRLL value
H: PRLH value
T: machine clock
(φ, φ/4, φ/16)
or
input from the timer base counter
(depending on the PPGC clock selection)
T x (H+1)
Start
n = 0 to 15
● The relationship between the reload value and pulse width
The pulse width of the output is acquired through the value written in the reload register added 1;
multiplied by the count clock cycle. In other words, please be careful when the reload register value in
8-bit PPG operations is "00H", or the reload register value in 16-bit PPG operations is "0000H", the
pulse width will be one cycle of the count clock. Furthermore, please be careful when the reload register
value in an 8-bit PPG operation is "FFH", it will have a pulse width of 256 cycles of the count clock,
and when the reload register value in 16-bit PPG operations is "FFFFH", it will have a pulse width of
65536 cycles of the count clock.
The formula to calculate pulse width is as follows.
P1= T × (L+1)
Ph = T × (H+1)
{
L :
H :
T :
Ph :
P1 :
PRLL value
PRLH value
Input clock cycle
"H" pulse width
"L" pulse width
191
CHAPTER 9 PPG
● Count clock selection
The count clock used in this block's operations employs input from the peripheral clock and the timebase counter, and 4 kinds of count clock input may be selected.
The count clock operates as follows.
PPGC0 to PPGC7 registers
Count clock operations
PCS1
PCS0
0
0
The count clock performs 1 count per peripheral clock
0
1
The count clock performs 1 count per 4 cycles of the peripheral clock
1
0
The count clock performs 1 count per 16 cycles of the peripheral clock
1
1
The count clock performs 1 count per 64 cycles of the peripheral clock
However in 8-bit prescaler + 8-bit PPG mode and 16-bit prescaler + 16-bit PPG mode, the values of
bit4, bit3: PCS1, PCS0 in the PPGC register of the PPG, other than the first PPG, become invalid.
Please be careful in 8-bit prescaler + 8-bit PPG mode or 16-bit prescaler + 16-bit PPG mode, as there is
a possibility that the first count cycle will go awry if the PPG side is started while the prescaler side is
active and the PPG side is stopped.
192
CHAPTER 9 PPG
● Control of the pin outputs of the pulse
The pulse output generated by the operations of this module can be output by external pins PPG0 to
PPG7.
In 16-bit PPG mode, the PPG (m) or PPG (m+1), wave form outputs are the same so the same output
can be obtained by enabling the external pin output of either one (m = 0, 2, 4, 6).
In 8-bit prescaler + 8-bit PPG mode and 16-bit prescaler + 16-bit PPG mode, the 8-bit prescaler's
toggled wave form is output on the prescaler side and the 8-bit PPG's wave form is output on the PPG
side. An example of the output wave form in this mode is shown below
Figure 9.4-2 8-bit Prescaler + 8-bit PPG output operation output wave form
Ph1
Pl1
PPG1
PPG0
Ph0
Pl0
Note: It is recommended that the same
value is set for the ch.1 PRLL
and ch.1 PRLH.
.
L1 : PRLL value for ch.1 and
PRLH value for ch.1
L0 : PRLL value for ch.0
H0 : PRLH value for ch.0
T : Input clock cycle
Ph0 : PPG0 "H" pulse width
Pl0 : PPG0 "L" pulse width
Ph1 : PPG1 "H" pulse width
Pl1 : PPG1 "L" pulse width
● Interrupts
This modules's interrupt becomes active when the reload value has counted out and a borrow has been
generated. However, when the INTMn bit has been made "1", it only becomes active when there is
underflow (borrow) from PRLHn. In other words, an interrupt is generated when "H" width pulse ends.
In 8-bit PPG mode and 8-bit prescaler + 8-bit PPG mode, various interrupt requests are made by the
borrows of corresponding counters, however in 16-bit PPG mode and 16-bit prescaler + 16-bit PPG
mode, PUF (m) and PUF (m+1) are simultaneously set by the borrow of the 16-bit counter. For this
reason, in order to unify the interrupt factors, it is recommended that either PIE (m) or PIE (m+1) be
enabled. In addition, it is recommended that the interrupt factor clear should also be performed
simultaneously on PUF (m) and PUF (m+1) (m=0, 2, 4, 6).
● Initial value of each hardware
Each hardware of this block is initialized below at a reset.
<Register>
PPGC (n) → 0000000XB
<Pulse output>
PPG (n) → "L"
<Interrupt request>
IRQ (n) → "L"
(n=0 to 7)
Hardware other than the above is not initialized.
193
CHAPTER 9 PPG
● PPG combinations
ch.0: PPGC
ch.2: PPGC
ch.0
ch.1
ch.2
ch.3
0
8-bit PPG
8-bit PPG
8-bit PPG
8-bit PPG
0
1
8-bit PPG
8-bit PPG
8-bit PPG
8-bit
prescaler
0
1
0
8-bit PPG
8-bit PPG
0
0
1
1
0
1
0
0
8-bit PPG
8-bit
prescaler
8-bit PPG
8-bit PPG
0
1
0
1
8-bit PPG
8-bit
prescaler
8-bit PPG
8-bit
prescaler
0
1
1
0
8-bit PPG
8-bit
prescaler
0
1
1
1
1
0
0
0
16-bit PPG
8-bit PPG
8-bit PPG
1
0
0
1
16-bit PPG
8-bit PPG
8-bit
prescaler
1
0
1
0
16-bit PPG
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
MD1
MD0
MD1
MD0
0
0
0
0
0
0
16-bit PPG
Setting disabled
16-bit PPG
Setting disabled
16-bit PPG
Setting disabled
16-bit PPG
16-bit prescaler
The same operational combinations as ch. (0, 1, 2, 3) are also possible for ch. (4, 5, 6, 7) respectively.
Please replace them below.
ch.0=ch.4
{
194
ch.1=ch.5
ch.2=ch.6
ch.3=ch.7
CHAPTER 10
PWC (Pulse Width Count:
Pulse Width Measurement)
This chapter explains the overview of the pulse width
counter (PWC), the register configuration and functions
and the counter operation.
10.1 Overview of PWC
10.2 PWC Registers
10.3 Operation Description of PWC
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CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
10.1
Overview of PWC
This is the pulse width count function of the input signal.
■ PWC Functions
The hardware has one channel that consists of one 16-bit up counter, one input pulse divider and divide
ratio control register, one count input pin and one 16-bit control register, and they are used to achieve
the following functions.
● Pulse width count function
Measures the time between any given external pulse input events.
It is possible to select the standard internal clock from three types.
(Machine clock divided by 4/16/32)
"H" pulse width (↑ to ↓ ) / "L" pulse with (↓ to ↑)
Count modes
Rising cycle (↑ to ↑) / falling cycle (↓ to ↓ )
Measurement between edges (↑ or ↓ to ↓ or ↑)
Frequency of input pulses can be divided by 2n (where n = 1 to 8) using the 8-bit input frequency
divider and the resulting periods can be measured.
It is possible to generate an interrupt request when measurement is completed.
It is possible to perform measurement once or continuous.
■ Register List of PWC
Figure 10.1-1 Register List of PWC
Address
bit15 to bit8
bit7 to bit0
000139H
196
PDIVR0
000130H
000131H
PWCSR0
000132H
000133H
PWCR0
PWC Divide Ratio Control Register0
PWC Control/Status Register0
PWC Data Buffer Register0
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
■ PWC Block Diagram
Figure 10.1-2 PWC Block Diagram
PWCR0 read
Error
detection
Write enabled
16
/
/
16
ERR
PWCR0
Internal clock
(Machine clock/4)
16
Reload
Data transfer
16
R-bus
Control bit output
divider
Clear
Count enabled
Control circuit
Flag set, etc.
2 Clock
23
Overflow
Start edge
Stop edge
selection
selection
Measurement
start edge
Edge
Measurement
stop edge
2
Clock
16-bit up counter
CKS1/
CKS0
Clear divider
Divide
ON/OFF
PWC0
detection
Measurement complete interrupt request
ERR
CKS1/CKS0
8-bit
divider
Overflow interrupt request
15
/
PWCSR0
Divide
ratio
2 selection
/
PDIVR0
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CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
10.2
PWC Registers
This section describes the details of the PWC registers.
■ PWC Control/Status Register (PWCSR)
Figure 10.2-1 Bit Configuration of PWCSR Register (PWCSR)
PWCSR0 (upper)
bit
Address: ch.0: 000130H
Read/Write→
Initial value→
15
14
13
12
11
10
9
8
STRT
R/W
(0)
STOP
R/W
(0)
EDIR
R
(0)
EDIE
R/W
(0)
OVIR
R/W
(0)
OVIE
R/W
(0)
ERR
R
(0)
------(X)
7
6
5
4
3
2
1
0
CKS1
R/W
(0)
CKS0
R/W
(0)
------(0)
------(0)
SC
R/W
(0)
MOD2
R/W
(0)
MOD1
R/W
(0)
MOD0
R/W
(0)
PWCSR0 (lower)
bit
Address: ch.0: 000131H
Read/Write→
Initial value→
R/W : Readable/writable
R : Read only
[bit15] STRT: Counter Start Bit
[bit14] STOP: Counter Stop Bit
This bit conducts 16-bit up counter startup/re-startup/stop and displays the operation state of the counter
on read. The bit functions are shown below.
• Write Functions (Operation Control)
STRT
STOP
Operation Control Functions
0
0
No function/Does not affect the operation
0
1
Counter startup/Reboot (count allowed)*
1
0
Counter operation forced stop (count disabled)*
1
1
No function/Does not affect the operation
*: Clear bit instruction can be used
• Read functions (Display operation state)
198
STRT
STOP
Display operation state
0
0
Count stop (Is not started or measurement is completed) [Initial value]
1
1
Count operation (During the measurement)
•
On reset: It is initialized to "00B" .
•
The bits can be read and written. However, the function differs on a write and on a read from
what is shown above.
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
•
The read value of the read-modify-write (RMW) instruction is "11B" regardless of the bit.
•
With write to STRT, STOP bit in order to startup/stop counter, it is possible to use a bit process
instruction (such as a bit clear) that corresponds to each bit, but bit process instructions cannot be
used for read of operation state (When read is conducted, it is always operating).
[bit13] EDIR: Measurement Complete Interrupt Request flag
This flag indicates that the measurement is completed in the pulse width measurement mode. If this bit
is set when measurement complete interrupt request is enabled (bit12: EDIE=1), a measurement
complete interrupt request is generated.
Set factor
Set when pulse width measurement is completed
(Measurement results are stored in PWCR)
Clear factor
Cleared by reading PWCR (measurement results)
• On reset: it is initialized to "0".
• Only read is possible. The bit value does not change even when write is conducted.
[bit12] EDIE: Measurement Complete Interrupt Request Enabling bit
In the pulse width measurement mode, the measurement complete interrupt request is controlled as
follows.
0
Measurement complete interrupt request output disabled
(Interrupt is not generated even if EDIR is set) [Initial value]
1
Measurement complete interrupt request output enabled
(Interrupt is generated if EDIR is set)
• On reset: It is initialized to "0".
• The bit can be read and written.
[bit11] OVIR: Counter Overflow Interrupt Request flag
In every mode, this flag indicates that the 16-bit up counter overflowed from "FFFFH"to "0000H". If this
bit is set when counter overflow interrupt request is enabled (bit10: OVIE=1), a counter overflow
interrupt request is generated.
Set factor
Clear factor
Set when counter overflow occurs
(From "FFFFH"to "0000H")
Cleared by writing "0"
• On reset: It is initialized to "0".
• The bit can be read and written. However, for write, only "0" is allowed. The bit value does not
change if "1" is written.
• The read value of the read-modify-write (RMW) instruction is "1" regardless of the bit value.
199
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
[bit10] OVIE: Counter Overflow Interrupt Request enabling bit
Counter overflow interrupt request is controlled as follows.
0
Overflow interrupt request output disabled
(Interrupt is not generated even if OVIR is set) [Initial value]
1
Overflow interrupt request output enabled
(Interrupt is generated if OVIR is set)
• On reset: It is initialized to "0".
• The bit can be read and written.
[bit9] ERR: error flag
In the continuous measurement mode of the pulse width measurement mode, this flag indicates that the
next measurement has completed before the measurement results in PWCR are read. In such cases, the
PWCR value is updated to the new measurement result and the previous measurement result is lost.
Measurement is continued regardless of the bit value.
Set factor
Clear factor
Set when unread measurement results are lost because of the next results
Cleared by reading PWCR (measurement results)
• During reset: It is initialized to "0".
• Only read is possible. The bit value does not change even when a write is conducted.
[bit8] (Reserved bit)
This is a reserved bit. The read value is indeterminate. Always write "0" to this bit.
[bit7, bit6] CKS1, CKS0: Clock selection bits
The internal count is selected as follows.
CKS1
CKS0
Count clock selection
0
0
Machine clock divided by 4 [Initial value]
0
1
Machine clock divided by 16
1
0
Machine clock divided by 32
1
1
Setting disabled
• On reset: It is initialized to "00B".
• The bits can be read and written. However, you must not set to "11B".
Note: Rewriting after startup is disabled. Always write before startup or after stop.
[bit5, bit4] (Reserved bits)
These are reserved bits. When writing on these bits, write "00B".
200
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
[bit3] SC: Measurement (single/continuous) selection bit
The measurement mode is selected as follows.
SC
Measurement mode selection
When using pulse width measurement
mode
0
Single measurement mode [Initial value]
Stop after one measurement
1
Continuous measurement mode
Continuous measurement: buffer register valid
• On reset: It is initialized to "0".
• The bits can be read and written.
Note: Rewriting after startup is disabled. Always write before startup or after stop.
[bit2 to bit0] MOD2 to MOD0: Operation mode/Measurement edge selection bits
Select the edge that conducts operation mode and width measurement as shown below.
MOD2
MOD1
MOD0
Operation mode/measurement edge selection
0
0
0
Pulse width count mode between all edges (↑ or ↓ to ↓ or ↑) [Initial value]
0
0
1
Divide cycle count mode (input divider valid)
0
1
0
Cycle count mode between rising edges (↑ to ↑)
0
1
1
"H" pulse width count mode (↑ to ↓)
1
0
0
"L" pulse width count mode (↓ to ↑)
1
0
1
Cycle count mode between falling edges (↓ to ↓)
1
1
0
1
1
1
Setting disabled
• On reset: it is initialized to "000B".
• The bits can be read and written.
Note: Rewriting after startup is disabled. Always write before startup or after stop.
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CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
■ PWCR Register (PWC Data Buffer Register)
Figure 10.2-2 Bit Configuration of PWC Data Buffer Register (PWCR)
PWCR0 (upper)
bit
Address: ch.0: 000132H
Read/Write→
Initial value→
15
14
13
12
11
10
9
8
R
(0)
R
(0)
R
(0)
R
(0)
R
(0)
R
(0)
R
(0)
R
(0)
7
6
5
4
3
2
1
0
R
(0)
R
(0)
R
(0)
R
(0)
R
(0)
R
(0)
R
(0)
R
(0)
PWCR0 (lower)
bit
Address: ch.0: 000133H
Read/Write→
Initial value→
R: Read only
● Pulse Width Count Mode
In the continuous measurement mode (PWCSR bit3: SC=1), it becomes a buffer register that retains the
previous measurement results. However, in this case only read is allowed and the register value does not
change with write.
Single-shot measurement mode (PWCSR bit3: SC = 0) enables direct access to the up counter.
Again, in this case only read is allowed and the register value does not change with write. Read can be
conducted anytime and the count value during the count operation can be obtained. After measurement
is completed, the measurement results are kept.
Note:
To access this register, always use a half word or word transfer instruction.
• On reset: It is initialized to "0000H".
• Only read is possible.
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CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
■ PDIVR (Divide Ratio Control Register)
Figure 10.2-3 Bit Configuration of Divide Ratio Control Register (PDIVR)
PDIVR0
bit
7
6
5
4
3
2
1
0
Address: ch.0: 000139H
Read/Write→
Initial value→
R/W : Readable/writable
(-)
(-)
(-)
(-)
(-)
DIV2
R/W
(0)
DIV1
R/W
(0)
DIV0
R/W
(0)
This register is used in the divide cycle measurement mode (PWCSR bit2 to bit0: MOD2 to
MOD0=001B) and has no effect in other modes.
In the divide cycle measurement mode, a pulse input of the measurement pin is divided only with the
division ratio set by this register, and one cycle width after division is measured. The division ratio is
selected as follows.
DIV2
DIV1
DIV0
Division Ratio Selection
0
0
0
21= divide by 2 [Initial value]
0
0
1
22= divide by 4
0
1
0
23= divide by 8
0
1
1
24= divide by 16
1
0
0
25= divide by 32
1
0
1
26= divide by 65
1
1
0
27= divide by 128
1
1
1
28= divide by 256
• On reset: It is initialized to "000B".
• The bits can be read and written.
Note:
Rewriting after startup is disabled. Always write before startup or after stop.
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CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
10.3
Operation Description of PWC
A measurement input pin, 8-bit input division and etc. are embedded. With PWC, there
is a pulse width count function, and a selection can be made from three types of count
clock. This section describes the basic functions/operations of the pulse width count
function.
■ Pulse Width Count Functions
The time/cycle between any pair of given event of the input pulse can be measured with the counter.
After startup, count is not conducted until the set measurement start edge is input. After clearing the
counter that detects the start edge to "0000H", start count up and when stop edge is detected, stop count.
During this time, the count value is saved in the register as the pulse width.
After measurement is complete and when overflow occurs, an interrupt request can be generated.
After measurement is complete, it operates as follows depending on the measurement mode.
• In single measurement mode. . . . . . . . . . . The operation is stopped.
• In continuous measurement mode. . . . . . . After the counter value is transferred to the buffer
register, count is stopped until the measurement start edge
is input again.
Figure 10.3-1 Pulse width count operation (single measurement mode / "H" width measurement)
(The solid line is the count value.)
PWC input
measured
pulse
Count value
FFFFH
Count clear
0000H
Measurement
Count start
start
Count stop
Time
EDIR flag set (measurement complete)
Figure 10.3-2 Pulse width count operation (continuous measurement mode / "H" width measurement)
(The solid line is the count value.)
PWC input
measured
pulse
Count value
Overflow
FFFFH
Transfer data to PWCR
Transfer data to PWCR
Count clear
0000H
Measurement
start
Count start
Count clear
Count stop
Count start
OVIR flag set
Count stop
Time
EDIR flag set (measurement complete)
204
Between EDIR flag set
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
■ Count Clock Selection
The count clock of the counter can be selected from three types within the internal clock sources, based
on the bit7, bit6: CKS1, CKS0 setting of the PWCSR register.
The count clock can be selected from the following.
PWCSR
The internal count clock to be selected
CKS1, CKS0
00B
Machine clock divided by 4 [Initial value]
01B
Machine clock divided by 16
10B
Machine clock divided by 32
For the initial value after reset, the machine clock divided by 4 clock is selected.
Note:
Be sure to select the count clock before starting up counter.
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CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
■ Operation Mode Selection
The selection of the operation/measurement modes are conducted by the PWCSR setting.
• Operation mode setting: PWCSR bit2 to bit0: MOD2, MOD1, MOD0
(Pulse width count mode selection, determining measurement edge, etc.)
• Measurement mode setting: PWCSR bit3: SC
(Single measurement/continuous measurement selection)
The selection of operation mode by the combination of mode setting bits are shown in the list below.
Operation mode
↑ or ↓ to ↑ or ↓
Measure between all
edges
Division cycle
measurement
(1 to 256 division)
Pulse width
count
↑ to ↑ Cycle
measurement between
rising edge
↑ to ↓
"H" Pulse width count
↓ to ↑
"L" Pulse width count
↓ to ↓ Cycle
measurement between
falling edge
SC
MOD2
MOD1
MOD0
Single measurement: Buffer disabled
0
0
0
0
Continuous measurement: Buffer enabled
1
0
0
0
Single measurement: Buffer disabled
0
0
0
1
Continuous measurement: Buffer enabled
1
0
0
1
Single measurement: Buffer disabled
0
0
1
0
Continuous measurement: Buffer enabled
1
0
1
0
Single measurement: Buffer disabled
0
0
1
1
Continuous measurement: Buffer enabled
1
0
1
1
Single measurement: Buffer disabled
0
1
0
0
Continuous measurement: Buffer enabled
1
1
0
0
Single measurement: Buffer disabled
0
1
0
1
Continuous measurement: Buffer enabled
1
1
0
1
0
1
1
0
1
1
1
0
0
1
1
1
1
1
1
1
Setting disabled
For the initial value after reset, all edges are measured and single measurement mode is selected.
Note:
Make sure to perform the selection of the operation mode before starting up counter.
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CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
■ Pulse Width Count Start and Stop
Startup/re-startup/forced stop of each operation is conducted through bit15, bit14: STRT, STOP bit of
PWCSR.
The functions are separated with the startup/re-startup of pulse width count conducted through the
STRT bit and the forced stop conducted through the STOP bit. Each one functions by writing "0",
however, the values written in both bits must be exclusive for it to function. When writing using
instructions other than the bit manipulation instruction (in units of bytes), be sure to write one of the
combinations shown below.
Function
STRT
STOP
Pulse Width Count Startup/Re-startup
0
1
Pulse Width Count Forced Stop
1
0
When using the bit manipulation instruction (bit clear instruction), the combinations above are written
automatically by the hardware, therefore there is no need to pay special attention.
● Operation after startup
The operation after the startup of the pulse width measurement mode is not counted until the
measurement start edge is input. After the measurement start edge is detected, the 16-bit up counter is
cleared to "0000H" and count is started.
● Re-startup
Start up (write "0" in the STRT bit) after pulse width count is started up is called re-startup. When restartup is conducted, the following operation is conducted.
• For measurement start edge wait state: It does not affect the operation.
• During measurement:
Count is stopped and it becomes measurement start edge
wait state again. In this case, if the measurement complete
edge detection and re-startup occur simultaneously, the
measurement complete flag (EDIR) is set and, the
measurement results are transferred to PWCR in the
continuous measurement mode.
● Stop
In the single measurement mode, the count operation stops automatically due to counter overflow or
measurement complete, therefore there is no need to pay special attention. In all other modes or when
stopping before automatic stop, it is necessary to perform forced stop.
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CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
● Operation State Confirmation
The STRT and STOP bits mentioned above function as an operation state display bit during read. The
value displayed shows the following contents.
STRT
STOP
Operation state
0
0
During counter stop (except for measurement start edge wait state)
It shows that it has not started up or that the measurement is complete.
1
1
Count operation or measurement start edge wait state
Note:
It is the same value regardless of whether the STRT or STOP bit is read. However, when the bit is
read with the read-modify-write (RMW) instruction (Bit process instruction, etc.), it is always "11B",
therefore do not use these instructions to read.
■ Clear Counter
16-bit up counter is cleared to "0000H" in the following cases.
• On reset
• In the pulse width measurement mode when the measurement start edge is detected and count is
started
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CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
■ Details of Pulse Width Count Operation
● Single measurement and Continuous measurement
For pulse width measurement, there are two modes; one mode conducts measurement once and the
other mode conducts measurements continuously. Each mode is selected using the SC bit of PWCSR
(refer to "■ Operation Mode Selection"). The difference between the two modes is shown below.
• Single Measurement Mode:
when the first measurement complete edge is input, the count of the counter is stopped, the
measurement complete flag (EDIR) within PWCSR is set and no further measurement may be
conducted.
However, if it reboots at the same time, it becomes measurement start wait state.
• Continuous Measurement Mode:
When the measurement complete edge is input, the counter count stops, the measurement complete
flag (EDIR) within PWSCR is set and count is stopped until the measurement start edge is input
again. If the measurement start edge is input again, the counter is cleared to "0000H" and then begins
measurement. When the measurement is complete, the measurement results of the counter are
transferred to PWCR.
Note:
Make sure to perform the selection/modification of the measurement mode when the counter is
stopped.
● Measurement Result Data
In the single measurement mode and the continuous measurement mode, there is a difference in how the
measurement results and counter values are handled and the how PWCR functions. The difference
between the measurement results of the two modes is shown below.
• Single Measurement Mode:
If PWCR is read during operation, the count value that is being measured can be obtained.
If PWCR is read after measurement is complete, the measurement result data can be obtained.
• Continuous Measurement Mode:
When the measurement is complete, the measurement results of the counter are transferred to
PWCR.
When PWCR is read, the previous measurement result is obtained and the previous measurement
result is held even during the measurement operation. You cannot read the count value that is being
measured.
In the continuous measurement mode, if the next measurement is completed before the previous
measurement results are read, the previous measurement results are erased by the new results. In such
cases, an error flag (ERR) is set within PWCSR. The error flag (ERR) is automatically cleared when
PWCR is read.
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CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
● Measurement Mode and Count Operation
The measurement mode can be selected from 5 types depending on what part of the input pulse is to be
measured. In addition, in order to accurately measure the width of high frequency pulses, there is a
mode where you can divide the input pulse by any given number. This is explained below.
Measurement mode
MOD2
MOD1
Measurement content
(W: pulse width to be measured)
MOD0
W
Pulse width count between all
edges
0
0
W
W
↓ Count Stop
↓ Start
↑ Count
Start
↑ Stop
↑ Start
0
↓
Stop
Measures the width between edges that are input continuously.
Count (Measurement) Start: when edge is detected
Count (Measurement) Stop: when edge is detected
W
W
↓ Count Start
(Example of Divide by 4)
Division Cycle Measurement
0
0
1
↑ Count
Start
0
1
↓
Stop
Only the division ratio selected in the division ratio setting register
PDIVR is used to divide the input pulse and measure its cycle.
Count (Measurement) Start: when rising edge is detected
immediately after startup
Count (Measurement) Stop: when the first cycle is complete after
divide
W
Cycle measurement between
rising edges
W
↑ Count Stop
↑ Start
0
W
W
↑ Count Stop
↑ Start
↑ Stop
↑ Start
↑
Stop
Measures the cycle between rising edges.
Count (Measurement) Start: when rising edge is detected
Count (Measurement) Stop: when rising edge is detected
W
"H" Pulse width count
0
1
1
↑ Count
Start
W
↓ Count
Stop
Start
↑
W
W
1
0
0
↑ Count
Stop
↓ Count
Start
1
0
1
Start
↓
Stop
↑
Measures the width of the "L" period.
Count (Measurement) Start: when falling edge is detected
Count (measurement) Stop: when the rising edge is detected
W
Cycle measurement between
falling edges
↓
Measures the width of the "H" period.
Count (Measurement) Start: when rising edge is detected
Count (Measurement) Stop: when falling edge is detected
↓ Count
Start
"L" Pulse width count
Stop
W
W
↓ Count Stop
↓ Start
↑ Stop
↓ Start
↓
Stop
Measures the cycle between falling edges.
Count (Measurement) Start: when falling edge is detected
Count (Measurement) Stop: when falling edge is detected
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CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
In any mode, after measurement is started up, the count operation of the counter is not started until the
measurement start edge is input. If the measurement start edge is input, the counter is cleared to
"0000H" and up count is continued in each count clock until the measurement stop edge is input.
When the measurement stop edge is input, the following operations are conducted.
• The measurement complete flag (EDIR) is set within PWCSR.
• The count operation of the counter is stopped (with exception of when it is conducted with reboot).
• Continuous measurement mode: The counter value (=measurement result) is transferred to PWCR
and count is stopped until the next measurement start edge is input.
• Single measurement mode:Measurement is completed (with exception of when it is conducted with
reboot).
In the continuous measurement mode, when pulse width count or cycle measurement is conducted
between all edges, the stop edge becomes the next measurement start edge.
● Minimum Input Pulse Width
The following are restrictions to the pulse that can be input in the pulse width count input pins (PWC0).
Minimum input width : machine cycle × 4 or more
(In the case of a 16MHz machine clock, it should be 0.25μs or more).
If a pulse smaller than the above is input, the operation is not guaranteed.
● Pulse Width/Cycle Calculation Method
After measurement is complete, the measured pulse width/cycle calculation method is conducted from
the measurement result data obtained in PWCR.
TW : Measured pulse width/cycle [μs]
TW = n × t ÷ DIV [μs]
n
: Measurement result data within PWCR
t
: Count clock cycle [μs]
DIV : Division ratio selected in the divide ratio register PDIVR
(Insert "1" for everything other than the divide cycle
measurement mode).
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CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
● Pulse Width/Cycle Measurement Range
The range of the pulse width/cycle that can be measured changes depending on the combination of the
count clock and input divider division ratio selection.
As an example, the measurement range for a machine clock (hereinafter referred to as φ)=16MHz is
listed below.
Divide ratio
DIV2, DIV1, DIV0
When CKS1, CKS0
=00B is set
(φ /4)
When CKS1, CKS0
=01B is set
(φ /16)
When CKS1, CKS0
=10B is set
(φ /32)
No Division
-
0.25μs to 16.4ms
[250ns]
0.25μs to 65.5ms
[1.0μs]
0.25μs to 131ms
[2.0μs]
Divided by 2
000B
0.25μs to 8.19ms
[125ns]
0.25μs to 32.8ms
[0.5μs]
0.25μs to 65.5ms
[1.0μs]
Divided by 4
001B
0.25μs to 4.10ms
[62.5ns]
0.25μs to 16.4ms
[250ns]
0.25μs to 32.8ms
[0.5μs]
Divided by 8
010B
0.25μs to 2.05ms
[31.25ns]
0.25μs to 8.19ms
[125ns]
0.25μs to 16.4ms
[250ns]
Divided by 16
011B
0.25μs to 1.02ms
[15.6ns]
0.25μs to 4.10ms
[62.5ns]
0.25μs to 8.19ms
[125ns]
Divided by 64
100B
0.25μs to 256μs
[3.91ns]
0.25μs to 1.024ms
[15.6ns]
0.25μs to 2.05ms
[31.25ns]
Divided by 256
101B
0.25μs to 64.0 μs
[0.98ns]
0.25μs to 256μs
[3.91ns]
0.25μs to 512μs
[7.81ns]
----
Others
Setting disabled
*When machine clock φ =16MHz
* The values in [ ] show the resolution for 1 bit.
● Interrupt Request Generation
In the pulse width measurement mode, the following two interrupt requests can be generated.
• Interrupt request due to counter overflow
If counter overflow occurs due to count up during measurement, the overflow flag is set and if
overflow interrupt request is allowed, an interrupt request is generated.
• Interrupt request due to measurement completion
If measurement complete edge is detected, the measurement complete flag (EDIR) is set in PWCSR
and if measurement complete interrupt request is allowed, an interrupt request is generated.
The measurement complete flag (EDIR) is automatically cleared when measurement result PWCR is
read.
212
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
Various settings
● Pulse Width Count Operation Flow
Reboot
Count clock selection
Operation/measurement mode selection
Clear Interrupt flag
Enable interrupt
Measurement input pin selection
Startup with STRT bit
Continuous measurement
mode
Single measurement mode
Measurement start edge
detection
Measurement start edge
detection
Clear counter
Clear counter
Count start
Count start
Up count
Up count
Oveflow occurrence
→ OVIR flag set
Oveflow occurrence
→ OVIR flag set
Measurement complete edge
detection → EDIR flag set
Measurement complete edge
detection → EDIR flag set
Count stop
Count stop
Transfer count value to PWCR
Operation stop
213
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
■ Notes
● Notes concerning register rewrite
The following PWCSR register bits may not be rewritten during operation. Always conduct rewrite
before startup or after stop.
[bit7, bit6] CKS1, CKS0:
Clock selection bits
[bit3] SC:
Measurement mode (single/continuous) selection bit
[bit2 to bit0] MOD2 to MOD0:
Operation mode/measurement edge selection bits
The PDIVR register may not be rewritten during operation. Always conduct rewrite before startup or
after stop.
● STRT and STOP bit of the PWCSR register
Be aware for both bits hold different meanings on a write and on a read. Refer to "■ PWC Control/
Status Register (PWCSR)".
In addition, the read value for the read-modify-write (RMW) instruction is "11B" regardless of the bit
value. For this reason, the bit process instruction cannot be used to read the operation state (if read it
will always be "Operating").
Write to the STRT and STOP bit for counter startup/stop can be conducted by using bit process
instructions (bit clear instruction, etc.) for each bit.
● Clear counter
In the case of pulse width measurement mode, the counter is cleared with the measurement start edge,
therefore the data in the counter before startup has no effect.
● Minimum Input Pulse Width
The following are restrictions to the pulse that can be input in the pulse width count input pins.
• Minimum input width:
machine cycle × 4 (when the machine cycle is 62.5ns, 250ns or higher)
• Maximum input frequency: machine clock divided by 4 (when the machine cycle is 16MHz, 4MHz
or lower)
If a pulse smaller than the above or higher frequency pulse is input, the operation is not guaranteed. If
there is a possibility that such noise is included in the input signal, put it through a filter outside the chip
and remove the noise before input.
● Divide Cycle Measurement Mode
Of the pulse width count modes, the divide cycle measurement mode divides the input pulse, therefore
the pulse width calculated from the measurement results is an average value.
● Clock Selection Bits
Setting "11B" to the [bit7, bit6] CKS1, CKS0: clock selection bits in the PWCSR register is prohibited.
● Reserved Bit
Bit8, bit5, and bit4 of the PWCSR register is a reserved bit. If writing in this bit, be sure to write "0".
214
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
● Reboot During Operation
When conducting reboot after the count operation is started, the following may occur depending on the
timing.
• In the pulse width single measurement mode, if it occurs at the same time as measurement complete
edge
Conduct reboot and turns to the measurement start edge wait state and the measurement complete
flag (EDIR) is set.
• In the pulse width continuous measurement mode, if it occurs at the same time as measurement stop
edge
Conduct reboot and turns to the measurement start edge wait state and the measurement complete
flag (EDIR) is set and the measurement result at that point is transferred to PWCR.
As shown above, when rebooting during operation, be aware of the flag operations and conduct
interrupt control and etc.
215
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
216
CHAPTER 11
MAIN OSCILLATION
STABILIZATION WAIT TIMER
This chapter gives an overview of the main oscillation
stabilization wait timer and describes its register
configuration, functions, and operations.
11.1
Overview of Main Oscillation Stabilization Wait Timer
11.2
Block Diagram of Main Oscillation Stabilization Wait Timer
11.3
Register of Main Oscillation Stabilization Wait Timer
11.4
Operations of Main Oscillation Stabilization Wait Interrupt
217
CHAPTER 11 MAIN OSCILLATION STABILIZATION WAIT TIMER
11.1
Overview of Main Oscillation Stabilization Wait Timer
The main oscillation stabilization wait timer is a 23-bit counter that counts up in
synchronization with the main clock. It has an interval timer function to generate
interrupts repeatedly at prescribed time intervals.
■ Overview of Main Oscillation Stabilization Wait Timer
During operations by the sub clock, if the main oscillation is once stopped by bit0 (OSCDS1) of OSCCR
(oscillation control register) but oscillation re-occurs, this timer is used to ensure the oscillation
stabilization waiting time of the main clock.
Select the interval time among all the following 3 types.
Main clock cycle
218
Interval times (when main oscillation is 4MHz)
φ
φ × 211 (1.0 ms)
Note:
φ is the internal base clock cycle and the
cycle of twice of the main oscillation.
φ × 216 (32.7 ms)
φ × 214 (8.0 ms)
CHAPTER 11 MAIN OSCILLATION STABILIZATION WAIT TIMER
11.2
Block Diagram of Main Oscillation Stabilization Wait Timer
This section shows the block diagram of the main oscillation stabilization wait timer.
■ Block Diagram of Main Oscillation Stabilization Wait Timer
Figure 11.2-1 Block Diagram of Main Oscillation Stabilization Wait Timer
Main oscillation
stabilization wait
timer counter
φ
6
10
13
15
2 1 22 23 24 25 26 27
211
214
216
0
1
2
3
4
5
22
Interval
timer selector
Reset
(INIT)
Counter clear circuit
Main oscillation
stabilization wait
timer interrupt
Main oscillation stabilization
wait timer control register
(OSCR)
WIF
WIE
WEN
-
-
WS1
WS0
WCL
φ : Internal base clock period
[Main oscillation stabilization wait timer]
This is the 23-bit up counter that acts as the count clock of the main clock oscillation.
[Counter clear circuit]
Other than the (WCL=0) setting by the OSCR register, the counter is cleared when reset (INIT).
[Interval timer selector]
The falling edge of the divided output selected by the circuit to select one type of divided output for the
interval timer from the three types of divided output for the main oscillation stabilization wait timer
counter is a factor in interrupts.
[Main oscillation stabilization wait register (OSCR)]
Selects interval time, clears the counter and checks the interrupt control and status, etc.
219
CHAPTER 11 MAIN OSCILLATION STABILIZATION WAIT TIMER
11.3
Register of Main Oscillation Stabilization Wait Timer
This section describes the register description of main oscillation stabilization wait
timer.
■ Main Oscillation Stabilization Wait Timer Register (OSCR)
Figure 11.3-1 Main Oscillation Stabilization Wait Timer Control Register
OSCR
bit
0000 0490H
15
WIF
R/W
14
WIE
R/W
13
WEN
R/W
12
----
11
----
10
WS1
R/W
9
WS0
R/W
8
WCL
W
Initial value
INIT
RST
xxH
00H
Access
R/W
[bit15] WIF (timer Interrupt Flag)
This is the main oscillation stabilization wait interrupt request flag.
It is set to "1" by the falling edge of the selected interval timer divided output.
When this bit and the interrupt request enable bit are "1", a main oscillation stabilization interrupt
request is output.
0
No main oscillation stabilization interrupt request [Initial value]
1
Main oscillation stabilization interrupt request occurs
• Initialized as "0" by a reset (INIT).
• Read and write are possible. However, only "0" can be written. Even if "1" is written to the bit, the
bit value does not change.
• Moreover, read-modify-write (RMW) instructions always make the read value "1".
[bit14] WIE (timer Interrupt Enable)
This bit enables/disables output of interrupt requests to CPU. When this bit and the main oscillation
stabilization interrupt request flag bit are "1", the main oscillation stabilization interrupt request is
output.
0
Main oscillation stabilization interrupt request output disabled [Initial value]
1
Main oscillation stabilization interrupt request output enabled
• Initialized as "0" by a reset (INIT).
• Read and write are possible.
220
CHAPTER 11 MAIN OSCILLATION STABILIZATION WAIT TIMER
[bit13] WEN (timer enable)
This bit enables timer operations.
When this bit is "1", the timer performs a count.
0
Timer operations stopped [Initial value]
1
Timer operations
• Initialized as "0" by a reset (INIT).
• Read and write are possible.
[bit12, bit11] (reserved bits)
These are reserved bits. When writing, write "0" ("1"write disabled).
The read value is indeterminate.
[bit10, bit9] WS1, WS0 (timer interval Select 1, 0)
Selects the interval timer cycle.
Selects the output bit of the counter for the main oscillation stabilization wait timer from the following 3
kinds.
WS1
WS0
Interval timer cycle (when main oscillation is 4MHz)
0
0
φ × 21 (1.0μs) [Initial value]
0
1
φ × 211 (1.0ms)
1
0
φ × 216 (32.7ms)
1
1
φ × 214 (8.0ms)
(The internal base clock cycle φ is a cycle of twice the main oscillation).
• Initialized as "00B" by a reset (INIT).
• When using this timer, write appropriate values for WS1 and WS0 bits.
• Read and write are possible.
[bit8] WCL (timer CLear)
• Writing "0" clears the main oscillation stabilization wait timer to "0".
• Only "0" can be written. Even if "1" is written to the bit, it will not affect the operations.
• The read value is always "1".
221
CHAPTER 11 MAIN OSCILLATION STABILIZATION WAIT TIMER
11.4
Operations of Main Oscillation Stabilization Wait Interrupt
This section describes the main oscillation stabilization wait interrupt operations.
■ Main Oscillation Stabilization Wait Operations
The counter for the main oscillation stabilization wait timer counts with the main clock; when the set
interval time has elapsed, it sets the main oscillation stabilization wait interrupt request flag (WIF) to "1".
At that time, when the interrupt request enable bit is enable (WIE=1), an interrupt request is generated to
CPU. However, when the main clock is stopping oscillation, (refer to "■Interval Timer Function
Operations") the count operation is also stopped and the main oscillation stabilization wait interrupt is not
generated.
In the interrupt processing routine, write "0" in the WIF flag and clear the interrupt request. The WIF bit is
unrelated to the WIE bit value, and it is set when the specified divided output falls.
After reset cancellation, when performing enable (WIE=1) for interrupt request output or changing the
WS [1: 0] bit, it is imperative to simultaneously clear (WIF=WCL=0) the WIF bit and the WCL bit.
• When the WIF bit is "1", an interrupt request is immediately generated when the WIE bit is changed
from disabled to enabled (0 → 1).
• If counter clear (OSCR: WCL=1) and overflow of the selected bit occur at the same time, the WIF
bit is not set.
■ Interval Timer Function Operations
The counter for the main oscillation stabilization wait timer counts up with the main clock, but under the
following conditions the main clock oscillation stops therefore, the count stops too.
• When the WEN bit is "0".
• If it is switched to stop mode by the setting that stops main oscillation in stop mode (standby control
register STCR’s bit0: OSCD1=1), the count stops during stop mode. When this product is initialized
to OSCD1=1 at reset (INIT), so if you want the main oscillation stabilization wait timer to function
during stop mode, set OSCD2=0 before switching to standby.
• In sub clock mode, when bit0: OSCDS1 of the OSCCR (oscillation control register) is set to "1", the
main oscillation stops therefore, the timer count stops too.
When the counter is cleared (WCL=0), the count is performed from "000000H" and when it reaches
"7FFFFFH", it returns to "000000H" and continues the count. During count up, when a falling edge is
generated in the divided output for the selected interval timer, the main oscillation stabilization wait
interrupt request bit (WIF) is set to "1". Namely, the cleared time is taken as the base, and a main
oscillation stabilization wait timer interrupt request is generated at each selected interval time.
222
CHAPTER 11 MAIN OSCILLATION STABILIZATION WAIT TIMER
■ Clock Supply Function Operations
With this product, the time-base counter is used to ensure the oscillation stabilization wait time after INIT
and the stop mode, however while the sub clock is selected as the clock source, this main oscillation
stabilization wait timer operated by the main clock is used to ensure the oscillation stabilization wait time
of the main clock, and this is unconnected with the clock source selection.
Please follow the process below to perform an oscillation stabilization wait for the main clock from a state
where the main oscillation is stopped in sub clock operations.
(1) Set the time required for oscillation stabilization of the main clock in WS1, WS0 bits, and clear
the counter to "0" (WS1, WS0=oscillation stabilization wait time, WCL=0 write). If you wish to
perform the process with the interrupt after completion of the oscillation stabilization wait,
initialize the interrupt flag (WIF=0, WIE=0 write).
(2) Main clock oscillation begins (OSCCR bit0: OCSDS1=0 write).
(3) In the program, wait for the WIF flag to become "1".
(4) Confirm that the WIF flag is "1", and perform the process after completion of the oscillation
stabilization wait. If interrupts have been enabled, an interrupt is generated when WIF=1, so
perform the process by the interrupt routine after completion of the oscillation stabilization wait.
When switching from the sub clock to the main clock too, do so after waiting for confirmation of WIF=1 in
(4) (If the main clock is switched to without waiting for oscillation stabilization, an unstable clock is
supplied throughout the whole device and the subsequent actions are not guaranteed).
■ Counter Status at the Transition to the Main Clock When Main Oscillation Stabilization
Wait Timer is Activated
When the main oscillation stabilization wait timer has been activated, the counter status at the time of
transfer to the main clock is shown below.
Figure 11.4-1 Counter Status at the Transition to the Main Clock
When Main Oscillation Stabilization Wait Timer is Activated
7FFFFF H
Counter value
Main clock
oscillation
stabilization wait time
Timer clear (WCL=1) Note: When other than 0
Interval time setting (WS1, WS0=11B)
Main oscillation start (OSCCR:OSCDS1=0)
Cleared by the
interrupt routine
WIF (interrupt request)
WIE (interrupt mask)
Clock mode
Sub clock
Main clock
Sub clock → main clock change
223
CHAPTER 11 MAIN OSCILLATION STABILIZATION WAIT TIMER
■ Notes When Using The Main Oscillation Stabilization Wait Timer
• Since the oscillation cycle is unstable immediately after the oscillation starts, the oscillation
stabilization wait time is an approximate value.
• When the main clock has stopped oscillation, the counter is also stopped, therefore, the main
oscillation stabilization interrupt is not generated either. To perform a process using the main
oscillation stabilization interrupt, do not stop the main oscillation.
• When the WIF flag set request and the "0" clear timing from the CPU overlap, the flag set is given
priority and "0" clear becomes invalid.
■ Example of Switching between the Main Clock ↔ the Sub Clock
An example of switching between the main clock and the sub clock is given below.
Figure 11.4-2 Example of Switching Main Clock ↔ Sub-Clock
Main run
Sub-run
4MHz oscillation activated
RTC 32kHz activated
PLL ON
RTC interrupt
end
NO
Main oscillation stabilization
wait timer activated
YES
Main clock switched,
PLL → divided by 2
PLL OFF
Main oscillation
stabilization ON
INT
YES
Source clock switched
4MHz → 32kHz
Source clock switched
32kHz → 4MHz
Main clock switched,
divided by 2 → PLL
4MHz oscillation stopped
Sub-run
224
Main run
NO
CHAPTER 12
16-BIT FREE-RUN TIMER
This chapter explains the overview of the 16-bit free-run
timer, the register configuration and functions, and the
timer operation.
12.1 Overview of 16-bit Free-run Timer
12.2 Register of 16-bit Free-run Timer
12.3 Description of 16-bit Free-run Timer Operation
225
CHAPTER 12 16-BIT FREE-RUN TIMER
12.1
Overview of 16-bit Free-run Timer
This section describes the overview and block diagram of the 16-bit free-run timer.
■ Features of 16-bit Free-run Timer
The 16-bit free-run timer consists of the 16-bit up counter and the control status register. The count
values of this timer are used as the basic times (base timer) of the output compare and input capture.
The MB91245/S series contains two 16-bit free-run timers;
The MB91245/S series contains a pair of 16-bit free-run timers. 16-bit free-run timer 0 is used for
output compare 0/1 and input capture 0/1.
16-bit free-run timer 1 is used as the base timer for input capture 2/3.
• The count clock can be selected from among 4 types.
• A counter overflow can generate an interrupt.
• Mode setting enables initialization of the counter of the 16-bit free-run timer 0 through matching
with values of the compare register 0 (OCCP0) of output compare.
■ Register List of 16-bit Free-run Timer
Figure 12.1-1 Register List of 16-bit Free-run Timer
TCDT0, TCDT1 (Upper byte)
bit
15
Address: ch.0 000D4H
T15
ch.1 000D8H
Read/Write
(R/W)
Initial value
(0)
14
T14
13
T13
12
T12
11
T11
10
T10
9
T9
8
T8
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
6
T6
5
T5
4
T4
3
T3
2
T2
1
T1
0
T0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
7
ELCK
6
IVF
5
IVFE
4
STOP
3
MODE
2
CLR
1
CLK1
0
CLK0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
TCDT0, TCDT1 (Lower byte)
bit
7
Address: ch.0 000D5H
T7
ch.1 000D9H
Read/Write
(R/W)
Initial value
(0)
TCCS0, TCCS1
bit
Address: ch.0 000D7H
ch.1 000DBH
Read/Write
Initial value
226
CHAPTER 12 16-BIT FREE-RUN TIMER
■ Block Diagram of 16-bit Free-run Timer
Figure 12.1-2 Block Diagram of 16-bit Free-run Timer
Interrupt
IVF
IVFE
STOP
MODE CLR
CLK1 CLK0
R-bus
ECLK
Frequency divider
φ
CK0
Clock selection
16-bit free-run timer
timer data register(TCDT)
CK1
Clock
To internal circuits (T15 to T00)
Comparator 0
(For the case of free-run timer 0)
227
CHAPTER 12 16-BIT FREE-RUN TIMER
12.2
Register of 16-bit Free-run Timer
This section describes the configuration and functions of registers used by the 16-bit
free-run timer.
■ Timer Data Register (TCDT)
Figure 12.2-1 Bit Configuration of Timer Data Register (TCDT)
TCDT0, TCDT1 (Upper byte)
bit
15
Address: ch.0 000D4H
T15
ch.1 000D8H
Read/Write
(R/W)
Initial value
(0)
TCDT0, TCDT1 (Lower byte)
bit
7
T7
Address: ch.0 000D5H
ch.1 000D9H
Read/Write
(R/W)
Initial value
(0)
14
T14
13
T13
12
T12
11
T11
10
T10
9
T9
8
T8
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
6
T6
5
T5
4
T4
3
T3
2
T2
1
T1
0
T0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
This register can read the count values of the 16-bit free-run timer. The counter values are cleared to
"0000H" at a reset. The timer values can be set by writing them to this register.
Be sure to write values in the stopped status (STOP =1). Access must be made word-by-word.
The timer is initialized according to one of the following factors:
• Reset
• Initialization by clearing (CLR) of the control status register
• Initialization of the counter of the 16-bit free-run timer 0 through matching between the compare
register 0 (OCCP0) values of the output compare and timer counter values (mode setting required)
228
CHAPTER 12 16-BIT FREE-RUN TIMER
■ Timer Control Register (TCCS)
Figure 12.2-2 Bit Configuration of Timer Control Register (TCCS)
TCCS0, TCCS1
bit
Address: ch.0 000D7H
ch.1 000DBH
Read/Write
Initial value
7
ELCK
6
IVF
5
IVFE
4
STOP
3
MODE
2
CLR
1
CLK1
0
CLK0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
[bit7] ECLK
Used to select an internal or external clock as the count clock source of the 16-bit free-run timer. Select
a clock source while the output compare and input capture are stopped.
ECLK
Clock selection
0
An internal clock source is selected [Initial value].
1
An external pin is selected (CK0, CK1).
Note:
If an internal clock is selected, set the count clock to bit1 (CLK1) and bit0 (CLK0) of the TCDT
register. This count clock is used as the base clock. To input the clock from FRCK, set the
corresponding DDR bit to "0".
The minimum pulse width required for the external clock is 2 T (T: peripheral clock cycle).
If the external clock is specified and the output compare is used, a compare match and interrupt will
occur in the next clock cycle. Therefore, to generate compare match output and an interrupt, at least
"1 clock cycle" must be input after a compare match.
[bit6] IVF
Used as the interrupt request flag of the 16-bit free-run timer.
This bit is set to "1" if the 16-bit free-run timer has overflowed or if a compare match has occurred with
the compare register 0 (OCCP0) of the output compare by the mode setting and the counter of the 16-bit
free-run timer 0 has been cleared.
An interrupt will occur if the interrupt request enable bit (IVFE) is set.
This bit is cleared when "0" is written to it. A read-modify-write (RMW) instruction always reads "1"
from this bit.
IVF
Interrupt request flag
0
No interrupt request [Initial value]
1
An interrupt request is generated
229
CHAPTER 12 16-BIT FREE-RUN TIMER
[bit5] IVFE
Used as the interrupt enable bit of the 16-bit free-run timer.
If this bit is "1", an interrupt will occur when the interrupt flag (IVF) is set to "1".
IVFE
Interrupt enable
0
Interrupt disabled [Initial value]
1
Interrupt enabled
[bit4] STOP
Used to stop the count of the 16-bit free-run timer.
STOP
Count operation
0
Counting enabled (operation) [Initial value]
1
Counting disabled (stop)
Note:
When the 16-bit free-run timer stops, the output compare operation also stops.
[bit3] MODE
Used to set the initialization condition of the 16-bit free-run timer.
If this bit is "0", the counter value can be initialized by the reset and clear bit (bit2: CLR).
If this bit is "1", the counter value can be initialized through matching with the compare register value of
the output compare, in addition to using the reset and clear bit (bit2: CLR). In this case, the 16-bit freerun timer ch.0 is initialized through matching with the compare register 0 (OCCP0) of the output
compare.
MODE
230
Initialization condition of the timer
0
Initialization by the reset or clear bit [Initial value]
1
Initialization by the reset, clear bit, or compare register
CHAPTER 12 16-BIT FREE-RUN TIMER
[bit2] CLR
Used to initialize values of the 16-bit free-run timer in operation, to "0000H".
By writing "1" to this bit, the timer value is initialized to "0000H". The read value is always "0". CLR is
reset when "0" is written to it.
Note:
The counter value is initialized to the point where count value changes. After "1" is written to this bit,
the timer value will not be initialized if "0" is written to this bit before the count value changes.
To initialize the timer value while the timer stops, write "0000H" to the data register. Clearing the
timer by CLR is forbidden while the timer stops.
[bit1, bit0] CLK1, CLK0
Used to select the count clock of the 16-bit free-run timer.
After values are written to these bits, the count clock is immediately changed. Change these bits while
the output compare and input capture are stopped.
CLK1
CLK0
Count clock
fccp =32MHz
fccp = 16MHz
0
0
fccp/22
125ns
250ns
0
1
fccp/24
0.5μs
1μs
1
0
fccp/25
1μs
2μs
1
1
fccp/26
2μs
4μs
fccp : Peripheral clock frequency
231
CHAPTER 12 16-BIT FREE-RUN TIMER
12.3
Description of 16-bit Free-run Timer Operation
The 16-bit free-run timer starts counting from the counter value "0000H" after the reset
is released. This counter value is the base time of the 16-bit output compare and 16-bit
input capture.
■ Description of 16-bit Free-run Timer Operations
The counter values are cleared under the following conditions:
• Overflow has occurred.
• A compare match has occurred with the compare register 0 (OCCP0) value of the output compare
(Mode setting is required).
• During operation, "1" was written in the CLR bit of the TCCS register.
• While the timer stops, "0000H" was written in TCDT.
• A reset has been applied.
If an overflow has occurred, an interrupt generate when a compare match occurs with the compare
register 0 (OCCP0) value of the output compare and the counter is cleared (A compare match interrupt
requires the mode setting).
Figure 12.3-1 Counter Clearing by Overflow
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
Interrupt
232
CHAPTER 12 16-BIT FREE-RUN TIMER
Figure 12.3-2 Counter Clearing by a Compare Match with the Compare Clear Register Value
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
Compare
register
BFFFH
Interrupt
■ 16-bit Free-run Timer Clear Timing
The counter is cleared by a reset, software, or a match with a compare clear register value.
Counter clearing by a reset or software occurs together with generation of clearing. However, counter
clearing by a match with the compare clear register 0 is synchronous with the count timing.
Figure 12.3-3 16-bit Free-run Timer Clear Timing
φ
Compare clear register value
N
Counter clear
Counter value
N
0000H
■ 16-bit Free-run Timer Count Timing
The 16-bit free-run timer is incremented by an input clock (an internal or external clock). If an external
clock is selected, the falling edge ↓ of the external clock is synchronized with the system clock and then
the timer is counted on the falling edge of the internal count clock.
Figure 12.3-4 16-bit Free-run Timer Count Timing
φ
External clock input
Internal clock input
Counter value
N
N+1
233
CHAPTER 12 16-BIT FREE-RUN TIMER
■ Notes of 16-bit Free-run Timer
• If the interrupt request flag set timing overlaps with the clear timing, the flag set operation is given
priority and the clear operation becomes invalid.
• After "1" is written in bit2 (counter initial bit: CLR) of the control register, the counter value is
initialized to the point where count value changes. After "1" is written in this bit, the timer value is
not initialized if "0" is written to this bit before the counter value changes.
• The counter clear operation is valid only while the internal counter is running (the internal prescaler
is also operating). To clear the counter while it stops, write "0000H" in the timer count data register.
234
CHAPTER 13
INPUT CAPTURE
This chapter describes the overview of the input
capture, the configuration and functions of registers,
and the operation of the input capture.
13.1 Overview of Input Capture
13.2 Registers of Input Capture
13.3 Operation of Input Capture
235
CHAPTER 13 INPUT CAPTURE
13.1
Overview of Input Capture
This section describes the features and block diagram of the input capture.
■ Features of Input Capture
This module can detect the rising and/or falling edge of a signal supplied from outside, and hold the 16-bit
free-run timer value at that time in a register. It can also generate an interrupt when detecting an edge.
The input capture unit consists of input capture data registers and control registers.
Each input capture unit has the corresponding external input pins.
• One of three types of edges of external inputs can be selected as the effective edge.
- Rising edge
- Falling edge
- Both edges
• An interrupt can be generated when the effective edge of an external inputs is detected.
236
CHAPTER 13 INPUT CAPTURE
■ Register List of Input Capture
Figure 13.1-1 shows the register list of input capture.
Figure 13.1-1 Register List of Input Capture
IPCP (upper byte)
Address:
bit 15
0000ECH (IPCP3)
CP15
0000EEH (IPCP2)
0000E4H (IPCP1)
0000E6H (IPCP0)
Read/Write
(R)
Initial value
(X)
IPCP (lower byte)
Address:
bit 7
0000EDH (IPCP3)
CP7
0000EFH (IPCP2)
0000E5H (IPCP1)
0000E7H (IPCP0)
Read/Write
(R)
Initial value
(X)
ICS23
Address:
0000F3H
bit 7
ICP3
Read/Write (R/W)
Initial value
(0)
ICS01
Address:
0000EBH
bit 7
ICP1
Read/Write (R/W)
Initial value
(0)
14
CP14
13
CP13
12
CP12
11
CP11
10
CP10
9
CP9
8
CP8
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
6
CP6
5
CP5
4
CP4
3
CP3
2
CP2
1
CP1
0
CP0
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
6
ICP2
(R/W)
(0)
5
ICE3
(R/W)
(0)
4
ICE2
(R/W)
(0)
3
EG31
(R/W)
(0)
2
EG30
(R/W)
(0)
1
EG21
(R/W)
(0)
0
EG20
(R/W)
(0)
6
ICP0
(R/W)
(0)
5
ICE1
(R/W)
(0)
4
ICE0
(R/W)
(0)
3
EG11
(R/W)
(0)
2
EG10
(R/W)
(0)
1
EG01
(R/W)
(0)
0
EG00
(R/W)
(0)
237
CHAPTER 13 INPUT CAPTURE
■ Block Diagram of Input Capture
Figure 13.1-2 shows the block diagram of input capture.
Figure 13.1-2 Block Diagram of Input Capture
16-bit timer (ch.0) count value
EG11
R-bus
IN0
input pin
Edge
detection
Capture data register
ch.0
EG10
EG11
EG00
16-bit timer (ch.0) count value
IN1
input pin
Edge
detection
Capture data register
ch.1
ICP1
ICP0
ICE1
ICE0
Interrupt
Interrupt
Note: In the case of input capture unit 0 or 1
238
CHAPTER 13 INPUT CAPTURE
13.2
Registers of Input Capture
This section describes the configuration and functions of registers used by the input
capture.
■ Input Capture Register (IPCP)
Figure 13.2-1 Bit Configuration of Input Capture Register (IPCP)
IPCP (upper byte)
Address:
bit 15
0000ECH (IPCP3)
CP15
0000EEH (IPCP2)
0000E4H (IPCP1)
0000E6H (IPCP0)
Read/Write
(R)
Initial value
(X)
IPCP (lower byte)
Address:
bit 7
0000EDH (IPCP3)
CP7
0000EFH (IPCP2)
0000E5H (IPCP1)
0000E7H (IPCP0)
Read/Write
(R)
Initial value
(X)
14
CP14
13
CP13
12
CP12
11
CP11
10
CP10
9
CP9
8
CP8
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
6
CP6
5
CP5
4
CP4
3
CP3
2
CP2
1
CP1
0
CP0
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
When the effective edge of the wave form at the pertinent external pin is detected, this register holds the
16-bit free-run timer value at that time. At the time of reset, the values of this register are undefined.
This register can be accessed when an attempt is made to read either 16 or 32 bits of data at one time. You
cannot write data in this register.
239
CHAPTER 13 INPUT CAPTURE
■ Input Capture Control Register (ICS)
Figure 13.2-2 Bit Configuration of Input Capture Control Register (ICS)
ICS23
Address:
0000F3H
bit 7
ICP3
Read/Write (R/W)
Initial value
(0)
ICS01
Address:
0000EBH
bit 7
ICP1
Read/Write (R/W)
Initial value
(0)
6
ICP2
(R/W)
(0)
5
ICE3
(R/W)
(0)
4
ICE2
(R/W)
(0)
3
EG31
(R/W)
(0)
2
EG30
(R/W)
(0)
1
EG21
(R/W)
(0)
0
EG20
(R/W)
(0)
6
ICP0
(R/W)
(0)
5
ICE1
(R/W)
(0)
4
ICE0
(R/W)
(0)
3
EG11
(R/W)
(0)
2
EG10
(R/W)
(0)
1
EG01
(R/W)
(0)
0
EG00
(R/W)
(0)
[bit7, bit6] ICP3, ICP2 (ICP1, ICP0)
These bits represent the input capture interrupt flag. When the effective edge of the external input
pin is detected, these bits are set to "1". If the interrupt enable bits (ICE3 to ICE0) are set, an
interrupt can be generated by detecting the effective edge. These bits will be cleared when "0" is
written. Writing "1" to these bits produces no effect. Read-modify-write (RMW) instructions can
read "1" from these bits.
0: No effective edge detected [Initial value]
1: Effective edge detected
ICPn: "n" represents the input capture channel number.
[bit5, bit4] ICE3, ICE2 (ICE1, ICE0)
There bits indicate whether to enable input capture interrupts. If there bits are "1", an input capture
interrupt will be generated when the interrupt flags (ICP3 to ICP0) are set to "1".
0: Interrupt disabled [Initial value]
1: Interrupt enabled
ICEn: "n" represents the input capture channel number.
[bit3 to bit0] EG31, EG30, EG21, EG20 (EG11, EG10, EG01, EG00)
These bits specify which edge polarity of the external input is effective. They also work to initiate
input capture operation.
EGn1
EGn0
Edge detection polarity
0
0
No edge detection (inactive) [Initial value]
0
1
Rising edge detection ↑
1
0
Falling edge detection ↓
1
1
Detection of both edges ↑ & ↓
EGn1/EGn0: "n" represents the input capture channel number.
240
CHAPTER 13 INPUT CAPTURE
13.3
Operation of Input Capture
This section describes the operation of the input capture.
■ Fetch Timing for Input Capture
The input capture function can fetch the 16-bit free-run timer value into the capture register and generate an
interrupt when it detects a predetermined effective edge.
Figure 13.3-1 Example of Fetch Timing for Input Capture
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
IN0
IN1
IN2
Data register 0
Indefinite
3FFFH
Data register 2
BFFFH
Indefinite
Data register 1
Indefinite
BFFFH
7FFFH
Capture 0 interrupt
Capture 1 interrupt
Capture 2 interrupt
Capture 0: Rising edge
Capture 1: Falling edge
Capture 2: Both edges
Interrupt generation due to re-detection
of an effective edge
Interrupt clearing by software
241
CHAPTER 13 INPUT CAPTURE
■ 16-Bit Input Capture Input Timing
Figure 13.3-2 shows the example of 16-bit input capture input timing.
Figure 13.3-2 16-Bit Input Capture Input Timing
φ
Counter value
Input capture input
N
N+1
Effective edge
Capture signal
Capture register value
Interrupt
242
N+1
CHAPTER 14
OUTPUT COMPARE
This chapter describes the overview of the output
compare, the configuration and functions of registers,
and the operation of the output compare.
14.1 Overview of Output Compare
14.2 Register of Output Compare
14.3 Operation of Output Compare
243
CHAPTER 14 OUTPUT COMPARE
14.1
Overview of Output Compare
This section describes the features and block diagram of the output compare.
■ Features of Output Compare
Output compare module consists of bit compare register, compare output latch and control register.
When 16-bit free-run timer value matches with compare register value, output level inverts and the
interrupt is issued.
•
2 compare registers can be used independently.
Output pin and interrupt flag correspond to compare register.
•
Output pin is controllable based on a pair of 2 compare registers.
Output pin is invertible by using 2 compare registers.
•
The initial value of output pin can be set.
•
When the compare matches, the interrupt can be generated.
■ Register List of Output Compare
Figure 14.1-1 Register LIst of Output Compare
OCCP (upper bytes)
Address:
bit 15
000108H(OCCP1)
C15
00010AH(OCCP0)
Read/Write (R/W)
Initial value
(X)
OCCP (lower bytes)
Address:
bit 7
000109H(OCCP1)
C7
00010BH(OCCP0)
Read/Write (R/W)
Initial value
(X)
14
C14
13
C13
12
C12
11
C11
10
C10
9
C9
8
C8
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
6
C6
5
C5
4
C4
3
C3
2
C2
1
C1
0
C0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
14
---(R/W)
(1)
13
---(R/W)
(1)
12
CMOD
(R/W)
(0)
11
---(R/W)
(1)
10
---(R/W)
(1)
9
OTD1
(R/W)
(0)
8
OTD0
(R/W)
(0)
6
ICP0
(R/W)
(0)
5
ICE1
(R/W)
(0)
4
ICE0
(R/W)
(0)
3
---(R/W)
(1)
2
---(R/W)
(1)
1
CST1
(R/W)
(0)
0
CST0
(R/W)
(0)
OCS01 (upper bytes)
bit 15
---Read/Write (R/W)
Initial value
(1)
Address: 000112H
OCS01 (lower bytes)
bit 7
ICP1
Read/Write (R/W)
Initial value
(0)
Address: 000113H
244
CHAPTER 14 OUTPUT COMPARE
■ Block Diagram of Output Compare
Figure 14.1-2 shows the block diagram of output compare.
Figure 14.1-2 Block Diagram of Output Compare
OTD1
OTD0
Compare register
Latch for
compare output
Compare circuit
OTE0
Output (ch.0)
R-bus
Compare register
CMOD
Latch for
compare output
Compare circuit
CST1
Output (ch.1)
CST0
ICP1
16-bit
free-run timer (0)
OTE1
ICP0
ICE1
ICE0
Interrupt output
Interrupt output
245
CHAPTER 14 OUTPUT COMPARE
14.2
Register of Output Compare
This section describes the configuration and functions of registers used by the output
compare.
■ Compare Register (OCCP)
Figure 14.2-1 Bit Configuration of Compare Register (OCCP)
OCCP (upper bytes)
Address:
bit 15
000108H (OCCP1)
C15
00010AH (OCCP0)
Read/Write (R/W)
Initial value
(X)
OCCP (lower bytes)
Address:
bit 7
000109H (OCCP1)
C7
00010BH (OCCP0)
Read/Write (R/W)
Initial value
(X)
14
C14
13
C13
12
C12
11
C11
10
C10
9
C9
8
C8
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
6
C6
5
C5
4
C4
3
C3
2
C2
1
C1
0
C0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
This is a 16-bit length compare register to compare with a 16-bit free-run timer. Since the initial value
of this register is indeterminate, enable the start after setting the compare value. Use 16 bits or 32 bits to
access this register. When this register value matches with the 16-bit free-run timer value, the compare
signal will be generated and set the output compare interrupt flag. And if it has set the corresponding
OTE of port function register (PFR) and enabled the output, it inverts the output level corresponding to
the compare register.
246
CHAPTER 14 OUTPUT COMPARE
■ Output Control Register (OCS)
Figure 14.2-2 Bit Configuration of Output Control Register (OCS)
OCS01 (upper bytes)
bit 15
Read/Write (R/W)
Initial value
(1)
Address: 000112H
14
(R/W)
(1)
13
(R/W)
(1)
12
CMOD
(R/W)
(0)
11
(R/W)
(1)
10
(R/W)
(1)
9
OTD1
(R/W)
(0)
8
OTD0
(R/W)
(0)
6
ICP0
(R/W)
(0)
5
ICE1
(R/W)
(0)
4
ICE0
(R/W)
(0)
3
(R/W)
(1)
2
(R/W)
(1)
1
CST1
(R/W)
(0)
0
CST0
(R/W)
(0)
OCS01 (lower bytes)
bit 7
ICP1
Read/Write (R/W)
Initial value
(0)
Address: 000113H
[bit15 to bit13] Unused bits
In a read, only "1" is read.
[bit12] CMOD
Specifies the pin output level inversion operation in compare match when output pin is enabled.
When CMOD =0 (initial value), it inverts the pin output level corresponding to the compare register.
OC0: Inverts the level using the match of compare register 0.
OC1: Inverts the level using the match of compare register 1.
When CMOD =1
OC0: Inverts the level using the match of compare register 0.
OC1: Inverts the level using the match of compare registers 0 and 1.
[bit9, bit8] OTD1, OTD0
Specify the pin output level when output pin of output compare register is enabled. Specify after
stopping the compare operation. In a read operation, output compare pin output is read.
0: Sets the compare pin output to "0". [Initial value]
1: Sets the compare pin output to "1".
[bit7, bit6] ICP1, ICP0
These are the interrupt flags for output compare. When the compare register matches with 16-bit freerun timer value, these are set to "1". If these bits are set to "1" while interrupt request bits (ICE1, ICE0)
are enabled, output compare interrupt will occur. These bits are cleared by writing "0", and writing "1"
has no effect. In the case of read-modify-write (RMW) instruction, "1" is read.
0: Without output compare match [Initial value]
1: With output compare match
If an external clock is specified to the free-run timer, compare match and interrupt will be generated in
the next clock. In order to generate the compare match output and interrupt, therefore, at least "1 clock"
should be input to the external clock of free-run timer after the compare match.
247
CHAPTER 14 OUTPUT COMPARE
[bit5, bit4] ICE1, ICE0
These bits enable the interrupt of output compare. If the interrupt flags (ICP1, ICP0) are set to "1" while
these bits are "1", the output compare interrupt will be generated.
0: Disable output compare interrupt [Initial value]
1: Enable output compare interrupt
[bit3, bit2] Unused bits
In a read, only "1" is read.
[bit1, bit0] CST1, CST0
These bits enable the matching operation with 16-bit free-run timer. Do not fail to set the compare
register value and the output control register value before enabling compare operation.
0: Disable compare operation [Initial value]
1: Enable compare operation
Since output compare is synchronized with 16-bit free-run timer, the compare operation will also stop if
16-bit free-run timer is stopped.
248
CHAPTER 14 OUTPUT COMPARE
14.3
Operation of Output Compare
This section describes the operation of the output compare.
■ Operation of Output Compare
Output compare makes comparisons between the set compare register value and the 16-bit free-run
timer value, and if the values match, it sets the interrupt flag and can invert the output level.
Figure 14.3-1 show the example of the output wave form when 1 channel can independently perform
the compare operation (When CMOD =0).
Figure 14.3-1 Examples of Output Wave form when the Compare Registers 0, 1 are Used
(Initial Value of Output is "0")
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare register 0 value
BFFFH
Compare register 1 value
7FFFH
OP0 output
OP1 output
Compare 0 interrupt
Compare 1 interrupt
249
CHAPTER 14 OUTPUT COMPARE
Figure 14.3-2 show the example of the output wave form when the output level is changed by using 2
sets of compare registers (When CMOD =1).
Figure 14.3-2 Examples of Output Wave form when the Compare Registers 0, 1 are Used
(the Initial Value of Output is "1")
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare register 0 value
BFFFH
Compare register 1 value
7FFFH
OP0 output
OP1 output
Compare 0 interrupt
Compare 1 interrupt
250
CHAPTER 14 OUTPUT COMPARE
■ Operation Timing of 16-bit Output Compare
You can change the output level by using 2 sets of compare registers (When CMOD = 1).
Output compare can invert the output and generate an interrupt with the compare match signal
generated when the free-run timer matches with the set compare register value. Output inversion timing
at the instant of the compare match is made in synchronization with the count timing of the counter.
<Compare register Write timing>
At the time of rewriting compare register, the register does not compare with the counter value.
N
Counter value
N+1
N+2
N+3
Signal match is not generated.
M
Compare clear register 0 value
N+1
Compare register write 0
L
Compare clear register 1 value
N+3
Compare register write 1
Compare 0 stop
Compare 1 stop
<Compare match, Interrupt timing>
φ
Count clock
N
Counter value
Compare register value
N+1
N+3
N+2
N
Compare match
Pin output
Interrupt
<Pin output timing>
Counter value
Compare register value
N
N+1
N+1
N+1
N
Compare match
Pin output
251
CHAPTER 14 OUTPUT COMPARE
252
CHAPTER 15
U-TIMER
This chapter describes the U-TIMER, the configuration
and functions of registers, and U-TIMER operation.
15.1 Overview of U-Timer
15.2 Register of U-Timer
15.3 Operation of U-Timer
253
CHAPTER 15 U-TIMER
15.1
Overview of U-Timer
This section describes the overview and block diagram of the U-Timer (16-bit timer for
UART baud rate generation).
■ Features of U-Timer
The U-Timer is a 16-bit timer for generating the UART baud rate. Any baud rate can be set by
combining the chip operating frequency and the U-Timer reload value.
■ Register List of U-Timer
Figure 15.1-1 shows the register list of U-TIMER.
Figure 15.1-1 Register List of U-Timer
UTIM (upper timer)
bit
Address: 000064H
Read/Write
Initial value
15
B15
(R)
(0)
14
B14
(R)
(0)
13
B13
(R)
(0)
12
B12
(R)
(0)
11
B11
(R)
(0)
10
B10
(R)
(0)
9
B9
(R)
(0)
8
B8
(R)
(0)
7
B7
(R)
(0)
6
B6
(R)
(0)
5
B5
(R)
(0)
4
B4
(R)
(0)
3
B3
(R)
(0)
2
B2
(R)
(0)
1
B1
(R)
(0)
0
B0
(R)
(0)
15
B15
(W)
(0)
14
B14
(W)
(0)
13
B13
(W)
(0)
12
B12
(W)
(0)
11
B11
(W)
(0)
10
B10
(W)
(0)
9
B9
(W)
(0)
8
B8
(W)
(0)
7
B7
(W)
(0)
6
B6
(W)
(0)
5
B5
(W)
(0)
4
B4
(W)
(0)
3
B3
(W)
(0)
2
B2
(W)
(0)
1
B1
(W)
(0)
0
B0
(W)
(0)
bit
Address: 000067H
Read/Write
Initial value
7
UCC1
(R/W)
(0)
6
(-)
(-)
5
(-)
(-)
4
UTIE
(R/W)
(0)
3
UNDR
(R/W)
(0)
2
CLKS
(R/W)
(0)
1
UTST
(R/W)
(0)
0
UTCR
(R/W)
(1)
bit
Address: 000066H
Read/Write
Initial value
7
(W)
(-)
6
(W)
(-)
5
(W)
(-)
4
(W)
(-)
3
(W)
(-)
2
(W)
(-)
1
(W)
(-)
0
(W)
(-)
UTIM (lower timer)
bit
Address: 000065H
Read/Write
Initial value
UTIMR (upper timer)
bit
Address: 000064H
Read/Write
Initial value
UTIMR (lower timer)
bit
Address: 000065H
Read/Write
Initial value
UTIMC
DRCL
254
CHAPTER 15 U-TIMER
■ Block Diagram of U-Timer
Figure 15.1-2 shows the block diagram of U-Timer.
Figure 15.1-2 Block Diagram of U-Timer
bit15
bit0
UTIMR (reload register)
UTIM (U-Timer)
Control
φ
(Peripheral clock)
Underflow
F/F
To UART
255
CHAPTER 15 U-TIMER
15.2
Register of U-Timer
This section describes the configuration and functions of registers used by the
U-Timer.
■ U-Timer (UTIM)
UTIM (Upper timer)
bit
Address: 000064H
Read/Write
Initial value
15
B15
(R)
(0)
14
B14
(R)
(0)
13
B13
(R)
(0)
12
B12
(R)
(0)
11
B11
(R)
(0)
10
B10
(R)
(0)
9
B9
(R)
(0)
8
B8
(R)
(0)
7
B7
(R)
(0)
6
B6
(R)
(0)
5
B5
(R)
(0)
4
B4
(R)
(0)
3
B3
(R)
(0)
2
B2
(R)
(0)
1
B1
(R)
(0)
0
B0
(R)
(0)
UTIM (Lower timer)
bit
Address: 000065H
Read/Write
Initial value
UTIM indicates the timer value. Access using 16-bit transfer instructions.
Note:
It is prohibited to set the reload register (UTIMER) to 0 when using the U-TIMER value as the baud
rate in UART mode 2 (CLK synchronous mode).
■ Reload Register (UTIMER)
UTIMR (Upper timer)
bit
Address: 000064H
Read/Write
Initial value
15
B15
(W)
(0)
14
B14
(W)
(0)
13
B13
(W)
(0)
12
B12
(W)
(0)
11
B11
(W)
(0)
10
B10
(W)
(0)
9
B9
(W)
(0)
8
B8
(W)
(0)
7
B7
(W)
(0)
6
B6
(W)
(0)
5
B5
(W)
(0)
4
B4
(W)
(0)
3
B3
(W)
(0)
2
B2
(W)
(0)
1
B1
(W)
(0)
0
B0
(W)
(0)
UTIMR (Lower timer)
bit
Address: 000065H
Read/Write
Initial value
UTIMR is the register that stores the value reloaded by UTIM when UTIM has underflowed.
Access using 16-bit transfer instructions.
256
CHAPTER 15 U-TIMER
■ U-Timer Control Register (UTIMC)
UTIMC controls U-Timer operations.
UTIMC
bit
Address: 000067H
Read/Write
Initial value
7
UCC1
(R/W)
(0)
6
(-)
(-)
5
(-)
(-)
4
UTIE
(R/W)
(0)
3
UNDR
(R/W)
(0)
2
CLKS
(R/W)
(0)
1
UTST
(R/W)
(0)
0
SUCR
(R/W)
(1)
[bit7] UCC1 (U-timer Count Control)
UCC1 bit controls the U-Timer count method.
UCC1
Operation
0
Operates normally. α=2n+2
1
+1Mode α=2n+3
n: UTIM set value
α: Output clock cycle to UART
UTIMC can set odd numbered divisions in addition to normal 2 (n+1) clock cycles for UART. If UCC1
is set to "1", a cycle of 2n+3 will be generated.
Setting example:
• UTIM = 5, UCC1 = 0 → Generation cycle= 2n+2= 12 cycles
• UTIM = 25, UCC1 = 1 → Generation cycle= 2n+3= 53 cycles
• UTIM = 60, UCC1 = 0 → Generation cycle= 2n+2= 122 cycles
[bit6, bit5] (Reserved bits)
[bit4] UTIE (Reserved)
Always write "0".
[bit3] UNDR (Underflow Flag)
UNDR is the flag that shows an underflow has been generated. UNDR is cleared by a reset or writing
"0".
When reading a read-modify-write (RMW) instruction, "1" will always be read.
Further, writing "1" to UNDR is disabled.
[bit2] CLKS (Reserved bit)
Always write "0".
[bit1] UTST (U-Timer Start)
This is the UTIM start bit.
0: Stop. Stop by writing "0" even during operations. [Initial value]
1: Operation. Even if "1" is written during operations, operations will continue.
257
CHAPTER 15 U-TIMER
[bit0] UTCR (U-Timer Clear)
If "0" is written to UTCR, the UTIM will be cleared to "0000H" (FF will also be cleared to "0").
When reading, "1" is always read.
Notes:
• If the start bit UTST is asserted (started) from a stop state, reloading will be performed
automatically.
• If the clear bit UTCR and the start bit UTST are asserted simultaneously from a stopped state, the
counter will be cleared to "0", and an underflow will be generated in the next count down.
• If clear bit UTCR is asserted during operations, the counter will be cleared to "0". Consequently, a
hazard may be output in the output wave form, and a misoperation may occur in the upper U-Timer.
If using an output clock, do not initialize by the clear bit during operation.
• If bit1 of the U-Timer control register (U-Timer start bit: UTST) and bit0 (U-Timer clear bit: UTCR)
are asserted simultaneously with the timer stopped, bit3 of the same register (underflow flag:
UNDR) will be set using counter load timing after the register has been cleared. Further, the
internal baud rate clock will be set to "H" level using the same timing.
• If the UNDR bit set timing and clear timing overlap, the flag setting will be prioritized, and the clear
operation becomes invalid.
• If writing to the U-Timer reload register and the reload timing overlap, the old data will be loaded
to the counter, and loading the new data to the counter will be performed according to the next
reload timing.
• If the timer clear and timer count/reload timing overlap, the timer clear operation will be prioritized.
■ DMA Interrupt Clear Register (DRCL)
The DMA interrupt clear register (DRCL) is used to prepare DMA transfers.
DRCL
bit
Address: 000066H
Read/Write
Initial value
7
(W)
(-)
6
(W)
(-)
5
(W)
(-)
4
(W)
(-)
3
(W)
(-)
2
(W)
(-)
If using DMA for the first time, first write to this register once before using DMA.
258
1
(W)
(-)
0
(W)
(-)
CHAPTER 15 U-TIMER
15.3
Operation of U-Timer
This section explains calculation of U-Timer baud rate.
■ Baud Rate Calculation
UART uses the corresponding U-Timer underflow flip-flop (FF in the diagram) as the baud rate clock
source.
● Asynchronous (Start-stop Synchronization) Mode
UART is used by dividing the U-Timer outputs into 16.
n : U-Timer (reload value)
φ : Peripheral machine clock frequency (changed by gear)
bps = φ / {(2n + 2) × 16} ... UCC1 =0
bps = φ / {(2n + 3) × 16} ... UCC1 =1
● Clock Synchronous Mode
n : U-Timer (reload value)
φ : Peripheral machine clock frequency (changed by gear)
bps = φ / (2n + 2) ... UCC1 =0
bps = φ / (2n + 3) ... UCC1 =1
Note:
It is prohibited to set the reload register (UTIMER) to "0" when using the U-Timer value as the baud
rate in UART mode 2 (Clock synchronous mode).
259
CHAPTER 15 U-TIMER
260
CHAPTER 16
EXTERNAL BUS INTERFACE
The external bus interface controls the internal bus and
external memory as well as I/O device interface.
16.1 Overview of External Bus Interface
16.2 Register of External Bus Interface
16.3 Endian and Bus Access of External Bus Interface
16.4 Normal Bus Interface of External Bus Interface
16.5 Register Setting Procedure of External Bus Interface
16.6 Notes on Using External Bus Interface
261
CHAPTER 16 EXTERNAL BUS INTERFACE
16.1
Overview of External Bus Interface
This section explains the features and block diagram of the external bus interface.
■ Features of External Bus Interface
• 16-bit long address output
• Data bus width, 8-bit/16-bit
• As well as a direct connection of each kind of external memory (8-bit/16-bit), mixed control of multiple
access timings is possible
Asynchronous SRAM, asynchronous ROM/Flash memory (multiple write strobe methods or byte enable
methods)
• Possible to set 4 independent banks (chip select areas) and have chip select output corresponding to each
one
Possible to set CS0X, CS1X in units of 64K/128K/256K/512Kbytes in allotted space in the external bus
area up to "003FFFFFH"
Possible to set CS2X, CS3X in units of 1M/2M/4M/8Mbytes in the "00400000H" to "00FFFFFFH"
space
There are boundary limits according to the area size
Note:
Even if a large area size is designated in this product, the image size stays on 64 Kbytes.
• It is possible to independently set the following functions for each chip select area
Enable and disable chip select areas (disabled areas are not accessed)
Access timing type configuration corresponding to each kind of memory
Detailed access timing configuration (separate access type configuration for wait cycles etc.)
Data bus width setting, 8-bit/16-bit
• Possible to set different detailed timings for each access timing type
- Possible to mix different configuration for each chip select area even if they are the same type
- Possible to set auto-wait up to 7 cycles (asynchronous SRAM, ROM, Flash, I/O areas)
- Possible to extend the bus cycle via external RDY input (asynchronous SRAM, ROM, Flash, I/O
areas)
- Possible to insert every kind of idle and recovery cycle, setup delay, etc.
• Possible to set unused external interface pins to be used as general-purpose I/O ports
262
CHAPTER 16 EXTERNAL BUS INTERFACE
■ Block Diagram of External Bus Interface
Figure 16.1-1 shows the block diagram of the external bus interface.
Figure 16.1-1 Block Diagram of External Bus Interface
Internal address bus
32
Internal data bus
32
External data bus
Write buffer
Switch
Read buffer
Switch
DATA BLOCK
ADDRESS BLOCK
+1 or +2
External address bus
Address buffer
ASR
CS0X to CS3X
ASZ
Comparator
External pin control unit
RDX
WR0X, WR1X,
ASX
All block controls
Register control unit
RDY
SYSCLK
263
CHAPTER 16 EXTERNAL BUS INTERFACE
■ I/O Pin
This is the external bus interface pin.
<Normal bus interface>
A15 to A00, D15 to D00
CS0X, CS1X, CS2X, CS3X
ASX, SYSCLK
RDX
WR0X, WR1X
RDY
■ Register List of External Bus Interface
The register configuration of the external bus interface is as follows.
Figure 16.1-2 Register LIst of External Bus Interface
Address
bit 31
24 23
16 15
00000640H
ASR0
ACR0
00000644H
ASR1
ACR1
00000648H
ASR2
ACR2
0000064CH
ASR3
ACR3
00000650H
reserved
reserved
00000654H
reserved
reserved
00000658H
reserved
reserved
0000065CH
reserved
reserved
00000660H
AWR0
AWR1
00000664H
AWR2
AWR3
00000668H
reserved
reserved
0000066CH
reserved
reserved
0
00000670H
−
−
−
−
00000674H
−
−
−
−
00000678H
−
−
−
−
0000067CH
−
−
−
−
00000680H
CSER
−
−
−
00000684H
−
−
−
−
00000688H
−
−
−
−
0000068CH
−
−
−
−
…
…
…
…
…
000007F8H
−
−
−
−
000007FCH
−
MODR
−
−
Reserved: This is a reserved register. "0" must be set if you write.
264
8 7
CHAPTER 16 EXTERNAL BUS INTERFACE
16.2
Register of External Bus Interface
This section describes the register of the external bus interface.
■ Overview of External Bus Interface's Registers
The external bus interface has the following six types of registers:
• ASR0 to ASR3(Area Select Register)
• ACR0 to ACR3(Area Configuration Register)
• AWR0 to AWR3(Area Wait Register)
• IOWR0 to IOWR3(I/O Wait Register for DMAC)
• CSER (Chip Select Enable register)
■ ASR0 to ASR3 (Area Select Register)
Figure 16.2-1 Bit Configuration of ASR0 to ASR3 (Area Select Register)
ASR0
Address:
0000 0640H
bit 15
-
...
...
8
-
7
A23
6
A22
ASR1
Address:
0000 0644H
bit 15
...
8
7
6
-
...
-
A23
A22
ASR2
Address:
0000 0648H
bit 15
...
8
7
6
-
...
-
A23
A22
ASR3
Address:
0000 064CH
bit 15
...
8
7
6
-
...
-
A23
A22
...
...
1
A17
0
A16
1
0
...
A17
A16
1
0
...
A17
A16
1
0
...
A17
A16
Initial value Access
0000H
R/W
XXXXH
R/W
XXXXH
R/W
XXXXH
R/W
[bit15 to bit8] (Reserved bits)
Set these bits to "0000H".
[bit7 to bit0] A23 to A16
ASR0 to ASR3 (Area Select Registers 0 to 3) specify the start address of each chip select area for CS0X
to CS3X.
The start address sets the upper 12 bits of A[23:16]. Each chip select area starts from the address set in
this register and is the range specified by the ASZ1, ASZ0 bits of the ACR0 to ACR3 registers.
The boundary of each chip select area accords with the setting of the ASZ1, ASZ0 bits of the ACR0 to
ACR3 registers. For example, when the area is set at 1Mbyte by the ASZ1, ASZ0 bits, the lower 4 bits
of the ASR0 to ASR3 registers are ignored and only the A[23:20] bit is significant.
The ASR0 register is initialized to "00H" by INIT and RST. ASR1 to ASR3 are not initialized by INIT
and RST and become indeterminate. After commencing LSI operations, the corresponding ASR register
must be set before the CSER register enables each chip select area.
265
CHAPTER 16 EXTERNAL BUS INTERFACE
Note:
Set ASR and ACR at the same time with word access.
To access ASR and ACR with half word, set ASR before ACR.
■ ACR0 to ACR3 (Area Configuration Register)
Figure 16.2-2 Bit Configuration of ACR0 to ACR3 (Area Configuration Register)
ACR0H
Address: bit
0000 0642H
ACR0L
Address: bit
0000 0643H
ACR1H
Address: bit
0000 0646H
ACR1L
Address: bit
0000 0647H
ACR2H
Address: bit
0000 064AH
ACR2L
Address: bit
0000 064BH
ACR3H
Address: bit
0000 064EH
ACR3L
Address: bit
0000 064FH
15
-
14
-
13
ASZ1
12
ASZ0
7
-
11
-
10
DBW0
9
-
8
-
Initial value
XX110*00B
Access
R/W
6
5
4
3
2
1
0
-
WREN
-
TYP3
TYP2
TYP1
TYP0
00000000B
R/W
15
-
14
-
13
ASZ1
12
ASZ0
11
-
10
DBW0
9
-
8
-
0XXX0X00B
R/W
7
6
5
4
3
2
1
0
-
-
WREN
-
TYP3
TYP2
TYP1
TYP0
00X0XXXXB
R/W
15
-
14
-
13
ASZ1
12
ASZ0
11
-
10
DBW0
9
-
8
-
XXXX0X00B
R/W
7
6
5
4
3
2
1
0
-
-
WREN
-
TYP3
TYP2
TYP1
TYP0
00X0XXXXB
R/W
15
-
14
-
13
ASZ1
12
ASZ0
11
-
10
DBW0
9
-
8
-
01XX0X00B
R/W
7
6
5
4
3
2
1
0
-
-
WREN
-
TYP3
TYP2
TYP1
TYP0
00X0XXXXB
R/W
ACR0 to ACR3 (Area Configuration Registers 0 to 3) set the functions of each chip select area.
[bit15, bit14] (Reserved bits)
Set these bits to "00B".
266
CHAPTER 16 EXTERNAL BUS INTERFACE
[bit13, bit12] ASZ1, ASZ0 = Area Size bit [1:0]
The size of each chip select area is set as follows.
Register
ASR0/
ASR1
ASR2/
ASR3
ASZ1
ASZ0
Size of each chip select area
0
0
64 Kbytes (00010000H byte, ASR A[23:16] bit designation is enabled)
0
1
128 Kbytes (00020000H byte, ASR A[23:17] bit designation is enabled)
1
0
256 Kbytes (00040000H byte, ASR A[23:18] bit designation is enabled)
1
1
512 Kbytes (00080000H byte, ASR A[23:19] bit designation is enabled)
0
0
1 Mbyte
0
1
2 Mbytes (00200000H byte, ASR A[23:21] bit designation is enabled)
1
0
4 Mbytes (00400000H byte, ASR A[23:22] bit designation is enabled)
1
1
8 Mbytes (00800000H byte, ASR A[23] bit designation only is enabled)
Setting
CS0X, CS1X only
enabled
(00100000H byte, ASR A[23:20] bit designation is enabled)
CS2X, CS3X only
enabled
In ASZ1, ASZ0, the size of each area is set by changing the bit number of the address comparison with
ASR. That is why ASR has some bits that are not compared.
The ASZ1, ASZ0 bits of ACR0 are initialized by RST to "11B", however regardless of this setting, the
CS0 area immediately after RST is specially set from "00000000H" to "00FFFFFFH" (the entire area).
From after the initial write into ACR0, all area configuration are canceled and the size is set according
to the table above.
Note:
Even when a large area size is designated in this product, the image is 64 Kbytes.
[bit11] (Reserved bit)
Set this bit to "0".
[bit10] DBW0 = Data Bus Width [0]
The data bus width of each chip select area is set as follows.
DBW0
Data bus width
0
8 bits
1
16 bits
(Byte access)
(half word access)
The same value as the value of the mode vector WTH bit is automatically written into the DBW0 bit of
ACR0 during the reset sequence.
[bit9, bit8] (Reserved bits)
Set these bits to "00B".
[bit7] (Reserved bit)
Set this bit to "0".
267
CHAPTER 16 EXTERNAL BUS INTERFACE
[bit6] (Reserved bit)
Set this bit to "0".
[bit5] WREN = WRite ENable
This sets the write enable/disable for each chip select area.
WREN
Write enable/disable
0
Write disabled
1
Write enabled
Even if the internal bus generates a write access for an area for which write is disabled, that access is
ignored and no external access is performed.
Set the WREN bit to "1" for areas, such as data areas, where write is necessary.
[bit4] (Reserved bit)
Set this bit to "0".
[bit3 to bit0] TYP3, TYP2, TYP1, TYP0 = TYPe select
The access type of each chip select area is set as follows.
TYP3
TYP2
TYP1
TYP0
Access type
0
X
X
Normal access (asynchronous SRAM, I/O, single ROM/Flash)
1
X
X
Setting is prohibited
X
0
Wait insert from RDY pins disabled
X
1
Wait insert from RDY pins enabled
0
X
WR0X, WR1X pins used as write strobes
1
X
Setting is prohibited
0
Setting is prohibited
1
Setting is prohibited
0
X
0
1
0
0
1
0
Setting is prohibited
0
1
1
Setting is prohibited
1
0
0
Setting is prohibited
1
0
1
Setting is prohibited
1
1
0
Setting is prohibited
1
1
1
Masked area configuration (the access type becomes that of coincident
areas)*
Each bit is set in combination.
*:
CS area masked functions
If you want to define an area for which operational configuration have been partially changed
within a specific CS area (hereafter called base set area), the other CS areas can be made to
268
CHAPTER 16 EXTERNAL BUS INTERFACE
function as masked areas by setting them as ACR: TYP[3:0]=1111B.
When masked functions are not used, overlapping area configuration in multiple CS areas are
disabled.
Access to masked areas performs the following operations.
- CSX is not asserted for masked areas.
- CSX is asserted for base set areas.
- The following ACR configuration are enabled on the masked area side.
bit10: DBW0: bus width setting
bit5: WREN: write enable setting
Note : This is the only setting that inhibits different configuration from the base set areas.
- The following ACR configuration on the base set area side are enabled.
bit[3:0] TYP[3:0]: access type setting
- The AWR configuration on the masked area side are enabled.
Masked areas can only be set within some areas inside other CS areas (base set areas). It is not
permitted to create masked areas in areas that do not have base set areas. Furthermore, multiple
overlaps of masked areas are not permitted. Please be very careful when setting the ASR and
ACR: ASZ1, ASZ0 bit.
Note:
Write enable configuration may not be implemented by a mask.
Make the write enable configuration the same configuration in base CS areas and masked areas.
If write disable is set in a masked area, that area is not masked and operates as a base CS area.
When write enable is set in the masked area after setting write disable in the base CS area, it
becomes an area with no base configuration and malfunctions.
269
CHAPTER 16 EXTERNAL BUS INTERFACE
■ AWR0 to AWR3 (Area Wait Register)
Figure 16.2-3 shows the bit configuration of AWR0 to AWR3.
Figure 16.2-3 Bit Configuration of AWR0 to AWR3 (Area Wait Register)
AWR0H
Address:
0000 0660H
bit 15
-
14
W14
13
W13
12
W12
11
-
10
-
9
-
8
-
bit 7
6
5
4
3
2
1
0
W06
-
W04
-
W02
W01
W00
14
13
12
11
10
9
8
W14
W13
W12
-
-
-
-
6
5
4
3
2
1
0
W06
-
W04
-
W02
W01
W00
14
13
12
11
10
9
8
W14
W13
W12
-
-
-
-
6
5
4
3
2
1
0
W06
-
W04
-
W02
W01
W00
14
13
12
11
10
9
8
W14
W13
W12
-
-
-
-
6
5
4
3
2
1
0
W06
-
W04
-
W02
W01
W00
Initial value
01110000B
Access
R/W
01011011B
R/W
XXXX0000B
R/W
XX0X1XXXB
R/W
0XXX0000B
R/W
XX0X1XXXB
R/W
0XXX0000B
R/W
0X0X1XXXB
R/W
AWR0L
Address:
0000 0661H
-
AWR1H
Address:
0000 0662H
bit 15
-
AWR1L
Address:
0000 0663H
bit 7
-
AWR2H
Address:
0000 0664H
bit 15
-
AWR2L
Address:
0000 0665H
bit 7
-
AWR3H
Address:
0000 0666H
bit 15
-
AWR3L
Address:
0000 0667H
bit 7
-
AWR0 to AWR3 designate each kind of wait timing for each chip select area.
The actions of each bit are changed by the configuration of the access type (TYP[3:0] bit) of the ACR0 to
ACR3 registers.
[bit15] (Reserved bit)
Set this bit to "0".
[bit14 to bit12] W14 to W12 = First Access Wait Cycle
They set the auto wait cycle number inserted into the first access cycle of each cycle.
270
CHAPTER 16 EXTERNAL BUS INTERFACE
The initial value is set at 7 waits for the CS0 area. The initial value is indeterminate for the other areas.
W14
W13
W12
0
0
0
Automatic wait cycle 0
0
0
1
Automatic wait cycle 1
...
First access wait cycle
...
1
1
0
Automatic wait cycle 6
1
1
1
Automatic wait cycle 7
[bit11 to bit7] (Reserved bits)
Set these bits to "00000B".
[bit6] W06 = Read → Write Idle Cycle
The read → write idle cycle is set to avoid collisions in the data bus between read data and write data
when the write cycle continues on after the read cycle. During the idle cycle, all chip select signals are
negated and the data pins retain a state of high impedance.
The designated idle cycle is inserted when write continues on after read, or when an access to another
chip select area is generated after read.
Read → Write Idle Cycle
W06
0
0 cycle
1
1 cycle
[bit5] (Reserved bit)
Set this bit to "0".
[bit4] W04 = Write Recovery Cycle
The write recovery cycle is set to control access to a device with space limitations when access
continues on after write access. During the write recovery cycle, all chip select signals are negated and
the data pins retain a state of high impedance.
The write recovery cycle will always be inserted after write access if the write recovery cycle is set at
"1" or higher.
W04
Write recovery cycle
0
0 cycle
1
1 cycle
[bit3] (Reserved bit)
Set this bit to "1".
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CHAPTER 16 EXTERNAL BUS INTERFACE
[bit2] W02 = Address → CSX Delay
Address → CSX delay is set when the address for CSX falling needs a prescribed setup, or when the
CSX edge is also needed to consecutively access the same chip select area.
The CS0X to CS3X output delay is set by the address and ASX output.
Address → CSX delay
W02
0
No delay
1
Delay
When "0" is set and "no delay" is selected, CS0X to CS3X start their assert at the same timing as the
ASX assert. At this time, if successive access is implemented to the same chip select area, in some cases
CS0X to CS3X continue with their asserts between both accesses too and do not change.
When "1" is set and "delay" is selected, the CS0X to CS3X asserts are started from the rising of the
external memory clock SYSCLK output. At this time, even if successive access is implemented to the
same chip select area, CS0X to CS3X negate timing is generated between both accesses.
If CSX delay is selected, 1 setup cycle is inserted before the assert of the read/write strobe from the
delayed CSX assert (This is the same operation as the CSX → RDX/WRX setup setting of W01).
[bit1] W01 = CSX → RDX/WRX setup
CSX → RDX/WRX setup extension cycle is set to extend the period after the CSX assert up until the
assert for the read/write strobe. After the CSX assert, a setup extension cycle with a minimum of 1 cycle
is inserted before the read/write strobe assert.
CSX → RDX/WRX setup extension cycle
W01
0
0 cycle
1
1 cycle
If "0" is set and 0 cycle selected, RDX/WR0X, WR1X are output at top speed after the rising of the
external memory clock SYSCLK output immediately after the CSX assert. In some cases, WR0X,
WR1X may be delayed for 1 cycle or more by the internal bus status.
When "1" is set and 1 cycle selected, the output of both RDX/WR0X, WR1X are always delayed by 1
cycle or more.
This setup extension cycle cannot be inserted when CSX is left un-negated and successive accesses are
performed in the same chip select area. When the address definition setup extension cycle is required,
by enabling the W02 bit and inserting the address → CSX delay, the CSX is temporarily negated at the
time of each access and this setup extension cycle is enabled.
When the W02 CSX delay is inserted, this setup cycle is always enabled, regardless of the W01 bit
setting.
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CHAPTER 16 EXTERNAL BUS INTERFACE
[bit0] W00 = RDX/WRX → CSX hold cycle
The RDX/WRX → CSX hold extension cycle is set when extending the period after the read/write
strobe negate until the CSX negate. After the read/write strobe negate, 1 cycle of the hold extension
cycle is inserted before the CSX negate.
RDX/WRX → CSX hold cycle
W00
0
0 cycle
1
1 cycle
When "0" is set and 0 cycle selected, CS0X to CS3X are negated after the expiration of the hold from
the external memory clock SYSCLK output rising edge after the negation of RDX/WR0X, WR1X.
When "1" is set and 1 cycle selected, CS0X to CS3X are negated after a delay of 1 cycle.
This hold extension cycle cannot be inserted when CSX is left un-negated and successive accesses are
performed in the same chip select area. When the address definition hold extension cycle is required, by
enabling the W02 bit and inserting the address → CSX delay, the CSX is temporarily negated at the
time of each access and this hold extension cycle is enabled.
● Normal Access and Address/Data Multiplex Access
Chip select areas that have been set as follows by the access type (TYP[3:0] bit) of the ACR0 to ACR3
registers become areas that perform normal access or address/data multiplex access.
TYP3
TYP2
TYP1
TYP0
Access type
0
0
x
x
Normal access (asynchronous SRAM, I/O, single ROM/Flash)
0
1
x
x
Address data multiplex access (limited to 8/16-bit bus width) (Disabled)
The functions of each bit of AWR0 to AWR3 with regard to normal access or address/data multiplex access
areas are as follows. Apart from AWR0, the initial value is indeterminate, so please set before enabling each
area via the CSER register.
Note:
Address/data multiplex access operational configuration are not possible for the MB91245/S series.
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CHAPTER 16 EXTERNAL BUS INTERFACE
■ CSER (Chip Select Enable Register)
Address:
0000 0680H
bit 31
----
30
----
29
----
28
----
27
CSE3
26
CSE2
25
CSE1
24
CSE0
Initial value
00000001B
Access
R/W
Enable/disable is set for each chip select area.
[bit31 to bit28] (Reserved bits)
Set these bits to "0000B".
[bit27 to bit24] CSE3, CSE0 = Chip select enable 0 to 3
These enable each chip select area of CS0X to CS3X.
The initial value is enabled for the CS0 area only by "0001B".
By writing in "1", operations are performed according to the ASR0 to ASR3, ACR0 to ACR3, AWR0 to
AWR3 configuration.
All the configuration for the corresponding chip select area must be performed before enabling.
CSE3 to CSE0
Area control
0
Disabled
1
Enabled
CSE bit
Corresponding CSX
bit24: CSE0
CS0X
bit25: CSE1
CS1X
bit26: CSE2
CS2X
bit27: CSE3
CS3X
● Chip Select Area
A total of 4 chip select areas can be set in the external bus interface.
The address space of each area consists of 16 Mbytes in ASR0 to ASR3 (area select register) and ACR0
to ACR3 (area configuration register), in which CS0X, CS1X may be set in units of 64K/128K/256K/
512 Kbytes in the allotted space in the external bus area up to "00000000H" to "003FFFFFH", and
CS2X, CS3X may be set in units of 1M/2M/4M/8Mbyte in the "00400000H" to "00FFFFFFH" space.
When there is bus access in an area designated by these registers, the corresponding chip select signal
CS0X to CS3X during the access cycle becomes active ("L" output).
274
CHAPTER 16 EXTERNAL BUS INTERFACE
Example of ASR and ASZ[1:0] configuration
• ASR1=0010H ACR -> ASZ[1:0]=00B
Chip select area 1 is allotted from "00100000H" to
"0010FFFFH".
• ASR2=0040H ACR2 -> ASZ[1:0]=00B
Chip select area 2 is allotted from "00400000H" to
"004FFFFFH".
• ASR3=0081H ACR3 -> ASZ[1:0]=11B
Chip select area 3 is allotted from "00800000H" to
"00FFFFFFH".
At this time, the ACR -> ASZ[1:0] setting is 8Mbytes, and the boundary is in units of 8 Mbytes and
ASR3[22:16] is ignored.
Before writing to ACR0 after reset, "00000000H" to "00FFFFFFH" is allotted to chip select area 0.
Note:
Please set so that there is no mutual overlapping between chip select areas.
Figure 16.2-4 Regarding Boundaries Depending on Area Size
(Initial value)
(Example)
00000000H
00000000H
00100000H
Area 1
64 Kbytes
Area 2
1 Mbyte
Area 0
00400000H
Area 3
00800000H
8 Mbytes
00FFFFFFH
00FFFFFFH
275
CHAPTER 16 EXTERNAL BUS INTERFACE
16.3
Endian and Bus Access of External Bus Interface
This section describes the endian and bus access.
■ Endian Overview
The FR family can switch between the big and little endian methods when using each chip select area,
except specific areas.
■ The Relationship between Data Bus Width and Control Signals
The WRX[1:0] control signal always has a 1 to 1 correspondence with the data bus byte position,
regardless of data bus width.
The data bus byte position used for the selected data bus width and the corresponding control signals
are shown below for each bus mode.
• Normal Bus Interface
a) 16-bit bus width
data bus
D15
b) 8-bit bus width
data bus
Control signal
Control signal
WR0X
WR1X
D00
WR0X
-
-
-
-
-
-
-
-
-
-
• Time Division Input/Output Interface
a) 16-bit bus width
data bus
b) 8-bit bus width
Output address Control signal
data bus
Output address Control signal
D15
A15 to A08
WR0X
A07 to A00
WR1X
D00
276
A07 to A00
WR0X
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CHAPTER 16 EXTERNAL BUS INTERFACE
■ Bus Access
This product performs big-endian external bus access.
● Data Bus Width
• 16-bit bus width
Internal register
External bus
Output address low order
"00B"
D31
D23
D15
D07
AA
Read/write
BB
"10B"
AA
CC
BB
DD
D15
D07
CC
DD
• 8-bit bus width
Internal register
External bus
Output address low order
D31
D23
D15
D07
Read/write
AA
"00B"
"01B"
"10B"
"11B"
AA
BB
CC
DD
D07
BB
CC
DD
● External Bus Access
External bus access (16/8 bits in bus width) is described below as word/halfword/byte access. The
following items are also covered.
• Access byte position
• Program address and output address
• Number of times of bus access
PA1/PA0
:
Lower 2 bits of the address specified in the program
Output A1/A0
:
Lower 2 bits of the address that is output
:
First byte position of the address that is output
:
Byte position of the data that is accessed
:
Number of times of bus access
+
(1)-(4)
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CHAPTER 16 EXTERNAL BUS INTERFACE
The FR family does not detect misalign errors.
Accordingly, in the case of word access, even if the address lower 2 bits designated by the program are
"00B", "01B", "10B", "11B", all the lower 2 bits of the addresses output become "00B". In the case of
half word access, they become "00B" when "00B", "01B", and become "10B" when "00B", "01B".
• 16-bit bus width
(A) word access
(a) PA1/PA0=00B
(b) PA1/PA0=01B
→[1]Output A1/A0=00B
→[1]Output A1/A0=00B
[2]Output A1/A0=10B
[2]Output A1/A0=10B
MSB
(c) PA1/PA0=10B
→[1]Output A1/A0=00B
[2]Output A1/A0=10B
(d) PA1/PA0=11B
→[1]Output A1/A0=00B
[2]Output A1/A0=10B
LSB
[1]
00
01
[1]
00
01
[1]
00
01
[1]
00
01
[2]
10
11
[2]
10
11
[2]
10
11
[2]
10
11
16bits
(B) half word access
(a) PA1/PA0=00B
(b) PA1/PA0=01B
→[1]Output A1/A0=00B
[1]
00
01
10
11
→[1]Output A1/A0=00B
[1]
00
01
10
11
(c) PA1/PA0=10B
→[1]Output A1/A0=10B
[1]
00
01
10
11
(d) PA1/PA0=11B
→[1]Output A1/A0=10B
[1]
00
01
10
11
(C) byte access
(a) PA1/PA0=00B
(b) PA1/PA0=01B
→[1]Output A1/A0=00B
[1]
278
00
01
10
11
→[1]Output A1/A0=01B
[1]
00
01
10
11
(c) PA1/PA0=10B
→[1]Output A1/A0=10B
[1]
00
01
10
11
(d) PA1/PA0=11B
→[1]Output A1/A0=11B
[1]
00
01
10
11
CHAPTER 16 EXTERNAL BUS INTERFACE
• 8-bit bus width
(A) word access
(a) PA1/PA0=00B
(b) PA1/PA0=01B
→[1]Output A1/A0=00B
→[1]Output A1/A0=00B
[2]Output A1/A0=01B
[2]Output A1/A0=01B
[3]Output A1/A0=10B
[3]Output A1/A0=10B
[4]Output A1/A0=11B
[4]Output A1/A0=11B
MSB
(c) PA1/PA0=10B
→[1]Output A1/A0=00B
[2]Output A1/A0=01B
[3]Output A1/A0=10B
[4]Output A1/A0=11B
(d) PA1/PA0=11B
→[1]Output A1/A0=00B
[2]Output A1/A0=01B
[3]Output A1/A0=10B
[4]Output A1/A0=11B
LSB
[1]
00
[1]
00
[1]
00
[1]
00
[2]
01
[2]
01
[2]
01
[2]
01
[3]
10
[3]
10
[3]
10
[3]
10
[4]
11
[4]
11
[4]
11
[4]
11
8bits
(B) half word access
(a) PA1/PA0=00B
(b) PA1/PA0=01B
→[1]Output A1/A0=00B
→[1]Output A1/A0=00B
[2]Output A1/A0=01B
[2]Output A1/A0=01B
(c) PA1/PA0=10B
→[1]Output A1/A0=10B
[2]Output A1/A0=11B
(d) PA1/PA0=11B
→[1]Output A1/A0=10B
[2]Output A1/A0=11B
[1]
00
[1]
00
00
00
[2]
01
[2]
01
01
01
10
10
[1]
10
[1]
10
11
11
[2]
11
[2]
11
(C) byte access
(a) PA1/PA0=00B
[1]
(d) PA1/PA0=11B
→[1]Output A1/A0=11B
00
00
00
01
01
01
10
10
→[1]Output A1/A0=01B
00
01
(c) PA1/PA0=10B
→[1]Output A1/A0=10B
(b) PA1/PA0=01B
→[1]Output A1/A0=00B
[1]
10
10
11
11
[1]
11
[1]
11
279
CHAPTER 16 EXTERNAL BUS INTERFACE
● Example of Connection with the Outside
Figure 16.3-1 shows the example of connection between MB91245/S series and the outside.
Figure 16.3-1 Example of Connection with the Outside
MB91245/S series
D15
to
D08
D07
to
D00
WR0X
WR1X
*: The MSB side data bus of MB91245/S
series is used in the case of the 8-bit
device.
0
1
D15 D08 D07 D00
16-bit device*
("0"/"1" Address lower 1bit)
■ External Access
(a) word (32 bits) access
Big-endian mode
Internal register External pin
Address:
D31
"2"
D15
AA
16-bit
bus width
"0"
Control pin
BB
AA CC
WR0X
BB DD
WR1X
D00
CC
-
-
-
DD
-
-
-
[1]
[2]
D00
Internal register External pin
Address:
"0"
"1"
"2"
"3"
D15
D31
AA
AA BB CC DD
WR0X
D08
8-bit
bus width
BB
-
-
-
-
-
CC
-
-
-
-
-
DD
-
-
-
-
-
[1]
[2]
[3]
[4]
D00
280
Control pin
0
D07 D00
8-bit device*
CHAPTER 16 EXTERNAL BUS INTERFACE
(b) half word (16 bits) access
Big-endian mode
Internal register External pin
Control pin
Address: "0"
D31
D15
AA
WR0X
BB
WR1X
D00
AA
-
-
BB
-
-
D00
16-bit
bus width
[1]
Internal register External pin
Control pin
Address: "2"
D31
D15
CC
WR0X
DD
WR1X
D00
CC
-
-
DD
-
-
D00
[1]
Internal register External pin
Address:
D31
"0"
Control pin
"1"
D15
AA BB
WR0X
D08
-
-
-
AA
-
-
-
BB
-
-
-
[1]
[2]
D00
8-bit
bus width
Internal register External pin
Address:
D31
Control pin
"2" "3"
D15
CC DD
WR0X
D08
-
-
-
CC
-
-
-
DD
-
-
-
[1]
[2]
D00
281
CHAPTER 16 EXTERNAL BUS INTERFACE
(c) byte (8-bits) access
Big-endian mode
Internal register External pin
Control pin
Address: "0"
D31
D15
AA
WR0X
D00
-
AA
D00
[1]
Internal register External pin
Control pin
Address: "1"
D31
D15
BB
WR1X
D00
-
BB
D00
16-bit
bus width
[1]
Internal register External pin
Control pin
Address: "2"
D31
D15
CC
WR0X
D00
CC
-
D00
[1]
Internal register External pin
Control pin
Address: "3"
D31
D15
DD
WR1X
D00
DD
-
D00
[1]
282
CHAPTER 16 EXTERNAL BUS INTERFACE
Big-endian mode
Internal register External pin
Address:
D31
Control pin
"0"
D15
AA
WR0X
D08
-
AA
D00
[1]
Internal register External pin
Address:
D31
Control pin
"1"
D15
BB
WR0X
D08
-
BB
D00
8-bit
bus width
[1]
Internal register External pin
Address:
D31
Control pin
"2"
D15
CC
WR0X
D08
CC
-
D00
[1]
Internal register External pin
Address:
D31
Control pin
"3"
D15
DD
WR0X
D08
DD
-
D00
[1]
283
CHAPTER 16 EXTERNAL BUS INTERFACE
16.4
Normal Bus Interface of External Bus Interface
In the normal bus interface, two-clock cycle is the basic bus cycle for both read
accesses and write accesses.
■ Normal Bus Interface
This section provides a timing chart to describe the following operations via the normal bus interface:
• Basic timing (for continuous access)
• WRnX + byte control type
• Read -> write timing
• Write -> read timing
• Automatic wait timing
• External wait timing
• CSnX delay setting
• CSnX -> RDX/WRX setup, RD/WRnX -> CSnX hold setting
■ Basic Timing (When there is Consecutive Access) (TYP[3:0] = 0000B, AWR = 0008H)
Figure 16.4-1 Basic Timing (When there is Consecutive Access) (TYP[3:0] = 0000B, AWR = 0008H)
SYSCLK
A[15:0]
#2
#1
ASX
CSnX
RDX
READ
D[15:0]
#2
#1
WRnX
WRITE
D[15:0]
#1
#2
• ASX performs a single cycle assert on the bus access start cycle.
• A[15:0] outputs the address of the first byte position in the word/half word/byte access from the bus
access start cycle to the bus access end cycle.
• When the W02 bit of the AWR0 to AWR3 registers is "0", CS0X to CS3X assert at the same timing as
ASX, and CS0X to CS3X do not negate when there is consecutive access. When the W00 bit of the
284
CHAPTER 16 EXTERNAL BUS INTERFACE
AWR register is "0", it negates CS0X to CS3X after the end of the bus cycle; when the W00 bit is "1", it
negates after 1 cycle after the end of bus access.
• RDX, WR0X, WR1X assert from the second bus access cycle. It negates after inserting the wait cycle
for the W14 to W12 bits of the AWR register. The timing of the RDX, WR0X, WR1X assert can be
delayed by one cycle by setting the W01 bit of the AWR register to "1". However, in some cases it may
also be delayed from the second cycle when WR0X, WR1X set the W01 bit to "0" depending on their
internal status.
• In the case of read access, D[15:0] is captured by the rising of the SYSCLK of the cycle that terminated
the wait cycle after the RDX assert.
• In the case of write access, data is output to D[15:0] by the timing at which WR0X, WR1X were
asserted.
■ Read → Write Timing (TYP[3:0]=0000B, AWR=0048H)
Figure 16.4-2 Read → Write Timing (TYP[3:0]=0000B, AWR=0048H)
Read
Idle
Write
SYSCLK
A[23:0]
ASX
CSnX
RDX
WRnX
D[31:16]
• It is possible to insert an idle cycle of up to 0 to 1 cycle via the setting of the W06 bit of the AWR
register.
• The read side of the CS area setting is enabled.
• This idle cycle is inserted when the next access after a read access is a write access, or when there is an
access to another area.
285
CHAPTER 16 EXTERNAL BUS INTERFACE
■ Write → Write Timing (TYP[3:0]=0000B, AWR=0018H)
Figure 16.4-3 Write → Write Timing (TYP[3:0]=0000B, AWR=0018H)
Write
Write recovery
Write
SYSCLK
A[23:0]
ASX
CSnX
WRnX
D[31:16]
• It is possible to insert a write recovery cycle of up to 0 to 1 cycle via the setting of the W04 bit of the
AWR register.
• The recovery cycle is generated after all the write cycles.
• The write recovery cycle is also generated when write access is split due to access exceeding the set bus
width.
286
CHAPTER 16 EXTERNAL BUS INTERFACE
■ Automatic Wait Timing (TYP[3:0]=0000B, AWR=2008H)
Figure 16.4-4 Automatic Wait Timing (TYP[3:0]=0000B, AWR=2008H)
Basic cycle
Wait cycle
SYSCLK
A[23:0]
ASX
CSnX
RDX
READ
D[31:16]
WRnX
WRITE
D[31:16]
• The automatic wait cycle can be set to 0 to 7 via the setting of the W14 to W12 bits of the AWR register
(first wait cycle).
• In the above diagram, 2 cycles of the automatic wait cycle have been inserted for access of a total of 4
cycles. When the automatic wait is set, the bus cycle becomes a minimum of 2 cycles + (first wait
cycle). In the case of write, it may become even longer depending on the internal status.
287
CHAPTER 16 EXTERNAL BUS INTERFACE
■ External Wait Timing (TYP[3:0]=0001B, AWR=2008H)
Figure 16.4-5 External Wait Timing (TYP[3:0]=0001B, AWR=2008H)
Basic cycle
Automatic wait
2 cycles
Wait cycle
by RDY
SYSCLK
A[23:0]
ASX
CSnX
RDX
READ
D[31:16]
WRnX
WRITE
D[31:16]
RDY
Cancel
Wait
The external wait cycle can be inserted by setting the TYP0 bit of the ACR register to "1" and enabling
the external RDY input pins.
In the above diagram, the enabling of the wait by the automatic wait cycle disables the forward slash
portion of the RDY pins. The value of the RDY input pins is judged after the final cycle of the
automatic wait cycle. Furthermore, once the wait cycle has finished, the value of the RDY input pins is
disabled until the activation of the next access cycle.
288
CHAPTER 16 EXTERNAL BUS INTERFACE
■ CSX Delay Setting (TYP[3:0]=0000B, AWR=000CH)
Figure 16.4-6 CSX Delay Setting (TYP[3:0]=0000B, AWR=000CH)
Access Cycle
Access Cycle
SYSCLK
A[23:0]
ASX
CSnX
RDX
READ
D[31:16]
WRnX
WRITE
D[31:16]
When the W02 bit is "1", it asserts from the next cycle after the ASX assert and inserts a negate period
when there are consecutive accesses.
289
CHAPTER 16 EXTERNAL BUS INTERFACE
■ CSX → RDX/WRX Setup, RDX/WRnX → CSX Hold Setting (TYP[3:0]=0000B,
AWR=000BH)
Figure 16.4-7 CSX → RDX/WRX Setup, RDX/WRnX → CSX Hold Setting (TYP[3:0]=0000B, AWR=000BH)
Access Cycle
SYSCLK
A[23:0]
ASX
CSnX
CSX->RDX/WRX
Delay
RDX/WRX->CSX
Delay
RDX
READ
D[31:16]
WRnX
WRITE
D[31:16]
• By setting the W01 bit of the AWR register to "1", it is possible to set the CSX → RDX/WRnX setup
delay. It is set to extend the period after the chip select assert up until the read/write strobe.
• By setting the W00 bit of the AWR register to "1", it is possible to set the RDX/WRnX → CSX hold
delay. It is set to extend the period after the read/write strobe negate up until the chip select negate.
• The CSX → RDX/WRnX setup delay (W01 bit) and the RDX/WRnX → CSX hold delay (W00 bit)
can be set independently.
• Neither the CSX → RDX/WRnX setup nor the RDX/WRnX → CSX hold delay can be inserted when
the chip select is left un-negated and there are consecutive accesses within the same chip select area.
• When the setup cycle from address definition and the address definition hold cycle are required, please
set the address-to-CSX delay setting (W02 bit of AWR register) to "1".
290
CHAPTER 16 EXTERNAL BUS INTERFACE
16.5
Register Setting Procedure of External Bus Interface
This section describes the register setting procedure of the external bus interface.
■ Register Setting Procedure
Please follow the general rules below regarding the setting procedures for the external bus interface.
• When rewriting the register content, you must perform the setting so that the area corresponding to the
CSER register is not used ("0").
If the setting is changed while it is stays "1", access before and after the change cannot be guaranteed.
• Please follow the procedures below when changing a register.
(1) Set the CSER bit that deals with the relevant area to "0".
(2) Set ASR and ACR at the same time with word access. To access ASR and ACR with half word, set
ASR before ACR.
(3) Set AWR.
(4) Set the CSER bit for the relevant area.
• The CS0X area is enabled from after reset cancellation; when it is being used as a program area, it is
necessary to rewrite CSER while it is "1". In this case, please perform the above configuration 2 and 3
with the internal clock in low initial state. After that, change the clock to the high-speed clock.
291
CHAPTER 16 EXTERNAL BUS INTERFACE
16.6
Notes on Using External Bus Interface
This section describes the warnings on use of the external bus interface.
■ Notes on Using
The following configuration must be performed for all the areas being used when the area that uses
WR0X, WR1X as the write strobe (TYP[3:0]=0X0XB) and the area that uses WRX as the write strobe
(TYP[3:0]=0X1XB) are to be mixed.
•
Set the read → write idle cycle to a minimum of 1 cycle or more (AWR W06=1).
•
Set the write recovery cycle to a minimum of 1 cycle or more (AWR W04=1).
However, when WR0X, WR1X are disabled (ROM only connection) in the area using WR0X, WR1X as
the write strobe (TYP[3:0]=0X0XB), the above limitations do not exist. In addition, the above limitations
do not exist when both the address → RDX/WRX setup cycle (W01=1) and the RDX/WRX → address
hold cycle (W00=1) are set in the area using WRX as the write strobe (TYP[3:0]=0X1XB).
<Reasons for the restrictions>
The WR0X/WR1X pins become byte enable (UBX/LBX) output in areas that use the WRX set with
TYPE[3:0]=0X1XB as the write strobe. In such a case, enable signals for each byte position are output
by the byte enable output at the same timing as the address and CSX output.
As a result, when there is access before or after that to areas using the WR0X/WR1X pins as the
asynchronous write strobe, the AC standards between CSX and WR0X/WR1X for these areas cannot be
satisfied, and there is the possibility that write error will be generated.
When the read → write idle cycle and write recovery cycle are set, the above AC can be satisfied as in
these cycles CSX is not asserted ("H" level is retained).
These limitations are not required when there is room for the AC standards (setup and hold) between
CSX and WR0X/WR1X in areas using the WR0X/WR1X pins as the asynchronous write strobe.
292
CHAPTER 17
DMAC
(DMA CONTROLLER)
This chapter explains the overview of the DMAC, the
configuration and functions of registers, and DMAC
operation.
17.1 Overview of DMAC
17.2 Detailed Explanation of the Register of DMAC
17.3 Description of DMAC Operation
17.4 Operation Flow of DMAC
17.5 Data Path of DMAC
293
CHAPTER 17 DMAC (DMA CONTROLLER)
17.1
Overview of DMAC
This is the module to enable DMA (Direct Memory Access) transfer with FR family
device.
The DMA transfer under the control of this module allows you to perform various
transfers of data at high speed without going through the CPU, increasing system
performance.
■ Hardware Configurations
This module consists mainly of the following.
• Independent DMA channel × 5 channels.
• 5 channels Independent access control circuit
• 20-bit Address register (Specifying reload possible: ch.0 to ch.3)
• 24-bit Address register (Specifying reload possible: ch.4)
• 16-bit Transfer count register (Specifying reload possible: 1 for each channel)
• 4-bit block count register (1 for each channel)
• Two-cycle transfer
■ Major Function
The data transfer by this module mainly has the functions as follows.
Enables independent data transfer of multiple channels (5 channels)
• Priority (ch.0 → ch.1 → ch.2 → ch.3 → ch.4)
• Allows the reverse of order between ch.0 and ch.1.
• DMAC Start factor
- Built-in peripheral request (sharing interrupt requests --- including external interrupt)
- Software requests (Write into register)
• Transfer mode
- Burst transfer/Step transfer/Block transfer
- Addressing mode : 20bit (24bit) address assignment (increase/decrease/fix)
(Address increase and decrease range ±1, 2, 4 fix)
- Type of data : byte/half word/word length
- Single-shot/Reload selectable
294
CHAPTER 17 DMAC (DMA CONTROLLER)
■ Register Overview of DMAC
Figure 17.1-1 Register Overview of DMAC
ch.0 control/status register A
DMACA0
(bit)
00000200H
ch.0 control/status register B
DMACB0
00000204H
ch.1 control/status register A
DMACA1
00000208H
ch.1 control/status register B
DMACB1
0000020CH
ch.2 control/status register A
DMACA2
00000210H
ch.2 control/status register B
DMACB2
00000214H
ch.3 control/status register A
DMACA3
00000218H
ch.3 control/status register B
DMACB3
0000021CH
ch.4 control/status register A
DMACA4
00000220H
ch.4 control/status register B
DMACB4
00000224H
Total control register
DMACR
00000240H
ch.0 Transfer-source address register
DMASA0
(bit)
00001000H
ch.0 Transfer-destination address register
DMADA0
00001004H
ch.1 Transfer-source address register
DMASA1
00001008H
ch.1 Transfer-destination address register
DMADA1
0000100CH
ch.2 Transfer-source address register
DMASA2
00001010H
ch.2 Transfer-destination address register
DMADA2
00001014H
ch.3 Transfer-source address register
DMASA3
00001018H
ch.3 Transfer-destination address register
DMADA3
0000101CH
ch.4 Transfer-source address register
DMASA4
(bit)
00001020H
ch.4 Transfer-destination address register
DMADA4
00001024H
31
24
31
31
24
23
16
20
19
23
15
8
7
0
0
0
295
CHAPTER 17 DMAC (DMA CONTROLLER)
■ Block Diagram of DMAC
Figure 17.1-2 Block Diagram of DMAC
Counter
DMA transfer request
to bus controller
DMA start
select factor circuit
&
request acceptance
control
Selector
Write back
Buffer
Peripheral start request/stop input
DTC two-stage register DTCR
Counter
DSS[2:0]
Buffer
Priority circuit
To interrupt controller
Read/Write control
Peripheral interrupt clearing
BLK register
Selector
Counter buffer
DMASA two-stage register SADM,SASZ[7:0] SADR
Selector
Write back
Counter buffer
Address counter
DMA control
Access
Address
Write back
296
TYPE.
MOD,WS
DMADA two-stage register DADM,DASZ[7:0] DADR
X-bus
Bus control block
State transition
circuit
To bus
controller
IRQ[4:0]
ERIR,EDIR
Selector
Bus control block
Read
Write
MCLREQ
CHAPTER 17 DMAC (DMA CONTROLLER)
17.2
Detailed Explanation of the Register of DMAC
This section describes the warning on register setting and detailed of registers used by
the DMAC.
■ Warning on Register Setting
In setting this DMAC, some bits must be set while DMA is stopped. If they are set during the operation
(during transfer), normal operation will not be guaranteed.
The * mark means the bits that affect the operation if they are set during DMAC transfer. Rewrite this
bit while DMAC transfer is stopped (start disabled or in pause).
If they are set while DMA transfer is disabled (when DMACR: DMAE=0 or DMACA: DENB=0), the
setting will become valid after enabling the start.
If they are set while DMA transfer is in pause (when DMACR: DMAH[3:0] not equal 0000B or
DMACA: PAUS=1), the setting will become valid after canceling the pause.
■ DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Control/Status Register A [DMACA0 to DMACA4]
This is the register to perform the operational control of each DMAC channel and exists independently
for each channel.
Each bit function is described as follows.
bit 31
30
29
Address:
ch.0 000200H
DENB PAUS STRG
ch.1 000208H
ch.2 000210H
ch.3 000218H
ch.4 000220H
Read/write
27
26
25
IS[4:0]
24
23
22
21
Reserved
20
19
18
17
16
BLK[3:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
bit
Read/write
28
15
14
13
11
11
10
9
8
7
6
5
4
3
2
1
0
DTC[15:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
(Initial value: 00000000 0000XXXX XXXXXXXX XXXXXXXXB)
[bit31] DENB (Dma ENaBle): DMA Operation enable bit
This bit is available with each transfer channel and enables/disables the start of DMA transfer.
The channel that is started begins DMA transfer when the transfer request is generated and accepted.
Transfer requests generated for a channel that is not enabled to start will all become invalid.
When the transfers of the started channel are completed covering all the specified number of times,
this bit will become "0" and the transfer will be stopped.
Writing "0" into this bit will cause the forced outage, but make sure that you conduct the forced
outage (write "0") after putting DMA in pause by PAUS bit [bit30:DMACA]. If you conduct the
forced outage without putting it into pause, DMA will be stopped but the transfer data will not be
guaranteed. Use DSS[2:0] bit (bit18 to bit16:DMACB) to confirm the stop.
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CHAPTER 17 DMAC (DMA CONTROLLER)
DENB
Function
0
Corresponding channel DMA operation disabled [Initial value]
1
Corresponding channel DMA operation enabled
•
When reset, if the stop request is accepted: It is initialized to "0".
•
Read/Write allowed.
•
If the operations of all the channels are disabled by bit15 (DMAE) bit of DMAC total control
register DMACR, writing "1" into this bit will be invalid and the stop status will be retained. And
if the operation is disabled by the above bit while it is enabled by this bit, this bit will become
"0", and the transfer will be interrupted (forced outage).
[bit30] PAUS (PAUSe): Pause order
This bit is used to perform the pause control of DMA transfer of the corresponding channel. Once
this bit is set, DMA transfer will not be performed until this bit is cleared again (While DMA is
stopped, DSS bit will become "1XXB").
If you start DMA after setting this bit before the start, it will remain in pause.
Transfer requests freshly generated while this bit is set will be accepted, but the transfer will not be
started unless this bit is cleared (See the section "17.3.2 Configuration for Transfer Request").
PAUS
Function
0
Corresponding channel DMA operation enable [Initial value]
1
Corresponding channel DMA operation pause
•
When reset: It is initialized to "0".
•
Read/Write allowed.
[bit29] STRG (Software TRiGger) : Transfer request
This bit generates DMA transfer request of the corresponding channel. Writing "1" into this bit will
generate a transfer request from the point of time when the write into the register is completed, and
will start the transfer of the corresponding channel.
However, if the corresponding channel is not started, the operation to this bit will be invalid.
298
CHAPTER 17 DMAC (DMA CONTROLLER)
Note:
If the transfer request by this bit coincides with the start by the write into DMAE bit, the transfer
request will become valid and the transfer will be started. And if it coincides with the write "1" into
PAUS bit, the transfer request will become valid, but DMA transfer will not be started until PAUS bit
is returned to "0".
STRG
Function
0
Invalid
1
DMA start request
•
When reset: It is initialized to "0".
•
The Read value is always "0".
•
Only "1" is valid as write value, and "0" does not affect the operation.
299
CHAPTER 17 DMAC (DMA CONTROLLER)
[bit28 to bit24] IS4 to IS0 (Input Select)*: Select transfer factor
These bits are used to select the factor of transfer request as follows. However, software transfer
request by STRG bit function will be valid independent of this setting.
The mark means the bits that affect the operation if they are set during DMAC transfer. Rewrite this
bit while DMAC transfer is stopped (start disabled or in pause).
IS
Function
00000B
Software transfer request only
00001B
↓
01111B
Setting is prohibited
10000B
UART0 (RX completed)
10001B
LIN-UART0 (RX completed)
10010B
LIN-UART1 (RX completed)
10011B
UART0 (TX completed)
10100B
LIN-UART0 (TX completed)
10101B
LIN-UART1 (TX completed)
10110B
External interrupt 0
10111B
External interrupt 1
11000B
Reload timer 0
11001B
Reload timer 1
11010B
Reload timer 2
No
Yes
No
11011B
—
11100B
—
11101B
—
11110B
Transfer stop request
A/D Converter
11111B
—
•
When reset: It is initialized to "00000B".
•
Read/Write allowed.
Note:
If you have configured the configuration for DMA start by the interrupt of peripheral function
(IS=1XXXXB), make the selected function disabled from interrupt by ICR register.
And if you start DMA transfer by software transfer request while you have configured the
configuration for DMA start by the interrupt of peripheral function, it will clear the factor for the
peripheries that apply after the transfer is completed. This may clear the original transfer request, so
please do not start it by software transfer request while you have configured the configuration for
DMA start by the interrupt of peripheral function.
300
CHAPTER 17 DMAC (DMA CONTROLLER)
[bit23 to bit20] Unused bits
The Read value is "0000B" fixed. Write becomes invalid.
[bit19 to bit16] BLK3 to BLK0 (BLocK size): Specify block size
These bits are used to specify the block size for the corresponding channel in block transfer. The
value to be set for these bits will be the number of words in the transfer unit at a time (iteration
counts of data width setting, to be exact). If you do not conduct the block transfer, set "01H" (size 1).
BLK
XXXXB
•
Function
Specifies the block size for the corresponding channel
When reset; Not initialized.
•
Read/Write allowed.
•
If you specify "0" to all the bits, the block size will be 16 words.
•
When read, the block size (reload value) is always read.
[bit15 to bit0] DTC15 to DTC0 (Dma Terminal Count register)*: Transfer count register
This is the register to store transfer count. Each register is configured with 16 bit length.
All the registers have the dedicated reload registers. If it is used for the channel that enables reload
of transfer count register, it automatically returns the initial value when the transfer is completed.
The mark means the bits that affect the operation if they are set during DMAC transfer. Rewrite this
bit while DMAC transfer is stopped (start disabled or in pause).
DTC
XXXXH
Function
Specifies the transfer count of the corresponding channel
When DMA transfer starts, it stores the data of this register in the counter buffer of DMA dedicated
transfer count counter and counts -1 for each one transfer unit (subtraction). When DMA transfer is
completed, it writes back the contents of counter buffer to this register and DMA will terminate.
Therefore, it is impossible to read the specified transfer count value during DMA operations.
•
When reset; Not initialized.
•
Read/Write allowed. Always use halfword length or word length to access DTC.
•
The value when read will be the count value. It is impossible to read the reload value.
301
CHAPTER 17 DMAC (DMA CONTROLLER)
■ DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Control/Status Register B [DMACB0 to DMACB4]
This is the register to perform the operational control of each DMAC channel and exists independently
for each channel.
Each bit function is described as follows.
bit 31
30
Address:
ch.0 000204H
TYPE[1:0]
ch.1 00020CH
ch.2 000214H
ch.3 00021CH
ch.4 000224H
Read/write
27
26
25
24
23
22
21
20
19
WS[1:0] SADM DADM DTCR SADR DADR ERIE EDIE
18
17
16
DSS[2:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
bit
Read/write
29
28
MOD[1:0]
15
14
13
11
11
10
9
8
7
6
5
4
3
2
1
SASZ[7:0]
DASZ[7:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W
0
R/W
(Initial value: 00000000 00000000 XXXXXXXX XXXXXXXXB)
[bit31, bit30] TYPE1, TYPE0 (TYPE)*: Transfer type setting
Set the operation type of the corresponding channel as follows.
Two-cycle transfer mode: This is the mode to set transfer-source address (DMASA) and transferdestination address (DMADA) and to iteratively transfer read operation and write operation for the
number of the transferring.
The mark means the bits that affect the operation if they are set during DMAC transfer. Rewrite this
bit while DMAC transfer is stopped (start disabled or in pause).
TYPE
302
Function
00B
Two-cycle transfer [Initial value]
01B
Setting is prohibited
10B
Setting is prohibited
11B
Setting is prohibited
•
When reset: It is initialized to "00B".
•
Read/Write allowed.
•
Always set this bit to "00B".
CHAPTER 17 DMAC (DMA CONTROLLER)
[bit29, bit28] MOD1,MOD0 (MODe)*: Transfer mode setting
Set the operation mode of the corresponding channel as follows.
The mark means the bits that affect the operation if they are set during DMAC transfer. Rewrite this
bit while DMAC transfer is stopped (start disabled or in pause).
MOD
Function
00B
Block/Step transfer mode [Initial value]
01B
Burst transfer mode
10B
Setting is prohibited
11B
Setting is prohibited
•
When reset: It is initialized to "00B".
•
Read/Write allowed.
[bit27, bit26] WS1, WS0 (Word Size): Select transfer data width
Select transfer data width for the corresponding channel. Conducts the transfer for the specified
number of times in the data width specified for this register.
WS
Function
00B
Transfer in byte unit [Initial value]
01B
Transfer in halfword unit
10B
Transfer in word width unit
11B
Setting is prohibited
•
When reset: It is initialized to "00B".
•
Read/Write allowed.
[bit25] SADM (Source-ADdr. count-Mode select)*: Transfer-source address count Mode
specification
Specifies address handling of transfer-source address for the corresponding channel at each transfer.
Address increase/decrease is added/reduced after 1 transfer in accordance with the set transfersource address count width (SASZ) and when the transfer is completed, the address for next access
is written into the corresponding address register (DMASA).
Therefore, transfer-source address register will not be updated until DMA transfer is completed.
To have address fixed, set this bit to "0" or "1" and set address count width (SASZ, DASZ) to "0".
The mark means the bits that affect the operation if they are set during DMAC transfer. Rewrite this
bit while DMAC transfer is stopped (start disabled or in pause).
SADM
Function
0
Transfer-source address will increase. [Initial value]
1
Transfer-source address will decrease.
303
CHAPTER 17 DMAC (DMA CONTROLLER)
•
When reset: It is initialized to "0".
•
Read/Write allowed.
[bit24] DADM (Destination-ADdr. Count-Mode select)*: Transfer-destination address count
Mode specification
Specifies address handling of transfer-destination address for the corresponding channel at each
transfer.
Address increase/decrease is added/reduced after 1 transfer in accordance with the set transferdestination address count width (DASZ) and when the transfer is completed, the address for next
access is written into the corresponding address register (DMADA).
Therefore, transfer-destination address register will not be updated until DMA transfer is completed.
To have address fixed, set this bit to "0" or "1" and set address count width (SASZ, DASZ) to "0".
The mark means the bits that affect the operation if they are set during DMAC transfer. Rewrite this
bit while DMAC transfer is stopped (start disabled or in pause).
DADM
Function
0
Transfer-destination address will increase. [Initial value]
1
Transfer-destination address will decrease.
•
When reset: It is initialized to "0".
•
Read/Write allowed.
[bit23] DTCR (DTC-reg. Reload)*: Specify transfer count register reload
Controls reload function of transfer count register for the corresponding channel.
If reload operation is enabled by this bit, it returns the count register value to initial value and stops
after the transfer is completed, and enters the transfer request (STRG or start request by IS setting)
wait state (If this bit is "1", DENB bit will not be cleared).
Setting DENB=0, or DMAE=0 will cause forced outage.
If reload operation of count counter is disabled, the operation will be single shot operation that stops
at the completion of transfer, even if reload is specified to address register. DENB bit will be cleared
in this case.
The mark means the bits that affect the operation if they are set during DMAC transfer. Rewrite this
bit while DMAC transfer is stopped (start disabled or in pause).
DTCR
304
Function
0
Disables transfer count register reload [Initial value]
1
Enables transfer count register reload
•
When reset: It is initialized to "0".
•
Read/Write allowed.
CHAPTER 17 DMAC (DMA CONTROLLER)
[bit22] SADR (Source-ADdr.-reg. Reload)*: Specify transfer-source address register reload
Controls reload function of transfer-source address register for the corresponding channel.
If reload operation is enabled by this bit, it returns the transfer-source address register value to initial
value after the transfer is completed.
If reload operation of count counter is disabled, the operation will be single shot operation that stops
at the completion of transfer, even if reload is specified to address register. In this case, address
register value will stop while initial value is reloaded.
If reload operation is disabled by this bit, the address register value at the completion of transfer will
be the access address next to the final address (if address increase is specified, it will be the
increased address).
The mark means the bits that affect the operation if they are set during DMAC transfer. Rewrite this
bit while DMAC transfer is stopped (start disabled or in pause).
SADR
Function
0
Disables transfer-source address register reload [Initial value]
1
Enables transfer-source address register reload
•
When reset: It is initialized to "0".
•
Read/Write allowed.
[bit21] DADR (Dest.-ADdr.-reg. Reload)*: Specify transfer-destination address register
reload
Controls reload function of transfer-destination address register for the corresponding channel.
If reload operation is enabled by this bit, it returns the transfer-destination address register value to
initial value after the transfer is completed.
Others and details of function will be equivalent to the content of bit22 (SADR).
The mark means the bits that affect the operation if they are set during DMAC transfer. Rewrite this
bit while DMAC transfer is stopped (start disabled or in pause).
DADR
Function
0
Disables transfer-destination address register reload [Initial value]
1
Enables transfer-destination address register reload
•
When reset: It is initialized to "0".
•
Read/Write allowed.
[bit20] ERIE (ERror Interrupt Enable)*: Enable error interrupt output
Controls the occurrence of interrupt caused by the occurrence of error at the completion. The content
of error occurred is displayed in DSS2 to DSS0. Note that this interrupt does not occur from all end
factor but that it occurs only in the specific end factor (see DSS2 to DSS0 bit description).
The mark means the bits that affect the operation if they are set during DMAC transfer. Rewrite this
bit while DMAC transfer is stopped (start disabled or in pause).
ERIE
Function
0
Disable error interrupt request output [Initial value]
1
Enables error interrupt request output
•
When reset: It is initialized to "0".
•
Read/Write allowed.
305
CHAPTER 17 DMAC (DMA CONTROLLER)
[bit19] EDIE (EnD Interrupt Enable)*: Enable end interrupt output
Controls the occurrence of interrupt at successful completion.
The mark means the bits that affect the operation if they are set during DMAC transfer. Rewrite this
bit while DMAC transfer is stopped (start disabled or in pause).
EDIE
Function
0
Disable end interrupt request output [Initial value]
1
Enable end interrupt request output
•
When reset: It is initialized to "0".
•
Read/Write allowed.
[bit18 to bit16] DSS2 to DSS0 (Dma Stop Status)*: Display transfer stop factor
Displays the code (completion code) of 3bits that indicates the factor of DMA transfer stop/
completion of the corresponding channel. Contents of the completion code are described as follows.
The mark means the bits that affect the operation if they are set during DMAC transfer. Rewrite this
bit while DMAC transfer is stopped (start disabled or in pause).
The mark means the bits that affect the operation if they are set during DMAC transfer. Rewrite this
bit while DMAC transfer is stopped (start disabled or in pause).
DSS2
Function
Occurrence of interrupt
0
Initial value
None
1
DMA in pause (DMAH, PAUS bit, interrupt etc.)
None
DSS1,
DSS0
00B
Function
Initial value
01B
Occurrence of interrupt
None
-----
None
10B
Transfer stop request
Error
11B
Successful completion
End
The transfer stop request is set only when the request from peripheral circuit is used.
Note: Occurrence of interrupt column shows the type of possible interrupt request.
• When reset: It is initialized to "000B".
• By writing "000B", it will be cleared.
• Read/Write are allowed, however, write "000B" into this bit will only be valid.
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CHAPTER 17 DMAC (DMA CONTROLLER)
[bit15 to bit8] SASZ7 to SASZ0 (Source Addr count SiZe)*: Specify transfer-source address
count size
Specifies increase/decrease range of transfer-source address (DMASA) for each single transfer of the
corresponding channel. The value that is set for this bit will become the increase/decrease range of
address in transmission unit for one time. The increase/decrease of address follows the specification
of transfer-source address count mode (SADM).
The mark means the bits that affect the operation if they are set during DMAC transfer. Rewrite this
bit while DMAC transfer is stopped (start disabled or in pause).
SASZ
Function
00H
Address fixed
01H
Transfer in byte unit
02H
Transfer in halfword unit
04H
Transfer in word unit
Other than
those above
Setting is prohibited
•
When reset; Not initialized.
•
Read/Write allowed.
•
If you set it to other than address fixed, set the same transmission unit as transfer data width
(WS).
[bit7 to bit0] DASZ7 to DASZ0 (Des Addr count SiZe)*:Specify transfer-destination address
count size
Specifies increase/decrease range of transfer-destination address (DMADA) for each single transfer
of the corresponding channel. The value that is set for this bit will become the increase/decrease
range of address in transmission unit for one time. The increase/decrease of address follows the
specification of transfer-destination address count mode (DADM).
The mark means the bits that affect the operation if they are set during DMAC transfer. Rewrite this
bit while DMAC transfer is stopped (start disabled or in pause).
DASZ
Function
00H
Address fixed
01H
Transfer in byte unit
02H
Transfer in halfword unit
04H
Transfer in word unit
Other than
those above
Setting is prohibited
•
When reset; Not initialized.
•
Read/Write allowed.
•
If you set it to other than address fixed, set the same transmission unit as transfer data width
(WS).
307
CHAPTER 17 DMAC (DMA CONTROLLER)
■ DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Transfer-source/Transfer-destination Address
Setting Register [DMASA0 to DMASA4/DMADA0 to DMADA4]
This is the register to perform the operational control of each DMAC channel and exists independently
for each channel.
Each bit function is described as follows.
● ch.0 to ch.3
Address:
bit
ch.0 001000H
ch.1 001008H
ch.2 001010H
ch.3 001018H
Read/write
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DMASA0 to DMASA3
[19:16]
15
14
13
11
11
10
9
8
7
6
5
4
3
2
1
0
DMASA0 to DMASA3 [15:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
(Initial value: XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXXB)
Read/write
bit
Address:
ch.0 001004H
ch.1 00100CH
ch.2 001014H
ch.3 00101CH
Read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DMADA0 to DMADA3
[19:16]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
bit
308
30
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
bit
Read/write
31
15
14
13
11
11
10
9
8
7
6
5
4
3
2
1
0
DMADA0 to DMADA3 [15:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
(Initial value: XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXXB)
CHAPTER 17 DMAC (DMA CONTROLLER)
● ch.4
Address:
bit
ch.4 001020H
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DMASA4 [23:16]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Read/write
bit
15
14
13
11
11
10
9
8
7
6
5
4
3
2
1
0
DMASA4 [15:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
(Initial value: XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXXB)
Read/write
Address:
bit
ch.4 001024H
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DMADA4 [23:16]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Read/write
bit
Read/write
31
15
14
13
11
11
10
9
8
7
6
5
4
3
2
1
0
DMADA4 [15:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
(Initial value: XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXXB)
This is a register group to store transfer-source/destination address. Ch.0 to ch.3 is configured with 20bit
length and ch.4 is configured with 24bit length.
[bit23 to bit0] DMASA (DMA Source Addr)*: Set transfer-source address
Configures the configuration for transfer-source address.
[bit23 to bit0] DMADA (DMA Destination Addr)*: Set transfer-destination address
Configures the configuration for transfer-destination address.
When DMA transfer starts, the device stores the data of this register in the counter buffer of DMA
dedicated address counter and conducts address count for each single transfer according to the
setting. When DMA transfer is completed, it writes back the contents of counter buffer to this
register and DMA will terminate. Therefore, it is impossible to read address counter value during
DMA operations.
All the registers have the dedicated reload registers. If it is used for the channel that enables reload
of transfer-source/transfer-destination address register, it automatically returns the initial value when
the transfer is completed. In this case, it will not affect other address registers.
•
When reset; Not initialized.
•
Read/Write allowed. Always use 32bit data to access this register.
•
The read value, during transfer, will be the address value before the transfer, and when the
transfer is completed, will be the next access address value. It is impossible to read the reload
value. Therefore, it is impossible to read the transfer address in real time.
•
Set "0" for higher-order bits that do not exist.
Note:
Do not set the register of DMAC itself with this register. It is impossible to perform DMA transfer to
the register of DMAC itself.
309
CHAPTER 17 DMAC (DMA CONTROLLER)
■ DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 DMAC Total Control Register
[DMACR]
This register conducts the operational control for overall DMAC 5 channels. Always access this register
by byte.
Each bit function is described as follows.
Address:
bit
000240H
Read/write
30
29
28
DMAE
-
-
PM01
27
26
25
24
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
DMAH[3:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
bit
Read/write
31
15
14
13
11
11
10
9
8
7
6
5
4
3
2
1
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
(Initial value: 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXXB)
[bit31] DMAE (DMA Enable) : Enable DMA operation
This bit is used to perform the operational control of all DMA channels.
If DMA operation is disabled by this bit, the transfer operations of all the channels are disabled,
regardless of start/stop configuration and operational state for each channel. The channels that have
been in transfer operations drop the request, and stop the transfer in block boundary. Any start
operation, which is conducted for each channel while the transfer operations are disabled, will
become invalid.
If DMA operation is enabled by this bit, start/stop operation will become valid for each channel. Just
enabling DMA operation by this bit is not going to start each channel.
Writing "0" into this bit will cause the forced outage, but make sure that you conduct the forced
outage (write "0") after putting DMA in pause by DMAH [3:0] bit (DMACR: bit27 to bit24). If you
conduct the forced outage without putting it into pause, DMA will be stopped but the transfer data
will not be guaranteed. Use DSS [2:0] bit (DMACB: bit18 to bit16) to confirm the stop.
DMAE
310
Function
0
Disable all channels DMA operations [Initial value]
1
Enable all channels DMA operations
•
When reset: It is initialized to "0".
•
Read/Write allowed.
CHAPTER 17 DMAC (DMA CONTROLLER)
[bit28] PM01 (Priority Mode ch.0, ch.1 robin): Channel priority reverse
Set this bit when reversing the priority order of ch.0, ch.1 at each transfer.
PM01
Function
0
Fix priority order (ch.0>ch.1) [Initial value]
1
Reverse priority order (ch.1>ch.0)
•
When reset: It is initialized to "0".
•
Read/Write allowed.
[bit27 to bit24] DMAH3 to DMAH0 (DMA Halt): Halt DMA
These bits are used to perform the halt operation of all DMA channels. Once these bits are set, DMA
transfer of all the channels will not be performed until these bits are cleared again.
If you start DMA after setting these bits before the start, all the channels will remain in halt.
Transfer requests generated in the channels with DMA transfer enabled (DENB=1) while these bits
are set will all be valid, and they will start the transfer by clearing these bits.
DMAH3 to DMAH0
0000B
Other than "0000B"
Function
Enable the total DMA operation [Initial value]
Halt the total DMA operation
•
When reset: It is initialized to "0000B".
•
Read/Write allowed.
[bit30, bit29, bit23 to bit0] Unused bits
The Read value is indeterminate.
311
CHAPTER 17 DMAC (DMA CONTROLLER)
17.3
Description of DMAC Operation
This section outlines DMAC operations and details its transfer request settings and
transfer sequences as well as running features.
■ Overview of DMAC
This block, which is built within the FR family, serves as a multifunction DMA controller that controls
high-speed data transfer without instruction operation from the CPU.
312
CHAPTER 17 DMAC (DMA CONTROLLER)
17.3.1
Operation of DMAC
This section describes the DMAC operation.
■ Major Operations
• Each transfer channel independently sets different types of functions.
• Each channel does not perform transfer operation until it detects the set transfer request after the start
is enabled.
• With the detection of transfer request, each channel outputs DMA transfer request to bus controller,
obtains bus grant through the control of bus controller and starts the transfer.
• The transfer is performed in the sequence compliant with the mode configuration independently
configured for each channel.
■ Transfer Mode
Each channel of DMA performs the transfer operation according to the transfer mode that is set by
MOD[1:0] bit of their respective DMACB registers.
● Block/Step transfer
In a single transfer request, each channel performs the transfer covering only 1 block transmission
unit, and then DMA stops the transfer request to the bus controller until the next transfer request is
accepted.
1 block transmission unit: The set block size equivalence (DMACA: BLK[3:0])
● Burst transfer
In a single transfer request, each channel continuously performs the transfer until the specified
counts of transfer are completed.
Specified transfer counts: Block size equivalence × transfer counts equivalence (DMACA: BLK[3:0] ×
DMACA: DTC[15:0])
■ Transfer Type
● Two-cycle transfer (Normal transfer)
DMA controller performs its operation based on a unit consisting of read operation and write
operation.
It reads the data from the address in transfer-source register and writes the data to the address in
transfer-destination register.
313
CHAPTER 17 DMAC (DMA CONTROLLER)
■ Transfer Address
Addressing includes the ones as below, and it is independently set for each channel transfer-source/
destination.
● Addressing in two-cycle transfer
It accesses the value, as the address, read from the register (DMASA, DMADA) containing the preset address.
Upon receiving transfer request, DMA stores the address from the register in the temporary memory
buffer and starts the transfer.
It generates (add/subtract/fix optional) the next access address in the address counter in each single
transfer (access), and returns it to the temporary memory buffer. The content of this temporary
memory buffer is written back to the register (DMASA, DMADA) each time one block transmission
unit is completed.
It follows that the address register (DMASA, DMADA) value is updated only for each single
transmission unit, therefore, it is impossible to know the address during the transfer in real time.
■ Transfer Count and Transfer Complete
● Transfer count
It decrements (-1) the transfer count register each time one block transmission unit is completed.
When the transfer count register becomes "0", the specified transfer counts will be completed, and it
will stop or restart by displaying the completion code.
As with address register, the transfer count register value is only updated for each single block
transmission unit.
If it is set to transfer count register reload disabled, it terminates the transfer. If it is enabled, it will
initialize the register value and enter the transfer request wait status (DMACB: DTCR).
● Transfer complete
Transfer complete factor includes the ones as described below, and when transfer is completed, the
factors are displayed as the completion code (DMACB: DSS[2:0]).
•
Specified transfer counts complete (DMACA: BLK[3:0] × DMACA: DTC[15:0]) → Successful
completion
•
Occurrence of transfer stop request from peripheral circuits → Error
•
Occurrence of reset → Initial value
Responding to each complete factor, the transfer stop factor is displayed (DSS) and transfer
complete interrupt/error interrupt can be generated.
314
CHAPTER 17 DMAC (DMA CONTROLLER)
17.3.2
Configuration for Transfer Request
Transfer request that starts DMA transfer includes the following 2 types.
• Built-in peripheral request
• Software requirements
Software requirements can always be used irrespective of the configuration for other
requests.
■ Built-in Peripheral Request
From the occurrence of interrupt of built-in peripheral circuits, generate the transfer request.
For each channel, configure the configuration for peripheral interrupt from which to generate the
transfer request (DMACA: IS[4:0]=1XXXXB).
Note:
The interrupt request used in the transfer request can also be regarded as the interrupt request to
CPU, so set the interrupt controller to interrupt disabled (ICR register).
■ Software Requirements
Writing into the trigger bit of register will generate the transfer request (DMACA: STRG).
Independent from the above transfer request, it can always be used.
If you make software requirements simultaneously with the start (transfer enable), the device outputs
DMA transfer request to the bus controller immediately after the requirements and starts the transfer.
Note:
If you make software requirements to the channel to which the built-in peripheral request is set, the
device will clear the factor for the peripheries that apply after the transfer is completed. This may
clear the original transfer request, so do not make software requirements.
315
CHAPTER 17 DMAC (DMA CONTROLLER)
17.3.3
Transfer Sequence
For each channel, it is possible to independently set the transfer type and transfer mode
that determine the operation sequence etc. after the start of DMA transfer
(Configuration for DMACB: TYPE[1:0], MOD[1:0]).
■ Select Transfer Sequence
The following sequence is selectable according to the configuration for register.
•
Burst two-cycle transfer
•
Block/Step two-cycle transfer
■ Burst Two-cycle Transfer
Continuously performs the transfer for the specified transfer counts by a single transfer factor. For
transfer-source/destination address for the case of two-cycle transfer, you can specify 20bit for ch.0 to
ch.3 and 24bit for ch.4.
For transfer factor, you can select peripheral transfer request/software transfer request.
[Characteristics of burst transfer]
•
Upon receiving transfer request once, it continues to transfer until the transfer count register
becomes "0".
•
The transfer counts will be block size equivalence × transfer counts equivalence.
(DMACA: BLK[3:0] × DMACA: DTC[15:0])
•
If the request occurs again during the transfer, the request will be ignored.
•
If reload function of transfer count register is valid, it will receive the request next after the
completion of transfer.
•
If it receives the request of other channel with higher priority during the transfer, it will switch
the channel in the boundary of block transmission unit, and will not revert until the transfer
request of the channel is cleared.
Peripheral transfer request
Bus operation
CPU
Transfer count
SA
DA
4
SA
DA
3
SA
DA
2
SA
DA
1
CPU
0
Transfer complete (internal)
(Peripheral transfer request, example of burst transfer when the number of block=1, transfer count=4)
316
CHAPTER 17 DMAC (DMA CONTROLLER)
■ Step/Block Transfer Two-cycle Transfer
For transfer-source/destination address for the case of step/block transfer (in each single transfer request,
it transfers covering the specified block counts equivalence), you can specify 20bit for ch.0 to ch.3 and
24bit for ch.4.
■ Step Transfer
Specifying "1" to the block size will make the step transfer sequence.
[Characteristics of step transfer]
•
Upon receiving transfer request once, it will clear the transfer request and stop the transfer after
performing the transfer for one time (Drops DMA transfer request to bus controller).
•
If the request occurs again during the transfer, the request will be ignored.
•
If it receives the request of other channel with higher priority during the transfer, it will switch
the channel and will subsequently starts the transfer after the transfer is stopped. Priority in step
transfer will become relevant only when transfer request coincidentally occurs.
■ Block Transfer
Specifying the value other than "1" to the block size will make the block transfer sequence.
[Characteristics of block transfer]
The operation is exactly the same as that of step transfer except that one transmission unit is
comprised of multiple (the number of blocks) transfer cycles.
Peripheral transfer request
Bus operation
CPU
The number of block
SA
DA
SA
2
Transfer count
DA
1
2
CPU
0
SA
DA
SA
2
DA
1
1
Transfer complete (internal)
(Peripheral transfer request, example of block transfer when the number of blocks=2, transfer count=2)
317
CHAPTER 17 DMAC (DMA CONTROLLER)
17.3.4
DMA Transfer in General
This section describes the block size and reload operation of the DMA transfer.
■ Block Size
• One transmission unit for transfer data will make the aggregate of the number of data (× data width)
that is set to the block size specification register.
• Since the data to be transferred in one transfer cycle is fixed by the value of data width specification,
one transmission unit will be comprised of the number of transfer cycles for the block size
specification value.
• In the case where a transfer request with higher priority is accepted or the transfer halt request is
generated during transfer, the transfer will not be stopped even during block transfer unless the block
reaches the boundary of one transmission unit. This allows you to protect the data of the data block
you do not want to divide/halt, however, it will also become the cause of lowering the response if the
block size is large.
• The transfer will be instantaneously stopped only in the case of reset occurrence, but the content of
the data being in transfer etc. will not be guaranteed.
■ Reload Operation
This module allows you to configure the configuration for the following 3 types of reload function for
each channel.
• Transfer count register reload function
After the transfer for the specified counts are completed, it newly sets the initial value to the transfer
count register and waits for the reception of start.
Set when you repeatedly conduct full transfer sequence.
If you do not specify reload, the count register value will remain "0" after the transfer for the
specified counts is completed, and the transfer after the completion will not be performed.
• Transfer-source address register reload function
After the transfer for the specified counts is completed, it newly sets the initial value to the transfersource address register.
It is set when repeatedly transferring from the fixed areas in transfer-source address areas.
If you do not specify reload, the transfer-source address register value will become the address next
to the one at the time of completion after the transfer for the specified counts is completed. It is used
when you do not fix address areas.
• Transfer-destination address register reload function
After the transfer for the specified counts is completed, it newly sets the initial value to the transferdestination address register.
It is set when repeatedly transferring to the fixed areas in transfer-destination address areas.
If you do not specify reload, the transfer-source address register value will become the address next
to the one at the time of completion after the transfer for the specified counts is completed. It is used
when you do not fix address areas.
Just making reload function of transfer-source/destination register valid will not enable the restart
after the completion of the transfer for specified counts, and each address register value will only be
reconfigured.
318
CHAPTER 17 DMAC (DMA CONTROLLER)
Note:
Particular case for operation mode and reload operation
• If you want to once stop at the completion of transfer and conduct again from input detection,
please do not specify reload.
• In the case of transferring in burst/block/step transfer mode, when the transfer is completed, the
transfer will be interrupted once after reload, and will not be performed until the transfer request
input is detected.
319
CHAPTER 17 DMAC (DMA CONTROLLER)
17.3.5
Addressing Mode
Specify transfer-destination and transfer-source address of each transfer channel
independently.
The way how to specify is as described below. Set according to the transfer sequence.
This section explains how to specify the addresses.
■ Specify Address Register
For two-cycle transfer mode, set transfer-source address to transfer-source address setting register
(DMASA) and transfer-destination address to transfer-destination address setting register (DMADA).
[Characteristics of address register]
Ch.0 to ch.3 is configured with 20-bit length and ch.4 is configured with 24-bit length.
[Function of address register]
•
The register is read at each access and the value is released to address bus.
•
At the same instant, address calculation for the access next time is executed in address counter,
and address register is updated by the address resulted from the calculation.
•
Select the address calculation independently for each channel/transfer-destination/transfer-source
from among fixed/addition/subtraction. Address increment/decrement range depends on the
address count size specification register value (DMACB: SASZ, DASZ).
•
In the address register at the end of the transfer, if reload function is not enabled, the address
resulted from the executed address calculation of the final address will be retained.
•
If reload function is enabled, the initial value of address will be reloaded.
Notes:
• If overflow/underflow occurs as the result of 20-bit or 24-bit length full address calculation, the
transfer of the channel will be continued. Set each channel to prevent what overflow/underflow will
occur.
• Do not set the address of the register of DMAC itself to address register.
320
CHAPTER 17 DMAC (DMA CONTROLLER)
17.3.6
Type of Data
Select the data length (data width) to be transferred in a single transfer from among the
following type.
• byte
• halfword
• word
■ Access Address
byte • halfword • word
DMA transfer also complies with word boundary specification, therefore, if an address that is different
from the data length is set in the transfer-destination/transfer-source address specification, the different
lower order bits will be ignored.
• word:
The actual access address will be 4bytes in which lower order 2bits begins with "00B".
• halfword: The actual access address will be 2bytes in which lower order 1bit begins with "0".
• byte:
The actual access address matches with the address specification.
If the lower order bit of transfer-source address differs from that of transfer-destination address, the
address exactly as is set will be outputted on the internal address bus, but the access will be gained for
each transfer object on the bus after the address is corrected in accordance with the rules above.
321
CHAPTER 17 DMAC (DMA CONTROLLER)
17.3.7
Transfer Count Control
Specify transfer count within the range of up to 16 bit length (once to 65536 times). Set
the transfer count specified value to transfer count register (DMACA: DTC).
■ Count Control Register and Reload Operation
The register value is temporarily stored in memory buffer at the start of the transfer and is subtracted by
transfer count counter. When the counter value reaches "0", it is detected as the completion of the
transfer for the specified number of times, and the transfer stop or restart standby of the channel (when
specifying reload) will be executed.
[Characteristics of transfer count register group]
•
Each register is 16 bit length.
•
All the registers have their dedicated reload registers respectively.
•
If DMA starts when the register value is "0", it performs the transfers of 65536 times.
[Reload operation]
322
•
Valid only for the register with reload function and with the reload function enabled.
•
At the start of the transfer, it evacuates the initial value of count register to reload register.
•
When the count reaches "0" while conducting the count in transfer count counter, it will notify
the completion of transfer, read the initial value from the reload register, and will write it into the
count register.
CHAPTER 17 DMAC (DMA CONTROLLER)
17.3.8
CPU Control
Once DMA transfer request is accepted, DMA issues the transfer request to bus
controller.
The bus controller delivers the internal bus ownership to DMA at the breakpoint of the
bus operation, and DMA transfer is started.
■ DMA Transfer and Interrupt
If the interrupt request generated is at a higher level than that of the NMI request or the hold inhibiting
level set in the HRCL register of the interrupt controller during DMA transfer, DMAC temporarily
withdraws the transfer request to the bus controller across the boundary of the transfer unit (1 block),
and suspends the transfer until the interrupt request is cleared. During this period, the transfer request is
retained internally. After the interrupt request is cleared, DMAC reissues the transfer request to the bus
controller to obtain the right to use the bus and DMA transfer resumes.
If the interrupt level is lower than the level set in the HRCL register, no interrupt can be accepted until
the DMA transfer is completed. Moreover, if DMA transfer request is made during the handling
operation of an interrupt at a level lower than the value set in HRCL, the transfer request is accepted and
the interrupt handling operation is suspended until the completion of the transfer.
The DMA transfer request level is set to the lowest by default. At this level, transfer is stopped for all
interrupt requests and the interrupt handling operation has a higher priority.
■ Inhibit DMA
The FR family will halt DMA transfer and branch to the corresponding interrupt routine if an interrupt
factor with higher priority occurs during DMA transfer. This mechanism is valid so long as there is
interrupt request, however, once the interrupt factor is cleared, the inhibiting mechanism will not work
and it will resume DMA transfer within the interrupt handling routine. Therefore, if you want to inhibit
the restart of DMA transfer after the interrupt factor is cleared within the interrupt factor handling
routine of the level that halts DMA transfer, use DMA inhibiting function. DMA inhibiting function is
started by writing the value other than "0" to DMAH[3:0] bit in overall DMA control register and is
stopped by writing "0".
This function is primarily used within the interrupt handling routine. Before clearing the interrupt factor
by the interrupt handling routine, increment the content of DMA inhibiting register by one. This will
keep DMA from being executed afterwards. After having dealt with the interrupt handling, decrement
the content of DMAH[3:0] bit by one before reverting. If it is multiple interrupt, the content of
DMAH[3:0]bit will not reach "0" yet, and so DMA transfer will continue to be forbidden. And if it is not
multiple interrupt, the content of DMAH[3:0] bit will reach "0", which will validate DMA request
immediately after that moment.
Notes:
• Since the number of bits of the register is 4 bits, it is not possible to use this function in the
multiple interrupt exceeding 15 levels.
• Put the priority order of DMA task always above other interrupt level by at least 15 levels.
323
CHAPTER 17 DMAC (DMA CONTROLLER)
17.3.9
Start Operation
This section describes the start operation of the DMA transfer.
■ Start Operation
The start of DMA transfer should be controlled independently for each channel, however, the operations
of all the channels should be enabled before that.
● Enable all channel's operations
Before starting each channel of DMAC, the operations of all the channels should be enabled in advance
by DMA operation enable bit (DMACR: DMAE). The start configuration conducted while the
operations are not enabled, and the transfer requests that have occurred will all become invalid.
● Start transfer
Start the transfer operation by the operation enable bit that is in the control register for each channel.
Once the transfer request for the stated channel is accepted, DMA transfer operation will be started in
the set mode.
● Start from pause status
If the transfer has been put into pause status by each channel's or all the channel's control before the
start, the pause status will be retained even if you start the transfer operation. If a transfer request occurs
during this time, the request will be accepted and retained. It will start the transfer operation from the
point of time when the pause is canceled.
324
CHAPTER 17 DMAC (DMA CONTROLLER)
17.3.10
Accept and Transfer the Transfer Request
This section describes the accept and transfer of the transfer request.
■ Accept and Transfer the Transfer Request
• After the start, the sampling of the transfer request set to each channel will be started.
• If you select the peripheral interrupt start, DMAC will continue the transfer until the transfer request
is cleared, but once it is cleared, DMAC will stop the transfer in a single transfer unit (peripheral
interrupt start).
Since peripheral interrupt is handled as level detection, make sure you execute the interrupt by the
interrupt clearing by DMA.
• Transfer request is constantly accepted even while the transfer is carried out with other channel's
request being accepted, and DMAC determines the channel to transfer for each single transfer unit
by prioritizing the transfer.
325
CHAPTER 17 DMAC (DMA CONTROLLER)
17.3.11
Peripheral Interrupt Clearing by DMA
This DMA has the function of clearing peripheral interrupt. This function works when
you select peripheral interrupt as DMA start factor (When IS[4:0]=1XXXXB).
Peripheral interrupt clearing is conducted only to the set start factor. This means that
the peripheral function set by IS[4:0] will only be cleared.
■ Occurrence Timing of Interrupt Clearing
The occurrence timing varies with transfer mode (See section "17.4 Operation Flow of DMAC").
[Block/Step transfer]
If you select block transfer, the clear signal will occur in each single block (step) transfer.
[Burst transfer]
If you select burst transfer, the clear signal will occur when the specified transfer counts are all
completed.
326
CHAPTER 17 DMAC (DMA CONTROLLER)
17.3.12
Pause
DMA will pause in the following cases.
■ When the Pause is Set by Writing into the Control Register
(Set Independently for Each Channel or Simultaneously for All the Channels).
Setting the pause by the pause bit will stop the transfer of the corresponding channel until the pause
cancellation is set again. Use DSS bit to check on the pause.
Once you cancel the pause, DMA will resume the transfer.
■ When NMI/Hold Inhibiting Level Interrupt Handling is in Process
In the case where NMI request, or an interrupt request of the higher level than the hold inhibiting level
occurs, the channels in transfer will all pause at the boundary of transfer unit, and prioritize NMI/
interrupt handling by releasing the bus ownership. And a transfer request accepted during NMI/interrupt
handling will be retained as is and wait for the completion of NMI handling.
The channel for which the request is retained will resume the transfer after NMI/interrupt handling is
completed.
327
CHAPTER 17 DMAC (DMA CONTROLLER)
17.3.13
Operation Complete/Stop
The completion of DMA transfer is controlled independently for each channel, and, it is
also possible to disable the operations of all the channels.
■ Transfer Complete
If reload operation is not valid, DMA will stop the transfer when transfer count register reaches "0", and
after displaying [Successful completion] by the completion code, the transfer request from then will
become invalid (Clear DMACA: DENB bit).
If reload operation is valid, DMA will reload the initial value when transfer count register reaches "0",
and after displaying [Successful completion] by the completion code, it will wait for the transfer request
again (Not clear DMACA: DENB bit).
■ Disable All Channel's Operations
If you disable the operations of all the channels by DMA operation enable bit DMAE, all the operations
of DMAC including the channels that have been in operation will stop. If you enable DMA operations
of all the channels again afterwards, the transfer will not be performed unless you restart with each
channel. In this case, interrupts will not occur at all.
328
CHAPTER 17 DMAC (DMA CONTROLLER)
17.3.14
Stop Caused by Error
Included in the cases where the transfer is stopped due to the factors other than
successful completion by the completion of transfer for the specified count are the stop
due to the occurrence of various errors and the forced outage.
■ Occurrence of Transfer Stop Request from Peripheral Circuits
Among the peripheral circuits that output transfer request, some generate a transfer stop request at such
a time when they detect a trouble (example: reception/transmission error in communication system
peripheries, etc.).
DMAC that receives the transfer stop request will display [Transfer stop request] by the completion
code and stop the transfer of the corresponding channel.
Notes:
• For the presence/absence of transfer stop request of peripheral circuits, see the description of
bit28 to bit24 (IS4 to IS0) Transfer factor selection bit in DMACA register.
• For details of occurrence condition of each transfer stop request, see the specification of each
peripheral circuit.
329
CHAPTER 17 DMAC (DMA CONTROLLER)
17.3.15
DMAC Interrupt Control
Independent from the peripheral interrupt as the transfer request, it is possible to
output the following interrupt for each DMAC channel.
■ Interrupts Enabling Output of DMAC Interrupt Control
• Transfer complete interrupt: Occurs only when DMA is successfully completed.
• Error interrupt
:Transfer stop request from peripheral circuits (Error attributable to the
peripheries)
These interrupts are all outputted according to the contents of completion code.
Write "000B" into DSS2 to DSS0 (completion code) of DMACS to clear interrupt request. For
completion code, do not fail to clear it by writing "000B" when restarting.
DMA will automatically restart if reload operation is valid, but the completion code will not be cleared
in this case, and it will be retained until the time when the new completion code is written with the
completion of the next transfer.
Completion factor that can be displayed by the completion code is only one type, so if several factors
occur at the same time, it will display the result of prioritization. Interrupts that occur in this case will
comply with the completion code displayed.
The priority for the display of completion code is described as follows (in the order of priority from the
top).
• Reset
• Clearing by writing "000B"
• Peripheral stop request
• Successful completion
• Channel selection and control
330
CHAPTER 17 DMAC (DMA CONTROLLER)
17.3.16
DMA Transfer During Sleep
DMAC can be operated even during sleep mode. This section describes the DMA
transfer during sleep.
■ Notes on DMA Transfer During Sleep
If you expect the operation in sleep mode, you must pay attention to the following.
- Since CPU is stopped, you cannot rewrite the registers of DMAC. Complete the configuration
before entering sleep mode.
- Sleep mode can be canceled by interrupt, so if you have selected the peripheral interrupt for
DMAC start factor, you must disable the interrupt by interrupt controller.
Also, if you do not want to cancel sleep mode by DMAC end interrupt, disable the interrupt.
331
CHAPTER 17 DMAC (DMA CONTROLLER)
17.3.17
Channel Selection and Control
The number of transfer channels can be set simultaneously up to 5 channels. Each
channel can basically set each function independently.
■ Priority among Channels
Since DMA transfer is available only with 1 channel at the same time, the priority is set among each
channel.
The priority configuration have 2 modes of fixed/reversed, and select it for each channel group (to be
hereinafter described).
● Fixed mode
To be fixed in ascending order of channel number.
(ch.0>ch.1>ch.2>ch.3>ch.4)
If a transfer request with higher priority is accepted during transfer, the transfer channel is switched
to the higher priority side at the end of the transfer for 1 transfer unit (the number set to the block
size specification register × data width).
When the transfer of the higher priority side ends, DMA will resume the transfer of the original
channel.
ch.0 transfer request
ch.1 transfer request
Bus operation
CPU
SA
Transfer channel
DA
SA
ch.1
DA
ch.0
SA
DA
ch.0
SA
DA
CPU
ch.1
ch.0 transfer complete
ch.1 transfer complete
● Reversed mode (between ch.0 and ch.1 only)
The initial state after enabling the operation is set in the same order as Fixed mode, but the priority
of the channel is reversed each time 1 transfer is completed. Therefore, if transfer request is
outputted at the same time, the channel will be switched for each single transfer unit.
This is the mode that is effective when continuous/burst transfer is set.
ch.0 transfer request
ch.1 transfer request
Bus operation
Transfer channel
ch.0 transfer complete
ch.1 transfer complete
332
CPU
SA
DA
ch.1
SA
DA
ch.0
SA
DA
ch.1
SA
DA
ch.0
CPU
CHAPTER 17 DMAC (DMA CONTROLLER)
■ Channel Group
Set the selection of priority by the following unit.
Mode
Priority
Remarks
Fixed
ch.0 > ch.1
-
Reversed
ch.0 > ch.1
↑ ↓
ch.0 < ch.1
The initial state is the order of upper side.
When the upper one is transferred, the order is reversed.
333
CHAPTER 17 DMAC (DMA CONTROLLER)
17.4
Operation Flow of DMAC
This section shows operation flowcharts for the following transfer modes.
• Block Transfer
• Burst Transfer
■ Block Transfer
Figure 17.4-1 Operation Flow of Block Transfer
DENB
DMA stop
0
DENB=1
Enable reload
Start request
standby
Start request
initial
Address, Transfer count, Number of blocks
Load
Transfer-source address access
Address operation
Transfer-destination address access
Address operation
Number of block-1
BLK=0
Transfer count-1
Only when selecting peripheral interrupt start factor
Address, Transfer count, Number of blocks
Write back
Interrupt clearing
Interrupt clearing occurrence
DTC=0
DMA transfer complete
DMA interrupt occurrence
Features:
• Can be started by all the start factors (select).
• Accessible to all the areas.
• The number of blocks is settable.
• Issues interrupt clearing at the completion of the number of blocks.
• Issues DMA interrupt at the completion of the specified transfer counts.
334
CHAPTER 17 DMAC (DMA CONTROLLER)
■ Burst Transfer
Figure 17.4-2 Operation Flow of Burst Transfer
DENB
DMA stop
0
DENB=1
Start request
standby
Enable reload
initial
Address, Transfer count, Number of blocks
Load
Transfer-source address access
Address operation
Transfer-destination address access
Address operation
Number of
block-1
BLK=0
Transfer count-1
DTC=0
Address, Transfer count,
Number of blocks
Write back
Only when selecting peripheral interrupt start factor
Interrupt clearing
DMA transfer complete
Interrupt clearing occurrence
DMA interrupt occurrence
Features:
• Can be started by all the start factors (select).
• Accessible to all the areas.
• The number of blocks is settable.
• Cleans interrupt at the completion of the specified transfer counts, and issues DMA interrupt.
335
CHAPTER 17 DMAC (DMA CONTROLLER)
17.5
Data Path of DMAC
This section describes the Two-cycle data flow during cycle transfer.
■ Two-cycle Data Flow During Cycle Transfer
6 types of transfer examples are shown in the figure (Other combinations are omitted).
X-bus
Bus controller
D-bus
Data buffer
I-bus
X-bus
Bus controller
D-bus
Data buffer
F-bus
F-bus
RAM
External bus I/F
CPU
I-bus
DMAC
Write cycle
CPU
DMAC
Read cycle
External bus I/F
External areas=>External areas transfer
I/O
RAM
I/O
CPU
I-bus
X-bus
Bus controller
D-bus
Write cycle
I-bus
Data buffer
X-bus
Bus controller
D-bus
Data buffer
F-bus
RAM
External bus I/F
Read cycle
DMAC
CPU
DMAC
External bus I/F
External areas=>Internal RAM areas transfer
F-bus
I/O
RAM
I/O
X-bus
Bus controller
D-bus
Data buffer
I-bus
X-bus
Bus controller
D-bus
Data buffer
F-bus
RAM
I/O
External bus I/F
CPU
I-bus
DMAC
Write cycle
CPU
DMAC
Read cycle
External bus I/F
External areas=>Built-in I/O areas transfer
F-bus
RAM
I/O
(Continued)
336
CHAPTER 17 DMAC (DMA CONTROLLER)
(Continued)
X-bus
Bus controller
D-bus
I-bus
Data buffer
X-bus
Bus controller
D-bus
F-bus
RAM
External bus I/F
CPU
I-bus
DMAC
Write cycle
CPU
DMAC
Read cycle
External bus I/F
Built-in I/O areas=>Built-in RAM areas transfer
F-bus
I/O
RAM
I/O
X-bus
Bus controller
D-bus
I-bus
Data buffer
X-bus
Bus controller
D-bus
Data buffer
F-bus
RAM
External bus I/F
CPU
I-bus
DMAC
Write cycle
CPU
DMAC
Read cycle
External bus I/F
Internal RAM areas=>External areas transfer
F-bus
I/O
RAM
I/O
CPU
Bus controller
D-bus
Data buffer
X-bus
I-bus
Bus controller
D-bus
Data buffer
F-bus
RAM
I/O
External bus I/F
X-bus
I-bus
DMAC
Write cycle
CPU
DMAC
Read cycle
External bus I/F
Internal RAM areas=>Built-in I/O areas transfer
F-bus
RAM
I/O
337
CHAPTER 17 DMAC (DMA CONTROLLER)
338
CHAPTER 18
STEPPER MOTOR
CONTROLLER
This chapter outlines the stepper motor controller and
describes its register configuration, functions and
operations.
18.1 Overview of the Stepper Motor Controller
18.2 Stepper Motor Controller Register
18.3 Precautions when Using Stepper Motor Controller
339
CHAPTER 18 STEPPER MOTOR CONTROLLER
18.1
Overview of the Stepper Motor Controller
This section describes an overview of the stepper motor controller and block diagrams.
■ Overview of the Stepper Motor Controller
The stepper motor controller is configured from two PWM pulse generators, four motor drivers, and a
selector logic.
This four type of motor driver has a high-output drive function, and can be connected directly to the
four terminals on the two motor coils. The motor rotation is designed to be controlled using a
combination of the PWM pulse generators and selector logic. The synchronization mechanism assures
synchronous operation of the two PWMs.
■ Block Diagram of the Stepper Motor Controller
The block diagram for the stepper motor controller is shown in Figure 18.1-1.
Figure 18.1-1 Stepper Motor Controller Block Diagram
Machine clock
CK
Prescaler
EN
P2
P1
PWM1P0
PWM1 pulse generator
Selector
PWM1M0
PWM
P0
PWM1
compare register
PWM1
select register
CK
PWM2P0
PWM2 pulse generator
CE
EN
Selector
PWM2M0
PWM
Load
PWM2
compare register
340
BS
PWM2
select register
CHAPTER 18 STEPPER MOTOR CONTROLLER
18.2
Stepper Motor Controller Register
This section explains the stepper motor controller register functions.
■ Stepper Motor Controller Register List
The stepper motor controller register list is described in Figure 18.2-1.
Figure 18.2-1 Stepper Motor Controller Register List
PWC
Address
ch.0: 000169H
ch.1: 000171H
ch.2: 000179H
ch.3: 000181H
ch.4: 000189H
ch.5: 000191H
PWC2
Address
ch.0: 000164H
ch.1: 00016CH
ch.2: 000174H
ch.3: 00017CH
ch.4: 000184H
ch.5: 00018CH
PWC1
Address
ch.0: 000165H
ch.1: 00016DH
ch.2: 000175H
ch.3: 00017DH
ch.4: 000185H
ch.5: 00018DH
PWS2
Address
ch.0: 00016AH
ch.1: 000172H
ch.2: 00017AH
ch.3: 000182H
ch.4: 00018AH
ch.5: 000192H
PWS1
Address
ch.0: 00016BH
ch.1: 000173H
ch.2: 00017BH
ch.3: 000183H
ch.4: 00018BH
ch.5: 000193H
bit 7
(-)
6
P2
(R/W)
5
P1
(R/W)
4
P0
(R/W)
3
CE
(R/W)
2
(-)
1
(-)
0
TST
(R/W)
(-)
(0)
(0)
(0)
(0)
(-)
(-)
(0)
bit 15
D7
(R/W)
14
D6
(R/W)
13
D5
(R/W)
12
D4
(R/W)
11
D3
(R/W)
10
D2
(R/W)
9
D1
(R/W)
8
D0
(R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
bit 7
D7
(R/W)
6
D6
(R/W)
5
D5
(R/W)
4
D4
(R/W)
3
D3
(R/W)
2
D2
(R/W)
1
D1
(R/W)
0
D0
(R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
14
BS
(R/W)
13
P2
(R/W)
12
P1
(R/W)
11
P0
(R/W)
10
M2
(R/W)
9
M1
(R/W)
8
M0
(R/W)
(-)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
bit 7
(-)
6
(-)
5
P2
(R/W)
4
P1
(R/W)
3
P0
(R/W)
2
M2
(R/W)
1
M1
(R/W)
0
M0
(R/W)
(-)
(-)
(0)
(0)
(0)
(0)
(0)
(0)
bit 15
(-)
Read/Write
Initial value
Read/Write
Initial value
Read/Write
Initial value
Read/Write
Initial value
Read/Write
Initial value
341
CHAPTER 18 STEPPER MOTOR CONTROLLER
18.2.1
PWM Control Register
This section explains the PWM control register functions.
■ PWM Control Register Bit Configuration
The PWM control register bit configuration is shown in Figure 18.2-2.
Figure 18.2-2 PWM Control Register Bit Configuration
PWC
Address
ch.0: 000169H
ch.1: 000171H
ch.2: 000179H
ch.3: 000181H
ch.4: 000189H
ch.5: 000191H
bit 7
(-)
(-)
6
P2
(R/W)
5
P1
(R/W)
4
P0
(R/W)
3
CE
(R/W)
2
(-)
1
(-)
0
TST
(R/W)
(0)
(0)
(0)
(0)
(-)
(-)
(0)
Read/Write
Initial value
[bit6 to bit4] P2 to P0: Operation clock selection bits
These bit specify clock input signals for the PWM pulse generator.
The configuration for the PWM pulse generator clock input signals are shown in Table 18.2-1.
Table 18.2-1 PWM Pulse Generator Clock Input Signals
P2
P1
P0
Clock input
0
0
0
Machine clock (CLKP)
0
0
1
1/2 machine clock
0
1
0
1/4 machine clock
0
1
1
1/8 machine clock
1
0
0
Reserved
1
0
1
1/5 machine clock
1
1
0
1/6 machine clock
1
1
1
Reserved
[bit3] CE: Count enable bit
This bit enables operations for the PWM pulse generator. Set this to "1" to start PWM pulse generator
operations. Note that the PWM2 pulse generator will start to operate after the completion of one
machine clock cycle from the start of the PWM1 pulse generator. Consequently, the switching noise
from the output driver is reduced.
[bit0] TST: Test bit
This bit is used for device testing. In user applications, it must always be set to "0".
342
CHAPTER 18 STEPPER MOTOR CONTROLLER
18.2.2
PWM1 and PWM2 Compare Registers
The PWM pulse width is determined by the content of the two 8-bit compare registers:
PWM1 and PWM2. When the stored value is "00H", it means the duty of PWM is 0%,
while "FFH" means that the duty is 99.6%.
■ PWM1 and PWM2 Compare Registers Functions
The bit configuration of the PWM1 and PWM2 compare registers is shown in Figure 18.2-3.
Figure 18.2-3 PWM1 and PWM2 Compare Registers Bit Configuration
PWC2
Address
ch.0: 000164H
ch.1: 00016CH
ch.2: 000174H
ch.3: 00017CH
ch.4: 000184H
ch.5: 00018CH
PWC1
Address
ch.0: 000165H
ch.1: 00016 DH
ch.2: 000175H
ch.3: 00017DH
ch.4: 000185H
ch.5: 00018DH
bit 15
D7
(R/W)
14
D6
(R/W)
13
D5
(R/W)
12
D4
(R/W)
11
D3
(R/W)
10
D2
(R/W)
9
D1
(R/W)
8
D0
(R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
bit 7
D7
(R/W)
6
D6
(R/W)
5
D5
(R/W)
4
D4
(R/W)
3
D3
(R/W)
2
D2
(R/W)
1
D1
(R/W)
0
D0
(R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Read/Write
Initial value
Read/Write
Initial value
The contents of the two 8-bit compare registers determine the PWM pulse widths.
The stored value of "00H" means the PWM duty of 0% and the stored value of "FFH" means the PWM
duty of 99.6%.
The relationship between the compare register set values and the PWM pulse widths are shown in
Figure 18.2-4.
343
CHAPTER 18 STEPPER MOTOR CONTROLLER
Figure 18.2-4 Relationship between the Compare Register Set Values and the PWM Pulse Widths
1 PWM cycle
Register value
256 input clock cycles
00H
80H
128 input clock cycles
FFH
256 input clock cycles
This register can be accessed at any time, but the adjustment value is reflected by the pulse width when
the current PWM cycle has ended, after "1" has been set as the BS bit in the PWM2 selection register.
344
CHAPTER 18 STEPPER MOTOR CONTROLLER
18.2.3
PWM1 and PWM2 Selection Register
This section explains the functions of the PWM1 and PWM2 selection register.
■ PWM1 and PWM2 Selection Register Functions
The bit configuration of the PWM1 and PWM2 selection register is shown in Figure 18.2-5.
Figure 18.2-5 PWM1 and PWM2 Selection Register Bit Configuration
PWS2
Address
ch.0: 00016AH
ch.1: 000172H
ch.2: 00017AH
ch.3: 000182H
ch.4: 00018AH
ch.5: 000192H
PWS1
Address
ch.0: 00016BH
ch.1: 000173H
ch.2: 00017BH
ch.3: 000183H
ch.4: 00018BH
ch.5: 000193H
bit 15
(-)
14
BS
(R/W)
13
P2
(R/W)
12
P1
(R/W)
11
P0
(R/W)
10
M2
(R/W)
9
M1
(R/W)
8
M0
(R/W)
(-)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
bit 7
(-)
6
(-)
5
P2
(R/W)
4
P1
(R/W)
3
P0
(R/W)
2
M2
(R/W)
1
M1
(R/W)
0
M0
(R/W)
(-)
(-)
(0)
(0)
(0)
(0)
(0)
(0)
Read/Write
Initial value
Read/Write
Initial value
[bit14] BS: Refresh bit
This bit is used to adjust the synchronization of the PWM output configuration. Adjustment of both
comparison registers and both selection registers are not applied in the output signals until this bit has
been set.
If this bit is set to "1", the PWM pulse generators and selectors load the register contents when the
current PWM cycle has ended. The BS bit is reset to "0" automatically when the PWM immediately
after PWM cycle ended cycle starts. If the software sets the BS bit to "1" at the same time as the
automatic reset is performed, the BS bit is set to "1" (i.e., remains unchanged), and the automatic reset is
canceled.
[bit13 to bit11] P2 to P0: Output selection bits
These bits select the PWM2P0 output signals.
[bit10 to bit8] M2 to M0: Output selection bits
These bits select the PWM2M0 output signals.
[bit5 to bit3] P2 to P0: Output selection bits
These bits select the PWM1P0 output signals.
The relations between the output levels and the selection bits are shown in Table 18.2-2.
345
CHAPTER 18 STEPPER MOTOR CONTROLLER
[bit2 to bit0] M2 to M0: Output selection bits
These bits select the PWM1M0 output signals.
The relations between the output levels and the selection bits are shown in Table 18.2-2.
Table 18.2-2 Relation between Output Level and Selection Bit
346
P2
P1
P0
PWMnP0
M2
M1
M0
PWMnM0
0
0
0
"L"
0
0
0
"L"
0
0
1
"H"
0
0
1
"H"
0
1
X
PWM pulse
0
1
X
PWM pulse
1
X
X
High impedance
1
X
X
High impedance
CHAPTER 18 STEPPER MOTOR CONTROLLER
18.3
Precautions when Using Stepper Motor Controller
This section explains the precautions that must be followed when using the stepper
motor controller.
■ Precautions When Changing PWM Setting Values
PWM comparison register 1 (PWC1n), PWM comparison register 2 (PWC2n), PWM selection register 1
(PWS1n) and PWM selection register 2 (PWS2n) can be accessed at any time. However, to change the
"H"-width setting of PWM or the PWM output, you must write "1" to the BS bit in the PWM selection
register 2 after (or at the same time as) writing a setting value in these registers.
When the BS bit is set to "1", the new setting value becomes valid and the BS bit is cleared automatically
upon completion of the current PWM cycle.
If an attempt is made to write "1" to the BS bit and reset this bit on completion of the PWM cycle at the
same time, the writing attempt has a higher priority; therefore, the reset attempt for the BS bit will be
canceled.
347
CHAPTER 18 STEPPER MOTOR CONTROLLER
348
CHAPTER 19
SOUND GENERATOR
This chapter outlines the sound generator and describes
its register configuration, functions and operations.
19.1 Overview of Sound Generator
19.2 Sound Generator Registers
349
CHAPTER 19 SOUND GENERATOR
19.1
Overview of Sound Generator
This section outlines the sound generator and presents its block diagram.
■ Sound Generator Components
The sound generator is composed of the following registers and counters.
• Sound control register
• Frequency data register
• Amplitude data register
• Decrement grade register
• Tone count register
• Sound disable register
• PWM pulse generator
• Frequency counter
• Decrement counter
• Tone pulse counter
■ Block Diagram of Sound Generator
Figure 19.1-1 shows a block diagram of the sound generator.
Figure 19.1-1 Block Diagram of Sound Generator
Clock input
Prescaler
S2
S1
8-bit PWM
pulse
generator
CO
EN
PWM
CI
Toggle
flip-flop
Frequency
counter
CO
EN
Reload
Amplitude Data
register
D
EN
Q
1/d
Reload
Frequency
data register
DEC
DEC
Decrement
counter
CI
CO
EN
SGA
Decrement Grade
register
Tone pulse
counter
Tone Count
register
Mix
SGO
TONE
CI
CO
EN
INTE
INT
ST
IRQ
350
CHAPTER 19 SOUND GENERATOR
19.2
Sound Generator Registers
This section describes the functions of the sound generator registers.
■ Sound Generator Register List
Figure 19.2-1 shows a list of the sound generator registers.
Figure 19.2-1 Sound Generator Register List
SGCR (upper byte)
bit 15
Address: 000092H
TST
Read/Write (R/W)
Initial value
(0)
14
(-)
(-)
13
(-)
(-)
12
(-)
(-)
11
(-)
(-)
10
(-)
(-)
9
BUSY
(R)
(0)
8
DEC
(R/W)
(0)
SGCR (lower byte)
bit 7
Address: 000093H
S1
Read/Write (R/W)
Initial value
(0)
6
S0
(R/W)
(0)
5
TONE
(R/W)
(0)
4
(-)
(-)
3
(-)
(-)
2
INTE
(R/W)
(0)
1
INT
(R/W)
(0)
0
ST
(R/W)
(0)
SGAR
bit 15
Address: 000094H
D7
Read/Write (R/W)
Initial value
(0)
14
D6
(R/W)
(0)
13
D5
(R/W)
(0)
12
D4
(R/W)
(0)
11
D3
(R/W)
(0)
10
D2
(R/W)
(0)
9
D1
(R/W)
(0)
8
D0
(R/W)
(0)
SGFR
bit 7
Address: 000095H
D7
Read/Write (R/W)
Initial value
(X)
6
D6
(R/W)
(X)
5
D5
(R/W)
(X)
4
D4
(R/W)
(X)
3
D3
(R/W)
(X)
2
D2
(R/W)
(X)
1
D1
(R/W)
(X)
0
D0
(R/W)
(X)
SGTR
bit 15
Address: 000096H
D7
Read/Write (R/W)
Initial value
(X)
14
D6
(R/W)
(X)
13
D5
(R/W)
(X)
12
D4
(R/W)
(X)
11
D3
(R/W)
(X)
10
D2
(R/W)
(X)
9
D1
(R/W)
(X)
8
D0
(R/W)
(X)
SGDR
bit 7
Address: 000097H
D7
Read/Write (R/W)
Initial value
(X)
6
D6
(R/W)
(X)
5
D5
(R/W)
(X)
4
D4
(R/W)
(X)
3
D3
(R/W)
(X)
2
D2
(R/W)
(X)
1
D1
(R/W)
(X)
0
D0
(R/W)
(X)
6
(-)
(-)
5
(-)
(-)
4
(-)
(-)
3
(-)
(-)
2
(-)
(-)
1
(-)
(-)
0
DBL
(R/W)
(0)
SGDBL
bit 7
Address: 000091H
Read/Write
(-)
Initial value
(-)
351
CHAPTER 19 SOUND GENERATOR
19.2.1
Sound Control Register
This section describes the functions of the sound control register.
■ Bit Configuration of Sound Control Register
Figure 19.2-2 shows the bit configuration in the sound control register.
Figure 19.2-2 Bit Configuration of Sound Control Register
SGCR (upper byte)
bit 15
Address: 000092H
TST
Read/Write (R/W)
Initial value
(0)
14
(-)
(-)
13
(-)
(-)
12
(-)
(-)
11
(-)
(-)
10
(-)
(-)
9
BUSY
(R)
(0)
8
DEC
(R/W)
(0)
SGCR (lower byte)
bit 7
Address: 000093H
S1
Read/Write (R/W)
Initial value
(0)
6
S0
(R/W)
(0)
5
TONE
(R/W)
(0)
4
(-)
(-)
3
(-)
(-)
2
INTE
(R/W)
(0)
1
INT
(R/W)
(0)
0
ST
(R/W)
(0)
The function of each bit on the sound control register is described below.
[bit15] TST: Test bit
This bit is used to test the device. Any user application must set this bit to "0".
[bit9] BUSY: Busy bit
This bit indicates whether the sound generator is operating. When the ST bit is set to "1", this bit is also
set to "1". When the ST bit is reset to "0" to end operation of one tone cycle, this bit is reset to "0". Any
instruction to write data to this bit is treated as invalid.
[bit8] DEC: Automatic decrement enable bit
The DEC bit, together with the decrement grade register, is designed to automatically decrement sounds.
If this bit is set to "1", the value stored in the amplitude data register will be decremented by 1 each time
the decrement counter counts the number of tone pulses from the toggle flip-flop designated by the
decrement grade register.
[bit7, bit6] S1, S0: Operation clock selection bits
These bits specify the clock input signal for the sound generator. Table 19.2-1 indicates how the input
clock signal is selected.
Table 19.2-1 Input Clock Signal Selection
352
S1
S0
Clock input
0
0
Machine clock
0
1
1/2 machine clock
1
0
1/4 machine clock
1
1
1/8 machine clock
CHAPTER 19 SOUND GENERATOR
[bit5] TONE: Tone output bit
When this bit is set to "1", the SGO signal becomes the simple square wave (tone pulses) from the
toggle flip-flop. When this bit is set to a non-"1" value, the SGO signal becomes the OR of the tone
pulses and the PWM pulses.
[bit2] INTE: Interrupt enable bit
This bit enables interrupt signals from the sound generator. When this bit is set to "1" and the INT bit is
also set to "1", the sound generator outputs an interrupt signal.
[bit1] INT: Interrupt bit
This bit is set to "1" when the tone pulse counter counts the number of tone pulses designated by the
tone count register and the decrement grade register.
This bit is reset to "0" when "0" is written to it. An attempt to write "1" to it fails. read-modify-write
(RMW) instructions always read "1" from this bit.
[bit0] ST: Start bit
This bit is used to start sound generator operation. While this bit is "1", the sound generator is operating.
If this bit is reset to "0", the sound generator will stop its operation when the current tone cycle ends.
The BUSY bit indicates whether the sound generator is completely inactive.
353
CHAPTER 19 SOUND GENERATOR
19.2.2
Amplitude Data Register
This section describes the functions of the amplitude data register.
■ Bit Configuration of Amplitude Data Register
Figure 19.2-3 shows the bit configuration in the amplitude data register.
Figure 19.2-3 Bit Configuration of Amplitude Data Register
SGAR
bit 15
Address: 000094H
D7
Read/Write (R/W)
Initial value
(0)
14
D6
(R/W)
(0)
13
D5
(R/W)
(0)
12
D4
(R/W)
(0)
11
D3
(R/W)
(0)
10
D2
(R/W)
(0)
9
D1
(R/W)
(0)
8
D0
(R/W)
(0)
The amplitude data register holds the reload value for the PWM pulse generator. The register value
represents the sound amplitude. Each time a tone cycle ends, the register value is reloaded to the PWM
pulse generator.
When the DEC bit of the SGCR register is "1" and the decrement counter reaches the reload value, the
value of this register is decremented by 1. Once the register value reaches "00H", it will no longer be
decremented. However, the sound generator continues to be active until the ST bit is cleared. Figure
19.2-4 shows how the register value relates to the PWM pulses.
Figure 19.2-4 Relationship between Register Values and PWM Pulses
1 PWM cycle
256 input clock cycles
Register value
00H
1 input clock cycle
B0H
128 input clock cycles
FEH
256 input clock cycles
FFH
256 input clock cycles
Note: If the register value is set to "FFH", the PWM signal is always "1".
354
CHAPTER 19 SOUND GENERATOR
19.2.3
Frequency Data Register
This section describes the functions of the frequency data register.
■ Bit Configuration of Frequency Data Register
Figure 19.2-5 shows the bit configuration in the frequency data register.
Figure 19.2-5 Bit Configuration of Frequency Data Register
SGFR
bit 7
Address: 000095H
D7
Read/Write (R/W)
Initial value
(X)
6
D6
(R/W)
(X)
5
D5
(R/W)
(X)
4
D4
(R/W)
(X)
3
D3
(R/W)
(X)
2
D2
(R/W)
(X)
1
D1
(R/W)
(X)
0
D0
(R/W)
(X)
The frequency data register holds the reload value for the frequency counter. The held value represents
the sound frequency (or the tone signal frequency from the toggle flip-flop). The register value is
reloaded to the counter each time the toggle signal changes.
Figure 19.2-6 shows how the register value relates to the tone signal.
Figure 19.2-6 Relationship between the Tone Signal and Register Values
1 tone cycle
Tone signal
(Register value +1) x
1 PWM cycle
(Register value +1) x
1 PWM cycle
Note:
Note that when the register value is changed during operation, the duty cycle of 50% may change
depending on the particular time of change.
355
CHAPTER 19 SOUND GENERATOR
19.2.4
Tone Count Register
This section describes the functions of the tone count register.
■ Bit Configuration of Tone Count Register
Figure 19.2-7 shows the bit configuration in the tone count register.
Figure 19.2-7 Bit Configuration of Tone Count Register
SGTR
bit 15
Address: 000096H
D7
Read/Write (R/W)
Initial value
(X)
14
D6
(R/W)
(X)
13
D5
(R/W)
(X)
12
D4
(R/W)
(X)
11
D3
(R/W)
(X)
10
D2
(R/W)
(X)
9
D1
(R/W)
(X)
8
D0
(R/W)
(X)
The tone count register holds the reload value for the tone pulse counter. The tone pulse counter retains
the cumulative number of tone pulses (or the number of decrement operations). When the reload value
is reached, the INT bit of the SGCR register is set. This arrangement is designed to reduce the number
of interrupt occurrences.
The count input for the tone pulse counter is connected to the carry-out signal from the decrement
counter. If the tone count register is set to "00H", it will set the INT bit of the SGCR register each time a
carry-out signal comes from the decrement counter. The cumulative number of tone pulses is
represented by the following formula:
((decrement grade register value) + 1) × ((tone count register value) + 1)
This means that if both registers are set to "00H", the INT bit of the SGCR register will be set each time
a tone cycle begins.
356
CHAPTER 19 SOUND GENERATOR
19.2.5
Decrement Grade Register
This section describes the functions of the decrement grade register.
■ Decrement Grade Register Functions
Figure 19.2-8 shows the bit configuration in the decrement grade register.
Figure 19.2-8 Bit Configuration of Decrement Grade Register
SGDR
bit 7
Address: 000097H
D7
Read/Write (R/W)
Initial value
(X)
6
D6
(R/W)
(X)
5
D5
(R/W)
(X)
4
D4
(R/W)
(X)
3
D3
(R/W)
(X)
2
D2
(R/W)
(X)
1
D1
(R/W)
(X)
0
D0
(R/W)
(X)
The decrement grade register holds the reload value for the decrement counter. This function is
designed to ensure that the value held in the amplitude data register will be automatically decremented.
If the DEC bit of the SGCR register is "1" and the decrement counter has reached the tone pulse count
reload value, the value held in the amplitude data register will be decremented by 1 when the current
tone cycle ends.
This operation ensures that automatic sound decrement can be achieved with a smaller number of CPU
interventions.
Note that the number of tone pulses determined by this register is "register value +1". If the decrement
grade register is set to "00H", decrement operation will be performed at each tone cycle.
357
CHAPTER 19 SOUND GENERATOR
19.2.6
Sound Disable Register
This section shows the bit configuration in the sound disable register.
■ Sound Disable Register Functions
Figure 19.2-9 shows the bit configuration in the sound disable register.
Figure 19.2-9 Bit Configuration of Sound Disable Register
SGDBL
bit 7
Address: 000091H
Read/Write
(-)
Initial value
(-)
6
(-)
(-)
5
(-)
(-)
4
(-)
(-)
3
(-)
(-)
2
(-)
(-)
1
(-)
(-)
0
DBL
(R/W)
(0)
[bit0]DBL:Sound disable
This bit is used to control the sound generator clock.
When "1" is written to this bit, the clock for the sound generator module is disabled. When "0" is set on
this bit, the clock is supplied to the sound generator module.
This bit is initialized to "0" at the time of reset. It can be read and a value can be written to it.
358
CHAPTER 20
REAL TIME CLOCK
This chapter outlines the real time clock and describes
its register configuration, functions and operations
20.1 Overview of Real Time Clock
20.2 Register of Real Time Clock
20.3 Real Time Clock Operation
359
CHAPTER 20 REAL TIME CLOCK
20.1
Overview of Real Time Clock
This section describes the overview and block diagram of the real time clock.
■ Overview of Real Time Clock
The real time clock (watch timer) is composed of a timer control register, subsecond register, second/
minute/hour register, 1/2 clock frequency divider, 21-bit prescaler, and second/minute/hour counter.
The operations of the real time clock are the same as the operations of the real-world timer and provide
real-world timer information.
■ Block Diagram of Real Time Clock
Figure 20.1-1 Block Diagram of Real Time Clock
Oscillation
clock
21-bit
prescaler
1/2 clock
divider
CO
EN
Subsecond
register
UPDT
ST
Second counter
CI
EN
LOAD
CO
6 bits
Minute counter
Hour counter
CO
6 bits
CO
5 bits
Second/minute/hour register
INTE0 INT0
INTE1 INT1
INTE2 INT2
INTE3 INT3
IRQ
The oscillation clock can select the main clock (4MHz) or the sub clock (32kHz) as the source clock for
RTC via the OSCCR register RTCSRC bit. For more information, see "■ OSCCR: Oscillation Control
Register" in Section "3.12.7 Detailed Description of Register of Clock Generation Control Unit".
360
CHAPTER 20 REAL TIME CLOCK
20.2
Register of Real Time Clock
This section describes the register function of the real time clock.
■ Register List of Real Time Clock
Figure 20.2-1 shows the register list.
Figure 20.2-1 Register List of Real Time Clock
Clock disable register (WTDBL)
bit
Address: 00000145H
7
6
5
4
3
2
1
0
Initial value
-
-
-
-
-
-
-
DBL
R/W
-------0B
Timer control register (WTCR)
bit
15
Address: 00000146H
INTE3
R/W
bit
Address: 00000147H
14
13
12
11
10
9
8
Initial value
INT3
R/W
INTE2
R/W
INT2
R/W
INTE1
R/W
INT1
R/W
INTE0
R/W
INT0
R/W
00000000B
Initial value
000-00-XB
7
6
5
4
3
2
1
0
TST2
R/W
TST1
R/W
TST0
R/W
-
RUN
R
UPDT
R/W
-
ST
R/W
Subsecond register (WTBR)
bit
Address: 00000149H
23
22
21
20
19
18
17
16
-
-
-
D20
R/W
D19
R/W
D18
R/W
D17
R/W
D16
R/W
bit
Address: 0000014AH
15
14
13
12
11
10
9
8
Initial value
bit
Address: 0000014BH
Initial value
---XXXXXB
D15
R/W
D14
R/W
D13
R/W
D12
R/W
D11
R/W
D10
R/W
D9
R/W
D8
R/W
XXXXXXXXB
7
6
5
4
3
2
1
0
Initial value
D7
R/W
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
R/W
XXXXXXXXB
15
14
13
12
11
10
9
8
-
-
S5
R/W
S4
R/W
S3
R/W
S2
R/W
S1
R/W
S0
R/W
Initial value
--XXXXXXB
7
6
5
4
3
2
1
0
Initial value
-
-
M5
R/W
M4
R/W
M3
R/W
M2
R/W
M1
R/W
M0
R/W
--XXXXXXB
15
14
13
12
11
10
9
8
-
-
-
H4
R/W
H3
R/W
H2
R/W
H1
R/W
H0
R/W
Initial value
---XXXXXB
Second register (WTSR)
bit
Address: 0000014EH
Minute register (WTMR)
bit
Address: 0000014DH
Hour register (WTHR)
bit
Address: 0000014CH
361
CHAPTER 20 REAL TIME CLOCK
■ Clock Disable Register (WTDBL)
Figure 20.2-2 Bit Configuration of Clock Disable Register (WTDBL)
bit
Address: 00000145H
7
6
5
4
3
2
1
0
Initial value
-
-
-
-
-
-
-
DBL
R/W
-------0B
[bit0] DBL: Clock disable
The RTC module clock is disabled when this bit is set to "1". Set this bit to "0" for normal operations.
This bit is initialized to "0". Read and write are possible.
■ Timer Control Register (WTCR)
Figure 20.2-3 Bit Configuration of Timer Control Register (WTCR)
bit
Address: 00000146H
15
14
13
12
11
10
9
8
Initial value
INTE3
R/W
INT3
R/W
INTE2
R/W
INT2
R/W
INTE1
R/W
INT1
R/W
INTE0
R/W
INT0
R/W
00000000B
bit
Address: 00000147H
7
6
5
4
3
2
1
0
Initial value
TST2
R/W
TST1
R/W
TST0
R/W
-
RUN
R
UPDT
R/W
-
ST
R/W
000-00-XB
[bit15 to bit8] INT3 to INT0, INTE3 to INTE0: Interrupt flag and interrupt enable flags
From INT0 to INT3 are interrupt flags. These flags are set by an overflow from the second counter,
minute counter and hour counter, respectively. If an INT bit is set when the corresponding INTE bit is
"1", the watch timer outputs an interrupt signal. The flag is set to output interrupt signals in second/
minute/hour units. When "0" is written into the INT bit the flag is cleared and the "1" write is disabled.
All read-modify-write (RMW) instructions operating in the INT bit read "1".
[bit7 to bit5] TST2 to TST0: Test bit
This bit is for device tests. It must be set to "000B" for all user applications.
[bit3] RUN: Flag
This bit can only read. When the read value is "1", this indicates that the RTC module is running.
[bit2] UPDT: Update bit
The UPDT bit is to update the values of the second/minute/hour counter.
Update data is written into the second/minute/hour register to update the counter value. Then the UPDT
bit is set to "1". The register value is (written) by the CO signal from the 21-bit prescaler and loaded into
the counter in the next cycle. The UPDT bit is reset by hardware when the counter value is updated.
However, the UPDT bit is not reset when a setting operation by software and a reset operation by
hardware are generated simultaneously.
Writing "0" into the UPDT bit is disabled. "0" is the read value in read-modify-write (RMW) instructions.
362
CHAPTER 20 REAL TIME CLOCK
[bit0] ST: Start bit
When the ST bit is set to "1", the watch timer loads the second/minute/hour value from the register and
starts operations. When it is reset to "0". the counter and prescaler are set completely to "0" and stop.
This bit can also be used to update the counter value. Set the ST bit to "0", wait until RUN becomes "0"
then update the counter value and set the ST bit to "1".
Note:
Please refer to section "20.3 Real Time Clock Operation" for the initial setting method.
It is recommended that the ST bit be used when changing the counter value.
When stopping the clock with the clock disable register (WTDBL) after changing the counter value
with the UPDT bit, read the hour/minute/second registers and check that the setting has been stored
before stopping the clock.
363
CHAPTER 20 REAL TIME CLOCK
■ Subsecond Register (WTBR)
Figure 20.2-4 Bit Configuration of Subsecond Register (WTBR)
bit
Address: 00000149H
bit
Address: 0000014AH
bit
Address: 0000014BH
23
22
21
20
19
18
17
16
Initial value
-
-
-
D20
R/W
D19
R/W
D18
R/W
D17
R/W
D16
R/W
---XXXXXB
15
14
13
12
11
10
9
8
Initial value
D15
R/W
D14
R/W
D13
R/W
D12
R/W
D11
R/W
D10
R/W
D9
R/W
D8
R/W
XXXXXXXXB
7
6
5
4
3
2
1
0
D7
R/W
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
R/W
Initial value
XXXXXXXXB
[bit23 to bit0] D23 to D0: Reload Data
The subsecond register stores the reload value of the 21-bit prescaler. This value is reloaded when the
reload counter becomes "0". When updating the entire 3 bytes, check that a reload has not been
performed between write instructions. Otherwise the 21-bit prescaler will combine old and new data
bytes and an incorrect value will be loaded. In general, it is recommended that the subsecond register be
updated while the ST bit is "0". 21-bit prescaler operations are stopped completely when the subsecond
register is set at "0".
Table 20.2-1 Subsecond Register Configuration Table
WTBR register value
Time
364
f =4MHz
f =32kHz
0.5μs
0
-
1μs
1
-
10μs
19
-
100μs
199
-
1ms
1999
15
10ms
19999
159
100ms
199999
1599
500ms
999999
7999
1s
1999999
15999
1.04s
2097151
16776.2
10s
-
159999
50s
-
799999
65.5s
-
1047999
CHAPTER 20 REAL TIME CLOCK
■ Second Register (WTBR)
Figure 20.2-5 Bit Configuration of Second Register (WTSR)
bit
Address: 0000014EH
15
14
13
12
11
10
9
8
Initial value
-
-
S5
R/W
S4
R/W
S3
R/W
S2
R/W
S1
R/W
S0
R/W
--XXXXXXB
Please refer to the "■Hour Register (WTHR)" for details.
■ Minute Register (WTMR)
Figure 20.2-6 Bit Configuration of Minute Register (WTMR)
bit
Address: 0000014DH
7
6
5
4
3
2
1
0
Initial value
-
-
M5
R/W
M4
R/W
M3
R/W
M2
R/W
M1
R/W
M0
R/W
--XXXXXXB
Please refer to the "■Hour Register (WTHR)" for details.
■ Hour Register (WTHR)
Figure 20.2-7 Bit Configuration of Hour Register (WTHR)
bit
Address: 0000014CH
15
14
13
12
11
10
9
8
Initial value
-
-
-
H4
R/W
H3
R/W
H2
R/W
H1
R/W
H0
R/W
---XXXXXB
The second/minute/hour register stores time information. Seconds, minutes and hours are shown in
binary.
Only the counter value is restored when this register is read. The register can combine with the write
value, however that write data is loaded into the counter after the UPDT bit has been set to "1".
As there are three byte registers, please check that there are no inconsistencies between the values
output from the registers. Namely it is possible that the output value [1hour, 59min, 59s] may be [0hour,
59min, 59s], [1hour, 0min, 0s] or [2hour, 0min, 0s].
Moreover, the read value from this register may be damaged when the MCU operation clock is half of
the oscillation clock (when PLL is stopped). This occurs due to synchronization adjustment of the read
operation and count operation. Accordingly, it is better to use a second interrupt as the read instruction
trigger.
Note:
In this module it is assumed the R-bus clock (CLKP) is not slow in comparison with the RTC clock
directly connected to the oscillator. If this is not the case, an undefined value will be read when the
register is accessed.
365
CHAPTER 20 REAL TIME CLOCK
20.3
Real Time Clock Operation
This section describes the real time clock operation.
■ Real Time Clock Operation
It is necessary to make the following configuration when starting RTC.
1)
Write "0" in WTDBL bit0.
2)
Write "1" in WTCR bit0 and the ST (Start) bit, and then write "0" in the ST bit.
3)
Write the initial value (any value) in WTBR.
4)
Write the initial value (any value) in each register of WTHR, WTMR, WTSR.
5)
Write "0" in the INT0 to INT3 bit in the WTCR register, and initialize the interrupt flag.
6)
Set INTE0 to INTE3 in the WTCR register.
Perform this setting when enabling interrupt notification.
7)
Write "1" in the WTCR ST bit and start RTC operations.
Note:
When it is necessary to access the RTC internal register, please access after writing "0" in WTDBL
bit0. If the access is performed when the status of the WTDBL bit0 is "1", an indeterminate value will
be read by a read, and the value written by a write will not be stored in the register.
The setting of the internal register is initialized by stopping RTC. Accordingly, when rebooting,
perform the necessary register setting and then set the WTCR: ST bit to "1".
The RTC counter is normally cleared by INITX/software reset, however the hour minute second
register is not cleared and the values are retained. Set the initial value by a write when clearing
register values at startup.
When using main clock RTC operations, set the clock source to 1/2 of the original oscillation input,
stop PLL, and then use the base clock division register 0, 1 (DIVR0, DIVR1) to set each clock of the
CPU clock (CLKB), peripheral clock (CLKP) and external interface clock (CLKT) to a division ratio of
8 or more divisions before making the transition to stop mode.
366
CHAPTER 21
UART
This chapter describes the overview of the UART, the
configuration and functions of registers, and UART
operation.
21.1 Overview of UART
21.2 Register of UART
21.3 Operation of UART
21.4 Application Example of UART
367
CHAPTER 21 UART
21.1
Overview of UART
UART is a serial I/O port that performs asynchronous (start- stop synchronization)
communication or CLK synchronous communication.
■ Features of UART
• Full-duplex buffer is supported.
• Asynchronous (start-stop synchronization) and CLK synchronous communications are possible.
• Multiprocessor mode is supported.
• Complete programmable baud rate: Any baud rate can be set with the built-in timer (see "CHAPTER 15
U-TIMER").
• Any baud rate can be freely set with external clocks.
• Error detection functions (parity, framing, and overrun) are provided.
• The transfer signal is the NRZ sign.
■ Block Diagram of UART
Figure 21.1-1 Block Diagram of UART
Control signal
U-Timer
External
clock
SC
Clock
selection
circuit
Reception interrupt
(To the CPU)
SC (clock)
Send clock
Transmit interrupt
(To the CPU)
Receive clock
SI (receive data)
Receive
control circuit
Send
control circuit
Start bit
detection circuit
Send start
circuit
Receive bit
detection circuit
Receive bit
counter
Receive parity
counter
Receive parity
counter
SO (send data)
Receive status
judgment circuit
Receive shifter
Send shifter
End of
receiving
DMA receive error
generation signal
SIDR
Start of
sending
SODR
(To DMAC)
R-bus
SMR
Register
MD1
MD0
CS0
SCKE
368
SCR
Register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR
Register
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
Control signal
CHAPTER 21 UART
21.2
Register of UART
This section explains the configuration and the function of the register used with UART.
■ Register List of UART
Figure 21.2-1 shows the register list.
Figure 21.2-1 Register List of UART
SMR
bit
Address: 000063H
Read/Write
Initial value
7
MD1
(R/W)
(0)
6
MD0
(R/W)
(0)
5
(-)
(-)
4
(-)
(-)
3
CS0
(W)
(0)
2
(-)
(-)
1
SCKE
(R/W)
(0)
0
(-)
(-)
15
PEN
(R/W)
(0)
14
P
(R/W)
(0)
13
SBL
(R/W)
(0)
12
CL
(R/W)
(0)
11
A/D
(R/W)
(0)
10
REC
(W)
(1)
9
RXE
(R/W)
(0)
8
TXE
(R/W)
(0)
7
D7
(R/W)
(X)
6
D6
(R/W)
(X)
5
D5
(R/W)
(X)
4
D4
(R/W)
(X)
3
D3
(R/W)
(X)
2
D2
(R/W)
(X)
1
D1
(R/W)
(X)
0
D0
(R/W)
(X)
15
PE
(R)
(0)
14
ORE
(R)
(0)
13
FRE
(R)
(0)
12
RDRF
(R)
(0)
11
TDRE
(R)
(1)
10
BDS
(R/W)
(0)
9
RIE
(R/W)
(0)
8
TIE
(R/W)
(0)
SCR
bit
Address: 000062H
Read/Write
Initial value
SIDR/SODR
bit
Address: 000061H
Read/Write
Initial value
SSR
bit
Address: 000060H
Read/Write
Initial value
■ Bit Configuration of Serial Mode Register (SMR)
Figure 21.2-2 Bit configuration of Serial Mode Register (SMR)
SMR
bit
Address: 000063H
Read/Write
Initial value
7
MD1
(R/W)
(0)
6
MD0
(R/W)
(0)
5
(-)
(-)
4
(-)
(-)
3
CS0
(W)
(0)
2
(-)
(-)
1
SCKE
(R/W)
(0)
0
(-)
(-)
SMR specifies the UART operation mode. Set the operation mode while operation stops. Do not write this
register during operation.
369
CHAPTER 21 UART
[bit7, bit6] MD1, MD0 (Mode Select)
Used to select the UART operation mode.
Mode
MD1
MD0
Operation mode
0
0
0
Asynchronous (start-stop synchronization) normal mode [Initial
value]
1
0
1
Asynchronous (start-stop synchronization) multiprocessor mode
2
1
0
CLK synchronous mode
-
1
1
Setting is prohibited.
Note: The CLK asynchronous mode (multiprocessor) in mode 1 indicates that a single host CPU connects
to several slave CPUs. This resource cannot recognize the format of receive data. Therefore, it
supports only the master in the multiprocessor mode. Moreover, the parity check function cannot be
used. So, set PEN of the SCR register to "0".
[bit5, bit4] (Reserved bits)
Always write "1" to this bit.
[bit3] CS0 (Clock Select)
Used to select the operating clock of UART.
0: Built-in timer (U-Timer) [Initial value]
1: External clock
Note: Bit3 of the serial mode register is used to switch internal and external baud rate clocks. This clock
switching influences UART immediately after a write to this bit3. So, write this bit while UART
stops.
[bit2] (Reserved bit)
Always write "0" to this bit.
[bit1] SCKE (SCLK Enable)
At CLK synchronous mode (mode 2) communication, this bit specifies whether the SCK pin is used as
the clock input or output.
In the CLK asynchronous mode or external clock mode, set this bit to "0".
0: Functions as the clock input pin. [Initial value]
1: Functions as the clock output pin.
Note: To use the SCK pin as the clock input, it is necessary to set the CS0 bit to "1" in advance to select the
external clock.
[bit0] (Reserved bit)
Always write "0" to this bit.
370
CHAPTER 21 UART
■ Bit Configuration of Serial Control Register (SCR)
Figure 21.2-3 Bit configuration of Serial Control Register (SCR)
SCR
bit
Address: 000062H
Read/Write
Initial value
15
PEN
(R/W)
(0)
14
P
(R/W)
(0)
13
SBL
(R/W)
(0)
12
CL
(R/W)
(0)
11
A/D
(R/W)
(0)
10
REC
(W)
(1)
9
RXE
(R/W)
(0)
8
TXE
(R/W)
(0)
SCR controls the transfer protocol used for serial communication.
[bit15] PEN (Parity Enable)
Used to specify whether to perform data communication with parity added during serial communication.
0: Without parity [Initial value]
1: With parity
Note: Parity can be added only in the normal mode (mode 0) of the asynchronous (start-stop synchronization)
communication mode. No parity can be added in the multiprocessor mode (mode 1) and CLK
synchronous communication (mode 2).
[bit14] P (Parity)
Used to specify odd/even parity when data communication is performed with parity added.
0: Even parity [Initial value]
1: Odd parity
[bit13] SBL (Stop bit Length)
Used to specify the bit length of the stop bit used as the frame end mark during asynchronous (start-stop
synchronization) communication.
0: One stop bit [Initial value]
1: Two stop bits
[bit12] CL (Character Length)
Used to specify the data length of one frame to be sent or received.
0: 7 bit data [Initial value]
1: 8 bit data
Note: 7 bit data can be manipulated only in the normal mode (mode 0) out of the asynchronous (start-stop
synchronization) communication modes. Use 8 bit data in the multiprocessor mode (mode 1) and
CLK synchronous communication mode (mode 2).
371
CHAPTER 21 UART
[bit11] A/D (Address/Data)
Used to specify the data format of the frame to be sent or received in the multiprocessor mode (mode 1)
of the asynchronous (start-stop synchronization) communication.
0: Data frame [Initial value]
1: Address frame
[bit10] REC (Receiver Error Clear)
Writing "0" to this bit clears the error flags (PE, ORE, and FRE) of the SSR register.
Writing "1" to this bit is invalid, and this bit is always "1" when read.
[bit9] RXE (Receiver Enable)
Controls the receive operation of UART.
0: Disables the receive operation. [Initial value]
1: Enables the receive operation.
Note: If the receive operation has been disabled during reception (when data is being input to the reception
shift register), the receive operation will stop when the reception of the relevant frame is completed
and when reception data is stored in the reception data buffer SIDR register.
[bit8] TXE (Transmitter Enable)
Controls the send operation of UART.
0: Disables the sending operation. [Initial value]
1: Enables the send operation.
Note: If the send operation has been disabled during sending (data is being output from the send register), it
will stop after the send data buffer SODR register runs out of data.
372
CHAPTER 21 UART
■ Serial Input Data Register (SIDR)/Serial Output Data Register (SODR)
Figure 21.2-4 Bit configuration of Serial Input Data Register (SIDR)/Serial Output Data Register (SODR)
SIDR
bit
Address: 000061H
Read/Write
Initial value
7
D7
(R)
(X)
6
D6
(R)
(X)
5
D5
(R)
(X)
4
D4
(R)
(X)
3
D3
(R)
(X)
2
D2
(R)
(X)
1
D1
(R)
(X)
0
D0
(R)
(X)
7
D7
(W)
(X)
6
D6
(W)
(X)
5
D5
(W)
(X)
4
D4
(W)
(X)
3
D3
(W)
(X)
2
D2
(W)
(X)
1
D1
(W)
(X)
0
D0
(W)
(X)
SODR
bit
Address: 000061H
Read/Write
Initial value
These registers are receive/send data buffer registers.
If the data length is 7 bits, data in bit7 (D7) is invalid. Write into the SODR register when TDRE of the
SSR register is "1".
Note:
Writing into this register means writing into the SODR register. Moreover, the read operation means
reading from the SIDR register.
373
CHAPTER 21 UART
■ Bit Configuration of Serial Status Register (SSR)
Figure 21.2-5 Bit configuration of Serial Status Register (SSR)
SSR
bit
Address: 000060H
Read/Write
Initial value
15
PE
(R)
(0)
14
ORE
(R)
(0)
13
FRE
(R)
(0)
12
RDRF
(R)
(0)
11
TDRE
(R)
(1)
10
BDS
(R/W)
(0)
9
RIE
(R/W)
(0)
8
TIE
(R/W)
(0)
[bit15] PE (Parity Error)
Used as the interrupt request flag that is set if a parity error occurs at reception.
To clear the flag once set, write "0" in the REC bit of the SCR register.
Once this bit is set, SIDR data is invalidated.
0: Without parity error [Initial value]
1: Parity error occurs
[bit14] ORE (Over Run Error)
Used as the interrupt request flag that is set if an overrun error occurs at reception.
To clear the flag once set, write "0" in the REC bit of the SCR register.
Once this bit is set, SIDR data is invalidated.
0: Without overrun error [Initial value]
1: Overrun error occurrence
[bit13] FRE (Framing Error)
Used as the interrupt request flag that is set if a framing error occurs at reception.
To clear the flag once set, write "0" in the REC bit of the SCR register.
Once this bit is set, SIDR data is invalidated.
0: Without framing error [Initial value]
1: Framing error occurrence
[bit12] RDRF (Receiver Data Register Full)
Used as the interrupt request flag that indicates that receive data exists in the SIDR register.
This bit is set when receive data is loaded in the SIDR register. This bit is automatically cleared when
the SIDR register is read.
0: Without receive data [Initial value]
1: With receive data
[bit11] TDRE (Transmitter Data Register Empty)
Used as the interrupt request flag that indicates that send data can be written in SODR.
This bit is cleared when send data is written in the SODR register. When written data is loaded to the
send shifter and transfer starts, this bit is set again to indicate that the next send data can be written into
SODR.
0: Disables send data writing.
1: Enables send data writing. [Initial value]
374
CHAPTER 21 UART
[bit10] BDS (Bit Direction Select)
Used to select a transfer direction.
0: Starts transfer from the least significant bit (LSB) side. [Initial value]
1: Starts transfer from the most significant bit (MSB) side.
Note: If this bit is changed after SIDR or SODR has been updated, the related data becomes invalid.
[bit9] RIE (Receiver Interrupt Enable)
Used to control a reception interrupt.
0: Disables an interrupt. [Initial value]
1: Enables an interrupt.
Note: The reception interrupt is caused by errors generated by PE, ORE, or FRE, in addition to by normal
reception by RDRF.
[bit8] TIE (Transmitter Interrupt Enable)
Used to control a transmit interrupt.
0: Disables an interrupt. [Initial value]
1: Enables an interrupt.
Note: A transmit interrupt is caused by a send request issued with TDRE.
375
CHAPTER 21 UART
21.3
Operation of UART
The UART has two operating modes: asynchronous (start-stop synchronization) mode
and clock synchronous mode.
Asynchronous mode consists of normal and multiprocessor mode.
This section describes the operation of these operating modes.
■ Operation Mode of UART
UART has the operation modes listed below. A mode can be switched by setting values in the SMR and
SCR registers.
Mode
Parity
Data length
Available or not
7
Available or not
8
0
Operation mode
Stop bit length
Asynchronous
(start-stop synchronization)
Normal mode
1 bit or 2 bits
1
Unavailable
8+1
2
Unavailable
8
Asynchronous
(start-stop synchronization)
Multiprocessor mode
CLK synchronous mode
None
However, the stop bit length in the asynchronous (start-stop synchronization) mode can be specified only
for the send operation. The 1 bit length is always used for the receive operation. Do not set UART in any
mode other than above because UART operates only in one of the above modes.
■ Selecting a UART Clock
● Internal Timer
If CS0 has been set to "0" to select U-Timer, a baud rate is determined with a reload value set in U-Timer.
The expression for calculating a baud rate is as follows:
Asynchronous (start-stop synchronization)
φ / (16 × β)
Clock synchronization
φ/β
φ : Peripheral machine clock frequency
β : Frequency set with U-Timer (2n+2 or 2n+3. n is a reload value).
Data can be transferred at the specified baud rate in the range from its -1% to +1% in the asynchronous
(start-stop synchronization) mode.
■ External Clock
If CS0 has been set to "1" to select the external clock, the baud rate will be obtained as shown below,
assuming that the external clock frequency is f.
Asynchronous (start-stop synchronization)
f/16
Clock synchronization
f
However, f can be up to 3.125MHz in maximum.
376
CHAPTER 21 UART
21.3.1
Asynchronous (Start-stop Synchronization) Mode
When used in operation mode 0 (normal mode) or operation mode 1 (multi-processor
mode), UART applies asynchronous transfer mode.
■ Transfer Data Format
UART handles only data having the NRZ (Non Return to Zero) format. The following shows the transfer
data format:
Figure 21.3-1 Transfer Data Format
S1,S0
0
1
Start LSB
0
1
1
0
0
1
0
1
1
MSB Stop
- - - - (Mode 0)
A/D Stop - - - - (Mode 1)
Transferred data is 01001101B
As shown in the figure above, transfer data surely begins with the start bit ("L" level data) and data is
transferred based on the data bit length specified in the LSB first. The transfer data ends with the stop bit
("H" level data).
If you have selected the external clock, always input clocks.
Normal mode (mode 0) enables a data length to be set to seven or eight bits. However, the multiprocessor
mode (mode 1) must use eight bits. Moreover, no parity can be added in the multiprocessor mode. Instead,
the A/D bit is surely added.
■ Receive Operation
If the SCR register's RXE bit (bit1) is "1", receive operation is always performed.
If the start bit appears in the reception line, one-frame data is received according to the data format
specified by the SCR register. When the one-frame data reception ends, if an error occurs, the error flag
will be set and then the RDRF flag (SSR register's bit4) will be set. In this case, if the same SSR register's
RIE bit (bit1) is set to "1", a reception interrupt will occur for the CPU. Check the flags of the SSR register.
When data reception is normal, read the SIDR register. If an error is occurring, take appropriate action on
it.
The RDRF flag is cleared when the SIDR register is read.
■ Send Operation
If the SSR register's TDRE flag (bit3) is "1", send data is written in the SODR register. Here, data will be
sent if the SCR register's TXE bit (bit0) is "1".
When the data set in the SODR register is loaded to the send shift register and transmission starts, the
TDRE flag is set again to enable the next send data to be set. In this case, if the same SSR register's TIE bit
(bit0) is "1", a send interrupt will occur for the CPU to request the CPU to set send data in the SODR
register.
The TDRE flag will be once cleared if data is set in the SODR register.
377
CHAPTER 21 UART
21.3.2
Clock Synchronous Mode
When used in operation mode 2, UART applies clock synchronous transfer mode.
■ Transfer Data Format
UART handles only data having the NRZ (Non Return to Zero) format. The following shows the
relationship between sending and receiving clocks and data format:
Figure 21.3-2 Transfer Data Format
SODR writing
Mark
SC
RXE, TXE
S1, S0
1
LSB
0
1
1
0
0
1
0
MSB
- - - - (Mode 2)
Transferred data is 01001101B
If the internal clock (U-Timer) has been selected and if data is sent, the data reception synchronous clock
will be automatically generated.
If the external clock has been selected, confirm that the send data buffer SODR register of the sending-end
UART contains data (TDRE flag is "0"). Then, the clocks for one byte must be supplied accurately. Be sure
to set the data line at the mark level before the start of sending and after the end of sending.
The data length is only 8 bits and no parity can be added. Moreover, no start/stop bits are provided, only an
overrun error is detected.
378
CHAPTER 21 UART
■ Initialization
The following lists the configuration of the control registers when the CLK synchronous mode is used:
(1) SMR register
MD1, MD0
: "10B"
CS
: Specifies the clock input.
SCKE
: For the internal timer, set "1". For the external clock, set "0".
SOE
: For sending, set "1". For receiving only, set "0".
(2) SCR register
PEN
: "0"
P, SBL, A/D
: These bits have no effect.
CL
: "1"
REC
: "0" (for initialization)
RXE,TXE
: Set at least one of them to "1"
(3) SSR register
RIE
: To use an interrupt, set "1", To cancel an interrupt, set "0"
TIE
: "0"
■ Start of Sending
Communication starts when the SODR register is written. For receiving only, be sure to write tentative
send data in the SODR register.
■ End of Sending
You can confirm the end of sending when the RDRF flag of the SSR register has been changed to "1".
From the ORE bit of the SSR register, confirm that communication has been normally performed.
379
CHAPTER 21 UART
21.3.3
Interrupt Generation and Flag Set Timings
This section describes the interrupt generation and flag set timings.
UART has the five flags and two interrupt factors.
Five flags are PE, ORE, FRE, RDRF, and TDRE. For the meanings of the flags, see the explanation of
"■Bit Configuration of Serial Status Register (SSR)" in Section "21.2 Register of UART ".
PE, ORE, and FRE are set if a receive error has occurred. These flags are cleared when "0" is written in
REC of the SCR register.
RDRF is set when receive data is loaded in the SIDR register. It is cleared when the SIDR register is read.
However, mode 1 has no parity detection function; mode 2 has neither the parity detection function nor
framing error detection function. TDRE is set when the SODR register becomes empty and writable. It is
cleared when the SODR register is written.
Interrupts are caused by send and receive flags. During receiving, interrupts are requested with PE/ORE/
FRE/RDRF. During sending, interrupts are requested with TDRE. The subsequent subsections explain the
interrupt flag set timings in each operation mode.
● Receive Operation in Mode 0
PE, ORE, FRE, and RDRF are set when the receive operation ends and the last stop bit is detected. With
this, an interrupt request is issued to the CPU. While PE, ORE, and FRE are active, SIDR data is invalid.
Figure 21.3-3 ORE, FRE, and RDRF Set Timings (Mode 0)
Data
D6
D7
Stop
PE, ORE, FRE
RDRF
Reception interrupt
● Receive Operation in Mode 1
ORE, FRE, and RDRF are set when the receive transfer ends and the last stop bit is detected. With this, an
interrupt request is issued to the CPU. Since the receivable data length is 8 bits, the data in the last 9th bit
indicating an address or data is invalid. While ORE and FRE are active, SIDR data is invalid.
380
CHAPTER 21 UART
Figure 21.3-4 ORE, FRE, and RDRF Set Timings (Mode 1)
Data
D7
address/data
Stop
ORE, FRE
RDRF
Reception interrupt
● Receive Operation in Mode 2
ORE and RDRF are set when the receive operation ends and the last data (D7) is detected. With this, an
interrupt request is issued to the CPU. While ORE is active, SIDR data is invalid.
Figure 21.3-5 ORE and RDRF Set Timings
Data
D5
D6
D7
ORE
RDRF
Reception interrupt
● Send Operations in Modes 0, 1, and 2
TDRE is cleared when the SODR register is written. It is set when data is transferred to the internal shift
register and the next data is ready to be written. With this, an interrupt request is issued to the CPU.
Suppose that "0" (RXE is also included in mode 2) is written in TXT of the SCR register during send
operation. In this case, TDRE of the SSR register is set to "1", and the send operation of UART is disabled
after the send shifter stops. Suppose that TXT of the SCR register has been written with "0" (RXE is also
included in mode 2) during send operation. In this case, the data written in the SODR register is sent before
the send operation stops.
381
CHAPTER 21 UART
Figure 21.3-6 TDRE Set Timing (Modes 0 and 1)
SODR writing
TDRE
An interrupt to the CPU is
requested.
SO interrupt
ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3
A/D
SO output
ST
: Start bit
D7 to D0 : Data bits
SP
: Stop bit
A/D
: Address/data multiplexer
Figure 21.3-7 TDRE Set Timing Mode (Mode 2)
SODR writing
TDRE
SO interrupt
SO output
An interrupt to the CPU is
requested.
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
D7 to D0: Data bits
■ Warning On Use
Set the communication mode while operation stops. The data sent or received during mode setting is not
guaranteed.
382
CHAPTER 21 UART
21.4
Application Example of UART
This section describes application example of the mode 1 of UART.
Mode 1 is used when one host CPU connects to two or more slave CPUs. This resource
supports only the host-side communication interface.
■ Application Example of UART
Figure 21.4-1 Example of System Construction in Mode 1
SO
SI
Host CPU
SO SI
Slave CPU#0
SO
SI
Slave CPU#1
Communication begins when the host CPU transfers address data. Address data is the one used when A/D
of the SCR register is "1". With this, a slave CPU used as the communication destination is selected to
enable communication with the host CPU. Usual data is the one used when A/D of the SCR register is "0".
The related flowchart is shown below.
In this mode, the parity check function cannot be used. So, set the PEN bit of the SCR register to "0".
383
CHAPTER 21 UART
Figure 21.4-2 Flowchart for Mode 1
(Host CPU)
START
Set transfer mode
to "1"
Set data to D0 to D7 to
select slave CPU and set
"1" to A/D for one-byte
transfer
Set "0" to A/D
Receive operation
is enabled
Communication with
slave CPU
Communication
completed?
NO
YES
Communication
completed?
NO
YES
Receive operation is
disabled
END
384
CHAPTER 22
LIN-UART
This chapter describes the overview of the LIN-UART,
the configuration and functions of registers, and LINUART operation.
22.1 Overview of LIN-UART
22.2 Register List of LIN-UART
22.3 Detecting Baud Rates with the Input Capture
22.4 Operation of LIN-UART
22.5 UART Interrupts
22.6 Clock Synchronization of LIN-UART
22.7 Flag Set Timing
22.8 Special Specifications of LIN-UART
22.9 LIN Communication Operation
22.10 Overview of Changes from Normal UART
22.11 Restrictions
385
CHAPTER 22 LIN-UART
22.1
Overview of LIN-UART
This section describes the overview and block diagram of the LIN-UART.
■ Overview of LIN-UART
LIN (Local Interconnect Network)-UART is a general-purpose serial data communication interface
used for asynchronous and synchronous communications with external devices. This interface provides
the bidirectional communication function (normal mode), master/slave communication function
(multiprocessor mode), and the LIN-bus system (master /slave operation).
LIN-UART is similar to ordinary UART; however, no software compatibility exists between them.
Table 22.1-1 Functions of UART
Item
Function
Data buffer
Full-duplex buffer
Serial input
5-time oversampling (asynchronous mode only)
Transfer mode
• CLK synchronous communication (start/stop synchronization, start-stop bit selection)
• CLK asynchronous (use of the start and stop bits)
Baud rate
• Dedicated baud rate generator (consisting of the 15-bit reload counter)
• An external clock can be entered. Moreover, it is adjustable with the reload counter.
Data length
• 7 bits (not in synchronous or LIN mode)
• 8 bits
Signal mode
NRZ (Non Return to Zero) and RZ (Return to Zero)
Start-bit timing
Synchronization with the start-bit falling edge in the asynchronous mode
Receive error detection
• Framing error
• Overrun error
• Parity error
Interrupt request
•
•
•
•
Master-slave communication
function (Multiprocessor mode)
1 (master) to N (slaves) communication is possible.
(This function is supported for both master and slave systems).
Synchronous mode
Master or slave function
Pin access
Direct read of serial input-output pin status is possible
LIN bus option
•
•
•
•
•
Synchronous serial clock
Clock output is continuously possible to the SCK pin for synchronous communication with the start/
stop bits.
386
Reception interrupt (reception completion, reception error detection)
Transmit interrupt (transmit completion)
Bus idle interrupt
LIN synch field detection interrupt
Master device operation
Slave device operation
LIN Synch break generation
LIN Synch break detection
Detection of the start /stop edges of the LIN Synch field connected to the capture
CHAPTER 22 LIN-UART
■ LIN-UART Block Diagrams
Figure 22.1-1 LIN-UART Block Diagrams
(OTO),
EXT,
REST)
CLK
PE
ORE FRE
TIE
RIE
LBIE
LBD
BIE
RBI
TBI
Transmision clock TRCK
Reload
Counter
SCK
Reception clock RSCK
Pin
Interrupt
Generation
circuit
TRANSMISSION
CONTROL
CIRCUIT
TRANSMISSION
CONTROL CIRCUIT
Start bit
Detection
Transmission
Start circuit
Received
Bit counter
Transmission
Bit counter
Received
Parity counter
Transmission
Parity counter
reception
IRQ
SEDGE
SIN
IN
Pin
(from ECCR)
transm.
IRQ
TDRE
SOUT
Oversampling
Unit
Pin
INV
RDRF
reception
complete
SCU
SIN
LSYN
(to ICU)
LIN break
and Synch
Field
Detection
circuit
SIN
Reception
shift register
Transmission
shift register
transmission
start
Bus idle
Detection
circuit
Error
Detection
STR
(to El2OS)
RE
ORE
FRE
LIN
bread
generation
RDR
LBR
LBL1
LBLD
TDR
RBI
LB
TBI
Internal data bus
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
SSR
register
MD1
MD0
OTO
EXT
REST
UPCL
SCKE
SOE
SMR
register
PEN
P
SBL
CL
A/D
CRE
RXE
TXE
SCR
register
LBIE
LBD
LBL1
LBL0
SOPE
SIOP
CCO
SCES
INV
LBR
MS
ESCR
register
Reserved
bit
SSM
BIE
RBI
TBI
ECCR
register
387
CHAPTER 22 LIN-UART
22.2
Register List of LIN-UART
This section describes the register function.
■ Register List of LIN-UART
MB91245/S series consist of three LIN-UARTs named "LIN-UART0", "LIN-UART1", and "LINUART2". LIN-UART0 connects to SIN3, SCK3, and SOT3 pins; LIN-UART1 to SIN4, SCK4, and
SOT4 pins; and LIN-UART2 through SIN5, SCK5, and SOT5 pins.
LIN-UART consists of the following registers:
LIN-UART0
Address
+0
+1
0000B0H
SCR3 (serial control register)
SMR3 (serial mode register)
0000B2H
SSR3 (serial status register)
RDR3/TDR3 (receive data/send data register)
0000B4H
ESCR3 (extended status control register)
ECCR3 (extended communication control register)
0000B6H
BGR13 (baud rate generator register 1)
BGR03 (baud rate generator register 0)
+0
+1
SCR4 (serial control register)
SMR4 (serial mode register)
SSR4 (serial status register)
RDR4/TDR4
(receive data/send data register)
0000BCH
ESCR4 (extended status control register)
ECCR4 (extended communication control register)
0000BEH
BGR14 (baud rate generator register 1)
BGR04 (baud rate generator register 0)
+0
+1
0000C0H
SCR5 (serial control register)
SMR5 (serial mode register)
0000C2H
SSR5 (serial status register)
RDR5/TDR5 (receive data/send data register)
0000C4H
ESCR5 (extended status control register)
ECCR5 (extended communication control register)
0000C6H
BGR15 (baud rate generator register 1)
BGR05 (baud rate generator register 0)
LIN-UART1
Address
0000B8H
0000BAH
LIN-UART2
Address
388
CHAPTER 22 LIN-UART
■ Serial Control Register (SCR)
Figure 22.2-1 Bit Configuration of Serial Control Register (SCR)
Initial value
bit 15 14 13 12 11 10 9
8
Address:
ch.3 0000B0H
ch.4 0000B8H
ch.5 0000C0H R/W R/W R/W R/W R/W R/W R/W R/W
00000000 B
bit8
TXE
0
1
Transmission enable
Disable Transmission
Enable Transmission
bit9
RXE
0
1
Reception enable
Disable Reception
Enable Reception
bit10
Clear Reception errors
Write
Read
CRE*1
0
1
ignored
Clear all reception errors
(PE,FRE, ORE)
always "0"
bit11
A/D
0
1
Read
Received data
bit
Received
address bit
Address/Data bit
Write
RMW-Read
Write data bit
to be sent
Write address
bit to be sent
Read data bit
to be sent
Read address
bit to be sent
bit12
Character (Data frame) Length
CL*2
7 bits
0
8 bits
1
bit13
SBL*3
1 stop bit
0
2 stop bits
1
Stop bit length
bit14
Parity setting
P
Even Parity enabled
0
Odd Parity enabled
1
R/W
:
Readable and writable
:
Initial value
bit15
Parity Enable
PEN*4
Parity disabled
0
Parity enabled
1
*1: If the receive error flag has been cleared, the state machine limited to reception will be reset. So, it is ready to detect a
new start bit (new data frame for mode 2).
When the reception error flag is cleared without disabling the reception, the reception is interrupted once at that timing
and then it restarts. Therefore, when the reception is restarted, Incorrect data might be received.
*2: In mode 2 and mode 3 (LIN mode), the data length is fixed to 8 bit. So, in these modes, writing "0" to this bit has no
effect on the operation.
*3: In mode 3 (LIN mode), the stop bit length is fixed to 1 bit. So, in this mode, writing "1" to this bit has no effect on the
operation.
*4: The parity bit is added in mode 0 and is added when the start /stop enable bit (SSM) of the extended communication
control register (ECCR) is valid in mode 2. In all other configuration, writing "1" in this bit has no effect on the
operation.
389
CHAPTER 22 LIN-UART
■ Serial Mode Register (SMR)
Figure 22.2-2 Bit Configuration of Serial Mode Register (SMR)
bit
Address:
ch.3 0000B1H
ch.4 0000B9H
ch.5 0000C1H
7
6
5
4
3
2
1
0
Initial value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
bit0
SOE
0
1
Serial Output enable
disable SOT3 pin (Hi-Z)
enable SOT3 pin (Tx Data)
bit1
SCKE
Serial Clock Output enable
0
External Serial Clock Input
1
Internal Serial Clock Output
bit2
UPCL
0
1
UAERT programmable clear (Software Reset)
write
ignored
Reset UART
read
always "0"
bit3
REST
0
1
bit4
EXT
0
1
bit5
OTO
0
1
R/W
390
:
Readable and writable
:
Initial value
bit6
MD0
0
1
0
1
Restart dedicated Reload Counter
write
read
ignored
always "0"
Restart Countier
External Serial Clock Source enable
Use internal Baud Rate Generator (Reload Counter)
Use external Serial Clock Source
One-to one external clock Input enable
Use ext. with Baud Rate Generator (Reload C)
Use external Clock as is
bit7
MD1
0
0
1
1
Operation Mode Setting
Mode 0 : Asynchronous normal
Mode 1 : Asynchronous Multiprocessor
Mode 2 : Synchronous
Mode 3 : Asynchronous LIN
CHAPTER 22 LIN-UART
■ Serial Status Register (SSR)
Figure 22.2-3 Bit Configuration of Serial Status Register (SSR)
Address:
ch.3 0000B2H
ch.4 0000BAH
ch.5 0000C2H
bit 15
14 13 12
11 10
9
Initial value
8
00001000 B
R
R
R
R
R R/W R/W R/W
bit8
TIE
0
1
bit9
RIE
0
1
Transmission Interup enable
Disables Transmission Interrupt
Enables Transmission Interrupt
Reception Interrupt enable
Disables Reception Interrupt
Enables Reception Interrupt
bit10
BDS*
Bit direction setting
0
send/receive LSB first
1
send/receive MSB first
bit11
TDRE
Transmission data register empty
0
Transmission data register is full
1
Transmission data register is empty
bit12
Reception data register full
RDRF
Reception data register is empty
0
Reception data register is full
1
bit13
Framing error
FRE
No framing error occurred
0
A framing error occurred during reception
1
bit14
Overun error
ORE
No overrun error occurred
0
An overrun error occurred during reception
1
R/W
R
:
:
Readable and writable
Read only
:
Initial value
bit15
Parity error
PE
No parity error occurred
0
A parity error occurred during reception
1
*: In mode 3 (LIN mode), the BDS bit is fixed to "0". So, writing "1" to this bit in this mode has no effect on the operation.
391
CHAPTER 22 LIN-UART
■ Receive Data Register (RDR) and Send Data Register (TDR)
Figure 22.2-4 Bit Configuration of Receive Data Register (RDR) and Send Data Register (TDR)
bit 7
Address:
ch.3 0000B3H
ch.4 0000BBH
ch.5 0000C3H
6
5
4
3
2
1
0
Initial value
RDR: 00000000 B
TDR : 11111111B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
Read
Write
R/W
392
:
Readable and writable
Data Registers
Read from Reception Data Register
Write to Transmission Data Register
CHAPTER 22 LIN-UART
■ Extended Status Control Register (ESCR)
Figure 22.2-5 Bit Configuration of Extended Status Control Register (ESCR)
Initial value
bit 15 14 13 12 11 10 9
8
Address:
ch.3 0000B4H
ch.4 0000BCH
ch.5 0000C4H R/W R/W R/W R/W R/W R/W R/W R/W
00000X00 B
bit8
SCES Sampling Clock Edge Selection (Mode 2)
Sampling on rising clock edge (normal)
0
Sampling on falling clock edge (inverted clock)
1
bit9
CCO Continuous Clock Output (Mode 2)
Coutinuous Clock Output disabled
0
Coutinuous Clock Output enabled
1
bit10
SIOP
0
1
Serial Input / Output Pin Access
Write (if SOPE=1)
read
SOT3 is forced to "0" reading the actual
SOT3 is forced to "1" value of SIN3
bit11
SOPE
Enable Serial Output pin direct Access
0
Serial Output pin direct access disable
1
Serial Output pin direct access enable
bit12
LBL0
0
1
0
1
bit13
LBL1
0
0
1
1
LIN break length
LIN break length 13 bit times
LIN break length 14 bit times
LIN break length 15 bit times
LIN break length 16 bit times
bit14
LBD
1
0
LIN break detected
Write
read
ignored
LIN break detected
Clear LIN break
No LIN break detected
detected flag
bit15
LIN break detection Interrupt enable
LBIE
LIN break interrupt disable
0
LIN break interrupt enable
1
R/W
X
:
:
:
Readable and writable
Undefined
Initial value
Table 22.2-1 Explanation of Interaction between SOPE and SIOP
SOPE
SIOP
0
R
1
R/W
Writing to SIOP
Reading from SIOP
No effect
SIN value is returned.
Writing "0" or "1" to SOUT
SIN value is returned.
If SOPE is "1", the initial value of SIOP is "1".
If the read-modify-write (RMW) cycle is active, SIOP returns a value of the serial output pin (SOUT) in
the read cycle.
393
CHAPTER 22 LIN-UART
■ Extended Communication Control Register (ECCR)
Figure 22.2-6 Bit Configuration of Extended Communication Control Register (ECCR)
Address:
ch.3 0000B5H
ch.4 0000BDH
ch.5 0000C5H
bit 7
6
5
4
3
2
1
Initial value
0
000000XX B
-
W R/W R/W R/W R/W R
R
bit0
TBI
0
1
bit1
RBI
0
1
bit2
BIE
0
1
bit3
SSM
0
1
Transmission bus idle
Transmission is ongoing
no transmission activity
Reception bus idle
Reception is ongoing
no reception activity
Bus idle interrupt enable
disable Bus idle interrupt
enable Bus idle interrupt
Synchronous start/stop bits in mode2
No start/stop bits in synchronous mode2
Enable start/stop bits in synchronous model2
bit4
Reserved bit : This bit must be set to "0"
bit5
MS
0
1
Master/Slave function in mode 2
Master mode (generating serial clock)
Slave mode (receiving external serial clock)
bit6
LBR
0
1
R/W
R
W
X
394
:
:
:
:
:
Readable and writable
Read only
Write only
Undefined
Initial value
bit7
INV
0
1
Set LIN break
write
read
ignored
always read "0"
Generate LIN break
Invert Serial Data Format
Data format NRZ
Data format RZ
CHAPTER 22 LIN-UART
22.2.1
Baud Rate / Reload Counter Register (BGR)
The baud rate / reload counter register (BGR) sets the division ratio of the serial clock.
It can also read the correct value from the transmission reload counter.
■ Baud Rate / Reload Counter Register (BGR)
This register can be read and written using byte access or half word access.
Figure 22.2-7 Baud Rate / Reload Counter Register
BGR1
Address:
bit
0000B6H
0000BEH
0000C6H
Read/Write
Initial Value
15
-
(-)
(0)
14
B14
13
B13
12
B12
11
B11
10
B10
9
B09
8
B08
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
BGR0
Address:
bit
7
6
5
4
3
2
1
0
0000B7H
B07
B06
B05
B04
B03
B02
B01
B00
0000BFH
0000C7H
Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial Value (0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
[bit15] (Reserved bit)
This bit is reserved. Reading it always returns "0".
[bit14 to bit8] B14 to B08: Baud rate generator register 1
BGR1
Baud rate generator register 1
Write
Writes the reload value set in bits 14 to 8 to the counter
Read
Reads counter bits 14 to 8
[bit7 to bit0] B07 to B00: Baud rate generator register 0
BGR0
Baud rate generator register 0
Write
Writes the reload value set in bits 7 to 0 to the counter
Read
Reads counter bits 7 to 0
395
CHAPTER 22 LIN-UART
22.3
Detecting Baud Rates with the Input Capture
This section describes the detecting baud rates with the input capture.
■ Detecting Baud Rates with the Input Capture
LIN-UART has LSYN signals and is connected to the ICU (input capture). The baud rates can be
adjusted in ICU by measuring pulse lengths of LSYN. The connection of ICUs and LSYN signals is
controlled with the port D function register PFRD (address 0000042DH, bits PFRD[2:0]).
Pin IN0
0
1
LIN-UART0
LSYN
IN
ICU0
S
FREE RUN TIMER0
PFRD[0]
Pin IN1
0
1
LIN-UART1
LSYN
IN
ICU1
S
FREE RUN TIMER1
PFRD[1]
0
Pin IN2
1
LIN-UART2
LSYN
IN
ICU2
S
FREE RUN TIMER2
PFRD[2]
If the PRF bit is set, ICU is connected to input pin IN.
Clearing the PFR bit causes the IN pin to enter the port mode (Port D[2:0]), enabling LIN-UART to be
connected to ICU.
396
CHAPTER 22 LIN-UART
22.3.1
Baud Rate for UART
One of the following can be selected as the serial clock for UART.
• Dedicated baud rate generator (reload counter)
• External clock (clock input from the SCK pin)
• External clock used as the baud rate generator (reload counter)
■ Selecting Baud Rate for UART
Figure 22.3-1 shows the baud rate selection circuit. The baud rate can be selected from the following three
options.
● Dedicated baud rate generator (reload counter)
UART has separate reload counters for each transmission/reception serial clock. The baud rate is set
using the 15-bit reload value contained in the baud rate generator register (BGR).
The reload counter uses the value set in the baud rate generator register to divide the machine clock.
● External clock (clock input from the SCK pin)
The clock input form the UART clock input pin (SCK) is used directly as the baud rate.
● External clock used as the baud rate generator (reload counter)
An external clock can also be connected to the reload counter within the device. In this mode, such
clock will be used to replace the internal machine clock.
Figure 22.3-1 Baud Rate Selection Circuit (Reload Counter)
REST
Start bit falling
edge detected
Reload Value:v
Rxc = 0?
set
Reception
15-bit Reload Counter
Reload
F/F
reset
Rxc = v/2?
0
1
Reload Value:v
CLK
0
SCK
(external
clock
input)
1
Reception
Clock
EXT
Txc = 0?
set
OTO
Transmission
15-bit Reload Counter
F/F
Reload
1
reset
Txc = v/2?
0
Transmission
Clock
Count Value: Txc
Internal data bus
EXT
REST
OTO
SMR
register
BGR14
BGR13
BGR12
BGR11
BGR10
BGR9
BGR8
BGR1
register
BGR7
BGR6
BGR5
BGR4
BGR3
BGR2
BGR1
BGR0
BGR0
register
397
CHAPTER 22 LIN-UART
22.3.2
Setting Baud Rate
This section explains how to set the baud rate and the calculation results of serial clock
frequencies.
■ Calculating Baud Rate
The baud rate generator register (BGR) is used to set the 15-bit reload counter.
Use the following formula to calculate the baud rate.
v= [ φ /b] - 1
Above, "φ" represents the machine clock frequency and "b" the baud rate.
● Calculation example
When the machine clock is 16 MHz and the target baud rate is 19200 bps, the reload value "v" can be
calculated as shown below:
v= [16× 106 / 19200] - 1 = 832
To achieve the accurate baud rate, recalculate it as follows:
bexact= φ /(v+1)=16× 106 / 833= 19207.6831 bps
Note:
When the reload value is set to "0", the reload counter stops. Therefore, the minimum division ratio is
2 divisions.
398
CHAPTER 22 LIN-UART
■ Example Baud Rate Setting for Each Machine Clock Frequency
Table 22.3-1 shows an example baud rate setting for each machine clock frequency.
Table 22.3-1 Example Baud Rate Setting for Each Machine Clock Frequency
Baud Rates
(bps)
8MHz
16MHz
20MHz
24MHz
32MHz
value
dev.
value
dev.
value
dev.
value
dev.
value
dev.
4M
-
-
-
-
4
0
5
0
7
0
2M
-
-
7
0
9
0
11
0
15
0
1M
7
0
15
0
19
0
23
0
31
0
500000
15
0
31
0
39
0
47
0
63
0
460800
-
-
-
-
-
-
51
-0.16
68
-0.64
250000
31
0
63
0
79
0
95
0
127
0
230400
-
-
-
-
-
-
103
-0.16
138
0.08
153600
51
-0.16
103
-0.16
129
-0.16
155
-0.16
207
-0.16
125000
63
0
127
0
159
0
191
0
255
0
115200
68
-0.64
138
0.08
173
0.22
207
-0.16
277
0.08
76800
103
-0.16
207
-0.16
259
-0.16
311
-0.16
416
0.08
57600
138
0.08
277
0.08
346
-0.06
416
0.08
555
0.08
38400
207
-0.16
416
0.08
520
0.03
624
0
832
-0.04
28800
277
0.08
554
-0.01
693
-0.06
832
-0.03
1110
-0.01
19200
416
0.08
832
-0.03
1041
0.03
1249
0
1666
0.02
10417
767
0
1535
0
1919
0
2303
0
3071
0
9600
832
-0.04
1666
0.02
2083
0.03
2499
0
3332
-0.01
7200
1110
-0.01
2221
-0.01
2777
0.011
3332
-0.01
4443
-0.01
4800
1666
0.02
3332
-0.01
4166
0.01
4999
0
6666
0
2400
3332
-0.01
6666
0
8332
0
9999
0
13332
0
1200
6666
0
13332
0
16666
0
19999
0
26666
0
600
13332
0
26666
0
-
-
-
-
-
-
300
26666
0
-
-
-
-
-
-
-
-
Note:
dev. : deviation unit (signal)
Deviation unit: Percent (%)
The maximum synchronous baud rate is 5 divisions of machine clock.
399
CHAPTER 22 LIN-UART
■ Using External Clock
When the EXT bit in SMR is set, the external pin SCK is selected as the clock. The external clock
signal is handled in the same way as the MCU clock signal. It is designed to connect a 1.8432MHz
crystal oscillator to the SCK pin, for example, and use the reload counter to select all the baud rates for
PC-16550-UART.
When the "1 to 1" external clock input mode (OTO bit in SMR) is selected, the SCK signal is connected
directly to the UART serial clock input. This is necessary to operate the unit as a slave device in UART
synchronous mode 2.
Note:
In any case, the clock signal is synchronized with the MCU clock signal in the UART. This means
that any undividable clock ratio will result in unstable signal generation.
■ Example Count
Figure 22.3-2 shows an example of transmission/reception reload counter operation. In the example, the
reload value is 832.
Figure 22.3-2 Example Count for Reload Counter
Transmission/
Reception Clock
Reload
counter
001
000
832
831
830
829
828
827
412
411
410
Reload Count value
Transmission/
Reception Clock
Reload
counter
417
416
415
414
413
Note:
The falling edge of the serial clock signal always occurs after [(v + 1)/2].
400
CHAPTER 22 LIN-UART
22.4
Operation of LIN-UART
This section describes the operation of LIN-UART.
■ Operation Mode of LIN-UART
LIN-UART operates in four different operation modes as listed below. The operation mode to be used
depends on the MD0 and MD1 bits of the serial mode register (SMR). Modes 0 and 2 are used for
bidirectional serial communication; mode 1 for the master/slave communication; and mode 3 for the
LIN master/slave communication.
Data length
Operation mode
Parity disabled
0
Normal mode
1
Multiprocessor
2
Normal mode
3
LIN mode
Parity enabled
7 bits or 8 bits
7 bits or
8 bits+1*2
8 bits
8 bits
-
Synchronous
mode
Stop bit length
Data bit direction*1
Asynchronous
1 bit or 2 bits
L/M
Asynchronous
1 bit or 2 bits
L/M
Synchronous
0 bit, 1 bit or 2 bits
L/M
Asynchronous
1
L
*1: Data bit transfer direction: LSB first or MSB first
*2: "+1" means the address/data format selection bit (A/D) used for communication control.
Note:
In mode 1 operation, multiple master/slave CPUs can be connected for communication. In mode 3,
the UART function works with a fixed communication format.
Send and receive data cannot be guaranteed if a mode is switched during sending or receiving.
As shown in the table below, the UART operation mode is determined according to setting the MD1
and MD0 bits of the serial mode register (SMR).
MD1
MD0
Mode
Description
0
0
0
Asynchronous (normal mode)
0
1
1
Asynchronous (multiprocessor mode)
1
0
2
Synchronous (normal mode)
1
1
3
Asynchronous (LIN mode)
401
CHAPTER 22 LIN-UART
22.4.1
Operations in Asynchronous Mode
(Operation Modes 0 and 1)
This section describes the operations in asynchronous mode
(operation modes 0 and 1).
■ Send/receive Data Format:
Send/receive data begins with the start bit ("L" level), and ends with the stop bit ("H" level). The bit
transfer direction (LSB first or MSB first) is determined with the transfer direction selection bit (BDS)
of the serial status register (SSR). If parity is enabled, the parity bit is always placed between the last
data bit and the first stop bit.
In operation mode 0, the data length can be 7 bits or 8 bits, with or without parity, and stop bit length 1
bit or 2 bits.
In operation mode 1, the data length can be set to 7 bits or 8 bits. In this mode, the address/data format
selection bit is added instead of adding parity. As the stop bit length, 1 bit or 2 bits can be selected.
To calculate a transfer frame bit length, use the following expression:
Length=1+d+p+s
(d = data bit count [7 or 8], p = parity [0 or 1], s = stop bit count [1 or 2])
*1
*2
Operation mode 0
ST D0 D1 D2 D3 D4 D5 D6 D7/P SP SP
Operation mode 1
ST D0 D1 D2 D3 D4 D5 D6 D7 A/D SP
*1
: D7 (bit 7) for data length 8 bits without parity
P (parity) for data length 7 bits with parity
*2 : Only when the SCR SBL bit is set to "1"
ST : Start bit
SP : Stop bit
A/D : Address data selection bit of mode 1
(multiprocessor mode)
Note:
If the BDS bit of the serial status register (SSR) is set to "1", the data is manipulated in the order of
D7, D6...D1, D0, and (P). If the stop bit length is set to 2 stop bits, both bits will be detected during
reception. The receive data full flag bit (RDRF) will be set to "1" at the first stop bit. However, if no
further receive operation occurs, the receive bus idle detection flag bit (RBI) of extended
communication control register (ECCR) is set to "1" after the second stop bit (The second stop bit is
for bus operations although it is the mark level).
402
CHAPTER 22 LIN-UART
■ Send Operation
If the send data register empty bit (TDRE) of the serial status register (SSR) is "1", send data is written in
the send data register (TDR). If data is written, the TDRE flag is set to "0". If the send enable bit (TXE)
of the serial status register (SCR) is set to "1" to enable sending, the related data is transferred to the send
shift register and sending starts from the start bit. As a result, the TDRE flag is set to "1" to enable new
data to be written in the TDR register.
If a send interrupt is possible (the send interrupt enable bit (TIE) of the serial status register (SSR) is
"1")), an interrupt occurs with the TDRE flag. Note that, if the TIE flag is set to "1", an interrupt will
occur since the initial value of the TDRE flag is "1".
■ Receive Operation
If the receive enable bit (RXE) of the serial control register (SCR) is "1", receive operation is
performed. If the start bit is detected, one data frame is received according to the data format set with
the serial control register (SCR). If an error occurs, the corresponding error flags (PE, ORE, and FRE)
are set. After one data frame has been received, the data is transferred from the serial shift register to the
receive data register (RDR) and the receive data register full flag bit (RDRF) of the serial status register
(SSR) is set to "1". When the receive data has been read, the RDRF flag is cleared.
If a reception interrupt is enabled (the reception interrupt enable bit (RIE) of the serial status register
(SSR) is "1"), an interrupt is generated with RDRF.
Note:
The receive data register (RDR) contains valid data only when the RDRF flag is set to "1".
■ Stop Bits, Error Detection, and Parity
During sending, 1 or 2bits can be selected as the stop bit length. If 2 bits have been selected as stop bits,
both are detected at reception. Set the extended communication control register (ECCR) 's receive bus
idle detection flag bit (RBI) after the 2nd stop bit.
Mode 0 can detect parity, overrun, and frame errors.
Mode 1 can detect overrun and frame errors but can detect no parity error.
Suppose that, in mode 0 (or, in mode 2, the ECCR register's start/stop enable bit (SSM) is set to "1"),
the serial control register (SCR)'s parity enable bit (PEN) is set. In this case, UART can perform parity
calculation (during sending), parity detection, and checking (during reception).
If the SCR register's parity selection bit (P) is cleared to "0", even parity is set. If the flag is set to "1",
odd parity is set.
403
CHAPTER 22 LIN-UART
22.4.2
Operations in Synchronous (Mode 2) Mode
This section describes the operations in synchronous (mode 2) mode.
■ Send/receive Data Format:
In the synchronous mode, the 8-bit data is transferred without start/stop bits if the extended
communication control register (ECCR)'s start/stop enable bit (SSM) is "0".
The following figure shows the data format in the synchronous operation mode:
Send data writing
Mark level
Serial clock (normal)
(CCO=0)
Mark level
Send data
0
1
1
0
1
0
0
1
For the sample rising edge (SCES=0), LSB first
■ Clock Supply
In the clock synchronous (extended I/O serial) mode, as many clocks as the number of send/receive bits
must be supplied. Note that, if communication with start/stop bits added is performed, the number of
clock cycles must match the number of added start/stop bits.
If the internal clock (dedicated reload counter) is selected and data is sent, the data reception
synchronous clock is automatically generated.
If the external clock is selected, confirm that the send data register contains send data and then the
clocks for each bit for sending must be generated and supplied from outside. Moreover, the mark level
("H") must be held before the start of sending and after the end of sending.
If the extended status control register (ESCR)'s sampling clock edge selection (SCES) is set to "1", the
UART's clock is reversed. As a result, receive data is extracted at the falling edge of the clock. In this
case, confirm that serial data is valid at the falling edge.
■ Error Detection
If the setting indicating that no start/stop bits are available is selected (the extended communication
control register (ECCR)'s start/stop enable bit (SSM is set to "0"), only overrun errors can be detected.
404
CHAPTER 22 LIN-UART
■ Communication Method
To use the synchronous mode, the following initialization is required:
Baud rate generator register (BGR0/BGR1):
Set a reload value required for the dedicated baud rate reload counter.
Serial mode register (SMR):
MD1, MD0
SCKE
SOE
: "10B" (mode 2)
: "1" Dedicated baud rate reload counter
"0" External clock
: "1" for sending
"0" for reception
Serial control register (SCR):
RXE, TXE
:
At least one of them must be "1".
For SSM=0 (default)
PEN, P
:
These bits are meaningless because no parity is provided.
For SSM=1
PEN
: "1"With parity: "0" Without parity
P
: "0" Even parity: "1" Odd parity
SBL, A/D
: These bits are meaningless because no parity, no stop bits, and no address/data
selection are set.
CL
: This bit has no effect because the data length is automatically set to 8-bit.
CRE
: "1" (the error flag is cleared for initialization to stop the send/receive operation).
Serial status register (SSR):
BDS
: "0" for LSB first;"1" for MSB first
RIE
: "1" if interrupts are used; "0 " without interrupt
TIE
: "1" for interrupts are used; "0" without interrupt
Extended communication control register (ECCR):
SSM
: "0" if no start/stop bits are available (normal)
: "1 " for adding start/stop bits (special)
MS
: "0" for the master mode (UART generates the serial clock).
: "1"for the slave mode
(UART receives the serial clock from the master device).
To start the communication, write data in the send data register (TDR).
To receive data, disable the SMR register's serial data output enable bit (SOE) and write dummy data in
TDR.
Note:
Because the SCK pin is used as clock input and output, sending and receiving at the same time is
not possible.
405
CHAPTER 22 LIN-UART
22.4.3
Operations with LIN Functions (Mode 3)
LIN-UART is used for LIN master/slave functions. For these LIN functions, mode 3 is
provided. In this mode, the data format is fixed; 8 bit data is sent or received;
1 start/stop bit is added; and the LSB first is configured.
■ LIN Master Operations
In the LIN master mode, the master determines all the baud rates. The slaves must synchronize with the
master. Therefore, the slaves need not set the baud rates.
If "1" is written in the extended communication control register (ECCR)'s LIN synch break generation
bit (LBR), the LIN synch break signal for 13 bits to16 bits is output from the SOUT pin as the "Low"
level. This signal enables the LIN communication to start.
As a result, the serial status register (SSR)'s send data empty flag bit (TDRE) is set to "0". After LIN
synch break, that bit is set to "1" to generate a transmit interrupt (when the SSR register's transmit
interrupt enable bit (TIE) is "1").
The Synch break length is determined with the extended status control register (ESCR)'s LIN synch
break length bit (LBL1/LBL0). The Synch break lengths are set as follows:
LBL1
LBL0
Break length
0
0
13-bit time
0
1
14-bit time
1
0
15-bit time
1
1
16-bit time
After LIN synch break, Synch Field (55H) is sent. To prevent a reception interrupt, "55H" can be written
in the send data register (TDR) after "1" is written in the ECCR register's LBR flag although the TDRE
flag is "0". The internal send shifter waits until the LIN break has finished and the TDR register value
has moved. With this, no transmit interrupt is generated after LIN synch break and before the start bit.
■ LIN Slave Operations
In the LIN slave mode, the UART is synchronized with the master's baud rate. UART generates a
reception interrupt if reception is disabled (the serial control register (SCR)'s receive enable bit (RXE)
is "0") and a LIN synch interrupt is enabled (extended status register (ESCR)'s LIN synch break
detection interrupt enable bit (LBIE) is "1"). If LIN synch break is detected, the ESCR register's LIN
synch break detection bit (LBD) is set. Writing "0" in this bit clears the interrupt.
Next, after LIN synch break detection, the LIN master's baud rate is analyzed. The internal capture
signal is set to "1" at the first falling edge of LIN synch field. It is set to "0" after the fifth falling edge.
At both-edge detection, an interrupt occurs if a capture interrupt is enabled.
At LIN synch field detection, the internal signal is equivalent to the serial clock eight bits of the master.
406
CHAPTER 22 LIN-UART
The following figure shows a typical start of the LIN message frame and LIN-UART operations.
Serial
clock
Serial
input
(LIN bus)
LBD
Capture
internal
LIN break
Synch field
407
CHAPTER 22 LIN-UART
22.4.4
Direct Access to the Serial Pin
This section describes the direct access to the serial pin.
■ Direct Access to the Serial Pin
LIN-UART enables a programmer to directly access the serial input-output pin. The software can
always monitor the status of the serial input pin (SIN) by reading the extended status register (ESCR)'s
serial input-output pin access setting bit (SIOP). Moreover, if the ESCR register's serial output pin
access enable bit (SOPE) is set, the software can set any serial output pin (SOUT) value. Note that this
access is possible only if the send shift register data has no data (no send operation).
In the LIN mode, this function can be used to read transmitted data or to handle errors occurring if the
LIN bus line signal is physically wrong.
Note:
Write a value in the SIOP bit before accessing the output pin.
408
CHAPTER 22 LIN-UART
22.4.5
Data Format Setting
This section describes the data format setting.
■ Data Format Setting
The extended communication control register (ECCR)'s serial data invert selection bit (INV) is set to
"1", then the serial data is inverted. This means that the signal mode is "Return To Zero" (RZ).
Otherwise, the signal mode for SIN and SOT is "Non Return To Zero" (NRZ, initial value).
The following figure explains the differences between two configuration:
SIN (NRZ)
INV = 0
ST
D0
D1
D2
D3
D4
D5
D6 D7
SP
SIN (RZ)
INV = 1
ST
D0
D1
D2
D3
D4
D5
D6 D7
SP
SOT (NRZ)
INV = 0
ST
D0
D1
D2
D3
D4
D5
D6 D7
SP
SOT (RZ)
INV = 1
ST
D0
D1
D2
D3
D4
D5
D6 D7
SP
Note:
The INV bit can be set in all operation modes including LIN mode 3.
409
CHAPTER 22 LIN-UART
22.4.6
Overview of the Register/Flag Bits
This section describes the register/flag bits.
■ Overview of the Register/Flag Bits
In LIN-UART (FL84), the send/receive operations depend on the mode which is set. So, setting a noneffect value to a flag bit in each mode (for example, parity is enabled in LIN mode 3) does not affect the
LIN-UART operation. Moreover, reading such a bit returns a correct value
The following table explains all possible configuration for all UART modes:
Mode
Parity
0
None, odd or
even
Stop bit
length
Byte length
A/D bit
7 bits or
8 bits
-
1 bit or 2 bits
1
-
2 (SSM=0)
-
-
2 (SSM=1)
None, odd or
even
1 bit or 2 bits
3 (LIN)
-
1 bit
❍: Available
-: Unused
410
❍
-
8 bits
Bit
direction
LSB first
or
MSB first
-
LSB first
SCES
SSM
-
-
-
-
❍
0
❍
1
-
-
INV
❍
CHAPTER 22 LIN-UART
22.5
UART Interrupts
This section describes the UART interrupts.
■ UART Interrupts
UART uses both reception and transmit interrupts. The following causes an interrupt:
•
Receive data is set in the receive data register (RDR) or receive error occurs.
•
Send data is transferred from the send data register (TDR) to the send shift register.
•
LIN-synch break is detected.
•
Bus is not in operation.
The following table shows the interrupt control bits and interrupt factors.
Operation mode
Interrupt
Send/receive/
request flag Flag register
capture
bit
0 1 2 3
Interrupt factor
Interrupt factor
enable bit
Receive data is
written to RDR.
Clearing interrupt
request
flag bit
Receive data is
read.
RDRF
SSR
❍
❍
❍
❍
ORE
SSR
❍
❍
❍
❍ Overrun error
FRE
SSR
❍
❍
▲
❍ Framing error
PE
SSR
❍
×
▲
× Parity error
LBR
ESCR
❍
×
×
❍
TBI and RBI
ECCR
❍
❍
▲
❍ No bus operation
Sending
TDRE
SSR
❍
❍
❍
❍ The send register is empty. SSR/TIE
8/16-bit
capture and
timer/
counter 1
ICP0
ICS01
❍
×
×
❍
LIN synch field's
first falling edge
ICS01/ICE0
ICE0 is temporarily
invalid.
ICP0
ICS01
❍
×
×
❍
LIN synch field's
fifth falling edge
ICS01/ICE0
ICE0 is invalid.
Reception
LIN-synch break is
detected.
SSR/RIE
Receive error
flag clear bit
(SCR: CRE) is
written with "1".
ESCR/LBIE
(ESCR: LBD) is
written with "0".
ESCR/BIE
Data reception/
sending
Send data is
written.
❍: Used bit
▲: Usable only for ECCR (SSM=1)
×: Unused
411
CHAPTER 22 LIN-UART
■ Reception Interrupt
If one of the following occurs in the receive mode, the corresponding flag bit of the serial status register
(SSR) is set to "1":
•
Completion of data reception
(Example) The receive data is transferred from the serial input shift register to the receive data
register (RDR): RDRF (receive data full flag bit)
•
Overrun error
(Example) RDRF=1, RDR read error: Overrun error flag bit (ORE)
•
Framing error
(Example) Stop bit receive error: Framing error flag bit (FRE)
•
Parity error
(Example) Parity detection error: Parity error flag bit (PE)
If at least one of these flag bits above is "1" and the reception interrupt is enabled (the SSR register's
reception interrupt enable bit (RIE) is set to "1"), a reception interrupt request is generated.
If the receive data register (RDR) is read, the RDRF flag is automatically cleared to "0".
Notes:
• The above is the method of resetting the RDRF flag.
If the receive error flag clear bit (CRE) of the serial control register (SCR) is written with "1", all
error flags are cleared to "0".
• If the RDRF flag is "1" and no error bits are set, the RDR register contains valid data.
• The CRE flag is write only. When "1" is written to it, it retains "1" for one clock cycle.
■ Transmit Interrupt
If send data is transferred from the send data register (TDR) to the send shift register (if the send shift
register is empty and send data is available), the send data register empty flag bit (TDRE) of the serial
status register (SSR) is set to "1". In this case, a transmit interrupt request is generated if a transmit
interrupt is enabled (SSR register's transmit interrupt enable bit (TIE) is "1").
Note:
The initial value after hardware or software reset is cleared to "0". So, an interrupt is generated
immediately if the TIE flag is "1". The way to reset TDRE is to write data to RDR.
412
CHAPTER 22 LIN-UART
■ LIN Synch Break Interrupt
This function works when LIN-UART operates in mode 0 or 3 as a LIN slave.
If the bus (serial input) is "0" for more than 13 bit times, LIN synch break detection flag bit (LBD) of
the extended status control register (ESCR) is set to "1".
Note:
To detect LIN synch break, reception must be disabled (the receive enable bit (RXE) of the serial
control register (SCR) is "0") or a reception interrupt must be disabled (the reception interrupt enable
bit (RIE) of the serial status register (SSR) is "0"). Note that, if this setting is enabled, a reception
error interrupt is generated after 9 bit times. In other cases, a receive error interrupt is generated
first. The interrupt handle routine must then wait for LBD=1.
The LIN synch break interrupt and the LBD flag are cleared when the LBD flag is written with "0".
With this, confirm that the CPU has detected the LIN synch break that indicates that the single clock is
adjusted to the LIN master.
■ LIN Synch Field Edge Detection Interrupt
This function works when LIN-UART operates in mode 0 or 3 as a LIN slave. After LIN synch break
detection, the internal signal LSYN (connected to ICU) is set to "1" at the first falling edge of LIN
synch field. It is set to "0" after the fifth falling edge. When both edges are detected, the capture
generates an interrupt. The difference of the input capture counter values is equivalent to the master's 8bit serial clock. A value obtained by dividing that difference value by 8 is set in the dedicated reload
counter. If a falling edge of the start bit is detected, the reload counter automatically restarts.
■ Bus Idle Interrupt
If no receive operation occurs on the SIN pin, the receive bus idle detection flag bit (RBI) of extended
communication control register (ECCR) is set to "1". If no send operation occurs on the SOUT pin, the
ECCR register's send bus idle detection flag bit (TBI) is set to "1". In this case, the bus idle interrupt of
ECCR is enabled (the ECCR register's bus idle interrupt enable bit (BIE) is set to "1"). If both bus idle flag
bits (TBI and RBI) are 1, an interrupt is generated.
Note:
Suppose that the serial output pin can be directly accessed (the serial output pin direct access
enable bit (SOPE of the ESCR register is "1"). In this case, if the SOUT pin is fixed to "0" (the serial
input-output pin access setting bit (SIOP) of the ESCR register is "0"), the TBI flag is set to "0"
without the send operation (ECCR register's TBI flag is "1").
413
CHAPTER 22 LIN-UART
22.5.1
Software Reset
This section describes the software reset of LIN-UART.
■ Software Reset
If LIN-UART does not run normally, there is the possibility to reset only the LIN-UART instead of
resetting MCU. The programmable clear bit (UPCL) of the serial mode register (SMR) provides such a
function. Writing "1" to this bit resets UART immediately. There is no need to set this bit again to "0".
Note:
If you fix the SOUT pin at "0" (by setting the serial I/O pin access setting bit (SIOP) in the ESCR
register to "0") when serial output pin direct access is enabled (with the serial output pin direct
access enable bit (SOPE) containing "1" in the ESCR register), the TBI flag is set to "0" even when a
transmit operation is not performed (with the ECCR register's TBI flag containing "1"). At a reset,
LIN-UART will be disconnected if it is in process of sending or receiving. The register configuration
are retained, but the dedicated reload counter (FL85) restarts.
Pay great care to use this function. To prevent data from being lost, it is recommended that any
instructions to be written to the LIN-UART's SMR register should be masked with "FBH".
An alternative to resetting LIN-UART without resetting the reload counter (FL85) is to temporarily
disable the reception function (the serial control register (SCR)'s receive enable bit (RXE) is set to "0")
or the transmission function (SCR register's send enable bit (TXE) is set to "0"). The receive and/or
send control circuit is internally reset.
Another alternative is to temporarily change the operation mode of LIN-UART. This will produce the
same effect.
To reset only the state machine limited to reception, simply write "1" to the reception error flag clear bit
(CRE) of the serial control register (SCR).
414
CHAPTER 22 LIN-UART
22.6
Clock Synchronization of LIN-UART
This section describes the clock synchronization of LIN-UART.
■ Clock Synchronization
In the asynchronous mode, UART detects a falling edge of the start bit and generates a signal (SEDGE)
to restart the baud rate reload counter (FL85). With this, the serial data is extracted during bit time.
CLKP
SIN
(oversampled)
start bit
data bit
SIN
to reception
shifter
SEDGE
(internal
signal)
Data sampling time
Reload Counter Restart
RSCL
(reception
clock)
clock phase cut off
bit time
415
CHAPTER 22 LIN-UART
22.7
Flag Set Timing
This section describes the interrupt generation and flag set timing.
■ Reception Interrupt Generation and Flag Set Timing
The flags are set if reception is compete (serial status register (SSR)'s receive data full flag bit (RDRF)),
or if a receive error is generated (SSR register's parity error flag bit (PE), the overrun flag bit (ORE),
and framing error bit (FRE)). In this case, a reception interrupt occurs if a reception interrupt is enabled
(SSR register's reception interrupt enable bit (RIE) is "1"). These interrupts are generated if the first
stop bit is detected in mode 0 or 1 (except parity error), or the last data bit is read in mode 2.
Note:
If a receive error has occurred, the data of the receive data register (RDR) has no effect.
Receive data
(mode 0/3)
ST
D0
D1
D2
…
D5
D6
D7/P
SP
ST
Receive data
(mode 1)
ST
D0
D1
D2
…
D5
D6
A/D
SP
ST
Receive data
(mode 2)
ST
D0
D1
D2
…
D4
D5
D6
D7
D0
PE*1, FRE
RDRF
ORE*2
(if RDRF = 1)
reception interrupt occurs
*1: The PE flag cannot be used in mode 1 or 3.
ST : Start Bit
SP : Stop Bit
A/D : Mode 1 (multi processor) address/data selection
*2: An overrun error (ORE) occurs if the next data is transferred to (RDRF=1) before the receive data is read.
Note:
The example above shows not all settable receive options for mode 0 and 3.
An overrun error (ORE) occurs if, before a transmit interrupt is generated and flag set timing receive
data is read (PDRF = 1), the next data is transferred.
Receive
data
RDRF
ORE
416
CHAPTER 22 LIN-UART
■ Transmit Interrupt Generation and Flag Set Timing
An interrupt is generated when the next data is ready to be written to the send data register (TDR). In
other words, a send interrupt occurs if the send interrupt enable bit (TIE) of the serial status register
(SSR) is set to"1" while the send data register (TDR) contains no data.
The send data empty flag bit (TDRE) of the SSR register indicates the status of the TDR register. Since
the TDRE bit is "read only", it is cleared by writing data in the TDR register.
The following shows one example of the send operation and flag set timing for the modes of LINUART:
transmission interrupt occurs
transmission interrupt occurs
Mode 0, 1 or 3 :
write to TDR
TDRE
serial output
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
A/D
A/D
transmission interrupt occurs
transmission interrupt occurs
Mode 2 :
write to TDR
TDRE
serial output
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4
ST : Start bit D0...D7 : data bits
P : Parity SP: Stop bit A/D : Address/data selection bit (mode1)
Note:
The example above shows not all settable send options for mode 0.
417
CHAPTER 22 LIN-UART
■ LIN Synch Break Detection Interrupt and Flags
If LIN Synch break is detected in the slave mode, the LIN Synch Break detection bit (LBD) of the
extended status control register (ESCR) is set to "1". In this case, an interrupt will occur if the LIN
Break Synch detection interrupt enable bit (LBIE) of the ESCR register is set.
The figure below shows the LIN synch break detection interrupt and the flag set timing.
Serial clock
0 1 2 3 4
cycle #
5 6 7 8 9 10 11 12 13 14 15
Receive
data
FRE
(RXE=1)
LBD
(RXE=0)
Reception interrupt occurs, if
RXE=1
Reception interrupt occurs, if RXE=0
Note:
If reception is enabled (serial control register (SCR)'s receive enable bit (RXE) is "1") and if a
reception interrupt is enabled (serial status register (SSR)'s reception interrupt enable bit (RIE) is
"1"), the SSR register's framing error flag bit (FRE) is set 2 bit times earlier than the LIN break
interrupt. So, if a LIN break interrupt is expected, it is recommended to set the RXE bit to "0".
The LBD bit is supported only in mode 0 and 3.
■ LIN Synch Field Edge Detection Interrupt
After LIN break detection, the first falling edge of the serial input (SIN pin) sets the LSYN signal
(internally connected to Input Capture Unit (ICU)). The fifth falling edge resets the LSYN signal.
Therefore, ICU must operate when both edges are detected. The value of the ICU counter register for
the first interrupt is retained. The value obtained by subtracting the first ICU counter register value from
the second ICU counter register value is equivalent to the master's 8 bit serial clock.
Synch Break
Synch Field
Receive
data
LSYN
(to ICU)
IRQ from
ICU
Interrupt cleared by CPU
418
Identifier
CHAPTER 22 LIN-UART
■ Bus Idle Interrupt and Flags
A bus idle interrupt occurs if the serial input shift register and serial output register are empty and if the
bus idle interrupt enable bit (BIE) of the extended communication control register (ECCR) is set. The
following figure shows the bus idle interrupt and the flag set timing:
Transmission
data
Reception
data
TBI
RBI
IRQ
: Start bit
: Sop bit
: Data bit
Note:
During reception if the receive operation is disabled (serial control register (SCR)'s receive enable bit
(RXE) is "0"), the receive bus idle detection flag (RBI) of the extended communication control
register (ECCR) is set to "1". If the serial output is enabled (ESCR register's serial output pin direct
access enable bit (SOPE) is "1") and if the SOUT pin is fixed to "0" (ESCR register's serial inputoutput pin access setting bit (SIOP) is "0"), the TBI flag is set to "0" without the send operation.
419
CHAPTER 22 LIN-UART
22.8
Special Specifications of LIN-UART
This section describes the special specifications of LIN-UART.
■ Sampling Clock Edge
The sampling clock edge selection bit (SCES) of the extended status control register (ESCR) determines
the sample edge where the receive bit is sampled to the receive shift register in mode 2. Moreover, if
LIN-UART is in master mode 2, this bit inverts the generated clock signal.
Serial clock signal
(SCES=0)
Serial clock signal
(SCES=1)
Data bit
(For the LSB first)
OR
D0
D1
D2
D3
D4
D5
D6
D7
: Sample clock edge
■ Synchronous Start/stop Bit Mode
In synchronous mode 2, if the start/stop enable bit (SSM) of the extended communication control
register (ECCR) is set, the start bit, and stop bit are added to the data stream like in mode 0. Therefore,
all additional bits are clock-output, too.
reception or transmission clock
(SCES= 0, CCO=0):
mark level
reception or transmission clock
(SCES= 1, CCO=0):
mark level
data stream (SSM=1)
(here: no parity, 1 stop bit)
ST
SP
data frame
420
CHAPTER 22 LIN-UART
■ Continuous Serial Clock Output
In mode 2, if the continuous clock output enable bit (CCO) of the extended status control register
(ESCR) is set, the serial clock is output directly to the SCK pin to synchronize with the shift clocks.
This is useful when using the start and stop bits in synchronous mode.
reception or transmission clock
(SCES=0, CCO=1):
reception or transmission clock
(SCES=1, CCO=1):
data stream (SSM=1)
(here: no parity, 1 stop bit)
ST
SP
data frame
421
CHAPTER 22 LIN-UART
22.9
LIN Communication Operation
The following flowchart shows the operation of LIN-UART when it functions as the
master device.
■ LIN Master-Slave Communication Function
The settings shown in the figure below are required to operate UART in LIN communication mode
(operation mode 3).
Figure 22.9-1 UART Settings
SCR5, SMR5
bit 15
PEN
Mode 3 ✕
14
P
✕
SSR5, TDR5/RDR5
bit 15
14
PE
Mode 3
13
SBL
+
12
CL
+
11
10
9
8
7
6
5
4
3
2
1
0
A/D CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SPE
✕
✕
0
1
1
0
0
0
1
13
12
11
10
9
ORE FRE RDRF TDRE BDS RIE
8
7
6
5
4
3
2
1
Set transmission data (during write)
Retain reception data (during read)
7
-
6
LBR
TIE
0
+
✕
ESCR5, ECCR5
bit 15
14
13
12
11
10
9
8
LBIE LBD LBL1 LBL0 SOPE SIOP CCO SECS
✕
✕
✕
✕
Mode 3
: Used bit
✕: Unused bit
0/1: Setting the bit to "0" or "1"
+: Set bit to the correct value automatically
5
4
3
MS SCDE SSM
✕
✕
✕
2
1
BIE
✕
RBI
✕
0
TBI
✕
■ Connecting LIN Device
The following figure illustrates the communication system used between one LIN master device and
another LIN slave device. UART can operate as both a LIN master and LIN slave.
Figure 22.9-2 Example Connection for Small-scale LIN Bus System
LIN bus
SOT
SOT
SIN
LIN-master
422
SIN
Single-wire transceiver
Single-wire transceiver
LIN-slave
CHAPTER 22 LIN-UART
■ LIN-UART Master
The following flowchart shows that LIN-UART serves as the master device:
START
Initialization:
Set Operant. mode 3
(8N1 data format)
TIE = 0, RIE = 0
Send Message?
NO
YES
Send Sleep Mode
TDR = 80H
TIE = 0
Send Synch Break:
write "1" to ECCR:
LBR; TIE = 1;
Send Synch Field:
TDR = 55H
Wake up
from CPU ?
TDRE = 1
Transm. Interrupt
YES
Send Wake up signal
RIE = 0
TIE = 1
TDR = 80H
NO
RIE = 1
Send
Sleep Mode?
YES
NO
NO
00H, 80H or C0H
received?
YES
RIE = 0
Send Identify Field:
TDR = Id
Write to slave?
NO
TIE = 0
RIE = 1
Read data from slave
RIE = 0
YES
TIE = 1
Write data to slave
TIE = 0
Errors occurred?
NO
YES
Error Handler
423
CHAPTER 22 LIN-UART
■ LIN-UART Slave
The following flowchart shows that the LIN-UART serves as the slave device:
START
A
B
Initialization:
Set Operant. mode 3
(8N1 data format)
C
Errors occurred?
RIE = 0; LBIE = 1; RXE = 0
NO
Slave address
match?
YES
E
C
YES
NO
NO
Master wants to
send data?
waiting
(slave
action)
YES
LBD = 1
LIN break interrupt
Awaiting message
from LIN master.
Write "0" to LBD to
clear interrupt
EnableICU interrupt
(both edges)
RIE = 0
TIE = 1
Calculate
checksurn
Send data
Receive data
+ checksum
YES
80H received?
(sleep mode)
S
(on next page)
waiting
(slave
action)
ICUInterrupt
TIE = 0
NO
C
B
Read ICU value
and store it.
Clear Interrupt.
Errors occurred?
YES
NO
waiting
(slave
action)
C
ICUInterrupt
Read ICU value.
Calculate new
baud rate.
Set it to Reload
Counter (FL85).
Clear Interrupt.
E
Error handler
Receive identifier
RIE = 1; RXE = 1
C
A
(Continued)
424
CHAPTER 22 LIN-UART
(Continued)
S
Wake up
from CPU?
YES
Send Wake up signal
RIE = 0
TIE = 1
TDR = 80H
NO
TIE = 0
RIE = 1
NO
00H, 80H or C0H
received?
YES
RIE = 0
C
425
CHAPTER 22 LIN-UART
22.10
Overview of Changes from Normal UART
This section describes the overview of changes from normal UART.
■ Overview of Changes from Normal UART
•
•
•
The extended status control register (ESCR) provides the following functions:
-
LIN interrupt generation
-
Direct access to the serial input /output pins (SIN, SOT).
-
Sampling clock edge selection bit (SCES) (clock inversion)
-
Continuous serial clock output for mode 2 (with start/stop bits)
The extended communication control register (ECCR) provides the following functions:
-
Start/stop bit enabling (SSM) in synchronous mode
-
Master and slave communication in synchronous mode (MS)
-
Bus idle interrupt generation with the send and receive idle flags
Changes in the serial mode register (SMR):
-
Mode 3 is added for the LIN slave function and for fixing the data format.
-
To install the reload counter, clock select bits were removed and replaced with control bits.
•
The communication prescaler control register (CPCR) was removed and two registers (BGR1 and
BGR0) required for the reload counter were added.
•
In mode 1 (multiprocessor mode), the master/slave function was added.
•
The flag bits relating to the send/receive data format always return "correct" values. For example: If
the programmer attempts to set parity in mode 3 (LIN mode), the PEN bit will return "0".
•
During reception, if the serial control register (SCR)'s stop bit length selection bit (SBL) is "1",
second stop bit is checked.
•
In the asynchronous mode, the five-time sampling function was added.
•
The SEDGE (for detecting the start bit falling edge) signal for the dedicated baud rate generator is
generated to synchronize the input data with the receive clock.
•
To support version 2.0, NRZ and RZ signal modes were added.
•
The bit manipulation instructions can handle read-modify-write (RMW) of the A/D bit.
LIN-UART is similar to ordinary UART; however, no software compatibility exists between them.
426
CHAPTER 22 LIN-UART
22.11
Restrictions
This section explains LIN-UART restrictions.
■ Restrictions
•
Always write "0" to the bus idle interrupt enable bit ECCR:
BIE to indicate it as the reserved bit. Alternatively, use it as the master for LIN.
•
At the MODE2 slave sending, UART must not be reset with TXE=1. Be sure to reset UART with
EXT=0.
•
Unnecessary transfer occurs if DMA transfer is performed after the CPU carries out program transfer
during LIN-UART data transfer. Therefore, disable the transmission enable bit (TIE) and reception
enable bit (RIE) in the serial status register (SSR) (i.e. write "0" to the bits) before starting DMA
transfer.
427
CHAPTER 22 LIN-UART
428
CHAPTER 23
A/D CONVERTER
This chapter describes the overview of the A/D
converter, the configuration and functions of registers,
and A/D converter operation.
23.1 Overview of the A/D Converter
23.2 A/D Converter Register List
23.3 A/D Converter Operations
429
CHAPTER 23 A/D CONVERTER
23.1
Overview of the A/D Converter
This section describes the features and block diagram of the A/D converter.
■ A/D Converter Overview
The A/D converter can convert analog input voltages into 10-bit or 8-bit digital values by means of RCtype successive approximation. The input signal is selected from among the individual analog input
pins; the activation of conversion can be selected from three options: software, internal clock, and
external pin trigger.
■ Features of the A/D Converter
The A/D converter converts analog input voltages to digital values.
The A/D converter has the following features:
• Conversion time
Minimum 3μs per channel (16/32 MHz machine clock)
• RC sequential compare conversion method with sample and hold circuit
• 10-bit or 8-bit resolution
• Analog inputs selected from 32 channels by programming
-
Single conversion mode:
One channel is selected for a conversion.
-
Scan conversion mode:
Continuos multiple channels are converted. Programmable up
to 32 channels.
-
Continuous conversion mode:
Specified channels are converted repeatedly.
-
Stop conversion mode:
After specified channels are converted, the system pauses and
waits for next activation (The conversion start points can be
synchronized).
• Interrupt request
When A/D conversions finish, a pertinent interrupt request can be issued to the CPU.
• Selectable activation factors
Available activation factors are the software, external trigger (falling edge), or timer (rising edge).
430
CHAPTER 23 A/D CONVERTER
■ A/D Converter Block Diagram
Figure 23.1-1 shows the A/D converter block diagram.
Figure 23.1-1 A/D Converter Block Diagram
MPX
AVCC
AVRH/
AVRL
AVSS
D/A converter
Sequential compare
register
Comparator
Internal data bus
Sample and
hold circuit
Decoder
Input circuit
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
Data register
A/D control register 0
A/D control register 1
Operation
clock
ATGX pin
16-bit
Reload timer
CLKP
Prescaler
431
CHAPTER 23 A/D CONVERTER
■ Input Impedance
The following equivalent circuit shows a sampling circuit of the A/D converter:
Figure 23.1-2 Input Impedance
Rin
13.6k Ω (AVCC >= 4.0V)
2.52kΩ (AVCC >= 4.5V)
Rext
Analog signal
source
ANx
Analog SW
Cin: Maximum 10.7pF
ADC
Ensure that the Rext does not exceed the maximum Sampling time (Tsamp).
Rext = Tsamp/(7 Cin) - Rin
432
CHAPTER 23 A/D CONVERTER
23.2
A/D Converter Register List
This section describes the A/D converter registers.
■ A/D Converter Register List
The A/D converter has the following registers:
• A/D control status register
• Data register
• Sampling timer setting register
• Start/End channel setting register
Figure 23.2-1 Map of the A/D Converter Register
bit15
8
7
0
ADCS1
ADCS0
ADCR1
ADCR0
ADCT1
ADCT0
ADSCH
ADECH
8 bits
8 bits
Figure 23.2-2 A/D Converter Registers
A/D control status register - Upper byte
Address:
bit 15
14
000154H
BUSY
INT
Read/Write→
(R/W)
(R/W)
Initial value→
(0)
(0)
A/D control status register - Lower byte
Address:
bit 7
6
000155H
MD1
MD0
Read/Write→
(R/W)
(R/W)
Initial value→
(0)
(0)
13
12
11
10
9
8
INTE
(R/W)
(0)
PAUS
(R/W)
(0)
STS1
(R/W)
(0)
STS0
(R/W)
(0)
STRT
(R/W)
(0)
Reserved
(R/W)
(0)
5
4
3
2
1
0
S10
(R/W)
(0)
ACH4
(R/W)
(0)
ACH3
(R/W)
(0)
ACH2
(R/W)
(0)
ACH1
(R/W)
(0)
ACH0
(R/W)
(0)
13
(-)
(-)
12
(-)
(-)
11
(-)
(-)
10
(-)
(-)
9
D9
(R)
(X)
8
D8
(R)
(X)
Data register - Upper byte
Address:
bit 15
000156H
Read/Write→
(-)
Initial value→
(-)
14
(-)
(-)
Data register - Lower byte
Address:
bit 7
000157H
D7
Read/Write→
(R)
Initial value→
(X)
6
5
4
3
2
1
0
D6
(R)
(X)
D5
(R)
(X)
D4
(R)
(X)
D3
(R)
(X)
D2
(R)
(X)
D1
(R)
(X)
D0
(R)
(X)
ADCS1
ADCS0
ADCR1
ADCR0
(Continued)
433
CHAPTER 23 A/D CONVERTER
(Continued)
A/D conversion time setting register - Upper byte
Address:
000158H
Read/Write→
Initial value→
bit 15
CT5
(R/W)
(0)
14
13
12
11
10
9
8
CT4
(R/W)
(0)
CT3
(R/W)
(0)
CT2
(R/W)
(1)
CT1
(R/W)
(0)
CT0
(R/W)
(0)
ST9
(R/W)
(0)
ST8
(R/W)
(0)
ADCT1
A/D conversion time setting register - Lower byte
Address:
000159H
Read/Write→
Initial value→
bit 7
6
5
4
3
2
1
0
ST6
(R/W)
(0)
ST5
(R/W)
(1)
ST4
(R/W)
(0)
ST3
(R/W)
(1)
ST2
(R/W)
(1)
ST1
(R/W)
(0)
ST0
(R/W)
(0)
bit 15
14
13
12
11
10
9
8
(-)
(-)
(-)
(-)
(-)
(-)
ANS4
(R/W)
(0)
ANS3
(R/W)
(0)
ANS2
(R/W)
(0)
ANS1
(R/W)
(0)
ANS0
(R/W)
(0)
6
5
4
3
2
1
0
(-)
(-)
(-)
(-)
ANE4
(R/W)
(0)
ANE3
(R/W)
(0)
ANE2
(R/W)
(0)
ANE1
(R/W)
(0)
ANE0
(R/W)
(0)
ST7
(R/W)
(0)
ADCT0
A/D start channel setting register
Address:
00015AH
Read/Write→
Initial value→
ADSCH
A/D end channel setting register
Address:
00015BH
Read/Write→
Initial value→
434
bit 7
(-)
(-)
ADECH
CHAPTER 23 A/D CONVERTER
■ Analog Input Enable Registers
Figure 23.2-3 Analog Input Enable Registers
Analog input enable registers
ADERH
bit 15
Address: 000150H
ADE31
Read/Write→ (R/W)
Initial value→
(0)
14
ADE30
(R/W)
(0)
13
ADE29
(R/W)
(0)
12
ADE28
(R/W)
(0)
11
ADE27
(R/W)
(0)
10
ADE26
(R/W)
(0)
9
ADE25
(R/W)
(0)
8
ADE24
(R/W)
(0)
bit 7
ADE23
(R/W)
(0)
6
ADE22
(R/W)
(0)
5
ADE21
(R/W)
(0)
4
ADE20
(R/W)
(0)
3
ADE19
(R/W)
(0)
2
ADE18
(R/W)
(0)
1
ADE17
(R/W)
(0)
0
ADE16
(R/W)
(0)
ADERL
bit 15
Address: 000152H
ADE15
Read/Write→ (R/W)
Initial value→
(0)
14
ADE14
(R/W)
(0)
13
ADE13
(R/W)
(0)
12
ADE12
(R/W)
(0)
11
ADE11
(R/W)
(0)
10
ADE10
(R/W)
(0)
9
ADE9
(R/W)
(0)
8
ADE8
(R/W)
(0)
bit 7
ADE7
(R/W)
(0)
6
ADE6
(R/W)
(0)
5
ADE5
(R/W)
(0)
4
ADE4
(R/W)
(0)
3
ADE3
(R/W)
(0)
2
ADE2
(R/W)
(0)
1
ADE1
(R/W)
(0)
0
ADE0
(R/W)
(0)
Address: 000151H
Read/Write→
Initial value→
Address: 000153H
Read/Write→
Initial value→
Always write "1" to ADE bit which corresponds to the pin used for analog input.
Set the pins used for analog inputs as follows:
• 0: Port input/output mode
• 1: Analog input mode
• Upon reset, this bit is initialized to "0".
• Always write "1" to the analog input enable register for start and end channels.
435
CHAPTER 23 A/D CONVERTER
■ A/D Control Status Register (ADCS1)
Figure 23.2-4 A/D Control Status Register (ADCS1)
A/D control status register - Upper byte
Address:
bit 15
000154H
BUSY
Read/Write→ (R/W)
Initial value→
(0)
14
13
12
11
10
9
8
INT
(R/W)
(0)
INTE
(R/W)
(0)
PAUS
(R/W)
(0)
STS1
(R/W)
(0)
STS0
(R/W)
(0)
STRT
(R/W)
(0)
Reserved
(R/W)
(0)
A/D control status register (ADCS1) is used to control the A/D converter and indicate the status.
[bit15] BUSY (busy flag and stop)
• Read:
This bit indicates the A/D converter operation.
It is set when A/D conversion is started, and cleared when conversion of the last channel
finishes.
• Write:
Writing "0" to this bit while A/D conversion is in progress forces the conversion to abort.
Use this for a forced abort in Continuous or Stop mode.
"1" cannot be written to the operation indicator bit. The read-modify-write (RMW) instructions can read
"1". In Single mode, this bit is cleared when the A/D conversion finishes with the specified last channel.
In Continuous or Stop mode, this bit is not cleared until the operation is stopped by writing "0".
Upon reset, this bit is initialized to "0".
Do not execute forced abort and software activation simultaneously (BUSY=0, STRT=1).
[bit14] INT (interrupt)
This bit is set when conversion data is written to ADCR.
When this bit is set while bit13 (INTE) is "1", an interrupt request will be issued.
It is cleared by writing "0".
Note: Write "0" to clear this bit only when the A/D conversion is not in progress.
Upon reset, this bit is initialized to "0".
If DMA is used, this bit is cleared when DMA finishes transfer.
[bit13] INTE (Interrupt enable)
This bit is used to enable or disable interrupts when conversion finishes.
• 0: Disable interrupts
• 1: Enable interrupts
Upon reset, this bit is initialized to "0".
436
CHAPTER 23 A/D CONVERTER
[bit12] PAUS (A/D converter pause)
This bit is set when the A/D conversion is paused.
There is only one register to store the A/D conversion results. Therefore the conversion results must be
transferred by DMA to avoid data corruption in Continuous conversions.
In order to protect the data, next conversion data will not be stored until DMA transfers the contents of
the data register. The A/D conversion is paused during this process. When DMA finishes the transfer,
the A/D conversion is resumed.
This bit is valid only when DMA is used.
• This bit can be cleared only by writing "0" (End of DMA transfer does not clear it). Note that this bit
cannot be cleared while waiting for DMA transfer.
• For information on conversion data protection feature, refer to section "23.3
Operations".
A/D Converter
• Upon reset, this bit is initialized to "0".
[bit11, bit10] STS1, STS0 (Start source select)
Upon reset, these bits are initialized to "00B".
These bits are used to select the A/D activation factor.
STS1
STS0
Function
0
0
Software start
0
1
Start by external pin trigger and software
1
0
Start by 16-bit reload timer and software
1
1
Start by external pin trigger, 16-bit reload timer, and software
In the modes allowing two or more activation factors, the first issued factor starts the A/D conversion.
Note that the changes in the activation source setting will be validated immediately even if the A/D
conversion is in progress.
• The external pin trigger detects the falling edge. If this bit is changed to an external pin trigger while
the external trigger input level is "L", the A/D conversion may be started immediately.
• When timer is selected, the 16-bit reload timer 2 will be selected.
[bit9] STRT (Start)
Writing "1" to this bit starts the A/D conversion (software activation).
To reactivate, write "1" again.
Upon reset, this bit is initialized to "0".
In Continuous and Stop modes, it will not be reactivated due to the operation functions. Before writing
"1", check the BUSY bit (Clear the BUSY bit first before starting).
Do not execute forced abort and software activation simultaneously (BUSY=0, STRT=1).
[bit8] (Reserved bit)
Always write "0" to this bit.
437
CHAPTER 23 A/D CONVERTER
■ A/D Control Status Register (ADCS0)
Figure 23.2-5 A/D Control Status Register (ADCS0)
A/D control status register - Lower byte
Address:
bit 7
000155H
MD1
Read/Write→ (R/W)
Initial value→
(0)
6
5
4
3
2
1
0
MD0
(R/W)
(0)
S10
(R/W)
(0)
ACH4
(R/W)
(0)
ACH3
(R/W)
(0)
ACH2
(R/W)
(0)
ACH1
(R/W)
(0)
ACH0
(R/W)
(0)
A/D control status register (ADCS0) is used to control the A/D converter and indicate the status. Do not
change the ADCS0 setting while conversion is in progress.
[bit7, bit6] MD1, MD0 (A/D converter mode set)
MD1 and MD0 bits are used to set the operation mode.
MD1
MD0
Operation mode
0
0
Single mode; all reactivations during operation are allowed.
0
1
Single mode; reactivations during operation are disabled.
1
0
Continuous mode; reactivations during operation are disabled.
1
1
Stop mode; reactivations during operation are disabled.
Note: Reactivations during the A/D conversion are enabled when A/D conversion mode selection bits
(MD1 and MD0) are set to "00B".
In this mode, only software activation (STS1 and STS0 = 00B) can be selected. To perform a
reactivation, follow the procedure below:
1. Clear the INT bit to "0".
2. Write "1" to the STRT bit at the same time as writing "0" to the INT bit.
• Single mode
Performs the A/D conversion for the specified channels from ANS4 to ANS0 through ANE4 to
ANE0 successively. Stops when all the channels are converted.
• Continuous mode
Performs the A/D conversion for the specified channels from ANS4 to ANS0 through ANE4 to
ANE0 repeatedly.
• Stop mode
Performs the A/D conversion for the specified channels from ANS4 to ANS0 through ANE4 to
ANE0 by each channel, then pauses. Resumes by issuing the activation factor.
Upon reset, these bits are initialized to "00B".
• When started while in Continuous or Stop mode, the A/D conversion continues until forced abort by
the BUSY bit.
• Forced abort will take place when "0" is written to the BUSY bit.
• Upon activation after forced abort, the conversion starts from the specified channels with ANS4 to
ANS0.
• In Single, Continuous, or Stop mode, the system does not allow reactivation regardless of the
activation factors; timer, external trigger or software.
438
CHAPTER 23 A/D CONVERTER
[bit5] S10
• This bit specifies the conversion resolution. When it is set to "0", the A/D conversion is performed in
10 bits. Otherwise, A/D conversions is performed in 8-bit and the results are stored in ADCR0.
• Upon reset, this bit is initialized to "0".
[bit4 to bit0] ACH4 to ACH0 (Analog convert select channel)
These bits are used to indicate what channels are currently converted.
ACH4
ACH3
ACH2
ACH1
ACH0
Conversion channel
0
0
0
0
0
AN0
0
0
0
0
1
AN1
0
0
0
1
0
AN2
0
0
0
1
1
AN3
0
0
1
0
0
AN4
0
0
1
0
1
AN5
0
0
1
1
0
AN6
0
0
1
1
1
AN7
0
1
0
0
0
AN8
0
1
0
0
1
AN9
0
1
0
1
0
AN10
0
1
0
1
1
AN11
0
1
1
0
0
AN12
0
1
1
0
1
AN13
0
1
1
1
0
AN14
0
1
1
1
1
AN15
1
0
0
0
0
AN16
1
0
0
0
1
AN17
1
0
0
1
0
AN18
1
0
0
1
1
AN19
1
0
1
0
0
AN20
1
0
1
0
1
AN21
1
0
1
1
0
AN22
1
0
1
1
1
AN23
1
1
0
0
0
AN24
1
1
0
0
1
AN25
1
1
0
1
0
AN26
1
1
0
1
1
AN27
1
1
1
0
0
AN28
1
1
1
0
1
AN29
1
1
1
1
0
AN30
1
1
1
1
1
AN31
• Read
During the A/D conversion (BUSY bit = 1), these bits indicate what channels are being converted.
When stopped by forced abort (BUSY bit=0), these bits indicate the channel where the conversion is
stopped.
439
CHAPTER 23 A/D CONVERTER
• Write
Writing to these bits has no effect.
• Upon reset, these bits are initialized to "00000B".
■ Data Register (ADCR0, ADCR1)
Figure 23.2-6 Data Register (ADCR0, ADCR1)
Data register - Upper byte
Address:
bit 15
000156H
Read/Write→
(-)
Initial value→
(-)
14
13
12
11
10
9
8
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
D9
(R)
(X)
D8
(R)
(X)
Data register - Lower byte
Address:
bit 7
000157H
D7
Read/Write→
(R)
Initial value→
(X)
6
5
4
3
2
1
0
D6
(R)
(X)
D5
(R)
(X)
D4
(R)
(X)
D3
(R)
(X)
D2
(R)
(X)
D1
(R)
(X)
D0
(R)
(X)
Data register (ADCR0, ADCR1) is used to store result digital values generated from conversions.
ADCR0 stores the lower 8 bits and ADCR1 stores the highest 2 bits. These register values are updated
after completion of each conversion. Normally, the last conversion value is stored in these bits.
Bit10 to bit15 of ADCR1 always read "0".
There is a conversion data protection feature. See section "23.3 A/D Converter Operations".
■ A/D Conversion Time Setting Register (ADCT0, ADCT1)
Figure 23.2-7 A/D Conversion Time Setting Register (ADCT0, ADCT1)
A/D conversion time setting register - Upper byte
Address:
bit 15
000158H
CT5
Read/Write→ (R/W)
Initial value→
(0)
14
13
12
11
10
9
8
CT4
(R/W)
(0)
CT3
(R/W)
(0)
CT2
(R/W)
(1)
CT1
(R/W)
(0)
CT0
(R/W)
(0)
ST9
(R/W)
(0)
ST8
(R/W)
(0)
6
5
4
3
2
1
0
ST6
(R/W)
(0)
ST5
(R/W)
(1)
ST4
(R/W)
(0)
ST3
(R/W)
(1)
ST2
(R/W)
(1)
ST1
(R/W)
(0)
ST0
(R/W)
(0)
A/D conversion time setting register - Lower byte
Address:
bit 7
000159H
ST7
Read/Write→ (R/W)
Initial value→
(0)
A/D conversion time setting register (ADCT0, ADCT1) is used to control analog input sampling time
and comparison time. Use this register to set the A/D conversion time.
Do not change ADCT0 or ADCT1 setting while the A/D conversion is in progress.
440
CHAPTER 23 A/D CONVERTER
[bit15 to bit10] CT5 to CT0 (A/D compare time set)
• These bits are used to specify the clock division value of the comparison time.
• When the CT5 to CT0 are set to "000001B" (01H), there is no division (= CLKP).
• Do not set the CT5 to CT0 to "000000B" (00H).
• Upon reset, these bits are initialized to "000100B" (04H).
Comparison time = CT setting value × CLKP cycle × 10 + 4CLKP
Note: Ensure that the comparison time does not exceed 500μs.
[bit9 to bit0] ST9 to ST0 (Analog input sampling time set)
• These bits are used to specify the sampling time of the analog inputs.
• Upon reset, these bits are initialized to "0000101100B" (02CH).
Sampling time = ST setting value × CLKP cycle
Note: Ensure the sampling time is not 1.375μs or less.
• Use the following formula to calculate the required sampling time and ST setting time.
Required sampling time (Tsamp) = (Rext + Rin) × Cin × 7
Setting values from ST9 to ST0 = required sampling time (Tsamp) / CLKP cycle
• Set the ST values so that the A/D sampling time is longer than the required sampling time.
e.g.When clock is 32MHz, AVCC = 4.5V or higher, and Rext = 200kΩ
Tsamp = (200 × 103 + 2.52 × 103) × 10.7 × 10-12 × 7
= approx. 15.17μs
ST = 15.17- 6 ÷ 31.25- 9 = 485.44
= 486 (1E6H) Set the ST value to this or higher.
• Since the required sampling time is determined by the Rext value, consider the conversion time
when determining the Rext.
• It is prohibited to set the following values to ST9 to ST0; "0000000010"(02H), "0000000001" (01H),
"0000000000"(00H).
Always set the value to 3 or more.
441
CHAPTER 23 A/D CONVERTER
■ Recommended Setting Values
In order to achieve the optimal conversion time, we recommend setting as follows:
(AVCC = 4.5V or higher, Rext = 15kΩ or lower).
CLKP (MHz)
Comparison time (CT5 to CT0)
Sampling time (CT5 to CT0)
Conversion time (ms)
16
000010B (02H)
0000010110B (016H)
1.375 + 1.500 = 2.875
32
000100B (04H)
0000101100B (02CH)
1.375 + 1.375 = 2.750
■ A/D Start/End Channel Setting Register (ADSCH, ADECH)
Figure 23.2-8 A/D Start/End Channel Setting Register (ADSCH, ADECH)
A/D Start channel setting register
Address:
bit 15
00015AH
Read/Write→
(-)
Initial value→
(-)
14
(-)
(-)
13
(-)
(-)
12
ANS4
(R/W)
(0)
11
ANS3
(R/W)
(0)
10
ANS2
(R/W)
(0)
9
ANS1
(R/W)
(0)
8
ANS0
(R/W)
(0)
A/D End channel setting register
Address:
bit 7
00015BH
Read/Write→
(-)
Initial value→
(-)
6
(-)
(-)
5
(-)
(-)
4
ANE4
(R/W)
(0)
3
ANE3
(R/W)
(0)
2
ANE2
(R/W)
(0)
1
ANE1
(R/W)
(0)
0
ANE0
(R/W)
(0)
This register is used to set the A/D conversion start channel and the end channel.
Do not change ADSCH and ADECH configuration while the A/D conversion is in progress.
• These bits are used to set the A/D conversion start channel and the end channel.
• If the channel with ANS4 to ANS0 and the channel with ANE4 to ANE0 are the same, only one
channel will be converted (Single conversion).
• If set to the Continuous mode or Stop mode, the system returns to the start channel specified with
ANS4 to ANS0 upon completion of conversion of the specified channels with these bits.
• If the specified channels are ANS>ANE, conversion starts from ANS, converts through 31 channels,
returns to the 0 channel, and then continues to ANE.
• Upon reset, these bits are initialized as follows: ANS=00000B, ANE=00000B.
e.g. When the channels are set to ANS = 6ch, ANE = 3ch; in Single mode, the conversion will take
place in the following order:
6 channels → 7 channels → 8 channels → ⋅⋅⋅ → 31 channels → 0 channel →
1 channel → 2 channels → 3 channels
442
CHAPTER 23 A/D CONVERTER
[bit12 to bit8] ANS4 to ANS0 (Analog start channel set)
[bit4 to bit0] ANE4 to ANE0 (Analog end channel set)
ANS4
ANE4
ANS3
ANE3
ANS2
ANE2
ANS1
ANE1
ANS0
ANE0
Start/End channel
0
0
0
0
0
AN0
0
0
0
0
1
AN1
0
0
0
1
0
AN2
0
0
0
1
1
AN3
0
0
1
0
0
AN4
0
0
1
0
1
AN5
0
0
1
1
0
AN6
0
0
1
1
1
AN7
0
1
0
0
0
AN8
0
1
0
0
1
AN9
0
1
0
1
0
AN10
0
1
0
1
1
AN11
0
1
1
0
0
AN12
0
1
1
0
1
AN13
0
1
1
1
0
AN14
0
1
1
1
1
AN15
1
0
0
0
0
AN16
1
0
0
0
1
AN17
1
0
0
1
0
AN18
1
0
0
1
1
AN19
1
0
1
0
0
AN20
1
0
1
0
1
AN21
1
0
1
1
0
AN22
1
0
1
1
1
AN23
1
1
0
0
0
AN24
1
1
0
0
1
AN25
1
1
0
1
0
AN26
1
1
0
1
1
AN27
1
1
1
0
0
AN28
1
1
1
0
1
AN29
1
1
1
1
0
AN30
1
1
1
1
1
AN31
443
CHAPTER 23 A/D CONVERTER
23.3
A/D Converter Operations
Three mode types, the single conversion, continuous conversion, and stop conversion
modes are available for the 8/10-bit A/D converter.
This section describes the A/D converter operations.
■ A/D Converter Operations
This A/D converter performs the sequential compare conversion and offers 10-bit or 8-bit resolution
choices.
Since this A/D converter contains one register (16 bits) to store conversion results, the conversion
register (ADCR0, ADCR1) is updated after completion of each conversion. Therefore, using the A/D
converter alone is not sufficient for the Continuous conversion. We recommend using DMA to transfer
conversion data to memory in such mode. The following describes operation modes available.
■ Single Mode
In Single mode, the A/D converter converts the analog inputs specified with ANS and ANE bits
sequentially, and stops upon completion of conversion for the end channel specified with ANE bit. If
the start channel and the end channel are the same (ANS = ANE), only one channel is converted.
[Example]
• ANS = 00000B, ANE = 00011B
Start → AN0 → AN1 → AN2 → AN3 → End
• ANS = 00010B, ANE = 00010B
Start → AN2 → End
■ Continuous Mode
In Continuous mode, the A/D converter converts the analog inputs specified with ANS and ANE bits
sequentially, returns to the analog input with ANS upon completion of conversion for the end channel
specified with ANE bit, and then repeats. If the start channel and the end channel are the same (ANS =
ANE), then only one channel is converted repeatedly.
[Example]
• ANS = 00000B, ANE = 00011B
Start → AN0 → AN1 → AN2 → AN3 → AN0 ⎯⎯→ Repeat
• ANS = 010B, ANE = 010B
Start → AN2 → AN2 → AN2 ⎯⎯→ Repeat
In Continuous mode, the conversion repeats until "0" is written to the BUSY bit (Writing "0" to the
BUSY bit forces abort). Note that the conversion may stop before completion when you forced abort (in
the conversion register, the previous data is stored instead of the data in progress).
444
CHAPTER 23 A/D CONVERTER
■ Stop Mode
In Stop mode, the A/D converter converts the analog inputs specified with ANS and ANE bits
sequentially. It pauses after each conversion. To disable pause, trigger activation again.
After the conversion is completed for the end channel specified with the ANE bit, the system returns to
the analog inputs with ANS and continue. If the start channel and the end channel are the same (ANS =
ANE), then only one channel is converted.
[Example]
• ANS = 00000B, ANE = 00011B
Start → AN0 → Pause → Start → AN1 → Pause → Start → AN2 → Pause
→ Start → AN3 → Pause → Start → AN0 ⎯⎯→ Repeat
• ANS = 010B, ANE = 010B
Start → AN2 → Pause → Start → AN2 → Pause → Start → AN2
→ Repeat
Valid activation factors in these cases are only the ones specified with STS1 and STS0.
In this mode, the start of conversion may be synchronized.
Note:
Reactivations during the A/D conversion are enabled when A/D conversion mode selection bits
(MD1 and MD0) are set to "00B". In this mode, only software activation (STS1 and STS0 = 00B) can
be selected. To perform a reactivation, follow the procedure below:
1. Clear the INT bit to "0".
2. Write "1" to the STRT bit at the same time as writing "0" to the INT bit.
445
CHAPTER 23 A/D CONVERTER
446
CHAPTER 24
C_CAN
This chapter describes functions and operations of the
C_CAN.
24.1 Features of the C_CAN
24.2 C_CAN Register Function
24.3 C_CAN Function
447
CHAPTER 24 C_CAN
24.1
Features of the C_CAN
The C_CAN complies with the CAN protocol version 2.0 parts A and B, a standard CAN
protocol for serial communication that is widely used for areas such as automobile
industry or FA.
■ Features of the C_CAN
The C_CAN has following features:
•
Support for controller area network (CAN) protocol version 2.0 parts A and B
•
Bit rates up to 1 Mbps
•
Each message object has its own ID mask
•
Programmable first-in first-out (FIFO) mode
•
Maskable interrupt
•
Programmable loop-back mode for self-test operation
•
Read and write the message buffer using the interface register
■ Block Diagram of the C_CAN
Figure 24.1-1 shows the block diagram of the C_CAN.
Figure 24.1-1 Block Diagram of the C_CAN
CAN_TX CAN_RX
C_CAN
Message RAM
Message handler
CAN controller
Register group
448
Interrupt
Data-OUT
Data-IN
Address[7:0]
Control
Reset
Clock
CPU interface
CHAPTER 24 C_CAN
CAN Controller
Controls the CAN protocol and the serial register for serial/parallel conversion for message
transmission.
Message RAM
Stores message objects.
Register Group
All the registers used for the C_CAN.
Message Handler
Controls the message RAM and the CAN controller.
CPU Interface
Controls the interface of the internal bus of the FR family.
449
CHAPTER 24 C_CAN
24.2
C_CAN Register Function
The address space of 256 bytes (or 64 words) is allocated for the CAN register and both
the byte-access and word-access are possible. CPU access to the message RAM is
performed via the message interface register.
This section describes CAN registers as well as their detailed functions.
■ CAN Register Types
● Total Control Register
•
CAN control register (CTRLR)
•
CAN status register (STATR)
•
CAN error counter (ERRCNT)
•
CAN bit timing register (BTR)
•
CAN interrupt register (INTR)
•
CAN test register (TESTR)
•
CAN prescaler extended register (BRPER)
● Message Interface Register
•
IFx command request register (IFxCREQ)
•
IFx command mask register (IFxCMSK)
•
IFx mask register 1, 2 (IFxMSK1, IFxMSK2)
•
IFx arbitration register 1, 2 (IFxARB1, IFxARB2)
•
IFx message control register (IFxMCTR)
•
IFx data register A1, A2, B1, B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2)
● Message Handler Register
•
CAN transmission request register 1, 2 (TREQR1, TREQR2)
•
CAN new data register 1, 2 (NEWDT1, NEWDT2)
•
CAN interrupt pending register 1, 2 (INTPND1, INTPND2)
•
CAN message valid register 1, 2 (MSGVAL1, MSGVAL2)
● Prescaler Register
•
450
CAN clock prescaler register (CANPRE)
CHAPTER 24 C_CAN
■ Total Control Register List
Table 24.2-1 Total Control Register List
Register
Address
Note
+0
+1
CAN control register
(CTRLR)
Base - addr +
020000H
+2
CAN status register
(STATR)
bit [15:8]
bit [7:0]
bit [15:8]
Reserved bits
See ■CAN
Control Register
(CTRLR).
Reserved bits
Reset: 00H
Reset: 01H
Reset: 00H
CAN error counter
(ERRCNT)
Base - addr +
020004H
bit [15:8]
STAR:
See ■CAN Status BOff, EWarn, EPass = Read only
RxOk, TxOk, LEC = Read/Write
Register
(STATR).
Reset: 00H
ERRCNT: Read only
bit [7:0]
bit [15:8]
bit [7:0]
RP, REC [6:0]
TEC [7:0]
TSeg2 [2:0],
TSeg1 [3:0]
SJW [1:0], BRP
[5:0]
Reset: 00H
Reset: 00H
Reset: 23H
Reset: 01H
BTR:
Writable at Init (CTLR) = CCE
(CTRLR) = 1
CAN test register
(TESTR)
bit [15:8]
bit [7:0]
bit [15:8]
bit [7:0]
IntId [15:8]
IntId [7:0]
Reserved bits
See ■CAN Test
Register
(TESTR).
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H &
0br0000000H
CAN prescaler extended
register (BRPER)
Base - addr +
02000CH
bit [7:0]
CAN bit timing
register (BTR)
CAN interrupt register
(INTR)
Base - addr +
020008H
+3
INTR: Read only
TESTR:
Writable at Test (CTRLR) = 1
"Rx" indicates the level value of
the CAN_RX pin.
Reserved bits
bit [15:8]
bit [7:0]
bit [15:8]
bit [7:0]
Reserved bits
BRP [3:0]
-
-
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
BRP:
Writable at CCE (CTRLR) = 1
451
CHAPTER 24 C_CAN
■ Message Interface Register List
Table 24.2-2 Message Interface Register List (1/2)
Register
Address
Note
+0
Base - addr +
020010H
+1
IF1 command mask register
(IF1CMSK)
bit [15:8]
bit [15:8]
bit [7:0]
bit [7:0]
Busy
Mess, No. [5:0]
Reserved bits
See ■IFx
Command Mask
Register
(IFxCMSK).
Reset: 00H
Reset: 01H
Reset: 00H
Reset: 00H
bit [7:0]
bit [15:8]
bit [7:0]
MXtd. MDir,
Msk [28:24]
Msk [23:16]
Msk [15:8]
Msk [7:0]
Reset: FFH
Reset: FFH
Reset: FFH
Reset: FFH
bit [15:8]
bit [7:0]
bit [15:8]
bit [7:0]
MsgVal, Xtd, Dir,
ID [28:24]
ID [23:16]
ID [15:8]
ID [7:0]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
Base - addr +
020020H
452
−
Reserved bits
bit [15:8]
bit [7:0]
bit [15:8]
bit [7:0]
See ■IFx
Message Control
Register
(IFxMCTR).
See ■IFx
Message Control
Register
(IFxMCTR).
-
-
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
IF1 data A register 1
(IF1DTA1)
−
IF1 arbitration
register 1 (IF1ARB1)
IF1 message control
register (IF1MCTR)
Base - addr +
02001CH
−
IF1 mask register 1
(IF1CMSK1)
bit [15:8]
IF1 arbitration
register 2 (IF1ARB2)
Base - addr +
020018H
+3
IF1 command request register
(IF1CREQ)
IF1 mask register 2
(IF1CMSK2)
Base - addr +
020014H
+2
−
IF1 data A register 2
(IF1DTA2)
bit [7:0]
bit [15:8]
bit [7:0]
bit [15:8]
Data [0]
Data [1]
Data [2]
Data [3]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
Byte arrangement order:
Big endian
CHAPTER 24 C_CAN
Table 24.2-2 Message Interface Register List (2/2)
Register
Address
Note
+0
+1
IF1 data B register 1
(IF1DTB1)
Base - addr +
020024H
IF1 data B register 2
(IF1DTB2)
bit [15:8]
bit [7:0]
bit [15:8]
Data [4]
Data [5]
Data [6]
Data [7]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
Byte arrangement order:
Big endian
IF1 data A register 1
(IF1DTA1)
bit [15:8]
bit [7:0]
bit [15:8]
bit [7:0]
Data [3]
Data [2]
Data [1]
Data [0]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
IF1 data B register 2
(IF1DTB2)
Base - addr +
020034H
+3
bit [7:0]
IF1 data A register 2
(IF1DTA2)
Base - addr +
020030H
+2
Byte arrangement order:
Little endian
IF1 data B register 1
(IF1DTB1)
bit [15:8]
bit [7:0]
bit [15:8]
bit [7:0]
Data [7]
Data [6]
Data [5]
Data [4]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
Byte arrangement order:
Little endian
453
CHAPTER 24 C_CAN
■ Message Interface Register List
Table 24.2-3 Message Interface Register List (1/2)
Register
Address
Note
+0
Base addr +
020040H
+1
IF2 command mask register
(IF2CMSK)
bit [15:8]
bit [15:8]
bit [7:0]
bit [7:0]
Busy
Mess, No. [5:0]
Reserved bits
See ■IFx
Command Mask
Register
(IFxCMSK).
Reset: 00H
Reset: 01H
Reset: 00H
Reset: 00H
bit [7:0]
bit [15:8]
bit [7:0]
MXtd. MDir,
Msk [28:24]
Msk [23:16]
Msk [15:8]
Msk [7:0]
Reset: FFH
Reset: FFH
Reset: FFH
Reset: FFH
bit [15:8]
bit [7:0]
bit [15:8]
bit [7:0]
MsgVal, Xtd, Dir,
ID [28:24]
ID [23:16]
ID [15:8]
ID [7:0]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
Base - addr +
020050H
454
−
Reserved bits
bit [15:8]
bit [7:0]
bit [7:0]
bit [15:8]
See ■IFx
Message Control
Register
(IFxMCTR).
See ■IFx
Message Control
Register
(IFxMCTR).
-
-
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
IF2 data A register 1
(IF2DTA1)
−
IF2 arbitration
register 1 (IF2ARB1)
IF2 Massage control register
(IF2MCTR)
Base - addr +
02004CH
−
IF2 mask register 1
(IF2CMSK1)
bit [15:8]
IF2 arbitration
register 2 (IF2ARB2)
Base - addr +
020048H
+3
IF2 command request register
(IF2CREQ)
IF2 mask register 2
(IF2CMSK2)
Base - addr +
020044H
+2
−
IF2 data A register 2
(IF2DTA2)
bit [7:0]
bit [15:8]
bit [7:0]
bit [15:8]
Data [0]
Data [1]
Data [2]
Data [3]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
Byte arrangement order:
Big endian
CHAPTER 24 C_CAN
Table 24.2-3 Message Interface Register List (2/2)
Register
Address
Note
+0
+1
IF2 data B register 1
(IF2DTB1)
Base - addr +
020054H
IF2 data B register 2
(IF2DTB2)
bit [15:8]
bit [7:0]
bit [15:8]
Data [4]
Data [5]
Data [6]
Data [7]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
Byte arrangement order:
Big endian
IF2 data A register 1
(IF2DTA1)
bit [15:8]
bit [7:0]
bit [15:8]
bit [7:0]
Data [3]
Data [2]
Data [1]
Data [0]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
IF2 data B register 2
(IF2DTB2)
Base - addr +
020064H
+3
bit [7:0]
IF2 data A register 2
(IF2DTA2)
Base - addr +
020060H
+2
Byte arrangement order:
Little endian
IF2 data B register 1
(IF2DTB1)
bit [15:8]
bit [7:0]
bit [15:8]
bit [7:0]
Data [7]
Data [6]
Data [5]
Data [4]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
Byte arrangement order:
Little endian
455
CHAPTER 24 C_CAN
■ Massage Handler Register List
Table 24.2-4 Massage Handler Register List
Register
Address
Note
+0
+1
CAN transmission request register 2
(TREQR2)
Base - addr +
020080H
Base - addr +
020084H
Base - addr +
020094H
Base - addr +
0200A4H
bit [15:8]
bit [7:0]
TxRqst [32:25]
TxRqst [24:17]
TxRqst [16:9]
TxRqst [8:1]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
Reserved area to support 32 message buffers or more
(See "■CAN Transmission Request Register (TREQR1, TREQR2)").
Base - addr +
0200B4H
456
INTR1, INTR2: Read only
−
CAN New Data register 1
(NEWDT1)
bit [15:8]
bit [7:0]
bit [15:8]
bit [7:0]
NewDat [32:25]
NewDat [24:17]
NewDat [16:9]
NewDat [8:1]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
Reserved area to support 32 message buffers or more
(See "■CAN New Data Register 1, 2 (NEWDT1, NEWDT2)").
NEWDT1, NEWDT2:
Read only
−
CAN interrupt pending
register 1 (INTPND1)
bit [15:8]
bit [7:0]
bit [15:8]
bit [7:0]
IntPnd [32:25]
IntPnd [24:17]
IntPnd [16:9]
IntPnd [8:1]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
Reserved area to support 32 message buffers or more
(See "■CAN Interrupt Pending Register (INTPND1, INTPND2)").
CAN message valid
register 2 (MSGVAL2)
Base - addr +
0200B0H
CAN transmission request register 1
(TREQR1)
bit [7:0]
CAN interrupt pending
register 2 (INTPND2)
Base - addr +
0200A0H
+3
bit [15:8]
CAN New Data register 2
(NEWDT2)
Base - addr +
020090H
+2
INTPND1, INTPND2:
Read only
−
CAN message valid
register 1 (MSGVAL1)
bit [15:8]
bit [7:0]
bit [15:8]
bit [7:0]
MsgVal [32:25]
MsgVal [24:17]
MsgVal [16:9]
MsgVal [8:1]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
Reserved area to support 32 message buffers or more
(See "■CAN Message Valid Register (MSGVAL1, MSGVAL2)").
MSGVAL1, MSGVAL2:
Read only
−
CHAPTER 24 C_CAN
■ Clock Prescaler Register
Table 24.2-5 Clock Prescaler Register
Register
Address
0001A8H
Note
+0
+1
+2
+3
CANPRE
-
-
-
bit [3:0]
-
-
-
CANPRE [3:0]
-
-
-
Reset: 00H
-
-
-
CAN Prescaler
457
CHAPTER 24 C_CAN
24.2.1
Total Control Register
The total control register controls the CAN protocol and operation mode and provides
status information.
■ CAN Control Register (CTRLR)
Figure 24.2-1 Bit Configuration of CAN Control Register (CTRLR)
CAN control register (upper bytes)
bit
15
14
13
12
11
10
9
8
Address: ch.0 020000H
ch.1 020100H
Read/Write
Initial value
—
—
—
—
—
—
—
—
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
7
6
5
4
3
2
1
0
Test
CCE
DAR
—
EIE
SIE
IE
Init
(R/W)
(R/W)
(R)
(R/W)
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(1)
CAN control register (lower bytes)
bit
Address: ch.0 020001H
ch.1 020101H
Read/Write (R/W)
Initial value
(0)
This register controls the operation mode of the CAN controller.
[bit15 to bit8] (Reserved bits)
For the reserved bits, "0"s are read. Set them to "0" when writing to them.
[bit7] Test: Test mode enable bit
Test
Function
0
Normal operation [Initial value]
1
Test mode
[bit6] CCE: Bit timing register write enable bit
CCE
458
Function
0
Disables writing to the CAN bit timing register and CAN prescaler extended register.
[Initial value]
1
Enables writing to the CAN bit timing register and CAN prescaler extended register. It is
valid when the Init bit is set to "1".
CHAPTER 24 C_CAN
[bit5] DAR: Automatic retransmission disable bit
DAR
Function
0
Enables messages to be resent automatically when losing the arbitration or detecting an error.
[Default]
1
Disables automatic retransmission
The CAN controller automatically retransmit frames when losing the arbitration or detecting an error
during transmission, according to the CAN specifications (see the section of "ISO11898, 6.3.3 Recovery
processing"). If automatic retransmission is to be performed, set the DAR bit to "0". For the CAN to be
operated under the Time Triggered CAN (TTCAN, see the section of "ISO 11898-1") environment, the
DAR bit must be set to "1".
Note: In the mode where the DAR bit is set to "1", the TxRqst bit and the NewDat bit of the message
object behave differently (For the description of message objects, see "■Message Object" in the
section "24.2.2 Message Interface Register").
•
At the start of frame transmission, the TxRqst bit of the message object is reset to "0",
while the NewDat bit remains to be set as it is.
•
The NewDat bit is reset to "0" after successfully completing the frame transmission.
If the transmission is lost in the arbitration or an error is detected during transmission, the
NewDat remains set. To resume the transmission, TxRqst must be set to "1" by the CPU.
[bit4] (Reserved bit)
For the reserved bit, "0" is read. Set it to "0" when writing to it.
[bit3] EIE: Error interrupt code enable bit
EIE
Function
0
Disables the interrupt code to be set in the CAN interrupt register, depending on the changes
of the Boff or EWarn bits in the CAN status register.
[Initial value]
1
Enables the interrupt code to be set in the CAN interrupt register, depending on the changes of
the Boff or EWarn bits in the CAN status register.
[bit2] SIE Status interrupt code enable bit
SIE
Function
0
Disables the interrupt code to be set in the CAN status register, depending on the changes of
the TxOk, RxOk, or LEC bits in the CAN status register. [Initial value]
1
Enables the interrupt code to be set in the CAN interrupt register, depending on the changes
of TxOk, RxOk, or LEC bits in the CAN status register. Changes made to the TxOk, RxOk,
or LEC bits by writing from the CPU do not reflect on the setting of the CAN interrupt
register.
459
CHAPTER 24 C_CAN
[bit1] IE: Interrupt enable bit
IE
Function
0
Disables interrupt event. [Initial value]
1
Enables interrupt event.
[bit0] Init: Initialize bit
Init
Function
0
CAN controller is able to operate.
1
Performs initialization. [Initial value]
Notes:
• The Bus Off recovery sequence (see the section of "CAN Specification Rev. 2.0") cannot be
shortened by setting or resetting Init. If the device goes Bus-Off, the CAN controller itself will set
Init to "1", stopping all the bus operations. Once the Init bit is to be cleared to "0" in Bus-Off status,
the bus will remain inactive until Bus Idle occurs 129 consecutive times (a sequence of 11
recessive bits is counted as one occurrence of Bus Idle) before resuming normal operations. At
the end of the Bus-Off recovery sequence, the error counters will be reset.
• To write in the CAN bit timing register, set the Init and the CCE bit to "1".
• Before shifting to low-power consumption mode (stop mode, clock mode), initialize the CAN
controller by writing "1" in the Init bit.
• When changing the frequency division ratio of the clock signal supplied to the CAN interface via
the CAN prescaler register, first set the Init bit to "1" before changing the CAN prescaler register.
460
CHAPTER 24 C_CAN
■ CAN Status Register (STATR)
Figure 24.2-2 Bit Configuration of CAN Status Register (STATR)
CAN status register (upper byte)
bit
Address: ch.0 020002H
ch.1 020102H
Read/Write
Initial value
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
6
5
4
3
2
1
0
RxOk
TxOk
(R/W)
(0)
(R/W)
(0)
CAN status register (lower byte)
bit
Address:
ch.0 020003H
ch.1 020103H
Read/Write
Initial value
7
BOff
Ewarn EPass
(R)
(0)
(R)
(0)
(R)
(0)
LEC
(R/W)
(0)
(R/W)
(0)
(R/W)
(1)
This register displays the CAN status and the status of the CAN bus.
[bit15 to bit8] Reserved bits
For the reserved bits, "0"s are read. Set them to "0" when writing to them.
[bit7] BOff: Bus Off bit
BOff
Function
0
Indicates that the CAN controller is not in the Bus-Off state.
[Initial value]
1
Indicates that the CAN controller is in the Bus-Off state.
[bit6] Ewarn: Warning bit
Ewarn
Function
0
Indicates that both the send and receive counters show the values less than 96.
[Initial value]
1
Indicates that either the send counter or the receive counter shows the value of 96 or more.
461
CHAPTER 24 C_CAN
[bit5] Epass: Error passive bit
EPass
Function
0
Indicates that both the transmit and receive counters show the values less than 128 (error
active state). [Initial value]
1
Indicates that the receive counter is the RP bit =1, and the send counter shows a value of 128
or more (error passive state).
[bit4] RxOk: Message normal reception bit
RxOk
Function
0
Indicates that messages are not transmitted normally on the CAN bus, or it implies the bus
idle state. [Initial value]
1
Indicates that messages were transmitted normally on the CAN bus,
[bit3] TxOk: Message normal transmission bit
TxOk
Function
0
Indicates that bus is in idle state, or messages are not transmitted normally. [Initial value]
1
Indicates that messages were transmitted normally.
Note:
The RxOk and TxOk bits can only be reset by the CPU.
462
CHAPTER 24 C_CAN
[bit2 to bit0] LEC: Last error code bits
LEC
Status
Function
0
Normal
1
Stuff error
Indicates that more than 6 consecutive dominant or recessive bits have been
detected in the message.
2
Form error
Indicates that the fixed format part of the received frame has been erroneously
detected.
3
Ack error
Indicates that the sent message has not been acknowledged by other nodes.
4
bit1 error
Indicates that a dominant bit has been detected in the transmission data of the
message excluding the arbitration field, even though the recessive bit has been
sent.
5
bit0 error
Indicates that the recessive bit has been detected in the transmission data of the
message, even though the dominant bit has been sent. During the bus recovery,
this error is set every time a sequence of 11 recessive bits is detected. The bus
recovery sequence can be monitored by reading out these bits.
6
CRC error
Indicates that the CRC data in the received message did not match the result of
the CRC calculation.
7
Non-detected
Indicates that no transmission or reception has been made since writing "7" in the
LEC bit by the CPU until reading the LEC value of "7" (Bus idle state).
Indicates that messages were sent or received normally.
[Initial value]
The LEC bit retains the code indicating the last error that has occurred on the CAN bus. It is to be
cleared to "0" when the transmission of the message completes without error. Non-detected code "7" is
set by the CPU to check code updates.
Notes:
• Status interrupt code (8000H) is set to the CAN interrupt register if the BOff or EWarn bit changes
when the EIE bit is "1", or if the RxOk, TxOk, or LEC bit changes when the SIE bit is "1".
• Since the RxOk and TxOk bits are updated by writing by the CPU, RxOk and TxOk bits that have
been set by the CAN controller will be lost. If the RxOk or TxOk bit is to be used, clear it within (45
× BT) hours after the RxOk or TxOk bit is set to "1". "BT" represents one bit time.
• If an interrupt occurs because of the LEC bit change when the SIE bit is "1", no data should be
written in the CAN status register.
• An interrupt does not occur from the EPass bit change or from writing operation by the CPU in the
RxOk, TxOk, or LEC bit.
• Even if the BOff or EPass bit becomes "1", the EWarn bit will be set to "1".
• By reading this register, the status interrupt code (8000H) in the CAN interrupt register is to be
cleared.
463
CHAPTER 24 C_CAN
■ CAN Error Counter (ERRCNT)
Figure 24.2-3 Bit Configuration of CAN Error Counter (ERRCNT)
CAN error counter register (upper byte)
bit
15
Address: ch.0 020004H
ch.1 020104H
RP
Read/Write
Initial value
(R)
(0)
14
13
12
11
10
9
8
REC6 to REC0
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
5
4
3
2
1
0
(R)
(0)
(R)
(0)
(R)
(0)
CAN error counter register (lower byte)
bit
Address: ch.0 020005H
ch.1 020105H
Read/Write
Initial value
7
6
TEC7 to TEC0
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
This register shows the receive error passive state, receive error counter, and send error counter.
[bit15] RP: Receive error passive display
RP
Function
0
Indicates that the receive error counter is not in the error passive state. [Initial value]
1
Indicates that the receive error counter reaches the error passive state as defined in the CAN
Specifications.
[bit14 to bit8] REC6 to REC0: Receive error counter
Value of the receive error counter. The value of the receive error counter ranges from 0 to 127.
[bit7 to bit0] TEC7 to TEC0: Send error counter
Value of the send error counter. The value of the send error counter ranges from 0 to 255.
464
CHAPTER 24 C_CAN
■ CAN Bit Timing Register (BTR)
Figure 24.2-4 Bit Configuration of CAN Bit Timing Register (BTR)
CAN bit timing register (upper byte)
bit
15
Address: ch.0 020006H
ch.1 020106H
Read/Write
Initial value
−
(R)
(0)
14
13
12
11
10
TSeg2
(R/W)
(0)
9
8
TSeg1
(R/W)
(1)
(R/W)
(0)
(R)
(0)
(R)
(0)
(R)
(1)
(R)
(1)
5
4
3
2
1
0
(R/W)
(0)
(R/W)
(0)
(R/W)
(1)
CAN bit timing register (lower byte)
bit
7
6
Address: ch.0 020007H
SJW
ch.1 020107H
Read/Write (R/W) (R/W)
Initial value
(0)
(0)
BRP
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
This register is used to set the prescaler and bit timing.
[bit15] (Reserved bit)
For the reserved bit, "0" is read. Set it to "0" when writing to it.
[bit14 to bit12] TSeg2: Time segment 2 setting bits
The valid setting value ranges from 0 to 7. The value of TSeg2 + 1 will be the time segment 2.
The time segment 2 corresponds to the phase buffer segment (PHASE_SEG2) according to the CAN
Specification.
[bit11 to bit8] TSeg1: Time segment 1 setting bits
The valid setting value ranges from 1 to 15. "0" cannot be set. The value of TSeg1 + 1 will be the time
segment 1.
The time segment 1 corresponds to the propagation segment (PROP_SEG) + phase buffer segment 1
(PHASE_SEG1) according to the CAN Specification.
[bit7, bit6] SJW: Resynchronization jump width setting bits
The valid setting value ranges from 0 to 3. The value of (SJW + 1) will be a resynchronization jump
width.
[bit5 to bit0] BRP: Baud rate prescaler setting bits
The valid setting value ranges from 0 to 63. The value of (BRP + 1) will be a baud rate prescaler.
The system clock (fsys) is divided to determine the basic unit time (tq) for the CAN controller.
465
CHAPTER 24 C_CAN
Note:
The CAN bit timing register and CAN prescaler extended register should be set when the CCE bit
and Init bit of the CAN control register are set to "1".
■ CAN Interrupt Register (INTR)
Figure 24.2-5 Bit Configuration of CAN Interrupt Register (INTR)
CAN interrupt register (upper byte)
bit
15
14
13
Address: ch.0 020008H
ch.1 020108H
Read/Write
Initial value
12
11
10
9
8
IntId15 to IntId8
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
6
5
4
3
2
1
0
(R)
(0)
(R)
(0)
(R)
(0)
CAN interrupt register (lower byte)
bit
Address: ch.0 020009H
ch.1 020109H
Read/Write
Initial value
7
IntId7 to IntId0
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
This register shows the message interrupt code and status interrupt code.
[bit15 to bit0] IntId15 to IntId0
IntId
0000H
Function
No interrupt
0001H to 0020H
The interrupt factor indicates the number of the message object (Message interrupt code).
0021H to 7FFFH
Not used.
8000H
8001H to FFFFH
Indicates the interrupt because of the change of the CAN status register (Status interrupt code).
Not used.
If multiple interrupt codes are pending, the code having higher priority is shown in the CAN interrupt
register. If a new interrupt code with higher priority is generated while another interrupt code with
lower priority has already been set in the CAN interrupt register, the CAN interrupt register is updated
to set the new code.
The order of priority for interrupt codes is: status interrupt code (8000H), message interrupt code
(0001H, 0002H, 0003H, .. .. .. , 0020H), beginning from the highest.
If the IE bit of the CAN control register is set to "1", with the IntId bit being other than "0000H", the
interrupt signal to the CPU becomes active. If the value of IntId becomes "0000H" (the interrupt factor is
reset) or if the IE bit of the CAN control register is reset to "0", the interrupt signal will become inactive.
The message interrupt code is to be cleared by clearing the value of the bit of the target message object
to "0" (For description of the message object, see "■Message Object " in the section "24.2.2 Message
Interface Register ").
The status interrupt code is to be cleared by reading the CAN status register.
466
CHAPTER 24 C_CAN
■ CAN Test Register (TESTR)
Figure 24.2-6 Bit Configuration of CAN Test Register (TESTR)
CAN test register (upper byte)
bit
Address:
ch.0 02000AH
ch.1 02010AH
Read/Write
Initial value
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
7
6
5
4
3
2
1
0
Rx
Tx1
Tx0
LBack
Silent
Basic
-
-
(R)
(r)
(R/W)
(0)
(R/W)
(0)
(R)
(0)
(R/W)
(0)
(R/W)
(0)
(R)
(0)
(R)
(0)
CAN test register (lower byte)
bit
Address:
ch.0 02000BH
ch.1 02010BH
Read/Write
Initial value
This register sets the test mode and monitors status of the RX pin. For operations of the CAN test
register, see "■ Test Mode" in the section "24.3 C_CAN Function".
[bit15 to bit8] (Reserved bits)
For the reserved bits, "0"s are read. Set them to "0" when writing to them.
[bit7] Rx: Rx pin monitor bit
The initial value (r) of Rx (bit7) indicates the level on the CAN bus.
Rx
Function
0
Indicates that Can bus is dominant.
1
Indicates that Can bus is recessive.
[bit6, bit5] Tx1, Tx0: TX pin control bit
Tx1, Tx0
Function
00B
Normal operation [Initial value]
01B
The sampling point is output to the TX pin.
10B
Dominant status is output to the TX pin.
11B
Recessive status is output to the TX pin.
467
CHAPTER 24 C_CAN
[bit4] Lback: Loop back mode
LBack
Function
0
Disables loop back mode. [Initial value]
1
Enables loop back mode.
[bit3] Silent: Silent mode
Silent
Function
0
Disables silent mode. [Initial value]
1
Enables silent mode.
[bit2] Basic: Basic mode
Basic
Function
0
Disables basic mode. [Initial value]
1
Enables basic mode.
The IF1 register is used for send message and the IF2 register is used for receive message.
[bit1, bit0] (Reserved bits)
For the reserved bits, "0"s are read. Set them to "0" when writing to them.
Notes:
• Write in this register after setting the Test bit of the CAN control register to "1". The test mode is
enabled when the test bit of the CAN control register is "1". If the test bit of the CAN control
register is changed to "0" in the test mode, it enters the normal mode.
• If the Tx bit is set to the value other than "00B", a message cannot be transmitted.
468
CHAPTER 24 C_CAN
■ CAN Prescaler Extended Register (BRPER)
Figure 24.2-7 Bit Configuration of CAN Prescaler Extended Register (BRPER)
CAN prescaler extended register (upper byte)
bit
Address: ch.0 02000CH
ch.1 02010CH
Read/Write
Initial value
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
3
2
1
0
(R/W)
(0)
(R/W)
(0)
CAN prescaler extended register (lower byte)
bit
7
6
5
4
Address: ch.0 02000DH
ch.1 02010DH
Read/Write
Initial value
-
-
-
-
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
BRPE
(R/W)
(0)
(R/W)
(0)
This register extends the prescaler used in the CAN controller by combining with the prescaler set up
for CAN bit timing.
[bit15 to bit4] (Reserved bits)
For the reserved bits, "0"s are read. Set them to "0" when writing to them.
[bit3 to bit0] BRPE: Baud rate prescaler extension bits
By combining BRP of the CAN bit timing register and BRPE, the baud rate prescaler can be extended to
values up to 1023.
The value of the CAN controller prescaler is {BRPE (MSB: 4 bits), BRP (LSB: 6 bits)} + 1.
469
CHAPTER 24 C_CAN
24.2.2
Message Interface Register
Two pairs of message interface registers are provided for controlling accesses to
message RAM by the CPU.
■ Overview
There are two pairs of message interface registers to control CPU access to the message RAM. These
two pairs of registers avoid access conflict between access from the CPU and access from the CAN
controller to the message RAM by buffering the data (message object) to be transmitted (or, that have
been transmitted). The message object is transmitted between the message interface register and the
message RAM as batch process (For the description of message objects, see "■Message Object" in the
section "24.2.2 Message Interface Register").
Except for the test basic mode, functions of the two pairs of message interface registers are identical and
can be operated independently. For example, while IF1 message interface register is performing write
operation in the message RAM, IF2 message interface register can be used to read messages from the
message RAM. Table 24.2-6 illustrates configuration with two pairs of message interface registers.
The message interface register consists of command registers (command request register, command
mask register) and message buffer registers (mask register, arbitration register, message control register,
data register) that are controlled by these command registers. The command mask register indicates the
direction of the data transfer as well as which part of the message object to be transmitted. The
command request register selects message number and performs operations set to the command mask
register.
Table 24.2-6 IF1, IF2 Message Interface Registers
470
Address
IF1 register set
Address
IF2 register set
Base + 10H
IF1 command request
Base + 40H
IF2 command request
Base + 12H
IF1 command mask
Base + 42H
IF2 command mask
Base + 14H
IF1 mask 2
Base + 44H
IF2 mask 2
Base + 16H
IF1 mask 1
Base + 46H
IF2 mask 1
Base + 18H
IF1 arbitration 2
Base + 48H
IF2 arbitration 2
Base + 1AH
IF1 arbitration 1
Base + 4AH
IF2 arbitration 1
Base + 1CH
IF1 message control
Base + 4CH
IF2 message control
Base + 20H
IF1 data A1
Base + 50H
IF2 data A1
Base + 22H
IF1 data A2
Base + 52H
IF2 data A2
Base + 24H
IF1 data B1
Base + 54H
IF2 data B1
Base + 26H
IF1 data B2
Base + 56H
IF2 data B2
CHAPTER 24 C_CAN
■ IFx Command Request Register (IFxCREQ)
Figure 24.2-8 Bit Configuration of IFx Command Request Register (IFxCREQ)
IFx command request register (upper byte)
bit
Address: ch.0 020010H
ch.1 020110H
15
14
13
12
11
10
9
8
BUSY
-
-
-
-
-
-
-
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
5
4
3
2
1
0
(R/W)
(0)
(R/W)
(0)
Read/Write (R/W)
Initial value
(0)
IFx command request register (lower byte)
bit
7
Address: ch.0 020011H
ch.1 020111H
Read/Write (R/W)
Initial value
(0)
6
(R/W)
(0)
Message Number
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
This register selects a message number of the message RAM and transmits data between the message
RAM and the message buffer register. In the test basic mode, IF1 is used for controlling transmission
and IF2 is used for controlling reception.
As soon as the message number is written in the IFx command request register, message transmission
between the message RAM and the message buffer registers (mask, arbitration, message control, data
registers) starts. This write operation sets the BUSY bit to "1", indicating that transmission process is
going on. The BUSY bit is reset to "0" when the transmission completes.
If the CPU attempts to access the message interface register while the BUSY bit is "1", it has to wait
until the BUSY bit becomes "0" (for about three to six clock cycles after writing in the command
request register).
The BUSY bit is used differently in the test basic mode. The IF1 command request register is used for
transmit message and instructs to start message transmission by setting the BUSY bit to "1". The BUSY
bit is reset to "0" when the transmission successfully completes. Message transmission can be
interrupted any time by resetting the BUSY bit to "0".
The IF2 command request register is used for incoming messages and stores the received message in the
IF2 message interface register by setting the BUSY bit to "1".
471
CHAPTER 24 C_CAN
[bit15] BUSY: Busy flag bit
• In modes other than the test basic mode
BUSY
•
Function
0
Indicates that no data transmission is being handled between the message interface register
and the message RAM. [Initial value]
1
Indicates that data transmission is being handled between the message interface register and
the message RAM.
Test basic mode
- IF1 command request register
BUSY
-
Function
0
Disables message transmission.
1
Enables message transmission.
IF2 command request register
BUSY
Function
0
Disables message reception.
1
Enables message reception.
[bit14 to bit6] (Reserved bits)
For the reserved bits, "0"s are read. Set them to "0" when writing to them.
[bit5 to bit0] Message Number: Message number (for 32-message buffer CAN)
Message
Number
00H
Function
Setting is disabled. When set, it is interpreted as 20H, and which will be read.
01H to 20H
Sets the message number to be processed.
21H to 3FH
Setting is disabled. When set, it is interpreted as the current value from 01H to 1FH, and it
will be read.
[bit4 to bit0] Message Number: Message number (for 128-message buffer CAN)
Message
Number
00H
472
Function
Setting is disabled. When set, it is interpreted as 20H, and which will be read.
01H to 80H
Sets the message number to be processed.
81H to FFH
Setting is disabled. When set, it is interpreted as the current value from 01H to 1FH, and it
will be read.
CHAPTER 24 C_CAN
Note:
The BUSY bit can be read and written. Anything which is written in this bit, it doesn't affect the
operation as long as it is in the mode other than the test basic mode (For the basic mode, see
"■Test Mode" in the section "24.3 C_CAN Function").
■ IFx Command Mask Register (IFxCMSK)
Figure 24.2-9 Bit Configuration of IFx Command Mask Register (IFxCMSK)
IFx command mask register (upper byte)
bit
Address:
ch.0 020012H
ch.1 020112H
Read/Write
Initial value
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
5
4
3
2
1
0
IFx command mask register (lower byte)
bit
Address:
7
6
ch.0 020013H WR/RD Mask
ch.1 020113H
Read/Write (R/W)
Initial value (0)
(R/W)
(0)
Arb
Control
CIP
TxRqst/
NewDat
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Data A Data B
(R/W)
(0)
(R/W)
(0)
This register controls the data transfer direction between the message interface register and the message
RAM and sets which data will be updated. This register is disabled in the test basic mode.
[bit15 to bit8] (Reserved bits)
For the reserved bits, "0"s are read. Set them to "0" when writing to them.
[bit7] WR/RD: Read/Write control bit
WR/RD
Function
0
Indicates that data is read from the message RAM. Reading out from the message RAM is
executed by writing in the IFx command request register. Data reads out from the message
RAM depend on the configuration of Mask, Arb, Control, CIP, TxRqst/NewDat, Data A, and
Data B bits. [Initial value]
1
Indicates that data is written in the message RAM. Writing in the message RAM is executed
by writing in the IFx command request register. Data written in the message RAM depends
on the configuration of Mask, Arb, Control, CIP, TxRqst/NewDat, Data A, and Data B bits.
Note: The data in the message RAM after resetting is indeterminate. It is prohibited to read the data
from the message RAM when the data is indeterminate.
The bit6 to bit0 in the IFx command mask register mean differently, depending on the setting of the
transfer direction (WR/RD bit).
473
CHAPTER 24 C_CAN
● When the transfer direction is "write" (WR/RD =1)
[bit6] Mask: Mask data update bit
Mask
Function
0
Indicates that the mask data (ID mask + MDir + MXtd) in the message object * are not to be
updated. [Initial value]
1
Indicates that the mask data (ID mask + MDir + MXtd) in the message object * are updated.
*: See "■Message Object" in the section "24.2.2 Message Interface Register".
[bit5] Arb: Arbitration data update bit
Arb
Function
0
Indicates that the arbitration data (ID + Dir + Xtd + MsgVal) in the message object * are not
to be updated. [Initial value]
1
Indicates that the arbitration data (ID + Dir + Xtd + MsgVal) in the message object * is
updated.
*: See "■Message Object" in the section "24.2.2 Message Interface Register".
[bit4] Control: Control data update bit
Control
Function
0
Indicates that the control data (IFx message control register) of the message object *
is not to be updated. [Initial value]
1
Indicates that the control data (IFx message control register) of the message object * is
updated.
*: See "■Message Object" in the section "24.2.2 Message Interface Register".
[bit3] CIP: Interrupt clear bit
Setting this bit to "0" or "1" does not affect the behavior of the CAN controller.
474
CHAPTER 24 C_CAN
[bit2] TxRqst/NewDat: Message transmission request bit
TxRqst/NewDat
Function
0
Indicates that the TxRqst bit of CAN transmission request register and the message object *
are not to be changed. [Initial value]
1
Indicates that "1" is set (transmission request) to the TxRqst bit of the message object *
and CAN transmission request register.
*: See "■Message Object" in the section "24.2.2 Message Interface Register".
[bit1] Data A: Data0 to Data3 update bit
Data A
Function
0
Indicates that the data0 to data3 of the message object * is not to be updated. [Initial value]
1
Indicates that the data0 to data3 of the message object * is updated.
*: See "■Message Object" in the section "24.2.2 Message Interface Register".
[bit0] Data B: Data4 to Data7 update bit
Data B
Function
0
The data4 to data7 of the message object * is not to be updated. [Initial value]
1
The data4 to data7 of the message object * is updated.
*: See "■Message Object" in the section "24.2.2 Message Interface Register".
Notes:
• The setting of the TxRqst bit of the IFx message control register is disabled if the TxRqst/NewDat
bit of the IFx command mask register is set to "1".
• This register is disabled in the test basic mode.
475
CHAPTER 24 C_CAN
● When the transfer direction is "read" (WR/RD =0)
[bit6] Mask: Mask data update bit
Mask
Function
0
Indicates that the mask data (ID mask + MDir + MXtd) is not to be transferred from the
message object * to the IFx mask register 1 and 2. [Initial value]
1
Indicates that the mask data (ID mask + MDir + MXtd) is to be transferred from the message
object * to the IFx mask register 1 and 2.
*: See "■Message Object" in the section "24.2.2 Message Interface Register".
[bit5] Arb: Arbitration data update bit
Arb
Function
0
Indicates that the data (ID + Dir + Xtd + MsgVal) is not to be transferred from the message
object * to the IFx arbitration 1 and 2. [Initial value]
1
Indicates that the data (ID + Dir + Xtd + MsgVal) is to be transferred from the message
object * to the IFx arbitration 1 and 2.
*: See "■Message Object" in the section "24.2.2 Message Interface Register".
[bit4] Control: Control data update bit
Control
Function
0
Indicates that the data is not to be transferred from the message object * to the IFx message
control register. [Initial value]
1
Indicates that the data is to be transferred from the message object * to the IFx message
control register.
*: See "■Message Object" in the section "24.2.2 Message Interface Register".
[bit3] CIP: Interrupt clear bit
CIP
Function
0
Indicates that the IntPnd bit of the message object * and CAN interrupt pending register are
to be retained. [Initial value]
1
Indicates that the IntPnd bit of the message object * and CAN interrupt pending register are
to be cleared to "0".
*: See "■Message Object" in the section "24.2.2 Message Interface Register".
476
CHAPTER 24 C_CAN
[bit2] TxRqst/NewDat: Data update bit
TxRqst/
NewDat
Function
0
Indicates that the TxRqst bit of CAN transmission request register and the message object *
are not to be changed. [Initial value]
1
Indicates that the NewDat bit of the message object * and CAN data update register are to be
cleared to "0".
*: See "■Message Object" in the section "24.2.2 Message Interface Register".
[bit1] Data A: Data0 to Data3 update bit
Data A
Function
0
Indicates that the data in the message object * and CAN data register A1 and A2 are to be
retained. [Initial value]
1
Indicates that the data in the message object * and CAN data register A1 and A2 are updated.
*: See "■Message Object" in the section "24.2.2 Message Interface Register".
[bit0] Data B: Data4 to Data7 update bit
Data B
Function
0
Indicates that the data in the message object * and CAN data register B1 and B2 are to be
retained. [Initial value]
1
Indicates that the data in the message object * and CAN data register B1 and B2 are updated.
*: See "■Message Object" in the section "24.2.2 Message Interface Register".
Notes:
• The IntPnd and NewDat bits can be reset to "0" by accessing the message object to read.
However, the IntPnd and NewDat bits before resetting by read accessing are stored in the IntPnd
and NewDat bits of the IFx message control register.
• This setting is disabled in the test basic mode.
477
CHAPTER 24 C_CAN
■ IFx Mask Register 1 and 2 (IFxMSK1, IFxMSK2)
Figure 24.2-10 Bit Configuration of IFx Mask Register 1 and 2 (IFxMSK1, IFxMSK2)
IFx mask register 2 (upper byte)
bit
15
14
13
MXtd
MDir
res
Read/Write (R/W)
Initial value
(1)
(R/W)
(1)
(R)
(1)
(R/W)
(1)
(R/W)
(1)
6
5
4
3
Address: ch.0 020014H
ch.1 020114H
12
11
10
9
8
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
2
1
0
Msk28 to Msk24
IFx mask register 2 (lower byte)
bit
7
Address: ch.0 020015H
ch.1 020115H
Read/Write (R/W)
Initial value
(1)
Msk23 to Msk16
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
14
13
12
11
10
9
8
IFx mask register 1 (upper bytes)
bit
15
Address: ch.0 020016H
ch.1 020116H
Msk15 to Msk8
Read/Write (R/W)
Initial value
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
6
5
4
3
2
1
0
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
IFx mask register 1 (lower byte)
bit
7
Address: ch.0 020017H
ch.1 020117H
Read/Write (R/W)
Initial value
(1)
Msk7 to Msk0
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
This register is used to write and read the message object mask data in the message RAM. The set mask
data is disabled in the test basic mode.
For functions of respective bits, see "■Message Object" in the section "24.2.2 Message Interface
Register".
For the reserved bit in this register (bit13 of the IFx mask register 2), "1" is read. Set it to "1" when
writing to it.
478
CHAPTER 24 C_CAN
■ IFx Arbitration Register 1, 2 (IFxARB1, IFxARB2)
Figure 24.2-11 Bit Configuration of IFx Arbitration Register 1, 2 (IFxARB1, IFxARB2)
IFx arbitration register 2 (upper byte)
bit
Address:
15
ch.0 020018H MsgVal
ch.1 020118H
Read/Write (R/W)
Initial value (0)
14
13
12
11
10
Xtd
Dir
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
6
5
4
3
9
8
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
2
1
0
ID28 to ID24
IFx arbitration register 2 (lower byte)
bit
Address:
7
ch.0 020019H
ch.1 020119H
ID23 to ID16
Read/Write (R/W)
Initial value (0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
14
13
12
11
10
9
8
IFx arbitration register 1 (upper byte)
bit
Address:
15
ch.0 02001AH
ch.1 02011AH
ID15 to ID8
Read/Write (R/W)
Initial value (0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
6
5
4
3
2
1
0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
IFx arbitration register 1 (lower byte)
bit
Address:
7
ch.0 02001BH
ch.1 02011BH
Read/Write (R/W)
Initial value (0)
ID7 to ID0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
This register is used to write and read the message object arbitration data in the message RAM. This
setting is disabled in the test basic mode.
For functions of respective bits, see "■Message Object" in the section "24.2.2 Message Interface
Register".
Note:
If the MsgVal bit is to be cleared to "0" during transmission, the TxOk bit in the CAN status register
becomes "1" at the completion of transmission. However, the TxRqst bit in the message object and
CAN transmission request register are not to be cleared to "0". So clear the TxRqst bits to "0" using
the message interface register.
479
CHAPTER 24 C_CAN
■ IFx Message Control Register (IFxMCTR)
Figure 24.2-12 Bit Configuration of IFx Message Control Register (IFxMCTR)
IFx message control register (upper byte)
bit
Address:
15
14
13
12
11
ch.0 02001CH NewDat MsgLst IntPnd UMask TxIE
ch.1 02011CH
Read/Write (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (0)
(0)
(0)
(0)
(0)
10
9
8
RxIE
RmtEn TxRqst
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
2
1
0
IFx message control register (lower byte)
bit
Address:
ch.0 02001DH
ch.1 02011DH
7
6
5
4
EoB
-
-
-
(R)
(0)
(R)
(0)
(R)
(0)
Read/Write (R/W)
Initial value (0)
3
ID3 to ID0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
This register is used to write and read the message object control data in the message RAM. The IF1
message control register is disabled in the test basic mode. The NewDat and MsgLst in the IF2 message
control register function normally and the DLC bit displays the DLC of the received message. Other
control bits operate as invalid ("0"). For functions of respective bits, see "■Message Object" in the
section "24.2.2 Message Interface Register".
Note:
The TxRqst, NewDat, and IntPnd bits operate as follows depending on the WR/RD bit setting of the
IFx command mask register.
• When the transfer direction is "write" (WR/RD =1)
The TxRqst bit of this register is enabled only when the TxRqst/NewDat of the IFx command
mask register is set to "0".
• When the transfer direction is "read" (WR/RD =0)
If the CIP bit of the IFx command mask register is set to "1", and the IntPnd bit of the message
object and CAN interrupt pending register are reset by writing in the IFx command request
register, the IntPnd bit before resetting is stored in this register.
If the TxRqst/NewDat bit of the IFx command mask register is set to "1", and the NewDat bit of
the message object and CAN new data register are reset by writing in the IFx command request
register, the NewDat bit before resetting is stored in this register.
480
CHAPTER 24 C_CAN
■ IFx Data Register A1, A2, B1, B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2)
addr + 0
addr + 1
addr + 2
addr + 3
IFx Message Data A1 (address 20H & 50H)
Data (0)
Data (1)
-
-
IFx Message Data A2 (address 22H & 52H)
-
-
Data (2)
Data (3)
IFx Message Data B1 (address 24H & 54H)
Data (4)
Data (5)
-
-
IFx Message Data B2 (address 26H & 56H)
-
-
Data (6)
Data (7)
IFx Message Data A2 (address 30H & 60H)
Data (3)
Data (2)
-
-
IFx Message Data A1 (address 32H & 62H)
-
-
Data (1)
Data (0)
IFx Message Data B2 (address 34H & 64H)
Data (7)
Data (6)
-
-
IFx Message Data B1 (address 36H & 66H)
-
-
Data (5)
Data (4)
Figure 24.2-13 IFx Data Register A1, A2, B1, B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2)
IFx data register
IF1DTA1(upper)
bit
15
14
13
Read/Write (R/W)
Initial value
9
8
bit
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
7
6
5
4
3
2
1
0
Data7 to Data0
Read/Write (R/W)
Initial value
bit
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
15
14
13
12
11
10
9
8
Data15 to Data8
Address:
ch.0 020022H
ch.1 020122H
Read/Write (R/W)
Initial value
IF1DTA2(lower)
10
(R/W)
Address:
ch.0 020021H
ch.1 020121H
IF1DTA2(upper)
11
Data15 to Data8
Address:
ch.0 020020H
ch.1 020120H
IF1DTA1(lower)
12
bit
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
7
6
5
4
3
2
1
0
Data7 to Data0
Address:
ch.0 020023H
ch.1 020123H
Read/Write (R/W)
Initial value
(0)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(Continued)
481
CHAPTER 24 C_CAN
(Continued)
IFx data register
IF1DTB1(upper)
bit
15
14
13
Read/Write (R/W)
Initial value
9
8
bit
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
7
6
5
4
3
2
1
0
Data7 to Data0
Read/Write (R/W)
Initial value
bit
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
15
14
13
12
11
10
9
8
Data15 to Data8
Address:
ch.0 020026H
ch.1 020126H
Read/Write (R/W)
Initial value
IF1DTB2(lower)
10
(R/W)
Address:
ch.0 020025H
ch.1 020125H
IF1DTB2(upper)
11
Data15 to Data8
Address:
ch.0 020024H
ch.1 020124H
IF1DTB1(lower)
12
bit
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
7
6
5
4
3
2
1
0
Data7 to Data0
Address:
ch.0 020027H
ch.1 020127H
Read/Write (R/W)
Initial value
(0)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
This register is used to write and read the message object transmission/reception data in the message
RAM. It is used only for data frame transmission/reception and not for remote frame transmission/
reception.
● Setting of the transmit message data
The data that have been set are transmitted in the order of Data (0), Data (1) ... Data (15) starting from
MSB (bit7, bit15).
● Receive message data
The receive message data are stored in the order of Data (0), Data (1) ... Data (15) starting from MSB
(bit7, bit15).
482
CHAPTER 24 C_CAN
Notes:
• If the receive message data is less than 8 bytes, the remaining bytes in the data register are filled
with indeterminate data.
• Since the data is to be transferred in 4 bytes of Data A or Data B, partial updating to the 4 bytes is
disabled.
483
CHAPTER 24 C_CAN
■ Message Object
The message RAM contains 32 (or 128, depending on the product) message objects. For avoiding
access conflict between access from the CPU and access from the CAN controller to the message RAM,
the CPU is disabled to access directly to the message object. These accesses are performed via the IFx
message interface register.
This section describes configuration and functions of the message object.
● Configuration of the Message Object
Message object
UMask
Msk28 to
Msk0
MXtd
MDir
MsgVal
ID28 to
ID0
Xtd
Dir
EoB
NewDat
DLC3 to
Data 0
DLC0
Data 1
MsgLst
RxIE
TxIE
IntPnd
RmtEn
TxRqst
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Note:
Message objects are not initialized by the Init bit of the CAN controller or by performing a hardware
reset. When performing a hardware reset, initialize the message RAM using the CPU after canceling
the hardware reset, or set the MsgVal of the message RAM to "0".
● Functions of the Message Object
The ID28 to ID0, Xtd, and Dir bits are used to identify the ID and the message type when transmitting
the message. They are used for the acceptance filter together with the Msk28 to Msk0, MXtd, and MDir
bits when receiving the message.
The data frame or the remote frame passed through the acceptance filter is stored in the message object.
Xtd identifies whether the frame is an extended frame or a standard frame: When XTd is "1", frames
with 29-bit IDs (extended frames) are received, and when "0", frames with 11-bit IDs (standard frames)
are received.
If the data frame or the remote frame that has been received matches one or more message objects, it
will be stored in the object having the smallest matched message number. For details, see the section of
the acceptance filter for the receive message in "■Message Object".
MsgVal: Message valid bit
MsgVal
484
Function
0
The message object has no effect.
Messages are not transmitted or received.
1
The message object is valid.
Messages can be transmitted and received.
CHAPTER 24 C_CAN
Notes:
• Always initialize the MsgVa bit in the message object before resetting the Init bit in the CAN
control register (CTRLR) to "0" or before changing ID28 to ID0, Xtd, Dir and DLC3 to DLC0.
• If the MsgVal bit is set to "0" during transmission, the TxOk bit in the CAN Status register
(STATR) will be set to "1" upon completion of the transmission, but the TxRqst bit in the message
object and CAN transmission request register (TREQR) will not be cleared to "0". Therefore, clear
the TxRqst bit to "0" using the message interface register.
UMask: Acceptance mask enable bit
UMask
Function
0
Msk28 to Msk0, MXtd, and MDir are not used.
1
Msk28 to Msk0, MXtd, and MDir are used.
Notes:
• Change the UMask bit when the Init bit of the CAN control register is "1", or the MsgVal bit is "0".
• When the Dir bit is "1" and the RmtEn bit is "0", the function differs depending on the setting of the
UMask.
- If the UMask is set to "1", the TxRqst bit is reset to "0" when the remote frame is received
through the acceptance filter. At this time, the received ID, IDE, RTR, and DLC are saved in the
message object and the NewDat bit is set to "1" without changing the data (These are used like
the data frame).
- If the UMask is set to "0", the TxRqst bit is to be retained, ignoring the remote frame when the
remote frame is received.
ID28 to ID0: Message ID
ID28 to ID0
Function
0
Indicates a 29-bit ID (extended frame).
1
Indicates an 11-bit ID (standard frame).
Msk28 to Msk0: ID mask
Msk28 to Msk0
Function
0
Masks message object IDs and corresponding bits.
1
Does not mask message object IDs and corresponding bits.
485
CHAPTER 24 C_CAN
Xtd: Extended ID enable bit
Xtd
Function
0
11-bit IDs (standard frames) are used for message objects.
1
29-bit IDs (extended frames) are used for message objects.
MXtd: Extended ID mask bit
MXtd
Function
0
Masks the extended ID bit (IDE) using an acceptance filter.
1
Does not mask the extended ID bit (IDE) using an acceptance filter.
Note:
If an 11-bit ID (standard frame) is set for the message object, the IDs of the received data frames are
written in ID28 to ID18. ID masks of Msk28 to Msk18 are used.
Dir: Message direction bit
Dir
Function
0
Indicates the reception direction.
If TxRqst is set to "1", the remote frame is transmitted. If it is set to "0", data frames passed
through the acceptance filter are received.
1
Indicates the transmission direction.
If the TxRqst is set to "1", data frames are transmitted. If the TxRqst is "0" and RmtEn is set
to "1", the CAN controller itself sets the TsRqst to "1" by receiving remote frames passed
through the acceptance filter.
MDir: Message direction mask bit
MDir
486
Function
0
Masks the message direction bit (Dir) using an acceptance filter.
1
Does not mask the message direction bit (Dir) using an acceptance filter.
CHAPTER 24 C_CAN
Note:
Always set the MDir bit to "1".
EoB: End of buffer bit
(see "■FIFO Buffer Function " in section "24.3 C_CAN Function" for details).
EoB
Function
0
Indicates that the message object is used as a FIFO buffer and is not a last message.
1
Indicates that the message object is a single message object or the last message object of the
FIFO buffer.
Notes:
• The EoB bit is used to configure the FIFO buffer for 2 to 32 messages.
• Be sure to set the EoB bit to "1" when it is a single message object (i.e., when FIFO is not used).
NewDat: New data bit
NewDat
Function
0
No valid data exists.
1
Valid data exists.
MsgLst: Message lost
MsgLst
Function
0
No message has been lost.
1
One or more messages have been lost.
Note:
The MsgLst bit is valid only when the Dir bit is "0" (receiving direction).
487
CHAPTER 24 C_CAN
RxIE: Receive interrupt flag enable bit
RxIE
Function
0
The IntPnd is not changed after receiving the frame successfully.
1
The IntPnd is set to "1" after receiving the frame successfully.
TxIE: Transmission interrupt flag enable bit
TxIE
Function
0
The IntPnd is not changed after transmitting the frame successfully.
1
The IntPnd is set to "1" after transmitting the frame successfully.
IntPnd: Interrupt pending bit
IntPnd
Function
0
No interrupt factor exists.
1
One or more interrupt factors exist.
When no other interrupt having higher priority exists, the IntId bit of the CAN interrupt
register indicates this message object.
RmtEn: Remote enable
RmtEn
Function
0
The TxRqst is not to be changed by receiving remote frames.
1
If the remote frame is received when the Dir bit is "1", the TxRqst is set to "1".
Note:
When the Dir bit is "1" and the RmtEn bit is "0", the operation differs depending on the setting of the
UMask.
• If the UMask is set to "1", the TxRqst bit is reset to "0" when the remote frame is received through
the acceptance filter. At this time, the received ID, IDE, RTR, and DLC are saved in the message
object and the NewDat bit is set to "1" without changing the data (These are used like the data
frame).
• If the UMask is set to "0", the TxRqst bit is to be retained, ignoring the remote frame when the
remote frame is received.
488
CHAPTER 24 C_CAN
TxRqst: Transmission request bit
TxRqst
Function
0
Indicates the transmit idle state (i.e. not in transmission nor waiting for transmission).
1
Indicates that it is in transmission or waiting for transmission.
DLC3 to DLC0: Data length code
DLC3 to
DLC0
Function
0 to 8
The length of the data frame is zero (0) to eight (8) bytes.
9 to 15
No setting allowed
When set, the length is eight (8) bytes.
Note:
The received DLC is saved in the DLC bits after a data frame is received.
Data0 to Data7
Function
Data 0
The first data byte of the CAN data frame.
Data 1
The second data byte of the CAN data frame.
Data 2
The third data byte of the CAN data frame.
Data 3
The fourth data byte of the CAN data frame.
Data 4
The fifth data byte of the CAN data frame.
Data 5
The sixth data byte of the CAN data frame.
Data 6
The seventh data byte of the CAN data frame.
Data 7
The eighth data byte of the CAN data frame.
Notes:
• The serial output to the CAN bus is performed from the MSB (bit7 or bit15).
• If the receive message data is less than eight bytes, the remaining bytes in the data register are
filled with indeterminate data.
• Since data is to be transferred to the message object in four bytes of Data A or Data B, partial
updating to the four bytes is disabled.
489
CHAPTER 24 C_CAN
24.2.3
Message Handler Register
All the message handler registers are read-only.
The TxRqst, NewDat, IntPnd, MsgVal, and IntId bits of the message object show status.
■ CAN Transmission Request Register (TREQR1, TREQR2)
Figure 24.2-14 Bit Configuration of CAN Transmission Request Register (TREQR1, TREQR2)
CAN transmission request register 2 (upper byte)
bit
Address: ch.0 020080H
ch.1 020180H
Read/Write
Initial value
15
14
13
12
11
10
9
8
TxRqst32 to TxRqst25
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
4
3
2
1
0
CAN transmission request register 2 (lower byte)
bit
Address:
7
6
5
ch.0 020081H
ch.1 020181H
Read/Write
Initial value
TxRqst24 to TxRqst17
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
12
11
10
9
8
CAN transmission request register 1 (upper byte)
bit
15
14
13
Address: ch.0 020082H
ch.1 020182H
Read/Write
Initial value
TxRqst16 to TxRqst9
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
4
3
2
1
0
(R)
(0)
(R)
(0)
(R)
(0)
CAN transmission request register 1 (lower byte)
bit
7
6
5
Address: ch.0 020083H
ch.1 020183H
Read/Write
Initial value
TxRqst8 to TxRqst1
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
This register shows the TxRqst bit of all the message objects. By reading out the TxRqst bit, message
objects whose transmission requests are pending can be checked.
490
CHAPTER 24 C_CAN
TxRqst32 to TxRqst1: Transmission request bit
TxRqst
Function
0
Indicates the send idle state (i.e. not in transmission nor waiting for transmission).
1
Indicates that it is in transmission or waiting for transmission.
The setting/resetting conditions for the TxRqst bit are shown below.
•
•
Setting conditions
-
By setting the WR/RD of the IFx command mask register to "1" and setting the TxRqst to "1",
and writing in the IFx command request register, the TxRqst of the specified object can be set.
-
When the WR/RD of the IFx command mask register is set to "1" and the TxRqst of the IFx
message control register is set to "1", the TxRqst of the specified object can be set by writing in
the IFx command request register.
-
The TxRqst is set by receiving the remote frame passed through the acceptance filter when the
Dir bit is set to "1" and the RmtEn bit is set to "1".
Resetting conditions
-
When the WR/RD of the IFx command mask register is set to "1" and the TxRqst of the IFx
message control register is set to "0", the TxRqst of the specified object can be reset by writing in
the IFx command request register.
-
It is reset when the frame is transmitted successfully.
-
It is reset by receiving the remote frame passed through the acceptance filter when the Dir bit is
set to "1", the RmtEN bit is set to "0" and the UMask is set to "1".
For checking the transmission request bit in the CAN macro equipped with 32 message buffers or more,
refer to the following table.
Register
Bit
addr + 0
addr +1
addr +2
addr +3
TREQR4, TREQR3
TxRqst64 to TxRqst33
(address 84H)
TxRqst64 to
TxRqst57
TxRqst56 to
TxRqst49
TxRqst48 to
TxRqst41
TxRqst40 to
TxRqst33
TREQR6, TREQR5
TxRqst96 to TxRqst65
(address 88H)
TxRqst96 to
TxRqst89
TxRqst88 to
TxRqst81
TxRqst80 to
TxRqst73
TxRqst72 to
TxRqst65
TREQR8, TREQR7
TxRqst128 to
TxRqst97
(address 8CH)
TxRqst128 to
TxRqst121
TxRqst120 to
TxRqst113
TxRqst112 to
TxRqst105
TxRqst104 to
TxRqst97
491
CHAPTER 24 C_CAN
■ CAN New Data Register 1, 2 (NEWDT1, NEWDT2)
Figure 24.2-15 Bit Configuration of CAN New Data Register 1, 2 (NEWDT1, NEWDT2)
CAN new data register 2 (upper byte)
bit
15
14
13
Address: ch.0 020090H
ch.1 020190H
Read/Write
Initial value
12
11
10
9
8
NewDat32 to NewDat25
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
6
5
4
3
2
1
0
CAN new data register 2 (lower byte)
bit
7
Address: ch.0 020091H
ch.1 020191H
Read/Write
Initial value
NewDat24 to NewDat17
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
14
13
12
11
10
9
8
CAN new data register 1 (upper byte)
bit
Address: ch.0 020092H
ch.1 020192H
Read/Write
Initial value
15
NewDat16 to NewDat9
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
6
5
4
3
2
1
0
(R)
(0)
(R)
(0)
(R)
(0)
CAN new data register 1 (lower byte)
bit
7
Address: ch.0 020093H
ch.1 020193H
Read/Write
Initial value
NewDat8 to NewDat1
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
This register shows the NewDat bit of all the message objects. By reading out the NewDat bit, message
objects whose data is updated can be checked.
NewDat32 to NewDat1: New data bits
NewDat32
to
NewDat1
492
Function
0
No valid data exists.
1
Valid data exists.
CHAPTER 24 C_CAN
The setting/resetting conditions for the NewDat bit are shown below.
•
•
Setting conditions
-
By setting the WR/RD of the IFx command mask register to "1" and setting the NewDat of the
message control register to "1", and writing in the IFx command request register, the Newdat of
the specified object can be set.
-
It is set by receiving the data frame passed through the acceptance filter.
-
It is set by receiving the remote frame passed through the acceptance filter when the Dir bit is set
to "1", the RmtEn bit is set to "0", and the Umask is set to "1".
Resetting conditions
-
By setting the WR/RD of the IFx command mask register to "0" and setting the NewDat to "1",
and writing in the IFx command request register, the NewDat of the specified object can be reset.
-
By setting the WR/RD of the IFx command mask register to "1" and setting the NewDat of the
IFx message control register to "0", and writing in the IFx command request register, the NewDat
of the specified object can be reset.
-
It is reset after completing the data transfer to the shift register (internal register) for sending
data.
For checking the new data bit in the CAN macro equipped with 32 message buffers or more, refer to the
following table.
Register
Bit
addr + 0
addr +1
addr +2
addr +3
NEWDT4, NEWDT3
NewDat64 to
NewDat33
(address 94H)
NewDat4 to
NewDat57
NewDat56 to
NewDat49
NewDat48 to
NewDat41
NewDat40 to
NewDat33
NEWDT6, NEWDT5
NewDat96 to
NewDat65
(address 98)
NewDat96 to
NewDat89
NewDat88 to
NewDat81
NewDat80 to
NewDat73
NewDat72 to
NewDat65
NEWDT8, NEWDT7
NewDat128 to
NewDat97
(address 9CH)
NewDat128 to
NewDat121
NewDat120 to
NewDat113
NewDat112 to
NewDat105
NewDat104 to
NewDat97
493
CHAPTER 24 C_CAN
■ CAN Interrupt Pending Register (INTPND1, INTPND2)
Figure 24.2-16 Bit Configuration of CAN Interrupt Pending Register (INTPND1, INTPND2)
CAN interrupt pending register 2 (upper byte)
bit
Address:
ch.0 0200A0H
ch.1 0201A0H
Read/Write
Initial value
15
14
13
12
11
10
9
8
IntPnd32 to IntPnd25
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
5
4
3
2
1
0
CAN interrupt pending register 2 (lower byte)
bit
Address: ch.0 0200A1H
ch.1 0201A1H
Read/Write
Initial value
7
6
IntPnd24 to IntPnd17
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
13
12
11
10
9
8
CAN interrupt pending register 1 (upper byte)
bit
15
14
Address: ch.0 0200A2H
ch.1 0201A2H
IntPnd16 to IntPnd9
Read/Write
Initial value
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
5
4
3
2
1
0
(R)
(0)
(R)
(0)
(R)
(0)
CAN interrupt pending register 1 (lower byte)
bit
7
6
Address: ch.0 0200A3H
ch.1 0201A3H
Read/Write
Initial value
IntPnd8 to IntPnd1
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
This register shows the IntPnd bit of all the message objects. By reading out the IntPnd bit, which
message objects whose transmission requests are pending can be checked.
IntPnd32 to IntPnd1: Interrupt pending bits
IntPnd32
to
IntPnd1
494
Function
0
No interrupt factor exists.
1
One or more interrupt factors exist.
CHAPTER 24 C_CAN
The setting/resetting conditions for the IntPnd bit are shown below.
•
•
Setting conditions
-
The IntPnd is set by completing the successful frame transmission when the TxIE is set to "1".
-
The IntPnd is set by successfully receiving the frame passed through the acceptance filter when
the RxIE is set to "1".
-
When WR/RD of IFx command mask register is set to "1" and Control is set "1" and IntPnd of
IFx message control register is set to "1", IntPnd of specific object can be set by writing to IFx
command request register.
Resetting conditions
-
By setting the WR/RD of the IFx command mask register to "0" and setting the CIP to "1", and
writing in the IFx command request register, the IntPnd of the specified object can be reset.
-
When WR/RD of IFx command mask register is set to "1" and Control is set "1" and IntPnd of
IFx message control register is set to "0", IntPnd of specific object can be reset by writing to IFx
command request register.
For checking the interrupt pending bit in the CAN macro equipped with 32 message buffers or more,
refer to the following table.
Register
Bit
addr + 0
INTPND4,
INTPND3
IntPnd64 to IntPnd33
(address A4H)
IntPnd64 to IntPnd57 IntPnd56 to IntPnd49 IntPnd48 to IntPnd41 IntPnd40 to IntPnd33
INTPND6,
INTPND5
IntPnd96 to IntPnd65
(address A8H)
IntPnd96 to IntPnd89 IntPnd88 to IntPnd81 IntPnd80 to IntPnd73 IntPnd72 to IntPnd65
INTPND8,
INTPND7
IntPnd128 to IntPnd97
(address ACH)
IntPnd128 to
IntPnd121
addr +1
IntPnd120 to
IntPnd113
addr +2
IntPnd112 to
IntPnd105
addr +3
IntPnd104 to
IntPnd97
495
CHAPTER 24 C_CAN
■ CAN Message Valid Register (MSGVAL1, MSGVAL2)
Figure 24.2-17 Bit Configuration of CAN Message Valid Register (MSGVAL1, MSGVAL2)
CAN message valid register 2 (upper byte)
bit
15
14
13
Address: ch.0 0200B0H
ch.1 0201B0H
Read/Write
Initial value
12
11
10
9
8
MsgVal32 to MsgVal25
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
5
4
3
2
1
0
CAN message valid register 2 (lower byte)
bit
Address: ch.0 0200B1H
ch.1 0201B1H
Read/Write
Initial value
7
6
MsgVal24 to MsgVal17
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
13
12
11
10
9
8
CAN message valid register 1 (upper byte)
bit
15
14
Address: ch.0 0200B2H
ch.1 0201B2H
Read/Write
Initial value
MsgVal16 to MsgVal9
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
5
4
3
2
1
0
(R)
(0)
(R)
(0)
(R)
(0)
CAN message valid register 1 (lower byte)
bit
Address: ch.0 0200B3H
ch.1 0201B3H
Read/Write
Initial value
7
6
MsgVal8 to MsgVal1
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
This register shows the MsgVal bit of all the message objects. By reading out the MsgVal bit, which
message object is valid can be checked.
MsgVal32 to MsgVal1: Message valid bits
MsgVal32
to
MsgVal1
496
Function
0
The message object has no effect.
Messages cannot be transmitted or received.
1
The message object is valid.
Messages can be transmitted and received.
CHAPTER 24 C_CAN
The setting/resetting conditions for the MsgVal bit are shown below.
•
Setting conditions
By setting the MsgVal of the IFx arbitration register 2 to "1" and writing in the IFx command
request register, the MsgVal of the specified object can be set.
•
Resetting conditions
By setting the MsgVal of the IFx arbitration register 2 to "0" and writing in the IFx command
request register, the MsgVal of the specified object can be reset.
For checking the message valid bit in the CAN macro equipped with 32 message buffers or more, refer
to the following table.
Register
Bit
addr + 0
addr +1
addr +2
addr +3
MSGVAL4,
MSGVAL3
MsgVal64 to
MsgVal33
(address A4H)
MsgVal64 to
MsgVal57
MsgVal56 to
MsgVal49
MsgVal48 to
MsgVal41
MsgVal40 to
MsgVal33
MSGVAL6,
MSGVAL5
MsgVal96 to
MsgVal65
(address A8H)
MsgVal96 to
MsgVal89
MsgVal88 to
MsgVal81
MsgVal80 to
MsgVal73
MsgVal72 to
MsgVal65
MSGVAL8,
MSGVAL7
MsgVal128 to
MsgVal97
(address ACH)
MsgVal128 to
MsgVal121
MsgVal120 to
MsgVal113
MsgVal112 to
MsgVal105
MsgVal104 to
MsgVal97
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CHAPTER 24 C_CAN
24.2.4
CAN Prescaler Register (CANPRE)
This register defines the division ratio of the clock signal that is supplied to the CAN
interface. To change the value of this register, set the initialize bit (Init) of the CAN
control register (CTRLR) to "1" to stop all the bus operations.
■ CAN Prescaler Register
Figure 24.2-18 Bit Configuration of CAN Prescaler Register (CANPRE)
CAN prescaler register
bit
Address: 0001A8H
Read/Write
Initial value
15
14
13
12
-
-
-
-
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
11
10
9
8
CANPRE CANPRE CANPRE CANPRE
3
(R/W)
(0)
2
(R/W)
(0)
1
(R/W)
(0)
0
(R/W)
(0)
[bit15 to bit12] (Reserved bits)
For these bits, "0"s are always read. Writing to these bits does not affect the register.
[bit11 to bit8] CANPRE3 to CANPRE0: CAN prescaler setting bits
CANPRE3
to
CANPRE0
Function
0000B
Disabled
0001B
A cycle of one-half of the system clock frequency is selected for the CAN clock.
001XB
A cycle of one-fourth of the system clock frequency is selected for the CAN clock.
01XXB
A cycle of one-eighth of the system clock frequency is selected for the CAN clock.
1000B
A cycle of two-thirds of the system clock frequency is selected for the CAN clock.
The duty of the clock signal will be 67%.
1001B
A cycle of one-third of the system clock frequency is selected for the CAN clock.
101XB
A cycle of one-sixth of the system clock frequency is selected for the CAN clock.
11XXB
A cycle of one-twelfth of the system clock frequency is selected for the CAN clock.
Notes:
• Change the CAN prescaler setting bit after stopping all the bus operations by setting the initialize
bit of the CAN control register to "1".
• Set this register in such a manner that the clock signal supplied to the CAN interface should be no
more than 16 MHz.
498
CHAPTER 24 C_CAN
24.3
C_CAN Function
This section describes operations of the CAN controller and its functions.
■ Message Object
The message object configuration of the message RAM (except for MsgVal, NewDat, IntPnd, and
TxRqst bits) are not initialized by performing a hardware reset. Therefore the message object should be
reset by the CPU, or set the MsgVal bit as invalid (msgVal =0). In addition, set the CAN bit timing
register (BTR) and CAN prescaler extension register (BRPER) when the Init bit of the CAN control
register is "1" and CCE bit is "1".
The message object setup is performed through writing in the message interface register (IFx mask
register, IFx arbitration register, IFx message control register, and IFx data register). The data in the
interface register is then transferred to the specified message object by writing the message number in
the IFx command request register.
By clearing the Init bit of the CAN control register to "0", the CAN controller starts operating. The
receive message passed through the acceptance filter is stored in the message RAM. Messages of which
the transmission requests are pending are transferred to the shift register of the CAN controller from the
message RAM, thus achieving the transmission to the CAN bus.
The CPU reads out incoming messages via the message interface register and updates outgoing
messages. In addition, an interrupt to the CPU is generated depending on the configuration of the CAN
control register and IFx message control register (message object).
● Transmitting/receiving Data to/from the Message RAM
When a data transfer between the message interface register and the message RAM starts, the BUSY bit
of the IFx command request register is set to "1". After the transfer has completed, the BUSY bit is
cleared to "0" (See Figure 24.3-1).
The IFx command mask register specifies whether a complete message object or only parts of it are
transferred. Due to the structure of the message RAM it is not possible to write some bits/bytes of a
message object, it is always necessary to write a complete message object into the message RAM.
Therefore the data transfer from the message interface registers to the message RAM is performed using
a read-modify-write (RMW) cycle.
499
CHAPTER 24 C_CAN
Figure 24.3-1 Transferring Data between the Message Interface Register and the Message RAM
Start
NO
Write to IFx command
request register.
YES
BUSY = 1
Interrupt = 0
NO
WR/RD = 1
Read from the message RAM to the message
interface register.
YES
Read from the message RAM to the message
interface register.
Write from the message interface register to the
message RAM
BUSY = 0
Interrupt = 1
■ Transmission of Messages
● Transmission of Messages
If there is no data transfer between the message interface register and message RAM, the MsgVal bit of
the CAN message valid register and TxRqst bit of the CAN transmission request register should be
checked. The valid message object with the highest priority among the ones whose transmission request
has been pending is to be transferred to the shift register for transmission. At this point, the NewDat bit
of the message object is reset to "0".
After a successful transmission and if there is no new data in the message object (NewDat =0), the TxRqst bit
will be reset to "0". If TxIE is set to "1", the IntPnd bit will be set to "1" after a successful transmission. If the
CAN controller has lost to arbitration on the CAN bus or if an error occurred during the transmission, the
message will be retransmitted as soon as the CAN bus enters an idle state.
● Transmission Priority
The transmission priority is determined by the message number. A message object with a number one
(1) has the highest priority, while a message object 32 (where "32" is the largest number of the message
object implemented) has the lowest priority. Therefore, when more than one transmission request is
pending, message objects with smaller numbers are transmitted earlier.
500
CHAPTER 24 C_CAN
● Configuration for a Transmission Message Object
Table 24.3-1 shows how a transmission message object is initialized.
Table 24.3-1 Initializing a Transmission Message Object
MsgVal
Arb
Data
Mask
EoB
Dir
1
appl.
appl.
appl.
1
1
NewDat MsgLst
0
0
RxIE
TxIE
IntPnd
RmtEn
TxRqst
0
appl.
0
appl.
0
The IFx arbitration registers (ID28 to ID0 and Xtd bits) are given by the application. They define the ID
and type of the transmit message.
If a standard frame (11-bit ID) is used, ID28 to ID18 are used and ID17 to ID0 are disabled. If an
extended frame (29-bit ID) is used, ID28 to ID0 are used.
If the TxIE bit is set to "1", the IntPnd bit will be set to "1" after a successful transmission of the
message object.
If the RmtEn bit is set to "1" and a matching remote frame is received, the TxRqst bit is set to "1" and a
data frame is transmitted automatically.
The data registers (DLC3 to DLC0, Data0 to Data7) are given by the application.
When UMask is set to "1", the IFx mask registers (Msk28 to Msk0, UMask, MXtd, and MDir bits) are
used to receive remote frames grouped by the masked value of their IDs and then to allow transmission
(TxRqst bit is set to "1"). For more information, see the section describing the remote frame in
"■Message Object".
Note:
The Dir bit in the IFx mask register may not be masked.
● Updating a Transmission Message Object
The CPU may update the data of a transmission message object via the message interface register.
Data writing of the transmission message object is performed by the unit of four bytes of the
corresponding IFx data register (IFx data register A, IFx data register B). For this reason, a transmission
message object should be updated in unit of four bytes, not by one byte.
To update only the eight data bytes, begin with writing "0087H" to the IFx command mask register.
Writing a message number to the command request register produces two effects: updating the data (8
bytes) in the transmission message object and setting the TxRqst bit to "1".
When sending messages with message numbers that are consecutive following the message number of
the message currently being sent, set the TxRqst and NewDat bits to "1". Then the TxRqst bit will not
reset to "0", allowing a consecutive transmission.
When both the NewDat and TxRqst bits are set to "1", and transmission is initiated, the NewDat bit will
be reset to "0".
501
CHAPTER 24 C_CAN
Notes:
• When updating data, perform updating by the unit of four bytes of the IFx data register A or IFx
data register B.
• If only data is to be updated, set the NewDat bit and TxRqst bit to "1".
■ Receiving Messages
● Acceptance Filter for Incoming Messages
When the arbitration/control field (ID + IDE + RTR + DLC) of a message is completely shifted to the
shift register of the CAN controller for reception, scanning of the message RAM for matching valid
message object is started.
At this point, the arbitration field and mask data (including MsgVal, UMask, NewDat, and EoB) are
loaded from the message object in the message RAM, and this message object is compared with the
arbitration filed of the shift register including the mask data.
This operation is repeated "until a matching between the message object and the shift register arbitration
field is found" or "until the end of the message RAM is reached". If a match is detected, the scanning of
the message RAM is stopped and the CAN controller performs processing depending on the type of the
incoming frame (data frame or remote frame).
● Reception Priority
The reception priority is determined by the message number. A message object with a number one (1)
has the highest priority, while a message object 32 (where "32" is the largest number of the message
object implemented) has the lowest priority. If more than one message is matched in the acceptance
filter, the object having the smaller message number will be the receive message object.
● Reception of Data Frame
The CAN controller transfers and stores the receive message from the shift register to the message
RAM of the message object matched in the acceptance filter. Not only the data bytes, but all the
arbitration field and the data length code are stored. This is performed even if the IFx mask register is
masked (They are stored to keep IDs and data bytes).
The NewDat bit is set to "1" if new data is received. After the CPU reads out the message object, reset
the NewDat bit to "0". If the NewDat bit is set to "1" even after the reception of the message, MsgLst is
set to "1" to indicate that the previous data is lost.
If a message buffer is received while the RxIE bit is set to "1", the IntPnd bit of the CAN interrupt
pending register is set to "1". At the same time, the TxRqst bit of the message object is reset to "0". This
prevents the transmission of a remote frame if a requested data frame is received during transmission
processing.
502
CHAPTER 24 C_CAN
● Remote Frame
When a remote frame is received, one of the following three operations is performed. One is selected
from these remote frame receive operations based on the setting of the matched message object.
•
Dir =1 (transmit direction), RmtEn =1, UMask =1 or 0
At the reception of a matched remote frame, the TxRqst bit of this message object only is set to "1"
and automatically transmit data frame answering to the received remote frame (The message object
other than the TxRqst bit remains unchanged).
•
Dir =1 (transmission direction), RmtEn =0, UMask =0
Even when the receiving remote frame matches to the message object, the remote frame is disabled
and not received (The TxRqst bit of this message object remains unchanged).
•
Dir =1 (transmission direction), RmtEn =0, UMask =1
At the reception of a matched remote frame, the TXRqst bit of this message object is reset to "0" and
the remote frame is treated like a incoming data frame. The received arbitration and control field (ID
+ IDE + RTR + DLC) are stored in the message object in the message RAM and the NewDat bit of
this message object is set to "1". The data field of the message object remains unchanged.
● Configuration of a Receive Message Object
Table 24.3-2 shows how a receive message object is initialized.
Table 24.3-2 Initializing an Receive Message Object
MsgVal
Arb
Data
Mask
EoB
Dir
1
appl.
appl.
appl.
1
0
NewDat MsgLst
0
0
RxIE
TxIE
IntPnd
RmtEn
TxRqst
appl.
0
0
0
0
The IFx arbitration registers (ID28 to ID0 and Xtd bits) are given by the application. They define the ID
and the type of receive message used for the acceptance filter.
If a standard frame (11-bit ID) is used, ID28 to ID18 are used and ID17 to ID0 are disabled. If a
standard frame is received, ID17 to ID0 are reset to "0". If an extended frame (29-bit ID) is set, ID28 to
ID0 are used.
When the RxIE bit is set to "1", the IntPnd bit is set to "1" after an incoming data frame is stored in the
message object.
The data length code (DLC3 to DLC0) is given by the application. When the CAN controller stores an
incoming data frame in the message object, the incoming data length code and 8-byte data are stored. If
the data length code is less than eight, the remaining bytes in the message object are filled with
indeterminate data.
When UMask =1, the IFx mask registers (Msk28 to Msk0, UMask, MXtd, and MDir bits) are used to
allow the reception of a data frame having the ID grouped by mask configuration. For more
information, see the section describing the reception of a data frame in "■Message Object".
Note:
The Dir bit of the IFx mask register may not be masked.
503
CHAPTER 24 C_CAN
● Handling Receiving Messages
The CPU can read a received message any time via the message interface register.
Typically the CPU writes "007FH" in the IFx command mask register. Then it writes the message
number of the message object in the IFx command request register. By performing above steps, the
received message of the specified message number is transferred to the message interface register from
the message RAM. At this point, the NewDat bit and IntPnd bit can be to be cleared to "0", based on the
configuration of the IFx command mask register.
When a matched receive message is found through the acceptance filter, the message will be received.
If the message object uses the acceptance filter mask, whether to receive the message or not is judged
based on the acceptance filter from which the masked data has been eliminated
The NewDat bit indicates whether a new message has been received since the message object was read
last time.
The MsgLst bit indicates whether the previous data has been lost because a new incoming data has been
received before the previous data has been read from the message object. The MsgLst bit will not be
reset automatically.
If a matching data frame through the acceptance filter is received while the remote frame is being
handled for transmission, the TxRqst bit is automatically reset to "0".
■ FIFO Buffer Function
This section describes the configuration of the FIFO buffer for the message object and its operations in
handling incoming messages.
● Configuration of the FIFO Buffer
The configuration of reception message object in the FIFO buffer is the same as that of a reception
object, with the exception of the EoB bit (See configuration of an receive message object in section
"■Message Object").
FIFO buffer is used by connecting two or more receive message objects. To store incoming messages in
this FIFO buffer, IDs and mask configuration (if used) of the receive message objects have to be
matched.
A message object having the lowest number (i.e. with the highest priority) will be the first receive
message object in the FIFO buffer. The EoB bit of the last receive message object of the FIFO buffer
should be set to "1" to indicate the end of the FIFO buffer block (The EoB bits of all message objects
other than the last object using the FIFO buffer should be set to "0").
Notes:
• Be sure to configure message objects used for the FIFO buffers to have the same IDs and mask
configuration.
• Be sure to set the EoB bit to "1" when FIFO is not used.
504
CHAPTER 24 C_CAN
● Receiving a Message with FIFO Buffers
When an ID of an receive message matches the ID of the FIFO buffer, that message is stored in an
receive message object of the FIFO buffer having the lowest message number.
When a message is stored in an receive message object of a FIFO buffer, the NewDat bit of this receive
message object is set to "1". By setting the NewDat bit of receive message objects to "1" whose EoB bit
is "0", the message object is protected against write accesses by the CAN controller until the last receive
message object (with the EoB bit set to "1") is reached.
If all the FIFO is stored with valid data to the last FIFO buffer, and "0" is not set to the NewDat bit of
an receive message object (to cancel the write protection), the subsequent receive message will be
written to the last message object and overwrite it.
● Reading from a FIFO Buffer
For the CPU to read contents of the receive message object, the messages should be transferred to the
message interface register by writing its message number in the IFx command request register. At this
point, set the WR/RD bit of the IFx command mask register to "0" (read), TxRqst/NewDat = 1 and
ClrIntPnd = 1, and reset the NewDat and IntPnd bits to "0".
To assure the correct function of a FIFO buffer, the receive message objects in the FIFO buffer must be
read in the order from the lower message number.
Figure 24.3-2 shows how the message objects connected in the FIFO buffer are handled by the CPU.
505
CHAPTER 24 C_CAN
Figure 24.3-2 CPU Handling of a FIFO Buffer
Start
Message interrupt
CAN interrupt
register Read
8000 H
0000H
CAN interrupt register value
Other than 8000 H or 0000 H
Status interrupt
process execution
End
(Normal process)
Message number =
CAN interrupt register value
IFx command request register
(Message number)
Message interface register
Read:
(Reset NewDat = 0, IntPnd = 0)
IFx message control register
Read
NO
NewDat = 1
YES
IFx message data register A, B
Read
EoB = 1
YES
NO
Message number = Message number 1
■ Interrupt Function
If multiple interrupts are pending, the CAN interrupt register indicates the interrupt code having the
highest priority. The chronological order of interrupts is ignored and the code with the highest priority
is always shown. The interrupt codes remain unchanged until the CPU clears them.
The status interrupt (IntId bit = 8000H) has the highest priority.
As for the message interrupts, the lower the message number, the higher the priority. Likewise, the
higher the message number, the lower the priority.
The message interrupt is cleared by clearing the IntPnd bit of the message object. The status interrupt is
cleared by reading the CAN status register.
The IntPnd bit of the CAN interrupt pending register indicates existence or absence of interrupts. If
there is no pending interrupt, the IntPnd bit is "0".
506
CHAPTER 24 C_CAN
When the IE bit of the CAN control register and TxIE and RxIE bits of the IFx message control register
are set to "1", and the IntPnd bit is changed to "1", the interrupt signal to the CPU becomes active. The
interrupt signal will remain active until the CAN interrupt pending register is cleared to "0" (reset the
interrupt factor) or the IE bit of the CAN control register is reset to "0".
The value 8000H of the CAN interrupt register indicates that the CAN status register has been updated
by the CAN controller and this interrupt has the highest priority. The interrupt by updating the CAN
status register can control whether to enable or disable the configuration of the CAN interrupt register
using the EIE bits and SIE bit of the CAN control register. In addition, the interrupt signal to the CPU
can be controlled using the IE bit of the CAN control register.
The RxOk, TxOk, and LEC bits in the CAN status register can be updated (reset) by writing via the
CPU, while interrupts cannot be set or reset by that writing.
Values of CAN interrupt registers other than 8000H or 0000H indicate one or more message interrupts
are pending and shows the pending message interrupt with the highest priority.
The CAN interrupt register is updated even if IE is reset.
The source of the message interrupt to the CPU can be checked by the CAN interrupt register or by the
CAN interrupt pending register (See section "24.2.3 Message Handler Register"). It is possible to clear
the message interrupt and to read the message data at the same time. If the message interrupt shown by
the CAN interrupt register is cleared, the interrupt with the next highest priority will be set to the CAN
interrupt register and awaits the next interrupt process. If there is no interrupt, the CAN interrupt
register shows 0000H.
Notes:
• The status interrupt (IntId = 8000H) is cleared by a read access to the CAN status register.
• A status interrupt (IntId = 8000H) by a write access to the CAN status register does not occur.
■ Bit Timing
Each CAN node of the CAN network has its clock oscillator (typically, a crystal oscillator). The time
parameter of the bit time can be individually configured for each CAN node. By doing so, a common bit
rate can be supplied even though the oscillator periods of the CAN nodes (fosc) may be different.
The frequencies of these oscillators may vary slightly depending on the change of temperature or
voltage or deterioration of the component. As long as the variations remain within an oscillator
tolerance range (df), the CAN nodes are able to compensate for the different bit rates by resynchronizing the bit stream.
According to the CAN specification, the bit time is divided into four segments (see Figure 24.3-3): the
synchronization segment (Sync_Seg), propagation time segment (Prop_seg), phase buffer segment 1
(Phase_Seg1), and phase buffer segment 2 (Phase_seg2). The duration of each segment is
programmable (see Table 24.3-3). A basic time quantum (tq) of the bit time is defined based on the
CAN controller's system clock fsys and the baud rate prescaler (BRP):
tq = BRP/fsys
The CAN's system clock fsys is the frequency of the clock input (see Figure 24.1-1). The
synchronization segment Sync_Seg defines timing such that a CAN bus edge should occur during this
bit time. The propagation time segment Prop_Seg compensates the physical delay time within the CAN
507
CHAPTER 24 C_CAN
network. The phase buffer segments Phase_Seg1 and Phase_Seg2 specify the sampling point. The
resynchronization jump width (SJW) defines shift width of the sampling point for resynchronization to
compensate edge phase errors.
Figure 24.3-3 Bit Timing
1 bit time (BT)
Sync
_Seg
Prop_Seg
Phase_Seg1
Phase_Seg2
one unit time
(tq)
Sampling point
Table 24.3-3 Parameters of the CAN Bit Time
Parameter
Range
BRP
[1 to 32]
Sync_Seg
1 tq
Prop_Seg
[1 to 8] tq
Compensation for the physical delay time
Phase_Seg1
[1 to 8] tq
Compensation for edge phase errors before the sample point
It can be temporarily lengthened by synchronization
Phase_Seg2
[1 to 8] tq
Compensation for edge phase errors after the sample point
It can be temporarily shortened by synchronization
SJW
[1 to 4] tq
Resynchronization jump width
It is not longer than either of the phase buffer segment length.
508
Function
Definition of length of time value tq
Fixed length synchronization with the system clock
CHAPTER 24 C_CAN
Figure 24.3-4 shows the bit timing in the CAN controller.
Figure 24.3-4 Bit Timing in the CAN Controller
1 bit time (BT)
Sync
_Seg
TEG1
one unit time
(tq)
TEG2
Sampling point
Table 24.3-4 Parameters of the CAN Controller
Parameter
Range
Function
BRPE, BRP
[0 to 1023]
Sync_Seg
1 tq
TSEG1
[1 to 15] tq
Time segment before the sampling point.
It corresponds to Prog_Seg and Phase_Seg1.
It can be controlled by the bit timing register.
TSEG2
[0 to 7] tq
Time segment after the sampling point.
It corresponds to Phase_Seg2.
It can be controlled by the bit timing register.
SJW
[0 to 3] tq
Resynchronization jump width.
It can be controlled by the bit timing register.
Definition of length of time value tq
The prescaler can be extended to a maximum of 1024 by the bit timing register and the
prescaler extension register.
Synchronization with the system clock
Fixed length
The relationships among parameters are shown below.
tq
= ([BRPE, BRP] + 1)/fsys
BT = Sync_Seg + TEG1 + TEG2
= (1 + (TSEG1 + 1) + (TSEG2 + 1)) × tq
= (3 + TSEG1 + TSEG2) × tq
509
CHAPTER 24 C_CAN
■ Test Mode
This section describes how to set the test mode and its operations.
● Setting the Test Mode
The test mode becomes effective by setting the Test bit of the CAN control register to "1". In the test
mode, the Tx1, Tx0, LBack, Silent, and Basic bits in the CAN test register are enabled.
By resetting the Test bit of the CAN control register to "0", all the test register functions are disabled.
● Silent Mode
The CAN controller can be set in silent mode by setting the Silent bit of the CAN test register to "1".
In silent mode, data frames and remote frames can be received, but only recessive bits are output on the
CAN bus and messages and ACKs are not transmitted.
If the CAN controller is required to send dominant bits (ACK bit, overload flag, active error flag), the
bits are sent to the RX side via the turn back circuit in the CAN controller. In this operation, although
the CAN bus is in recessive state, the receiver side will receive the dominant bit that has been sent back
within the CAN controller.
In silent mode, user can analyze the traffic on a CAN bus without being affected by the transmission of
dominant bits (ACK bit and error flag).
Figure 24.3-5 shows the connection of signals CAN_TX and CAN_RX to the CAN controller in silent
mode.
Figure 24.3-5 CAN Controller in Silent Mode
CAN_TX
CAN_RX
CAN controller
Silent bit = 1
Tx
Rx
CAN Core
● Loop Back Mode
The CAN controller can be set in loop back mode by setting the LBack bit of the CAN test register to
"1".
The loop back mode is used for self-diagnosis.
In loop back mode, the TX side is connected to the RX side in the CAN controller. Messages sent by
the CAN controller are handled as those received by the RX side and messages passed through the
acceptance filter are stored in the receive buffer.
Figure 24.3-6 shows the connection of signals CAN_TX and CAN_RX to the CAN controller in
loopback mode.
510
CHAPTER 24 C_CAN
Figure 24.3-6 CAN Controller in Loop Back Mode
CAN_TX
CAN_RX
Tx
Rx
CAN controller
CAN Core
Note:
Being independent from external signals, dominant bits of data/remote frames at the acknowledge
slot are not sampled in loop back mode. Therefore, the CAN controller does not issue acknowledge
errors in the test mode although such errors are issued in normal mode.
● Silent Mode Combined with Loop Back Mode
It is possible to combine loop back mode and silent mode by setting the LBack bit and Silent bit of the
CAN test register to "1" at the same time.
This mode can be used for a "hot self-test". A "hot self-test" means that test operations of the CAN
controller in loop back mode have no effect on the CAN system because the output from the CAN_TX
pin is always recessive and inputs from the CAN_RX pin are ignored in this mode.
Figure 24.3-7 shows the connection of signals CAN_TX and CAN_RX to the CAN controller in silent
mode combined with loopback mode.
Figure 24.3-7 CAN Controller in Silent Mode Combined with Loop Back Mode
CAN_TX
CAN_RX
CAN controller
Loop Back bit and
Silent bit = 1
Tx
Rx
CAN Core
511
CHAPTER 24 C_CAN
● Basic Mode
The CAN controller can be set in basic mode by setting the Basic bit of the CAN test register to "1".
In basic mode, the CAN controller operates without using the message RAM.
The IF1 message interface register is used to control transmission.
To begin transmitting messages, the contents to be sent are set to the IF1 message interface register.
Then issue a transmission request by setting the BUSY bit of the IF1 command request register to "1".
When the BUSY bit is set to "1", it indicates that the IF1 message interface register is locked or the
transmission is pending.
If the BUSY bit is set to "1", the CAN controller performs following operations.
As soon as the CAN bus becomes idle, the contents of the IF1 message interface register are loaded to
the shift register for transmission and starts the transmission. When the transmission is completed
successfully, the BUSY bit is reset to "0" to release the locked IF1 message interface register.
A pending transmission can be aborted any time by resetting the BUSY bit of the IF1 command request
register to "0". If the BUSY bit is reset to "0" during transmission, retransmission due to the losing of
arbitration or detecting of an error is canceled.
The IF2 message interface register is used to control reception.
All the messages are received without using an acceptance filter. The contents of the received message
can be read by setting the BUSY bit of the IF2 command request register to "1".
If the BUSY bit is set to "1", the CAN controller performs following operations.
- It stores the received message (contents of the shift register for reception) in the IF2 message interface
register without using an acceptance filter.
When a new message is stored in the IF2 message interface register, the CAN controller sets the
NewDat bit to "1". When another message is received while the NewDat bit is "1", the CAN controller
sets the MsgLst to "1".
Notes:
• In basic mode, all message objects relating to the control and status bits and control mode
configuration of the IFx command mask register are disabled.
• The message number of the command request register is disabled.
• The NewDat and MsgLst bits of the IF2 message control register operate as usual, DLC3 to DLC0
shows the received DLC, and other control bits are read as "0".
512
CHAPTER 24 C_CAN
● Software Control of Pin CAN_TX
Four output functions are available for the CAN transmit pin CAN_TX.
•
Serial data output [Normal output]
•
CAN sampling point signal output for monitoring bit timing of the CAN controller.
•
Dominant constant output
•
Recessive constant output
Dominant and recessive constant outputs can be used to monitor CAN receive pin CAN_RX as well as
to check the physical layer of the CAN bus.
The output mode of CAN_TX pin can be controlled with the Tx1 and TX0 bits.
Note:
CAN_TX should be set for serial data output when transmitting a CAN message or using loop back
mode, silent mode, or basic mode.
■ Software Initialization
Factors for initializing by software are listed below:
•
Hardware reset
•
Setting the Init bit of the CAN control register
•
Transition to the Bus Off state
A hardware reset initializes all the settings other than those of message RAM (except for MsgVal,
NewDat, IntPnd, and TxRqst bits). After the hardware reset, the message RAM should be initialized by
the CPU or by setting the MsgVal bit of the message RAM to "0". When setting a bit timing register, set
it before clearing the Init bit of the CAN control register to "0".
The Init bit of the CAN control register will be set to "1" by the following conditions.
•
Writing of "1" by the CPU
•
Hardware reset
•
Bus Off
If the Init bit is set to "1", all the message transmission and reception operations on the CAN bus are
aborted and the CAN_TX pin of the CAN bus output becomes recessive (except for CAN_TX test
mode).
If the Init bit is set to "1", the error counter does not change and no changes are made on registers.
If the Init and CCE bits of the CAN control register are set to "1", configuration of the bit timing
register (for controlling baud rate) and of the prescaler extension register are enabled.
By resetting the Init bit to "0", software initialization is completed. Only the CPU can access and set the
Init bit to "0".
Once the Init bit is reset to "0", the device will wait for the occurrence of 11 consecutive recessive bits
(Bus Idle) before synchronizing with data transfer on the CAN bus and start performing message
transmission.
Before changing the mask, ID, XTD, EoB, and RmtEn of the message object in normal operation, set
MsgVal to disabled.
513
CHAPTER 24 C_CAN
■ CAN Clock Prescaler
This section describes how to switch the CAN clock while the PLL is running.
● Block Diagram
The following block diagrams illustrates outlines of the CAN clock prescaler.
The frequency division ratio of the clock signal that will be supplied to the CAN interface is determined
according to the setting of the CANPRE bit of the CAN clock prescaler register.
Figure 24.3-8 Block Diagram of CAN Clock Prescaler
PLL
CAN clock1
Clock
Divider
X0
Div by
CANPRE
514
CAN clock0
CHAPTER 24 C_CAN
● Procedure for Switching the Clocks
It is recommended to use the following procedure to change the clocks which use a CAN clock
prescaler.
Figure 24.3-9 How to Switch a Clock which uses the CAN Clock Prescaler
Switching CAN clock :
OSCILLATOR -> PLL
Switching CAN clock :
PLL -> OSCILLATOR
Set bit Init in the CAN
Control Register
Set bit Init in the CAN
Control Register
Enable PLL
Set prescaler value
Wait for PLL Lock Time
Disable PLL
Set prescaler value
Initialize bit Init in the
CAN Control Register
Initialize bit Init in the
CAN Control Register
515
CHAPTER 24 C_CAN
● CAN Clock Prescaler Configuration
A List of values that can be set for the CAN clock prescaler is shown below.
The frequency of the clock signal that is supplied to the CAN interface is a divided system clock
frequency based on the configuration for the CAN clock prescaler.
CANPRE [3:0]
Function
System clock:
32 MHz
0000B
Setting is prohibited.
0001B
A cycle of one-half of the system clock cycle time is selected for the CAN clock.
16MHz
001XB
A cycle of one-fourth of the system clock cycle time is selected for the CAN clock.
8MHz
01XXB
A cycle of one-eighth of the system clock cycle time is selected for the CAN clock.
4MHz
1000B
A cycle of two-thirds of the system clock cycle time is selected for the CAN clock.
The duty of the clock signal will be 67%.
21.33MHz
(Setting is prohibited).
1001B
A cycle of one-third of the system clock cycle time is selected for the CAN clock.
10.67MHz
101XB
A cycle of one-sixth of the system clock cycle time is selected for the CAN clock.
5.33MHz
11XXB
A cycle of one-twelfth of the system clock cycle time is selected for the CAN clock.
2.67MHz
Setting is prohibited.
Notes:
• Change the setting bit of the CAN prescaler after stopping all the bus operations by setting the
initialize bit of the CAN control register to "1".
• Set this register in such a manner that the clock signal supplied to the CAN interface should be no
more than 16 MHz.
516
CHAPTER 25
LCD CONTROLLER (LCDC)
This chapter outlines the LCD controller/driver (LCDC)
and describes its register configuration, functions and
operations.
25.1 Overview of LCD Controller
25.2 LCD Controller Registers
25.3 Operation of LCD Controller
517
CHAPTER 25 LCD CONTROLLER (LCDC)
25.1
Overview of LCD Controller
This section describes the features and block diagram of the LCD controller.
■ Features of LCD Controller
The LCD controller directly displays the contents of the data memory for display on the LCD via
common and segment outputs.
•
The LCD contains a drive voltage split resistor.
•
Up to four common outputs (pins COM0 to COM3) and 32 segment outputs (pins SEG0 to SEG31)
are available.
•
The LCDC contains 16-byte data memory for display.
•
The duty cycle is 1/2, 2/3, or 1/4 selectable. The bias is fixed at 1/3.
•
The oscillation clock (HCLK) or sub clock (SCLK) is used as the LCD drive clock.
•
The LCD can be directly controlled.
•
Pins COM0 to COM3 and SEG0 to SEG31 can be used as general-purpose I/O ports. Table 25.1-1
indicates the common outputs that can be used when a particular bias and duty cycle are selected
(based on the LCDCMR and CLR1 registers).
Table 25.1-1 Combinations of Common Outputs with Biases and Duty Cycles
Bias
1/2 duty cycle output mode
1/3 duty cycle output mode
1/4 duty cycle output mode
❍
❍
❍
Outputs COM1 and COM0
Outputs COM2 to COM0
Outputs COM3 to COM0
1/3 Bias
518
CHAPTER 25 LCD CONTROLLER (LCDC)
■ Block Diagram of LCD Controller
Figure 25.1-1 Block Diagram of LCD Controller
Common pin selection register (LCDCMR)
⎯
⎯
⎯
COM3 COM2 COM1 COM0
4
LCD control
register 0
(LCR0)
CSS
⎯ VSEL BK
Internal split
resistor
MS1 MS0 FP1 FP0
Common driver
Prescaler
Timing
controller
AC Circuit
Oscillation clock
Sub clock
Internal data bus
2
2
Display data memory
(16 bytes)
32
Pin
COM0
Pin
COM1
Pin
COM2
Pin
COM3
Pin
SEG0
Pin
SEG1
Pin
SEG2
Controller block
.....
LCD control register 1 (LCR1)
.....
SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0
Segment driver
6
Pin
SEG29
Pin
SEG30
Pin
SEG31
-: Undefined bit
Driver block
519
CHAPTER 25 LCD CONTROLLER (LCDC)
25.2
LCD Controller Registers
This section describes the LCD controller/driver register function.
■ LCD Controller Register List
LCDCMR
Address: 000098H
Read/Write
Initial value
LCR0
bit 15
14
13
12
11
10
9
8
−
−
−
−
COM3
COM2
COM1
COM0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
14
13
12
11
10
9
8
bit 15
Address: 00009AH
Read/Write
Initial value
LCR1
CSS
−
VSEL
BK
MS1
MS0
FP1
FP0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(1)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
6
5
4
3
2
1
0
SEG6
(R/W)
(0)
SEG5
(R/W)
(0)
SEG4
(R/W)
(0)
SEG3
(R/W)
(0)
SEG2
(R/W)
(0)
SEG1
(R/W)
(0)
SEG0
(R/W)
(0)
14
13
12
11
10
9
8
D14
(R/W)
(X)
D13
(R/W)
(X)
D12
(R/W)
(X)
D11
(R/W)
(X)
D10
(R/W)
(X)
D09
(R/W)
(X)
D08
(R/W)
(X)
6
5
4
3
2
1
0
D06
(R/W)
(X)
D05
(R/W)
(X)
D04
(R/W)
(X)
D03
(R/W)
(X)
D02
(R/W)
(X)
D01
(R/W)
(X)
D00
(R/W)
(X)
bit 7
Address: 00009BH
Read/Write
Initial value
SEG7
(R/W)
(0)
VRAMn (n = 0, 2, 4, 6, 8, 10, 12, 14)
bit 15
Address:
D15
00009CH (VRAM0)
Read/Write (R/W)
00009EH (VRAM2)
Initial value
(X)
0000A0H (VRAM4)
0000A2H (VRAM6)
0000A4H (VRAM8)
0000A6H (VRAM10)
0000A8H (VRAM12)
0000AAH (VRAM14)
VRAMn (n = 1, 3, 5, 7, 9, 11, 13, 15)
bit 7
Address:
D07
00009DH (VRAM1)
Read/Write (R/W)
00009FH (VRAM3)
Initial value
(X)
0000A1H (VRAM5)
0000A3H (VRAM7)
0000A5H (VRAM9)
0000A7H (VRAM11)
0000A9H (VRAM13)
0000ABH (VRAM15)
520
CHAPTER 25 LCD CONTROLLER (LCDC)
■ Common Pin Selection Register (LCDCMR)
Figure 25.2-1 Bit Configuration of Common Pin Selection Register (LCDCMR)
LCDCMR
bit 15
Address: 000098H
Read/Write
Initial value
14
13
12
11
10
9
8
−
−
−
−
COM3
COM2
COM1
COM0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
[bit15 to bit12] (Reserved bits)
Do not write the value excluding "0" to these bits.
[bit11 to bit8] COM3 to COM0: Common pin enable bits
COM3
COM2
COM1
COM0
Common output
0
0
0
0
Common output disabled [Initial value]
1
1
1
1
Common output enabled
Other than the above settings
Setting disabled
Using these bits, specify whether to enable the common outputs. To use this product with the LCD, be
sure to set LCDCMR =00001111B.
Note: In addition to the above setting, setting the Port Function Register (PER and EPER) is needed.
For more information, see "CHAPTER 4 I/O PORT".
521
CHAPTER 25 LCD CONTROLLER (LCDC)
■ LCDC Control Register 0 (LCR0)
LCDC control register 0 (LCR0) controls selection of a frame interval and a clock used to generate
pulses with the selected frame interval and selection of a display mode and whether to display or hide. It
also controls the drive power.
Figure 25.2-2 Bit Configuration of LCDC Control Register 0 (LCR0)
LCR0
bit 15
14
13
12
11
10
9
8
Address: 00009AH
CSS
−
VSEL
BK
MS1
MS0
FP1
FP0
Read/Write
Initial value
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(1)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
[bit15] CSS: Frame interval generation clock selection bit
This bit is used to select a clock for the LCD display frame interval.
CSS
Operation
0
The LCD control driver works on the oscillation clock.
[Initial value]
1
The LCD control driver works on the sub clock.
Notes:
•
In sub clock mode, the configuration based on the oscillation clock do not work because the
oscillation clock is inactive.
•
If you use a single clock product (whose product name ends with an S), do not set this bit to "1".
[bit14] (Reserved bit)
Do not write the value excluding "0" to this bit.
[bit13] VSEL: LCD drive power control bit
This bit specifies whether to connect or disconnect the internal split resistor. Before starting use, be sure
to set this bit to "1".
VSEL
522
Operation
0
Disconnects the internal split resistor. [Initial value]
1
Connects the internal split resistor.
CHAPTER 25 LCD CONTROLLER (LCDC)
[bit12] BK: Blanking selection bit
This bit is used to specify whether to display or hide the LCD. When this bit is set, the segment outputs
are non-select wave forms (which do not satisfy the display conditions) and are not displayed.
BK
Operation
0
Display
1
Blanked [Initial value]
[bit10, bit11] MS1, MS0: Display mode selection bits
These bits specify one of three duty cycles for the output wave forms. The common pins to be used are
determined by the specified duty output mode. When these bits are set to "00B", the LCD controller
driver stops display operation and the outputs from the common and segment pins become "L".
MS1
MS0
Operation
0
0
The LCD stops operation.
0
1
1/2-duty-cycle output mode (Time divisions = 2)
1
0
1/3-duty-cycle output mode (Time divisions = 3)
1
1
1/4-duty-cycle output mode (Time divisions = 4)
[bit8, bit9] FP1, FP0: Frame interval selection bits
These bits specify one of four frame intervals for LCD display.
Frame frequency [Hz]
FP1
FP0
Main clock selected (CSS = 0)
sub clock selected (CSS = 1)
0
0
HCLK/(213 × N)
SCLK/(23 × N)
0
1
HCLK/(214 × N)
SCLK/(24 × N)
1
0
HCLK/(215 × N)
SCLK/(25 × N)
1
1
HCLK/(216 × N)
SCLK/(26 × N)
HCLK: Peripheral clock frequency that works when the main clock is used
SCLK: Sub clock input frequency
N:
Number of time divisions (based on the display mode selection bits)
Note:
Set the frame interval that is best suited for the frame frequency of the LCD panel to be used.
523
CHAPTER 25 LCD CONTROLLER (LCDC)
■ LCDC Control Register 1 (LCR1)
Figure 25.2-3 Bit Configuration of LCDC Control Register 1 (LCR1)
LCR1
bit 7
Address: 00009BH
Read/Write
Initial value
SEG7
(R/W)
(0)
6
5
4
3
2
1
0
SEG6
(R/W)
(0)
SEG5
(R/W)
(0)
SEG4
(R/W)
(0)
SEG3
(R/W)
(0)
SEG2
(R/W)
(0)
SEG1
(R/W)
(0)
SEG0
(R/W)
(0)
[bit7 to bit0] SEG7 to SEG0: Segment pin enable bits
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
Segment output
0
0
0
0
0
0
0
0
Segment output disabled [Initial value]
0
0
0
0
0
0
0
1
SEG0 to SEG3 outputs enabled
0
0
0
0
0
0
1
1
SEG0 to SEG7 outputs enabled
0
0
0
0
0
1
1
1
SEG0 to SEG11 outputs enabled
0
0
0
0
1
1
1
1
SEG0 to SEG15 outputs enabled
0
0
0
1
1
1
1
1
SEG0 to SEG19 outputs enabled
0
0
1
1
1
1
1
1
SEG0 to SEG23 outputs enabled
0
1
1
1
1
1
1
1
SEG0 to SEG27 outputs enabled
1
1
1
1
1
1
1
1
SEG0 to SEG31 outputs enabled
Using these bits, specify whether to enable each segment output. If you plan to use this product with the
LCD, be sure to set LCR1 = 11111111B.
Note: In addition to the above setting, you need to set the pertinent Port Function Register (PER and
EPER). For further information, see "CHAPTER 4 I/O PORT".
524
CHAPTER 25 LCD CONTROLLER (LCDC)
■ Data Memory for Display (VRAM)
The data memory for display is data RAM with a capacity of 16 bytes. It is used for data setting for
display.
Figure 25.2-4 Bit Configuration of Data Memory for Display (VRAM)
VRAMn (n = 0, 2, 4, 6, 8, 10, 12, 14)
bit 15
Address:
D15
00009CH (VRAM0)
Read/Write (R/W)
Initial value
(X)
00009EH (VRAM2)
0000A0H (VRAM4)
0000A2H (VRAM6)
0000A4H (VRAM8)
0000A6H (VRAM10)
0000A8H (VRAM12)
0000AAH (VRAM14)
14
D14
(R/W)
(X)
13
D13
(R/W)
(X)
12
D12
(R/W)
(X)
11
D11
(R/W)
(X)
10
D10
(R/W)
(X)
9
D09
(R/W)
(X)
8
D08
(R/W)
(X)
VRAMn (n = 1, 3, 5, 7, 9, 11, 13, 15)
bit 7
Address:
D07
00009DH (VRAM1)
Read/Write (R/W)
Initial value
(X)
00009FH (VRAM3)
0000A1H (VRAM5)
0000A3H (VRAM7)
0000A5H (VRAM9)
0000A7H (VRAM11)
0000A9H (VRAM13)
0000ABH (VRAM15)
6
D06
(R/W)
(X)
5
D05
(R/W)
(X)
4
D04
(R/W)
(X)
3
D03
(R/W)
(X)
2
D02
(R/W)
(X)
1
D01
(R/W)
(X)
0
D00
(R/W)
(X)
The VRAM contents are automatically read in synchronization with the appropriate common signal and
output via segment output pins.
The VRAM contents are output via the segment output pins at the same time as they are rewritten to the
data memory for display (VRAM).
If the bits corresponding to the common and segment outputs are set to "1", select wave forms are output
via the segment output pins. If they are set to "0", select wave forms are output via the segment output
pins.
VRAM can be accessed for a read or write at an arbitrary timing irrespective of the operation of the
LCD controller.
VRAM can be accessed for read/write anytime regardless of the LCD controller operation.
525
CHAPTER 25 LCD CONTROLLER (LCDC)
The following table indicates how the individual VRAM elements relate to the common and segment
pins:
Figure 25.2-5 Relationship between VRAM Elements and Common/Segment Pins
VRAM0
VRAM1
VRAM2
VRAM3
VRAM4
VRAM5
VRAM6
VRAM7
VRAM8
VRAM9
VRAM10
VRAM11
VRAM12
VRAM13
VRAM14
VRAM15
bit11
bit15
bit3
bit7
bit11
bit15
bit3
bit7
bit11
bit15
bit3
bit7
bit11
bit15
bit3
bit7
bit11
bit15
bit3
bit7
bit11
bit15
bit3
bit7
bit11
bit15
bit3
bit7
bit11
bit15
bit3
bit7
COM3
bit10
bit14
bit2
bit6
bit10
bit14
bit2
bit6
bit10
bit14
bit2
bit6
bit10
bit14
bit2
bit6
bit10
bit14
bit2
bit6
bit10
bit14
bit2
bit6
bit10
bit14
bit2
bit6
bit10
bit14
bit2
bit6
COM2
bit9
bit13
bit1
bit5
bit9
bit13
bit1
bit5
bit9
bit13
bit1
bit5
bit9
bit13
bit1
bit5
bit9
bit13
bit1
bit5
bit9
bit13
bit1
bit5
bit9
bit13
bit1
bit5
bit9
bit13
bit1
bit5
COM1
bit8
bit12
bit0
bit4
bit8
bit12
bit0
bit4
bit8
bit12
bit0
bit4
bit8
bit12
bit0
bit4
bit8
bit12
bit0
bit4
bit8
bit12
bit0
bit4
bit8
bit12
bit0
bit4
bit8
bit12
bit0
bit4
COM0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
RAM area and common pins used
in 1/2-duty-cycle output mode
RAM area and common pins used
in 1/3-duty-cycle output mode
RAM area and common pins used
in 1/4-duty-cycle output mode
526
CHAPTER 25 LCD CONTROLLER (LCDC)
25.3
Operation of LCD Controller
This section describes the LCD controller/driver (LCDC) operation.
■ Operation of LCD Controller
While the frame interval generation clock is oscillating after configuration required are written to the
registers, the wave forms that drive the LCD are output via the common/segment output pins (COM0 to
COM3 and SEG0 to SEG31) based on the configuration held in the data memory for display.
The LCD is driven by two-frame AC wave forms based on the duty cycle setting held in LCDC control
register 0 (LCR0: MS1, MS0).
Non-select wave forms are output via the COM2 and COM3 pins if the display mode is based on the
duty cycle of 1/2. Non-select wave forms are output via the COM3 pin if the display mode is based on
the duty cycle of 1/3.
When the LCD stops display operation (MS1, MS0 =00B on LCR0), the signals at the common and
segment output pins become "L" level.
■ Frame Interval Generation Clock Selection
Even when the LCD is performing display operation, the frame interval generation clock can be
switched (LCR0: CSS). However, the display may flicker at the time of switching even if the new clock
corresponds to a frame interval that is compatible with the LCD.
To prevent this switching-induced flicker, blank the display by setting the blanking selection bit on
LCDC control register 0 to "1" (LCR0:BK =1), hide status, before switching the frame interval
generation clock.
Also, if the MS bits are changed, operation will be unpredictable during the bit change. Therefore, stop
the LCDC, and then change the MS bits.
■ LCD Drive Wave Forms
The LCD panel will have its display elements deteriorated if driven by DC wave forms. Therefore, it is
driven by two-frame Ac wave forms. One of the following three output wave forms can be selected
using the display mode selection bits of LCD control register 0 (MS1 and MS1 on LCR0).
1/2-duty-cycle output mode (Time division constant = 2)
1/3-duty-cycle output mode (Time division constant = 3)
1/4-duty-cycle output mode (Time division constant = 4)
■ Stop Mode
In stop mode, the LCD controller stops its operation (on the common and segment outputs).
527
CHAPTER 25 LCD CONTROLLER (LCDC)
■ Output Wave Forms during LCD Controller Driver Operation
(1/2 Duty Cycle Output Mode)
In 1/2-duty-cycle output mode, only the outputs from the COM0 and COM1 pins are used for display
on the LCD. Outputs from the COM2 and COM3 pin are not used.
● 1/3-bias, 1/2-duty-cycle Output Wave Form Examples
On the LCD, LCD elements turn on if the potential difference between their common and segment
outputs are the greatest.
If the contents of data memory for display are as indicated in Table 25.3-1, the output wave forms are as
shown in Figure 25.3-1.
Table 25.3-1 Example of Data Memory Contents for Display
Contents of data memory for display
Segment
528
COM3 Output
COM2 output
COM1 output
COM0 output
SEG n output
----
----
0
0
SEG (n+1) output
----
----
1
1
CHAPTER 25 LCD CONTROLLER (LCDC)
Figure 25.3-1 1/3-bias, 1/2-duty-cycle Output Wave Form Examples
COM0 output
COM1 output
COM2 output
COM3 output
SEG n output
SEG (n+1) output
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
ON
LCD element corresponding to
SEG n and COM0 output
OFF
ON
LCD element corresponding to
SEG n and COM1 output
OFF
ON
LCD element corresponding to
SEG (n+1) and COM0 output
OFF
ON
LCD element corresponding to
SEG (n+1) and COM1 output
OFF
529
CHAPTER 25 LCD CONTROLLER (LCDC)
■ Output Wave Forms during LCD Controller Driver Operation
(1/3 Duty Cycle Output Mode)
In 1/3-duty-cycle output mode, the outputs from the COM0 to COM2 pins are used for display on the
LCD. Output from the COM3 pin is not used.
● 1/3-bias, 1/3-duty-cycle Output Wave Form Examples
On the LCD, LCD elements turn on if the potential difference between their common and segment
outputs are the greatest.
If the contents of data memory for display are as indicated in Table 25.3-2, the output wave forms are as
shown in the Figure 25.3-2.
Table 25.3-2 Example of Data Memory Contents for Display
Contents of data memory for display
Segment
530
COM3 Output
COM2 output
COM1 output
COM0 output
SEG n output
----
1
0
0
SEG (n+1) output
----
1
0
1
CHAPTER 25 LCD CONTROLLER (LCDC)
Figure 25.3-2 1/3-bias, 1/3-duty-cycle Output Wave Form Examples
COM0 output
COM1 output
COM2 output
COM3 output
SEG n output
SEG (n+1) output
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
ON
LCD element corresponding to
SEG n and COM0 output
OFF
ON
LCD element corresponding to
SEG n and COM1 output
OFF
ON
LCD element corresponding to
SEG n and COM2 output
OFF
ON
LCD element corresponding to
SEG (n+1) and COM0 output
OFF
ON
LCD element corresponding to
SEG (n+1) and COM1 output
OFF
ON
LCD element corresponding to
SEG (n+1) and COM2 output
OFF
531
CHAPTER 25 LCD CONTROLLER (LCDC)
■ Output Wave Forms during LCD Controller Driver Operation
(1/4 Duty Cycle Output Mode)
In 1/4-duty-cycle output mode, all the outputs from the COM0 to COM3 pins are used for display on
the LCD.
● 1/3-bias, 1/4-duty-cycle Output Wave Form Examples
On the LCD, LCD elements turn on if the potential difference between their common and segment
outputs are the greatest.
If the contents of data memory for display are as indicated in Table 25.3-3, the output wave forms are as
shown in Figure 25.3-3.
Table 25.3-3 Example of Data Memory Contents for Display
Contents of data memory for display
Segment
532
COM3 output
COM2 output
COM1 output
COM0 output
SEG n output
0
1
0
0
SEG (n+1) output
0
1
0
1
CHAPTER 25 LCD CONTROLLER (LCDC)
Figure 25.3-3 1/3-bias, 1/4-duty-cycle Output Wave Form Examples
COM0 output
COM1 output
COM2 output
COM3 output
SEG n output
SEG (n + 1) output
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
ON
Liquid crystal display elements
corresponding to SEG n and
COM0 outputs
OFF
ON
Liquid crystal display elements
corresponding to SEG n and
COM1 outputs
OFF
ON
Liquid crystal display elements
corresponding to SEG n and
COM2 outputs
OFF
ON
Liquid crystal display elements
corresponding to SEG n and
COM3 outputs
OFF
ON
Liquid crystal display elements
corresponding to SEG (n + 1)
and COM0 outputs
OFF
ON
Liquid crystal display elements
corresponding to SEG (n + 1)
and COM1 outputs
OFF
ON
Liquid crystal display elements
corresponding to SEG (n + 1)
and COM2 outputs
OFF
ON
Liquid crystal display elements
corresponding to SEG (n + 1)
and COM3 outputs
OFF
533
CHAPTER 25 LCD CONTROLLER (LCDC)
534
CHAPTER 26
32 kHz CLOCK
CORRECTION UNIT
This chapter outlines the 32 kHz clock correction unit
and describes its register configuration and functions.
26.1 Overview of 32 kHz Clock Correction Unit
26.2 Register of 32 kHz Clock Correction Unit
26.3 Application Notes
535
CHAPTER 26 32 kHz CLOCK CORRECTION UNIT
26.1
Overview of 32 kHz Clock Correction Unit
By using the 32 kHz clock correction module, it is possible to correct the 32 kHz
oscillation clock using the 4 MHz oscillation clock as the standard.
■ About the Correction Unit
When this module is used, by means of the software, the time generated by the 32 kHz clock can be
measured by the 4 MHz clock.
The accuracy of the 32 kHz clock can approach the accuracy of the 4 MHz via processing by software
and the use of this module. The measurements by the 32 kHz clock correction module can be processed
by software. In addition, configuration necessary for the real time clock module can be obtained.
This module is composed of two timers: the timer operating with the 32 kHz clock and the timer
operating with the 4 MHz clock. The 32 kHz timer triggers the 4 MHz timer and the value of the 4 MHz
timer is stored in the register. The value stored in the register is processed by software and the necessary
real time clock module setting is calculated.
■ Block Diagram of the 32 kHz Clock Correction Unit
Figure 26.1-1 Block Diagram of the 32 kHz Clock Correction Unit
UC18CLK
OSC4
CLK4G = OSC4 |~STRT |(READY and ~RUNS);
gate
CLK4G
STRT
READY
RUNS
OSC32
gate
STRT
CLKP
gate
CLKPG
32kHz
timer
CLK32G
RSLEEPB
gate
CLKPG2 CUTD
4MHz
timer
RUN
Counter(16bits)
Synchronous
32->4
Asynchronous
RUN
RST
STRTS
RSLEEPB
STRT
CLKPG2 = CLKP|(~STRT & RSLEEPB);
UC18TRD
READY
RUNS
CUTR
CUTR(24bits)
UC18TRR
READY
STRT
Synchronous
CLKP->32
Asynchronous
RST
STRT
Reset
STR
T
RB
STRT
READY
Set/reset
RUNSS1
RUNSS
INTEN
RBB
RB
Set/reset
RSLEEPB
RSLEEP
INT
RMWB
RMW
Reset
UC18BUS
Set
READY PULSE
CUCR(3bits)
INT_I
INT
Synchronous
4->CLKP
INT_INT
CUTR(24bits)
*_RDB
*_RD
*_WRB
*_WR
RSTB
RST
UC18IO
CUTD(16bits)
CUTD
UC18RBI
FC18
536
CHAPTER 26 32 kHz CLOCK CORRECTION UNIT
■ Timing of 32 kHz Clock Correction Unit
Figure 26.1-2 Measurement Processing Timing
32 kHz
STRT (CLKP)
STRTS (32 kHz)
RUN (32 kHz)
RUNS (4 MHz)
CUTD CUTD-1
32 kHz counter (16-bit)
4 MHz counter (24-bit)
2
1
Former
CUTR
0
CUTD
New CUTR
READY (32 kHz)
READYPULSE (CLKP)
INT (CLKP)
■ Clock Timing of 32 kHz Clock Correction Unit
The module is operated by 3 different clocks: the 4 MHz clock OSC4, the 32 kHz clock OSC32, and the
R-bus clock CLKP. Each domain is made to conform by a synchronous circuit.
All three clocks are gate-controlled. When STRT is "0", the 32 kHz and 4 MHz clocks are switched off.
The CLKPG control signal is RSLEEPB, and the CLKPG2 control signal is RSLEEP and the 2 bits of
STRT; these are set/reset by hardware.
The clock frequency must satisfy the following conditions.
Clock ratio
TOSC32 > 2 × TOSC4 + 3 × TCLKP
TOSC4 < 1/2 × TOSC32 - 3/2 × TCLKP
TCLKP < 1/3 × TOSC32 - 2/3 × TOSC4
Table 26.1-1 Example of valid clock ratio
OSC32
Normal
Operation
32 MHz
OSC4
31.25 μs
4 MHz
CLKP
250 ns
2 MHz or more
500 ns or less
537
CHAPTER 26 32 kHz CLOCK CORRECTION UNIT
26.2
Register of 32 kHz Clock Correction Unit
This section shows the register list of the correction unit and gives a detailed
explanation of each register.
■ Register List of the Correction Unit
● Correction Unit Control Register (CUCR)
Figure 26.2-1 Bit Configuration of Correction Unit Control Register (CUCR)
bit
15
14
13
12
11
10
9
8
Read/Write→
Initial value→
---(R)
(-)
---(R)
(-)
---(R)
(-)
STRT
(R/W)
(0)
---(R)
(-)
---(R)
(-)
INT
(R/W)
(0)
INTEN
(R/W)
(0)
Address: 00015DH
● 32 kHz Timer Data Register (CUTD)
Figure 26.2-2 Bit Configuration of 32 kHz Timer Data Register (CUTD)
bit
Address: 00015EH
Read/Write→
Initial value→
bit
Address: 00015FH
Read/Write→
Initial value→
538
15
14
13
12
11
10
9
8
TDD15
(R/W)
(1)
TDD14
(R/W)
(0)
TDD13
(R/W)
(0)
TDD12
(R/W)
(0)
TDD11
(R/W)
(0)
TDD10
(R/W)
(0)
TDD9
(R/W)
(0)
TDD8
(R/W)
(0)
7
6
5
4
3
2
1
0
TDD7
(R/W)
(0)
TDD6
(R/W)
(0)
TDD5
(R/W)
(0)
TDD4
(R/W)
(0)
TDD3
(R/W)
(0)
TDD2
(R/W)
(0)
TDD1
(R/W)
(0)
TDD0
(R/W)
(0)
CHAPTER 26 32 kHz CLOCK CORRECTION UNIT
● 4 MHz Timer Data Register (CUTR)
Figure 26.2-3 Bit Configuration of 4 MHz Timer Data Register (CUTR)
CUTR1
bit
15
14
13
12
11
10
9
8
---(R)
(-)
---(R)
(-)
---(R)
(-)
---(R)
(-)
---(R)
(-)
---(R)
(-)
---(R)
(-)
---(R)
(-)
7
6
5
4
3
2
1
0
TDR23
(R)
(0)
TDR22
(R)
(0)
TDR21
(R)
(0)
TDR20
(R)
(0)
TDR19
(R)
(0)
TDR18
(R)
(0)
TDR17
(R)
(0)
TDR16
(R)
(0)
15
14
13
12
11
10
9
8
Read/Write→
Initial value→
TDR15
(R)
(0)
TDR14
(R)
(0)
TDR13
(R)
(0)
TDR12
(R)
(0)
TDR11
(R)
(0)
TDR10
(R)
(0)
TDR9
(R)
(0)
TDR8
(R)
(0)
bit
Address: 000163H
Read/Write→
Initial value→
7
6
5
4
3
2
1
0
TDR7
(R)
(0)
TDR6
(R)
(0)
TDR5
(R)
(0)
TDR4
(R)
(0)
TDR3
(R)
(0)
TDR2
(R)
(0)
TDR1
(R)
(0)
TDR0
(R)
(0)
Address: 000160H
Read/Write→
Initial value→
bit
Address: 000161H
Read/Write→
Initial value→
CUTR2
bit
Address: 000162H
■ Correction Unit Control Register (CUCR)
Figure 26.2-4 Bit Configuration of Correction Unit Control Register (CUCR)
bit
15
14
13
12
11
10
9
8
Read/Write→
Initial value→
---(R)
(-)
---(R)
(-)
---(R)
(-)
STRT
(R/W)
(0)
---(R)
(-)
---(R)
(-)
INT
(R/W)
(0)
INTEN
(R/W)
(0)
Address: 00015DH
The control register (CUCR) has the following functions.
• Start/stop correction measurements
• Enable/disable interrupts
• Show the end of correction measurements
539
CHAPTER 26 32 kHz CLOCK CORRECTION UNIT
[bit12] STRT - Start correction
STRT
Function
0
Stop correction, module switch off (Initial value)
1
Start correction
Correction starts when the STRT bit is set to "1" by software. The 32 kHz timer starts its countdown
from the value stored in the 32 kHz timer data register, and the 4 MHz timer starts its count up from "0".
When the 32 kHz timer reaches zero, this bit is reset by hardware to "0".
Correction will stop immediately if software writes "0" in this bit during the correction. If a software
write of "0" and a hardware reset to "0" are generated simultaneously, the hardware operation is given
priority by the software operation.
Namely, the correction ends properly and the INT bit is set to "1". Even if 1 is written in this bit during
correction, it is not affected.
[bit9] INT - Interrupt
INT
Function
0
Correcting/module inactive (Initial value)
1
Correction complete
This bit shows the completion of the correction. After correction starts, when the 32 kHz timer reaches
"0", the 4 MHz timer data register stores the final 4 MHz timer value and the INT bit is set to "1".
When read-modify-write (RMW) instruction is performed for this bit, "1" is read. The flag is cleared
when "0" is written in this bit (INT=0). Even if 1 is written in this bit, it is not affected.
The INT interrupt flag is not reset by hardware. Therefore it is necessary to reset by software before
starting a new correction. Without a reset, the correction completion is only available from the STRT bit
(the INT flag remains "1" even during the correction).
[bit8] INTEN - Interrupt enabled
INTEN
Function
0
Interrupt disabled (Initial value)
1
Interrupt enabled
This is the interrupt enable bit corresponding to the INT bit. When this bit is set to "1" and the INT is set
by hardware, the correction module sends an interrupt signal to the CPU. The INT bit itself is not
affected by the INTEN bit and is set by hardware even when interrupts are disabled (INTEN=0).
540
CHAPTER 26 32 kHz CLOCK CORRECTION UNIT
■ 32 kHz Timer Data Register (16-bit) (CUTD)
Figure 26.2-5 Bit Configuration of 32 kHz Timer Data Register (16-bit) (CUTD)
bit
15
14
13
12
11
10
9
8
TDD14
(R/W)
(0)
TDD13
(R/W)
(0)
TDD12
(R/W)
(0)
TDD11
(R/W)
(0)
TDD10
(R/W)
(0)
TDD9
(R/W)
(0)
TDD8
(R/W)
(0)
7
6
5
4
3
2
1
0
TDD7
(R/W)
(0)
TDD6
(R/W)
(0)
TDD5
(R/W)
(0)
TDD4
(R/W)
(0)
TDD3
(R/W)
(0)
TDD2
(R/W)
(0)
TDD1
(R/W)
(0)
TDD0
(R/W)
(0)
Address: 00015EH
TDD15
Read/Write→ (R/W)
Initial value→
(1)
bit
Address: 00015FH
Read/Write→
Initial value→
The 32 kHz timer data register (CUTD) retains the value that determines the correction period (32kHz
reload value).
The default value when using the 32.768 kHz crystal is "8000H" and corresponds to a measurement
duration of 1s.
Other than when correction is inactive (STRT=0), this register cannot be written.
The 32 kHz timer register stores the value that designates the duration of the correction. When the
correction starts, the stored value is loaded into the 32 kHz timer and a countdown until the timer
reaches "0" starts.
When CUTD is initialized to "0000H", underflow is generated and the measurement value becomes
(FFFFH+1) × TOSC32.
The 32 kHz timer operates with the 32 kHz oscillation clock.
It is necessary to load "8000H"=32768 (decimal) into the CUTD register to obtain a measurement
duration of 1s. This numerical value is obtained from the accurate oscillation frequency of the crystal,
FOSC=32768 Hz. The ideal values of the measurements (when using a 4.00 MHz crystal) are shown in
the table below.
Table 26.2-1 Ideal Measurements Depending on Measurement Duration
Correction time
CUTD value
CUTR value
2s
0000H
7A1200H
1.75 s
E000H
6ACFC0H
1.5 s
C000H
5B8D80H
1.25 s
A000H
4C4B40H
1s
8000H
3D0900H
0.75 s
6000H
2DC6C0H
0.5 s
4000H
1E8480H
0.25 s
2000H
0F4240H
The overall processing time from writing "1" into the STRT bit to the reset by hardware of STRT is
longer than the actual correction duration in order to synchronize the different clock domains.
The processing time becomes (CUTD + 3) × TOSC32.
The exact correction duration becomes CUTD × TOSC32.
541
CHAPTER 26 32 kHz CLOCK CORRECTION UNIT
■ 4 MHz Timer Data Register (24-bit) (CUTR)
Figure 26.2-6 Bit Configuration of 4 MHz Timer Data Register (24-bit) (CUTR)
bit
Address: 000160H
Read/Write→
Initial value→
bit
Address: 000161H
Read/Write→
Initial value→
bit
15
14
13
12
11
10
9
8
---(R)
(-)
---(R)
(-)
---(R)
(-)
---(R)
(-)
---(R)
(-)
---(R)
(-)
---(R)
(-)
---(R)
(-)
7
6
5
4
3
2
1
0
TDR23
(R)
(0)
TDR22
(R)
(0)
TDR21
(R)
(0)
TDR20
(R)
(0)
TDR19
(R)
(0)
TDR18
(R)
(0)
TDR17
(R)
(0)
TDR16
(R)
(0)
15
14
13
12
11
10
9
8
TDR14
(R)
(0)
TDR13
(R)
(0)
TDR12
(R)
(0)
TDR11
(R)
(0)
TDR10
(R)
(0)
TDR9
(R)
(0)
TDR8
(R)
(0)
Address: 000162H
TDR15
Read/Write→
(R)
Initial value→
(0)
bit
Address: 000163H
Read/Write→
Initial value→
7
6
5
4
3
2
1
0
TDR7
(R)
(0)
TDR6
(R)
(0)
TDR5
(R)
(0)
TDR4
(R)
(0)
TDR3
(R)
(0)
TDR2
(R)
(0)
TDR1
(R)
(0)
TDR0
(R)
(0)
The timer data register (CUTR) retains the value of the correction results (4 MHz counter).
The end of the correction is indicated by the INT bit and the STRT bit of the CUCR register.
The CUTR value becomes valid when INT changes from "0" to "1" and STRT changes from "1" to "0".
The 4 MHz timer data register stores the correction results. When the correction starts, the 4 MHz timer
starts to count up from zero. The 4 MHz timer stops when the 32 kHz reaches "0", and the register
retains the correction results until the next correction is triggered by software.
If this register is read during correction, the value obtained will be random.
There is no effect even if the register is written in by software.
The 4 MHz timer operates with the 4 MHz oscillation clock.
Note:
If this register is read during correction, the value obtained will be random.
542
CHAPTER 26 32 kHz CLOCK CORRECTION UNIT
26.3
Application Notes
This section shows application notes dealing with correction accuracy, power
dissipation and measurement time.
■ 32 kHz Timer Data Register Configuration
The 32 kHz timer data register setting can be calculated according to the method below.
When a duration of 1s is required for the correction, it is necessary to set "8000H"=32768Dec in the 32
kHz timer data register. This shows the 32,768 pulse of the 32.768 kHz oscillation clock.
Approximately "3D0900H" values are stored within the 4 MHz timer data register by this setting. These
values show 4,000,000 pulses of the 4 MHz oscillator.
Table 26.3-1 Ideal Measurements for the 32.768 kHz Oscillator and the 4.0 MHz Oscillator
(CUTR)
Correction time
CUTD value
CUTR value
2s
0000H
7A1200H
1.75 s
E000H
6ACFC0H
1.5 s
C000H
5B8D80H
1.25 s
A000H
4C4B40H
1s
8000H
3D0900H
0.75 s
6000H
2DC6C0H
0.5 s
4000H
1E8480H
0.25 s
2000H
0F4240H
Correction accuracy together with power dissipation is important when using the correction module.
543
CHAPTER 26 32 kHz CLOCK CORRECTION UNIT
544
CHAPTER 27
CPU OPERATION
DETECTION RESET CIRCUIT
This chapter describes the functions and operation of
the CPU operation detection reset circuit.
27.1 Overview of CPU Operation Detection Reset Circuit
27.2 Registers in the CPU Operation Detection Reset Circuit
27.3 CPU Operation Detection Reset Circuit Operation
27.4 Notes on Using the CPU Operation Detection Reset Circuit
545
CHAPTER 27 CPU OPERATION DETECTION RESET CIRCUIT
27.1
Overview of CPU Operation Detection Reset Circuit
The CPU operation detection reset circuit is a 20-bit counter that is based on the source
oscillation as the count clock and generates a setting initialization reset if it is not
cleared within a certain period of time after start.
■ CPU Operation Detection Reset Circuit
The CPU operation detection reset circuit is a counter designed to prevent program runaways. After a
reset, the circuit will start automatically. After started, it must be cleared at certain regular intervals. If it
is not cleared longer than a predetermined period of time due to an endless loop or other problem, it
generates an internal reset.
Table 27.1-1 Interval for the CPU Operation Detection Reset Circuit
Interval
Number of oscillation clock cycles
About 262 ms
220 cycles
It is assumed that the oscillation clock frequency is 4 MHz.
Note:
In any mode in which the CPU becomes inactive, this circuit stops.
The conditions for this circuit to be cleared are as follows:
• Writing "0" to the CL bit of the LCRC register
• Internal reset
• Main oscillation clock stop (required if the sub clock is in use)
• Transition to sleep mode
• Transition to RTC mode
• Transition to STOP mode
546
CHAPTER 27 CPU OPERATION DETECTION RESET CIRCUIT
■ CPU Operation Detection Reset Circuit Block Diagram
The CPU operation detection reset circuit consists of the following two blocks:
• CPU operation detection circuit
• CPU operation detection reset control register (LVRC)
Figure 27.1-1 CPU Operation Detection Reset Circuit Block Diagram
CPU operation detection circuit
Oscillation clock
Counter
OF
Internal reset
F/F
Clear
RESV0 RESV0 RESV0 RESV1
CL
RESV0 RESV0 CPUF
CPU detection reset control register (LVRC)
Internal data bus
● CPU operation detection circuit
This circuit is a counter designed to prevent program runaways. After started, it must be cleared at
certain regular intervals.
● CPU operation detection reset control register (LVRC)
This register is used to clear the counter for the CPU operation detection reset flag and the CPU
operation detection function.
● The reset factors for CPU operation detection reset circuit
If a counter in the CPU operation detection circuit is not cleared within a certain period of time, a
setting initialization reset is generated.
The CPU operation detection reset circuit must work only on the main clock. It cannot be used on the
sub clock.
547
CHAPTER 27 CPU OPERATION DETECTION RESET CIRCUIT
27.2
Registers in the CPU Operation Detection Reset Circuit
The CPU operation detection reset control register (LVRC) is used to clear the counters
for the CPU operation detection reset flag and the CPU operation detection circuit etc.
■ CPU Operation Detection Reset Control Register (LVRC)
Figure 27.2-1 CPU Operation Detection Reset Control Register (LVRC)
Address
bit7
bit6
bit5
bit4
00057DH RESV0 RESV0 RESV0 RESV1
R/W
R/W
R/W
R/W
bit3
CL
bit2
R/W
R/W
00011000B
R/W
0
1
Overflow
CL
0
1
548
R/W
Initial value
CPU operation detection flag bit
Read
Write
No overflow This bit cleared
RESV0
: Readable/writable
: Undefined value
: Initial value
bit0
RESV0 RESV0 CPUF
CPUF
R/W
X
bit1
No change and no influence on other
components
Reserved bit
Be sure to write "0" to this bit.
CPU operation detection circuit clear bit
The counter cleared
No change and no influence on other components
RESV1
Reserved bit
Be sure to write "1" to this bit.
RESV0
Reserved bit
Be sure to write "0" to this bit.
CHAPTER 27 CPU OPERATION DETECTION RESET CIRCUIT
Table 27.2-1 Function of Each Bit in the CPU Operation Detection Reset Control Register
Bit name
bit7
to
bit5
Function
RESV0:
Reserved bits
Note:
Be sure to write "0" to the RESV0 bit.
bit4
RESV1:
Reserved bit
Note:
Be sure to write "1" to the RESV1 bit.
bit3
CL:
CPU operation
detection clear
bit
This bit is used to clear the counter in the CPU operation detection circuit.
This bit is reset to "0" when "0" is written to it.
This bit is always "1" when read.
bit2
RESV0:
Reserved bit
Note:
Be sure to write "0" to the RESV0 bit.
bit1
RESV0:
Reserved bit
Note:
Be sure to write "0" to the RESV0 bit.
CPUF:
CPU operation
detection flag bit
When the counter for the CPU operation detection function overflows, the CPUF bit is set to
"1".
A write to this bit clears it to "0". Any attempt to write "1" does not affect the CPUF bit.
This bit is not initialized by an internal reset, but is initialized by an external reset input.
bit0
549
CHAPTER 27 CPU OPERATION DETECTION RESET CIRCUIT
27.3
CPU Operation Detection Reset Circuit Operation
The CPU operation detection function generates an internal reset if the counter is not
cleared at certain regular intervals. The register contents are unpredictable after an
internal reset is generated due to the detection of a CPU runaway. After the operation
stabilization wait time subsequent to the clearing of the reset status, a reset sequence
will be executed, and then program execution will resume at the address designated by
the reset vector.
■ CPU Operation Detection Reset Circuit Operation
After clearing of reset, the CPU operation detection reset circuit starts CPU operation detection
immediately without spending the operation stabilization wait time.
550
CHAPTER 27 CPU OPERATION DETECTION RESET CIRCUIT
27.4
Notes on Using the CPU Operation Detection Reset Circuit
This section explains precautions for using the CPU operation detection reset circuit.
■ Notes on Using the CPU Operation Detection Reset Circuit
● Prohibition of program-controlled disabling
The CPU operation detection reset circuit starts and continues operation immediately after power-on.
This operation cannot be stopped under software control.
● Suppression of reset generation by the CPU operation detection function
To suppress reset generation by the CPU operation detection function, the counter needs to be cleared at
certain regular intervals. Reset generations can be suppressed by writing "0" to the CL bit of the LVRC
register to clear the counter.
● Stopping and clearing the counter
The CPU operation detection function clears the counter and stops its operation in any mode in which
the CPU becomes inactive.
● CPU operation detection reset during DMA transfer
During DMA transfer between modules connected in the D-bus, a CPU operation detection reset will be
generated when continuous transfer time exceeds 262 ms (at an original oscillation frequency of 4
MHz) because "0" cannot be written to the CL bit.
● Warning on transition to a mode based on the sub clock
Upon transition to sub clock operation mode, stop the main clock and clear the CPU detection reset
circuit.
● Operational condition for CPU operation detection mode
• This function only works when the main oscillation clock, rather than the sub clock, is used.
• This function cannot be used in STOP, SLEEP, or RTC mode. Before entering one of these modes, clear
the CPU operation detection reset circuit.
551
CHAPTER 27 CPU OPERATION DETECTION RESET CIRCUIT
552
CHAPTER 28
FLASH MEMORY
This chapter gives an overview of flash memory and
describes its register configuration/functions and
operations.
28.1 Overview of FLASH Memory
28.2 FLASH Memory Register
28.3 FLASH Memory Access Modes
28.4 Auto Algorithm Activation Method
28.5 Execution Status of Auto Algorithm
28.6 Details on Writing/Erasing FLASH Memory
28.7 Sector Protecting Operations
553
CHAPTER 28 FLASH MEMORY
28.1
Overview of FLASH Memory
A 256 Kbyte (2 Mbit) FLASH memory is integrated in the MB91F248/S, 512 Kbyte (4 Mbit)
FLASH memory is integrated in the MB91F249/S featuring a sector erasing function
(sector-by-sector or sectors batch erase) with a +3.3V single power supply. This FLASH
memory also supports half word (16-bit) writing.
■ Overview of FLASH Memory
This is a built-in 3.3V, 256 Kbyte (MB91F248/S)/512 Kbyte (MB91F249/S) FLASH memory. With the
exception of its capacity and a part of its sector structure, it is the same as our 2 Mbit (256K × 8/128K ×
16/64K × 32)/4 Mbit (512K × 8/256K × 16) FLASH memory, MBM29LV200TC/MBM29LV400TC. It
supports writing from outside the device by using a ROM writer.
In addition to the equivalent features of the MBM29LV200TC/MBM29LV400TC, this FLASH memory,
when used as a FR-CPU built-in ROM, supports word-length (32-bit) instructions/data reading which
allows devices to operate faster.
Data can be written to this memory by using a program that operates in either single chip mode or internal
ROM external bus mode.
In addition to this document, refer to the MBM29LV200TC/MBM29LV400TC Datasheet.
Integration of the FLASH memory macro and the FR-CPU interface circuit has the following
advantages:
•
•
Functions as memory for CPU writing/data storing
-
When used as a ROM, it is accessible in 32-bit bus width
-
Supports Read/write/erase by CPU (Auto-programming Algorithm*)
Offers equivalent features as a stand alone FLASH memory product, MBM29LV200TC/
MBM29LV400TC
Supports Read/write/erase by ROM writer (Auto-programming Algorithm*).
*: Auto programming Algorithm = Embedded Algorithm
This document provides information on the use of the FLASH memory from FR-CPU.
For information on the use of the FLASH memory from a ROM writer, refer to "the ROM writer User's
Guide".
■ Execution Status of Auto Algorithm
If the Auto Algorithm was started by the CPU programming mode, use the internal Ready signal (RDY)
to monitor the execution status of Auto Algorithm. The level of this Ready signal may be read as the
RDY bit in the FLASH memory status register.
If the RDY bit is "0", writing or erasing is currently processed by Auto Algorithm. During this process,
no other writing or erasing instructions may be received. Reading data from the FLASH memory
address may not be accepted either. The data read while the RDY bit is "0" becomes a hardware
sequence flag which indicates the status of FLASH memory (See section "28.4 Auto Algorithm
Activation Method").
554
CHAPTER 28 FLASH MEMORY
■ Writing from a ROM Writer
This FLASH memory supports writing from outside the device by using a ROM writer. In this mode,
the same pin functions as our stand alone FLASH memory product MBM29LV200TC/
MBM29LV400TC are assigned, and the FR-CPU stops. In CPU mode, the address line connections and
the mapping of the memory area are altered. For more information, refer to "Corresponding ROM
Writer Specification".
■ FLASH Memory Block Diagram
Figure 28.1-1 FLASH Memory Block Diagram (MB91F248/S)
CPU
FLASH interface
CPU core
FLASH memory
Control signal
Control signal
Control signal
A0 to A17
A-1/A0 to A17
Address
DQ0 to DQ15
DQ0 to DQ15
Data
Control
signal
Address
FLASH
writer
interface
(in
FLASH
mode)
Data
555
CHAPTER 28 FLASH MEMORY
■ Sector Structure of the FLASH Memory
The address map of the FLASH memory differs between access from the FR-CPU and ROM writer.
Figure 28.1-2 and Table 28.1-1 show the address map when accessing from the FR-CPU; Figure 28.1-5
shows the address map when accessing from a ROM writer.
● Map when accessing from the FR-CPU
Figure 28.1-2 Map when Accessing from the FR-CPU (MB91F248/S)
FFFFFFFFH
000FFFFFH
SA4 (16 Kbytes)
SA9 (16 Kbytes)
SA3 (8 Kbytes)
SA8 (8 Kbytes)
SA2 (8 Kbytes)
SA7 (8 Kbytes)
SA1 (32 Kbytes)
SA6 (32 Kbytes)
SA0 (64 Kbytes)
SA5 (64 Kbytes)
000F8000H
000F7FFFH
000F4000H
00100000H
000F3FFFH
000FFFFFH
000F0000H
FLASH
memory
256 Kbytes
000C0000H
000EFFFFH
000E0000H
000DFFFFH
00000000H
000C0000H
bit 31
Byte position when accessing in
CPU mode
556
16 15
0
1
0
2
3
CHAPTER 28 FLASH MEMORY
Table 28.1-1 Sector address List (Accessing from FR-CPU) (MB91F248/S)
Sector
Address
Address Range
Corresponding bit position
Sector Capacity
SA9
000FFFFFH to 000F8000H
bit15 to bit0
16 Kbytes
SA8
000F7FFFH to 000F4000H
bit15 to bit0
8 Kbytes
SA7
000F3FFFH to 000F0000H
bit15 to bit0
8 Kbytes
SA6
000EFFFFH to 000E0000H
bit15 to bit0
32 Kbytes
SA5
000DFFFFH to 000C0000H
bit15 to bit0
64 Kbytes
SA4
000FFFFFH to 000F8000H
bit15 to bit0
16 Kbytes
SA3
000F7FFFH to 000F4000H
bit15 to bit0
8 Kbytes
SA2
000F3FFFH to 000F0000H
bit15 to bit0
8 Kbytes
SA1
000EFFFFH to 000E0000H
bit15 to bit0
32 Kbytes
SA0
000DFFFFH to 000C0000H
bit15 to bit0
64 Kbytes
557
CHAPTER 28 FLASH MEMORY
Figure 28.1-3 FLASH Memory Block Diagram (MB91F249/S)
CPU
FLASH interface
CPU core
FLASH memory
Control signal
Control signal
Control signal
A0 to A18
A0 to A18
Address
DQ0 to DQ15
DQ0 to DQ15
Data
Control
signal
Address
FLASH
writer
interface
(in
FLASH
mode)
Data
Figure 28.1-4 Map when Accessing from the FR-CPU (MB91F249/S)
000F FFFFH
FFFF FFFFH
SA6 (16 Kbytes)
SA13 (16 Kbytes)
SA5 (8 Kbytes)
SA12 (8 Kbytes)
SA4 (8 Kbytes)
SA11 (8 Kbytes)
SA3 (32 Kbytes)
SA10 (32 Kbytes)
SA2 (64 Kbytes)
SA9 (64 Kbytes)
SA1 (64 Kbytes)
SA8 (64 Kbytes)
SA0 (64 Kbytes)
SA7 (64 Kbytes)
000F 8000H
000F 7FFFH
000F 4000H
000F 3FFFH
0010 0000H
000F 0000H
000F FFFFH
FLASH
memory
512Kbytes
0008 0000H
000E FFFFH
000E 0000H
000D FFFFH
000C 0000H
0000 0000H
000B FFFFH
000A 0000H
0009 FFFFH
0008 0000H
bit 31
Byte position when accessing
in CPU mode
558
16 15
0
1
0
2
3
CHAPTER 28 FLASH MEMORY
Table 28.1-2 Sector address List (Accessing from FR-CPU) (MB91F249/S)
Sector
Address
Address Range
Corresponding bit position
Sector Capacity
SA13
000F FFFFH to 000F 8000H
bit15 to bit0
16 Kbytes
SA12
000F 7FFFH to 000F 4000H
bit15 to bit0
8 Kbytes
SA11
000F 3FFFH to 000F 0000H
bit15 to bit0
8 Kbytes
SA10
000E FFFEH to 000E 0000H
bit15 to bit0
32 Kbytes
SA9
000D FFFEH to 000C 0000H
bit15 to bit0
64 Kbytes
SA8
000B FFFEH to 000A 0000H
bit15 to bit0
64 Kbytes
SA7
0009 FFFEH to 0008 0000H
bit15 to bit0
64 Kbytes
SA6
000F FFFCH to 000F 8000H
bit31 to bit15
16 Kbytes
SA5
000F 7FFCH to 000F 4000H
bit31 to bit15
8 Kbytes
SA4
000F 3FFCH to 000F 0000H
bit31 to bit15
8 Kbytes
SA3
000E FFFCH to 000E 0000H
bit31 to bit15
32 Kbytes
SA2
000D FFFCH to 000C 0000H
bit31 to bit15
64 Kbytes
SA1
000B FFFCH to 000A 0000H
bit31 to bit15
64 Kbytes
SA0
0009 FFFCH to 0008 0000H
bit31 to bit15
64 Kbytes
559
CHAPTER 28 FLASH MEMORY
● Map when accessing from a ROM writer
Figure 28.1-5 Address Map when Accessing from a ROM Writer (MB91F248/S)
8 bits
FFFFFH
000FFFFFH
000FC000H
SA9 (16 Kbytes)
000FBFFFH
000FA000H
SA8 (8 Kbytes)
000F9FFFH
000F8000H
SA7 (8 Kbytes)
000F7FFFH
000F0000H
SA6 (32 Kbytes)
000EFFFFH
000E0000H
SA5 (64 Kbytes)
000DFFFFH
000DC000H
SA4 (16 Kbytes)
000DBFFFH
000DA000H
SA3 (8 Kbytes)
000D9FFFH
000D8000H
SA2 (8 Kbytes)
000D7FFFH
000D0000H
SA1 (32 Kbytes)
000CFFFFH
000C0000H
SA0 (64 Kbytes)
bit15
560
bit0
1
0
Byte position (while writing from a writer)
0
1
While being read by CPU
CHAPTER 28 FLASH MEMORY
Table 28.1-3 Sector address List (Accessing from a ROM Writer) (MB91F248/S)
Sector
Address
Address Range
Corresponding bit position
Sector Capacity
8bits
000FFFFFH
bit15 to bit0
-
SA9 (16 Kbytes)
000FFFFFH to 000FC000H
bit15 to bit0
16 Kbytes
SA8 (8 Kbytes)
000FBFFFH to 000FA000H
bit15 to bit0
8 Kbytes
SA7 (8 Kbytes)
000F9FFFH to 000F8000H
bit15 to bit0
8 Kbytes
SA6 (32 Kbytes)
000F7FFFH to 000F0000H
bit15 to bit0
32 Kbytes
SA5 (64 Kbytes)
000EFFFFH to 000E0000H
bit15 to bit0
64 Kbytes
SA4 (16 Kbytes)
000DFFFFH to 000DC000H
bit15 to bit0
16 Kbytes
SA3 (8 Kbytes)
000DBFFFH to 000DA000H
bit15 to bit0
8 Kbytes
SA2 (8 Kbytes)
000D9FFFH to 000D8000H
bit15 to bit0
8 Kbytes
SA1 (32 Kbytes)
000D7FFFH to 000D0000H
bit15 to bit0
32 Kbytes
SA0 (64 Kbytes)
000CFFFFH to 000C0000H
bit15 to bit0
64 Kbytes
561
CHAPTER 28 FLASH MEMORY
Figure 28.1-6 Address Map when Accessing from a ROM Writer (MB91F249/S)
000F FFFFH
000F C000H
SA13 (16 Kbytes)
000F BFFFH
000F A000H
SA12 (8 Kbytes)
000F 9FFFH
000F 8000H
SA11 (8 Kbytes)
000F 7FFFH
000F 0000H
SA10 (32 Kbytes)
000E FFFFH
000E 0000H
SA9 (64 Kbytes)
000D FFFFH
000D 0000H
SA8 (64 Kbytes)
000C FFFFH
000C 0000H
SA7 (64 Kbytes)
000B FFFFH
000B C000H
SA6 (16 Kbytes)
000B BFFFH
000B A000H
SA5 (8 Kbytes)
000B 9FFFH
000B 8000H
SA4 (8 Kbytes)
000B 7FFFH
000B 0000H
SA3 (32 Kbytes)
000A FFFFH
000A 0000H
SA2 (64 Kbytes)
0009 FFFFH
0009 0000H
SA1 (64 Kbytes)
0008 FFFFH
0008 0000H
SA0 (64 Kbytes)
bit15
562
bit0
1
0
Byte position (while writing from a writer)
0
1
While being read by CPU
CHAPTER 28 FLASH MEMORY
Table 28.1-4 Sector address List (Accessing from a ROM Writer) (MB91F249/S)
Sector
Address
Address Range
Corresponding bit position
Sector Capacity
SA13 (16 Kbytes)
000F FFFFH to 000F C000H
bit15 to bit0
16 Kbytes
SA12 (8 Kbytes)
000F BFFFH to 000F A000H
bit15 to bit0
8 Kbytes
SA11 (8 Kbytes)
000F 9FFFH to 000F 8000H
bit15 to bit0
8 Kbytes
SA10 (32 Kbytes)
000F 7FFFH to 000F 0000H
bit15 to bit0
32 Kbytes
SA9 (64 Kbytes)
000E FFFFH to 000E 0000H
bit15 to bit0
64 Kbytes
SA8 (64 Kbytes)
000D FFFFH to 000D 0000H
bit15 to bit0
64 Kbytes
SA7 (64 Kbytes)
000C FFFFH to 000C 0000H
bit15 to bit0
64 Kbytes
SA6 (16 Kbytes)
000B FFFFH to 000B C000H
bit15 to bit0
16 Kbytes
SA5 (8 Kbytes)
000B BFFFH to 000B A000H
bit15 to bit0
8 Kbytes
SA4 (8 Kbytes)
000B 9FFFH to 000B 8000H
bit15 to bit0
8 Kbytes
SA3 (32 Kbytes)
000B 7FFFH to 000B 0000H
bit15 to bit0
32 Kbytes
SA2 (64 Kbytes)
000A FFFFH to 000A 0000H
bit15 to bit0
64 Kbytes
SA1 (64 Kbytes)
0009 FFFFH to 0009 0000H
bit15 to bit0
64 Kbytes
SA0 (64 Kbytes)
0008 FFFFH to 0008 0000H
bit15 to bit0
64 Kbytes
563
CHAPTER 28 FLASH MEMORY
28.2
FLASH Memory Register
The FLASH memory has two registers; the FLASH memory status register (FLCR) and
the FLASH memory wait register (FLWC).
■ FLASH Memory Register List
Figure 28.2-1 shows the list of FLASH memory registers.
Figure 28.2-1 FLASH Memory Register List
bit7
0
FLASH memory wait register (FLWC)
bit7
0
FLASH memory status register (FLCR)
Table 28.2-1 Address Map
Register
Address
Block
+0
+1
+2
+3
007000H
FLCR [R/W] B
01XX1000
-
-
-
FLASH interface
007004H
FLWC [R/W] B
00000011
-
-
-
FLASH interface
564
CHAPTER 28 FLASH MEMORY
■ FLASH Memory Status Register (FLCR)
Figure 28.2-2 Bit Configuration of the FLASH Memory Status Register (FLCR)
Address:
bit 7
6
5
4
3
2
1
0
-
-
BIRE
-
RDY
-
WE
-
Read/Write
R/W
R/W
R/W
R
R
R/W
R/W
R/W
Initial value
0
1
X
X
1
0
0
0
007000H
The FLASH memory status register (FLCR) is used to indicate the operation status of the FLASH
memory. This register is used to control interrupt to the CPU and the writing to the FLASH memory. It
is only accessible from the CPU. It is not accessible while it is loaded on the writer.
Do not access to this register with any read-modify-write (RMW) instruction.
The function of each bit is described as follows:
[bit7] (Reserved bit)
This bit is reserved. Always write "0" to this bit.
[bit6] (Reserved bit)
This bit is reserved. Always write "1" to this bit.
[bit5] BIRE: Burn In ROM Enable
In Burn In ROM mode, this bit is used to control access to the Burn In ROM area which overlaps with
the FLASH memory.
BIRE
Function
0
Disable Burn In ROM access
1
Enable Burn In ROM access
This bit can be set only when the BIRM (Burn In ROM) input is "1".
[bit4] (Reserved bit)
This bit is reserved. This bit is read-only and writing has no affect on operations.
[bit3] RDY: This bit indicates the operation status of the Auto Algorithm.
RDY
Function
0
It is being read/written therefore it does not accept writing, reading or erasing data
instructions.
1
Accepts writing, reading or erasing data instructions
The RDY signal takes 90ns to indicate the operation status after writing to the FLASH-ROM.
Do not use this signal to determine whether writing is completed, because it is used for checking
whether FLASH-ROM is able to accept writing/reading. Use the data polling to determine whether
writing is completed.
565
CHAPTER 28 FLASH MEMORY
[bit2] (Reserved bit)
This bit is reserved. Always write "0" to this bit.
[bit1] WE: This bit is used to control writing of data/instruction to the FLASH memory in
CPU mode.
While this bit is "0", all the data or instructions writing to the FLASH memory are invalid. And data
reading from the FLASH memory is performed in 32-bit access.
While this bit is "1", data or instruction writing to the FLASH memory is valid and activation of the
Auto Algorithm is enabled.
However, data reading or writing from the FLASH memory is in 16-bit access. When accessing to the
FLASH memory, use the 16-bit access only. 32 or 8-bit access prohibited.
Ensure that the Auto Algorithm is stopped before changing this bit by checking the RDY bit.
While RDY bit is "0", this bit cannot be changed.
WE
Function
0
Disables writing to FLASH memory; 32 bit read mode
1
Enables writing to FLASH memory; 16 bit read mode
[bit0] (Reserved bit)
This bit is reserved. Always write "0" to this bit.
■ FLASH Wait Register (FLWC)
Figure 28.2-3 Bit Configuration of FLASH Wait Register (FLWC)
Address
bit 7
6
5
4
3
-
-
FAC1
FAC0
-
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
1
1
007004H
2
1
0
WTC2 WTC1 WTC0
In CPU mode, the FLASH wait register (FLWC) is used to control waiting of the FLASH memory.
The function of each bit in the FLASH wait register (FLWC) is described as follows:
[bit7, bit6] (Reserved bits)
These bits are reserved. Always write "0" to these bits.
[bit5, bit4] FAC1, FAC0: Pulse width control bits for internal write signals
FAC1
FAC0
ATDIN
EQIN
0
0
0.5 clock
1 clock [Default]
0
1
1 clock
1.5 clocks
1
0
1.5 clocks
2 clocks
1
1
2 clocks
2.5 clocks
Note: ATDIN, EQIN are internal write signals. Normally, use the default setting.
566
CHAPTER 28 FLASH MEMORY
[bit3] (Reserved bit)
This bit is reserved. Always write "0" in this bit.
[bit2 to bit0] WTC2 to WTC0: Wait cycle control bits
This bit is used to control the wait cycles for FLASH access.
WTC2
WTC1
WTC0
Wait Cycle
Flash Read
Flash Write
0
0
0
-
Disabled
Disabled
0
0
1
1
Operable up to 33 MHz
Disabled
0
1
0
2
Operable up to 33 MHz
Disabled
0
1
1
3
Operable up to 33 MHz
Operable up to 33 MHz [Default]
1
0
0
4
Disabled
Disabled
1
0
1
5
Disabled
Disabled
1
1
0
6
Disabled
Disabled
1
1
1
7
Disabled
Disabled
Notes:
• Ensure to set the same or higher value than the cycle set in the FAC1, FAC0.
• Initial set value is for write. If performing read only (FLCR: WE = 0), by setting the wait cycle to 1
(WTC2, WTC1, WTC0 = 001B), the fastest speed can be achieved.
567
CHAPTER 28 FLASH MEMORY
28.3
FLASH Memory Access Modes
When accessing from the FR-CPU, there are two access modes:
• ROM mode:
a word (32-bit length) can be read simultaneously, but cannot be written.
• Programming mode:
a word (32-bit length) cannot be accessed, but can be written in half word (16-bit)
length.
■ FR-CPU ROM Mode (32/16/8-bit, Read Only)
This mode makes the FLASH memory to work as a built-in FR-CPU ROM. It can read full-word (32bit) length data. However, this mode does not support writing in the FLASH memory or starting Auto
Algorithm.
● How to set this mode
• This mode is set when the WE bit of the FLASH memory status register is "0".
• After reset cancellation during the CPU operation, the FLASH memory is always in this mode.
• This mode can only be set during the CPU operation.
● Operations
When reading FLASH memory area, data is read in full-word (32-bit) length at once.
The number of cycles required for a read is 2 per word (1 wait). This makes it possible to supply
instructions to FR-CPU without any wait.
● Restrictions
Note that the addressing method and the endian in this mode are different from those which are in effect
when a ROM writer is in use. In this mode, writing of instructions or data to the FLASH memory is
disabled.
■ FR-CPU Programming Mode (16-bit, Read/Write)
This mode enables erasing/writing of data. Since the data access in full-word (32-bit) length is disabled
in this mode, programs on the FLASH memory can not be executed.
● How to set this mode
• This mode is set when the WE bit of the FLASH memory status register (FLCR) is "1".
• After reset cancellation during the CPU operation, the WE bit is set to "0". To turn to this mode, write
"1" to the WE bit. When the WE bit becomes "0" upon reset or by writing "0", the mode returns to ROM
mode.
• During the RDY bit of the FLASH memory status register (FLCR) is "0", the WE bit cannot be
changed. Ensure that the RDY bit is "1" before changing the WE bit.
568
CHAPTER 28 FLASH MEMORY
● Operations
• When reading the FLASH memory area, memory data is read in half word (16-bit) length at once.
The number of cycles required for a read is 4 per half word (3 wait).
• By writing instructions to the FLASH memory, the Auto Algorithm can be started. Starting the Auto
Algorithm enables erasing/wiring data in FLASH memory.
For details on the Auto Algorithm, see the following pages.
● Restrictions
• Note that the addressing method and the endian in this mode are different from those which are used
when a ROM writer is in use. In this mode, reading data in full-word (32-bit) length is prohibited.
• In this mode, reading data in full-word (32-bit) length is prohibited.
• When you change the WE bit in order to change to the programming access mode, follow the
restrictions described in section "■FLASH Memory Status Register (FLCR)".
■ FLASH Memory Mode
If you set the MD2 to MD0 pins to "111B" and reset, then the CPU stops its operation. At this state, the
FLASH memory interface circuit function causes a part of the signals in port 2 to port B to be directly
connected to the control signals of the FLASH memory device, and allows direct connections to the
FLASH memory device from the external pins. In this mode, the FLASH memory appears to be a
stand-alone memory available via external pins. This mode is used mainly for writing/erasing using a
FLASH memory writer. In this mode, all operations of the Auto Algorithm in the 2 Mbit/4 Mbit
FLASH memory are enabled.
569
CHAPTER 28 FLASH MEMORY
■ Relationship between the MBM29LV200TC/MBM29LV400TC and the FLASH Memory
Control Signals
Table 28.3-1 shows the relationship between the MBM29LV200TC/MBM29LV400TC and the FLASH
memory control signals.
Table 28.3-1 Relationship between the MBM29LV200TC/MBM29LV400TC and the FLASH Memory Control
Signals
MB91F248/S, MB91F249/S external control pins
MBM29LV200TC/
MBM29LV400TC
External pins
FLASH memory mode
FR-CPU mode
Normal operation
VID applied pins
RESET
RSTX
RSTX
MD1
RY/BY
None
RY/BY
-
BYTE
Internal "H" fixed
BYTEX
-
WEX
-
OEX
MD2
CE
CEX
-
A17 to A10*1
A18 to A11
-
A16 to A10*2
A17 to A11
-
A10
MD0
A8 to A0
A9 to A1
-
A-1
A0
-
None
-
D7 to D0
-
WE
OE
A9
Internal control signal
controlled by +I/F circuit
Internal address bus
DQ15 to DQ8
Internal data bus
DQ7 to DQ0
*1: MB91F249/S
*2: MB91F248/S
570
CHAPTER 28 FLASH MEMORY
28.4
Auto Algorithm Activation Method
Writing/erasing in the FLASH memory can be performed by starting the Auto Algorithm
built into the FLASH memory.
■ Instruction Operation
To start the Auto Algorithm, execute consecutive writing of a half word (16-bit) data to the FLASH
memory one to six times. This is called a instruction. The FLASH memory will be reset to the read-only
mode if an invalid address or data is written, or the order of address and data is wrong.
Table 28.4-1 shows the list of instructions.
Table 28.4-1 List of the Instructions
Instruction
Sequence
Number of
Accesses
1st Write
Cycle
2nd Write
Cycle
3rd Write
Cycle
4th Write
/Read Cycle
5th Write
Cycle
6th Write
Cycle
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
1
XXXXH
F0H
-
-
-
-
-
-
-
-
-
-
4
D5557H
AAH
CAAABH
55H
D5557H
F0H
RA
RD
-
-
-
-
4
D5557H
AAH
CAAABH
55H
D5557H
A0H
Erase chip
6
D5557H
AAH
CAAABH
55H
D5557H
80H
PA
D5557H
PD
AAH
CAAABH
55H
D5557H
10H
Erase sector
6
D5557H
AAH
CAAABH
55H
D5557H
80H
D5557H
AAH
CAAABH
55H
SA
30H
Read/
Reset
Read/
Reset
Programming
Suspend sector erase
Erasing sectors is suspended by specifying the address = XXXXH, data =B0H.
Resume sector erase
Consecutive
mode
Consecutive
write
Consecutive
mode
Reset
Erasing sectors is resumed after being suspended by specifying the address =XXXXH, data =30H.
3
D5557H
AAH
CAAABH
55H
D5557H
20H
-
-
-
-
-
-
2
XXXXH
A0H
PA
PD
-
-
-
-
-
-
-
-
2
XXXXH
90H
XXXXH
F0H or
00H
-
-
-
-
-
-
-
-
The same instructions are applicable both to the full-word mode and byte mode. The bit data not indicated is arbitrary.
RA: Read address
PA: Write address
SA: Sector address (Specify an address in the sector. Refer to the Table 28.1-1).
RD: Read data
PD: Programming data
● Read/reset instruction
In order to return to the Read mode after exceeding timing limit, issue read/reset instruction sequence.
Read data from FLASH memory during the read cycle. Until another instruction is issued, the FLASH
memory remains in read status.
When power is turned on, the status of the FLASH memory is set to read/reset. In this status, no
instructions are required to read data.
571
CHAPTER 28 FLASH MEMORY
● Programming (Write)
In CPU Programming mode, programs are written in half word length. Writing is performed in four bus
cycles. This instruction sequence has two "unlock" cycles, followed by a writing setup instruction and
data write cycle. At the last write cycle, the writing in the memory starts.
After executing the Auto writing Algorithm instruction sequence, the FLASH memory does not require
any more controls from outside. The FLASH memory internally generates appropriate writing pulses
and verifies the margin of the written cells. The Auto Programming ends when data polling function
finds that the data in bit7 matches to the data written to this bit (refer to the Hardware sequence flag in
section "28.5 Execution Status of Auto Algorithm") and returns to Read mode; and writing addresses
will not be accepted any further. As a result, the FLASH memory requests the next valid address at this
time. This is how data polling indicates that the memory is currently being written.
During the writing, all the instructions written in the FLASH memory are ignored. When the hardware
reset is started during the writing, data in the address being written is indeterminate. Write addresses
may be specified in any order and they may cross sector boundaries. The data "0" cannot be changed
back to "1" by writing. If attempted to write "1" to data "0", data polling algorithm may judge that the
FLASH memory is defected. Or, it might look as if data "1" had been written. However, the data
remains "0" if it is read in the reset/read mode. Only erase operation can change the data from "0" to
"1". Figure 28.4-1 shows the writing procedure using the programming instruction.
Figure 28.4-1 Writing Procedure Using the Programming Instruction
Start writing
Write command sequence
Device data polling
Next address
NO
Last
address?
YES
Write complete
572
CHAPTER 28 FLASH MEMORY
● Erase chip
Erasing chip (erase all sectors) performs in six cycles. Starting with two "unlock" cycles, writing of
setup instruction follows. Then two "unlock" cycles continue until the completion of chip erase
instruction.
There is no need that the user writes in the FLASH memory before erasing the chip. While the Auto
Erase Algorithm is in progress, the FLASH memory automatically performs verification by writing "0"
before erasing all cells (preprogramming). During this process, the FLASH memory does not need
outside control.
Auto Erase is started by the write operation of the instruction sequence and ends when the bit7 becomes
"1". Then, the FLASH memory returns to the read mode. Time required for erasing the chip is "Sector
erasing time × Number of sectors + Chip write time (preprogram)".
Figure 28.4-2 shows the chip erasing procedure using the chip erase instruction.
● Erase sector
Erasing of a sector is performed through six access cycles. The first two cycles are "unlock" cycles, next
comes a write cycle of a setup instruction, another two "unlock" cycles continue, and a sector erase
instruction issued at the sixth cycle starts the sector erasing process. During the 50μs time out period
after the writing of the last erase sector instruction, the next erase sector instruction can be accepted.
Erasing of multiple sectors can be accepted simultaneously by writing the six bus cycles described
above. This sequence is executed by writing the erase sector instruction (30H) in the address of sectors
which should be erased simultaneously. After issuing the last erase sector instruction, there is a 50μs
time out period before starting erasing. In other words, if multiple sectors need to be erased, one erase
sector instruction must be entered within 50μs after the previous instruction. A instruction that is
entered later than that may not be accepted. You can use bit3 to determine whether the subsequent erase
sector instruction is valid (refer to the Hardware sequence flag in section "28.5 Execution Status of
Auto Algorithm").
The issuance of a instruction that is not a sector erase instruction or erase suspend instruction during the
time-out period causes a reset that restores read mode and the preceding instruction sequence to be
ignored. In this case, the erasing is completed by erasing those sectors again. The specifying of address
in the erase sector buffer may be any combination of sectors or numbers (0 to 6). When erasing sectors,
user does not have to write into the FLASH memory before erasing. The FLASH memory writes in all
cells within the sector to be erased automatically (preprogramming). During sector erasing, sectors
other than the one being erased would not be affected in any way. During this process, the FLASH
memory does not require any outside control.
Auto Erase is started after a 50μs time-out period from the last writing of erase sector instruction, and it
ends when the bit7 becomes "1" (refer to the Hardware sequence flag in section "28.5 Execution Status
of Auto Algorithm"). Then, the FLASH memory returns to the Read mode. Other instructions are
ignored. Data polling works in any address within the erased sectors. The time required for erasing
multiple sectors is "Sector erasing time + Sector writing time (preprogramming) × Number of sectors".
Figure 28.4-2 shows the chip erasing procedure using the chip erase instruction.
573
CHAPTER 28 FLASH MEMORY
Figure 28.4-2 Chip Erasing Procedure Using the Chip Erase Instruction
Start erasing
Erase chip/Erase sector
command sequence
Device data polling
or toggle bit complete
Write complete
● Suspend erase
A suspend erase instruction allows the user to suspend the FLASH memory Auto Algorithm while
erasing a sector, to enable that data can be read from or written into a sector that is not being erased.
This instruction is only valid when sector erasing is in progress and it is ignored during erasing or
writing chip. The suspend erase instruction (B0H) is only valid when the sector erasing is in progress
including the time-out period after issuing the erase sector instruction (30H). If this instruction is issued
during the time-out period, the time-out ends immediately and suspends the erasing operation. When
resume erase instruction is issued, the erasing operation resumes. You can specify any address when
issuing the suspend erase instruction or resume erase instruction.
When a suspend erase instruction is issued during erasing sectors, it takes up to 20μs to stop the erase
operation. When the FLASH memory is in Suspend Erase mode, the Ready/Busy and bit7 output "1"
and the bit6 stops toggling. You can check if erasing operation is suspended by checking the bit6 and
bit7 of the address that is being erased. Also, issuing a suspend erase instruction is ignored. When the
erase operation is suspended, the FLASH memory is in Suspend Erase Read mode. Reading data in this
mode is valid for sectors that are not being suspended from erasing. Otherwise, this instruction works
the same as the normal read instruction. While the FLASH memory is in Suspend Erase Read mode, the
bit2 toggles if an attempt is made to read consecutively from the sector being suspended from erasing
(refer to the Hardware sequence flag in section "28.5 Execution Status of Auto Algorithm").
In Suspend Erase Read mode, the user can issue a write instruction sequence to the FLASH memory.
This write mode is Suspend Erase Write mode. Writing in this mode is valid for sectors that are not
being suspended from erasing. Otherwise this instruction works the same as the normal byte write
instruction. In the Suspend Erase Write mode, the bit2 toggles when an attempt is made to read
consecutively from the sector being suspended from erasing. Use the suspend erase bit (bit6) for
detection.
Note: Reading from the bit6 is allowed for any addresses, but reading from bit7 must be performed
against a write address. To resume sector erasing operation, a resume erase instruction (30H)
must to be issued. Issuing resume instruction again at this time would be ignored. On the other
hand, a suspend erase instruction may be issued after the FLASH memory resumes erasing.
574
CHAPTER 28 FLASH MEMORY
28.5
Execution Status of Auto Algorithm
The FLASH memory has hardware to inform its internal status and the completion of
operations toward the outside of the FLASH memory because it uses the Auto
Algorithm for writing/erasing operations. One is a Ready/Busy signal, and the other one
is a hardware sequence flag.
■ Ready/Busy Signal (RDY/BUSYX)
The FLASH memory has a Ready/Busy signal, in addition to a hardware sequence flag, to indicate
whether its internal Auto Algorithm is in progress or completed. This ready/busy signal is connected to
the FLASH memory interface circuit, and can be read as the RDY bit in the FLASH memory status
register. In addition, a rise of this Ready/Busy signal can issue an interrupt request to the CPU (For more
information, see section "28.1 Overview of FLASH Memory").
If the RDY bit is "0", writing or erasing is in progress in the FLASH memory. In this state, neither
writing nor erase instruction would be accepted. If the RDY bit is "1", then the FLASH memory is in
read/write mode or waiting for erase operation.
■ Hardware Sequence Flag
The hardware sequence flag can be obtained as data by reading any address of the FLASH memory
(odd number address in byte access) while the Auto Algorithm is in progress. In the data being read,
there are five valid bits. Each bit indicates Auto Algorithm status. Figure 28.5-1 shows the
configuration of the hardware sequence flag.
Figure 28.5-1 Configuration of the Hardware Sequence Flag
Reading hardware
bit 15
8 7
0
(Indeterminate)
Hardware sequence flag
bit 7
0
Reading byte (odd number address only)
Hardware sequence flag
half word, byte access
bit
7
6
5
4
3
2
1
0
DPOLL
TOGGLE
TLOVER
Indeterminate
SETIMR
TOGGL2
Indeterminate
Indeterminate
In FR-CPU ROM mode, these flags have no effect. In FR-CPU programming mode, always read half
word or byte.
575
CHAPTER 28 FLASH MEMORY
Table 28.5-1 shows the status list of the hardware sequence flags.
Table 28.5-1 Hardware Sequence Flag Status List
Status
In progress
Exceeding
time limit
DPOLL
(bit7)
Auto Programming
Inverted data
Writing/erasing during Auto Erase
0
Read (sector being erased)
1
Suspend
Read (sector not being erased)
Data
erase
Programming (sector not being erased) Inverted data
Auto Programming
Writing/erasing during Auto Erase
Inverted data
0
TOGLLE
(bit6)
TLOVER
(bit5)
SETIMR
(bit3)
TOGGL2
(bit2)
Toggle
Toggle
1
Data
0
0
0
Data
0
1
0
Data
1
Toggle
Toggle
Data
Toggle
0
0
Toggle
Toggle
1
1
0
1
1 *1
1
*2
*1: If the Suspend Erase Programming is in progress, then the bit2 outputs a logic value "1" when an attempt is made to
read the address being programmed.
However, the bit2 toggles if an attempt is made to read consecutively from the sector which is suspended from
erasing.
*2: While bit5 is "1" (Exceeding time limit), the bit2 toggles when read consecutively to the sector while writing/
erasing. Reading to any other sectors is not toggled.
The function of each bit is described as follows:
[bit7] DPOLL: Data polling
• While the Auto Programming is in progress
If an attempt to read is made while the Auto Programming Algorithm is in progress, then the FLASH
memory outputs the inverted data of the last written data in bit7. When reading when the Auto
Programming Algorithm is completed, then the FLASH memory outputs the value of bit7 of the read
data from the specified address by the address signal.
• While the Auto Erase is in progress
When reading while the Auto Erase Algorithm is in progress, then the FLASH memory outputs "0"
regardless of the address specified by the address signal. Similarly, upon completion, it outputs "1".
• While sector erasing is suspended
When reading while sector erasing is suspended, then the FLASH memory outputs "1" when the
address specified by the address signal belongs to the sector being erased. If the address does not
belong to the sector being erased, then the FLASH memory outputs the value of bit7 of the read value
from the address specified by the address signal. By checking this along with toggle bit6 (which is
described later), you can determine the current status if sector erase is being suspended or not, and
which sector is being erased.
Note: When the Auto Algorithm process is near completion, bit7 (data polling) changes
asynchronously while reading. This indicates that the FLASH memory has sent out the operation
status information to the bit7, and is about to send the finalized data. Other bits are not yet
finalized even if the FLASH memory completes the Auto Algorithm, or the bit7 is outputting the
finalized data. The finalized data for other bits are read only by executing consecutive reading.
576
CHAPTER 28 FLASH MEMORY
[bit6] TOGGLE: Toggle bit
• During the Auto writing/erasing
When reading consecutively while the Auto Programming Algorithm or Auto Erase Algorithm is in
progress, then the FLASH memory outputs the result which toggles "1" and "0" into bit6. When either
Auto Programming Algorithm or Auto Erase Algorithm is completed, then the FLASH memory stops
toggling to the consecutive read and outputs a valid data.
Toggle bit is valid after the last write cycle of each instruction sequence.
If programming a sector that is write-protected, this bit toggles for about 2μs and then stops toggling
without changing data. If erasing the sectors when all selected sectors are write-protected, this bit
toggles for about 100μs, then stops toggling without changing data, and returns to the Read mode.
• While sector erasing is suspended
When reading while sector erasing is suspended, then the FLASH memory outputs "1" when the
address specified by the address signal belongs to the sector being erased. If the address does not
belong to the sector being erased, then the FLASH memory outputs bit6 with a read value from the
address specified by the address signal.
[bit5] TLOVER: Exceeding timing limit
While the Auto writing/erasing is in progress
Bit5 indicates that the execution of Auto Algorithm has exceeded the time (internal pulse count)
specified in the FLASH memory. In this state, the bit5 outputs "1". In other words, "1" in this flag while
the Auto Algorithm is in progress indicates that programming or erasing has failed.
Bit5 also indicates failed status if an attempt is made to program in a non-blank area without erasing. In
this case, the bit6 remains toggling and the system cannot read finalized data from the bit7 (data
polling). If time limit is exceeded in this state, the bit5 outputs "1". Note that this means that the
FLASH memory has been used incorrectly; it does not mean that the FLASH memory is defective in
this case. If this happens, execute a reset instruction.
[bit3] SETIMR: Sector erase timer
While sector erasing is in progress
After executing the erase sector instruction sequence the first time, the FLASH memory goes into an
erase sector wait period. Bit3 outputs "0" during this period and outputs "1" if it exceeds the erase sector
wait period. The data polling bit and the toggle bit are valid after executing the erase sector instruction
sequence the first time.
If the data polling function and the toggle bit function indicate that the erase algorithm is in progress
and if this flag is "1", that means that the internally controlled erasing has been started. Subsequent
instructions are ignored until either the data polling bit or the toggle bit indicates completion of erasing
(only a suspend erase code can be accepted). If this flag is "0", then the FLASH memory accepts erase
sector codes subsequently. To be sure, we recommend to check the status of this flag before issuing
erase sector codes subsequently. If the second status check shows "1", the erase sector codes issued
subsequently might not have been accepted. When reading while sector erasing is suspended, then the
FLASH memory outputs "1" when the address specified by the address signal belongs to the sector
being erased. If the address does not belong to the sector being erased, then the FLASH memory
outputs bit3 with a read value from the address specified by the address signal.
577
CHAPTER 28 FLASH MEMORY
[bit2] TOGGL2: Toggle bit2
While sector erasing is in progress
In addition to the bit6 (toggle bit), this toggle bit is used to detect the current status if the FLASH
memory's Auto Erase is in progress, or the erase is being suspended. Bit2 toggles if an attempt is made
to read consecutively from the sector which is being erased during Auto Erase. If the FLASH memory
is in erase-suspend read mode, then the bit2 toggles when an attempt is made to read consecutively from
the sector being suspended from erasing.
If the FLASH memory is in erase-suspend write mode, then the bit2 reads "1" when an attempt is made
to read address consecutively from the sector not being suspended from erasing. Unlike the bit2, the
bit6 toggles only during normal programming or during erasing, or while the erase-suspend writing is in
progress.
For example, bit2 and bit6 are used together to detect a Suspend Erase Read mode (bit2 toggles but bit6
does not toggle). In addition, the bit2 is used to detect sectors. While the FLASH memory is being
erased, the bit2 toggles when reading from the sector being erased.
578
CHAPTER 28 FLASH MEMORY
■ Example of Using the Hardware Sequence Flags
As described in the previous sections, the status of the Auto Algorithm within the FLASH memory can
be determined by using the hardware sequence flags. Figure 28.5-2 and Figure 28.5-3 show the two
examples; one with the use of a data polling function and the other one with the use of a toggle bit
function.
Figure 28.5-2 Flow Chart to Determine the Status of Write/Erase Using a Data Polling Function
Start writing/erasing
VA = Write address
Read (D0 to D7)
Address = VA
D7=Data ?
YES
NO
NO
= sector address that is being
erased by the sector erasing
operation
= sector address that is not
protected during the chip erasing
operation
* : Even if D5 = 1, it is necessary to
re-check the D7 since it is updated
simultaneously with the D5.
D5=1 ?
YES
Read (D0 to D7)
Address = VA
D7=Data ?
*
YES
NO
Writing/erasing
Failure
Writing/erasing
Pass
579
CHAPTER 28 FLASH MEMORY
Figure 28.5-3 Flow Chart to Determine the Status of Write/Erase Using a Toggle Bit Function
Start writing/erasing
Read (D0 to D7)
Address = "H" or "L"
D6 = toggle?
NO
YES
NO
D5=1 ?
YES
Read (D0 to D7)
Address = "H" or "L"
D6* = toggle?
NO
YES
Writing/erasing
Failure
Writing/erasing
Pass
*: When D5 changes to "1", D6 stops toggling immediately. Therefore, D6 needs to
be re-checked even if D5 is "1".
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CHAPTER 28 FLASH MEMORY
28.6
Details on Writing/Erasing FLASH Memory
This section describes procedures on how to issue instructions to activate the Auto
Algorithm in order to run the following operations; reading/resetting FLASH memory,
programming, erasing chip, erasing sectors, suspending sector erase, and resuming
sector erase.
■ Details on Writing/Erasing FLASH Memory
Auto Algorithm in the FLASH memory can be executed by the instruction sequences (see Instruction
list of Table 28.4-1) using bus writing cycles for reading/resetting, programming, erasing chip, erasing
sectors, suspending sector erase, and resuming sector erase. Each bus write cycle must be sent
consecutively. Completion of the Auto Algorithm can be determined by data polling function. When it
is completed successfully, it is return to the read/reset status.
The next section describes the following operations in the listed order:
1. Setting read/reset status
2. Programming data
3. Erasing all data (erase entire chip)
4. Erasing any data (sector erase)
5. Suspending sector erase
6. Resuming sector erase
■ Setting the Read/Reset Status to the FLASH Memory
To set the FLASH memory to read/reset status, send the read/reset instruction to the target sectors in the
FLASH memory consecutively. For more information on the instruction, see the instruction sequence
table (Instruction list of Table 28.4-1).
There are two types of instruction sequences for read/reset instruction, performing the bus cycle either
once or three times, but there are no significant differences between them.
Read/reset is the initial status of the FLASH memory. When power is turned on and when instructions
complete successfully, the status is always set to read/reset. During read/reset status, the FLASH
memory waits for other instructions.
During this status, a normal read access can be used to read data. Programming access from the CPU is
allowed just like mask ROMs. To read data, a normal read access does not require this instruction. This
instruction is mainly used when the instruction is not completed successfully for some reason or when
Auto Algorithm requires resetting.
■ Programming Data in FLASH Memory
To start the Auto Programming Algorithm with data, send the programming instruction to the target
sectors in the FLASH memory consecutively. For more information on the instruction, see the
instruction sequence table (Instruction list of Table 28.4-1). The Auto Algorithm is started and starts
auto programming when the fourth cycle of data programming in the target address is completed.
581
CHAPTER 28 FLASH MEMORY
● Specifying address
Addresses specified during the programming data cycle must be even numbers. If an odd number is
specified, programming cannot be performed correctly. Therefore, the programming has to specify
addresses with even numbers and data must be in full-word length.
Programming may be specified in any order and they may be from different sector boundaries, but only
one word can be programmed with a single programming instruction.
● Warning on programming data
The data "0" cannot be changed to "1" by programming. If attempted to program "1" to data "0", data
polling algorithm (DQ7) or toggle function (DQ6) would not be completed. This will result in one of
two errors. It might be determined as a bad FLASH memory device, exceeding the programming timing
limit, and would result in error indicated in the exceeding timing limit flag (DQ6). Otherwise, it might
look as if data "1" had been programmed. However, the data remains as "0" if it is read at the read/reset
status. Only erase operation can change the data from "0" to "1".
While the Auto Programming is in progress, all other instructions are ignored. Note that when the
hardware reset is started while programming is in progress, data being programmed to the address is not
write-protected.
● FLASH Memory Programming Procedure
Figure 28.6-1 shows the example of the FLASH memory programming procedure. The status of Auto
Algorithm in FLASH memory can be determined by using the hardware sequence flag (see section
"28.5 Execution Status of Auto Algorithm"). In this section, the data polling flag (DQ7) is used to
check the completion of programming.
The data read for flag check is read from the last programming address.
Since the data polling flag (DQ7) is updated simultaneously with the exceeding timing limit flag (DQ5),
it is necessary to re-check the data polling flag (DQ7) even if the exceeding timing limit flag (DQ5) is
"1".
Furthermore, it is necessary to re-check the toggle bit flag (DQ6) since it stops when the exceeding
timing limit flag (DQ5) changes to "1".
582
CHAPTER 28 FLASH MEMORY
Figure 28.6-1 Example of the FLASH Memory Programming Procedure
Start writing
FLCR:WE(bit1)
Enable writing on FLASH
memory
Write command sequence
(1)D5557H←AAH
(2)CAAABH←55H
(3)D5557H←A0H
(4)Write address ← Write data
Internal address read
Data polling
(DQ7)
Next address
Data
Data
0
Timing limit
(DQ5)
1
Internal address read
Data
Data polling
(DQ7)
Data
Write error
Last address
FLCR:WE(bit1)
Disable writing on
FLASH memory
Checking hardware sequence flags
Write Complete
■ Erasing Data from the FLASH Memory (Erase Chip)
To erase all data from the FLASH memory, send the chip erase instruction to the target sectors in the
FLASH memory consecutively. For more information on the instruction, see the instruction sequence
table ("28.4 Auto Algorithm Activation Method").
Chip erase instruction takes place in six bus operations. When the sixth cycle is completed, the chip
erasing process starts. When erasing chip, the user does not have to program the FLASH memory
before erasing. While the Auto Erase Algorithm is in progress, the FLASH memory automatically
writes "0" before erasing all cells to verify the operation.
583
CHAPTER 28 FLASH MEMORY
■ Erasing Data from FLASH Memory (Erase Sector)
To erase sectors, from the FLASH memory, send the erase sector instruction to the target sectors in the
FLASH memory consecutively. For more information on the instruction, see the instruction sequence
table ("28.5 Execution Status of Auto Algorithm").
● Specifying sectors
The erase sector instruction takes place in six bus cycles. The 50μs erase sector wait period starts when
an erase sector code (30H) is written to any accessible address (even number address) within the target
sector at the sixth cycle. If erasing multiple sectors, write subsequent erase code (30H) to an address in
another target sector.
● Warning on specifying multiple sectors
After the write of the last erase sector code, there is a 50μs sector erase wait period before a sector erase
starts. In other words, if erasing multiple sectors simultaneously, then each erase code (sixth cycle of
the instruction sequence) and the sector address has to be specified within 50μs. Otherwise, the next
instruction may not be accepted. The sector erase timer can be used (hardware sequence flag DQ3) to
check whether all consecutive erase sector codes are valid. In this case, the address to be read for the
sector erase timer should specify the sector to be erased.
● FLASH Memory Sector Erasing Procedure
The status of Auto Algorithm inside the FLASH memory can be determined by using the hardware
sequence flag (see section "28.5 Execution Status of Auto Algorithm"). Figure 28.6-2 shows an
example of the FLASH memory sector erasing procedure. In this section, the toggle bit flag (DQ6) is
used to check completion of the erasing.
Note that the data to be read for the flag check is in the sector to be erased.
Since the toggle bit flag (DQ6) stops toggling when the exceeding timing limit flag (DQ5) changes to
"1", it is necessary to re-check the toggle bit flag (DQ6) even if the exceeding timing limit flag (DQ5) is
"1".
Furthermore, it is necessary to re-check the data polling flag (DQ7) since it is updated simultaneously
with the exceeding timing limit flag (DQ5).
584
CHAPTER 28 FLASH MEMORY
Figure 28.6-2 Example of the FLASH Memory Sector Erasing Procedure
Start erasing
FLCR:WE(bit1)
Enable erasing flash memory
Erase command sequence
(1)D5557H ←AAH
(2)CAAABH←55H
(3)D5557H ←80H
(4)D5557H ←AAH
(5)CAAABH←55H
1
Sector ease timer (DQ3)
0
(6) Input code into erasing
sector (30H)
Internal address read
YES
Any other sectors
to erase?
NO
Internal address read 1
Internal address read 2
Toggle bit (DQ6)
Data 1 (DQ6) = Data 2 (DQ6)
Next sector
YES
NO
0
Timing limit (DQ5)
1
Internal address read 1
Internal address read 2
NO
Toggle bit (DQ6)
Data 1 (DQ6) = Data 2 (DQ6)
YES
Erase error
Last sector
NO
YES
FLCR:WE(bit1)
Disable erasing flash memory
Erase Complete
Checking hardware
sequence flags
585
CHAPTER 28 FLASH MEMORY
■ Suspending Sector Erase of the FLASH Memory
To suspend sector erasing, send the sector erase suspend instruction to the FLASH memory consecutively.
For more information on the instruction, see the instruction sequence table ("28.4 Auto Algorithm
Activation Method").
The suspend sector erase instruction suspends the erasing operation while erasing sectors, in order to
enable reading from the sectors which are not being erased. In this case, it only enables reading but not
writing. This instruction is only valid while sector erasing, including its wait period, is in progress. It is
ignored during programming or erasing chip.
It starts suspending when a suspend erase code (B0H) is written. In this case, specify any address in the
FLASH memory. Another suspend erase instruction is ignored while erasing is suspended.
If a suspend sector erase instruction is issued during the wait period, then the erase sector wait ends
immediately and it suspends the erasing operation. This is the Suspend Erase mode. If a suspend erase
instruction is issued during sector erasing operation after the erase sector wait period, then it takes up to
20μs before its status changes to a Suspend Erase mode. A suspend erase instruction must be executed
20μs or more after a sector erase instruction or a resume sector erase instruction is issued.
■ Resuming Sector Erase in the FLASH Memory
To resume the sector erasing, send the sector erase resume instruction to the FLASH memory
consecutively. For more information on the instruction, see the instruction sequence table ("28.4 Auto
Algorithm Activation Method").
Resume sector erase instruction is used to resume the sector erasing operation while it is in the Suspend
Sector Erase status. It is started when a resume erase code (30H) is written. In this case, specify any
address in the FLASH memory.
The resume sector erase instruction is ignored while erasing sectors.
586
CHAPTER 28 FLASH MEMORY
28.6.1
Notes on Using the FLASH Memory
This section describes some notes on using the FLASH memory, MB91F248/MB91F249.
■ Notes on Using the FLASH Memory
● Inputting Reset (INITX)
While no Auto Algorithm is running, allow 500ns or more for the "L" level width to input a reset during
reading. In this case, it requires at least 500ns after starting the reset before the data reading starts.
Similarly, while the Auto Algorithm is running, allow 500ns or more for the "L" level width to input a
reset during writing/erasing. In this case, it requires 20μs before the data reading starts after stopping
the current operation to initiate FLASH memory.
Inputting a reset during write operation makes the data that is currently being written undefined. The
sector that is being erased may become unusable if a hardware reset occurs or the power is turned off
during erase operation.
● Canceling a software reset, a watchdog timer reset
While the Auto Algorithm is active, the CPU might run away if the reset condition occurs during the
writing/erasing of the FLASH memory through a CPU access. Such a reset condition may cause the
Auto Algorithm to continue running without initiating the FLASH memory unit. This could result in the
FLASH memory remaining in Read status when the CPU starts a sequence after the reset. Such a reset
condition should be disabled during the writing/erasing of the FLASH memory.
● Programming access of the FLASH memory
While the Auto Algorithm is running, a read access to the FLASH memory is disabled. If the CPU's
memory access mode is set to the built-in ROM mode, the programming area has to be changed to
another area such as RAM before the start of writing/erasing. In this case, if the sector (SA6) which
includes the interrupt vector is erased, programming/interrupting erase process cannot be executed.
For the same reason, all other interrupting sources except the FLASH memory are disabled while the
Auto Algorithm is running.
● Hold function
When the CPU receives a Hold request, the programming signal, WE, of the FLASH memory unit may
be distorted and allows invalid writing/erasing from an invalid programming operation. Ensure that the
WE bit in the control status register (FLCR) is always "0" when the Hold request is accepted.
● Applying VID
The application of VID, which is required for the sector protection operation, must start and stop while
the power is still ON.
587
CHAPTER 28 FLASH MEMORY
28.7
Sector Protecting Operations
This FLASH memory has a sector protection function which protects sectors (sector by
sector) from the invalid writing/erasing. Once the protection is set to a sector, that
sector is protected forever unless the device is destroyed. However, this protection may
be released temporarily for writing/erasing. Such operations would be processed
through the sector protecting operations.
The sector protecting operations do not have any Auto Algorithm such as writing/
erasing. These operations are executable during the FLASH Memory mode only; it is not
executable during the Normal mode.
Therefore, these operations should be controlled with the external pins using a FLASH
memory writer.
■ List of the Sector Protecting Operations
There are three types of sector protecting operations:
• Enable Sector protection
• Verify Sector protection
• Cancel Sector Protection Temporarily
Table 28.7-1 shows each pin setting.
Table 28.7-1 Pin Setting
Operation
CEX
OEX
WEX
A1
A2
A7
A17 to A13 D0 to D15 RSTX
MD2
MD1
MD0
Enable
Sector Protection
"L"
"H"
"L"
"L"
"H"
"L"
Sector
Address
-
"H"
VID
"H"
VID
Verify
Sector Protection
"L"
"L"
"H"
"L"
"H"
"L"
Sector
Address
Code
Output *
"H"
"H"
"H"
VID
Cancel Sector
Protection
Temporarily
-
-
-
-
-
-
-
-
"H"
"H"
VID
"H"
*: Outputs 01H while a sector is protected and 00H while a sector is not protected.
588
CHAPTER 28 FLASH MEMORY
■ Enable Sector Protection
The Enable Sector Protection operation allows programming to the protection circuit in the FLASH
memory.
This operation can disable writing/erasing of any combination of ten sectors. No sectors are protected
when the MB91F248/MB91F249 is shipped. In this operation, the sector addresses (B91F248: A17,
A16, A15, A14, A13, MB91F249: A18, A17, A16, A15, A14, A13) of the sectors to be protected must
be set to the address signals first. See Table 28.1-1 for the information on the sectors and the sector
addresses.
For the programming of the protective circuit, first apply VID (=12V) to the MD2 and the MD0. Then,
set CEX=0, start with a rise of the WEX pulse and end with a fall. The sector addresses must to be
unchanged throughout the WEX pulse. Once it is set, the sector protection cannot be canceled. No
further writing/erasing is allowed in the protected sectors.
■ Verifying Sector Protection
The Verify Sector Protection operation verifies (checks) the programming in the protective circuit of the
FLASH memory. This operation first sets the CEX and OEX to "0". Then, while WEX is "1", apply
VID to MD0 (margin mode). If (A7, A2, A1)=(0, 1, 0), then the DQ0 outputs "1" at the sectors that are
protected when it reads by specifying the address signal to a sector address. At the sectors that are not
protected, "00H" is read. Figure 28.7-1 shows the sector protecting algorithm using the Enable Sector
Protection and Verify Sector Protection.
589
CHAPTER 28 FLASH MEMORY
Figure 28.7-1 Sector Protecting Algorithm Using the Enable Sector Protection and
Verify Sector Protection
Start
Setup sector addresses
A17 to A13
PLSCNT=1
MD2=MD0=VID, MD1="H"
A1=CEX=WEX="L"
OEX=RSTX="H"
Apply WEX pulse
WEX=MD2="H"
CEX=OEX="L"
(Keep MD0 as VID)
Read sector address SA
(address = SA, A1="L",
A2="H", A7="L")
NO
NO
Data = 01H?
YES
PLSCNT=50 ?
YES
Cancel VID from MD0;
write of reset command
Any other sectors
NO
Cancel VID from MD0;
write of reset command
Fail
Sector protection
complete
590
YES
CHAPTER 28 FLASH MEMORY
■ Cancel Sector Protection Temporarily
Enabling sector protection sets a permanent protection, the sectors will be protected from writing/
erasing forever unless the device is destroyed. However, the Cancel Sector Protection Temporarily
operation can cancel a previously set protection temporarily. This operation is set by keeping applying
the VID to MD1. During this operation, the previously set sector protection information is ignored and
the writing/erasing of all sectors is allowed. When you reset the MD1 to "1" (=3.3V), this operation is
canceled and previously set protected sectors are protected again. Figure 28.7-2 shows the algorithm for
the Cancel Sector Protection Temporarily.
Figure 28.7-2 Cancel Sector Protection Temporarily Algorithm
Start
MD1=VID
*1
Executed erase/write operation
MD1="H"
Canceling sector
protection complete
*2
*1: Protection will be canceled with all protected sectors.
*2: Previously set protected sectors are protected again.
591
CHAPTER 28 FLASH MEMORY
592
CHAPTER 29
EXAMPLE OF SERIAL
WRITING CONNECTION
This chapter describes the basic serial writing structure,
pins used for serial on-board writing, example
connection for serial writing, and the system
configuration of the Flash microcontroller programmer.
29.1 Example of Serial Writing Connection in the MB91F24x/S
29.2 Example of MB91F24x/S Serial Writing (Asynchronous)
Connection
593
CHAPTER 29 EXAMPLE OF SERIAL WRITING CONNECTION
29.1
Example of Serial Writing Connection in the MB91F24x/S
In MB91F24x/S, the serial on-board writing of Flash ROM (Fujitsu standard) is
supported. This specification is explained as follows:
■ Basic Configuration for Serial Programming in the MB91F24x/S
For Fujitsu standard serial on-board writing, the AF200 Flash microcontroller programmer by
Yokogawa Digital Computer Corporation is used.
Figure 29.1-1 Basic Configuration for Serial Programming in the MB91F24x/S
Host interface cable (AZ201)
General-purpose common cable (AZ210)
RS232C
AF200
Flash
microcontroller
programmer
+
Memory card
CLK sync serial
MB91F24x/S
User system
Operable independently
Note:
Contact Yokogawa Digital Computer Corporation for more information about the function and
operation methods of AF200 Flash microcontroller programmer and the general-purpose common
cables (AZ210) and connectors for the connection.
594
CHAPTER 29 EXAMPLE OF SERIAL WRITING CONNECTION
■ Pins for Fujitsu Standard Serial On-board Writing
Table 29.1-1 Function of Terminal used for Fujitsu Standard Serial On-board Writing
Pin
Function
Supplementary Explanation
Mode pins
The Flash microcontroller programmer changes the pin mode to the write mode.
Flash serial write mode: MD2, MD1, MD0=1, 0, 0
Reference: Single-chip mode: MD2, MD1, MD0=0, 0, 0
X0, X1
Oscillation pins
In write mode, the internal CPU operation clock is one time of the PLL clock.
Therefore, the oscillation clock frequency is used for the internal operation
clock, therefore the oscillator frequency used for serial rewriting is 1 MHz to 16
MHz.
P10, P11
Writing program start pins
Set P10 to the "L" level and P11 to the "H" level.
INITX
Reset pin
SIN0
Serial data input pin
SOT0
Serial data output pin
SCK0
Serial clock input pin
VCC
Power voltage supply pin
When the user system supplies the writing voltage, the connection with the
Flash microcontroller is unnecessary.
During connection, do not cause short-circuit with the user-side power supply.
VSS
GND pin
It is common to Flash microcontroller programmer's GND.
MD2, MD1,
MD0
----
Use UART in the CLK synchronous mode.
Note:
If P10, P11, SIN0, SOT0, and SCK0 pins are also used by the user system, the control circuit in the
figure below is necessary.
(During the serial writing, the user circuit can be cut off by the Flash microcontroller programmer's
/TICS signal. See the connection example).
AF200
Write control pin
MB91F24x/S
Write control pin
10kΩ
AF200
/TICS pin
User circuit
595
CHAPTER 29 EXAMPLE OF SERIAL WRITING CONNECTION
■ Example of Serial Writing Connection (When User Power Supply is Used)
The following gives an example of serial writing connection when the user power supply is used.
MD2=1 and MD0=0 are input to mode pins MD2 and MD0 from the Flash microcontroller programmer
(AF200)'s TAUX3 and TMODE (Serial rewriting mode: MD2, MD1, MD0=100B).
Figure 29.1-2 Example of Serial Writing Connection in the MB91F24x/S Internal Vector Mode
(When User Power Supply is Used)
AF200
Flash microcontroller
programmer
TAUX3
User's system
Connector
DX10 -28S
(19)
MB91F24x/S
MD2
MD1
TMODE
MD0
(12)
X0
4MHz
X1
TAUX
(23)
P10
10kΩ
/TICS
(10)
User
circuit
/TRES
(5)
INITX
P11
User circuit
TTXD
(13)
SIN
TRXD
(27)
SOT0
TCK
(6)
SCK0
TVcc
GND
(2)
(7,8,
14,15,
21,22,
1,28)
Pins 3, 4, 9, 11, 16,
17, 18, 20, 24, 25, 26
are OPEN
User power
supply
Pin 14
596
VSS
Pin 1
DX10-28S
Pin 28
DX10-28S: Right angle type
VCC
Pin 15
Pin assignment of the connector
(manufactured by Hirose Electric)
CHAPTER 29 EXAMPLE OF SERIAL WRITING CONNECTION
Notes:
• If P10, P11, SIN0, SOT0, and SCK0 pins are also used by the user system, the control circuit in
the figure below is necessary.
(During the serial writing, the user circuit can be disconnected by the Flash microcontroller
programmer's /TICS signal).
AF200
Write control pin
10k
AF200
/TICS pin
MB91F24x/S
Write control pin
User circuit
• Ensure the user power supply is OFF when connecting AF200.
597
CHAPTER 29 EXAMPLE OF SERIAL WRITING CONNECTION
■ Example of Serial Writing Connection
(When Power is Supplied from the Flash Microcontroller Programmer)
The following gives an example of serial writing connection when power is supplied from the Flash
microcontroller programmer (AF200).
MD2=1 and MD0=0 are input to mode pins MD2 and MD0 from the Flash microcontroller programmer
(AF200)'s TAUX3 and TMODE (Serial rewriting mode: MD2, MD1, MD0=100B).
Figure 29.1-3 Example of Serial Writing Connection in the MB91F24x/S Internal Vector Mode
(When Power is Supplied from Writer)
User's system
AF200
Flash microcontroller
Connector
programmer
DX10-28S
MB91F24x/S
MD2
MD1
(19)
TAUX3
10k
TMODE
(12)
MD0
10kΩ
X0
4M Hz
X1
TAUX
(23)
/TICS
(10)
/TRES
(5)
P10
10k
User
circuit
10k
INITX
10k
P11
User circuit
TTXD
(13)
SIN0
TRXD
(27)
SOT0
TCK
(6)
SCK0
(3)
Vcc
GND
(7,8,
14,15,
21,22,
1,28)
User power
supply
Pin 14
Power supply
regulator AZ264
Pins
2,4,9,11,16,17,18,
20, 24, 25, 26
are OPEN
DX10-28S: Right angle type
598
VCC
VSS
Pin 1
DX10-28S
Pin 28
Pin 15
Pin assignment of the connector
(manufactured by Hirose Electric)
CHAPTER 29 EXAMPLE OF SERIAL WRITING CONNECTION
Notes:
• If P10, P11, SIN0, SOT0, and SCK0 pins are used by the user system, the control circuit in the
figure below is necessary.
(During the serial writing, the user circuit can be cut off by the Flash microcontroller programmer's
/TICS signal).
AF200
Write control pin
MB91F24x/S
Write control pin
10k
AF200
/TICS pin
User circuit
• Ensure the user power supply is OFF when connecting AF200.
• Do not make a short-circuit with the user power supply when the writing power supply is supplied
from AF200.
599
CHAPTER 29 EXAMPLE OF SERIAL WRITING CONNECTION
■ Example of Minimum Connection with Flash Microcontroller Programmer
(When User Power Supply is Used)
The following gives an example of the minimum connection with the Flash microcontroller
programmer (AF200) when the user power supply is used. If each pin is set as shown below during
Flash memory writing, MD2, MD1, MD0, P10, or P11 need not be connected with the Flash
microcontroller programmer.
(Serial rewriting mode: MD2, MD1, MD0=100B)
Figure 29.1-4 When the User Power Supply is Used
AF200
Flash microcontroller
programmer
User's system
MB91F24x/S
For serial rewrite 1
MD2
For serial rewrite 0
MD1
10
MD0
For serial rewrite 0
X0
4MHz
X1
For serial rewrite 0
User circuit
P10
P11
For serial rewrite 1
User circuit
/TRES
Connector
DX10-28S
(5)
INITX
TTXD
(13)
SIN0
TRXD
(27)
SOT0
(6)
SCK0
(2)
VCC
TCK
TVcc
GND
(7,8,
14,15,
User power supply
VSS
21,22,
1,28)
Pin 14
Pins 3, 4, 9, 10, 11, 12,
16, 17, 18, 19, 20, 23,
24, 25, 26 are OPEN
DX10-28S: Right angle type
600
Pin 1
DX 10-28S
Pin 28
Pin 15
Pin assignment of the connector
(manufactured by Hirose Electric)
CHAPTER 29 EXAMPLE OF SERIAL WRITING CONNECTION
Notes:
• If the SIN0, SOT0, and SCK0 pins are also used by the user system, the control circuit in the
figure below is necessary.
(During the serial writing, the user circuit can be cut off by the Flash microcontroller
programmer's/TICS signal).
AF200
Write control pin
MB91F24x/S
Write control pin
k
AF200
/TICS Pin
User circuit
• Ensure the user power supply is OFF when connecting AF200.
601
CHAPTER 29 EXAMPLE OF SERIAL WRITING CONNECTION
■ Example of Minimum Connection with Flash Microcontroller Programmer
(When Power is Supplied from Writer)
The following gives an example of minimum connection with the Flash microcontroller programmer
(AF200) when power is supplied from AF200.
If each pin is set as shown below during Flash memory writing, MD2, MD1, MD0, P10, or P11 need
not be connected to the Flash microcontroller programmer.
(Serial rewriting mode: MD2, MD1, MD0=100B)
Figure 29.1-5 When Power is Supplied from the Flash Microcontroller Programmer
AF200
Flash microcontroller
programmer
User's system
MB91F24x/S
For serial rewrite 1
MD2
For serial
rewrite 0
MD1
MD0
For serial rewrite 0
X0
4MHz
X1
P10
For serial
rewrite 0
User circuit
P11
For serial rewrite 1
User circuit
Connector
DX10-28S
/TRES
TTXD
TRXD
TCK
Vcc
GND
Power supply
regulator AZ264
(5)
(13)
(27)
(6)
INITX
SIN0
SOT0
SCK0
(3)
(7,8,
14,15,
21,22,
1,28)
VCC
User power
supply
Pin 14
Pins 2, 4, 9, 10,
11, 12, 16, 17, 18,
19, 20, 23, 24, 25,
26 are OPEN
VSS
Pin 1
DX10-28S
Pin 28
Pin 15
DX10-28S: Pin assignment of the right angle type connector (manufactured by Hirose Electric)
602
CHAPTER 29 EXAMPLE OF SERIAL WRITING CONNECTION
Notes:
• If SIN0, SOT0, and SCK0 pins are used by the user system, the control circuit in the figure below
is necessary.
(During the serial writing, the user circuit can be cut off by the Flash microcontroller programmer's
/TICS signal).
AF200
Write control pin
MB91F24x/S
Write control pin
AF200
/TICS pin
User circuit
• Ensure the user power supply is OFF when connecting AF200.
• Do not cause short-circuit with the user power supply when the writing power is supplied from
AF200.
603
CHAPTER 29 EXAMPLE OF SERIAL WRITING CONNECTION
■ Configuration of the AF200 Flash Microcontroller Programmer System
(Manufactured by Yokogawa Digital Computer Corporation)
The table below shows the configuration of the AF220/AF210/AF120/AF110 Flash microcontroller
programmer system (manufactured by Yokogawa Digital Computer Corporation).
Mainframe
Product
Function
AF220
/AC4P
Ethernet interface product
/100 V to220 V power adapter
AF210
/AC4P
Standard product
/100 V to 220 V power adapter
AF120
/AC4P
Single-key Ethernet interface product
/100 V to 220 V power adapter
AF110
/AC4P
Single-key product
/100 V to 220 V power adapter
AZ221
PC-AT RS232C cable dedicated to the writer
AZ210
Standard target probe (a) length: 1m
FF003
Fujitsu FR Flash microcontroller control module
AZ290
Remote controller
/P2
2 Mbytes PC card (option) for Flash memory sizes of up to 128 Kbytes
/P4
4 Mbytes PC card (option) for Flash memory sizes of up to 512 Kbytes
Contact: Yokogawa Digital Computer Corporation
Telephone number: +81-42-333-6224
■ Original Oscillation Clock Frequency
At Flash memory writing, the usable original oscillation clock frequency is 4.0 MHz.
■ Other Warnings
During Flash memory writing by the serial writer, the ports are in the same status as the reset status,
excluding the pins used in writing.
604
CHAPTER 29 EXAMPLE OF SERIAL WRITING CONNECTION
29.2
Example of MB91F24x/S Serial Writing (Asynchronous)
Connection
This section shows an example connection for serial writing (asynchronous) in the
MB91F24x/S.
■ Basic Structure of Serial Writing (Asynchronous) in the MB91F24x/S
Figure 29.2-1 Basic Structure of Serial Writing (Asynchronous)
User system
RS232C driver
RS232C
Communication by UART
MB91F24x/S
The Flash memory of the Flash built-in microcontroller installed in the user system can be rewritten
from the personal computer through RS232C. However, this requires that the user system should
contain the RS232C driver that enables communication with microcontroller's UART.
605
CHAPTER 29 EXAMPLE OF SERIAL WRITING CONNECTION
■ Example of On-board Rewriting by Programmer
User system
MB91F24x/S
For serial rewrite 1
1
MD2
0
For serial rewrite 0
1
MD1
0
1
MD0
For serial rewrite 0
0
1
P10
0
For serial rewrite 0
1
User circuit
0
For serial rewrite 0
P11
User circuit
X0
4 MHz
X1
RS232C
driver
INITX
SIN
SOT
Communication by UART
RS232C
Set the MD2, MD1, and MD0 pins and the P10 and P11 pins on the user system because they cannot be
controlled from the PC side. Moreover, during the serial rewriting, it turns to the serial rewriting mode
by changing INITX from "L" to "H" after the MD2, MD1, and MD0 pins and the P10 and 11 pins are
set. So, serial rewriting is possible from the PC.
After the serial rewriting is complete, the user program is executed by setting the MD2, MD1, and MD0
pins to the usual mode, switching the P10 and P11 pins to the user circuit side, and changing INITX
from "L" to "H".
Note:
To perform mass writing using the serial programmer manufactured by Yokogawa Digital Computer
Corporation in the future, it is recommended to set the serial clock pin pattern on the PC board while
referring to serial writing connection examples written in the hardware manual of each product class.
606
CHAPTER 29 EXAMPLE OF SERIAL WRITING CONNECTION
■ Pins Used by This Programmer for On-board Rewriting
Table 29.2-1 Setting for MB91F24x/S
Pin
Function
Supplementary Explanation
MD2, MD1,
MD0
Mode pins
Control these pins at Flash rewriting.
Set MD2 to "H" and MD1 and MD0 to "L" to change to the Flash rewriting
mode.
P10, P11
Writing program start pins
In the Flash rewriting mode, set P10 and P11 to "L".
INITX
Reset pin
Set MD2, MD1, and MD0 pins and P10 and P11 pins to the Flash rewriting
mode and then cancel the reset.
SIN0
Serial data input pin
Use UART.
SOT0
Serial data output pin
Use UART.
X0, X1
Oscillation pins
In write mode, the internal CPU operation clock is the PLL clock whose
frequency is multiplied. Therefore, the oscillation clock frequency is used
for the internal operation clock, and so the oscillator frequency used for
serial rewriting is 1MHz to 16MHz.
VCC
Power supply voltage
−
VSS
GND pin
−
607
CHAPTER 29 EXAMPLE OF SERIAL WRITING CONNECTION
■ Timing Chart of Each Pin
Using the INITX pin input as the standard, perform input to each pin of the microcontroller based on
the following timings.
The minimum values P10 and P11, which are the setup and hold times of each signal for the INITX
rising edge, indicate the writing program start pins, and SIN0 indicates the serial data input pin.
"H"
INITX
5tcp
"L"
MD0
"H"
tcp
"L"
MD1
"H"
tcp
"L"
MD2
"H"
tcp
"L"
"H"
P10,P11
tcp
tcp × 250
"L"
SIN0
"H"
Data
"L"
608
tcp × 3500 (Min)
APPENDIX
This appendix includes I/O maps, vector tables, status of
each pin, notes when little endian area is used,
instruction lists, and precautions on handling.
APPENDIX A I/O Map
APPENDIX B Vector Table
APPENDIX C Status of Each Pin due to Reset
APPENDIX D Notes when Little Endian Area is Used
APPENDIX E Instruction Lists
APPENDIX F Notes on Handling
609
APPENDIX
APPENDIX A I/O Map
The following I/O map shows the relationship between memory space addresses and
registers for peripheral resources.
■ I/O Map
[Legend of I/O map]
address
00000H
+0
PDR0 [R/W] B
XXXXXXXX
register
+1
+2
PDR1 [R/W]B
PDR2 [R/W]B
XXXXXXXX
XXXXXXXX
+3
PDR3 [R/W]B
XXXXXXXX
block
T-unit
Port Data Register
Read/write attribute and access unit
(B:Byte,H:Half Word,W:Word)
Initial register value after reset
Register name
(the register on the first column is at address 4n,
the register in the second column is at address 4n+2, ...)
Leftmost register address
(the first column register represents the MSB side of
the data in word access mode)
Note:
Register bit values indicate initial values as shown below:
"1": Initial value "1"
"0": Initial value "0"
"X": Initial value "X"
"-": No physical register exists at that location.
The access by the data access attribute not described is disable.
610
APPENDIX A I/O Map
Table A-1 I/O Map (1 / 13)
Register
Address
Block
+0
+1
+2
+3
00000000H
PDR0 [R/W] B, H
XXXXXXXX
PDR1 [R/W] B, H
XXXXXXXX
PDR2 [R/W] B, H
00000000
PDR3 [R/W] B, H
XXXX0000
00000004H
PDR4 [R/W] B, H
XXXXXXXX
PDR5 [R/W] B, H
XXXXXXXX
PDR6 [R/W] B, H
XXXXXXXX
PDR7 [R/W] B, H
----XXXX
00000008H
PDR8 [R/W] B, H
XXXXXXXX
PDR9 [R/W] B, H
XXXXXXXX
PDRA [R/W] B, H
----XXXX
PDRB [R/W] B, H
XXXXXXXX
0000000CH
PDRC [R/W] B, H
----XXXX
PDRD [R/W] B, H
0000XXXX
PDRE [R/W] B, H
XXXXXXXX
PDRF [R/W] B, H
XXXXXXXX
00000010H
PDRG [R/W] B, H
----XXXX
-
-
-
00000014H
to
0000003CH
-
Port Data Register
Reserved
00000040H
EIRR0 [R/W] B, H, W
00000000
ENIR0 [R/W] B, H, W
00000000
ELVR0 [R/W] B, H, W
00000000 00000000
Ext.int
(INT0 to INT7)
00000044H
DICR [R/W] B, H, W
-------0
HRCL [R/W] B
0--11111
-
DLY/I-unit
00000048H
0000004CH
TMRLR0 [W] H, W
XXXXXXXX XXXXXXXX
-
TMR0 [R] H, W
XXXXXXXX XXXXXXXX
TMCSR0 [R/W] B, H, W
----0000 00000000
Reserved
TMRLR1 [W] H, W
XXXXXXXX XXXXXXXX
TMR1 [R] H, W
XXXXXXXX XXXXXXXX
00000054H
-
TMCSR1 [R/W] B, H, W
----0000 00000000
00000058H
TMRLR2 [W] H, W
XXXXXXXX XXXXXXXX
TMR2 [R] H, W
XXXXXXXX XXXXXXXX
-
TMCSR2 [R/W] B, H, W
----0000 00000000
00000050H
0000005CH
00000060H
00000064H
SSR [R/W, R] B, H, W
00001000
SIDR [R]/SODR [W]
B, H, W
XXXXXXXX
SCR [R/W, W] B, H, W SMR [R/W, W] B, H, W
00000100
00--0-0-
UTIM [R] H (UTIMR [W] H)
00000000 00000000
00000068H
to
0000008CH
DRCL [W] B
--------
UTIMC [R/W] B
0--00001
-
00000090H
-
SGDBL [R/W] B
-------0
00000094H
SGAR [R/W] B, H, W
00000000
SGFR [R/W] B, H, W
XXXXXXXX
Reload Timer 0
Reload Timer 1
Reload Timer 2
UART0
U-Timer0
Reserved
SGCR [R/W, R] B, H, W
0------00 000--000
SGTR [R/W] B, H, W
XXXXXXXX
SGDR [R/W] B, H, W
XXXXXXXX
Sound Generator
611
APPENDIX
Table A-1 I/O Map (2 / 13)
Register
Address
00000098H
Block
+0
+1
+2
+3
LCDCMR [R/W]
B, H, W
00000000
-
LCR0 [R/W] B, H, W
00010000
LCR1 [R/W] B, H, W
00000000
0000009CH
VRAM0 [R/W] B, H, W VRAM1 [R/W] B, H, W VRAM2 [R/W] B, H, W VRAM3 [R/W] B, H, W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
000000A0H
VRAM4 [R/W] B, H, W VRAM5 [R/W] B, H, W VRAM6 [R/W] B, H, W VRAM7 [R/W] B, H, W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
000000A4H
VRAM8 [R/W] B, H, W VRAM9 [R/W] B, H, W
XXXXXXXX
XXXXXXXX
000000A8H
VRAM12 [R/W]
B, H, W
XXXXXXXX
VRAM13 [R/W]
B, H, W
XXXXXXXX
000000ACH
to
000000AFH
VRAM10 [R/W]
B, H, W
XXXXXXXX
VRAM11 [R/W]
B, H, W
XXXXXXXX
VRAM14 [R/W]
B, H, W
XXXXXXXX
VRAM15 [R/W]
B, H, W
XXXXXXXX
-
Reserved
SMR3 [R/W] B, H, W
00000000
000000B4H
ESCR3 [R/W] B, H, W
00000X00
ECCR3 [R/W,R,W]
B, H, W
000000XX
000000B8H
SCR4 [R/W] B, H, W
00000000
SMR4 [R/W] B, H, W
00000000
SSR4 [R/W,R] B, H, W
00001000
000000BCH
ESCR4 [R/W] B, H, W
00000X00
ECCR4 [R/W, R, W]
B, H, W
000000XX
BGR14 [R/W] B, H, W BGR04 [R/W] B, H, W
00000000
00000000
000000C0H
SCR5 [R/W] B, H, W
00000000
SMR5 [R/W] B, H, W
00000000
SSR5 [R/W, R] B, H, W
00001000
ESCR5 [R/W] B, H, W
00000X00
ECCR5 [R/W,R,W]
B, H, W
000000XX
000000C4H
000000C8H
to
000000D0H
SSR3 [R/W,R] B, H, W
00001000
RDR3/TDR3 [R/W]
B, H, W
−
SCR3 [R/W] B, H, W
00000000
000000B0H
LCD
Controller
Driver
LIN-UART0
BGR13 [R/W] B, H, W BGR03 [R/W] B, H, W
00000000
00000000
RDR4/TDR4 [R/W]
B, H, W
−
RDR5/TDR5 [R/W]
B, H, W
−
LIN-UART1
LIN-UART2
BGR15 [R/W] B, H, W BGR05 [R/W] B, H, W
00000000
00000000
-
Reserved
000000D4H
TCDT0 [R/W] H, W
00000000 00000000
-
TCCS0 [R/W] B, H, W
00000000
16-bit Free-Run
Timer 0
000000D8H
TCDT1 [R/W] H, W
00000000 00000000
-
TCCS1 [R/W] B, H, W
00000000
16-bit Free-Run
Timer 1
000000DCH
to
000000E0H
000000E4H
000000E8H
612
IPCP1 [R] H, W
XXXXXXXX XXXXXXXX
-
-
Reserved
IPCP0 [R] H, W
XXXXXXXX XXXXXXXX
-
ICS01 [R/W] B, H, W
00000000
16-bit ICU 0, 1
APPENDIX A I/O Map
Table A-1 I/O Map (3 / 13)
Register
Address
Block
+0
000000ECH
000000F0H
+1
+2
IPCP3 [R] H, W
XXXXXXXX XXXXXXXX
-
IPCP2 [R] H, W
XXXXXXXX XXXXXXXX
-
ICS23 [R/W] B, H, W
00000000
-
000000F4H
to
00000104H
00000108H
+3
OCCP1 [R/W] H, W
XXXXXXXX XXXXXXXX
0000010CH
-
-
00000110H
-
-
Reserved
OCCP0 [R/W] H, W
XXXXXXXX XXXXXXXX
-
-
-
Reserved
00000130H
PWCSR0 [R/W, R] B, H, W
0000000X 00000000
PWCR0 [R] H, W
00000000 00000000
00000134H
-
PDIVR0 [R/W] B, H, W
-----000
-
0000013CH
to
00000140H
PWC Timer
-
-
WTDBL [R/W] B
------0
00000144H
-
00000148H
-
0000014CH
WTHR [R/W] B, H
---XXXXX
16-bit OCU
OCS01 [R/W] B, H, W
11101100 00001100
00000114H
to
0000012CH
00000138H
16-bit ICU 2, 3
Reserved
WTCR [R/W, R] B, H
00000000 000-00-X
WTBR [R/W] B
---XXXXX XXXXXXX XXXXXXXX
WTMR [R/W] B, H
--XXXXXX
WTSR [R/W] B
--XXXXXX
Real Time Clock
----
00000150H
ADERH [R/W] B, H, W
00000000 00000000
ADERL [R/W] B, H, W
00000000 00000000
00000154H
ADCS1 [R/W] B, H, W ADCS0 [R/W] B, H, W
00000000
00000000
00000158H
ADCT1 [R/W] B, H, W ADCT0 [R/W] B, H, W ADSCH [R/W] B, H, W ADECH [R/W] B, H, W
00010000
00101100
---00000
---00000
ADCR1 [R] B, H, W
------XX
ADCR0 [R] B, H, W
XXXXXXXX
0000015CH
CUCR [R/W, R] B, H, W
-------- ---0--00
CUTD [R/W] B, H, W
10000000 00000000
00000160H
CUTR1 [R] B, H, W
-------- 00000000
CUTR2 [R] B, H, W
00000000 00000000
ADC
Clock Calibrator
613
APPENDIX
Table A-1 I/O Map (4 / 13)
Register
Address
Block
+0
00000164H
00000168H
0000016CH
00000170H
00000174H
00000178H
0000017CH
00000180H
00000184H
00000188H
0000018CH
00000190H
+1
PWC20 [R/W] B, H, W PWC10 [R/W] B, H, W
XXXXXXXX
XXXXXXXX
-
PWC0 [R/W] B
-0000--0
+3
-
Reserved
PWS20 [R/W] B, H, W PWS10 [R/W] B, H, W
-0000000
--000000
PWC21 [R/W] B, H, W PWC11 [R/W] B, H, W
XXXXXXXX
XXXXXXXX
-
-
PWC1 [R/W] B
-0000--0
PWS21 [R/W] B, H, W PWS11 [R/W] B, H, W
-0000000
--000000
PWC22 [R/W] B, H, W PWC12 [R/W] B, H, W
XXXXXXXX
XXXXXXXX
-
PWS22 [R/W] B, H, W PWS12 [R/W] B, H, W
-0000000
--000000
PWC23 [R/W] B, H, W PWC13 [R/W] B, H, W
XXXXXXXX
XXXXXXXX
-
-
PWC3 [R/W] B
-0000--0
PWS23 [R/W] B, H, W PWS13 [R/W] B, H, W
-0000000
--000000
PWC24 [R/W] B, H, W PWC14 [R/W] B, H, W
XXXXXXXX
XXXXXXXX
-
-
PWC4 [R/W] B
-0000--0
PWS24 [R/W] B, H, W PWS14 [R/W] B, H, W
-0000000
--000000
PWC25 [R/W] B, H, W PWC15 [R/W] B, H, W
XXXXXXXX
XXXXXXXX
-
PWC5 [R/W] B
-0000--0
PWS25 [R/W] B, H, W PWS15 [R/W] B, H, W
-0000000
--000000
Reserved
00000000
000001ACH
Reserved
-
-
-
CAN Prescaler
Reserved
000001B0H
-
TRG [R/W] B, H, W
00000000
-
REVC [R/W] B, H, W
00000000
000001B4H
PRLH0 [R/W]B, H, W
XXXXXXXX
PRLL0 [R/W]B, H, W
XXXXXXXX
PRLH1 [R/W]B, H, W
XXXXXXXX
PRLL1 [R/W]B, H, W
XXXXXXXX
000001B8H
PRLH2 [R/W]B, H, W
XXXXXXXX
PRLL2 [R/W]B, H, W
XXXXXXXX
PRLH3 [R/W]B, H, W
XXXXXXXX
PRLL3 [R/W]B, H, W
XXXXXXXX
000001BCH
PPGC0 [R/W]B, H, W
0000000X
PPGC1 [R/W]B, H, W
0000000X
PPGC2 [R/W]B, H, W
0000000X
PPGC3 [R/W]B, H, W
0000000X
000001C0H
PRLH4 [R/W]B, H, W
XXXXXXXX
PRLL4 [R/W]B, H, W
XXXXXXXX
PRLH5 [R/W]B, H, W
XXXXXXXX
PRLL5 [R/W]B, H, W
XXXXXXXX
000001C4H
PRLH6 [R/W]B, H, W
XXXXXXXX
PRLL6 [R/W]B, H, W
XXXXXXXX
PRLH7 [R/W]B, H, W
XXXXXXXX
PRLL7 [R/W]B, H, W
XXXXXXXX
000001C8H
PPGC4 [R/W]B, H, W
0000000X
PPGC5 [R/W]B, H, W
0000000X
PPGC6 [R/W]B, H, W
0000000X
PPGC7 [R/W]B, H, W
0000000X
614
SMC
-
CANPRE [R/W, R]
B, H, W
00000000
SMC
-
PWC2 [R/W] B
-0000--0
00000194H
to
000001A4H
000001A8H
+2
PPG0
APPENDIX A I/O Map
Table A-1 I/O Map (5 / 13)
Register
Address
Block
+0
+1
+2
000001CCH
to
000001FCH
-
00000200H
DMACA0 [R/W] B, H, W *1
00000000 0000XXXX XXXXXXXX XXXXXXXX
00000204H
DMACB0 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
00000208H
DMACA1 [R/W] B, H, W *1
00000000 0000XXXX XXXXXXXX XXXXXXXX
0000020CH
DMACB1 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
00000210H
DMACA2 [R/W] B, H, W *1
00000000 0000XXXX XXXXXXXX XXXXXXXX
00000214H
DMACB2 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
00000218H
DMACA3 [R/W] B, H, W *1
00000000 0000XXXX XXXXXXXX XXXXXXXX
0000021CH
DMACB3 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
00000220H
DMACA4 [R/W] B, H, W *1
00000000 0000XXXX XXXXXXXX XXXXXXXX
00000224H
DMACB4 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
00000228H
to
0000023CH
Reserved
00000240H
DMACR [R/W] B
0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX
00000244H
to
000003ECH
-
000003F0H
BSD0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000003F4H
BSD1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000003F8H
BSDC [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000003FCH
BSRR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+3
Reserved
DMAC
DMAC
Reserved
Bit Search
615
APPENDIX
Table A-1 I/O Map (6 / 13)
Register
Address
Block
+0
+1
+2
+3
00000400H
DDR0 [R/W] B, H, W
00000000
DDR1 [R/W] B, H, W
00000000
DDR2 [R/W] B, H, W
11111111
DDR3 [R/W] B, H, W
00001111
00000404H
DDR4 [R/W] B, H, W
00000000
DDR5 [R/W] B, H, W
00000000
DDR6 [R/W] B, H, W
00000000
DDR7 [R/W] B, H, W
----0000
00000408H
DDR8 [R/W] B, H, W
00000000
DDR9 [R/W] B, H, W
00000000
DDRA [R/W] B, H, W
----0000
DDRB [R/W] B, H, W
00000000
0000040CH
DDRC [R/W] B, H, W
----0000
DDRD [R/W] B, H, W
1111----
DDRE [R/W] B, H, W
00000000
DDRF [R/W] B, H, W
00000000
00000410H
DDRG [R/W] B, H, W
----0000
-
-
-
00000414H
to
0000041CH
-
Reserved
00000420H
PFR0 [R/W] B, H, W
00000000
PFR1 [R/W] B, H, W
00000000
PFR2 [R/W] B, H, W
00000000
PFR3 [R/W] B, H, W
00000000
00000424H
PFR4 [R/W] B, H, W
00000000
PFR5 [R/W] B, H, W
00000000
-
PFR7 [R/W] B, H, W
----0000
00000428H
-
-
PFRA [R/W] B, H, W
----0000
PFRB [R/W] B, H, W
00000000
0000042CH
PFRC [R/W] B, H, W
----0000
PFRD [R/W] B, H, W
00000000
PFRE [R/W] B, H, W
00000000
-
00000430H
PFRG [R/W] B, H, W
----0000
-
-
-
00000434H
to
0000043CH
616
-
Data Direction
Register
Port Function
Register
Reserved
APPENDIX A I/O Map
Table A-1 I/O Map (7 / 13)
Register
Address
Block
+0
+1
+2
+3
00000440H
ICR00 [R/W] B, H, W
---11111
ICR01 [R/W] B, H, W
---11111
ICR02 [R/W] B, H, W
---11111
ICR03 [R/W] B, H, W
---11111
00000444H
ICR04 [R/W] B, H, W
---11111
ICR05 [R/W] B, H, W
---11111
ICR06 [R/W] B, H, W
---11111
ICR07 [R/W] B, H, W
---11111
00000448H
ICR08 [R/W] B, H, W
---11111
ICR09 [R/W] B, H, W
---11111
ICR10 [R/W] B, H, W
---11111
ICR11 [R/W] B, H, W
---11111
0000044CH
ICR12 [R/W] B, H, W
---11111
ICR13 [R/W] B, H, W
---11111
ICR14 [R/W] B, H, W
---11111
ICR15 [R/W] B, H, W
---11111
00000450H
ICR16 [R/W] B, H, W
---11111
ICR17 [R/W] B, H, W
---11111
ICR18 [R/W] B, H, W
---11111
ICR19 [R/W] B, H, W
---11111
00000454H
ICR20 [R/W] B, H, W
---11111
ICR21 [R/W] B, H, W
---11111
ICR22 [R/W] B, H, W
---11111
ICR23 [R/W] B, H, W
---11111
00000458H
ICR24 [R/W] B, H, W
---11111
ICR25 [R/W] B, H, W
---11111
ICR26 [R/W] B, H, W
---11111
ICR27 [R/W] B, H, W
---11111
0000045CH
ICR28 [R/W] B, H, W
---11111
ICR29 [R/W] B, H, W
---11111
ICR30 [R/W] B, H, W
---11111
ICR31 [R/W] B, H, W
---11111
00000460H
ICR32 [R/W] B, H, W
---11111
ICR33 [R/W] B, H, W
---11111
ICR34 [R/W] B, H, W
---11111
ICR35 [R/W] B, H, W
---11111
00000464H
ICR36 [R/W] B, H, W
---11111
ICR37 [R/W] B, H, W
---11111
ICR38 [R/W] B, H, W
---11111
ICR39 [R/W] B, H, W
---11111
00000468H
ICR40 [R/W] B, H, W
---11111
ICR41 [R/W] B, H, W
---11111
ICR42 [R/W] B, H, W
---11111
ICR43 [R/W] B, H, W
---11111
0000046CH
ICR44 [R/W] B, H, W
---11111
ICR45 [R/W] B, H, W
---11111
ICR46 [R/W] B, H, W
---11111
ICR47 [R/W] B, H, W
---11111
00000470H
to
0000047CH
-
Interrupt Control
Unit
Reserved
00000480H
RSRR [R/W] B, H, W
10000000
STCR [R/W] B, H, W
00110011
TBCR [R/W] B, H, W
00XXXX11
CTBR [W] B, H, W
XXXXXXXX
00000484H
CLKR [R/W] B, H, W
00000000
WPR [R/W] B, H, W
XXXXXXXX
DIVR0 [R/W] B, H, W
00000011
DIVR1 [R/W] B, H, W
00000000
Clock Control Unit
617
APPENDIX
Table A-1 I/O Map (8 / 13)
Register
Address
00000488H
Block
+0
+1
+2
+3
-
-
OSCCR [R/W] B
X000XXX0
-
0000048CH
00000490H
OSCR [R/W] B
000--001
-
00000494H
to
000004F8H
000004FCH
-
-
00000500H
to
0000053CH
-
PILR0 [R/W] B, H, W
00000000
PILR1 [R/W] B, H, W
00000000
00000544H
-
PILR5 [R/W] B, H, W
0-------
00000548H
-
-
0000054CH
-
Reserved
00000550H
Reserved
-
00000554H
to
00000578H
-
-
-
-
-
Reserved
LVRC [R/W] B, H, W
00011000
00000580H
to
000005FCH
Reserved
Reserved
-
EPFR2 [R/W] B, H, W
00000000
EPFR3 [R/W] B, H, W
00000000
00000604H
EPFR4 [R/W] B, H, W
00000000
EPFR5 [R/W] B, H, W
00000000
-
-
00000608H
-
-
-
-
0000060CH
-
EPFRD [R/W] B, H, W
00000000
-
-
00000610H
EPFRG [R/W] B, H, W
----0000
-
-
-
618
CPU - Detection of
operation
Reserved
-
-
Port Input Level
Select Register
Reserved
00000600H
00000614H
to
0000063CH
Port Input Level
Select Register
Reserved
-
-
Main oscillation
stabilization wait
timer
Reserved
-
00000540H
0000057CH
Reserved
PSCR [W] B
XXXXXXXX
Clock Control Unit
Extra PFR
Extra PFR
Reserved
APPENDIX A I/O Map
Table A-1 I/O Map (9 / 13)
Register
Address
Block
+0
+1
+2
+3
00000640H
ASR0 [R/W] B, H, W
00000000 00000000
ACR0 [R/W] B, H, W
XX110*00 00000000
00000644H
ASR1 [R/W] B, H, W
XXXXXXXX XXXXXXXX
ACR1 [R/W] B, H, W
0XXX0X00 00X0XXXX
00000648H
ASR2 [R/W] B, H, W
XXXXXXXX XXXXXXXX
ACR2 [R/W] B, H, W
XXXX0X00 00X0XXXX
0000064CH
ASR3 [R/W] B, H, W
XXXXXXXX XXXXXXXX
ACR3 [R/W] B, H, W
01XX0X00 00X0XXXX
00000650H
to
0000065CH
Reserved
00000660H
AWR0 [R/W] B, H, W
01110000 01011011
AWR1 [R/W] B, H, W
XXXX0000 XX0X1XXX
00000664H
AWR2 [R/W] B, H, W
0XXX0000 XX0X1XXX
AWR3 [R/W] B, H, W
0XXX0000 0X0X1XXX
00000668H
to
0000067CH
00000680H
T-unit
CSER [R/W] B, H, W
00000001
-
Reserved
-
-
T-unit
00000684H
-
Reserved
000007F8H
000007FCH
-
MODR (*2)
-
-
-
00000800H
to
00000FFCH
-
-
-
-
Reserved
619
APPENDIX
Table A-1 I/O Map (10 / 13)
Register
Address
Block
+0
+1
+2
+3
00001000H
DMASA0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00001004H
DMADA0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00001008H
DMASA1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000100CH
DMADA1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00001010H
DMASA2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00001014H
DMADA2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00001018H
DMASA3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0000101CH
DMADA3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00001020H
DMASA4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00001024H
DMADA4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00001028H
to
00006FFCH
-
DMAC
Reserved
00007000H
FLCR [R/W]
01XX1000
-
-
-
00007004H
FLWC [R/W]
00000011
-
-
-
00007008H
to
0000FFFCH
-
Reserved
00020000H
CTRLR0
STATR0
00020004H
ERRCNT0
BTR0
00020008H
INTR0
TESTR0
0002000CH
BRPER0
-
00020010H
IF1CREQ0
IF1CMSK0
00020014H
IF1MSK20
IF1MSK10
00020018H
IF1ARB20
IF1ARB10
0002001CH
IF1MCTR0
----
00020020H
IF1DTA10
IF1DTA20
00020024H
IF1DTB10
IF1DTB20
00020028H
to
0002002CH
620
-
Flash I/F
(Only mass
production
products)
CAN0
APPENDIX A I/O Map
Table A-1 I/O Map (11 / 13)
Register
Address
Block
+0
+1
+2
+3
00020030H
Reserved (IF1 data mirror, little endian byte ordering)
00020034H
to
0002003CH
-
00020040H
IF2CREQ0
IF2CMSK0
00020044H
IF2MSK20
IF2MSK10
00020048H
IF2ARB20
IF2ARB10
0002004CH
IF2MCTR0
-
00020050H
IF2DTA10
IF2DTA20
00020054H
IF2DTB10
IF2DTB20
00020058H
to
0002005CH
-
00020060H
Reserved (IF2 data mirror, little endian byte ordering)
00020064H
to
0002007CH
-
00020080H
CAN0
TREQR20
TREQR10
00020084H
Reserved (32..128 Message buffer)
00020088H
to
0002008CH
-
00020090H
NEWDT20
NEWDT10
00020094H
Reserved (32..128 Message buffer)
00020098H
to
0002009CH
-
000200A0H
INTPND20
INTPND10
000200A4H
Reserved (32..128 Message buffer)
000200A8H
to
000200ACH
-
000200B0H
000200B4H
MESVAL20
MESVAL10
Reserved (32..128 Message buffer)
621
APPENDIX
Table A-1 I/O Map (12 / 13)
Register
Address
Block
+0
+1
+2
+3
00020100H
CTRLR1
STATR1
00020104H
ERRCNT1
BTR1
00020108H
INTR1
TESTR1
0002010CH
BRPER1
-
00020110H
IF1CREQ1
IF1CMSK1
00020114H
IF1MSK21
IF1MSK11
00020118H
IF1ARB21
IF1ARB11
0002011CH
IF1MCTR1
-
00020120H
IF1DTA11
IF1DTA21
00020124H
IF1DTB11
IF1DTB21
00020128H
to
0002012CH
-
00020130H
Reserved (IF1 data mirror, little endian byte ordering)
00020134H
to
0002013CH
-
00020140H
IF2CREQ1
IF2CMSK1
00020144H
IF2MSK21
IF2MSK11
00020148H
IF2ARB21
IF2ARB11
0002014CH
IF2MCTR1
-
00020150H
IF2DTA11
IF2DTA21
00020154H
IF2DTB11
IF2DTB21
00020158H
to
0002015CH
-
00020160H
Reserved (IF2 data mirror, little endian byte ordering)
00020164H
to
0002017CH
-
00020180H
TREQR21
TREQR11
00020184H
Reserved (32..128 Message buffer)
00020188H
to
0002018CH
-
00020190H
NEWDT21
NEWDT11
00020194H
Reserved (32..128 Message buffer)
00020198H
to
0002019CH
-
622
CAN1
APPENDIX A I/O Map
Table A-1 I/O Map (13 / 13)
Register
Address
Block
+0
000201A0H
+1
+2
INTPND21
INTPND11
000201A4H
Reserved (32..128 Message buffer)
000201A8H
to
000201ACH
-
000201B0H
+3
MESVAL21
CAN1
MESVAL11
000201B4H
Reserved (32..128 Message buffer)
00380000H
to
003FFFFCH
-
F-bus RAM
(32 Kbytes)
003A00000H
to
003FFFFCH
-
F-bus RAM
(24 Kbytes)
003C00000H
to
003FFFFCH
-
F-bus RAM
(16 Kbytes)
003E0000H
to
003FFFFCH
-
F-bus RAM
(8 Kbytes)
...
-
-
000A0000H
to
000FFFFCH
-
User ROM
512 Kbytes
(MB91F249/S)
...
-
-
000C0000H
to
000FFFFCH
-
User ROM
256 Kbytes
(MB91F248/S,
MB91248/S)
...
-
-
000E0000H
to
000FFFFCH
-
User ROM
128 Kbytes
(MB91247/S)
*1: The lower 16 bits (DTC[15:0]) of DMCA0 to DMCA4 cannot be accessed in bytes.
*2: This register is set by a pertinent mode vector fetch. It is inaccessible to users.
Notes:
• Do not use a read-modify-write (RMW) instruction for any register containing a write-only bit.
• Data in reserved or "-" areas is indeterminate.
623
APPENDIX
APPENDIX B Vector Table
Table B-1 contains an interrupt vector table. This table shows interrupt sources used in
MB91245/S series as well as assigned interrupt vectors and interrupt control registers.
■ Vector Table
ICR: This sets the interrupt level for each interrupt request by the registers provided in the interrupt
controller. ICR is available for each corresponding interrupt request.
TBR: This is the register that indicates the start address of the EIT vector table.
The vector address is calculated by adding TBR to the offset value determined for each EIT source.
The EIT vector area is a 1Kbyte area starting from the address indicated by TBR.
Each vector consists of 4 bytes. The relationship between vector numbers and vector addresses is as
follows:
vctadr
624
= TBR + vctofs
= TBR + (3FCH − 4 × vct)
vctadr:
Vector address
vctofs:
Vector offset
vct:
Vector number
APPENDIX B Vector Table
Table B-1 Vector Table (1 / 2)
Interrupt number
Interrupt factor
Decimal
Interrupt level
Hexa
decimal
Reset
0
0
Mode vector
1
1
System reserved
2
2
System reserved
3
3
System reserved
4
4
System reserved
5
5
System reserved
6
6
Coprocessor absent trap
7
7
Coprocessor error trap
8
8
INTE instruction
9
9
System reserved
10
0A
System reserved
11
0B
Step trace trap
12
0C
NMI request (tool)
13
0D
Undefined-instruction exception
14
0E
-
NMI request
15
0F
External interrupt 0
16
External interrupt 1
17
External interrupt 2
Offset
TBR default
address
3FCH
000FFFFCH
3F8H
000FFFF8H
3F4H
000FFFF4H
3F0H
000FFFF0H
3ECH
000FFFECH
3E8H
000FFFE8H
3E4H
000FFFE4H
DMA
activation
factor
3E0H
000FFFE0H
3DCH
000FFFDCH
3D8H
000FFFD8H
3D4H
000FFFD4H
3D0H
000FFFD0H
3CCHH
000FFFCCH
3C8H
000FFFC8H
3C4H
000FFFC4H
Always 15 (FH)
3C0H
000FFFC0H
-
10
ICR00
3BCH
000FFFBCH
6
11
ICR01
3B8H
000FFFB8H
7
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
-
Reload timer 0 underflow
24
18
ICR08
39CH
000FFF9CH
8
Reload timer 1 underflow
25
19
ICR09
398H
000FFF98H
9
Reload timer 2 underflow
26
1A
ICR10
394H
000FFF94H
10
UART0 (reception completed, reception error)
27
1B
ICR11
390H
000FFF90H
0
UART0 (transmission completed)
28
1C
ICR12
38CH
000FFF8CH
3
29
1D
ICR13
388H
000FFF88H
1
30
1E
ICR14
384H
000FFF84H
4
31
1F
ICR15
380H
000FFF80H
2
32
20
ICR16
37CH
000FFF7CH
5
33
21
ICR17
378H
000FFF78H
-
35
23
ICR19
370H
000FFF70H
-
36
24
ICR20
36CH
000FFF6CH
-
LIN-UART0 (reception completed, reception error,
LIN Synch break, bus idle)
LIN-UART0 (transmission completed)
LIN-UART1 (reception completed, reception error,
LIN Synch break, bus idle)
LIN-UART1 (transmission completed)
LIN-UART2 (reception completed, reception error,
LIN Synch break, bus idle)
CAN0 reception/transmission completed
Node status transition
CAN1 reception/transmission completed
Node status transition
625
APPENDIX
Table B-1 Vector Table (2 / 2)
Interrupt number
Interrupt factor
Offset
TBR default
address
Decimal
Hexa
decimal
Interrupt level
System reserved
37
25
ICR21
368H
000FFF68H
System reserved
38
26
ICR22
364H
000FFF64H
System reserved
39
27
ICR23
360H
000FFF60H
000FFF5CH
DMA
activation
factor
PWC (measurement completed)
40
28
ICR24
35CH
PWC (overflow)
41
29
ICR25
358H
000FFF58H
DMAC transfer completed, transfer error
42
2A
ICR26
354H
000FFF54H
-
000FFF50H
14
A/DC
Real-time clock
Hour/minute/second overflow, correction completed
System reserved
43
2B
ICR27
350H
44
2C
ICR28
34CH
000FFF4CH
-
45
2D
ICR29
348H
000FFF48H
46
2E
ICR30
344H
000FFF44H
000FFF40H
PPG4/5 underflow
50
32
ICR34
334H
PPG6/7 underflow
51
33
ICR35
330H
000FFF30H
-
52
34
ICR36
32CH
000FFF2CH
-
53
35
ICR37
328H
000FFF28H
000FFF24H
-
Main oscillator stabilization wait timer
Time-base timer overflow
47
2F
ICR31
340H
PPG0/1 underflow
48
30
ICR32
33CH
000FFF3CH
PPG2/3 underflow
49
31
ICR33
338H
000FFF38H
000FFF34H
16-bit free-run timer 0 overflow
and OCU0 compare match clear
16-bit free-run timer 1 overflow
ICU0 (fetch)
54
36
ICR38
324H
ICU1 (fetch)
55
37
ICR39
320H
000FFF20H
ICU2 (fetch)
56
38
ICR40
31CH
000FFF1CH
000FFF18H
000FFF14H
ICU3 (fetch)
57
39
ICR41
318H
OCU0 (match)
58
3A
ICR42
314H
OCU1 (match)
59
3B
ICR43
310H
000FFF10H
000FFF0CH
System reserved
60
3C
ICR44
30CH
System reserved
61
3D
ICR45
308H
000FFF08H
Sound generator designation counting completed
62
3E
ICR46
304H
000FFF04H
000FFF00H
Delay interrupt factor bit
63
3F
ICR47
300H
System reserved (used by REALOS)
64
40
2FCH
000FFEFCH
System reserved (used by REALOS)
65
41
-
2F8H
000FFEF8H
2F4H
|
2C0H
000FFEF4H
|
000FFEC0H
-
2BCH|
000FFEBCH
|
000FFC00H
-
System reserved
Used by INT Instruction
626
66
|
79
42
|
4F
-
80
|
255
50
|
FF
000H
APPENDIX C Status of Each Pin due to Reset
APPENDIX C Status of Each Pin due to Reset
This section describes the status of each pin due to reset.
■ Status of Pin During Reset
The state of each pin during a reset is determined by the setting of the mode pins (MD2 to MD0=00XB).
● When setting internal vector mode (MD2, MD1, MD0=000B)
The I/O pin (peripheral function pin) becomes high impedance (In the MB91245/S series, SEG0 to SEG11/
COM0 to COM3 is "L"output) and the read location of the mode data is the internal ROM.
● When setting external vector mode (MD2, MD1, MD0=001B)
The I/O pin (peripheral function pin) becomes high impedance (In the MB91245/S series, SEG0 to SEG11/
COM0 to COM3 is "L"output) and the read location of the mode data is the external ROM.
Note:
Concerning pins that become high impedance when a reset factor occurs, make sure that the
devices connected to those pins do not malfunction.
In the internal vector mode, be sure to store the mode data in the internal (Flash) ROM area.
Only address data multiplex is supported in the external bus mode. When using the external bus, set
the access type to address data multiplex.
For details on the state of each pin during reset, see Table C-1.
627
APPENDIX
Table C-1 Table of Pin Status for Each Mode (1 / 2)
Single Chip mode
Initial value
Pin Name
Function name
INITX
INITX
X0
X0
X1
X1
X0A
X0A
X1A
X1A
MD0
MD0
MD1
MD1
MD2
MD2
P00
P00/SEG24/INT0/D00
P01
P01/SEG25/INT1/D01
P02
P02/SEG26/INT2/D02
P03
P03/SEG27/INT3/D03
P04
P04/SEG28/INT4/D04
P05
P05/SEG29/INT5/D05
P06
P06/SEG30/D06
P07
P07/SEG31/ATGX/D07
P10 to P17
P10 to P17/SEG16 to SEG23/D08 to
D15
P20 to P27
P20 to P27/SEG0 to SEG7/A00 to A07
P30 to P33
P30 to P33/SEG8 to SEG11/A08 to
A11
P34 to P37
P34 to P37/SEG12 to SEG15/A12 to
A15
628
P40
P40/SIN0
P41
P41/SOT0
P42
P42/SCK0
P43
P43/SIN3
P44
P44/SOT3
P45
P45/SCK3
P46
P46/SGA/ASX
P47
P47/SGO/SYSCLK
P50
P50/SIN4/CK0/CS0X
P51
P51/SOT4/CS1X
INITX= when
set at "L"
INITX= when
set at "H"
STOP
SLEEP
HIZ=0
HIZ=1
Input permitted
Input permitted
Hi-Z or input permitted Hi-Z or input permitted
"H" output or input
permitted
Input permitted Input permitted
Input
permitted
"L" output
Output Hi-Z
Output Hi-Z
Input permitted Input permitted
Hi-Z or input permitted Hi-Z or input permitted
"H" output or input
permitted
"H" output or input
permitted
Input permitted
Input permitted
Operation during
P: Previous state held LCDC output or output
held, others
F: During LCDC output
Output Hi-Z
operation or output
when PFR0
held, when PFR0
register =0,
register =0, INT0 to
INT0 to INT5 input
INT5 input permitted
permitted
Output Hi-Z
Output Hi-Z
Input permitted Input permitted
"L" output
"H" output or input
permitted
P: Previous
state held
F: Normal
operation
P: Previous state held,
F: during LCDC output
operation or output held
Others Hi-Z
Operation during
LCDC output or
output held, others
Output Hi-Z/
Input fixed at "0"
P: Previous state held
F: Output held or
Hi-Z
Output Hi-Z/
Input fixed at "0"
APPENDIX C Status of Each Pin due to Reset
Table C-1 Table of Pin Status for Each Mode (2 / 2)
Single Chip mode
Initial value
Pin Name
Function name
P52
P52/SCK4/CS2X
P53
P53/SIN5/CK1/CS3X
P54
P54/SOT5/RDX
P55
P55/SCK5/WR0X
P56
P56/OUT0/WR1X
P57
P57/OUT1/RDY
P60 to P67
P60 to P67/AN0 to AN7
P70
P70/RX0/INT6
P71
P71/TX0
P72
P72/RX1/INT7
P73
P73/TX0
P80 to P87
P80 to P87/AN16 to AN23
P90 to P97
P90 to P97/AN24 to AN31
PA0 to PA3
PA0 to PA3/ PWMxxx to PWMxxx
PB0 to PB7
PB0 to PB7/ PWMxxx to PWMxxx
PC0 to PC3
PC0 to PC3/ PWMxxx to PWMxxx
PD0
PD0/TIN0/IN0/PWC0
PD1
PD1/TIN1
PD2
PD2/TIN2
PD3
PD3/IN3
PD4
PD4/COM0/PPG1
PD5
PD5/COM1/PPG3
PD6
PD6/COM2/PPG5
PD7
PD7/COM3/PPG7
PE0 to PE7
PE0 to PE7/ PWMxxx to PWMxxx
PF0 to PF7
PF0 to PF7/AN8 to AN15
PG0
PG0/PPG0
PG1
PG1/TOT0/PPG2
PG2
PG2/TOT1/PPG4
PG3
PG3/TOT2/PPG6
INITX= when
set at "L"
INITX= when
set at "H"
Output Hi-Z
Output Hi-Z
Input permitted Input permitted
Input permitted Input permitted
STOP
SLEEP
P: Previous
state held
F: Normal
operation
Input
permitted
HIZ=0
HIZ=1
P: Previous state held
F: Output held or
Hi-Z
Output Hi-Z/
Input fixed at "0"
P: Previous status held
F: Output held, INT6
input permitted
Output Hi-Z/when
PFR7 register =1,
INT6 input permitted
P: Previous state held,
F: Hi-Z
Output Hi-Z/
Input fixed at "0"
P: Previous status held
F: Output held,
INT7 input permitted
Output Hi-Z/when
PFR7 register =1,
INT7 input permitted
P: Previous state held
F: Output held or Hi-Z
Output Hi-Z/
Input fixed at "0"
Hi-Z
Input fixed at "0"
"L" output
P: Previous state held
LCDC: output or held
PPG: Output held
"L" output
P: Previous
state held
F: Normal
operation
Output Hi-Z
Output Hi-Z
Input permitted Input permitted
P: Previous state held
F: Output held or Hi-Z
Output Hi-Z/
Input fixed at "0"
629
APPENDIX
Table C-2 Table of Pin Status for Each Mode (1 / 3)
External Bus Mode
Initial value
8 bit
INITX=
INITX=
when set at when set at
"L"
"H"
SLEEP
INITX
X0
X1
X0A
Input
permitted
Input
permitted
Input
permitted
X1A
MD0
MD1
MD2
P00/SEG24/
INT0
P01/SEG25/
INT1
P02/SEG26/
INT2
P03/SEG27/
INT3
P04/SEG28/
INT4
P: Previous
P05/SEG29/
state held
INT5
Output Hi-Z Output Hi-Z F: Normal
input
input
operation
P06/SEG30 permitted permitted
P07/SEG31/
ATGX
D08 to D15
630
Initial value
(same as 8-bit)
STOP
Hi-Z
16 bits
HIZ=0
HIZ=1
Input
permitted
Hi-Z or
input
permitted
"H" output
or input
permitted
Hi-Z or
input
permitted
"H" output
or input
permitted
Input
permitted
Hi-Z or
input
permitted
"H" output
or input
permitted
Hi-Z or
input
permitted
"H" output
or input
permitted
Input
permitted
Input
permitted
P: Previous
state held
F:
Operation
during
LCDC
output or
output
held, when
PFR0
register=0,
INT0 to
INT5 input
permitted
P: Previous
state held,
F:
Operation
during
LCDC
output or
output held
Others
Hi-Z
Hi-Z
Operation
during
LCDC
output or
output held
other
output HiZ/ when
PFR0
register=0
INT0 to
INT5 input
permitted
Operation
during
LCDC
output or
output
held, others
output
Hi-z / input
fixed at "0"
Output HiZ/input
fixed at "0"
INITX=
INITX=
when set at when set at
"L"
"H"
STOP
SLEEP
HIZ=0
←
←
←
←
Input
permitted
Input
permitted
Input
permitted
←
←
←
←
HIZ=1
Input
Input
permitted permitted
Hi-Z or
Hi-Z or
input
input
permitted permitted
"H" output "H" output
or input
or input
permitted permitted
Hi-Z or
Hi-Z or
input
input
permitted permitted
"H" output "H" output
or input
or input
permitted permitted
Input
permitted
Input
permitted
Hi-Z
Output
Hi-Z/input
fixed at "0"
D00
D01
D02
D03
D04
D05
D06
D07
D08 to
D15
Output Hi-Z Output Hi-Z
input
input
permitted permitted
Hi-Z
APPENDIX C Status of Each Pin due to Reset
Table C-2 Table of Pin Status for Each Mode (2 / 3)
External Bus Mode
Initial value
8 bit
A00 to A07
INITX=
INITX=
when set at when set at
"L"
"H"
SLEEP
16 bits
HIZ=0
"L" output
A08 to A11
"H" output
F: Address F: Address
output
output
A12 to A15
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN3
P44/SOT3
P45/SCK3
P: Previous
F: Normal
Output Hi-Z
state held
operation
input
F: Output
P: Previous
permitted
held or
state held
Hi-Z
P: Previous
Output Hi-Z
state held,
input
P46/SGA/
ASX:
permitted "H" output
ASX
"H" output,
F: Normal
operation
P47/SGO/
SYSCLK
P: Previous
state held
CLK: CLK
CLK output
output
F: Normal
operation
P: Previous
state held,
ASX:
"H" output,
F: Output
held
P: Previous
state held
CLK:
"H" or "L"
output
F: Normal
operation
P50/SIN4/
CK0/CS0X
P51/SOT4/
CS1X
Bus control:
"H" output
P: Previous
state held
F: Normal
operation
P52/SCK4/
CS2X
P53/SIN5/
CK1/CS3X
P54/SOT5/
RDX
Output Hi-Z
input
P55/SCK5/ permitted
WR0X
P56/OUT0
P57/OUT1/
RDY
Initial value
(same as 8-bit)
STOP
"H" output
P: Previous
state held
F: Normal
operation,
when
EPFR=0:
"H" output
P: Previous
state held
RDY input F: Normal
state RDY
input
Bus
control:
"H" output
P: Previous
state held
F: Output
held or
Hi-Z
HIZ=1
INITX=
INITX=
when set at when set at
"L"
"H"
STOP
SLEEP
A00 to
A07
"L" output
F: Address
A08 to
"H" output
output
A11
A12 to
A15
P40/SIN0
F: Normal
P41/SOT0
Output Hi-Z
operation
P42/SCK0
input
P43/SIN3
P: Previous
permitted
P44/SOT3
state held
Output P45/SCK3
Hi-Z/
P: Previous
input fixed
state held
Output Hi-Z
at 0
P46/SGA/
ASX: "H"
input
"H" output
ASX
output,
permitted
F: Normal
operation
P47/SGO/
SYSCLK
HIZ=0
HIZ=1
F: Address
output
P: Previous
state held
F: Output
held or Hi-Z
Output
P: Previous Hi-Z/input
state held fixed at "0"
ASX: "H"
output,
F: Output
held
P: Previous
P: Previous
state held,
state held,
CLK: "H"
CLK: CLK
CLK output
or "L"
output
output
F: Normal
F: Normal
operation
operation
P50/SIN4/
CK0/
CS0X
P51/
SOT4/
CS1X
P52/
SCK4/
CS2X
P53/SIN5/
Bus control: Bus control:
CK1/
"H" output "H" output
CS3X
P: Previous P: Previous
P54/
"H" output
state held
state held
SOT5/
Output
Output Hi-Z
Output
F: Normal F: Output
RDX
Hi-Z/
input
operation held or Hi-Z Hi-Z/input
P55/
input fixed
permitted
fixed at "0"
SCK5/
at 0
WR0X
P: Previous
state held
F: output
held, when
EPFR=0:
"H" output
P56/
OUT0/
WR1X
P: Previous
state held
F: Output
held RDY
input
P57/
OUT1/
RDY
P: Previous P: Previous
state held
state held
RDY input F: Normal F: Output
state RDY held RDY
input
input
631
APPENDIX
Table C-2 Table of Pin Status for Each Mode (3 / 3)
External Bus Mode
Initial value
8 bit
P60 to P77/
AN0 to AN7
P70/RX0/
INT6
P71/TX0
P72/RX1/
INT7
P80 to P87/
AN16 to
AN23
P90 to P97/
AN24 to
AN31
PA0 to PA3/
PWMxxxPWMxxx
PB0 to PB7/
PWMxxxPWMxxx
PC0 to PC3/
PWMxxxPWMxxx
PD0/TIN0/
IN0/PWC0
PD1/TIN1
PD2/TIN2
PD3/IN3
PD4/COM0/
PPG1
PD5/COM1/
PPG3
PD6/COM2/
PPG5
PD7/COM3/
PPG7
PE0 to PE7/
PWMxxxPWMxxx
PF0 to PF7/
AN8 to
AN15
PG0/PPG0
PG1/TOT0/
PPG2
PG2/TOT1/
PPG4
PG3/TOT2/
PPG6
632
INITX=
INITX=
when set at when set at
"L"
"H"
Initial value
(same as 8-bit)
STOP
SLEEP
16 bits
HIZ=0
HIZ=1
INITX=
INITX=
when set at when set at
"L"
"H"
Same as the single chip mode
STOP
SLEEP
HIZ=0
HIZ=1
APPENDIX D Notes when Little Endian Area is Used
APPENDIX D Notes when Little Endian Area is Used
This appendix explains operating suggestions for the following items when using the
little endian area.
• C compiler
• Assembler
• Linker
• Debugger
■ C Compiler (fcc911)
Please note that operations cannot be guaranteed, if the following operations are performed to the little
endian area when programming by C language.
- Arrangement of variable with initial value
- Assignment of structure
- Operations other than character type array that uses character string operation function
- Specification of -K lib option when using character string operation function
- Use of double type and long double type
- Arrangement of stack in little endian area
● Arrangement of variable with initial value
The variable with an initial value cannot be arranged in the little endian area.
The compiler does not have a function to generate an initial value of the little endian. The variable can be
arranged in the little endian area but an initial value cannot be set to it.
Please run a process to set an initial value at the head of the program.
[Example] When setting an initial value to the variable little_data of the little endian area.
extern int little_data;
void little_init(void) {
little_data = initial value;
}
void main(void) {
little_init();
...
}
633
APPENDIX
● Assignment of structure
When assigning between structures, the compiler selects the best method to transfer and transfers on a byte,
halfword, and word basis. Therefore, when the structure assignment is done between a structure variable
allocated in the normal area and a structure variable allocated in the little endian area, a correct result
cannot be obtained.
Please assign the structure member respectively.
[Example] When assigning the structure to the structure variable little_st of the little endian area.
struct tag { char c; int i; } normal_st;
extern struct tag little_st;
#define STRMOVE(DEST,SRC) DEST.c=SRC.c;DEST.i=SRC.i;
void main(void) {
STRMOVE(little_st,normal_st);
}
In addition, the arrangement of the structure member is different in each compiler. Therefore, the member's
arrangement might be different from that of the structure compiled by other compilers. In this case, a
correct result is not obtained from the above-mentioned method.
Please do not arrange the structure variable in the little endian area when the arrangement of the structure
member is different.
● Operations other than character type array that uses character string operation function
The character string operation function prepared as a standard library processes on a byte basis. Therefore,
when processing by using the character string operation function is done to the area with types other than
char, unsigned char, and the signed char type arranged in the little endian area, a correct result cannot be
obtained.
Please do not use such processing.
[Example of trouble] Transferring of word data with memcpy
int big = 0x01020304;
/* Big endian area
*/
extern int little;
/* Little endian area
*/
memcpy(&little,&big, 4);
/* Transferring by memcpy */
The above-mentioned execution result is as follows:
(Big endian area)
01 02
03
04
(Little endian area)
→ memcpy →
01
02
03
04
04
03 02
01
The result of transferring the word data is incorrect.
(Correct result)
634
APPENDIX D Notes when Little Endian Area is Used
● Specification of -K lib option when using character string operation function
When -K lib option is specified, the compiler performs inline expansion to some character string operation
functions. At this time, since the best processing method is selected, the processing may be changed to the
halfword or the word basis processing.
Therefore, processing to the little endian area is not executed correctly.
Please do not specify -K lib option when a process is executed to the little endian area by using the
character string operation function.
Also, please do not specify either -O4 option or -K speed option that including -K lib option.
● Use of double type and long double type
The access to the double type and the long double type is done by using a method of accessing to one highlevel word and one low-level word respectively. Therefore, accessing to the double type and the long
double type variables arranged in the little endian area yields an incorrect result.
The substitution of the variables of the same type allocated in the little endian area is possible. However,
these substitutions are occasionally replaced with the substitution of the constant as a result of optimization.
Please do not arrange either double type or long double type variables in the little endian area.
[Example of trouble] Transferring of double type data
double big = 1.0;
/* Big endian area
*/
extern int little;
/* Little endian area
*/
little = big;
/* Transferring of double type data */
The above-mentioned execution result is as follows:
(Big endian area)
3f
f0
00
00
00
00
(Little endian area)
00
00
→
00
00
f0
3f
00
00
00
00
00
00
00
00
f0
3f
The result of transferring the double type data is incorrect.
(Correct result)
00
00
● Arrangement of stack in little endian area
When all or a part of the stack is arranged in the little endian area, operation is not guaranteed.
635
APPENDIX
■ Assembler (fasm911)
For programming using the assembler language of FR family, operating suggestions relating to the little
endian area are shown below.
● Section
The little endian area is used mainly for exchanging data to the little endian CPU. Therefore, please define
the little endian area as a data section where an initial value does not exist.
When specifying a code, a stack, or a data section with an initial value to the little endian area, the access
operation by MB91245/S series cannot be guaranteed.
[Example]
/* Correct section definition in the little endian area */
.SECTION Little_Area, DATA, ALIGN=4
Little_Word:
.RES.W 1
Little_Half:
.RES.H 1
Little_Byte:
.RES.B 1
● Data access
When accessing to the little endian area data, coding can be done to the value of the data without
considering endians. However, please access to the little endian area data by using the same size access as
the data size.
[Example]
LDI
#0x01020304, r0
LDI
#Little_Word, r1
LDI
#0x0102, r2
LDI
#Little_Half, r3
LDI
#0x01, r4
LDI
#Little_Byte, r5
/* Use a ST instruction (or a LD instruction, etc.) for 32-bit data access */
ST
r0, @r1
/* Use a STH instruction (or a LDH instruction, etc.) for 16-bit data access */
STH
636
r2, @r3
APPENDIX D Notes when Little Endian Area is Used
/* Use a STB instruction (or LDB instruction, etc.) for 8-bit data access */
STB
r4, @r5
The value cannot be guaranteed when accessing it by a different data size in this MB91245/S series. For
example, when two consecutive 16-bit data are accessed at a time by using a 32-bit access instruction, the
value of data cannot be guaranteed.
637
APPENDIX
■ Linker (flnk911)
For making the program that uses the little endian area, operating suggestions for the section arrangement
when linking are shown below.
● Section type limitation
Only the data section without an initial value can be arranged in the little endian area.
When the data section with an initial value, stack section, and code section are arranged in the little endian
area, since the arithmetic processing of the address solution etc. is performed in the big endian inside of the
linker, so the program operation cannot be guaranteed.
● Undetected error
The linker does not recognize the little endian area. Therefore, the error message is not notified even if an
arrangement that violates the above-mentioned limitations is done. Please confirm the content of the
section arranged in the little endian area thoroughly before using the linker.
638
APPENDIX D Notes when Little Endian Area is Used
■ Debugger (sim911, eml911, mon911)
● Simulator debugger
There is no memory space specification instruction to indicate the little endian area.
Therefore, memory operation instructions and instruction executions that operate memory are treated as big
endian.
● Emulator debugger and monitor debugger
When the little endian area is accessed by the following instructions, it is not treated as a normal value.
– set memory/show memory/enter/examine/set watch instruction
→ When using floating point (single/double) data, the specified value cannot be set or displayed.
– search memory instruction
→ When searching halfword and word data, the specified value cannot be searched.
– Line/reverse assemble (including reverse assemble display of the source window)
→ Normal instruction codes cannot be set or displayed (Please do not arrange the instruction code
in the little endian area).
– call/show call instruction
→ When the stack area is placed in the little endian area, it does not operate properly (Please do not
arrange the stack area in the little endian area).
639
APPENDIX
APPENDIX E Instruction Lists
FR family instruction lists are shown below.
■ Instruction Lists
[How to read instruction lists]
Mnemonic
ADD Rj, Rj
*ADD #s5, Rj
(1)
Type
A
C
OP
AG
A4
CYC
1
1
NZVC
CCCC
CCCC
,
,
,
,
,
,
,
,
,
,
(2)
(3)
(4)
(5)
(6)
Operation
Ri + Rj -> Rj
Ri + s5 -> Ri
Remarks
,
,
(7)
(1) Instruction name
An asterisk (*) indicates an extended instruction that is not contained in the CPU specifications and is
obtained by extension or addition by the assembler.
(2) Symbols indicating addressing modes that can be specified for the operand.
For the meaning of symbols, see "Addressing Mode Symbols (on the next page)".
(3) Instruction format
(4) Instruction code in hexadecimal notation
(5) Number of machine cycles
a:
Memory access cycle. It may be extended by the Ready function.
b:
Memory access cycle. It may be extended by the Ready function.
However, the cycle is interlocked if the instruction immediately after refers to a targeted register
for LD operation, and the number of execution cycles is increased by 1.
c:
Interlocked if the instruction immediately after is an instruction that reads or writes to R15, SSP,
or USP, or an instruction in instruction format A. The number of execution cycles is increased by
1 and so it becomes 2.
d:
Interlocked if the instruction immediately after refers to MDH/MDL. The number of execution
cycles is increased to 2.
The minimum cycle number is 1 for each case a, b, c, and d.
(6) Indicating flag changes
Flag change
C: Change
-: No change
0: Clear
1: Set
(7) Instruction operation
640
Flag meaning
N: Negative flag
Z: Zero flag
V: Over flag
C: Carry flag
APPENDIX E Instruction Lists
● Addressing mode symbols
Ri
: Register direct (R0 to R15, AC, FP, SP)
Rj
: Register direct (R0 to R15, AC, FP, SP)
R13
: Register direct (R13, AC)
Ps
: Register direct (Program status register)
Rs
: Register direct (TBR, RP, SSP, USP, MDH, MDL)
Cri
: Register direct (CR0 to CR15)
CRj
: Register direct (CR0 to CR15)
#i8
: Unsigned 8-bit immediate (-128 to 255)
Note: -128 to -1 is handled as 128 to 255.
#i20
: Unsigned 20-bit immediate (-0X80000 to 0XFFFFF)
Note: -0X7FFFF to -1 is handled as 0X7FFFF to 0XFFFFF.
#i32
: Unsigned 32-bit immediate (-0X80000000 to 0XFFFFFFFF)
Note: -0X80000000 to -1 is handled as 0X80000000 to 0XFFFFFFFF.
#s5
: Signed 5-bit immediate (-16 to 15)
#s10
: Signed 10-bit immediate (-512 to 508, multiples of 4 only)
#u4
: Unsigned 4-bit immediate (0 to 15)
#u5
: Unsigned 5-bit immediate (0 to 31)
#u8
: Unsigned 8-bit immediate (0 to 255)
#u10
: Unsigned 10-bit immediate (0 to 1020, multiples of 4 only)
@dir8
: Unsigned 8-bit direct address (0 to 0XFF)
@dir9
: Unsigned 9-bit direct address (0 to 0X1FE, multiples of 2 only)
@dir10
: Unsigned 10-bit direct address (0 to 0X3FC, multiples of 4 only)
label9
: Signed 9-bit branch address (-0X100 to 0XFC, multiples of 2 only)
label12
: Signed 12-bit branch address (-0X800 to 0X7FC, multiples of 2 only)
label20
: Signed 20-bit branch address (-0X80000 to 0X7FFFF)
label32
: Signed 32-bit branch address (-0X80000000 to 0X7FFFFFFF)
@Ri
: Register indirect (R0 to R15, AC, FP, SP)
@Rj
: Register indirect (R0 to R15, AC, FP, SP)
@(R13,Rj)
: Register relative indirect (Rj: R0 to R15, AC, FP, SP)
@(R14,disp10)
: Register relative indirect (disp10: -0X200 to 0X1FC, multiples of 4 only)
@(R14,disp9)
: Register relative indirect (disp9: -0X100 to 0XFE, multiples of 2 only)
@(R14,disp8)
: Register relative indirect (disp8: -0X80 to 0X7F)
@(R15,udisp6)
: Register relative indirect (udisp6: 0 to 60, multiples of 4 only)
@Ri+
: Register indirect with post-increment (R0 to R15, AC, FP, SP)
@R13+
: Register indirect with post-increment (R13, AC)
@SP+
: Stack pop
@-SP
: Stack push
(reglist)
: Register list
641
APPENDIX
● Instruction format
Figure E-1 Instruction Format
MSB
LSB
16bits
A
B
OP
Rj
Ri
8
4
4
OP
i8/O8
Ri
4
8
4
C
OP
u4/m4
Ri
8
4
4
ADD, ADDN, CMP, LSL, LSR, and ASR instructions only
*C'
OP
7
D
F
5
4
8
OP
SUB-OP
Ri
8
4
4
OP
rel11
5
642
Ri
u8/rel8/dir/
reglist
8
OP
E
s5/u5
11
APPENDIX E Instruction Lists
Appendix Table E-1 Addition and Subtraction
Mnemonic
Type
OP
CYCLE
NZVC
Operation
ADD Rj, Ri
*ADD #s5, Ri
A
C’
A6
A4
1
1
CCCC
CCCC
Ri+Rj->Ri
Ri+s5->Ri
ADD #u4, Ri
ADD2 #u4, Ri
ADDN Rj, Ri
ADDN Rj, Ri
*ADDN #s5, Ri
C
C
A
A
C’
A4
A5
A7
A2
A0
1
1
1
1
1
CCCC
CCCC
CCCC
-------
Ri+extu(i4)->Ri
Ri+extu(i4)->Ri
Ri+Rj+c->Ri
Ri+Rj->Ri
Ri+s5->Ri
ADDN #u4, Ri
ADDN2 #u4, Ri
SUB Rj, Ri
SUBC Rj, Ri
SUBN Rj, Ri
C
C
A
A
A
A0
A1
AC
AD
AE
1
1
1
1
1
------CCCC
CCCC
----
Ri+extu(i4)->Ri
Ri+extu(i4)->Ri
Ri-Rj->Ri
Ri-Rj-c->Ri
Ri-Rj->Ri
Remarks
The assembler treats the
highest-order 1 bit as the
sign.
Zero extension
Minus extension
Addition with carry
The assembler treats the
highest-order 1 bit as the
sign.
Zero extension
Minus extension
Subtraction with carry
Appendix Table E-2 Comparison Operation
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remarks
CMP Rj, Ri
*CMP #s5, Ri
A
C’
AA
A8
1
1
CCCC
CCCC
Ri-Rj
Ri-s5
The assembler treats the
highest-order 1 bit as the sign.
CMP #u4, Ri
CMP2 #u4, Ri
C
C
A8
A9
1
1
CCCC
CCCC
Ri-extu(i4)
Ri-extu(i4)
Zero extension
Minus extension
643
APPENDIX
Appendix Table E-3 Logic Operation
Mnemonic
Type
OP
CYCLE
NZVC
A
A
A
A
A
A
A
A
A
A
A
A
82
84
85
86
92
94
95
96
9A
9C
9D
9E
1
1+2a
1+2a
1+2a
1
1+2a
1+2a
1+2a
1
1+2a
1+2a
1+2a
CC-CC-CC-CC-CC-CC-CC-CC-CC-CC-CC-CC--
AND Rj, Ri
AND Rj, @Ri
ANDH Rj, @Ri
ANDB Rj, @Ri
OR Rj, Ri
OR Rj, @Ri
ORH Rj, @Ri
ORB Rj, @Ri
EOR Rj, Ri
EOR Rj, @Ri
EORH Rj, @Ri
EORB Rj, @Ri
Operation
RMW
Ri & = Rj
(Ri) & = Rj
(Ri) & = Rj
(Ri) & = Rj
Ri | = Rj
(Ri) | = Rj
(Ri) | = Rj
(Ri) | = Rj
Ri ^ = Rj
(Ri) ^ = Rj
(Ri) ^ = Rj
(Ri) ^ = Rj
❍
❍
❍
❍
❍
❍
❍
❍
❍
Remarks
Word
Word
Halfword
Byte
Word
Word
Halfword
Byte
Word
Word
Halfword
Byte
Appendix Table E-4 Bit Manipulation Instruction
Mnemonic
Type OP
BANDL #u4, @Ri
BANDH #u4, @Ri
*BAND #u8, @Ri
CYCLE
NZVC
Operation
RMW
Remarks
C
C
80
81
1+2a
1+2a
----------
(Ri)&=(0xF0+u4)
(Ri)&=((u4<<4)+0x0F)
(Ri)&=u8
❍
❍
-
Low-order 4 bits are manipulated.
High-order 4 bits are manipulated.
C
C
90
91
1+2a
1+2a
----------
(Ri) | = u4
(Ri) | = (u4<<4)
(Ri) | = u8
❍
❍
-
Low-order 4 bits are manipulated.
High-order 4 bits are manipulated.
C
C
98
99
1+2a
1+2a
----------
(Ri) ^ = u4
(Ri) ^ = (u4<<4)
(Ri) ^ = u8
❍
❍
-
Low-order 4 bits are manipulated.
High-order 4 bits are manipulated.
C
C
88
89
2+a
2+a
0C-CC--
(Ri) & u4
(Ri) & (u4<<4)
-
Low-order 4 bits are tested.
High-order 4 bits are tested.
*1
BORL #u4, @Ri
BORH #u4, @Ri
*BOR #u8, @Ri
*2
BEORL #u4, @Ri
BEORH #u4, @Ri
*BEOR #u8, @Ri
*3
BTSTL #u4, @Ri
BTSTH #u4, @Ri
*1:
The assembler generates BANDL if the bit is set at u8&0x0F, and BANDH if the bit is set at u8&0xF0. In some
cases, both BANDL and BANDH may be generated.
*2:
The assembler generates BORL if the bit is set at u8&0x0F, and BORH if the bit is set at u8&0xF0. In some cases,
both BORL and BORH are generated.
*3:
The assembler generates BEORL if the bit is set at u8&0x0F, and BEORH if the bit is set at u8&0xF0. In some cases,
both BEORL and BEORH are generated.
644
APPENDIX E Instruction Lists
Appendix Table E-5 Multiplication and Division
Mnemonic
Type
OP
CYCLE
NZVC
A
A
A
A
E
E
E
E
E
E
AF
AB
BF
BB
97-4
97-5
97-6
97-7
9F-6
9F-7
5
5
3
3
1
1
d
1
1
1
36
CCCCCCCC-CC--------C-C
-C-C
-------C-C
Ri * Rj -> MDH, MDL
Ri * Rj -> MDH, MDL
Ri * Rj -> MDL
Ri * Rj -> MDL
-C-C
MDL / Ri -> MDL , MDL % Ri -> MDH
MUL Rj,Ri
MULU Rj,Ri
MULH Rj,Ri
MULUH Rj,Ri
DIV0S Ri
DIV0U Ri
DIV1 Ri
DIV2 Ri
DIV3
DIV4S
*DIV Ri
*2
Remarks
32bit*32bit=64bit
No sign
16bit*16bit=32bit
No sign
Step operation
32bit/32bit=32bit
MDL / Ri -> MDL , MDL % Ri -> MDH
*1
*DIVU Ri
Operation
*1:
DIV0S, DIV1 x 32, DIV2, DIV3, and DIV4S are generated. The instruction code length becomes 72 bytes.
*2:
DIV0U and DIV1 x 32 are generated. The instruction code length becomes 66 bytes.
Appendix Table E-6 Shift
Mnemonic
Type
OP
CYCLE
NZVC
Operation
A
C’
C
C
A
C’
C
C
A
C’
C
C
B6
B4
B4
B5
B2
B0
B0
B1
BA
B8
B8
B9
1
1
1
1
1
1
1
1
1
1
1
1
CC-C
CC-C
CC-C
CC-C
CC-C
CC-C
CC-C
CC-C
CC-C
CC-C
CC-C
CC-C
Ri << Rj -> Ri
Ri << u5 -> Ri
Ri << u4 -> Ri
Ri <<(u4+16) -> Ri
Ri >> Rj -> Ri
Ri >> u5 -> Ri
Ri >> u4 -> Ri
Ri >>(u4+16) -> Ri
Ri >> Rj -> Ri
Ri >> u5 -> Ri
Ri >> u4 -> Ri
Ri >>(u4+16) -> Ri
LSL Rj, Ri
*LSL #u5, Ri(u5:0 to 31)
LSL #u4, Ri
LSL2 #u4, Ri
LSR Rj, Ri
*LSR #u5, Ri(u5:0 to 31)
LSR #u4, Ri
LSR2 #u4, Ri
ASR Rj, Ri
*ASR #u5, Ri (u5:0 to 31)
ASR #u4, Ri
ASR2 #u4, Ri
Remarks
Logical shift
Logical shift
Arithmetic shift
Appendix Table E-7 Immediate Value Set/16-Bit/32-Bit Immediate Value Transfer Instruction
Mnemonic
LDI:32 #i32, Ri
LDI:20 #i20, Ri
LDI:8 #i8, Ri
*LDI # {i8|i20|i32} ,Ri
Type
OP
CYCLE
NZVC
E
C
B
9F-8
9B
C0
3
2
1
----------
Operation
Remarks
i32 -> Ri
High-order 12 bits are zero-extended.
i20 -> Ri
High-order 24 bits are zero-extended.
i8 -> Ri
{i8 | i20 | i32} -> Ri
*
*:
If the immediate value is an absolute value, i8, i20, or i32 is selected automatically by the assembler.
If immediate value contains a relative value or an external reference symbol, i32 is selected.
645
APPENDIX
Appendix Table E-8 Memory Load
Mnemonic
LD @Rj, Ri
LD @(R13,Rj), Ri
LD @(R14,disp10),Ri
LD @(R15,udisp6),Ri
LD @R15+, Ri
LD @R15+, Rs
LD @R15+, PS
LDUH @Rj, Ri
LDUH @(R13,Rj), Ri
LDUH @(R14,disp9), Ri
LDUB @Rj, Ri
LDUB @(R13,Rj), Ri
LDUB @(R14,disp8), Ri
Type
OP
CYCLE
NZVC
Operation
A
A
B
C
E
E
E
A
A
B
A
A
B
04
00
2
03
07-0
07-8
07-9
05
01
4
06
02
6
b
b
b
b
b
b
1+a+b
b
b
b
b
b
b
------------------CCCC
-------------------
(Rj)->Ri
(R13+Rj)->Ri
(R14+disp10)->Ri
(R15+udisp6)->Ri
(R15)->Ri,R15+=4
(R15)->Rs,R15+=4
(R15)->PS, R15+=4
(Rj)->Ri
(R13+Rj)->Ri
(R14+disp9)->Ri
(Rj)->Ri
(R13+Rj)->Ri
(R14+disp8)->Ri
Remarks
Rs: Special register
*
Zero extension
Zero extension
Zero extension
Zero extension
Zero extension
Zero extension
*: In the o8 and o4 fields of the hardware specifications, the assembler calculates values and sets them as shown below:
disp10/4->o8, disp9/2->o8, disp8->o8, disp10, disp9, and disp8 have a sign, udisp6/4->o4 udisp6 has no sign.
Appendix Table E-9 Memory Store
Mnemonic
ST Ri,@Rj
ST Ri,@(R13,Rj)
ST Ri,@(R14,disp10)
ST Ri,@(R15,udisp6)
ST Ri,@-R15
ST Rs,@-R15
ST PS,@-R15
STH Ri,@Rj
STH Ri,@(R13,Rj)
STH Ri,@(R14,disp9)
STB Ri,@Rj
STB Ri,@(R13,Rj)
STB Ri,@(R14,disp8)
Type
OP
CYCLE
NZVC
Operation
A
A
B
C
E
E
E
A
A
B
A
A
B
14
10
3
13
17-0
17-8
17-9
15
11
5
16
12
7
a
a
a
a
a
a
a
a
a
a
a
a
a
----------------------------------------
Ri->(Rj)
Ri->(R13+Rj)
Ri->(R14+disp10)
Ri->(R15+udisp6)
R15-=4,Ri->(R15)
R15-=4, Rs->(R15)
R15-=4, PS->(R15)
Ri->(Rj)
Ri->(R13+Rj)
Ri->(R14+disp9)
Ri->(Rj)
Ri->(R13+Rj)
Ri->(R14+disp8)
Remarks
Word
Word
Word
Rs: Special register
*
Halfword
Halfword
Halfword
Byte
Byte
Byte
*: In the o8 and o4 fields of the hardware specifications, the assembler calculates values and sets them as shown below:
disp10/4->o8, disp9/2->o8, disp8->o8, disp10, disp9, and disp8 have a sign, udisp6/4->o4 udisp6 has no sign.
Appendix Table E-10 Register-to-Register Transfer
Mnemonic
MOV
MOV
MOV
MOV
MOV
*:
646
Rj, Ri
Rs, Ri
Ri, Rs
PS, Ri
Ri, PS
Type
OP
CYCLE
NZVC
A
A
E
E
E
8B
B7
B3
17-1
07-1
1
1
1
1
c
------------CCCC
Special register Rs: TBR, RP, USP, SSP, MDH, and MDL
Operation
Rj -> Ri
Rs -> Ri
Ri -> Rs
PS -> Ri
Ri -> PS
Remarks
Transfer between generalpurpose registers
Rs: Special register
Rs: Special register
*
APPENDIX E Instruction Lists
Appendix Table E-11 Normal Branch (No Delay)
Mnemonic
Type
OP
CYCLE
NZVC
JMP @Ri
CALL label12
CALL @Ri
RET
INT #u8
E
E
F
E
D
97-0
D0
97-1
97-2
1F
2
2
2
2
3+3a
----------------
INTE
E
9F-3
3+3a
----
RETI
BRA label9
BNO label9
BEQ label9
E
D
D
D
97-3
E0
E1
E2
2+2A
2
1
2/1
CCCC
----------
BNE label9
BC label9
BNC label9
BN label9
BP label9
BV label9
BNV label9
BLT label9
BGE label9
BLE label9
BGT label9
BLS label9
BHI label9
D
D
D
D
D
D
D
D
D
D
D
D
D
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
----------------------------------------
Operation
Remarks
Ri -> PC
PC+2->RP , PC+2+(label12-PC-2)->PC
PC+2->RP ,Ri->PC
RP -> PC
Return
SSP-=4, PS->(SSP), SSP-=4, PC+2->(SSP),
0->I Flag, 0->S Flag,
(TBR+0x3FC-u8 × 4)->PC
SSP-=4, PS->(SSP), SSP-=4, PC+2->(SSP),
0->S Flag,(TBR+0x3D8)->PC
For emulator
(R15)->PC,R15-=4,(R15)->PS,R15-=4
PC+2+(label9-PC-2)->PC
No branch
if(Z==1) then
PC+2+(label9-PC-2)->PC
↑ s/Z==0
↑ s/C==1
↑ s/C==0
↑ s/N==1
↑ s/N==0
↑ s/V==1
↑ s/V==0
↑ s/V xor N==1
↑ s/V xor N==0
↑ s/(V xor N) or Z==1
↑ s/(V xor N) or Z==0
↑ s/C or Z==1
↑ s/C or Z==0
Notes:
•
"2/1" under CYCLE indicates "2" cycles when branching occurs and "1" cycle when branching does not occur.
•
In the rel11 and rel8 fields of the hardware specifications, the assembler calculates values and sets them as shown below:
(label12-PC-2)/2->rel11, (label9-PC-2)/2->rel8, label12 and label9 have a sign.
•
To execute the RETI instruction, the S flag must be set to "0".
647
APPENDIX
Appendix Table E-12 Delayed Branch
Mnemonic
Type
OP
CYCLE
NZVC
JMP:D @Ri
CALL:D label12
CALL:D @Ri
RET:D
BRA:D label9
BNO:D label9
BEQ:D label9
E
F
E
E
D
D
D
9F-0
D8
9F-1
9F-2
F0
F1
F2
1
1
1
1
1
1
1
----------------------
BNE:D label9
BC:D label9
BNC:D label9
BN:D label9
BP:D label9
BV:D label9
BNV:D label9
BLT:D label9
BGE:D label9
BLE:D label9
BGT:D label9
BLS:D label9
BHI:D label9
D
D
D
D
D
D
D
D
D
D
D
D
D
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
1
1
1
1
1
1
1
1
1
1
1
1
1
----------------------------------------
Operation
Remarks
Ri -> PC
PC+4->RP , PC+2+(label12-PC-2)->PC
PC+4->RP ,Ri->PC
RP -> PC
Return
PC+2+(label9-PC-2)->PC
No branch
if(Z==1) then
PC+2+(label9-PC-2)->PC
↑ s/Z==0
↑ s/C==1
↑ s/C==0
↑ s/N==1
↑ s/N==0
↑ s/V==1
↑ s/V==0
↑ s/V xor N==1
↑ s/V xor N==0
↑ s/(V xor N) or Z==1
↑ s/(V xor N) or Z==0
↑ s/C or Z==1
↑ s/C or Z==0
Notes:
• In the rel11 and rel8 fields of the hardware specifications, the assembler calculates values and sets them as shown below:
(label12-PC-2)/2->rel11, (label9-PC-2)/2->rel8, label12 and label9 have a sign.
• A delayed branch always occurs after the next instruction (delay slot) is executed.
• Instructions that can be placed in the delay slot are all 1-cycle, a-, b-, c-, and d-cycle instructions.
Multi-cycle instructions cannot be placed in the delay slot.
648
APPENDIX E Instruction Lists
Appendix Table E-13 Other Instructions
Mnemonic
Type
OP
CYCLE
NZVC
NOP
ANDCCR #u8
ORCCR #u8
STILM #u8
ADDSP #s10 *1
EXTSB Ri
EXTUB Ri
EXTSH Ri
EXTUH Ri
LDM0 (reglist)
E
D
D
D
D
E
E
E
E
D
9F-A
83
93
87
A3
97-8
97-9
97-A
97-B
8C
1
c
c
1
1
1
1
1
1
---cccc
cccc
----------------------
LDM1 (reglist)
D
8D
-------
*LDM (reglist)
*2
STM0 (reglist)
D
8E
----
STM1 (reglist)
D
8F
-------
*STM (reglist)
*3
D
0F
1+a
----
LEAVE
E
9F-9
b
----
XCHB @Rj, Ri
A
8A
2a
----
ENTER #u10
*4
Operation
No change
CCR and u8 -> CCR
CCR or u8 -> CCR
i8 -> ILM
R15 += s10
Sign extension 8->32bit
Zero extension 8->32bit
Sign extension 16->32bit
Zero extension 16->32bit
(R15)->reglist,
R15 increment
(R15)->reglist,
R15 increment
(R15)->reglist,
R15 increment
R15 decrement
reglist->(R15)
R15 decrement
reglist->(R15)
R15 decrement
reglist->(R15)
R14 -> (R15 - 4),
R15 - 4 -> R14,
R15 - u10 -> R15
R14 + 4 -> R15,
(R15 - 4) -> R14
Ri -> TEMP
(Rj) -> Ri
TEMP -> (Rj)
RMW
-
Remarks
ILM Immediate set
ADD SP instruction
Load multi R0-R7
-
Load multi R8-R15
-
Load multi R0-R15
-
Store multi R0-R7
-
Store multi R8-R15
-
Store multi R0-R15
-
Entry processing of a
function
-
Exit processing of a
function
For semaphore
management
Byte data
❍
*1: For s10, the assembler calculates s10/4 and then changes to s8 to set a value. s10 has a sign.
*2: If any of R0 to R7 is specified in reglist, LDM0 is generated, and if any of R8 to R15 is specified, LDM1 is generated.
In some cases, both LDM0 and LDM1 are generated.
*3: If any of R0 to R7 is specified in reglist, STM0 is generated, and if any of R8 to R15 is specified, STM1 is generated. In
some cases, both STM0 and STM1 are generated.
*4: For u10, the assembler calculates u10/4 and then changes to u8 to set a value. u10 has no sign.
Notes:
• The number of execution cycles of LDM0(reglist) and LDM1(reglist) can be calculated as a × (n-1)+b+1 cycles if the
number of specified registers is n.
• The number of execution cycles of STM0(reglist) and STM1(reglist) can be calculated as a × n+1 cycles if the number of
specified registers is n.
649
APPENDIX
Appendix Table E-14 20-Bit Normal Branch Macro Instruction
Mnemonic
Operation
*CALL20 label20,Ri
Address of the next instruction ->RP,
label20->PC
label20->PC
if(Z==1) then label20->PC
↑ s/Z==0
↑ s/C==1
↑ s/C==0
↑ s/N==1
↑ s/N==0
↑ s/V==1
↑ s/V==0
↑ s/V xor N==1
↑ s/V xor N==0
↑ s/(V xor N) or Z==1
↑ s/(V xor N) or Z==0
↑ s/C or Z==1
↑ s/C or Z==0
*BRA20 label20,Ri
*BEQ20 label20,Ri
*BNE20 label20,Ri
*BC20 label20,Ri
*BNC20 label20,Ri
*BN20 label20,Ri
*BP20 label20,Ri
*BV20 label20,Ri
*BNV20 label20,Ri
*BLT20 label20,Ri
*BGE20 label20,Ri
*BLE20 label20,Ri
*BGT20 label20,Ri
*BLS20 label20,Ri
*BHI20 label20,Ri
Remarks
Ri: Temporary register (See Reference 1)
Ri: Temporary register (See Reference 2)
Ri: Temporary register (See Reference 3)
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
[Reference 1] CALL20
(1) If label20-PC-2 is between -0x800 and +0x7fe, the following instruction will be generated:
CALL label12
(2) If label20-PC-2 is outside the range of (1) or contains an external reference symbol, the following instruction will be
generated:
LDI:20 #label20,Ri
CALL @Ri
[Reference 2] BRA20
(1) If label20-PC-2 is between -0x100 and +0xfe, the following instruction will be generated:
BRA label9
(2) If label20-PC-2 is outside the range of (1) or contains an external reference symbol, the following instruction will be
generated:
LDI:20 #label20,Ri
JMP @Ri
[Reference 3] Bcc20
(1) If label20-PC-2 is between -0x100 and +0xfe, the following instruction will be generated:
Bcc label9
(2) If label20-PC-2 is outside the range of (1) or contains an external reference symbol, the following instruction will be
generated:
Bxcc false
xcc is the opposite condition of cc.
LDI:20 #label20,Ri
JMP @Ri
false:
650
APPENDIX E Instruction Lists
Appendix Table E-15 20-Bit Delayed Branch Macro Instruction
Mnemonic
Operation
*CALL20:D label20,Ri
*BRA20:D label20,Ri
*BEQ20:D label20,Ri
*BNE20:D label20,Ri
*BC20:D label20,Ri
*BNC20:D label20,Ri
*BN20:D label20,Ri
*BP20:D label20,Ri
*BV20:D label20,Ri
*BNV20:D label20,Ri
*BLT20:D label20,Ri
*BGE20:D label20,Ri
*BLE20:D label20,Ri
*BGT20:D label20,Ri
*BLS20:D label20,Ri
*BHI20:D label20,Ri
Address of the next instruction +2->RP,
label20->PC
label20->PC
if(Z==1) then label20->PC
↑ s/Z==0
↑ s/C==1
↑ s/C==0
↑ s/N==1
↑ s/N==0
↑ s/V==1
↑ s/V==0
↑ s/V xor N==1
↑ s/V xor N==0
↑ s/(V xor N) or Z==1
↑ s/(V xor N) or Z==0
↑ s/C or Z==1
↑ s/C or Z==0
Remarks
RRi: Temporary register (See Reference 1)
Ri: Temporary register (See Reference 2)
Ri: Temporary register (See Reference 3)
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
[Reference 1] CALL20:D
(1) If label20-PC-2 is between -0x800 and +0x7fe, the following instruction will be generated:
CALL:D label12
(2) If label20-PC-2 is outside the range of (1) or contains an external reference symbol, the following instruction will be
generated:
LDI:20 #label20,Ri
CALL:D @Ri
[Reference 2] BRA20:D
(1) If label20-PC-2 is between -0x100 and +0xfe, the following instruction will be generated:
BRA:D label9
(2) If label20-PC-2 is outside the range of (1) or contains an external reference symbol, the following instruction will be
generated:
LDI:20 #label20,Ri
JMP:D @Ri
[Reference 3] Bcc20:D
(1) If label20-PC-2 is between -0x100 and +0xfe, the following instruction will be generated:
Bcc:D label9
(2) If label20-PC-2 is outside the range of (1) or contains an external reference symbol, the following instruction will be
generated:
Bxcc false
xcc is the opposite condition of cc.
LDI:20 #label20,Ri
JMP:D @Ri
false:
651
APPENDIX
Appendix Table E-16 32-Bit Normal Branch Macro Instruction
Mnemonic
Operation
*CALL32 label32,Ri
Address of the next instruction ->RP,
label32->PC
label32->PC
if(Z==1) then label32->PC
↑ s/Z==0
↑ s/C==1
↑ s/C==0
↑ s/N==1
↑ s/N==0
↑ s/V==1
↑ s/V==0
↑ s/V xor N==1
↑ s/V xor N==0
↑ s/(V xor N) or Z==1
↑ s/(V xor N) or Z==0
↑ s/C or Z==1
↑ s/C or Z==0
*BRA32 label32,Ri
*BEQ32 label32,Ri
*BNE32 label32,Ri
*BC32 label32,Ri
*BNC32 label32,Ri
*BN32 label32,Ri
*BP32 label32,Ri
*BV32 label32,Ri
*BNV32 label32,Ri
*BLT32 label32,Ri
*BGE32 label32,Ri
*BLE32 label32,Ri
*BGT32 label32,Ri
*BLS32 label32,Ri
*BHI32 label32,Ri
Remarks
Ri: Temporary register (See Reference 1)
Ri: Temporary register (See Reference 2)
Ri: Temporary register (See Reference 3)
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
[Reference 1] CALL32
(1) If label32-PC-2 is between -0x800 and +0x7fe, the following instruction will be generated:
CALL label12
(2) If label32-PC-2 is outside the range of (1) or contains an external reference symbol, the following instruction will be
generated:
LDI:32 #label32,Ri
CALL @Ri
[Reference 2] BRA32
(1) If label32-PC-2 is between -0x100 and +0xfe, the following instruction will be generated:
BRA label9
(2) If label32-PC-2 is outside the range of (1) or contains an external reference symbol, the following instruction will be
generated:
LDI:32 #label32,Ri
JMP @Ri
[Reference 3] Bcc32
(1) If label32-PC-2 is between -0x100 and +0xfe, the following instruction will be generated:
Bcc label9
(2) If label32-PC-2 is outside the range of (1) or contains an external reference symbol, the following instruction will be
generated:
Bxcc false
xcc is the opposite condition of cc.
LDI:32 #label32,Ri
JMP @Ri
false:
652
APPENDIX E Instruction Lists
Appendix Table E-17 32-Bit Delayed Branch Macro Instruction
Mnemonic
Operation
*CALL32D label32,Ri
Address of the next instruction +2->RP,
label32->PC
label32->PC
if(Z==1) then label32->PC
↑ s/Z==0
↑ s/C==1
↑ s/C==0
↑ s/N==1
↑ s/N==0
↑ s/V==1
↑ s/V==0
↑ s/V xor N==1
↑ s/V xor N==0
↑ s/(V xor N) or Z==1
↑ s/(V xor N) or Z==0
↑ s/C or Z==1
↑ s/C or Z==0
*BRA32:D label32,Ri
*BEQ32:D label32,Ri
*BNE32:D label32,Ri
*BC32:D label32,Ri
*BNC32:D label32,Ri
*BN32:D label32,Ri
*BP32:D label32,Ri
*BV32:D label32,Ri
*BNV32:D label32,Ri
*BLT32:D label32,Ri
*BGE32:D label32,Ri
*BLE32:D label32,Ri
*BGT32:D label32,Ri
*BLS32:D label32,Ri
*BHI32:D label32,Ri
Remarks
Ri: Temporary register (See Reference 1)
Ri: Temporary register (See Reference 2)
Ri: Temporary register (See Reference 3)
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
[Reference 1] CALL32:D
(1) If label32-PC-2 is between -0x800 and +0x7fe, the following instruction will be generated:
CALL:D label12
(2) If label32-PC-2 is outside the range of (1) or contains an external reference symbol, the following instruction will be
generated:
LDI:32 #label32,Ri
CALL:D @Ri
[Reference 2] BRA32:D
(1) If label32-PC-2 is between -0x100 and +0xfe, the following instruction will be generated:
BRA:D label9
(2) If label32-PC-2 is outside the range of (1) or contains an external reference symbol, the following instruction will be
generated:
LDI:32 #label32,Ri
JMP:D @Ri
[Reference 3] Bcc32:D
(1) If label32-PC-2 is between -0x100 and +0xfe, the following instruction will be generated:
Bcc:D label9
(2) If label32-PC-2 is outside the range of (1) or contains an external reference symbol, the following instruction will be
generated:
Bxcc false
xcc is the opposite condition of cc.
LDI:32 #label32,Ri
JMP:D @Ri
false:
653
APPENDIX
Appendix Table E-18 Direct Addressing
Mnemonic
DMOV @dir10, R13
DMOV R13, @dir10
DMOV @dir10, @R13+
DMOV @R13+, @dir10
DMOV @dir10, @-R15
DMOV @R15+, @dir10
DMOVH @dir9, R13
DMOVH R13, @dir9
DMOVH @dir9, @R13+
DMOVH @R13+, @dir9
DMOVB @dir8, R13
DMOVB R13, @dir8
DMOVB @dir8, @R13+
DMOVB @R13+, @dir8
Type
OP
CYCLE
NZVC
D
D
D
D
D
D
D
D
D
D
D
D
D
D
08
18
0C
1C
0B
1B
09
19
0D
1D
0A
1A
0E
1E
b
a
2a
2a
2a
2a
b
a
2a
2a
b
a
2a
2a
-------------------------------------------
Operation
Remarks
(dir10)-> R13
R13 ->(dir10)
(dir10)->(R13),R13+=4
(R13)->(dir10),R13+=4
R15-=4,(R15)->(dir10)
(R15)->(dir10),R15+=4
(dir9)-> R13
R13 ->(dir9)
(dir9)->(R13),R13+=2
(R13)->(dir9),R13+=2
(dir8)-> R13
R13 ->(dir8)
(dir8)->(R13),R13++
(R13)->(dir8),R13++
Word
Word
Word
Word
Word
Word
Halfword
Halfword
Halfword
Halfword
Byte
Byte
Byte
Byte
Note: In the dir8, dir9, and dir10 fields, the assembler calculates values and sets them as shown below:
dir8->dir, dir9/2->dir, dir10/4->dir dir8, dir9, and dir10 have no sign.
Appendix Table E-19 Resource Instruction
Mnemonic
Type
OP
CYCLE
NZVC
LDRES @Ri+, #u4
C
BC
a
----
STRES #u4, @Ri+
C
BD
a
----
Operation
(Ri) -> Resource of u4
Ri+=4
Resource of u4->(Ri)
Ri+=4
Remarks
u4: Channel No.
u4: Channel No.
Note: These instructions cannot be used in this MB91245/S series since resource having channel number is not installed.
Appendix Table E-20 Coprocessor Control Instruction
{CRi|CRj} := CR0 | CR1 | CR2 | CR3 | CR4 | CR5 | CR6 | CR7 | CR8 | CR9 | CR10 | CR11 | CR12 | CR13 | CR14 | | CR15
u4: := Specify channel
u8: := Specify instruction
COPOP
COPLD
COPST
COPSV
Mnemonic
Type
OP
CYCLE
NZVC
#u4, #u8, CRj, CRi
#u4, #u8, Rj, CRi
#u4, #u8, CRj, Ri
#u4, #u8, CRj, Ri
E
E
E
E
9F-C
9F-D
9F-E
9F-F
2+a
1+2a
1+2a
1+2a
-------------
Operation
Note: These instructions cannot be used in this MB91245/S series since coprocessor is not installed.
654
Remarks
Operation instruction
Rj -> CRi
No error stop
CRj -> Ri
CRj -> Ri
APPENDIX F Notes on Handling
APPENDIX F Notes on Handling
This appendix shows precautions on handling.
■ Common Items
● Clock controller
When inputting "L" to INITX, the oscillation stabilization wait time must be secured.
● Switching functions between port and pin
When a port serves both as a port and a pin, port and pin functions are switched by PFR (Port Function
Register). However, a bus pin is switched by external bus settings.
Note: External bus mode is not supported by the MB91245/S series.
● D-bus memory
Do not set the code area in the D-bus memory.
No instruction fetch to the D-bus memory is executed. If instruction fetch to the D-bus memory is
executed, incorrect data will be interpreted as a code, causing a runaway condition.
● Low-power consumption mode
(1) To switch to standby mode, use synchronous standby mode (set by the SYNCS bit, that is bit8 of the
TBCR, time-base counter control register) and be sure to use the following sequence:
/* Writing STCR */
ldi
#_STCR, R0
; STCR register (0x0481)
ldi
#Val_of_Stby, rl
; Val_of_Stby is the write data to STCR.
stb
rl,@r0
; Writing to STCR
/* Writing STBR */
ldi
#_CTBR, r2
; CTBR register (0x0483)
ldi
#0xA5, rl
; Clear instruction (1)
stb
rl,@r2
; Writing A5 to CTBR
ldi
#0xA5, rl
; Clear instruction (2)
stb
rl,@r2
; Writing A5 to CTBR
/* Clearing the time-base counter in here */
ldub
@r0, rl
; Reading STCR
/* Starting synchronous standby transition */
ldub
nop
@r0, rl
; Reading dummy STCR
; NOP × 5 for timing adjustment
nop
nop
nop
nop
655
APPENDIX
(2) When using the monitor debugger, DO NOT:
- Set a break point within the above sequence of instructions.
- Execute step within the above sequence of instructions.
● Notes on using PS register
PS register is processed by some instructions in advance so that exception operations as stated below may
cause breaks during interruption processing routine when using debugger and may cause updates to the
display contents of PS flags.
In either case, this device is designed to carry out reprocessing properly after returning from such EIT
events. The operations before and after the events are performed as prescribed in the specification.
1. If the instruction immediately before DIV0U/DIV0S instruction (a) receives a user interrupt/NMI, (b)
executes stepping or (c) breaks by data event or emulator menu, the following operations may be
performed.
(1) D0 and D1 flags are updated in advance.
(2) EIT handling routine (user interrupt/NMI, or emulator) is executed.
(3) After returning from the EIT, DIV0U/DIV0S instruction is executed and the D0 and D1 flags are
updated to the same values as in (1).
2. The following operations are performed if each instruction from OR CCR, ST ILM, MOV Ri and PS is
executed to allow an interruption while user interrupt/NMI trigger exists.
(1) PS register is updated in advance.
(2) EIT handling routine (user interrupt/NMI) is executed.
(3) After returning from the EIT, the above instructions are executed and the PS register is updated to
the same value as in (1).
● Watchdog timer function
The watchdog timer equipped in this product operates to monitor programs to ensure that they execute reset
defer function within a certain period of time and to reset the CPU if the reset defer function is not executed
due to the program runaway. Therefore, once the watchdog timer function is enabled, it keeps its operation
until it is reset.
By way of exception, the watchdog timer automatically defers a reset under the conditions where the CPU
program executions are stopped. For more detail about such conditions, refer to "■ RSRR: Reset Factor
Register/Watchdog Timer Control Register" of section "3.12.7 Detailed Description of Register of Clock
Generation Control Unit".
656
APPENDIX F Notes on Handling
■ Notes on Using Debugger
● Stepping of the RETI instruction
In the environment where interruptions occur frequently during stepping, the RETI is executed repeatedly
for the corresponding interrupt processing routines after the stepping. As the result of it, the main routine
and low-interrupt-level programs are not executed.
To avoid this situation, do not step the RETI instruction. Otherwise, perform debugging by disabling the
interruptions when the debug on the corresponding interrupt routines becomes unnecessary.
● Operand break
Do not set the access to the areas containing the address of system stack pointer as a target of data event
break.
● Debugging on unused area of FLASH memory
If debug is performed on the unused area of FLASH memory (where data is FFFFH) by mistake, break will
not be accepted. To avoid this situation, the use of address mask function of debugger code event is
recommended to break when an instruction is accessing to the unused area.
● Power-on debug
When powering off by the power-on debug, be sure to power off under the condition that all the following
three requirements are met.
(1) Time taken to decrease user power supply from 0.9 VCC to 0.5 VCC is 25 µs or more.
Note: If using two power supplies, VCC is external I/O power supply voltage.
(2) CPU operating frequency is 1 MHz or higher.
(3) User program is in execution.
● Interrupt handler for NMI request (tool)
When ICE is unconnected, to prevent the malfunction caused by noise or other sources affecting DSU pin
to set a flag which is only set by the break request from ICE, add the following programs to the interrupt
handler.
ICE can be used even if this program is added.
Location to add
The following interrupt handler
Interrupt factor
: NMI request (tool)
Interrupt No.
: 13 (decimal), 0D (hexadecimal)
Offset
: 3C8H
TBR as a default address
: 000FFFC8H
Additional program
STM
(R0, R1)
LDI
#B00H, R0
LDI
#0, R1
STB
R1, @R0
LDM
(R0, R1)
; B00H is the address of break factor register of DSU.
; Clear break factor register.
RETI
657
APPENDIX
658
INDEX
INDEX
The index follows on the next page.
This is listed in alphabetic order.
659
INDEX
Index
Numerics
A
1/2 Duty Cycle Output Mode
Output Wave Forms during LCD Controller Driver
Operation (1/2 Duty Cycle Output Mode)
.......................................................... 528
1/3 Duty Cycle Output Mode
Output Wave Forms during LCD Controller Driver
Operation (1/3 Duty Cycle Output Mode)
.......................................................... 530
1/4 Duty Cycle Output Mode
Output Wave Forms during LCD Controller Driver
Operation (1/4 Duty Cycle Output Mode)
.......................................................... 532
16-bit Free-run Timer
16-bit Free-run Timer Clear Timing ................... 233
16-bit Free-run Timer Count Timing .................. 233
Block Diagram of 16-bit Free-run Timer ............ 227
Description of 16-bit Free-run Timer Operations
.......................................................... 232
Features of 16-bit Free-run Timer ...................... 226
Notes of 16-bit Free-run Timer .......................... 234
Register List of 16-bit Free-run Timer ................ 226
16-Bit Input Capture
16-Bit Input Capture Input Timing..................... 242
16-bit Output Compare
Operation Timing of 16-bit Output Compare....... 251
16-bit Reload Register
16-bit Reload Register (TMRLR)....................... 173
16-bit Timer Register
16-bit Timer Register (TMR)............................. 173
32kHz Clock Correction Unit
Block Diagram of the 32kHz Clock Correction Unit
.......................................................... 536
Clock Timing of 32kHz Clock Correction Unit
.......................................................... 537
Timing of 32kHz Clock Correction Unit............. 537
32kHz Timer Data Register
32kHz Timer Data Register (16-bit) (CUTD) ...... 541
32kHz Timer Data Register Configuration.......... 543
4MHz Timer Data Register
4MHz Timer Data Register (24-bit) (CUTR)....... 542
8-bit PPG
8-bit PPG ch.0,ch.2,ch.4,ch.6 Block Diagram...... 183
8-bit PPG ch.1,ch.5 Block Diagram.................... 184
8-bit PPG ch.3,ch.7 Block Diagram.................... 185
A/D Control Status Register
A/D Control Status Register (ADCS0) ............... 438
A/D Control Status Register (ADCS1) ............... 436
A/D Conversion Time Setting Register
A/D Conversion Time Setting Register
(ADCT0,ADCT1) ............................... 440
A/D Converter
A/D Converter Block Diagram .......................... 431
A/D Converter Operations ................................ 444
A/D Converter Overview .................................. 430
A/D Converter Register List.............................. 433
Features of the A/D Converter........................... 430
A/D Start/End Channel Setting Register
A/D Start/End Channel Setting Register
(ADSCH,ADECH).............................. 442
Accept
Accept and Transfer the Transfer Request .......... 325
Access
Basic Timing (When there is Consecutive Access)
(TYP[3:0]=0000B,AWR=0008H).......... 284
Bus Access...................................................... 277
Data Access....................................................... 42
External Access ............................................... 280
Program Access ................................................. 42
ACR
ACR0 to ACR3 (Area Configuration Register)
......................................................... 266
ADCR
Data Register (ADCR0,ADCR1) ....................... 440
ADCS
A/D Control Status Register (ADCS0) ............... 438
A/D Control Status Register (ADCS1) ............... 436
ADCT
A/D Conversion Time Setting Register
(ADCT0,ADCT1) ............................... 440
Addressing
Direct Addressing Area ................................ 43, 24
ADSCH
A/D Start/End Channel Setting Register
(ADSCH,ADECH).............................. 442
AF200 Flash Microcontroller Programmer
Configuration of the AF200 Flash Microcontroller
Programmer System (Manufactured by
Yokogawa Digital Computer Corporation)
......................................................... 604
Algorithm
Execution Status of Auto Algorithm .................. 554
660
INDEX
Amplitude Data Register
Amplitude Data Register Bit Configuration ........ 354
Analog Input Enable Registers
Analog Input Enable Registers .......................... 435
Architecture
Internal Architecture .......................................... 29
Area Configuration Register
ACR0 to ACR3 (Area Configuration Register)
.......................................................... 266
Area Select Register
ASR0 to ASR3 (Area Select Register) ............... 265
Area Wait Register
AWR0 to AWR3 (Area Wait Register) .............. 270
ASR
ASR0 to ASR3 (Area Select Register) ............... 265
Assembler
Assembler (fasm911) ....................................... 636
Asynchronous
Basic Structure of Serial Writing (Asynchronous) in
the MB91F24x/S................................. 605
Auto Algorithm
Execution Status of Auto Algorithm .................. 554
Automatic Wait Timing
Automatic Wait Timing
(TYP[3:0]=0000B,AWR=2008H).......... 287
AWR
Automatic Wait Timing
(TYP[3:0]=0000B,AWR=2008H).......... 287
AWR0 to AWR3 (Area Wait Register) .............. 270
Basic Timing (When there is Consecutive Access)
(TYP[3:0]=0000B,AWR=0008H).......... 284
CSX Delay Setting (TYP[3:0]=0000B,AWR=000CH)
.......................................................... 289
CSX→ RDX/WRX Setup,RDX/WRnX→ CSX Hold
Setting (TYP[3:0]=0000B,AWR=000BH)
.......................................................... 290
External Wait Timing
(TYP[3:0]=0001B,AWR=2008H).......... 288
ReadÆWrite Timing
(TYP[3:0]=0000B,AWR=0048H).......... 285
WriteÆWrite Timing
(TYP[3:0]=0000B,AWR=0018H).......... 286
B
Base Clock Divide
DIVR1: Base Clock Divide Setting Register 1
.......................................................... 100
Base Clock Divide Setting Register
DIVR0: Base Clock Divide Setting Register 0 ...... 98
Basic Block Diagram
Basic Block Diagram of the Port ....................... 114
Basic Configuration
Basic Configuration for Serial Programming in the
MB91F24x/S ...................................... 594
Basic Programming Model
Basic Programming Model ..................................33
Basic Structure
Basic Structure of Serial Writing (Asynchronous) in
the MB91F24x/S .................................605
Basic Timing
Basic Timing (When there is Consecutive Access)
(TYP[3:0]=0000B,AWR=0008H) ..........284
Baud Rate
Baud Rate Calculation.......................................259
Calculating Baud Rate.......................................398
Example Baud Rate Setting for Each Machine Clock
Frequency ...........................................399
Selecting Baud Rate for UART ..........................397
Baud Rate/Reload Counter Register
Baud Rate/Reload Counter Register (BGR).........395
Baud Rates
Detecting Baud Rates with the Input Capture ......396
BGR
Baud Rate/Reload Counter Register (BGR).........395
Bit Configuration
Amplitude Data Register Bit Configuration.........354
Bit Configuration of Interrupt Control Register (ICR)
..........................................................136
Bit Configuration of Serial Status Register (SSR) 374
Frequency Data Register Bit Configuration .........355
PWM Control Register Bit Configuration ...........342
Sound Control Register Bit Configuration...........352
Tone Count Register Bit Configuration...............356
Bit Configuration of Serial Control Register (SCR)
..........................................................371
Bit Configuration of Serial Mode Register (SMR)
..........................................................369
Bit Ordering
Bit Ordering .......................................................41
Block Diagram
8-bit PPG ch.0,ch.2,ch.4,ch.6 Block Diagram
..........................................................183
8-bit PPG ch.1,ch.5 Block Diagram ....................184
8-bit PPG ch.3,ch.7 Block Diagram ....................185
A/D Converter Block Diagram...........................431
Basic Block Diagram of the Port ........................114
Block Diagram .....................................5, 158, 160
Block Diagram of 16-bit Free-run Timer.............227
Block Diagram of Clock Generation Control Unit
............................................................86
Block Diagram of DMAC .................................296
Block Diagram of External Bus Interface ............263
Block Diagram of External Interrupt Controller ...148
Block Diagram of External Reset Pin ...................71
Block Diagram of Input Capture ........................238
Block Diagram of Interrupt Controller ................135
Block Diagram of LCD Controller .....................519
Block Diagram of Main Oscillation Stabilization Wait
Timer .................................................219
661
INDEX
Block Diagram of Output Compare.................... 245
Block Diagram of Real Time Clock ................... 360
Block Diagram of the 32kHz Clock Correction Unit
.......................................................... 536
Block Diagram of the C_CAN ........................... 448
Block Diagram of the Stepper Motor Controller .. 340
Block Diagram of UART .................................. 368
Block Diagram of U-Timer ............................... 255
CPU Operation Detection Reset Circuit Block
Diagram ............................................. 547
FLASH Memory Block Diagram ....................... 555
PWC Block Diagram ........................................ 197
Sound Generator Block Diagram ....................... 350
Block Diagrams
LIN-UART Block Diagrams ............................. 387
Block Transfer
Block Transfer ......................................... 334, 317
Step/Block Transfer Two-cycle Transfer ............ 317
Break Detection Interrupt
LIN Synch Break Detection Interrupt and Flags
.......................................................... 418
Break Interrupt
LIN Synch Break Interrupt ................................ 413
BRPER
CAN Prescaler Extended Register (BRPER) ....... 469
BTR
CAN Bit Timing Register (BTR) ....................... 465
Built-in Peripheral
Built-in Peripheral Request ............................... 315
Burst Transfer
Burst Transfer .................................................. 335
Burst Two-cycle Transfer
Burst Two-cycle Transfer.................................. 316
Bus Access
Bus Access ...................................................... 277
Bus Converter
32-bit´16-bit Bus Converter................................. 30
Harvard´Princeton Bus Converter ........................ 31
Bus Idle Interrupt
Bus Idle Interrupt ............................................. 413
Bus Idle Interrupt and Flags .............................. 419
Bus Mode
Bus Mode .......................................................... 62
Busy Signal
Ready/Busy Signal (RDY/BUSYX) ................... 575
BUSYX
Ready/Busy Signal (RDY/BUSYX) ................... 575
Byte Ordering
Byte Ordering .................................................... 41
C
C Compiler
C Compiler (fcc911)......................................... 633
662
C_CAN
Block Diagram of the C_CAN .......................... 448
Features of the C_CAN .................................... 448
CAN
CAN Clock Prescaler ....................................... 514
CAN Register Types ........................................ 450
CAN Bit Timing Register
CAN Bit Timing Register (BTR) ....................... 465
CAN Clock Prescaler
CAN Clock Prescaler ....................................... 514
CAN Control Register
CAN Control Register (CTRLR) ....................... 458
CAN Error Counter
CAN Error Counter (ERRCNT) ........................ 464
CAN Interrupt Pending Register
CAN Interrupt Pending Register
(INTPND1,INTPND2) ........................ 494
CAN Interrupt Register
CAN Interrupt Register (INTR)......................... 466
CAN Message Valid Register
CAN Message Valid Register
(MSGVAL1,MSGVAL2) .................... 496
CAN New Data Register
CAN New Data Register 1,2 (NEWDT1,NEWDT2)
......................................................... 492
CAN Prescaler Extended Register
CAN Prescaler Extended Register (BRPER)....... 469
CAN Prescaler Register
CAN Prescaler Register .................................... 498
CAN Status Register
CAN Status Register (STATR).......................... 461
CAN Test Register
CAN Test Register (TESTR)............................. 467
CAN Transmission Request Register
CAN Transmission Request Register
(TREQR1,TREQR2) ........................... 490
CCR
CCR (Condition Code Register) .......................... 35
Channel Group
Channel Group ................................................ 333
Chip
Erasing Data from the FLASH Memory (Erase Chip)
......................................................... 583
Chip Select Enable Register
CSER (Chip Select Enable Register).................. 274
CLKB
CPU Clock (CLKB) ........................................... 84
CLKP
Peripheral Clock (CLKP).................................... 84
CLKR
CLKR: Clock Source Control Register................. 94
CLKT
External Bus Clock (CLKT)................................ 84
INDEX
Clock
Block Diagram of the 32kHz Clock Correction Unit
.......................................................... 536
CAN Clock Prescaler ....................................... 514
Clock Division................................................... 85
Clock Supply................................................... 404
Clock Supply Function Operations .................... 223
Clock Synchronization ..................................... 415
Clock Timing of 32kHz Clock Correction Unit ... 537
Continuous Serial Clock Output ........................ 421
Count Clock Selection ...................................... 205
CPU Clock (CLKB) ........................................... 84
Example Baud Rate Setting for Each Machine Clock
Frequency .......................................... 399
Example of Switching between the Main Clock´the
Sub Clock .......................................... 224
External Bus Clock (CLKT)................................ 84
External Clock................................................. 376
Frame Interval Generation Clock Selection......... 527
Internal Clock Operations ................................. 174
Original Oscillation Clock Frequency ................ 604
Peripheral Clock (CLKP).................................... 84
Sampling Clock Edge ....................................... 420
Selecting a UART Clock .................................. 376
Timing of 32kHz Clock Correction Unit ............ 537
Using External Clock ....................................... 400
Clock Correction Unit
Block Diagram of the 32kHz Clock Correction Unit
.......................................................... 536
Clock Timing of 32kHz Clock Correction Unit
.......................................................... 537
Timing of 32kHz Clock Correction Unit ............ 537
Clock Disable Register
Clock Disable Register (WTDBL) ..................... 362
Clock Division
Clock Division................................................... 85
Clock Generation Control
Block Diagram of Clock Generation Control Unit
............................................................ 86
Clock Generation Control ................................... 78
Clock Prescaler Register
Clock Prescaler Register ................................... 457
Clock Source Control Register
CLKR: Clock Source Control Register................. 94
Clock Supply Function
Clock Supply Function Operations .................... 223
Clock Synchronization
Clock Synchronization ..................................... 415
Common Pin Selection Register
Common Pin Selection Register (LCDCMR)...... 521
Communication
Communication Method ................................... 405
LIN Master-Slave Communication Function....... 422
Compare Register
Compare Register (OCCP)................................ 246
Compare Registers
PWM1 and PWM2 Compare Registers Functions
..........................................................343
Compiler
C Compiler (fcc911) .........................................633
Components
Components of Each Product .................................4
Hardware Components of Interrupt Controller
..........................................................132
Sound Generator Components............................350
Condition Code Register
CCR (Condition Code Register) ...........................35
Configuration
Basic Configuration for Serial Programming in the
MB91F24x/S.......................................594
Connection
Example of Minimum Connection with Flash
Microcontroller Programmer (When Power
is Supplied from Writer).......................602
Example of Minimum Connection with Flash
Microcontroller Programmer (When User
Power Supply is Used) .........................600
Example of Serial Writing Connection (When Power
is Supplied from the Flash Microcontroller
Programmer) .......................................598
Example of Serial Writing Connection (When User
Power Supply is Used) .........................596
Consecutive Access
Basic Timing (When there is Consecutive Access)
(TYP[3:0]=0000B,AWR=0008H) ..........284
Continuous Mode
Continuous Mode .............................................444
Continuous Serial Clock
Continuous Serial Clock Output .........................421
Control Status Register
Control Status Register (TMCSR) ......................170
Control/Status Register
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Control/Status
Register A [DMACA0 to DMACA4]
..........................................................297
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Control/Status
Register B [DMACB0 to DMACB4]
..........................................................302
Correction Unit
About the Correction Unit .................................536
Block Diagram of the 32kHz Clock Correction Unit
..........................................................536
Clock Timing of 32kHz Clock Correction Unit
..........................................................537
Register List of the Correction Unit ....................538
Timing of 32kHz Clock Correction Unit .............537
Correction Unit Control Register
Correction Unit Control Register (CUCR)...........539
Count Clock
Count Clock Selection.......................................205
663
INDEX
Count Control Register
Count Control Register and Reload Operation
.......................................................... 322
CPU
CPU.................................................................. 30
CPU Clock (CLKB) ........................................... 84
FR60Lite CPU ..................................................... 2
CPU Clock
CPU Clock (CLKB) ........................................... 84
CPU Operation Detection Reset Circuit
CPU Operation Detection Reset Circuit.............. 546
CPU Operation Detection Reset Circuit Block
Diagram ............................................. 547
CPU Operation Detection Reset Circuit Operation
.......................................................... 550
Notes on Using the CPU Operation Detection Reset
Circuit ................................................ 551
CPU Operation Detection Reset Control Register
CPU Operation Detection Reset Control Register
(LVRC) .............................................. 548
CSER
CSER (Chip Select Enable Register) .................. 274
CSX
CSX→ RDX/WRX Setup,RDX/WRnX→ CSX Hold
Setting (TYP[3:0]=0000B,AWR=000BH)
.......................................................... 290
CSX Delay Setting
CSX Delay Setting (TYP[3:0]=0000B,AWR=000CH)
.......................................................... 289
CSX Hold Setting
CSX→ RDX/WRX Setup,RDX/WRnX→ CSX Hold
Setting (TYP[3:0]=0000B,AWR=000BH)
.......................................................... 290
CTBR
CTBR: Time-base Counter Clear Register ............ 93
CTRLR
CAN Control Register (CTRLR)........................ 458
CUCR
Correction Unit Control Register (CUCR) .......... 539
CUTD
32kHz Timer Data Register (16-bit) (CUTD) ...... 541
CUTR
4MHz Timer Data Register (24-bit) (CUTR)....... 542
Cycle Transfer
Two-cycle Data Flow During Cycle Transfer ...... 336
D
Data Access
Data Access ....................................................... 42
Data Bus Width
The Relationship between Data Bus Width and
Control Signals ................................... 276
664
Data Direction Register
Data Direction Register (DDR:DDR0 to DDRG)
......................................................... 119
Data Format
Data Format Setting ......................................... 409
Send/receive Data Format: ........................ 402, 404
Data Register
Data Register (ADCR0,ADCR1) ....................... 440
DDR
Data Direction Register (DDR:DDR0 to DDRG)
......................................................... 119
Debugger
Debugger (sim911,eml911,mon911) .................. 639
Notes on Using Debugger ................................. 657
Decrement Grade Register
Decrement Grade Register Functions ................. 357
Delay Slot
Operation with Delay Slot................................... 44
Delay Slots
Operation without Delay Slots............................. 46
Delayed Slot
Note on Delayed Slot ......................................... 61
Detection
CPU Operation Detection Reset Circuit ............. 546
CPU Operation Detection Reset Circuit Block
Diagram ............................................. 547
CPU Operation Detection Reset Circuit Operation
......................................................... 550
Error Detection ................................................ 404
LIN Synch Field Edge Detection Interrupt
................................................. 413, 418
Notes on Using the CPU Operation Detection Reset
Circuit ............................................... 551
Stop Bits,Error Detection,and Parity .................. 403
Device
Connecting LIN Device .................................... 422
Device Statuses and Individual Transitions......... 106
Devices
Handling Devices............................................... 20
Direct Access
Direct Access to the Serial Pin .......................... 408
Direct Addressing
Direct Addressing Area ................................ 43, 24
Divide Ratio Control Register
PDIVR (Divide Ratio Control Register) ............. 203
DIVR
DIVR0: Base Clock Divide Setting Register 0 ...... 98
DIVR1: Base Clock Divide Setting Register 1
......................................................... 100
DMA
Inhibit DMA.................................................... 323
DMA Interrupt Clear Register
DMA Interrupt Clear Register (DRCL) .............. 258
INDEX
DMA Transfer
DMA Transfer and Interrupt ............................. 323
DMAC
Block Diagram of DMAC ................................. 296
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Control/Status
Register A [DMACA0 to DMACA4]
.......................................................... 297
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Control/Status
Register B [DMACB0 to DMACB4]
.......................................................... 302
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Transfer-source/
Transfer-destination Address Setting
Register [DMASA0 to DMASA4/DMADA0
to DMADA4] ..................................... 308
Interrupts Enabling Output of DMAC Interrupt
Control............................................... 330
Overview of DMAC......................................... 312
Register Overview of DMAC ............................ 295
DMAC Total Control Register
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 DMAC Total Control
Register [DMACR] ............................. 310
DMACB
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Control/Status
Register B [DMACB0 to DMACB4]
.......................................................... 302
DMACR
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 DMAC Total Control
Register [DMACR] ............................. 310
DMADA
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Transfer-source/
Transfer-destination Address Setting
Register [DMASA0 to DMASA4/DMADA0
to DMADA4] ..................................... 308
DMASA
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Transfer-source/
Transfer-destination Address Setting
Register [DMASA0 to DMASA4/DMADA0
to DMADA4] ..................................... 308
DRCL
DMA Interrupt Clear Register (DRCL) .............. 258
Duty
Output Wave Forms during LCD Controller Driver
Operation (1/2 Duty Cycle Output Mode)
.......................................................... 528
Output Wave Forms during LCD Controller Driver
Operation (1/3 Duty Cycle Output Mode)
.......................................................... 530
Output Wave Forms during LCD Controller Driver
Operation (1/4 Duty Cycle Output Mode)
.......................................................... 532
E
ECCR
Extended Communication Control Register (ECCR)
.......................................................... 394
EIRR
External Interrupt Request Register (EIRR: External
Interrupt Request Register) ...................151
EIT
EIT (Exception,Interrupt,and Trap) ......................47
EIT Characteristics .............................................47
EIT Factors ........................................................47
EIT Vector Table................................................52
Interrupt Level of EIT .........................................48
Operation of EIT ................................................58
Priority for EIT Factor Acceptance.......................56
Return from EIT .................................................47
ELVR
External Interrupt Request Level Setting Register
(ELVR: External LeVel Register)..........152
eml911
Debugger (sim911,eml911,mon911)...................639
Endian
Endian Overview ..............................................276
ENIR
Interrupt Enabled Register (ENIR: ENable Interrupt
Request Register).................................150
Erase
Resuming Sector Erase in the FLASH Memory
..........................................................586
Suspending Sector Erase of the FLASH Memory
..........................................................586
Erase Chip
Erasing Data from the FLASH Memory (Erase Chip)
..........................................................583
Erase Sector
Erasing Data from FLASH Memory (Erase Sector)
..........................................................584
Erasing
Details on Writing/Erasing FLASH Memory.......581
Erasing Data from FLASH Memory (Erase Sector)
..........................................................584
Erasing Data from the FLASH Memory (Erase Chip)
..........................................................583
ERRCNT
CAN Error Counter (ERRCNT) .........................464
Error
Error Detection.................................................404
Stop Bits,Error Detection,and Parity ...................403
ESCR
Extended Status Control Register (ESCR)...........393
Exception
EIT (Exception,Interrupt,and Trap) ......................47
Extended Communication Control Register
Extended Communication Control Register (ECCR)
..........................................................394
Extended Status Control Register
Extended Status Control Register (ESCR)...........393
665
INDEX
External Access
External Access................................................ 280
External Bus Clock
External Bus Clock (CLKT) ................................ 84
External Bus Interface
Block Diagram of External Bus Interface............ 263
Features of External Bus Interface ..................... 262
Overview of External Bus Interface's Registers
.......................................................... 265
Register List of External Bus Interface ............... 264
External Clock
External Clock ................................................. 376
Using External Clock........................................ 400
External Interrupt
External Interrupt Operations ............................ 153
External Interrupt Request Levels ...................... 154
Notes If Restoring from STOP Status Performed
Using an External Interrupt .................. 155
Operation Procedure of External Interrupt .......... 153
External Interrupt Control
Details of Registers in External Interrupt Control
Block ................................................. 149
External Interrupt Controller
Block Diagram of External Interrupt Controller
.......................................................... 148
Register List of External Interrupt Controller ...... 148
External Interrupt Request Level Setting Register
External Interrupt Request Level Setting Register
(ELVR: External LeVel Register) ......... 152
External Interrupt Request Register
External Interrupt Request Register (EIRR: External
Interrupt Request Register)................... 151
External Reset Pin
Block Diagram of External Reset Pin ................... 71
External Wait Timing
External Wait Timing
(TYP[3:0]=0001B,AWR=2008H) .......... 288
F
fasm911
Assembler (fasm911)........................................ 636
fcc911
C Compiler (fcc911)......................................... 633
Fetch
Fetch Timing for Input Capture ......................... 241
Mode Fetch........................................................ 73
Field Edge Detection Interrupt
LIN Synch Field Edge Detection Interrupt
.................................................. 413, 418
FIFO Buffer
FIFO Buffer Function ....................................... 504
FLASH Memory
Details on Writing/Erasing FLASH Memory ...... 581
666
Erasing Data from FLASH Memory (Erase Sector)
......................................................... 584
Erasing Data from the FLASH Memory (Erase Chip)
......................................................... 583
FLASH Memory Block Diagram....................... 555
FLASH Memory Overview............................... 554
FLASH Memory Register List .......................... 564
Notes on Using the FLASH Memory ................. 587
Programming Data in FLASH Memory.............. 581
Relationship between the MBM29LV400C and the
FLASH Memory Control Signals ......... 570
Resuming Sector Erase in the FLASH Memory .. 586
Sector Structure of the FLASH Memory ............ 556
Setting the Read/Reset Status to the FLASH Memory
......................................................... 581
Suspending Sector Erase of the FLASH Memory 586
FLASH Memory Mode
FLASH Memory Mode .................................... 569
FLASH Memory Status Register
FLASH Memory Status Register (FLCR) ........... 565
Flash Microcontroller Programmer
Configuration of the AF200 Flash Microcontroller
Programmer System (Manufactured by
Yokogawa Digital Computer Corporation)
......................................................... 604
Example of Minimum Connection with Flash
Microcontroller Programmer (When Power
is Supplied from Writer) ...................... 602
Example of Minimum Connection with Flash
Microcontroller Programmer (When User
Power Supply is Used) ........................ 600
Example of Serial Writing Connection (When Power
is Supplied from the Flash Microcontroller
Programmer) ...................................... 598
FLASH Wait Register
FLASH Wait Register (FLWC) ......................... 566
FLCR
FLASH Memory Status Register (FLCR) ........... 565
flnk911
Linker (flnk911) .............................................. 638
FLWC
FLASH Wait Register (FLWC) ......................... 566
FR60Lite
FR60Lite CPU..................................................... 2
Frame Interval Generation Clock
Frame Interval Generation Clock Selection ........ 527
FR-CPU Programming Mode
FR-CPU Programming Mode (16-bit,Read/Write)
......................................................... 568
FR-CPU ROM Mode
FR-CPU ROM Mode (32/16/8-bit,Read Only).... 568
Free-run Timer
16-bit Free-run Timer Clear Timing................... 233
16-bit Free-run Timer Count Timing.................. 233
Block Diagram of 16-bit Free-run Timer ............ 227
INDEX
Description of 16-bit Free-run Timer Operations
.......................................................... 232
Features of 16-bit Free-run Timer ...................... 226
Notes of 16-bit Free-run Timer.......................... 234
Register List of 16-bit Free-run Timer................ 226
Frequency Data Register
Frequency Data Register Bit Configuration ........ 355
Fujitsu Standard
Pins for Fujitsu Standard Serial On-board Writing
.......................................................... 595
G
General-purpose Registers
General-purpose Registers .................................. 34
H
Hardware
Hardware Components of Interrupt Controller
.......................................................... 132
Hardware Configurations .................................. 294
Hardware Sequence Flag
Hardware Sequence Flag .................................. 575
Hardware Sequence Flags
Example of Using the Hardware Sequence Flags. 579
Harvard
Harvard´Princeton Bus Converter ........................ 31
Hold
Hold Request Cancel Request ........................... 141
Hold Request Cancel Level Register
HRCL (Hold Request Cancel Level Register)
.......................................................... 137
Hold Request Cancel Register
Example of Using the Hold Request Cancel Register
(HRCL).............................................. 143
Hour Register
Hour Register (WTHR) .................................... 365
HRCL
Example of Using the Hold Request Cancel Register
(HRCL).............................................. 143
HRCL (Hold Request Cancel Level Register)
.......................................................... 137
I
I Flag
I Flag ................................................................ 48
I/O
I/O Pin ............................................................ 264
I/O Map
I/O Map .......................................................... 610
ICR
Bit Configuration of Interrupt Control Register (ICR)
.......................................................... 136
ICR Mapping..................................................... 50
Interrupt Control Register (ICR) ..........................50
ICS
Input Capture Control Register (ICS)..................240
IFx Arbitration Register
IFx Arbitration Register 1,2 (IFxARB1,IFxARB2)
..........................................................479
IFx Command Mask Register
IFx Command Mask Register (IFxCMSK) ..........473
IFx Command Request Register
IFx Command Request Register (IFxCREQ) .......471
IFx Data Register
IFx Data Register A1,A2,B1,B2
(IFxDTA1,IFxDTA2,IFxDTB1,IFxDTB2)
..........................................................481
IFx Mask Register
IFx Mask Register 1 and 2 (IFxMSK1,IFxMSK2)
..........................................................478
IFx Message Control Register
IFx Message Control Register (IFxMCTR) .........480
IFxARB
IFx Arbitration Register 1,2 (IFxARB1,IFxARB2)
..........................................................479
IFxCMSK
IFx Command Mask Register (IFxCMSK) ..........473
IFxCREQ
IFx Command Request Register (IFxCREQ) .......471
IFxDTA
IFx Data Register A1,A2,B1,B2
(IFxDTA1,IFxDTA2,IFxDTB1,IFxDTB2)
..........................................................481
IFxDTB
IFx Data Register A1,A2,B1,B2
(IFxDTA1,IFxDTA2,IFxDTB1,IFxDTB2)
..........................................................481
IFxMCTR
IFx Message Control Register (IFxMCTR) .........480
IFxMSK
IFx Mask Register 1 and 2 (IFxMSK1,IFxMSK2)
..........................................................478
ILM
ILM...................................................................38
Interrupt Level Mask (ILM).................................49
Impedance
Input Impedance ...............................................432
INIT
During Reset (INIT) Cancellation ........................77
Setting Initialization Reset (INIT) ........................69
Initial Vector Table
Initial Vector Table Area .....................................43
Initialization
Initialization.....................................................379
Software Initialization .......................................513
667
INDEX
Initialization Reset
Operation Initialization Reset (RST) .................... 70
Setting Initialization Reset (INIT) ........................ 69
INITX
Concerning Recovery by the INITX Pin During Stop
Mode ................................................... 68
Input Capture
16-Bit Input Capture Input Timing..................... 242
Block Diagram of Input Capture ........................ 238
Detecting Baud Rates with the Input Capture ...... 396
Features of Input Capture .................................. 236
Fetch Timing for Input Capture ......................... 241
Register List of Input Capture............................ 237
Input Capture Control Register
Input Capture Control Register (ICS) ................. 240
Input Capture Register
Input Capture Register (IPCP) ........................... 239
Input Impedance
Input Impedance............................................... 432
Input-Output Circuit
Input-Output Circuit Types ................................. 16
Instruction
Instruction Lists ............................................... 640
Instructions
Outline of Instructions ........................................ 31
Internal Architecture
Internal Architecture........................................... 29
Internal Clock
Internal Clock Operations ................................. 174
Internal Peripheral
Internal Peripheral Functions................................. 2
Internal Peripheral Functions
Internal Peripheral Functions................................. 2
Interrupt
Block Diagram of External Interrupt Controller
.......................................................... 148
Bus Idle Interrupt ............................................. 413
Bus Idle Interrupt and Flags .............................. 419
Details of Registers in External Interrupt Control
Block ................................................. 149
EIT (Exception,Interrupt,and Trap) ...................... 47
External Interrupt Operations ............................ 153
External Interrupt Request Levels ...................... 154
Hardware Components of Interrupt Controller
.......................................................... 132
Interrupt Function............................................. 506
Interrupt Level of EIT......................................... 48
Interrupt Stack ................................................... 51
Level Mask for Interrupt/NMI ............................. 49
LIN Synch Break Detection Interrupt and Flags
.......................................................... 418
LIN Synch Break Interrupt ................................ 413
LIN Synch Field Edge Detection Interrupt
.................................................. 413, 418
Major Functions of Interrupt Controller .............. 132
668
Notes If Restoring from STOP Status Performed
Using an External Interrupt .................. 155
Operation Procedure of External Interrupt .......... 153
Reception Interrupt .......................................... 412
Reception Interrupt Generation and Flag Set Timing
......................................................... 416
Register List of External Interrupt Controller...... 148
Transmit Interrupt ............................................ 412
Transmit Interrupt Generation and Flag Set Timing
......................................................... 417
DMA Transfer and Interrupt ............................. 323
Occurrence Timing of Interrupt Clearing............ 326
When NMI/Hold Inhibiting Level Interrupt Handling
is in Process ....................................... 327
Interrupt Control Register
Bit Configuration of Interrupt Control Register (ICR)
......................................................... 136
Interrupt Control Register (ICR).......................... 50
Interrupt Controller
Block Diagram of Interrupt Controller ............... 135
Hardware Components of Interrupt Controller
......................................................... 132
Major Functions of Interrupt Controller ............. 132
Register List of Interrupt Controller ................... 133
Interrupt Enabled Register
Interrupt Enabled Register (ENIR: ENable Interrupt
Request Register)................................ 150
Interrupt Level Mask
Interrupt Level Mask (ILM) ................................ 49
Interrupts
Interrupts Enabling Output of DMAC Interrupt
Control .............................................. 330
UART Interrupts.............................................. 411
Interval Timer
Interval Timer Function Operations ................... 222
INTPND
CAN Interrupt Pending Register
(INTPND1,INTPND2) ........................ 494
INTR
CAN Interrupt Register (INTR)......................... 466
IPCP
Input Capture Register (IPCP)........................... 239
L
LCD Controller
Block Diagram of LCD Controller..................... 519
Features of LCD Controller............................... 518
LCD Controller................................................ 527
LCD Controller Register List ............................ 520
Output Wave Forms during LCD Controller Driver
Operation (1/2 Duty Cycle Output Mode)
......................................................... 528
Output Wave Forms during LCD Controller Driver
Operation (1/3 Duty Cycle Output Mode)
......................................................... 530
INDEX
Output Wave Forms during LCD Controller Driver
Operation (1/4 Duty Cycle Output Mode)
.......................................................... 532
LCD Drive Wave Forms
LCD Drive Wave Forms................................... 527
LCDC Control Register
LCDC Control Register 0 (LCR0) ..................... 522
LCDC Control Register 1 (LCR1) ..................... 524
LCDCMR
Common Pin Selection Register (LCDCMR)...... 521
LCR
LCDC Control Register 0 (LCR0) ..................... 522
LCDC Control Register 1 (LCR1) ..................... 524
Level Mask
Level Mask for Interrupt/NMI............................. 49
LIN
LIN Master-Slave Communication Function....... 422
LIN Device
Connecting LIN Device .................................... 422
LIN Master
LIN Master Operations ..................................... 406
LIN Master-Slave Communication Function....... 422
LIN Master-Slave Communication
LIN Master-Slave Communication Function....... 422
LIN Slave
LIN Slave Operations ....................................... 406
LIN Synch Break Detection Interrupt
LIN Synch Break Detection Interrupt and Flags
.......................................................... 418
LIN Synch Break Interrupt
LIN Synch Break Interrupt................................ 413
LIN Synch Field Edge Detection Interrupt
LIN Synch Field Edge Detection Interrupt
.................................................. 413, 418
Linker
Linker (flnk911) .............................................. 638
LIN-UART
LIN-UART Block Diagrams ............................. 387
LIN-UART Master........................................... 423
LIN-UART Slave............................................. 424
Operation Mode of LIN-UART ......................... 401
Overview of LIN-UART................................... 386
Register List of LIN-UART .............................. 388
Low-power Dissipation Mode
Low-power Dissipation Mode ........................... 109
LVRC
CPU Operation Detection Reset Control Register
(LVRC).............................................. 548
M
Machine Clock
Example Baud Rate Setting for Each Machine Clock
Frequency .......................................... 399
Main Clock
Example of Switching between the Main Clock´the
Sub Clock ...........................................224
Main Oscillation
When Watchdog Reset Occurs while Main Oscillation
is Stopped in Sub Run ............................77
Main Oscillation Stabilization Wait
Main Oscillation Stabilization Wait Operations
..........................................................222
Main Oscillation Stabilization Wait Timer
Block Diagram of Main Oscillation Stabilization Wait
Timer .................................................219
Notes When Using The Main Oscillation Stabilization
Wait Timer..........................................224
Overview of Main Oscillation Stabilization Wait
Timer .................................................218
Main PLL Lock Wait Time
Oscillation Stabilization Wait/Main PLL Lock Wait
Time.....................................................82
Mask
Level Mask for Interrupt/NMI .............................49
Massage Handler Register
Massage Handler Register List...........................456
Master
LIN Master Operations......................................406
LIN Master-Slave Communication Function .......422
LIN-UART Master ...........................................423
Master-Slave Communication
LIN Master-Slave Communication Function .......422
MB91245/S
Memory Map of MB91245/S Series .....................25
MB91F24x/S
Basic Structure of Serial Writing (Asynchronous) in
the MB91F24x/S .................................605
MBM29LV400C
Relationship between the MBM29LV400C and the
FLASH Memory Control Signals ..........570
Memory Map
Memory Map .....................................................43
Memory Map of MB91245/S Series .....................25
Message Interface Register
Message Interface Register List .................452, 454
Message Object
Message Object ........................................484, 499
Messages
Receiving Messages..........................................502
Transmission of Messages .................................500
Minimum Connection
Example of Minimum Connection with Flash
Microcontroller Programmer (When Power
is Supplied from Writer).......................602
Example of Minimum Connection with Flash
Microcontroller Programmer (When User
Power Supply is Used) .........................600
669
INDEX
Minute Register
Minute Register (WTMR) ................................. 365
Mode
Bus Mode .......................................................... 62
Concerning Recovery by the INITX Pin During Stop
Mode ................................................... 68
Continuous Mode ............................................. 444
During Recovery from Stop Mode ....................... 77
FLASH Memory Mode..................................... 569
FR-CPU Programming Mode (16-bit,Read/Write)
.......................................................... 568
FR-CPU ROM Mode (32/16/8-bit,Read Only) .... 568
Low-power Dissipation Mode ........................... 109
Mode Fetch........................................................ 73
Mode Pins ......................................................... 73
Operation Mode ................................................. 62
Operation Mode of LIN-UART ......................... 401
Operation Mode of UART................................. 376
Operation Mode Selection................................. 206
Output Wave Forms during LCD Controller Driver
Operation (1/2 Duty Cycle Output Mode)
.......................................................... 528
Output Wave Forms during LCD Controller Driver
Operation (1/3 Duty Cycle Output Mode)
.......................................................... 530
Output Wave Forms during LCD Controller Driver
Operation (1/4 Duty Cycle Output Mode)
.......................................................... 532
Return from Standby Mode (Stop/Sleep) ............ 143
Setting the Mode ................................................ 63
Single Mode .................................................... 444
Stop Mode ............................................... 445, 527
Synchronous Start/stop Bit Mode....................... 420
Test Mode ....................................................... 510
Transfer Mode ................................................. 313
Mode Fetch
Mode Fetch........................................................ 73
Modes
Operating Modes.............................................. 116
mon911
Debugger (sim911,eml911,mon911) .................. 639
MSGVAL
CAN Message Valid Register
(MSGVAL1,MSGVAL2)..................... 496
Multiplier
PLL Multiplier ................................................... 81
Multiply and Divide Register
Multiply and Divide Register............................... 40
N
NEWDT
CAN New Data Register 1,2 (NEWDT1,NEWDT2)
.......................................................... 492
NMI
Level Mask for Interrupt/NMI ............................. 49
670
Normal Bus Interface
Normal Bus Interface ....................................... 284
O
OCCP
Compare Register (OCCP)................................ 246
OCS
Output Control Register (OCS) ......................... 247
On-board Rewriting
Example of On-board Rewriting by Programmer
......................................................... 606
Pins Used by This Programmer for On-board
Rewriting ........................................... 607
Operating Modes
Operating Modes ............................................. 116
Operation Initialization Reset
Operation Initialization Reset (RST) .................... 70
Operation Mode
Operation Mode................................................. 62
Operation Mode of LIN-UART ......................... 401
Operation Mode of UART ................................ 376
Operation Mode Selection ................................ 206
Ordering
Bit Ordering ...................................................... 41
Byte Ordering.................................................... 41
Original Oscillation Clock
Original Oscillation Clock Frequency ................ 604
OSCCR
OSCCR: Oscillation Control Register ................ 101
Oscillation Control Register
OSCCR: Oscillation Control Register ................ 101
Oscillation Stabilization Wait
Main Oscillation Stabilization Wait Operations
......................................................... 222
Oscillation Stabilization Wait/Main PLL Lock Wait
Time .................................................... 82
Oscillation Stabilization Wait Time
Concerning the Oscillation Stabilization Wait Time at
the Time of Power-on............................ 68
Reset Factor and Oscillation Stabilization Wait Time
........................................................... 67
Oscillation Stabilization Wait Timer
Block Diagram of Main Oscillation Stabilization Wait
Timer................................................. 219
Notes When Using The Main Oscillation Stabilization
Wait Timer......................................... 224
Overview of Main Oscillation Stabilization Wait
Timer................................................. 218
OSCR
MainOscillationStabilizationWaitTimerRegister
(OSCR).............................................. 220
Output Compare
Block Diagram of Output Compare ................... 245
Features of Output Compare ............................. 244
INDEX
Operation of Output Compare ........................... 249
Operation Timing of 16-bit Output Compare ...... 251
Register List of Output Compare ....................... 244
Output Control Register
Output Control Register (OCS) ......................... 247
Output Inversion Register
Output Inversion Register (REVC) .................... 189
Output Wave Forms
Output Wave Forms during LCD Controller Driver
Operation (1/2 Duty Cycle Output Mode)
.......................................................... 528
Output Wave Forms during LCD Controller Driver
Operation (1/3 Duty Cycle Output Mode)
.......................................................... 530
Output Wave Forms during LCD Controller Driver
Operation (1/4 Duty Cycle Output Mode)
.......................................................... 532
P
Package Dimension
Package Dimension.............................................. 6
Parity
Stop Bits,Error Detection,and Parity .................. 403
Pause
When the Pause is Set by Writing into the Control
Register (Set Independently for Each
Channel or Simultaneously for All the
Channels). .......................................... 327
PC
PC (Program Counter) ........................................ 39
PDIVR
PDIVR (Divide Ratio Control Register) ............. 203
PDR
Port Data Register (PDR:PDR0 to PDRG).......... 117
Peripheral
Peripheral Clock (CLKP).................................... 84
Built-in Peripheral Request ............................... 315
Internal Peripheral Functions................................. 2
Occurrence of Transfer Stop Request from Peripheral
Circuits .............................................. 329
Peripheral Clock
Peripheral Clock (CLKP).................................... 84
Peripheral Functions
Internal Peripheral Functions................................. 2
PFR
Port Function Register (PFR,EPFR)................... 121
PILR
Port Input Level Select Register (PILR) ............. 128
Pin Assignment
Pin Assignment.................................................... 7
Pin Descriptions
Pin Descriptions................................................... 8
PLL
During Recovery from Abnormal State when
Selecting PLL........................................77
Enable PLL Operation.........................................80
PLL Multiplier ...................................................81
PLL Multiplier
PLL Multiplier ...................................................81
Pointer
RP (Return Pointer) ............................................39
SSP (System Stack Pointer) .................................39
System Stack Pointer (SSP) .................................51
USP (User Stack Pointer) ....................................40
Port
Basic Block Diagram of the Port ........................114
Port Data Register
Port Data Register (PDR:PDR0 to PDRG) ..........117
Port Function Register
Port Function Register (PFR,EPFR) ...................121
Port Input Level Select Register
Port Input Level Select Register (PILR) ..............128
Port Status Control Register
Port Status Control Register (PSCR)...................129
Power Supply
Example of Minimum Connection with Flash
Microcontroller Programmer (When User
Power Supply is Used) .........................600
Example of Serial Writing Connection (When User
Power Supply is Used) .........................596
Power-on
Concerning the Oscillation Stabilization Wait Time at
the Time of Power-on.............................68
PPG
8-bit PPG ch.0,ch.2,ch.4,ch.6 Block Diagram
..........................................................183
8-bit PPG ch.1,ch.5 Block Diagram ....................184
8-bit PPG ch.3,ch.7 Block Diagram ....................185
PPG Functions .................................................180
Register List of PPG .........................................181
PPG Activation Register
PPG Activation Register (TRG) .........................189
PPGCn
PPGCn Register (PPGn Operation Mode Control
Register) n=0,1,2,3,4,5,6,7....................186
PPGn Operation Mode Control Register
PPGCn Register (PPGn Operation Mode Control
Register) n=0,1,2,3,4,5,6,7....................186
Prescaler
CAN Clock Prescaler ........................................514
Princeton
Harvard´Princeton Bus Converter.........................31
Priority
Priority among Channels ...................................332
Priority Judgment
Priority Judgment .............................................138
671
INDEX
PRLH
PRLL/PRLH Register (Reload Register:PRLL0 to
PRLL7/PRLH0 to PRLH7) .................. 188
PRLL
PRLL/PRLH Register (Reload Register:PRLL0 to
PRLL7/PRLH0 to PRLH7) .................. 188
Product
Components of Each Product................................. 4
Program Access
Program Access ................................................. 42
Program Counter
PC (Program Counter) ........................................ 39
Program Status
PS (Program Status) ........................................... 34
Programmer
Example of Minimum Connection with Flash
Microcontroller Programmer (When User
Power Supply is Used)......................... 600
Example of On-board Rewriting by Programmer. 606
Pins Used by This Programmer for On-board
Rewriting ........................................... 607
Example of Serial Writing Connection (When Power
is Supplied from the Flash Microcontroller
Programmer)....................................... 598
Programming
Basic Configuration for Serial Programming in the
MB91F24x/S ...................................... 594
Programming Data
Programming Data in FLASH Memory .............. 581
Programming Model
Basic Programming Model.................................. 33
Protecting
List of the Sector Protecting Operations.............. 588
Protection
Cancel Sector Protection Temporarily ................ 591
Enable Sector Protection ................................... 589
Verifying Sector Protection ............................... 589
PS
Notes on PS Register .......................................... 38
PS (Program Status) ........................................... 34
PSCR
Port Status Control Register (PSCR) .................. 129
Pulse Width Count
Details of Pulse Width Count Operation ............. 209
Pulse Width Count Functions ............................ 204
Pulse Width Count Start and Stop ...................... 207
PWC
PWC Block Diagram ........................................ 197
PWC Functions ................................................ 196
Register List of PWC........................................ 196
PWC Control/Status Register
PWC Control/Status Register (PWCSR) ............. 198
PWC Data Buffer Register
PWCR Register (PWC Data Buffer Register)...... 202
672
PWCR
PWCR Register (PWC Data Buffer Register) ..... 202
PWCSR
PWC Control/Status Register (PWCSR)............. 198
PWM
Precautions When Changing PWM Setting Values
......................................................... 347
PWM1 and PWM2 Compare Registers Functions
......................................................... 343
PWM1 and PWM2 Selection Register Functions
......................................................... 345
PWM Control Register
PWM Control Register Bit Configuration........... 342
R
RDR
Receive Data Register (RDR) and Send Data Register
(TDR) ................................................ 392
RDX
CSX→ RDX/WRX Setup,RDX/WRnX→ CSX Hold
Setting (TYP[3:0]=0000B,AWR=000BH)
......................................................... 290
RDY
Ready/Busy Signal (RDY/BUSYX)................... 575
Ready
Ready/Busy Signal (RDY/BUSYX)................... 575
Real Time Clock
Block Diagram of Real Time Clock ................... 360
Overview of Real Time Clock ........................... 360
Real Time Clock Operation............................... 366
Register List of Real Time Clock....................... 361
receive Data Format
Send/receive Data Format: ........................ 402, 404
Receive Data Register
Receive Data Register (RDR) and Send Data Register
(TDR) ................................................ 392
Receive Operation
Receive Operation.................................... 377, 403
Reception
Reception Interrupt .......................................... 412
Reception Interrupt
Reception Interrupt Generation and Flag Set Timing
......................................................... 416
Recommended Setting
Recommended Setting Values ........................... 442
Register
32kHz Timer Data Register (16-bit) (CUTD)...... 541
32kHz Timer Data Register Configuration ......... 543
4MHz Timer Data Register (24-bit) (CUTR) ...... 542
A/D Control Status Register (ADCS1) ............... 436
A/D Conversion Time Setting Register
(ADCT0,ADCT1) ............................... 440
A/D Start/End Channel Setting Register
(ADSCH,ADECH).............................. 442
INDEX
Amplitude Data Register Bit Configuration ........ 354
Baud Rate/Reload Counter Register (BGR) ........ 395
Bit Configuration of Interrupt Control Register (ICR)
.......................................................... 136
Bit Configuration of Serial Control Register (SCR)
.......................................................... 371
Bit Configuration of Serial Mode Register (SMR)
.......................................................... 369
CAN Bit Timing Register (BTR) ....................... 465
CAN Control Register (CTRLR) ....................... 458
CAN Interrupt Pending Register
(INTPND1,INTPND2) ........................ 494
CAN Interrupt Register (INTR) ......................... 466
CAN Message Valid Register
(MSGVAL1,MSGVAL2) .................... 496
CAN New Data Register 1,2 (NEWDT1,NEWDT2)
.......................................................... 492
CAN Prescaler Extended Register (BRPER)....... 469
CAN Prescaler Register .................................... 498
CAN Status Register (STATR).......................... 461
CAN Test Register (TESTR)............................. 467
CAN Transmission Request Register
(TREQR1,TREQR2) ........................... 490
CLKR: Clock Source Control Register................. 94
Clock Prescaler Register ................................... 457
Common Pin Selection Register (LCDCMR)...... 521
Compare Register (OCCP)................................ 246
Correction Unit Control Register (CUCR) .......... 539
CPU Operation Detection Reset Control Register
(LVRC).............................................. 548
CTBR: Time-base Counter Clear Register ............ 93
Data Direction Register (DDR:DDR0 to DDRG) 119
Decrement Grade Register Functions ................. 357
DIVR0: Base Clock Divide Setting Register 0 ...... 98
DIVR1: Base Clock Divide Setting Register 1
.......................................................... 100
DMA Interrupt Clear Register (DRCL) .............. 258
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Control/Status
Register A [DMACA0 to DMACA4]
.......................................................... 297
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Control/Status
Register B [DMACB0 to DMACB4]
.......................................................... 302
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 DMAC Total Control
Register [DMACR] ............................. 310
Example of Using the Hold Request Cancel Register
(HRCL).............................................. 143
Extended Communication Control Register (ECCR)
.......................................................... 394
Extended Status Control Register (ESCR) .......... 393
External Interrupt Request Level Setting Register
(ELVR: External LeVel Register) ......... 152
External Interrupt Request Register (EIRR: External
Interrupt Request Register) .................. 151
FLASH Memory Status Register (FLCR) ........... 565
FLASH Wait Register (FLWC) ......................... 566
Frequency Data Register Bit Configuration ........ 355
HRCL (Hold Request Cancel Level Register)......137
IFx Arbitration Register 1,2 (IFxARB1,IFxARB2)
..........................................................479
IFx Command Mask Register (IFxCMSK) ..........473
IFx Command Request Register (IFxCREQ) .......471
IFx Data Register A1,A2,B1,B2
(IFxDTA1,IFxDTA2,IFxDTB1,IFxDTB2)
..........................................................481
IFx Mask Register 1 and 2 (IFxMSK1,IFxMSK2)
..........................................................478
IFx Message Control Register (IFxMCTR) .........480
Interrupt Control Register (ICR) ..........................50
Interrupt Enabled Register (ENIR: ENable Interrupt
Request Register).................................150
LCDC Control Register 0 (LCR0) ......................522
LCDC Control Register 1 (LCR1) ......................524
Massage Handler Register List...........................456
Message Interface Register List .................452, 454
Multiply and Divide Register ...............................40
Notes on PS Register ..........................................38
OSCCR: Oscillation Control Register .................101
Output Control Register (OCS) ..........................247
PDIVR (Divide Ratio Control Register)..............203
Port Data Register (PDR:PDR0 to PDRG) ..........117
Port Input Level Select Register (PILR) ..............128
Port Status Control Register (PSCR)...................129
PPG Activation Register (TRG) .........................189
PPGCn Register (PPGn Operation Mode Control
Register) n=0,1,2,3,4,5,6,7....................186
PWC Control/Status Register (PWCSR) .............198
PWCR Register (PWC Data Buffer Register)
..........................................................202
PWM Control Register Bit Configuration ...........342
PWM1 and PWM2 Selection Register Functions
..........................................................345
Receive Data Register (RDR) and Send Data Register
(TDR).................................................392
Reload Register (UTIMER) ...............................256
RSRR: Reset Factor Register/Watchdog Timer
Control Register ....................................87
Serial Control Register (SCR) ............................389
Serial Input Data Register (SIDR)/Serial Output Data
Register (SODR) .................................373
Serial Mode Register (SMR)..............................390
Serial Status Register (SSR) ..............................391
Sound Control Register Bit Configuration...........352
Sound Disable Register Functions ......................358
STCR: Standby Control Register..........................89
Table Base Register (TBR) ..................................52
TBCR: Time-base Counter Control Register .........91
TBR (Table Base Register) ..................................39
Timer Control Register (TCCS) .........................229
Timer Data Register (TCDT) .............................228
Tone Count Register Bit Configuration...............356
Total Control Register List ................................451
U-Timer Control Register (UTIMC) ...................257
673
INDEX
WPR: Watchdog Reset Occurrence Postponing
Register ................................................ 97
Register/Flag Bits
Overview of the Register/Flag Bits .................... 410
Registers
Analog Input Enable Registers........................... 435
General-purpose Registers................................... 34
Reload Operation
Count Control Register and Reload Operation
.......................................................... 322
Reload Operation ............................................. 318
Reload Register
16-bit Reload Register (TMRLR)....................... 173
PRLL/PRLH Register (Reload Register:PRLL0 to
PRLL7/PRLH0 to PRLH7) .................. 188
Reload Register (UTIMER)............................... 256
Reload Timer
Register List of Reload Timer............................ 168
Reset
Block Diagram of External Reset Pin ................... 71
Correspondence between Reset Factor Bit and Reset
Factor................................................... 75
CPU Operation Detection Reset Circuit .............. 546
CPU Operation Detection Reset Circuit Block
Diagram ............................................. 547
CPU Operation Detection Reset Circuit Operation
.......................................................... 550
During Reset (INIT) Cancellation ........................ 77
External Pin Reset Timing................................... 71
Notes on Reset Factor Bit.................................... 76
Notes on Using the CPU Operation Detection Reset
Circuit ................................................ 551
Operation Initialization Reset (RST) .................... 70
Overview of Reset Operation............................... 72
Reset................................................................. 74
Reset Factor and Oscillation Stabilization Wait Time
............................................................ 67
Setting Initialization Reset (INIT) ........................ 69
Software Reset ................................................. 414
Status of Pin During Reset ................................ 627
When Watchdog Reset Occurs while Main Oscillation
is Stopped in Sub Run............................ 77
Reset Factor
RSRR: Reset Factor Register/Watchdog Timer
Control Register .................................... 87
Reset Factor Bit
Correspondence between Reset Factor Bit and Reset
Factor................................................... 75
Notes on Reset Factor Bit.................................... 76
Return Pointer
RP (Return Pointer) ............................................ 39
REVC
Output Inversion Register (REVC)..................... 189
ROM
Writing from a ROM Writer .............................. 555
674
ROM Writer
Writing from a ROM Writer ............................. 555
RP
RP (Return Pointer)............................................ 39
RSRR
RSRR: Reset Factor Register/Watchdog Timer
Control Register.................................... 87
RST
Operation Initialization Reset (RST) .................... 70
S
Sampling Clock
Sampling Clock Edge ....................................... 420
SCR
Bit Configuration of Serial Control Register (SCR)
......................................................... 371
SCR (System Condition Code Register) ............... 37
Serial Control Register (SCR) ........................... 389
Second Register
Second Register (WTBR) ................................. 365
Sector
Cancel Sector Protection Temporarily................ 591
Enable Sector Protection................................... 589
Erasing Data from FLASH Memory (Erase Sector)
......................................................... 584
List of the Sector Protecting Operations ............. 588
Resuming Sector Erase in the FLASH Memory
......................................................... 586
Sector Structure of the FLASH Memory ............ 556
Suspending Sector Erase of the FLASH Memory
......................................................... 586
Verifying Sector Protection............................... 589
Sector Erase
Resuming Sector Erase in the FLASH Memory
......................................................... 586
Suspending Sector Erase of the FLASH Memory
......................................................... 586
Sector Protection
Cancel Sector Protection Temporarily................ 591
Enable Sector Protection................................... 589
Verifying Sector Protection............................... 589
Selection Register
PWM1 and PWM2 Selection Register Functions
......................................................... 345
Send
Send/receive Data Format: ........................ 402, 404
Send Data Register
Receive Data Register (RDR) and Send Data Register
(TDR) ................................................ 392
Send Operation
Send Operation ........................................ 377, 403
Sending
End of Sending ................................................ 379
Start of Sending ............................................... 379
INDEX
Serial Control Register
Bit Configuration of Serial Control Register (SCR)
.......................................................... 371
Serial Control Register (SCR) ........................... 389
Serial Input Data Register
Serial Input Data Register (SIDR)/Serial Output Data
Register (SODR)................................. 373
Serial Mode Register
Bit Configuration of Serial Mode Register (SMR)
.......................................................... 369
Serial Mode Register (SMR) ............................. 390
Serial On-board Writing
Pins for Fujitsu Standard Serial On-board Writing
.......................................................... 595
Serial Output Data Register
Serial Input Data Register (SIDR)/Serial Output Data
Register (SODR)................................. 373
Serial Pin
Direct Access to the Serial Pin .......................... 408
Serial Programming
Basic Configuration for Serial Programming in the
MB91F24x/S ...................................... 594
Serial Status Register
Bit Configuration of Serial Status Register (SSR)
.......................................................... 374
Serial Status Register (SSR).............................. 391
Serial Writing
Basic Structure of Serial Writing (Asynchronous) in
the MB91F24x/S................................. 605
Serial Writing Connection
Example of Serial Writing Connection (When Power
is Supplied from the Flash Microcontroller
Programmer) ...................................... 598
Example of Serial Writing Connection (When User
Power Supply is Used) ........................ 596
Setting Initialization Reset
Setting Initialization Reset (INIT)........................ 69
Setting Register
DIVR1: Base Clock Divide Setting Register 1
.......................................................... 100
SIDR
Serial Input Data Register (SIDR)/Serial Output Data
Register (SODR)................................. 373
Signal
Ready/Busy Signal (RDY/BUSYX)................... 575
sim911
Debugger (sim911,eml911,mon911) .................. 639
Single Mode
Single Mode .................................................... 444
Slave
LIN Master-Slave Communication Function....... 422
LIN Slave Operations ....................................... 406
LIN-UART Slave............................................. 424
Sleep
Notes on DMA Transfer During Sleep ................331
Slot
Note on Delayed Slot ..........................................61
Operation with Delay Slot ...................................44
Slots
Operation without Delay Slots .............................46
SMR
Bit Configuration of Serial Mode Register (SMR)
..........................................................369
Serial Mode Register (SMR)..............................390
SODR
Serial Input Data Register (SIDR)/Serial Output Data
Register (SODR) .................................373
Software
Software Initialization .......................................513
Software Requirements .....................................315
Software Reset .................................................414
Sound Control Register
Sound Control Register Bit Configuration...........352
Sound Disable Register
Sound Disable Register Functions ......................358
Sound Generator
Sound Generator Block Diagram........................350
Sound Generator Components............................350
Sound Generator Register List ...........................351
Source Clock
Selecting a Source Clock .....................................79
SSP
SSP (System Stack Pointer) .................................39
System Stack Pointer (SSP) .................................51
SSR
Bit Configuration of Serial Status Register (SSR)
..........................................................374
Serial Status Register (SSR) ..............................391
Stack
Interrupt Stack....................................................51
Stack Pointer
SSP (System Stack Pointer) .................................39
System Stack Pointer (SSP) .................................51
USP (User Stack Pointer) ....................................40
Standby
Recovery from Standby.....................................153
Standby Control Register
STCR: Standby Control Register..........................89
Standby Mode
Return from Standby Mode (Stop/Sleep).............143
STATR
CAN Status Register (STATR) ..........................461
STCR
STCR: Standby Control Register..........................89
Step
Step/Block Transfer Two-cycle Transfer.............317
675
INDEX
Step Transfer
Step Transfer ................................................... 317
Stepper Motor Controller
Block Diagram of the Stepper Motor Controller
.......................................................... 340
Overview of the Stepper Motor Controller .......... 340
Stepper Motor Controller Register List............... 341
STOP
Notes If Restoring from STOP Status Performed
Using an External Interrupt .................. 155
Recovery Operations from STOP Status ............. 156
Stop Mode
Concerning Recovery by the INITX Pin During Stop
Mode ................................................... 68
During Recovery from Stop Mode ....................... 77
Stop Mode ............................................... 445, 527
Sub Clock
Example of Switching between the Main Clock´the
Sub Clock........................................... 224
Subsecond Register
Subsecond Register (WTBR)............................. 364
Synchronization
Clock Synchronization...................................... 415
Synchronous Start/stop Bit Mode
Synchronous Start/stop Bit Mode....................... 420
System Condition Code Register
SCR (System Condition Code Register) ............... 37
System Stack Pointer
SSP (System Stack Pointer)................................. 39
System Stack Pointer (SSP)................................. 51
T
Table Base Register
Table Base Register (TBR).................................. 52
TBR (Table Base Register).................................. 39
TBCR
TBCR: Time-base Counter Control Register ......... 91
TBR
Table Base Register (TBR).................................. 52
TBR (Table Base Register).................................. 39
TCCS
Timer Control Register (TCCS) ......................... 229
TCDT
Timer Data Register (TCDT)............................. 228
TDR
Receive Data Register (RDR) and Send Data Register
(TDR) ................................................ 392
Test Mode
Test Mode ....................................................... 510
TESTR
CAN Test Register (TESTR) ............................. 467
676
Time
Oscillation Stabilization Wait/Main PLL Lock Wait
Time .................................................... 82
Time-base Counter
Time-base Counter........................................... 103
Time-base Counter Clear Register
CTBR: Time-base Counter Clear Register ............ 93
Time-base Counter Control Register
TBCR: Time-base Counter Control Register......... 91
Timer Control Register
Timer Control Register (TCCS)......................... 229
Timer Control Register (WTCR) ....................... 362
Timer Data Register
Timer Data Register (TCDT) ............................ 228
Timer Register
16-bit Timer Register (TMR) ............................ 173
Timing Chart
Timing Chart of Each Pin ................................. 608
TMCSR
Control Status Register (TMCSR) ..................... 170
TMR
16-bit Timer Register (TMR) ............................ 173
TMRLR
16-bit Reload Register (TMRLR) ...................... 173
Tone Count Register
Tone Count Register Bit Configuration .............. 356
Total Control Register
Total Control Register List................................ 451
Transfer
Accept and Transfer the Transfer Request .......... 325
Block Transfer................................................. 334
Burst Transfer.................................................. 335
Notes on DMA Transfer During Sleep ............... 331
Select Transfer Sequence .................................. 316
Transfer Aaddress ............................................ 314
Transfer Complete ........................................... 328
Transfer Count and Transfer Complete .............. 314
Transfer Data Format ....................................... 377
Transfer Mode ................................................. 313
Transfer Type .................................................. 313
Two-cycle Data Flow During Cycle Transfer...... 336
Block Transfer................................................. 317
Burst Two-cycle Transfer ................................. 316
DMA Transfer and Interrupt ............................. 323
Occurrence of Transfer Stop Request from Peripheral
Circuits .............................................. 329
Step Transfer ................................................... 317
Step/Block Transfer Two-cycle Transfer ............ 317
Transfer Data Format
Transfer Data Format ............................... 377, 378
INDEX
Transfer-destination
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Transfer-source/
Transfer-destination Address Setting
Register [DMASA0 to DMASA4/DMADA0
to DMADA4] ..................................... 308
Transfer-destination Address
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Transfer-source/
Transfer-destination Address Setting
Register [DMASA0 to DMASA4/DMADA0
to DMADA4] ..................................... 308
Transfer-source
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Transfer-source/
Transfer-destination Address Setting
Register [DMASA0 to DMASA4/DMADA0
to DMADA4] ..................................... 308
Transfer-source Address
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Transfer-source/
Transfer-destination Address Setting
Register [DMASA0 to DMASA4/DMADA0
to DMADA4] ..................................... 308
Transition
Counter Status at the Transition to the Main Clock
When Main Oscillation Stabilization Wait
Timer is Activated............................... 223
Transitions
Device Statuses and Individual Transitions......... 106
Transmit
Transmit Interrupt ............................................ 412
Transmit Interrupt
Transmit Interrupt Generation and Flag Set Timing
.......................................................... 417
Trap
EIT (Exception,Interrupt,and Trap)...................... 47
TREQR
CAN Transmission Request Register
(TREQR1,TREQR2) ........................... 490
TRG
PPG Activation Register (TRG) ........................ 189
Two-cycle Data Flow
Two-cycle Data Flow During Cycle Transfer...... 336
Two-cycle Transfer
Burst Two-cycle Transfer ................................. 316
Step/Block Transfer Two-cycle Transfer ............ 317
TYP
Automatic Wait Timing
(TYP[3:0]=0000B,AWR=2008H).......... 287
Basic Timing (When there is Consecutive Access)
(TYP[3:0]=0000B,AWR=0008H).......... 284
CSX Delay Setting (TYP[3:0]=0000B,AWR=000CH)
.......................................................... 289
CSX→ RDX/WRX Setup,RDX/WRnX→ CSX Hold
Setting (TYP[3:0]=0000B,AWR=000BH)
.......................................................... 290
External Wait Timing
(TYP[3:0]=0001B,AWR=2008H).......... 288
ReadÆWrite Timing
(TYP[3:0]=0000B,AWR=0048H) ..........285
WriteÆWrite Timing
(TYP[3:0]=0000B,AWR=0018H) ..........286
U
UART
Application Example of UART ..........................383
Block Diagram of UART ..................................368
Features of UART ............................................368
Operation Mode of UART .................................376
Overview of Changes from Normal UART .........426
Register List of UART ......................................369
Selecting a UART Clock ...................................376
Selecting Baud Rate for UART ..........................397
UART Interrupts ..............................................411
Underflow
Underflow Operation ........................................175
User Power Supply
Example of Minimum Connection with Flash
Microcontroller Programmer (When User
Power Supply is Used) .........................600
Example of Serial Writing Connection (When User
Power Supply is Used) .........................596
User Stack Pointer
USP (User Stack Pointer) ....................................40
USP
USP (User Stack Pointer) ....................................40
UTIM
U-Timer (UTIM) ..............................................256
UTIMC
U-Timer Control Register (UTIMC) ...................257
UTIMER
Reload Register (UTIMER) ...............................256
U-Timer
Block Diagram of U-Timer................................255
Features of U-Timer..........................................254
Register List of U-Timer ...................................254
U-Timer (UTIM) ..............................................256
U-Timer Control Register
U-Timer Control Register (UTIMC) ...................257
V
Vector Table
EIT Vector Table................................................52
Initial Vector Table Area .....................................43
Vector Table ....................................................624
VRAM
Data Memory for Display (VRAM)....................525
677
INDEX
W
Watchdog Reset
When Watchdog Reset Occurs while Main Oscillation
is Stopped in Sub Run............................ 77
Watchdog Reset Occurrence Postponing Register
WPR: Watchdog Reset Occurrence Postponing
Register ................................................ 97
Wave Forms
LCD Drive Wave Forms ................................... 527
Output Wave Forms during LCD Controller Driver
Operation (1/2 Duty Cycle Output Mode)
.......................................................... 528
Output Wave Forms during LCD Controller Driver
Operation (1/3 Duty Cycle Output Mode)
.......................................................... 530
Output Wave Forms during LCD Controller Driver
Operation (1/4 Duty Cycle Output Mode)
.......................................................... 532
WPR
WPR: Watchdog Reset Occurrence Postponing
Register ................................................ 97
Write Timing
ReadÆWrite Timing
(TYP[3:0]=0000B,AWR=0048H) .......... 285
WriteÆWrite Timing
(TYP[3:0]=0000B,AWR=0018H) .......... 286
Writing
Basic Structure of Serial Writing (Asynchronous) in
the MB91F24x/S ................................. 605
Details on Writing/Erasing FLASH Memory ...... 581
678
Example of Serial Writing Connection (When Power
is Supplied from the Flash Microcontroller
Programmer) ...................................... 598
Example of Serial Writing Connection (When User
Power Supply is Used) ........................ 596
Pins for Fujitsu Standard Serial On-board Writing
......................................................... 595
WRX
CSX→ RDX/WRX Setup,RDX/WRnX→ CSX Hold
Setting (TYP[3:0]=0000B,AWR=000BH)
......................................................... 290
WTBR
Second Register (WTBR) ................................. 365
Subsecond Register (WTBR) ............................ 364
WTCR
Timer Control Register (WTCR) ....................... 362
WTDBL
Clock Disable Register (WTDBL) ..................... 362
WTHR
Hour Register (WTHR) .................................... 365
WTMR
Minute Register (WTMR)................................. 365
Y
Yokogawa Digital Computer Corporation
Configuration of the AF200 Flash Microcontroller
Programmer System (Manufactured by
Yokogawa Digital Computer Corporation)
......................................................... 604
CM71-10136-2E
FUJITSU MICROELECTRONICS • CONTROLLER MANUAL
FR60Lite
32-BIT MICROCONTROLLER
MB91245/S Series
HARDWARE MANUAL
April 2009 the 2nd edition
Published
FUJITSU MICROELECTRONICS LIMITED
Edited
Sales Promotion Dept.