7.5MB

The following document contains information on Cypress products.
FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
CM71-10128-2E
FR60Lite
32-BIT MICROCONTROLLER
MB91270 Series
HARDWARE MANUAL
FR60Lite
32-BIT MICROCONTROLLER
MB91270 Series
HARDWARE MANUAL
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
FUJITSU LIMITED
PREFACE
■ Purpose of this document and intended reader
We sincerely thank you for your continued use of Fujitsu semiconductor products.
The MB91270 series is shingle chip microcontroller that builds various I/O resources and the bus control
mechanisms into by using 32-bit efficient RISC CPU for the built-in control being demanded for CPU
processing high performance/high-speed. Because the vast address space that 32 bits CPU access is
supported, the external bus access is basically. To speed up CPU instruction execution, MB91270 series
has built-in RAM of 24KB (for data).
This series is optimized to the embedded applications; automotive applications such as car audio or car airconditioning equipment that require high-performance CPU processing power.
The MB91270 series power-up the bus access based on FR30/40 family CPU, and is FR60Lite family
corresponding to use at high speed.
This manual describes the functions and operations of the MB91270 Series for engineers who develop
products using the MB91270 Series. Please read through this manual.
For more information on various instructions, refer to "Instruction Manual".
Note: FR is the abbreviation of FUJITSU RISC CONTROLLER, which is a product of Fujitsu.
■ Trademarks
The company names and brand names herein are the trademarks or registered trademarks of their respective
owners.
■ I2C license
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C Standard Specification as
defined by Philips.
■ Organization of this document
This manual contains the following 27 chapters and appendix.
CHAPTER 1 OVERVIEW
FR family is a standard single-chip microcontroller that has a 32-bit high-performance RISC CPU as well
as built-in I/O resources and bus control mechanisms for embedded controller requiring highperformance and high-speed CPU processing.
CHAPTER 2 HANDLING DEVICES
This chapter provides precautions on handling the FR family.
CHAPTER 3 CPU and CONTROL UNIT
This chapter provides basic information required to understand the CPU core functions of FR family. It
covers architecture, specifications, and instructions.
CHAPTER 4 RESET
This chapter describes reset.
CHAPTER 5 EXTERNAL BUS INTERFACE
The external bus interface controller controls the interfaces with the internal bus for chips and with
external memory and I/O devices. This chapter explains each function of the external bus interface and its
operation.
i
CHAPTER 6 I/O PORT
This chapter describes the I/O ports and the configuration and functions of registers.
CHAPTER 7 INTERRUPT CONTROLLER
This chapter describes the overview of the interrupt controller, the configuration and functions of
registers, and interrupt controller operation.
CHAPTER 8 EXTERNAL INTERRUPT
This chapter describes the overview of the external interrupt, the configuration and functions of registers,
and operation of the external interrupt.
CHAPTER 9 REALOS-RELATED HARDWARE
REALOS-related hardware is used by the real-time OS. Therefore, when REALOS is used, the hardware
cannot be used with the user program.
CHAPTER 10 DMA CONTROLLER (DMAC)
This chapter describes the overview of the DMA controller (DMAC), the configuration and functions of
registers, and DMAC operation.
CHAPTER 11 CAN CONTROLLER
This chapter explains the functions and operations of CAN controller.
CHAPTER 12 LIN-UART
This chapter explains functions and operation of LIN-UART.
CHAPTER 13 I2C INTERFACE
This chapter describes the outline of the I2C interface, the configuration and functions of registers, and
I2C interface operation.
CHAPTER 14 16-BIT RELOAD TIMER
This chapter explains register configuration/ function and timer operation of 16-bit reload timer.
CHAPTER 15 16-BIT FREE-RUN TIMER
This chapter describes the functions and operation of the 16-bit free-run timer.
CHAPTER 16 INPUT CAPTURE
This chapter describes the function and operation of the input capture.
CHAPTER 17 OUTPUT COMPARE
This chapter explains functions and operation of the output compare.
CHAPTER 18 PPG TIMER
This chapter describes the PPG timer.
CHAPTER 19 UP/DOWN COUNTER
This chapter describes the function and operation of 8/16-bit up/down counter.
CHAPTER 20 CLOCK MONITOR
This chapter explains the functions and operation of clock monitor.
CHAPTER 21 REAL TIME CLOCK
This chapter describes the register structure and functions of the Real Time Clock (hereafter, referred to
as RTC) and describes the operation of RTC module.
CHAPTER 22 A/D CONVERTER
This chapter explains the overview of the A/D converter, the configuration/function of the register, and
its operation.
ii
CHAPTER 23 D/A CONVERTER
This chapter describes the overview of the D/A converter, the configuration and functions of registers,
and the D/A converter operation. Note: MB91V280 Only
CHAPTER 24 CLOCK MODULATOR
This chapter describes the register configuration, function and operation of the clock modulator.
CHAPTER 25 CLOCK SUPERVISOR
This chapter explains clock supervisor's function.
CHAPTER 26 FLASH MEMORY
This chapter provides an outline of flash memory and explains its register configuration, register
functions, and operations.
CHAPTER 27 HARDWARE WATCHDOG TIMER
This chapter explains the functions of hardware watchdog timer.
APPENDIX
The appendixes describe the I/O map, interrupt vectors, and pin states in each CPU state.
iii
•
•
•
•
•
•
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented
solely for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device;
FUJITSU does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility
arising out of such use of the information. FUJITSU assumes no liability for any damages whatsoever arising out
of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be
construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or
any other right of FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party's
intellectual property right or other right by using such information. FUJITSU assumes no liability for any
infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general
use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but
are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers
that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to
death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control
in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy,
fire protection, and prevention of over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or technologies subject to certain restrictions on export
under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will
be required for export of those products from Japan.
Copyright© 2007 FUJITSU LIMITED All rights reserved
iv
CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
CHAPTER 2
2.1
HANDLING DEVICES ................................................................................ 31
Precautions when Handling Devices ................................................................................................ 32
CHAPTER 3
3.1
3.2
3.2.1
3.2.2
3.3
3.3.1
3.3.2
3.4
3.5
3.6
3.6.1
3.6.2
3.7
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
3.7.7
3.7.8
3.8
3.8.1
3.8.2
3.9
3.9.1
3.9.2
3.9.3
3.9.4
3.9.5
OVERVIEW ................................................................................................... 1
Features .............................................................................................................................................. 2
Block Diagram .................................................................................................................................... 7
Package Dimension ............................................................................................................................ 8
Pin Assignment ................................................................................................................................... 9
Memory Map ..................................................................................................................................... 10
Description of Pin Function ............................................................................................................... 11
I/O Circuit Type ................................................................................................................................. 25
CPU and CONTROL UNIT ......................................................................... 35
Memory Space ..................................................................................................................................
Internal Architecture ..........................................................................................................................
Internal Architecture ....................................................................................................................
Overview of Instructions ..............................................................................................................
Programming Model .........................................................................................................................
General-Purpose Registers .........................................................................................................
Dedicated Registers ....................................................................................................................
Data Configuration ............................................................................................................................
Memory Map .....................................................................................................................................
Branch Instructions ...........................................................................................................................
Operation with Delay Slot ............................................................................................................
Operation without Delay Slot .......................................................................................................
EIT (Exception, Interruption, and Trap) ............................................................................................
EIT Interrupt Levels .....................................................................................................................
ICR (Interrupt Control Register) ...................................................................................................
SSP (System Stack Pointer) ........................................................................................................
Interrupt Stack .............................................................................................................................
TBR (Table Base Register) .........................................................................................................
EIT Vector Table ..........................................................................................................................
Multiple EIT Processing ...............................................................................................................
Operations ...................................................................................................................................
Operating Mode ................................................................................................................................
Bus Modes ...................................................................................................................................
Mode Settings ..............................................................................................................................
Clock Generation Control .................................................................................................................
PLL Controls ................................................................................................................................
Oscillation stability waiting and PLL lock waiting time .................................................................
Clock Distribution .........................................................................................................................
Clock Division ..............................................................................................................................
Block Diagram of Clock Generation Controller ............................................................................
v
36
37
38
41
43
44
45
52
54
55
56
58
59
60
62
64
65
66
67
70
72
76
77
78
81
82
84
85
87
88
3.9.6
Register of Clock Generation Controller ...................................................................................... 89
3.9.7
Peripheral Circuits of Clock Controller ....................................................................................... 106
3.10 Device state control ........................................................................................................................ 109
3.10.1 State of device and each transition ........................................................................................... 110
3.10.2 Low-power Consumption Mode ................................................................................................. 113
3.11 Main Clock Oscillation Stabilization Wait Timer .............................................................................. 117
CHAPTER 4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
CHAPTER 5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
5.4.3
5.5
5.6
5.7
5.8
138
141
142
143
148
153
154
156
157
158
163
167
175
178
181
I/O PORT .................................................................................................. 183
Overview of I/O Ports ......................................................................................................................
Port Data Register (PDR)/Data Direction Register (DDR) ..............................................................
Setting of the Port Function Register ..............................................................................................
Rearrangement of External Interrupt Input .....................................................................................
Selection of Pin Input Level ............................................................................................................
Pull-up and Pull-down Control Register ..........................................................................................
Input Data Direct Read Register .....................................................................................................
CHAPTER 7
126
128
130
132
133
134
136
EXTERNAL BUS INTERFACE ................................................................ 137
Features of External Bus Interface .................................................................................................
External Bus Interface Registers ....................................................................................................
ASR0 to ASR3 (Area Select Register) ......................................................................................
ACR0 to ACR3 (Area Configuration Register) ...........................................................................
AWR0 to AWR3 (Area Wait Register) .......................................................................................
CSER (Chip Select Enable Register) ........................................................................................
Chip Select Area .............................................................................................................................
Endian and Bus Access ..................................................................................................................
Relationship between Data Bus Width and Control Signal ........................................................
Bus Access ................................................................................................................................
External Access .........................................................................................................................
Ordinary Bus Interface ....................................................................................................................
Address/Data Multiplex Interface ....................................................................................................
DMA Access ...................................................................................................................................
Procedure for Setting Registers ......................................................................................................
CHAPTER 6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
RESET ...................................................................................................... 125
Overview of Reset ..........................................................................................................................
Reset Factors and Oscillation Stabilization Wait Times .................................................................
Reset Levels ...................................................................................................................................
External Reset Pin ..........................................................................................................................
Reset Operation ..............................................................................................................................
Reset Factor Bit ..............................................................................................................................
State of Each Pin at Reset ..............................................................................................................
184
186
188
204
206
208
211
INTERRUPT CONTROLLER ................................................................... 213
7.1
Overview of the Interrupt Controller ................................................................................................
7.2
Interrupt Controller Registers ..........................................................................................................
7.2.1
Interrupt Control Register (ICR) .................................................................................................
7.2.2
Hold Request Cancellation Request Level Setting Register (HRCL) ........................................
vi
214
217
218
219
7.3
Interrupt Controller Operation ......................................................................................................... 220
CHAPTER 8
EXTERNAL INTERRUPT ......................................................................... 227
8.1
Overview of the External Interrupt ..................................................................................................
8.2
External Interrupt Registers ............................................................................................................
8.2.1
Interrupt Enable Register (ENIR) ...............................................................................................
8.2.2
External Interrupt Factor Register (EIRR) .................................................................................
8.2.3
External Interrupt Request Level Setting Register (ELVR) ........................................................
8.3
Operation of the External Interrupt .................................................................................................
CHAPTER 9
228
229
230
231
232
233
REALOS-RELATED HARDWARE .......................................................... 237
9.1
Delayed Interrupt Module ...............................................................................................................
9.1.1
Overview of the Delayed Interrupt Module ................................................................................
9.1.2
Delayed Interrupt Module Registers ..........................................................................................
9.1.3
Operation of the Delayed Interrupt Module ...............................................................................
9.2
Bit Search Module ..........................................................................................................................
9.2.1
Overview of the Bit Search Module ...........................................................................................
9.2.2
Bit Search Module Registers .....................................................................................................
9.2.3
Bit Search Module Operation ....................................................................................................
238
239
240
241
242
243
244
246
CHAPTER 10 DMA CONTROLLER (DMAC) .................................................................. 249
10.1 Overview of the DMA Controller (DMAC) .......................................................................................
10.2 Register Details Explanation ...........................................................................................................
10.2.1 Control/Status Registers A (DMACA0 to DMACA4) ..................................................................
10.2.2 Control/Status Registers B (DMACB0 to DMACB4) ..................................................................
10.2.3 Transfer Source/Transfer Destination Address Setting Registers
(DMASA0 to DMASA4/DMADA0 to DMADA4) ..........................................................................
10.2.4 All-Channel Control Register (DMACR) ....................................................................................
10.3 DMA Controller Operation ..............................................................................................................
10.3.1 DMA Controller Operation .........................................................................................................
10.3.2 Setting up Transfer Requests ....................................................................................................
10.3.3 Transfer Sequence ....................................................................................................................
10.3.4 General Aspects of DMA Transfer .............................................................................................
10.3.5 Addressing Mode .......................................................................................................................
10.3.6 Data Types ................................................................................................................................
10.3.7 Control of the Transfer Count ....................................................................................................
10.3.8 CPU Control ..............................................................................................................................
10.3.9 Operation Start ..........................................................................................................................
10.3.10 Transfer Request Acceptance and Transfer ..............................................................................
10.3.11 Clearing Peripheral Interrupts by DMA ......................................................................................
10.3.12 Temporary Stopping ..................................................................................................................
10.3.13 Operation End/Stopping ............................................................................................................
10.3.14 Stopping Due To an Error ..........................................................................................................
10.3.15 DMAC Interrupt Control .............................................................................................................
10.3.16 DMA Transfer during Sleep Mode .............................................................................................
10.3.17 Channel Selection and Control ..................................................................................................
10.4 Operation Flowcharts ......................................................................................................................
vii
250
253
254
258
264
266
268
269
271
272
274
275
276
277
278
279
280
281
282
283
284
285
286
287
289
10.5
Data Path ........................................................................................................................................ 291
CHAPTER 11 CAN CONTROLLER ................................................................................ 293
11.1 Feature of CAN ...............................................................................................................................
11.2 CAN Block Diagram ........................................................................................................................
11.3 Register of CAN ..............................................................................................................................
11.4 Functions of CAN Registers ...........................................................................................................
11.4.1 Overall Control Registers ..........................................................................................................
11.4.1.1 CAN Control Registers (CTRLR0, CTRLR1) ..........................................................................
11.4.1.2 CAN Status Register (STATR) ...............................................................................................
11.4.1.3 CAN Error Counter (ERRCNT0 to ERRCNT2) .......................................................................
11.4.1.4 CAN Bit Timing Register (BTR0 to BTR2) ..............................................................................
11.4.1.5 CAN Interrupt Register (INTR0 to INTR2) ..............................................................................
11.4.1.6 CAN Test Register (TESTR0 to TESTR2) ..............................................................................
11.4.1.7 BRP Extension Register (BRPER0 to BRPER2) ....................................................................
11.4.2 Message Interface Register .......................................................................................................
11.4.2.1 IFx Command Request Register (IFxCREQ) .........................................................................
11.4.2.2 IFx Command Mask Register (IFxCMSK) ..............................................................................
11.4.2.3 IFx Mask Register 1 and 2 (IFxMSK1, IFxMSK2) ...................................................................
11.4.2.4 IFx Arbitration Register 1 and 2 (IFxARB1, IFxARB2) ............................................................
11.4.2.5 IFx Message Control Register (IFxMCTR) .............................................................................
11.4.2.6 IFx Data Register A1,A2,B1,B2(IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2) .............................
11.4.3 Message Object .........................................................................................................................
11.4.4 Message Handler Register ........................................................................................................
11.4.4.1 CAN Transmission Request Register (TREQR1, TREQR2) ..................................................
11.4.4.2 CAN New Data Register (NEWDT1, NEWDT2) .....................................................................
11.4.4.3 CAN Interrupt Pending Register (INTPND1, INTPND2) .........................................................
11.4.4.4 CAN Message Valid Register (MSGVAL1, MSGVAL2) ..........................................................
11.4.5 CAN Prescaler Register (CANPRE) ..........................................................................................
11.5 CAN Functions ................................................................................................................................
11.5.1 Message Object .........................................................................................................................
11.5.2 Message Transmission Operation .............................................................................................
11.5.3 Message Reception Operation ..................................................................................................
11.5.4 FIFO Buffer Function .................................................................................................................
11.5.5 Interrupt Function ......................................................................................................................
11.5.6 Bit Timing ...................................................................................................................................
11.5.7 Test Mode ..................................................................................................................................
11.5.8 Software Initialization .................................................................................................................
11.5.9 CAN Clock Prescaler .................................................................................................................
294
295
296
300
301
302
305
308
309
310
311
313
314
315
317
322
323
324
325
326
331
332
334
336
338
340
341
342
344
346
349
351
352
355
359
360
CHAPTER 12 LIN-UART ................................................................................................. 363
12.1 Overview .........................................................................................................................................
12.2 Configuration of UART ....................................................................................................................
12.3 Register of UART ............................................................................................................................
12.3.1 Serial Control Register (SCR) ...................................................................................................
12.3.2 Serial Mode Register (SMR) ......................................................................................................
12.3.3 Serial Status Register (SSR) .....................................................................................................
viii
364
367
372
374
377
380
12.3.4 Reception/Transmission Data Register (RDR/TDR) ..................................................................
12.3.5 Extended Status/Control Register (ESCR) ................................................................................
12.3.6 Extended Communication Control Register (ECCR) .................................................................
12.3.7 Baud Rate/Reload Counter Register (BGR) ..............................................................................
12.4 UART Interrupt ................................................................................................................................
12.4.1 Generation of Reception Interrupt and Flag Set Timing ............................................................
12.4.2 Transmission Interrupt Generation and Flag Timing .................................................................
12.5 UART Baud Rate ............................................................................................................................
12.5.1 Setting the Baud Rate ...............................................................................................................
12.5.2 Restart of the Reload Counter ...................................................................................................
12.6 Operation of UART ........................................................................................................................
12.6.1 Operation in the Asynchronous Mode (Operation Mode 0 and Mode 1) ...................................
12.6.2 Operation in the Synchronous Mode (Operation Mode 2) .........................................................
12.6.3 Operating in LIN Function (Operation Mode 3) .........................................................................
12.6.4 Direct Access to Serial Pins ......................................................................................................
12.6.5 Bidirectional Communication Function (Normal Mode) .............................................................
12.6.6 Master-Slave Communication Function (Multiprocessor Mode) ................................................
12.6.7 LIN Communication Function ....................................................................................................
12.6.8 LIN Communication Mode (Operation Mode 3) UART Sample Flowchart ................................
12.7 Precautions when Using UART ......................................................................................................
383
385
388
391
392
395
397
399
401
404
406
408
410
413
417
418
420
423
425
428
CHAPTER 13 I2C INTERFACE ....................................................................................... 431
13.1 Outline of I2C Interface ...................................................................................................................
13.2 I2C Interface Register .....................................................................................................................
13.2.1 Bus Status Register (IBSR0 to IBSR2) ......................................................................................
13.2.2 Bus Control Register (IBCR0 to IBCR2) ....................................................................................
13.2.3 Clock Control Register (ICCR0 to ICCR2) ................................................................................
13.2.4 10-bit Slave Address Register (ITBAH0 to ITBAH2, ITBAL0 to ITBAL2) ..................................
13.2.5 10-bit Slave Address Mask Register (ITMKH0 to ITMKH2, ITMKL0 to ITMKL2) .......................
13.2.6 7-bit Slave Address Register (ISBA0 to ISBA2) ........................................................................
13.2.7 7-bit Slave Address Mask Register (ISMK0 to ISMK2) .............................................................
13.2.8 Data Register (IDAR0 to IDAR2) ...............................................................................................
13.3 Operation Explanation of I2C Interface ...........................................................................................
13.4 Operation Flowcharts ......................................................................................................................
432
436
437
440
447
449
450
452
453
454
455
460
CHAPTER 14 16-BIT RELOAD TIMER ........................................................................... 463
14.1 Overview of the 16-bit Reload Timer ..............................................................................................
14.2
Registers of the 16-bit Reload Timer .............................................................................................
14.2.1 Control Status Registers (TMCSR) ...........................................................................................
14.2.2 16-bit Timer Register (TMR) ......................................................................................................
14.2.3 16-bit Reload Register (TMRLR) ...............................................................................................
14.3 Operation of 16-bit Reload Timer ...................................................................................................
464
465
466
469
470
471
CHAPTER 15 16-BIT FREE-RUN TIMER ....................................................................... 475
15.1 Overview of 16-bit Free-run Timer .................................................................................................. 476
15.2 16-bit Free-run Timer Registers ...................................................................................................... 477
15.2.1 Timer Data Register (TCDT) ..................................................................................................... 478
ix
15.2.2 Timer Control Status Register (TCCS) ...................................................................................... 479
15.3 Operation of 16-bit Free-run Timer ................................................................................................. 482
15.4 Notes on Using the 16-bit Free-run Timer ...................................................................................... 484
CHAPTER 16 INPUT CAPTURE ..................................................................................... 485
16.1 Overview of the Input Capture ........................................................................................................
16.2 Input Capture Registers ..................................................................................................................
16.2.1 Input Capture Register (IPCP) ...................................................................................................
16.2.2 Input Capture Control Register (ICS) ........................................................................................
16.3 Operation of Input Capture .............................................................................................................
486
487
488
489
490
CHAPTER 17 OUTPUT COMPARE ................................................................................ 491
17.1 Overview of the Output Compare ...................................................................................................
17.2 Registers of the Output Compare ...................................................................................................
17.2.1 Compare Register (OCCP) ........................................................................................................
17.2.2 Control Register (OCS) .............................................................................................................
17.3 Output Compare Operation ............................................................................................................
492
493
494
495
497
CHAPTER 18 PPG TIMER .............................................................................................. 501
18.1 Overview .........................................................................................................................................
18.2 Block Diagram ................................................................................................................................
18.3 PPG Register ..................................................................................................................................
18.3.1 PPG Operation Mode Control Register (PPGC) ........................................................................
18.3.2 Reload Registers (PRLL/PRLH) ................................................................................................
18.3.3 PPG Starting Register (TRG) ....................................................................................................
18.3.4 Output Inverted Register (REVC) ..............................................................................................
18.4 Operation Explanation ....................................................................................................................
502
503
506
507
509
510
511
512
CHAPTER 19 UP/DOWN COUNTER .............................................................................. 519
19.1 Overview of Up/Down Counter .......................................................................................................
19.2 Register of Up/Down Counter .........................................................................................................
19.2.1 Up/Down Count Register (UDCR) .............................................................................................
19.2.2 Reload Compare Register (RCR) ..............................................................................................
19.2.3 Counter Status Register (CSR) .................................................................................................
19.2.4 Counter Control Register (CCR) ................................................................................................
19.3 Operation of Up/Down Counters .....................................................................................................
520
523
524
525
526
528
531
CHAPTER 20 CLOCK MONITOR ................................................................................... 541
20.1
20.2
Overview of Clock Monitor .............................................................................................................. 542
Clock Output Enable Register ........................................................................................................ 544
CHAPTER 21 REAL TIME CLOCK ................................................................................. 545
21.1
21.2
21.3
21.4
21.5
Configuration of Registers ..............................................................................................................
Block Diagram ................................................................................................................................
Details of Registers .........................................................................................................................
Clock Calibration Unit .....................................................................................................................
Register of Clock Calibration Unit ...................................................................................................
x
546
548
549
554
555
21.5.1 Calibration Unit Control Register (CUCR) .................................................................................
21.5.2 Sub Timer Data Register (CUTD) ..............................................................................................
21.5.3 Main Timer Data Register (CUTR) ............................................................................................
21.6 Using of Clock Calibration Unit .......................................................................................................
556
558
560
561
CHAPTER 22 A/D CONVERTER .................................................................................... 563
22.1 Overview of A/D Converter .............................................................................................................
22.2 Block Diagram of the A/D Converter ...............................................................................................
22.3 Registers of A/D Converter .............................................................................................................
22.3.1 Analog Input Enable Register (ADER) ......................................................................................
22.3.2 A/D Control Status Register (ADCS) .........................................................................................
22.3.3 Data Register (ADCR1, ADCR0) ...............................................................................................
22.3.4 Conversion Time Setting Register (ADCT) ...............................................................................
22.3.5 Start Channel Setting Register (ADSCH) End Channel Setting Register (ADECH) .................
22.4 Operation of A/D Converter ............................................................................................................
564
565
566
568
569
575
576
578
580
CHAPTER 23 D/A CONVERTER .................................................................................... 583
23.1
23.2
23.3
Overview of D/A Converter ............................................................................................................. 584
Registers of D/A Converter ............................................................................................................. 585
Operation of the D/A Converter ...................................................................................................... 589
CHAPTER 24 CLOCK MODULATOR ............................................................................. 591
24.1 Overview of Clock Modulator ..........................................................................................................
24.2 Registers of Clock Modulator ..........................................................................................................
24.2.1 Clock Modulator Parameter Register (CMPR) ..........................................................................
24.2.2 Clock Modulator Control Register (CMCR) ...............................................................................
592
593
594
595
CHAPTER 25 CLOCK SUPERVISOR ............................................................................. 597
25.1
25.2
25.3
Overview of Clock Supervisor ......................................................................................................... 598
Clock Supervisor Control Register (CSVCR) .................................................................................. 599
Clock Supervisor Operation ............................................................................................................ 602
CHAPTER 26 FLASH MEMORY ..................................................................................... 605
26.1 Outline of Flash Memory .................................................................................................................
26.2 Flash Memory Registers .................................................................................................................
26.2.1 FLASH Control/Status Registers (FLCR) .................................................................................
26.2.2 Wait Register (FLWC) ...............................................................................................................
26.3 Explanation of Flash Memory Operation .......................................................................................
26.4 Automatic Algorithm of Flash Memory ............................................................................................
26.4.1 Command Sequence .................................................................................................................
26.4.2 Check the Execution State of Automatic Algorithm ...................................................................
26.5 Writing to and Erasing from Flash Memory ....................................................................................
26.5.1 Read/Reset Status ....................................................................................................................
26.5.2 Data Writing ...............................................................................................................................
26.5.3 Data Erase (Chip Erase) ...........................................................................................................
26.5.4 Data Erase (Sector Erase) ........................................................................................................
26.5.5 Temporary Sector Erase Stop ...................................................................................................
xi
606
609
610
612
614
616
617
621
626
627
628
630
631
633
26.5.6 Sector Erase Restart ................................................................................................................. 634
26.6 Wild Register .................................................................................................................................. 635
26.7 Notes on Flash Memory Programming ........................................................................................... 636
CHAPTER 27 HARDWARE WATCHDOG TIMER .......................................................... 637
27.1
27.2
27.3
27.4
27.5
Overview of Hardware Watchdog Timer .........................................................................................
Configuration of Hardware Watchdog Timer ..................................................................................
Hardware Watchdog Timer Registers .............................................................................................
Function of Hardware Watchdog Timer ..........................................................................................
Precautions .....................................................................................................................................
638
639
640
641
642
APPENDIX ......................................................................................................................... 643
APPENDIX A
APPENDIX B
APPENDIX C
APPENDIX D
APPENDIX E
I/O Map ................................................................................................................................
Interrupt Vector ....................................................................................................................
Pin States in Each CPU State ..............................................................................................
Programming Example of Serial Programming (Asynchronous) .........................................
Programming Example of Serial Programming (Synchronous) ...........................................
644
661
664
680
683
INDEX................................................................................................................................... 691
xii
Main changes in this edition
Page
-
Changes (For details, refer to main body.)
First edition
xiii
xiv
CHAPTER 1
OVERVIEW
FR family is a standard single-chip microcontroller that
has a 32-bit high-performance RISC CPU as well as builtin I/O resources and bus control mechanisms for
embedded controller requiring high-performance and
high-speed CPU processing.
1.1 Features
1.2 Block Diagram
1.3 Package Dimension
1.4 Pin Assignment
1.5 Memory Map
1.6 Description of Pin Function
1.7 I/O Circuit Type
1
CHAPTER 1 OVERVIEW
1.1
Features
This section describes the features of MB91270 series.
■ Feature of FR CPU
• 32 bits RISC, load/store architecture and five steps in pipeline
• Maximum operating frequency: 32MHz [use of PLL: when source oscillation is 4MHz]
• 16-bit fixed length instruction (basic instruction), one instruction/one cycle
• Memory to memory transfer, bit processing and instruction of barrel shift and so on.
- Instruction suitable for embedded application
• Function entry and exit instructions, multi load/store instructions of register content
- Instructions compatible with high-level languages
• Register interlock function
- Simplification of assembler description
• Built-in multiplier/instruction-level support
- 32-bit multiplication with sign : Five cycles
- 16-bit multiplication with sign : Three cycles
• Interruption (save of PC and PS): Six cycles and 16 priority levels
• Harvard architecture enabling simultaneous execution of both program access and data access
• The instruction is interchangeable with the FR family.
■ External Bus Interface
• Maximum operating frequency 16MHz
• 24-bit address full output enable (16MB space)
• 8- and 16-bit data output
• Unused data and address pins are usable as a general I/O port.
• Totally independent 4-area chip select output that can be defined at a minimum of 64 KB
• Support in interface to various memories
SRAM, ROM/FLASH
• Basic bus cycle: Two cycles
• Automatic wait cycle generator that can be programmed for each area and can insert waits
• External wait cycle by RDY input
2
CHAPTER 1 OVERVIEW
■ Built-in Memory
Table 1.1-1 shows the details of built-in memory.
Table 1.1-1 Details of Internal Memory
Built-in ROM/FLASH
F bus RAM
MB91V280
MB91F273(S)
MB91F278(S)
External SRAM
FLASH 512KB
FLASH 512KB
48KB
24KB
24KB
Overview of peripheral circuit is described in the following.
Check Table 1.1-2 for built-in channel number of each product.
■ DMAC (DMA Controller)
• Maximum 5 channels can be operated simultaneously.
• Two forwarding factors (internal peripheral/software)
■ Bit Search Module (Using REALOS)
• Searches for the position of the first bit varying between 1 and 0 in the MSB of a word
■ UART which Supports for LIN: Maximum 7 Channels
• Asynchronous (Start-Stop synchronous) communication, clock synchronous communication
• Synch-break detection
• Baud rate generator is installed in each channel.
• Can be for SPI (Mode 2: clock synchronous communication mode)
■ CAN Controller: Maximum 3 Channels
• Maximum transferring rate: 1Mbps
• 32 message buffers (128 message buffers in MB91V280)
■ Timers
• 16-bit reload timer 3 channels (including 1 ch for REALOS)
Internal clock is selectable from 2/8/32-division.
• 16-bit free-run timer: 4 channels
Output compare: 8 channels
Input capture: 8 channels
• 8/16-bit PPG: 8 bits × 16 channels or 16 bits × 8 channels
3
CHAPTER 1 OVERVIEW
■ Interrupt Controller: Maximum 40 Channels
• Interruption from internal peripheral
• Priority level is settable by software (16 levels).
■ D/A Converter: 2 Channels (MB91V280 Only)
• 8-/10-bit resolution, R-2R type
■ A/D Converter: 24 Channels (in MB91V280, Support +8 Channels as Independent
Module)
• 10-bit resolution
• Successive conversion type
Conversion time: 3µs
• Conversion mode (Single conversion mode and serial conversion mode)
• Start-up factor (soft, external trigger and peripheral interrupt)
■ Other Interval Timer/Counter
• 8/16-bit up/down counter:
8-bit × 4 channels or 16-bit × 2 channels
• 16-bit time-base timer/ watchdog timer
■ I2C Interface (Supported for 400Kbps) : 3 Channels
• Master/slave transmission and reception
• Arbitration function and clock synchronization function
■ Hardware Watchdog
• Interval time: 569ms(min), 771ms(max)
* Use of self-oscillation circuit with trimming (100 kHz)
■ I/O Port
• Each pin can control pull-up or pull-down.
• Each pin can select CMOS Schmitt trigger or CMOS automotive Schmitt trigger as input level.
• Direct read of pin level is enabled.
• Maximum 128 ports
4
CHAPTER 1 OVERVIEW
■ Other Features
• Internal oscillation circuit is provided as a clock source. PLL multiplication can also be selected.
• INIT is prepared as a reset terminal.
• Additionally, a watchdog timer reset and software reset are provided.
• Support for stop mode, sleep mode and real time clock mode as low-power consumption mode.
Low-power consumption by 32kHz CPU operation is enabled. (only for products without "S" type)
• Gear function
• Built-in time-base timer
• Wild register
• Clock output (clock monitor)
• Clock modulator
• Clock supervisor
The stop of the main clock is supervised by the internal self-oscillation.
• Package: LQFP-100
• CMOS technology (0.35µm)
• Power supply voltage: 3.5V to 5.5V
Internal circuit is supplied 3.3 V by the built-in step-down circuit.
5
CHAPTER 1 OVERVIEW
■ Comparison of Functions
Table 1.1-2 shows the comparison of functions in MB91270 series.
Table 1.1-2 Comparison of Functions
MB91V280
Package
Built-in ROM/FLASH
RAM
External bus
External interrupt
MB91F273(S)
PGA-401
LQFP-100
External SRAM
FLASH 512KB
48KB
24KB
Address: 24 bits
Data: 16 bits
Address: 24 bits
Data: 16 bits
(only for multiplex)
40channels
16channels
DMA controller
5channels
Clock modulator
Yes
Clock supervisor
Yes
Clock monitor
32kHz sub clock
No
Yes
Option (only for products without "S" type)
Yes
3channels (128 message
buffer)
LIN corresponded UART
1channel (32 message buffer)
7channels
2
I C interface
3channels
16-bit reload timer
3channels
8-/16-bit up/down counter
2channels
16-bit free-run timer
4channels
Input capture
8channels
Output compare
8channels
8channels × 16-bit
16channels × 8-bit
8-/16-bit PPG
10-bit A/D converter
Yes
Yes
Real time clock
CAN controller
MB91F278(S)
24channels + 8channels
24channels
2channels
None
Pin pull-up/pull-down
All pins
Refer to the Section "1.6 Description of Pin Function".
Input level selector
All pins
Refer to the Section "1.6 Description of Pin Function".
DSU4
Wild register
8-/10-bit D/A converter
Debug support
6
CHAPTER 1 OVERVIEW
1.2
Block Diagram
This section shows the block diagram of MB91270 series.
■ Block Diagram of the MB91270 Series
Figure 1.2-1 Block Diagram of the MB91270 Series
FR60 Lite
CPU Core
Clock generator
Watchdog timer
Voltage regulator
32
32
I-bus
Bit search
module
D-bus
FLASH memory/
MASK ROM
Debug support
32
DMA controller
Harvard bus
converter
F-bus
32
F-busRAM
32
External bus
24-bit address
16-bit data
External bus
interface
CAN
R-bus
adaptor
16
Clock
supervisor
DAC*
Hardware
watchdog
ADC
R-bus
Sub clock
LINUART
Reload timer
ICU
16-bit
Clock monitor
Free-run timer
Real time clock
OCU
16-bit
I2C
400kHz
External interrupt
Up/down counter
8/16-bit
PPG
8/16-bit
*: Only for MB91V280
7
CHAPTER 1 OVERVIEW
1.3
Package Dimension
This section shows the package dimensions of MB91270 series.
■ LQFP 100-pin
Figure 1.3-1 Package Dimension of FPT-100P-M5
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.0 × 14.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.65g
Code
(Reference)
P-LFQFP100-14 × 14-0.50
(FPT-100P-M05)
100-pin plastic LQFP
(FPT-100P-M05)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
100
26
C
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
25
1
0.20±0.05
(.008±.002)
0.08(.003)
M
0.145±0.055
(.0057±.0022)
2003 FUJITSU LIMITED F100007S-c-4-6
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
8
0.10±0.10
(.004±.004)
(Stand off)
0°~8°
"A"
0.50(.020)
+.008
1.50 –0.10 .059 –.004
(Mounting height)
INDEX
CHAPTER 1 OVERVIEW
1.4
Pin Assignment
This section shows the pin assignments of MB91270 series.
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P25/A21/IN1
P24/A20/IN0
P23/A19/PPGF
P22/A18/PPGD
P21/A17/PPGB
P20/A16/PPG9
P17/AD15/SCK4
P16/AD14/SOT4
P15/AD13/SIN4
X0
X1
VSS
VCC
P14/AD12/SCK3
P13/AD11/SOT3
P12/AD10/SIN3/INT11R
P11/AD09/TOT1
P10/AD08/TIN1
P07/AD07/INT15
P06/AD06/INT14
P05/AD05/SCK6/INT13
P04/AD04/SOT6/INT12
P03/AD03/SIN6/INT11
P02/AD02/SCK5/INT10
P01/AD01/SOT5/INT9
■ LQFP 100-pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P00/AD00/SIN5/INT8
PA1/TX0
PA0/RX0/INT8R
P97/OUT3
P96/OUT2/ZIN0
P95/OUT1/BIN0
P94/OUT0/AIN0
P93/PPG7/ZIN3/CS3
P92/PPG5/BIN3/CS2
P91/PPG3/AIN3/CS1
P90/PPG1/CS0
VSS
VCC
P87/SCK1
P86/SOT1
P85/SIN1
P84/SCK0/INT15R
P83/TOT2/SOT0
P82/TIN2/SIN0/INT14R
P81/TOT0/INT13R/CKOT
P80/TIN0/INT12R/ADTG
P77/AN23/INT7/SCL2
P76/AN22/INT6/SDA2
INIT
MD0
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P54/AN12/AIN1
P55/AN13/ZIN1
P56/AN14/DAO0
P57/AN15/DAO1
AVCC
AVRH
AVRL
AVSS
P60/AN0/PPG0
P61/AN1/PPG2
P62/AN2/PPG4
P63/AN3/PPG6
P64/AN4/PPG8
P65/AN5/PPGA
P66/AN6/PPGC
P67/AN7/PPGE
VSS
P70/AN16/INT0
P71/AN17/INT1
P72/AN18/INT2
P73/AN19/INT3
P74/AN20/INT4
P75/AN21/INT5
MD2
MD1
P26/A22/IN2
P27/A23/IN3
P30/AS/IN4
P31/RD/IN5
P32/WR0/RX2/INT10R
P33/WR1/TX2
P34/BRQ/OUT4
P35/BGRNT/OUT5
P36/RDY/OUT6
P37/SYSCLK/OUT7
P40/(X0A)
P41/(X1A)
VCC
VSS
C
P42/IN6/RX1/INT9R
P43/IN7/TX1
P44/SDA0/FRCK0
P45/AIN2/SCL0/FRCK1
P46/BIN2/SDA1
P47/ZIN2/SCL1
P50/AN8/SIN2
P51/AN9/SOT2
P52/AN10/SCK2
P53/AN11/BIN1
9
CHAPTER 1 OVERVIEW
1.5
Memory Map
This section shows the memory map of MB91270 series.
■ Memory Map of MB91270 Series
Figure 1.5-1 Memory Map of MB91270 Series
0000 0000H
MB91V280
MB91F273(S)
MB91F278(S)
I/O
I/O
I/O
I/O
Access prohibited
Access prohibited
CAN
CAN
Direct addressing area
Refer to I/O map
0000 0400H
0000 0000H
0001 0000H
0002 0000H
0002 0500H
Access prohibited
Access
prohibited
0003 4000H
0003 A000H
Built-in
RAM48KB
0003 D800H
Built-in
RAM24KB
0004 0000H
Access
prohibited
Access
prohibited
Emulation
RAM area
FLASH
512KB
External area
External area
0008 0000H
0010 0000H
FFFF FFFFH
Note:
The initial value for emulation SRAM area of MB91V280 is 512KB(0x80000-0x100000). The area up
to 1024KB(0x50000-0x150000) is supported as SRAM area.
10
CHAPTER 1 OVERVIEW
1.6
Description of Pin Function
This section shows the description of pin function.
■ Description of Pin Function
Table 1.6-1 Description of Pin Function (1 / 13)
Function
I/O circuit
Pin No.
Pin name
name
type*
Function
90
X1
X1
OB
Oscillator output pin
91
X0
X0
OA
Oscillator input pin
52
INIT
INIT
N
Reset input pin (“L” active)
J
Operation mode select input pin.
Connect to VCC or VSS directly.
49 to 51
MD2 to MD0 MD2 to MD0
Port 0
General-purpose I/O ports.
This function is enabled in single-chip mode.
P00
75
76
P00/AD00/
SIN5/INT8
P01/AD01/
SOT5/INT9
AD00
T
INT8
External interrupt request 8 input pin
SIN5
Serial data input pin for LIN-UART5
P01
General-purpose I/O ports.
This function is enabled in single-chip mode.
AD01
T
P02/AD02/
SCK5/INT10
External interrupt request 9 input pin
SOT5
Serial data output pin for LIN-UART5
General-purpose I/O ports.
This function is enabled in single-chip mode.
AD02
T
P03/AD03/
SIN6/INT11
External address/data bus I/O pin bit 2
This function is enabled when the external bus is enabled.
INT10
External interrupt request 10 input pin
SCK5
Clock I/O pin for LIN-UART5
General-purpose I/O ports.
This function is enabled in single-chip mode.
P03
78
External address/data bus I/O pin bit 1
This function is enabled when the external bus is enabled.
INT9
P02
77
External address/data bus I/O pin bit 0
This function is enabled when the external bus is enabled.
AD03
T
External address/data bus I/O pin bit 3
This function is enabled when the external bus is enabled.
INT11
External interrupt request 11 input pin
SIN6
Serial data input pin for LIN-UART6
11
CHAPTER 1 OVERVIEW
Table 1.6-1 Description of Pin Function (2 / 13)
Function
I/O circuit
Pin No.
Pin name
name
type*
General-purpose I/O ports.
This function is enabled in single-chip mode.
P04
79
P04/AD04/
SOT6/INT12
AD04
T
P05/AD05/
SCK6/INT13
External interrupt request 12 input pin
SOT6
Serial data output pin for LIN-UART6
General-purpose I/O ports.
This function is enabled in single-chip mode.
AD05
T
P06/AD06/
INT14
External interrupt request 13 input pin
SCK6
Clock I/O pin for LIN-UART6
General-purpose I/O ports.
This function is enabled in single-chip mode.
AD06
T
INT14
P07/AD07/
INT15
AD07
External address/data bus I/O pin bit 6
This function is enabled when the external bus is enabled.
External interrupt request 14 input pin
General-purpose I/O ports.
This function is enabled in single-chip mode.
P07
82
External address/data bus I/O pin bit 5
This function is enabled when the external bus is enabled.
INT13
P06
81
External address/data bus I/O pin bit 4
This function is enabled when the external bus is enabled.
INT12
P05
80
Function
T
INT15
External address/data bus I/O pin bit 7
This function is enabled when the external bus is enabled.
External interrupt request 15 input pin
Port 1
General-purpose I/O ports.
This function is enabled in single-chip mode.
P10
83
84
P10/AD08/
TIN1
P11/AD09/
TOT1
AD08
T
TIN1
Event input pin for reload timer 1
P11
General-purpose I/O ports.
This function is enabled in single-chip mode.
AD09
T
TOT1
P12/AD10/
SIN3/
INT11R
AD10
SIN3
INT11R
12
External address/data bus I/O pin bit 9
This function is enabled when the external bus is enabled.
Output pin for reload timer 1
General-purpose I/O ports.
This function is enabled in single-chip mode.
P12
85
External address/data bus I/O pin bit 8
This function is enabled when the external bus is enabled.
T
External address/data bus I/O pin bit 10
This function is enabled when the external bus is enabled.
Serial data input pin for LIN-UART3
External interrupt request 11 input pin (Set by EISSR)
CHAPTER 1 OVERVIEW
Table 1.6-1 Description of Pin Function (3 / 13)
I/O circuit
Function
Pin No.
Pin name
type*
name
General-purpose I/O ports.
This function is enabled in single-chip mode.
P13
86
P13/AD11/
SOT3
AD11
T
SOT3
P14/AD12/
SCK3
AD12
General-purpose I/O ports.
This function is enabled in single-chip mode.
T
SCK3
93
P15/AD13/
SIN4
P16/AD14/
SOT4
AD13
General-purpose I/O ports.
This function is enabled in single-chip mode.
T
Serial data input pin for LIN-UART4
P16
General-purpose I/O ports.
This function is enabled in single-chip mode.
AD14
T
AD15
External address/data bus I/O pin bit 14
This function is enabled when the external bus is enabled.
Serial data output pin for LIN-UART4
General-purpose I/O ports.
This function is enabled in single-chip mode.
P17
P17/AD15/
SCK4
External address/data bus I/O pin bit 13
This function is enabled when the external bus is enabled.
SIN4
SOT4
94
External address/data bus I/O pin bit 12
This function is enabled when the external bus is enabled.
Clock I/O pin for LIN-UART3
P15
92
External address/data bus I/O pin bit 11
This function is enabled when the external bus is enabled.
Serial data output pin for LIN-UART3
P14
87
Function
T
SCK4
External address/data bus I/O pin bit 15
This function is enabled when the external bus is enabled.
Clock I/O pin for LIN-UART4
Port 2
General-purpose I/O ports.
This function is enabled in single-chip mode.
P20
95
P20/A16/
PPG9
A16
A
PPG9
Output pin for PPG9
General-purpose I/O ports.
This function is enabled in single-chip mode.
P21
96
P21/A17/
PPGB
A17
A
PPGB
P22/A18/
PPGD
A18
PPGD
External address bus output pin bit 17
This function is enabled when the external bus is enabled.
Output pin for PPGB
General-purpose I/O ports.
This function is enabled in single-chip mode.
P22
97
External address bus output pin bit 16
This function is enabled when the external bus is enabled.
A
External address bus output pin bit 18
This function is enabled when the external bus is enabled.
Output pin for PPGD
13
CHAPTER 1 OVERVIEW
Table 1.6-1 Description of Pin Function (4 / 13)
Function
I/O circuit
Pin No.
Pin name
name
type*
General-purpose I/O ports.
This function is enabled in single-chip mode.
P23
98
P23/A19/
PPGF
A19
A
PPGF
P24/A20/IN0
to
P27/A23/IN3
A20 to A23
External address bus output pin bit 19
This function is enabled when the external bus is enabled.
Output pin for PPGF
General-purpose I/O ports.
This function is enabled in single-chip mode.
P24 to P27
99, 100,
1, 2
Function
A
IN0 to IN3
External address bus output pin bits 20 to 23
This function is enabled when the external bus is enabled.
Data sample input pins for input capture ICU0 to ICU3
Port 3
General-purpose I/O ports.
This function is enabled in single-chip mode.
P30
3
4
5
P30/AS/IN4
P31/RD/IN5
P32/WR0/
RX2/INT10R
AS
A
IN4
Data sample input pin for input capture ICU4
P31
General-purpose I/O ports.
This function is enabled in single-chip mode.
RD
A
Data sample input pin for input capture ICU5
P32
General-purpose I/O ports.
This function is enabled in single-chip mode.
WR0
External data bus write strobe output pin. Enabled when the
external bus is enabled.
WR0 is used as the data write strobe for 8-bit access and as
the upper 8 bits of the data in 16-bit access.
A
CAN2 RX input pin (MB91V280 only)
INT10R
External interrupt request 10 input pin (Set by EISSR)
General-purpose I/O ports.
This function is enabled in single-chip mode.
P33
7
P33/WR1/
TX2
P34/BRQ/
OUT4
WR1
A
Write strobe output pin for lower 8 bits in external data bus
Enabled when the external bus is enabled and external bus
16-bit mode is selected.
TX2
CAN2 TX output pin (MB91V280 only)
P34
General-purpose I/O ports.
This function is enabled in single-chip mode.
BRQ
OUT4
14
External read strobe output pin
This function is enabled when the external bus is enabled.
IN5
RX2
6
External address strobe output pin
This function is enabled when the external bus is enabled.
T
(A)
External bus request input pin
Enabled when the external bus and the bus request functions are enabled.
(MB91V280 only)
Waveform output pin for output compare OCU4.
CHAPTER 1 OVERVIEW
Table 1.6-1 Description of Pin Function (5 / 13)
Function
I/O circuit
Pin No.
Pin name
name
type*
General-purpose I/O ports.
This function is enabled in single-chip mode.
P35
8
P35/
BGRNT/
OUT5
BGRNT
A
OUT5
P36/RDY/
OUT6
RDY
General-purpose I/O ports.
This function is enabled in single-chip mode.
T
OUT6
P37/
SYSCLK/
OUT7
SYSCLK
External ready input pin
Enabled when the external bus and the bus request functions are enabled.
Waveform output pin for output compare OCU6.
General-purpose I/O ports.
This function is enabled in single-chip mode.
P37
10
External bus acknowledge output pin
Enabled when the external bus and the bus request
functions are enabled.
(MB91V280 only)
Waveform output pin for output compare OCU5.
P36
9
Function
A
OUT7
External clock output pin
This function is enabled when the external bus is enabled.
Waveform output pin for output compare OCU7.
Port 4
11, 12
P40/ (X0A) ,
P41/ (X1A)
P40, P41
A
X0A, X1A
WA
WB
P42
16
P42/IN6/
RX1/INT9R
IN6
RX1
A
18
P44/SDA0/
FRCK0
IN7
A
20
P46/BIN2/
SDA1
Data sample input pin for input capture ICU7
TX1
CAN1 TX output pin (MB91V280 only)
P44
General-purpose I/O ports
SDA0
C
SCL0
FRCK1
Serial data I/O pin for I2C0
16-bit input/output timer 0 input pin
P45
19
CAN1 RX input pin (MB91V280 only)
General-purpose I/O ports
FRCK0
P45/AIN2/
SCL0/
FRCK1
Data sample input pin for input capture ICU6
External interrupt request 9 input pin (Set by EISSR)
P43
P43/IN7/TX1
Sub clock oscillator input pin
(without S-suffix models)
General-purpose I/O ports
INT9R
17
General-purpose I/O ports
(S-suffix models)
General-purpose I/O ports
C
Serial clock I/O pin for I2C0
16-bit input/output timer 1 input pin
AIN2
16/8-bit up-count input pin for up down counter 2/3
P46
General-purpose I/O ports
SDA1
BIN2
C
Serial clock I/O pin for I2C1
16/8-bit down-count input pin for up down counter 2/3
15
CHAPTER 1 OVERVIEW
Table 1.6-1 Description of Pin Function (6 / 13)
Function
I/O circuit
Pin No.
Pin name
name
type*
P47
21
P47/ZIN2/
SCL1
SCL1
Function
General-purpose I/O ports
C
ZIN2
Serial clock I/O pin for I2C1
16/8-bit reset input pin for up down counter 2/3
Port 5
P50
22
23
P50/AN8/
SIN2
P51/AN9/
SOT2
AN8
General-purpose I/O ports
D
SIN2
Serial data input pin for LIN-UART2
P51
General-purpose I/O ports
AN9
D
SOT2
24
AN10
General-purpose I/O ports
D
SCK2
25
26
27
28
P54/AN12/
AIN1
P55/AN13/
ZIN1
P56/AN14/
DAO0
AN11
General-purpose I/O ports
D
8-bit down-count input pin for 16-bit up down counter 1
P54
General-purpose I/O ports
AN12
D
Analog input pin of A/D converter
AIN1
8-bit up-count input pin for 16-bit up down counter 1
P55
General-purpose I/O ports
AN13
D
Analog input pin of A/D converter
ZIN1
8-bit reset input pin for 16-bit up down counter 1
P56
General-purpose I/O ports
AN14
E
AN15
Analog input pin of A/D converter
Analog output pin 0 for D/A converter (MB91V280 only)
P57
29
Analog input pin of A/D converter
BIN1
DAO0
P57/AN15/
DAO1
Analog input pin of A/D converter
Clock I/O pin for LIN-UART2
P53
P53/AN11/
BIN1
Analog input pin of A/D converter
Serial data output pin for LIN-UART2
P52
P52/AN10/
SCK2
Analog input pin of A/D converter
General-purpose I/O ports
E
DAO1
Analog input pin of A/D converter
Analog output pin 1 for D/A converter (MB91V280 only)
Port 6
34 to 41
16
P60/AN0/
PPG0
to
P67/AN7/
PPGE
P60 to P67
General-purpose I/O ports
AN0 to AN7
Analog input pin of A/D converter
PPG0
PPG2
PPG4
PPG6
PPG8
PPGA
PPGC
PPGE
D
Output pin for PPG
CHAPTER 1 OVERVIEW
Table 1.6-1 Description of Pin Function (7 / 13)
Function
I/O circuit
Pin No.
Pin name
name
type*
Function
Port 7
43 to 48
P70/AN16/
INT0
to
P75/AN21/
INT5
P70 to P75
AN16 to
AN21
General-purpose I/O ports
D
INT0 to INT5
External interrupt request 0 to 5 input pin
P76
53
54
P76/AN22/
INT6/SDA2
P77/AN23/
INT7/SCL2
AN22
INT6
Analog input pin of A/D converter
General-purpose I/O ports
CA
Analog input pin of A/D converter
External interrupt request 6 input pin
SDA2
Serial data I/O pin for I2C2
P77
General-purpose I/O ports
AN23
INT7
CA
Analog input pin of A/D converter
External interrupt request 7 input pin
Serial clock I/O pin for I2C2
SCL2
Port 8
General-purpose I/O ports
P80
55
P80/TIN0/
INT12R/
ADTG
TIN0
ADTG
A
INT12R
56
TOT0
CKOT
General-purpose I/O ports
A
INT13R
57
SIN0
TIN2
A
SOT0
A
SCK0
General-purpose I/O ports
A
INT15R
60
P85/SIN1
61
P86/SOT1
62
P87/SCK1
P85
SIN1
P86
SOT1
P87
SCK1
Serial data output pin for LIN-UART0
Output pin for reload timer 2
P84
59
Event input pin for reload timer 2
General-purpose I/O ports
TOT2
P84/SCK0/
INT15R
Serial data input pin for LIN-UART0
External interrupt request 14 input pin (Set by EISSR)
P83
58
Output pin for clock monitor
General-purpose I/O ports
INT14R
P83/TOT2/
SOT0
Output pin for reload timer 0
External interrupt request 13 input pin (Set by EISSR)
P82
P82/TIN2/
SIN0/
INT14R
Trigger input pin for A/D converter
External interrupt request 12 input pin (Set by EISSR)
P81
P81/TOT0/
INT13R/
CKOT
Event input pin for reload timer 0
Clock I/O pin for LIN-UART0
External interrupt request 15 input pin (Set by EISSR)
A
A
A
General-purpose I/O ports
Serial data input pin for LIN-UART1
General-purpose I/O ports
Serial data output pin for LIN-UART1
General-purpose I/O ports
Clock I/O pin for LIN-UART1
17
CHAPTER 1 OVERVIEW
Table 1.6-1 Description of Pin Function (8 / 13)
Function
I/O circuit
Pin No.
Pin name
name
type*
Function
Port 9
P90
65
P90/PPG1/
CS0
CS0
General-purpose I/O ports
A
PPG1
Output pin for PPG1
P91
66
67
68
69
70
71
P91/PPG3/
AIN3/CS1
P92/PPG5/
BIN3/CS2
P93/PPG7/
ZIN3/CS3
P94/OUT0/
AIN0
P95/OUT1/
BIN0
P96/OUT2/
ZIN0
CS1
General-purpose I/O ports
A
P97/OUT3
External chip select 1
This function is enabled when the external bus is enabled.
PPG3
Output pin for PPG3
AIN3
8-bit up-count input pin for up down counter 3
P92
General-purpose I/O ports
CS2
External chip select 2
This function is enabled when the external bus is enabled.
A
PPG5
Output pin for PPG5
BIN3
8-bit down-count input pin for up down counter 3
P93
General-purpose I/O ports
CS3
A
External chip select 3
This function is enabled when the external bus is enabled.
PPG7
Output pin for PPG7
ZIN3
8-bit reset input pin for up down counter 3
P94
General-purpose I/O ports
OUT0
A
Waveform output pin for output compare OCU0
AIN0
16/8-bit up-count input pin for up down counter 0/1
P95
General-purpose I/O ports
OUT1
A
Waveform output pin for output compare OCU1
BIN0
16/8-bit down-count input pin for up down counter 0/1
P96
General-purpose I/O ports
OUT2
A
ZIN0
72
External chip select 0
This function is enabled when the external bus is enabled.
P97
OUT3
Waveform output pin for output compare OCU2
16/8-bit reset input pin for up down counter 0/1
A
General-purpose I/O ports
Waveform output pin for output compare OCU3
Port A
PA0
73
PA0/RX0/
INT8R
RX0
General-purpose I/O ports
A
INT8R
74
18
PA1/TX0
PA1
TX0
RX input pin for CAN0
External interrupt request 8 input pin (Set by EISSR)
A
General-purpose I/O ports
TX output pin for CAN0
CHAPTER 1 OVERVIEW
Table 1.6-1 Description of Pin Function (9 / 13)
Function
I/O circuit
Pin No.
Pin name
name
type*
Function
Port B (MB91V280 only)
PB0
⎯
PB0
INT8-2
General-purpose I/O ports
A
SIN5-2
Serial data input pin for LIN-UART5 (Set by PFRB)
PB1
⎯
PB1
INT9-2
General-purpose I/O ports
A
SOT5-2
PB2
INT10-2
General-purpose I/O ports
A
SCK5-2
PB3
INT11-2
General-purpose I/O ports
A
SIN6-2
PB4
INT12-2
General-purpose I/O ports
A
SOT6-2
PB5
INT13-2
External interrupt request 12 input pin (Set by EPFRB)
Serial data output pin for LIN-UART6
PB5
⎯
External interrupt request 11 input pin (Set by EPFRB)
Serial data input pin for LIN-UART6 (Set by PFRB)
PB4
⎯
External interrupt request 10 input pin (Set by EPFRB)
Clock I/O pin for LIN-UART5 (set by PFRB)
PB3
⎯
External interrupt request 9 input pin (Set by EPFRB)
Serial data output pin for LIN-UART5
PB2
⎯
External interrupt request 8 input pin (Set by EPFRB)
General-purpose I/O ports
A
SCK6-2
External interrupt request 13 input pin (Set by EPFRB)
Clock I/O pin for LIN-UART6 (set by PFRB)
Port C (MB91V280 only)
PC0
⎯
PC0
OUT4-2
General-purpose I/O ports
A
INT0R
External interrupt request 0 input pin (Set by EISSR)
PC1
⎯
PC1
OUT5-2
General-purpose I/O ports
A
INT1R
PC2
SIN3-2
General-purpose I/O ports
A
INT2R
PC3
SOT3-2
General-purpose I/O ports
A
INT3R
PC4
SCK3-2
General-purpose I/O ports
A
INT4R
PC5
SIN4-2
INT5R
Clock I/O pin for LIN-UART3 (set by PFRC)
External interrupt request 4 input pin (Set by EISSR)
PC5
⎯
Serial data output pin for LIN-UART3
External interrupt request 3 input pin (Set by EISSR)
PC4
⎯
Serial data input pin for LIN-UART3 (Set by PFRC)
External interrupt request 2 input pin (Set by EISSR)
PC3
⎯
Output pin for output compare OCU5
External interrupt request 1 input pin (Set by EISSR)
PC2
⎯
Output pin for output compare OCU4
General-purpose I/O ports
A
Serial data input pin for LIN-UART4 (Set by PFRC)
External interrupt request 5 input pin (Set by EISSR)
19
CHAPTER 1 OVERVIEW
Table 1.6-1 Description of Pin Function (10 / 13)
Function
I/O circuit
Pin No.
Pin name
name
type*
PC6
⎯
PC6
SOT4-2
General-purpose I/O ports
A
INT6R
PC7
SCK4-2
Serial data output pin for LIN-UART4
External interrupt request 6 input pin (Set by EISSR)
PC7
⎯
Function
General-purpose I/O ports
A
INT7R
Clock I/O pin for LIN-UART4 (set by PFRC)
External interrupt request 7 input pin (Set by EISSR)
Port D (MB91V280 only)
PD0
⎯
PD0
INT16
General-purpose I/O ports
A
PPG9-2
Output pin for PPG9 (8)
PD1
⎯
PD1
INT17
General-purpose I/O ports
A
PPGB-2
PD2
INT18
General-purpose I/O ports
A
PPGD-2
PD3
INT19
General-purpose I/O ports
A
PPGF-2
⎯
⎯
⎯
PD4
PD5
PD6
PD7
INT20
External interrupt request 19 input pin
Output pin for PPGF (E)
PD4
⎯
External interrupt request 18 input pin
Output pin for PPGD (C)
PD3
⎯
External interrupt request 17 input pin
Output pin for PPGB (A)
PD2
⎯
External interrupt request 16 input pin
General-purpose I/O ports
A
External interrupt request 20 input pin
IN0-2
Input pin for input capture ICU0 (set by PFRD)
PD5
General-purpose I/O ports
INT21
A
External interrupt request 21 input pin
IN1-2
Input pin for input capture ICU1 (set by PFRD)
PD6
General-purpose I/O ports
INT22
A
External interrupt request 22 input pin
IN2-2
Input pin for input capture ICU2 (set by PFRD)
PD7
General-purpose I/O ports
INT23
A
IN3-2
External interrupt request 23 input pin
Input pin for input capture ICU3 (set by PFRD)
Port E (MB91V280 only)
PE0
⎯
PE0
A00
INT24
20
General-purpose I/O ports
A
External address bus output pin bit 0
This function is enabled when the external bus is enabled.
External interrupt request 24 input pin
CHAPTER 1 OVERVIEW
Table 1.6-1 Description of Pin Function (11 / 13)
Function
I/O circuit
Pin No.
Pin name
name
type*
PE1
⎯
PE1
A01
General-purpose I/O ports
A
INT25
PE2
A02
General-purpose I/O ports
A
INT26
PE3
A03
General-purpose I/O ports
A
INT27
PE4
A04
General-purpose I/O ports
A
INT28
PE5
A05
General-purpose I/O ports
A
INT29
PE6
A06
General-purpose I/O ports
A
INT30
PE7
A07
External address bus output pin bit 6
This function is enabled when the external bus is enabled.
External interrupt request 30 input pin
PE7
⎯
External address bus output pin bit 5
This function is enabled when the external bus is enabled.
External interrupt request 29 input pin
PE6
⎯
External address bus output pin bit 4
This function is enabled when the external bus is enabled.
External interrupt request 28 input pin
PE5
⎯
External address bus output pin bit 3
This function is enabled when the external bus is enabled.
External interrupt request 27 input pin
PE4
⎯
External address bus output pin bit 2
This function is enabled when the external bus is enabled.
External interrupt request 26 input pin
PE3
⎯
External address bus output pin bit 1
This function is enabled when the external bus is enabled.
External interrupt request 25 input pin
PE2
⎯
Function
General-purpose I/O ports
A
INT31
External address bus output pin bit 7
This function is enabled when the external bus is enabled.
External interrupt request 31 input pin
Port F (MB91V280 only)
PF0
⎯
PF0
A08
General-purpose I/O ports
A
INT32
External interrupt request 32 input pin
PF1
⎯
PF1
A09
INT33
External address bus output pin bit 8
This function is enabled when the external bus is enabled.
General-purpose I/O ports
A
External address bus output pin bit 9
This function is enabled when the external bus is enabled.
External interrupt request 33 input pin
21
CHAPTER 1 OVERVIEW
Table 1.6-1 Description of Pin Function (12 / 13)
Function
I/O circuit
Pin No.
Pin name
name
type*
PF2
⎯
PF2
A10
General-purpose I/O ports
A
INT34
PF3
A11
General-purpose I/O ports
A
INT35
PF4
A12
General-purpose I/O ports
A
INT36
PF5
A13
General-purpose I/O ports
A
INT37
PF6
A14
General-purpose I/O ports
A
INT38
PF7
A15
External address bus output pin bit 14
This function is enabled when the external bus is enabled.
External interrupt request 38 input pin
PF7
⎯
External address bus output pin bit 13
This function is enabled when the external bus is enabled.
External interrupt request 37 input pin
PF6
⎯
External address bus output pin bit 12
This function is enabled when the external bus is enabled.
External interrupt request 36 input pin
PF5
⎯
External address bus output pin bit 11
This function is enabled when the external bus is enabled.
External interrupt request 35 input pin
PF4
⎯
External address bus output pin bit 10
This function is enabled when the external bus is enabled.
External interrupt request 34 input pin
PF3
⎯
Function
General-purpose I/O ports
A
INT39
External address bus output pin bit 15
This function is enabled when the external bus is enabled.
External interrupt request 39 input pin
Port G (MB91V280 only)
22
⎯
PG0
⎯
PG1
⎯
PG2
⎯
PG3
⎯
PG4
⎯
PG5
⎯
PG6
PG0
AN24
PG1
AN25
PG2
AN26
PG3
AN27
PG4
AN28
PG5
AN29
PG6
AN30
D
D
D
D
D
D
D
General-purpose I/O ports
Analog input pin of A/D converter
General-purpose I/O ports
Analog input pin of A/D converter
General-purpose I/O ports
Analog input pin of A/D converter
General-purpose I/O ports
Analog input pin of A/D converter
General-purpose I/O ports
Analog input pin of A/D converter
General-purpose I/O ports
Analog input pin of A/D converter
General-purpose I/O ports
Analog input pin of A/D converter
CHAPTER 1 OVERVIEW
Table 1.6-1 Description of Pin Function (13 / 13)
Function
I/O circuit
Pin No.
Pin name
name
type*
⎯
PG7
PG7
AN31
Function
General-purpose I/O ports
D
Analog input pin of A/D converter
Power supply pin
13, 63, 88
VCC
⎯
⎯
Power supply (5 V) input pin
14, 42,
64, 89
VSS
⎯
⎯
Power supply (0 V) input pin
15
C
⎯
⎯
Power stabilization capacitance pin
30
AVCC
⎯
⎯
Analog power supply input pin
31
AVRH
⎯
⎯
Reference voltage input pin for the A/D converter
Ensure that a voltage greater than AVRH is applied to AVCC
when turning this power supply on or off.
32
AVRL
⎯
⎯
Low reference voltage input pin for the A/D converter
33
AVSS
⎯
⎯
Analog VSS input pin
*: See "1.7 I/O Circuit Type" for the I/O circuit type.
23
CHAPTER 1 OVERVIEW
■ I/O Pin Number
Table 1.6-2 I/O Pin Number
Package pin number
Pin name
LQFP100
X1
90
X0
91
INIT
52
P00 to P07
75 to 82
P10 to P14
83 to 87
P15 to P17
92 to 94
P20 to P25
95 to 100
P26, P27
1, 2
P30 to P33
3 to 6
P34, P35
7, 8
P36, P37
9, 10
P40, P41
11, 12
X0A, X1A *
[11, 12]
P42 to P47
16 to 21
P50 to P57
22 to 29
P60 to P67
34 to 41
P70 to P75
43 to 48
P76, P77
53, 54
P80 to P87
55 to 62
P90 to P93
65 to 68
P94 to P97
69 to 72
PA0, PA1
73, 74
AVCC
30
AVRH
31
AVRL
32
AVSS
33
MD2 to MD0
49 to 51
VCC
13, 63, 88
VSS
14, 42, 64, 89
C
15
*: X0A and X1A are the option pins (for 32kHz sub-clock).
24
CHAPTER 1 OVERVIEW
1.7
I/O Circuit Type
This section shows I/O circuit.
■ I/O Cell List
Table 1.7-1 I/O Cell List
Input
Analog
line
Output
driver
Comment
Stops
-
4mA
-
CS/A switch
Stops
-
4mA
-
-
CS/A switch
Stops
-
3mA
I2C
CA *
-
CS/A switch
Stops
Input
3mA
I2C+ADC
D
Up/Down switch
CS/A switch
Stops
Input
4mA
ADC
E
-
CS/A switch
Stops
Input/
Output
4mA
ADC+DAC
J
-
C
-
-
-
MD[2:0]
N
Up
CS (INITX)
-
-
-
INIT
T
Up/Down switch
CS/A/TTL switch
Stops
-
4mA
With TTL input
OA
OB
-
-
Stops
-
-
4MHz oscillator
WA
WB
-
-
Stops
-
-
32kHz oscillator
Type
Pull up/down
(50kΩ)
CMOS (C)
CMOS Schmitt (CS)
automotive (A)
Input
stop
A
Up/Down switch
CS/A switch
B
-
C*
*: When port of C and CA is set for the I2C interface, the output is Nch open-drain. Otherwise, it is CMOS output.
■ Pin Input Voltage
Table 1.7-2 Pin Input Voltage
Form
VIL
VIH
CMOS input
VSS + 0.3V
VCC - 0.3V
CMOS Schmitt trigger input (for INIT pin)
0.2 × VCC
0.8 × VCC
CS
CMOS Schmitt trigger input
0.3 × VCC
0.7 × VCC
A
CMOS automotive Schmitt trigger input
0.5 × VCC
0.8 × VCC
T
TTL input
0.8V
2.1V
C
CS (INITX)
Type
25
CHAPTER 1 OVERVIEW
■ I/O Circuit Type
Table 1.7-3 I/O Circuit Type (1 / 4)
Type
Circuit
Remark
Pull-up control
Pout
Nout
A
Pull-down control
• CMOS-level output
(IOL = 4mA, IOH = -4mA)
• CMOS hysteresis input
(with function which shuts out the input at standby)
• Automotive input
(with function which shuts out the input at standby)
• Pull-up resistance setting enable resistance: approx.
50kΩ
• Pull-down resistance setting enable resistance:
approx. 50kΩ
CMOS
hysteresis input
Automotive input
Standby control
for input interception
Pout
Nout
B
• CMOS-level output
(IOL = 4mA, IOH = -4mA)
• CMOS hysteresis input
(with function which shuts out the input at standby)
• Automotive input
(with function which shuts out the input at standby)
CMOS
hysteresis input
Automotive input
Standby control
for input interception
Pout
Nout
C
CMOS
hysteresis input
Automotive input
Standby control
for input interception
26
• CMOS-level output
(IOL = 3mA, IOH = -3mA)
• CMOS hysteresis input
(with function which shuts out the input at standby)
• Automotive input
(with function which shuts out the input at standby)
CHAPTER 1 OVERVIEW
Table 1.7-3 I/O Circuit Type (2 / 4)
Type
Circuit
Remark
Pout
Nout
CA
CMOS
hysteresis input
• CMOS-level output
(IOL = 3mA, IOH = -3mA)
• CMOS hysteresis input
(with function which shuts out the input at standby)
• Automotive input
(with function which shuts out the input at standby)
• A/D analog input
Automotive input
Standby control
for input interception
Analog input
Pull-up control
Pout
Nout
D
Pull-down control
• CMOS-level output
(IOL = 4mA, IOH = -4mA)
• CMOS hysteresis input
(with function which shuts out the input at standby)
• Automotive input
(with function which shuts out the input at standby)
• Pull-up resistance setting enable resistance: approx.
50kΩ
• A/D analog input
• Pull-down resistance setting enable resistance:
approx. 50kΩ
CMOS
hysteresis input
Automotive input
Standby control
for input interception
Analog input
27
CHAPTER 1 OVERVIEW
Table 1.7-3 I/O Circuit Type (3 / 4)
Type
Circuit
Remark
Pout
Nout
CMOS
hysteresis input
• CMOS-level output
(IOL = 4mA, IOH = -4mA)
• CMOS hysteresis input
(with function which shuts out the input at standby)
• Automotive input
(with function which shuts out the input at standby)
• A/D analog input
• D/A analog output (MB91V280 only)
Automotive input
E
Standby control
for input interception
Analog input
Analog output
• CMOS hysteresis input
J
CMOS
hysteresis input
• CMOS hysteresis input
• Pull-up resistance value: approx. 50kΩ
N
Pull-up resistance
CMOS
hysteresis input
Pull-up control
Pout
Nout
T
Pull-down control
CMOS
hysteresis input
Automotive input
TTL input
Standby control
for input interception
28
• CMOS-level output
(IOL = 4mA, IOH = -4mA)
• CMOS hysteresis input
(with function which shuts out the input at standby)
• Automotive input
(with function which shuts out the input at standby)
• TTL
(with function which shuts out the input at standby)
• Pull-up resistance setting enable resistance: approx.
50kΩ
• Pull-down resistance setting enable resistance:
approx. 50kΩ
CHAPTER 1 OVERVIEW
Table 1.7-3 I/O Circuit Type (4 / 4)
Type
Circuit
Remark
Oscillation circuit
• High-speed oscillation feedback resistance = approx.
1MΩ
X1
OA
OB
X0
Standby control
signal
X1A
WA
WB
Xout
Oscillation circuit (Option: S-suffix product)
• Low-speed oscillation feedback resistance = approx.
10MΩ
X0A
Standby control
signal
29
CHAPTER 1 OVERVIEW
30
CHAPTER 2
HANDLING DEVICES
This chapter provides precautions on handling the FR
family.
2.1 Precautions when Handling Devices
31
CHAPTER 2 HANDLING DEVICES
2.1
Precautions when Handling Devices
This section contains information on preventing a latch up, processing of pins,
handling of circuit, and the input at power ON.
■ Preventing a Latch Up
Latch up phenomenon may occur with CMOS IC, when a voltage higher than VCC or lower than VSS is
applied to either the input or output pins, or when a voltage is applied between VCC and VSS that exceeds
the rated voltage. When latch up occurs, a significant power supply current surge results, which may
damage some elements due to the excess heat, so great care must be taken to ensure that the maximum
rating is never exceeded during use.
■ About the Processing of an Unused Input Pin
If unused input pins are kept being opened, it may cause erroneous operation, so they should be pulled up
or pulled down.
■ Power Pins
If more than one VCC or VSS pin exists, those that must be kept at the same potential are designed to be
connected to one other inside the device to prevent malfunctions such as latch up. Be sure to connect the
pins to a power supply and ground external to the device to minimize undesired electromagnetic radiation,
prevent strobe signal malfunctions due to an increase in ground level, and conform to the total output
current rating. Given consideration to connecting the current supply source to VCC and VSS of the device
at the lowest impedance possible.
It is also recommended that a ceramic capacitor of around 0.1µF be connected between VCC and VSS at
circuit points close to the device as a bypass capacitor.
The regulator is built into this device. Please supply 5V power supply to the VCC pin, and connect the
bypass capacitor of about 1µF with C pin for the regulator when this device is used in 5V power supply.
■ Crystal Oscillator Circuit
The noise near X0, X1, X0A and X1A pins becomes original of the malfunction of this device. Design
printed circuit boards so that X0, X1, X0A, X1A, the quartz oscillator (or ceramic oscillator), and the
bypass capacitor to ground are located as near to one another as possible.
It is strongly recommended that printed circuit board artwork that surrounds the X0, X1, X0A, and X1A
pins with ground be used to increase the expectation of stable operation.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
32
CHAPTER 2 HANDLING DEVICES
■ Note on Using External Clock
When using an external clock under normal conditions, supply clock signals to X0 pin and simultaneously
supply the antiphase signals with X0 to X1 pin. In this case, however, do not use STOP mode (oscillation
stop mode) because in the STOP mode, the X1 pin stops at "H" output state.
Figure 2.1-1 Example of Using External Clock (Normal)
X0
X1
Note
The STOP mode (oscillation stop mode) cannot be used.
■ Precautions of Non-use of Sub Clock
When the sub clock is not used, use single-system product. Be sure to connect the oscillator of 100kHz or
less for dual-system product.
■ About the Processing of the NC and the OPEN Pins
The NC pin and the OPEN pin must open to use.
■ About Mode Pin (MD0 to MD2)
These pins must be directly connected to VCC or VSS when they are used. In order to prevent erroneous
entry to test mode due to noise, the pattern length between each mode pin and VCC or VSS on the printing
circuit board should be as short as possible, and they should be connected at low impedance.
■ At Power-on
Also immediately after power-on, keep the INITX pin at the L level.
■ Source Oscillation Input at Power-on
At power-on, be sure to input a source clock until the oscillation stabilization wait time is reached.
■ Note on PLL Clock Mode Operation
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops
while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its
operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such
failure occurs.
■ External Bus Setting
MB91270 series guarantees at 16MHz external bus.
If the base clock is set to 32MHz with DIVR1 (external bus basic clock dividing frequency setting register)
held to an initial value, the external bus is set to 32MHz. Please change the base clock after it is set that an
external bus does not exceed 16MHz at the base clock changing.
■ Pull-up Control
When the pull-up resistor is connected with the pin used as an external bus pin, the AC standard is not
guaranteed.
33
CHAPTER 2 HANDLING DEVICES
■ Software Reset In Synchronous Mode (Only for MB91V280)
When using the software reset in synchronous mode, the following two conditions should be satisfied
before setting "0" to the SRST bit in STCR (standby control register).
• Set the interrupt enable flag (I-Flag) to the interrupt disable (I-Flag = 0).
• Don't use NMI.
34
CHAPTER 3
CPU and CONTROL UNIT
This chapter provides basic information required to
understand the CPU core functions of FR family. It
covers architecture, specifications, and instructions.
3.1 Memory Space
3.2 Internal Architecture
3.3 Programming Model
3.4 Data Configuration
3.5 Memory Map
3.6 Branch Instructions
3.7 EIT (Exception, Interruption, and Trap)
3.8 Operating Mode
3.9 Clock Generation Control
3.10 Device state control
3.11 Main Clock Oscillation Stabilization Wait Timer
35
CHAPTER 3 CPU and CONTROL UNIT
3.1
Memory Space
The FR family has a logical address space of 4 GB (232 addresses), which the CPU
accesses linearly.
■ Direct Addressing Area
The under mentioned region of the address space is used for I/O.
These areas called the direct addressing area. The address of an operand can be directly specified in an
instruction.
The size of the direct addressing area varies according to the size of data to be accessed:
• Byte data access
: 000H to 0FFH
• Half-word data access : 000H to 1FFH
• Word data access
: 000H to 3FFH
■ Memory Map
Figure 3.1-1 shows the memory space.
Figure 3.1-1 Memory Map
Single chip mode
Internal ROM
external bus
External ROM
external bus
I/O
I/O
I/O
I/O
I/O
0000 0000H
0000 0400H
I/O
0001 0000H Access prohibited
0002 0000H F-bus area
0004 0000H Access prohibited
0005 0000H
User
ROM area
Access prohibited
Access prohibited
F-bus area
F-bus area
Access prohibited
Access prohibited
User
ROM area
0010 0000H
Access
prohibited
Direct addressing
area
Refer to I/O map
External
area
External
area
FFFF FFFFH
The setting of each mode is determined by the mode vector fetch after INIT negating. (For the setting of
the mode, see "3.8.2 Mode Settings".)
36
CHAPTER 3 CPU and CONTROL UNIT
3.2
Internal Architecture
This section explains the configuration of the internal architecture and the instruction
overview for the FR family.
■ Overview of the Internal Architecture
The FR family CPU is a high-performance core that is designed based on a RISC architecture with highlevel function instructions for embedded applications.
37
CHAPTER 3 CPU and CONTROL UNIT
3.2.1
Internal Architecture
This section explains the features and the configuration of internal architecture.
■ Features of the Internal Architecture
• RISC architecture used
Basic instruction: One instruction per cycle
• 32-bit architecture
General-purpose register: 32 bits × 16
• Linear memory space of 4GB
• Multiplier installed
32-bit by 32-bit multiplication: 5 cycles
16-bit by 16-bit multiplication: 3 cycles
• Enhanced interrupt processing function
Quick response speed: 6 cycles
Support of multiple interrupts
Level mask function: 16 levels
• Enhanced instructions for I/O operations
Memory-to-memory transfer instruction
Bit-processing instructions
• Efficient code
Basic instruction word length: 16 bits
• Low-power consumption
Sleep and stop modes
Gear function
38
CHAPTER 3 CPU and CONTROL UNIT
■ Configuration of the Internal Architecture
The FR family CPU uses the Harvard architecture, in which the instruction bus and data buses are independent
of each other.
A 32-bit <----> 16-bit bus converter is connected to the 32-bit bus (F bus) to provide an interface between
the CPU and peripheral resources. A Harvard <----> Princeton bus converter is connected to the I bus and
D bus to provide an interface between the CPU and the bus controller.
Figure 3.2-1 shows the configuration of the internal architecture.
Figure 3.2-1 Configuration of the Internal Architecture
FR CPU
D-bus
I-bus
32
I address
Harvard
32
External address
24
I data
External data
D address
32
Princeton
16
bus converter
Data RAM
D data
32
32-bit
F Address
32
16-bit
F Data
32
bus converter
16
F-bus
R-bus
Peripheral resources
Internal I/O
Bus converter
39
CHAPTER 3 CPU and CONTROL UNIT
■ CPU
The CPU is a compact implementation of the 32-bit RISC FR architecture. Five step instruction pipelines
are used to execute one instruction per cycle. A pipeline consists of the following stages:
Figure 3.2-2 shows the configuration of connections in the instruction pipeline.
• Instruction fetch (IF): The instruction address is outputted, and the instruction is fetched.
• Instruction decode (ID): Decode the fetched instruction. Also reads a register.
• Execution (EX): The operation is executed.
• Memory access (MA): Loading into the memory or the store is accessed.
• Write-back (WB): Writes an operation result (or loaded memory data) to a register.
Figure 3.2-2 Instruction Pipeline
CLK
Instruction 1
WB
Instruction 2
MA
WB
Instruction 3
EX
MA
WB
Instruction 4
ID
EX
MA
WB
Instruction 5
IF
ID
EX
MA
WB
IF
ID
EX
MA
Instruction 6
WB
The instruction is never executed in any order executed. Accordingly, if instruction A enters the pipeline
before instruction B, instruction A always reaches write-back stage before instruction B.
As a rule, the instruction is executed at the speed of one instruction per cycle. However, multiple cycles are
required to execute a load/store instruction with a memory wait, a branch instruction without a delay slot,
or a multiple-cycle instruction. The execution of instructions slows down if the instructions are not supplied
fast enough.
■ 32-bit/16-bit Bus Converter
The 32-bit/16-bit bus converter provides an interface between the F-bus accessed with 32-bit width and the
R-bus accessed with 16-bit width and enables data access from the CPU to built-in peripheral circuits.
If the CPU performs a 32-bit width access to the R-bus, this bus converter converts the access into two 16bit width accesses. Some of the built-in peripheral circuits have limitations on the access bus width.
■ Harvard/Princeton Bus Converter
The Harvard/Princeton bus converter coordinates the CPU’s instruction and data accesses to provide a
smooth interface between it and external buses.
The CPU has a Harvard architecture with separate buses for instructions and data. On the other hand, the
bus controller that performs control of external buses has a Princeton architecture with a single bus. The
Harvard/Princeton bus converter assigns priorities to instruction and data accesses from the CPU, and
controls accesses to the bus controller. This function allows the order of external bus accesses to be
permanently optimized.
40
CHAPTER 3 CPU and CONTROL UNIT
3.2.2
Overview of Instructions
The FR family supports the general RISC instruction set as well as the logical operation,
bit manipulation, and direct addressing instructions optimized for embedded
applications. Each instruction is 16-bit long (except for some instructions are 32- or 48bit long), resulting in superior efficiency of memory use.
An instruction set is classified into the following function groups:
• Arithmetic operation
• Load and store
• Divergence
• Logical operation and bit operation
• Direct addressing
• The others
■ Arithmetic Operation
It has standard arithmetic operation instructions (addition, subtraction, comparison) and shift instructions
(logic shift, arithmetic operation shift). Operations with carry that are used for multi-word length operations
and operations that do not change the flag which are convenient for address calculations are enabled for
addition and subtraction.
Furthermore, 32-bit-by-32-bit and 16-bit-by-16-bit multiplication instructions and a 32-bit-by-32-bit step
division instruction are provided.
Additionally, an immediate data transfer instruction that sets immediate data in a register and a register-toregister transfer instruction are provided.
An arithmetic operation instruction is executed using the general-purpose registers and the multiplication
and division registers in the CPU.
■ Load and Store
Load and store instructions read and write to external memory. They are also used to read and write to a
peripheral circuit (I/O) on the chip.
Load and store instructions have three access lengths: byte, halfword, and word. In addition to indirect
memory addressing via general registers, indirect memory addressing via registers with displacements and
via registers with register incrementing or decrementing are provided for some instructions.
■ Divergence
It is an instruction of the divergence, the call, the interruption, and the return. There are two types of
branch instructions; one type features a delay slot while the other does not. They can be optimized in
accordance with the purpose. Details of the branch instruction are described later.
41
CHAPTER 3 CPU and CONTROL UNIT
■ Logical Operation and Bit Operation
Logic operation instructions can perform AND, OR, and EOR logic operations between general-purpose
registers, or between a general-purpose register and the memory (and I/O). Moreover, the bit operation
instruction can operate the content of the memory (and I/O) directly.
The memory addressing is generally indirect register.
■ Direct Addressing
Direct addressing instructions are used to access between I/O and general-purpose registers, or between I/O
and the memory. The I/O address can be accessed quickly and efficiently by direct specification within the
instruction instead of indirectly to the register. Indirect memory addressing via registers with register
incrementing or decrementing are provided for some instructions.
■ Overview of Other Instructions
Other types of instructions include instructions that provide flag setting, stack manipulation, sign/zero
extension, and other functions in the PS register. Also, function entry and exit instructions that support
high-level languages and register multi-load/store instructions are provided.
42
CHAPTER 3 CPU and CONTROL UNIT
3.3
Programming Model
This section explains the programming model, general-purpose registers, and
dedicated registers of FR family in detail.
■ Basic Programming Model
Figure 3.3-1 shows the basic programming model of FR family.
Figure 3.3-1 Basic Programming Model
32-bit
[Initial value]
R0
XXXX XXXXH
R1
General-purpose
register
R12
R13
AC
R14
XXXX XXXXH
FP
R15
Program counter
PC
Program status
PS
Table base register
TBR
Return pointer
RP
System stack pointer
SSP
User stack pointer
USP
Multiplication/division
result register
MDH
MDL
0000 0000H
SP
ILM
SCR CCR
43
CHAPTER 3 CPU and CONTROL UNIT
3.3.1
General-Purpose Registers
Registers R0 to R15 are general-purpose registers.
They are used as the accumulator for various operations and pointers for memory
access.
■ General-purpose Register
Figure 3.3-2 shows the configuration of a general-purpose register.
Figure 3.3-2 Configuration of a General-purpose Register
32-bit
[Initial value]
R0
R1
R12
R13
R14
R15
XXXX XXXXH
AC
FP
SP
XXXX XXXXH
0000 0000H
The following of the 16 registers are expected to have special usage, so some instructions are emphasized.
• R13:Virtual accumulator
• R14:Frame pointer
• R15:Stack pointers
R0 to R14 of the initial value by reset is undefined. R15 becomes 00000000H(value of SSP).
44
CHAPTER 3 CPU and CONTROL UNIT
3.3.2
Dedicated Registers
Dedicated register is used for a specific purpose.
In the FR family, the following dedicated registers are prepared.
• PS (Program Status)
• CCR (Condition Code Register)
• SCR (System Condition code Register)
• ILM (Interrupt Level Mask Register)
• PC (Program Counter)
• TBR (Table Base Register)
• RP (Return Pointer)
• SSP (System Stack Pointer)
• USP (User Stack Pointer)
• Multiplication and division register (Multiply&Divide register)
■ PS (Program Status)
This register retains the program status, and is separated into three parts, namely, ILM, SCR, and CCR.
In the figure, all the undefined bits are reserved. During reading, "0" is always read. Writing is disabled.
The register configuration of PS (Program Status) is as follows.
bit
31
16
20
ILM
10 8 7
SCR
0
CCR
45
CHAPTER 3 CPU and CONTROL UNIT
■ CCR (Condition Code Register)
The register configuration of CCR (Condition Code Register) is as follows.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
[Initial value]
-
-
S
I
N
Z
V
C
--00XXXXB
[bit5] Stack flag
The stack pointer used as R15 is specified.
Value
Description
0
SSP is used as R15.
When an EIT occurs, this bit is automatically set to "0".
(Note that the value saved on the stack is the value before it is cleared.)
1
USP is used as R15.
• Reset clears this bit to "0".
• Set this bit to "0" when executing a RETI instruction.
[bit4] Interrupt enable flag
Enable or disable a user interrupt request.
Value
Description
0
User interrupt disabled.
When the INT instruction is executed, this bit is cleared to "0".
(Note that the value saved on the stack is the value before it is cleared.)
1
User interrupt enabled.
The mask processing of a user interrupt request is controlled by the value held in ILM.
• Reset clears this bit to "0".
[bit3] Negative flag
The sign when considering the integer to which the operation result is expressed by the 2's complement is
indicated.
Value
Description
0
It is indicated that operation result was a positive value.
1
It is indicated that operation result was a negative value.
• Initial state by reset is undefined.
46
CHAPTER 3 CPU and CONTROL UNIT
[bit2] Zero flag
It is shown whether operation result was 0.
Value
Description
0
It is indicated that operation result was the values other than 0.
1
It is shown that operation result was 0.
• Initial state by reset is undefined.
[bit1] Overflow flag
Indicate whether an overflow has occurred as a result of the operation when the operand used for
operation is regarded as an integer represented by its 2's complement.
Value
Description
0
Indicates that the operation did not cause an overflow.
1
Indicates that the operation caused an overflow.
• Initial state by reset is undefined.
[bit0] Carry flag
Indicate whether a carry or a borrow has occurred from the most significant bit in the operation.
Value
Description
0
Indicates that no carry or borrow has occurred.
1
Indicates that a carry or borrow has occurred.
• Initial state by reset is undefined.
47
CHAPTER 3 CPU and CONTROL UNIT
■ SCR (System Condition Code Register)
The register configuration of SCR (System Condition code Register) is as follows.
bit10
bit9
bit8
[Initial value]
D1
D0
T
XX0B
[bit10, bit9] Step division flag
The middle data of step division execution time is maintained.
Do not change these bits during step division. To execute other processing during a step division, save
and restore the value of the PS register to ensure that the step division is restarted.
• Initial state by reset is undefined.
• It is set by executing the DIV0S instruction referring to the dividend and the divisor.
• When the DIV0U instruction is executed, this flag is cleared forcibly.
• Do not perform any process desiring the D0/D1 bit of the PS register before the EIT branch in the
DIV0S/DIV0U instruction and user interrupt/NMI simultaneous acceptance EIT processing routine.
• When a halt caused by break, step, etc. occurs immediately before the DIV0S/DIV0U instruction, the
D0/D1 bit of the PS register may not display a valid value. However, the calculation result after
return will be valid.
[bit8] Step trace trap flag
It is a flag which specifies whether to make the step trace trap effective.
Value
Description
0
The step trace trap is disabled.
1
The step trace trap is enabled.
All user NMIs and user interrupts are prohibited.
• Initialized to "0" by reset.
• The emulator uses the function of the step trace trap. When the emulator is used, this function
cannot be done in the user program.
48
CHAPTER 3 CPU and CONTROL UNIT
■ ILM
The register configuration of ILM is as follows.
bit20
bit19
bit18
bit17
bit16
[Initial value]
ILM4
ILM3
ILM2
ILM1
ILM0
01111B
The interrupt level mask (ILM) register holds an interrupt level mask value. The value held in ILM is used
as a level mask.
An interrupt request to the CPU is accepted only when its interrupt level is higher than the level indicated
in this ILM.
As for the level value, 0(00000B) is the strongest, and 31(11111B) is the weakest.
There is a limitation in the value which can be set from the program.
• When the original value is between 16 and 31:
A new value between 16 and 31 can be set. If an instruction that sets a value between 0 and 15 is
executed, the specified value plus 16 is transferred.
• When the original value is between 0 and 15:
Any value between 0 and 31 can be set.
Reset initializes this bit to 15 (01111B).
■ PC (Program Counter)
The register configuration of PC (Program Counter) is as follows.
bit31
bit0
PC
[Initial value]
XXXXXXXXH
[bit31 to bit0]
The address of the executed instruction is shown with the program counter.
Bit0 is set to "0" when the PC is updated after an instruction is executed. Bit0 can become "1" only if the
branch destination address is an odd-number address.
However, even if the branch destination address is an odd-number address, bit0 is invalid and therefore
the instruction should be placed at an address that is multiple of 2.
The initial value by reset is undefined.
■ TBR (Table Base Register)
The register configuration of TBR (Table Base Register) is as follows.
bit31
TBR
bit0
[Initial value]
000FFC00H
The table base register holds the first address of the vector table to be used during EIT processing.
The initial value by reset is 000FFC00H.
49
CHAPTER 3 CPU and CONTROL UNIT
■ RP (Return Pointer)
The register configuration of RP (Return Pointer) is as follows.
bit31
bit0
RP
[Initial value]
XXXXXXXXH
The address which returns from the sub routine is maintained with the return pointer.
The value of PC is forwarded to this RP at CALL instruction execution time.
The content of RP is forwarded to PC at RET instruction execution time.
The initial value by reset is undefined.
■ SSP (System Stack Pointer)
The register configuration of SSP (System Stack Pointer) is as follows.
bit31
bit0
SSP
[Initial value]
00000000H
SSP is the system stack pointer.
SSP functions as R15 when the S flag is "0".
SSP can also be specified explicitly.
Also used as the stack pointer specifying the stack that saves the PS and PC when EIT occurs.
The initial value by reset is 00000000H.
■ USP (User Stack Pointer)
The register configuration of USP (User Stack Pointer) is as follows.
bit31
USP
USP is the user stack pointer.
USP functions as R15 when the S flag is "1".
USP can also be specified explicitly.
The initial value by reset is undefined.
This register cannot be used in the RETI instruction.
50
bit0
[Initial value]
XXXXXXXXH
CHAPTER 3 CPU and CONTROL UNIT
■ Multiplication and Division Register (Multiply & Divide Register)
The register configuration of
follows.
multiplication and division register (Multiply & Divide register) is as
bit31
bit0
MDH
MDL
They are the register for multiplication and division and 32-bit lengths respectively.
The initial value by reset is undefined.
• When the multiplication is executed
When performing 32-bit-by-32-bit multiplications, 64-bit length calculation results are stored in the
multiplication/division results storage register in the following format.
MDH: High-order 32 bits
MDL: Low-order 32 bits
For a 16-bit-by-16-bit multiplication, the result is stored as follows:
MDH: Undefined
MDL: 32-bit result
• When the division is executed
When beginning to calculate, the dividend is stored in MDL. When divisions are performed using the
DIV0S/DIV0U, DIV1, DIV2, DIV3, and DIV4S instructions, the results are stored in MDL and MDH.
MDH: Surplus
MDL: Quotient
51
CHAPTER 3 CPU and CONTROL UNIT
3.4 Data Configuration
This section explains the data configuration of the FR family.
■ Bit Ordering
In the FR family, the little endian has been adopted as a bit ordering. The data arrangement of the bit
ordering is indicated in Figure 3.4-1.
Figure 3.4-1 Data Configuration of Bit Ordering
bit
31
29
30
27
28
25
26
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
MSB
4
1
2
0
LSB
■ Byte Ordering
In the FR family, the big endian has been adopted as byte ordering.
The data arrangement of byte ordering is indicated in Figure 3.4-2.
Figure 3.4-2 Data Configuration of Byte Ordering
Memory
Bit
7
52
3
0
n address
10101010
(n+1) address
11001100
(n+2) address
11111111
(n+3) address
00010001
LSB
23
15
7
0
10101010 11001100 11111111 00010001
MSB
bit 31
CHAPTER 3 CPU and CONTROL UNIT
■ Word Alignment
● Program Access
It is necessary to arrange the program of the FR family in the address of the multiple of two.
Bit0 of the PC is set to "0" if the PC is updated when an instruction is executed.
Bit0 can be set to "1" only if an odd-number address is specified as the branch address.
If bit0 is set to "1", however, bit0 is invalid and an instruction must be placed at the address that is a
multiple of 2.
There is no odd-number address exception.
● Data Access
In the FR family, if data is accessed, forced alignment is applied to the address based on the width.
Word access: An address must be a multiple of 4. (The lowest-order 2 bits are forcibly set to "00".)
Halfword access: An address must be a multiple of 2. (The lowest-order bit is forcibly set to "0".)
Byte access: When word or halfword data is accessed, "0" is forcibly set to some bits, which are the calculation results
of the effective address.
For example, in @(R13, Ri) addressing mode, the register before addition is used without change in the
calculation (even if the lowest-order bit is "1") and the low-order bits of the added result are masked. A
register before calculation is not masked.
[Example] LD @(R13, R2), R0
R13
00002222H
R2
00000003H
Added result
Address pin
00002225H
Lower 2 bits are forcibly masked.
00002224H
53
CHAPTER 3 CPU and CONTROL UNIT
3.5
Memory Map
This section shows the memory map for the FR family.
■ Memory Map
The address space is 32-bit linear.
Figure 3.5-1 shows the memory map.
Figure 3.5-1 Memory Map
0000 0000H
Byte data
0000 0100H
Halfword data
0000 0200H
Direct addressing area
Word data
0000 0400H
000F FC00H
Vector table
Initial area
000F FFFFH
FFFF FFFFH
● Direct addressing area
The following areas in the address space are the areas for I/O. When direct addressing is used in these
areas, an operand address can be directly specified in an instruction.
The size of the address region of direct possible addressing is different in each data length.
• Byte data: (8 bits)
: 000H to 0FFH
• Halfword data: (16 bits)
: 000H to 1FFH
• Word data: (32 bits)
: 000H to 3FFH
● Vector table initial area
The region of 000FFC00H to 000FFFFFH is EIT vector table initial area.
The vector table used for EIT processing can be allocated to an arbitrary address by rewriting the TBR, but
it is allocated to this address on initialization through reset.
54
CHAPTER 3 CPU and CONTROL UNIT
3.6
Branch Instructions
This section explains the branch instructions of the FR family.
■ Overview of Branch Instruction
In the FR family, whether the operations are with or without delay slots can be specified for the branch
command.
55
CHAPTER 3 CPU and CONTROL UNIT
3.6.1
Operation with Delay Slot
This section explains the case where operating with the delay slot is specified for the
branch instruction.
■ Instructions of Operation with Delay Slot
Instructions written as follows perform a branch operation with a delay slot:
JMP:D @Ri
CALL:D label12
CALL:[email protected]
RET:D
BRA:D label9
BNO:D label9
BEQ:D label9
BNE:D label9
BC:D
label9
BNC:D label9
BN:D
BP:D
BV:D
label9
BNV:D label9
BLT:D label9
BGE:D label9
BLE:D label9
BGT:D label9
BLS:D label9
BHI:D label9
label9
label9
■ Explanation of Operation with Delay Slot
Operations with delay slots branch out after executing the command placed just after the branch command
(called a "delay slot") before executing the branch destination command.
Since an instruction in the delay slot is executed before the branch operation, the apparent execution speed
is one cycle. However, a NOP instruction must be placed in the delay slot if there is no valid instruction put
there.
[Example]
; Row of instruction
ADD
R1, R2
;
BRA:D
LABEL
; Branch instruction
MOV
R2, R3
; Delay slot ... Executed before branch
...
LABEL: ST
R3, @R4
; Branch destination
If a conditional branch instruction is used, an instruction placed in the delay slot is executed whether or not
the condition for branching is met.
If a delay branch instruction is used, the order of execution for some instructions seems to be reversed.
However, this occurs only for updating the PC and the instructions are executed in the specified order for
other operations (register update and reference, etc.)
A concrete explanation is done as follows.
1. The Ri to be referred to for the JMP:[email protected]/CALL:[email protected] command will not be affected even if the
command within the delay slot updates the Ri.
[Example]
LDI:32
#Label,
JMP:D
@R0
LDI:8
#0,
...
56
R0
;Branch to Label
R0
;No effect on the branch destination address
CHAPTER 3 CPU and CONTROL UNIT
2. The RP to be referred by the RET:D command will not be affected even if the command within the
delay slot updates the RP.
[Example]
RET:D
MOV
;Branch to address defined beforehand in RP
R8,
RP
;No effect on the return operation
...
3. The flag to be referred by the Bcc:D rel instruction is not affected by the instruction in the delay slot.
[Example]
ADD
#1, R0
; Flag change
BC:D
Overflow
; Branch to execution result of above instruction
AND
CCR #0
; Do not refer to this flag update in the above mentioned branch instruction.
...
4. When RP is referred to for the command within the delay slot under the CALL:D command, the updated
contents will be read by the CALL:D command.
[Example]
CALL:D
Label
; Updating RP and branching
MOV
RP, R0
; RP of an execution result in the above-mentioned
CALL:D is forwarded.
...
■ Limitation of Operation with Delay Slot
● Instructions that can be placed in the delay slot
Only an instruction meeting the following conditions can be executed in the delay slot.
• One-cycle instruction
• Instruction other than a branch instruction
• Instruction whose operation is not affected even though the order is changed
The "1-cycle command" is a command with "1", "a", "b", "c", or "d" described in the cycle number field
within the command list.
● Step trace trap
Step trace trap is not generated between executing the branch command with the delay slot and the delay
slot.
● Interrupt and NMI
An interrupt and NMI is not accepted between the execution of a branch instruction with a delay slot and
the delay slot.
● Undefined instruction exception
An undefined instruction exception does not occur if there is an undefined instruction in the delay slot. At
this time, undefined instruction operates as NOP instruction.
57
CHAPTER 3 CPU and CONTROL UNIT
3.6.2
Operation without Delay Slot
This section explains the case when no operating of the delay slot is specified for the
branch instruction.
■ Instruction of Operation without Delay Slot
Instructions written as follows perform a branch operation without a delay slot:
JMP @Ri
CALL label12
CALL @Ri
RET
BRA label9
BNO
label9
BEQ
label9
BNE
label9
BC
label9
BNC
label9
BN
label9
BP
label9
BV
label9
BNV
label9
BLT
label9
BGE
label9
BLE label9
BGT
label9
BLS
label9
BHI
label9
■ Explanation of Operation without Delay Slot
In operation without a delay slot, instructions are executed in the order in which they are specified. An
instruction immediately following a branch is never executed before it.
[Example]
; Row of instruction
ADD R1, R2
;
BRA LABEL
; Branch instruction (without delay slot)
MOV R2, R3
; Not executed
...
LABEL: ST
R3, @R4
; The divergence ahead
A branch instruction without a delay slot is executed in two cycles if a branch occurs and in one cycle if no
branch occurs.
Since no appropriate instruction can be placed in the delay slot, this instruction results in a more efficient
instruction code than a branch instruction with a delay slot which NOP is specified.
For both optimal execution speed and code efficiency, select an operation with a delay slot if a valid
instruction can be placed in the delay slot; otherwise, select an operation without a delay slot.
58
CHAPTER 3 CPU and CONTROL UNIT
3.7
EIT (Exception, Interruption, and Trap)
EIT, a generic term for exception, interrupt, and trap, refers to suspending program
execution if an event occurs during execution and then executing another program.
The exception is an incident which occurs in relation to the context under execution.
Execution restarts from the instruction that caused the exception.
The interruption is an incident which occurs without any relation to the context under
execution. The event factor is hardware.
The trap is an incident which occurs in relation to the context under execution. There is
something directed by the program like the system call. Execution restarts from the
instruction following the one that caused the trap.
■ Features of EIT
• Multiple interrupt is supported to the interruption.
• It is a level mask function (15 levels are available to the user) to the interruption.
• Trap instruction (INT)
• EIT (hardware/software) for emulator startup
■ EIT Causes
The following are causes of EIT:
• Reset
• User interruption (internal resource and external interruption)
• NMI
• Delayed interrupt
• Undefined instruction exception
• Trap instruction (INT)
• Trap instruction (INTE)
• Step trace trap
• No-coprocessor trap
• Coprocessor error trap
Note:
In the delay slot of the branch instruction, there is a restriction concerning EIT. Refer to Section "3.6
Branch Instructions".
■ Return from EIT
Execute the RETI instruction to return from EIT.
59
CHAPTER 3 CPU and CONTROL UNIT
3.7.1
EIT Interrupt Levels
Interrupt levels are 0 to 31 and are controlled by five bits.
■ Interrupt Levels
Table 3.7-1 shows the allocation of the levels.
Table 3.7-1 EIT Interrupt Levels
Level
Interrupt factor
Binary
Decimal
00000
0
(Reserved for system)
...
...
...
...
...
...
00011
3
(Reserved for system)
00100
4
INTE instruction
Step trace trap
00101
5
(Reserved for system)
...
...
...
...
...
...
01110
14
(Reserved for system)
01111
15
NMI (for user)
10000
16
Interrupt
10001
17
Interrupt
...
...
...
...
...
...
11110
30
Interrupt
11111
31
-
Precautions
If the original ILM value is between 16
and 31, a program cannot set a value in
this ILM range.
User interrupts prohibited if ILM is set
Interrupts prohibited if ICR is set
It is a level of 16 to 31 that the operation is possible.
Undefined command exceptions, coprocessor absence traps, coprocessor error traps, and INT commands
are not affected by interruption levels. Moreover, ILM is not changed.
60
CHAPTER 3 CPU and CONTROL UNIT
■ I Flag
It is a flag which specifies the permission and interdiction of the interruption. This flag is provided as bit4
of the CCR in the PS register.
Value
Description
0
Interrupts prohibited
Cleared to 0 if the INT instruction is executed.
(Note that a value saved on the stack is the value before it is cleared.)
1
Interrupts permitted
The mask processing of an interrupt request is controlled by the value in the ILM register.
■ ILM
It is PS register (20 to 16) which maintains the interrupt level mask value.
The CPU accepts an interrupt request among interrupt requests input to the CPU only when the
corresponding interrupt level is higher than the level indicated by the ILM.
As for the level value, 0(00000B) is the strongest, and 31(11111B) is the weakest.
There is a limitation in the value which can be set from the program. If the original value is between 16
and 31, the new value must be between 16 and 31. If an instruction that sets a value between 0 and 15 is
executed, the specified value plus 16 is transferred.
When former value is 0 to 15, the any value of 0 to 31 can be set.
The ST ILM instruction is used for setting any value.
■ Level Mask for Interrupt and NMI
If an NMI or interrupt request occurs, the interrupt level (Table 3.7-1) of the interrupt source is compared
with the level mask value held in the ILM. And, when the following condition consists, the mask is done,
and the demand is not accepted.
Interrupt levels of factor ≥ level mask value
61
CHAPTER 3 CPU and CONTROL UNIT
3.7.2
ICR (Interrupt Control Register)
The interrupt control register (ICR: Interrupt Control Register), located in the interrupt
controller, sets the level of an interrupt request. An ICR is provided for each of the
interrupt request inputs. The mapping is done in the I/O space, and ICR is accessed by
CPU through the bus.
■ Bit Configuration of Interrupt Control Register (ICR)
The following shows the bit configuration of the ICR.
ICR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0007FCH
-
-
-
ICR4
R
ICR3
R/W
ICR2
R/W
ICR1
R/W
ICR0
R/W
---11111B
R/W: Readable/Writable
R:
Read only
[bit4] ICR4
ICR4 is always set to "1".
[bit3 to bit0] ICR3 to ICR0
These bits are the low-order 4 bits of the interrupt level of the corresponding interrupt source. They can
be read and written to. Together with bit4, a value between 16 and 31 can be set in the ICR.
62
CHAPTER 3 CPU and CONTROL UNIT
■ Mapping of Interrupt Control Register (ICR)
Table 3.7-2 shows the allocation of the interruption source, the interruption control register, and the
interruption vector.
Table 3.7-2 Interrupt Sources, Interrupt Control Registers, and Interrupt Vectors
Interrupt control registers
Interrupt
source
Corresponding interruption vector
Number
Number
Address
Address
Hexa-decimal
Decimal
IRQ00
ICR00
00000440H
10H
16
TBR+3BCH
IRQ01
ICR01
00000441H
11H
17
TBR+3B8H
IRQ02
ICR02
00000442H
12H
18
TBR+3B4H
...
...
...
...
...
...
...
...
...
...
...
...
IRQ45
ICR45
0000046DH
3DH
61
TBR+308H
IRQ46
ICR46
0000046EH
3EH
62
TBR+304H
IRQ47
ICR47
0000046FH
3FH
63
TBR+300H
TBR Initial value:000FFC00H
Note: See "CHAPTER 7 INTERRUPT CONTROLLER".
63
CHAPTER 3 CPU and CONTROL UNIT
3.7.3
SSP (System Stack Pointer)
The system stack pointer (SSP) is used as a pointer to point to the stack to save and
restore data when EIT is accepted or a return operation occurs.
■ SSP (System Stack Pointer)
The register configuration of SSP is as follows.
bit
31..
SSP
..0
[Initial value]
00000000H
8 is deducted from the content during EIT processing, and 8 is added when returning from EIT in line with
execution of the RETI command.
The initial value by reset is 00000000H.
The SSP is also used as general-purpose register R15 if the S flag in the CCR is set to "0".
64
CHAPTER 3 CPU and CONTROL UNIT
3.7.4
Interrupt Stack
The value of PC and PS is saved and revived in the region shown by SSP.
After an interrupt occurs, the PC contents are stored at the address indicated by SSP
and the PS contents are stored at the address indicated by SSP plus 4.
■ Interrupt Stack
Figure 3.7-1 shows the interrupt stack example.
Figure 3.7-1 Interrupt Stack
[Before interrupt]
SSP
80000000H
[After interrupt]
SSP
7FFFFFF8H
Memory
80000000H
7FFFFFFCH
7FFFFFF8H
80000000H
7FFFFFFCH
7FFFFFF8H
PS
PC
65
CHAPTER 3 CPU and CONTROL UNIT
3.7.5
TBR (Table Base Register)
It is a register which shows the first address of the vector table for EIT.
■ TBR (Table Base Register)
The register configuration of TBR is as follows.
bit
31..
TBR
..0
[Initial value]
000FFC00H
Obtain a vector address by adding the offset value predetermined for the TBR and the EIT cause.
The initial value by reset is 000FFC00H.
66
CHAPTER 3 CPU and CONTROL UNIT
3.7.6
EIT Vector Table
A 1 KB area from the address indicated in the table base register (TBR) is the vector
area for EIT.
■ EIT Vector Table
The size for each vector is 4 bytes. The relationship between a vector number and a vector address can be
expressed as follows:
vctadr =TBR + vctofs
=TBR + (3FCH – 4 × vct)
vctadr:
Vector Address
vctofs:
Vector offset
vct:
Vector number
The low-order two bits of the addition result are always handled as 00.
The region of 000FFC00H to 000FFFFFH is an initial region of the vector table by reset.
A special function is allocated to the vector partially.
Table 3.7-3 shows the vector table on the architecture.
Table 3.7-3 Vector Table (1 / 3)
Interrupt number
Decimal
Hexadecimal
Interrupt
level
Reset *1
0
00
-
3FCH
000FFFFCH
Mode vector *1
1
01
-
3F8H
000FFFF8H
Reserved for system
2
02
-
3F4H
000FFFF4H
Reserved for system
3
03
-
3F0H
000FFFF0H
Reserved for system
4
04
-
3ECH
000FFFECH
Reserved for system
5
05
-
3E8H
000FFFE8H
Reserved for system
6
06
-
3E4H
000FFFE4H
Coprocessor absent trap
7
07
-
3E0H
000FFFE0H
Coprocessor error trap
8
08
-
3DCH
000FFFDCH
INTE instruction
9
09
-
3D8H
000FFFD8H
Reserved for system
10
0A
-
3D4H
000FFFD4H
Reserved for system
11
0B
-
3D0H
000FFFD0H
Step trace trap
12
0C
-
3CCH
000FFFCCH
NMI demand (tool)
13
0D
-
3C8H
000FFFC8H
Undefined instruction exception
14
0E
-
3C4H
000FFFC4H
NMI demand
15
0F
fixed 15(FH)
3C0H
000FFFC0H
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
Interrupt source
Offset
Default address
of TBR
67
CHAPTER 3 CPU and CONTROL UNIT
Table 3.7-3 Vector Table (2 / 3)
Interrupt number
Decimal
Hexadecimal
Interrupt
level
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
Reload timer 0
24
18
ICR08
39CH
000FFF9CH
Reload timer 1
25
19
ICR09
398H
000FFF98H
Reload timer 2
26
1A
ICR10
394H
000FFF94H
Maskable source *2
27
1B
ICR11
390H
000FFF90H
Maskable source *2
28
1C
ICR12
38CH
000FFF8CH
Maskable source *2
29
1D
ICR13
388H
000FFF88H
Maskable source *2
30
1E
ICR14
384H
000FFF84H
Maskable source *2
31
1F
ICR15
380H
000FFF80H
Maskable source *2
32
20
ICR16
37CH
000FFF7CH
Maskable source *2
33
21
ICR17
378H
000FFF78H
Maskable source *2
34
22
ICR18
374H
000FFF74H
Maskable source *2
35
23
ICR19
370H
000FFF70H
Maskable source *2
36
24
ICR20
36CH
000FFF6CH
Maskable source *2
37
25
ICR21
368H
000FFF68H
Maskable source *2
38
26
ICR22
364H
000FFF64H
Maskable source *2
39
27
ICR23
360H
000FFF60H
Maskable source *2
40
28
ICR24
35CH
000FFF5CH
Maskable source *2
41
29
ICR25
358H
000FFF58H
Maskable source *2
42
2A
ICR26
354H
000FFF54H
Maskable source *2
43
2B
ICR27
350H
000FFF50H
Maskable source *2
44
2C
ICR28
34CH
000FFF4CH
Maskable source *2
45
2D
ICR29
348H
000FFF48H
Maskable source *2
46
2E
ICR30
344H
000FFF44H
Time-base timer overflow
47
2F
ICR31
340H
000FFF40H
Maskable source *2
48
30
ICR32
33CH
000FFF3CH
Maskable source *2
49
31
ICR33
338H
000FFF38H
Maskable source *2
50
32
ICR34
334H
000FFF34H
Maskable source *2
51
33
ICR35
330H
000FFF30H
Maskable source *2
52
34
ICR36
32CH
000FFF2CH
Interrupt source
68
Offset
Default address
of TBR
CHAPTER 3 CPU and CONTROL UNIT
Table 3.7-3 Vector Table (3 / 3)
Interrupt number
Decimal
Hexadecimal
Interrupt
level
Maskable source *2
53
35
ICR37
328H
000FFF28H
Maskable source *2
54
36
ICR38
324H
000FFF24H
Maskable source *2
55
37
ICR39
320H
000FFF20H
Maskable source *2
56
38
ICR40
31CH
000FFF1CH
Maskable source *2
57
39
ICR41
318H
000FFF18H
Maskable source *2
58
3A
ICR42
314H
000FFF14H
Maskable source *2
59
3B
ICR43
310H
000FFF10H
Maskable source *2
60
3C
ICR44
30CH
000FFF0CH
Maskable source *2
61
3D
ICR45
308H
000FFF08H
Maskable source *2
62
3E
ICR46
304H
000FFF04H
Delayed interrupt source bit
63
3F
ICR47
300H
000FFF00H
Reserved for system
(used in REALOS)
64
40
-
2FCH
000FFEFCH
Reserved for system
(used in REALOS)
65
41
-
2F8H
000FFEF8H
Reserved for system
66
42
-
2F4H
000FFEF4H
Reserved for system
67
43
-
2F0H
000FFEF0H
Reserved for system
68
44
-
2ECH
000FFEECH
Reserved for system
69
45
-
2E8H
000FFEE8H
Reserved for system
70
46
-
2E4H
000FFEE4H
Reserved for system
71
47
-
2E0H
000FFEE0H
Reserved for system
72
48
-
2DCH
000FFEDCH
Reserved for system
73
49
-
2D8H
000FFED8H
Reserved for system
74
4A
-
2D4H
000FFED4H
Reserved for system
75
4B
-
2D0H
000FFED0H
Reserved for system
76
4C
-
2CCH
000FFECCH
Reserved for system
77
4D
-
2C8H
000FFEC8H
Reserved for system
78
4E
-
2C4H
000FFEC4H
Reserved for system
79
4F
-
2C0H
000FFEC0H
Used in INT instruction
80
to
255
50
to
FF
-
2BCH
to
000H
000FFEBCH
to
000FFC00H
Interrupt source
Offset
Default address
of TBR
*1: Even though the TBR value is changed the fixed addresses. 000FFFFCH and 000FFFF8H are always used for the reset
vector and the mode vector.
*2: The maskable source is defined for each model.
For the vector table, see "APPENDIX B Interrupt Vector".
69
CHAPTER 3 CPU and CONTROL UNIT
3.7.7
Multiple EIT Processing
When a number of EIT factors are simultaneously generated, the CPU selects and
accepts one EIT factor, and after executing the EIT sequence, the detection of EIT
factors is repeated. When EIT factors are detected, if there are no more EIT factors that
can be accepted, the handler command for the last EIT factor accepted will be executed.
As a result, the order of executing handlers for multiple EIT factor that occur at the
same time is determined according to the following two elements:
• Priority of EIT causes to be accepted
• How other causes can be masked when one cause is accepted
■ Priority of EIT Factor To Be Accepted
The priority of EIT factor to be accepted is the order of causes for which the EIT sequence is to be executed
that is, saving the PS and PC, updating the PC, and masking other causes (if required).
It is because handler of the factor previously accepted is not previously executed necessarily.
Table 3.7-4 lists the acceptance priority of EIT causes.
Table 3.7-4 Priority of EIT Causes to Be Accepted and Masking of Other Causes
Priority of acceptance
Cause
Masking of other causes
1
Reset
Other causes are abandoned.
2
Undefined instruction exception
Cancellation
3
INT instruction
I flag=0
4
Coprocessor absent trap
Coprocessor error trap
5
User interrupt
ILM=level of cause accepted
6
NMI (for users)
ILM=15
7
(INTE instruction)
ILM=4 *
8
NMI (for emulator)
ILM=4
9
Step trace trap
ILM=4
10
INTE instruction
ILM=4
-
*: The priority is 6 only if the INTE instruction and the NMI for emulators occur at the same time. (For
this product, the NMI for emulators is used for breaks due to data access.)
70
CHAPTER 3 CPU and CONTROL UNIT
In consideration of masking other causes after an EIT cause is accepted, the handlers of EIT causes that
occur at the same time are executed in the order shown in Table 3.7-5.
Table 3.7-5 Order of Executing EIT Handlers
Order of executing handlers
Cause
1
Reset *1
2
Undefined instruction exception
3
Step trace trap *2
4
INTE instruction *2
5
NMI (for users)
6
INT instruction
7
User interrupt
8
Coprocessor absent trap and coprocessor error trap
*1: Other causes are abandoned.
*2: If the INTE instruction is executed in steps, only a step trace trap EIT occurs.
An INTE cause is ignored.
Figure 3.7-2 shows the multiple EIT processing example.
Figure 3.7-2 Multiple EIT Processing
Main routine
Handler of NMI
Handler of INT
instruction
Priority level
(High) NMI generated
1) Execution at the first
(Low) INT instruction execution
2) Execution at the next
71
CHAPTER 3 CPU and CONTROL UNIT
3.7.8
Operations
This section describes operations of the FR family.
In the following, it is assumed that the transfer source PC indicates the address of the
instruction that detected an EIT cause. In addition, "address of the next instruction"
means that the instruction that detected EIT is as follows:
• If LDI:32 PC + 6
• If LDI:20 and COPOP, COPLD, COPST, and COPSV are used: PC + 4
• Other instructions: PC + 2
■ Operation of User Interrupt/NMI
If an interrupt request for a user interrupt or a user NMI occurs, whether the request can be accepted is
determined with the following procedure:
[Enable or disable judgment of interrupt demand acceptance]
1. The interruption levels of requests that are generated simultaneously are compared, and the one with the
highest level (the smallest numeric value) will be selected.
As levels to be compared, the value held in the corresponding ICR is used for a maskable interrupt and a
predetermined constant is used for an NMI.
2. If multiple interrupt requests with the same level occur, select the interrupt request with the smallest
interrupt number.
3. Mask and do no accept an interrupt request with an interrupt level greater than or equal to the level mask
value. Go to Step 4 if the interrupt level is less than the level mask value.
4. Mask and do not accept the selected interrupt request if it is maskable and the I flag is set to "0". Go to
Step 5 if the I flag is "1". If the selected interrupt request is an NMI, go to Step 5 regardless of the I flag
value.
5. If the above conditions are met, the interrupt request is accepted at a break in the instruction processing.
If a user interrupt or NMI request is accepted when EIT requests are detected, the CPU operates as follows,
using an interrupt number corresponding to the accepted interrupt request.
Note: Parentheses in [Operation] show an address indicated by the register.
[Operation]
1. SSP-4 --> SSP
2. PS --> (SSP)
3. SSP-4 --> SSP
4. Address of the following instruction --> (SSP)
5. Interrupt level of accepted request --> ILM
6. "0" --> S flag
7. (TBR + Vector offset of accepted interrupt request) --> PC
After the interrupt sequence is ended, new EIT is detected before first instruction of the handler is executed.
At this time, if an acceptable EIT occurs, CPU transits to the EIT processing sequence.
If OR CCR, ST ILM, MOV Ri, and PS instruction have been executed to permit interrupting with user
interrupt or NMI source, the above-mentioned instruction might be executed twice before or after the
interruption handler. However, there is no problem for operating because it sets the same value to the
register in CPU twice.
72
CHAPTER 3 CPU and CONTROL UNIT
Please do not do processing to expect the content of the PS register (that is the content before EIT diverges)
in the EIT processing routine.
■ Operation of INT Instruction
INT #u8 :
A branch to the interrupt handler for the vector indicated by u8 generation.
[Operation]
1. SSP-4 --> SSP
2. PS --> (SSP)
3. SSP-4 --> SSP
4. PC + 2 --> (SSP)
5. "0" --> I flag
6. "0" --> S flag
7. (TBR + 3FCH-4 × u8) --> PC
■ Operation of INTE Instruction
INTE :
A branch to the interrupt handler for the vector indicated by vector number #9 generation.
[Operation]
1. SSP-4 --> SSP
2. PS --> (SSP)
3. SSP-4 --> SSP
4. PC + 2 --> (SSP)
5. "00100B" --> ILM
6. "0" --> S flag
7. (TBR+3D8H) --> PC
Do not use the INTE command during the INTE command and step trace trap processing routine.
Moreover, EIT is not generated while executing the step by INTE.
73
CHAPTER 3 CPU and CONTROL UNIT
■ Operation of Step Trace Trap
Set the T flag in the SCR of the PS to enable the step trace function. A trap and a break then occur every
time an instruction is executed.
[Step trace trap detection conditions]
1. T flag =1
2. There is no delayed branch instruction.
3. A processing routine other than the INTE instruction or a step trace trap is in progress.
4. If the above conditions are met, a break occurs between instruction operations.
[Operation]
1. SSP-4 --> SSP
2. PS --> (SSP)
3. SSP-4 --> SSP
4. Address of next instruction --> (SSP)
5. "00100B" --> ILM
6. "0" --> S flag
7. (TBR + 3CCH) --> PC
When step trace traps are enabled by setting the T flag, NMI for users and user interruption are disabled.
Moreover, EIT by the INTE instruction is not generated.
In the FR family, the trap is generated from the following instruction by which T flag is set.
■ Operation of Undefined Instruction Exception
If, during instruction decode, an undefined instruction is detected, an undefined instruction exception
occurs.
[Detection condition of undefined instruction exception]
1. It is detected that it is undefined instruction at the decode of the instruction.
2. The instruction is not located in the delay slot (it does not immediately follow the delayed branch
instruction).
3. If the above conditions are met, an undefined instruction exception and a break occur.
[Operation]
1. SSP-4 --> SSP
2. PS --> (SSP)
3. SSP-4 --> SSP
4. PC --> (SSP)
5. "0" --> S flag
6. (TBR + 3C4H) --> PC
The PC value to be saved is the address of an instruction that detected an undefined instruction exception.
74
CHAPTER 3 CPU and CONTROL UNIT
■ No-coprocessor Trap
When a coprocessor command using an unmounted coprocessor is executed, a coprocessor absence trap
will be generated.
[Operation]
1. SSP-4 --> SSP
2. PS --> (SSP)
3. SSP-4 --> SSP
4. Address of next instruction --> (SSP)
5. "0" --> S flag
6. (TBR + 3E0H) --> PC
■ Coprocessor Error Trap
If an error occurs while a coprocessor is being used and then a coprocessor instruction that operates on the
coprocessor is executed, a coprocessor error trap occurs.
[Operation]
1. SSP-4 --> SSP
2. PS --> (SSP)
3. SSP-4 --> SSP
4. Address of next instruction --> (SSP)
5. "0" --> S flag
6. (TBR + 3DCH) --> PC
■ Operation of RETI Instruction
The RETI instruction is an instruction which returns from EIT processing routine.
[Operation]
1. (R15) --> PC
2. R15 + 4 --> R15
3. (R15) --> PS
4. R15 + 4 --> R15
The RETI instruction must be executed while the S flag is set to "0".
75
CHAPTER 3 CPU and CONTROL UNIT
3.8
Operating Mode
This section explains the operating mode of the FR family.
■ Overview of Operating Mode
In the operation mode, there are a bus mode and an access mode.
■ Bus Mode
Bus mode indicates the mode that controls the internal ROM operations and external access function
operations and is specified using the mode set up terminals (MD2, MD1, MD0) and ROMA bit contents
within the mode data.
■ Access Mode
Access mode indicates the mode that controls the external data bus width and is specified by the WTH1/
WTH0 bits in the mode register and the DBW0 bit within ACR0 to ACR3 (Area Configuration Registers).
76
CHAPTER 3 CPU and CONTROL UNIT
3.8.1
Bus Modes
In the FR family, there are three bus modes shown next.
Refer to "3.1 Memory Space".
■ Bus Mode 0 (Single-chip Mode)
The internal I/O, F-bus RAM, and F-bus ROM are valid, while access to any other areas is invalid under
this mode.
The external pins serve as peripherals or general-purpose ports. The pin does not work as a bus pin.
■ Bus Mode 1 (Internal ROM External Bus Mode)
The internal I/O, F-bus RAM, and F-bus ROM are valid, and access to areas where external access is
enabled will access external space under this mode. A part of an external pin functions as a bus pin.
■ Bus Mode 2 (External ROM External Bus Mode)
In this mode, internal I/O, and F-bus RAM are valid, but access to F-bus ROM is invalid. All accesses are
handled as access to an external space. A part of an external pin functions as a bus pin.
77
CHAPTER 3 CPU and CONTROL UNIT
3.8.2
Mode Settings
In the FR family, set the operating mode using the mode pins (MD2, MD1, and MD0) and
the mode register (MODR).
■ Mode Pin
Use the three mode pins (MD2, MD1, and MD0) to specify mode vector fetch.
Table 3.8-1 shows specification of the mode vector fetch.
Table 3.8-1 Specification of the Mode Vector Fetch
Mode Pin
Mode Name
Reset vector
access area
Remarks
MD2
MD1
MD0
0
0
0
Internal ROM
mode vector
Internal
-
0
0
1
External ROM
mode vector
External
The width of the bus is set
with the mode register.
Note that any setting other than those listed in the table is not allowed.
Note:
In the FR family, the external mode vector fetch by multiplex bus is not supported.
78
CHAPTER 3 CPU and CONTROL UNIT
■ Mode Register (MODR)
Mode data is data written to the mode register by a mode vector fetch (see "4.5 Reset Operation").
After the mode data is set to the mode register (MODR), the data is operated in the operation mode
according to this register.
The mode register is set when any reset trigger event occurs. A user program cannot write data to the mode
register.
Note:
Mode data which is set to mode vector needs to be set to 000FFFF8H as byte data. The FR family
uses the big endian as the byte endian, therefore set the big endian to the most significant byte,
bit31 to bit24.
Error
bit
000FFFF8H
31
Correction
bit
000FFFF8H
000FFFFCH
31
24 23
XXXXXXXX
16 15
XXXXXXXX
24 23
Mode Data
8 7
XXXXXXXX
16 15
0
Mode Data
8 7
XXXXXXXX
XXXXXXXX
Reset Vector
0
XXXXXXXX
Data can be rewritten to the mode register in emulator mode. Use an 8-bit width data transfer instruction to
rewrite data. A 16-bit or 32-bit long data transfer instruction cannot be used to rewrite data to the mode
register.
Details of the mode register are as follows.
Register details explanation
MODR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0007FCH
0
0
0
0
0
ROMA
WTH1
WTH0
XXXXXXXXB
Operation mode setting bits
[bit7 to bit3] Reserved bits
Be sure to set these bits to "00000B".
If a value other than "00000B" is set for these bits, operation is not guaranteed.
79
CHAPTER 3 CPU and CONTROL UNIT
[bit2] ROMA (Internal ROM enable bit)
It is set whether to make internal F-bus RAM and the F-bus ROM region effective.
ROMA
Function
Remarks
0
External ROM mode
The built-in F-bus RAM is enabled, and the internal ROM area
(50000H to FFFFFH) becomes the external ROM area.
1
Internal ROM mode
The built-in F-bus RAM and F-bus ROM are enabled.
[bit1, bit0] WTH1, WTH0 (Bus width specification bit)
The specification of the bus width at the external bus mode is set.
This value is set to DBW0 bit of ACR0 (CS0 region) at the external bus mode.
WTH1
WTH0
Function
0
0
8-bit bus width
0
1
16-bit bus width
1
0
1
1
Remarks
External bus mode
80
Single-chip mode
Setting disabled
Single-chip mode
CHAPTER 3 CPU and CONTROL UNIT
3.9
Clock Generation Control
This section describes clock generation control.
■ Generation of Internal Operating Clock
The internal operating clock of this device is generated as follows:
• Selection of source clock:
The sources of supply of the clock is selected.
• Generation of a base clock:
Divide the source clock by two or perform PLL oscillation to
generate a base clock.
• Generation of an internal clock:
Divide the base clock and generate four types of operating clocks,
which are supplied to each section.
Each clock generation and its control is described.
The description of each register and the detailed explanation of the flag refer to this chapter of clock
generation controller "3.9.5 Block Diagram of Clock Generation Controller" and "3.9.6 Register of Clock
Generation Controller".
φ indicates a base clock generated by dividing the source clock by two or performing PLL oscillation.
Therefore, the system base clock is a clock generated at the location where the above-mentioned internal
base clock occurs.
■ Selection of Source Clock
It explains the selection of the source clock.
A resonator is connected to external oscillator pins X0/X1 and X0A/X1A, and the source oscillation
generated by the built-in oscillator circuit is used as the source clock.
This device is the source of all clocks, including the external bus clock.
The external oscillator pins and built-in oscillator circuit can use the main clock or sub clock, and these two
clocks can be arbitrarily switched during operation.
• Main clock
The main clock, generated from the X0/X1 pins, is intended for use as a high-speed clock.
• Sub clock
The sub clock, generated from the X0A/X1A pins, is intended for use as a low-speed clock.
The main clock is multiplied by the built-in main PLL, which can be controlled.
Generate an internal base clock by selecting one of the following source clocks:
• Main clock divided by two
• Main clock multiplied in the main PLL
• Sub clock as it is
Select a source clock by setting the clock source control register (CLKR).
81
CHAPTER 3 CPU and CONTROL UNIT
3.9.1
PLL Controls
The operation (oscillation) enable and disable and multiply-by-rate setting can be
independently controlled for each of the PLL oscillation provided for each of main
clock.
Each control is done by setting CLKR (clock source control register).
This section describes each control.
■ PLL Operation Enable
To enable or disable the main PLL oscillation operation, set bit10 (PLL1EN bit) of the clock source control
register (CLKR).
To enable or disable the sub clock oscillation operation, set bit11 (PLL2EN bit) of the clock source control
register (CLKR).
After a settings initialization reset (INIT), bits PLL1EN and PLL2EN are initialized to "0", causing the PLL
oscillation operation to stop. While it is stopped, PLL output cannot be selected as the source clock.
When the program operation starts, set the multiply-by rate of the PLL to be used as the clock source,
enable it, and switch the source clock after the PLL lock wait time elapses. For the PLL lock wait time, use
of a time-base timer interrupt is recommended.
While PLL output is selected as the source clock, the PLL cannot be stopped (writing to the register is
disabled). To stop a PLL upon transition to stop mode, reselect the source clock as the main clock divided
by two before stopping the PLL.
If bit0 (OSCD1 bit) or bit1 (OSCD2 bit) of the standby control register (STCR) is set to stop oscillation in
stop mode, the corresponding PLL automatically stops when the device enters stop mode. As a result, you
do not need to set operation stop. When the device returns from stop mode later, the PLL automatically
restarts the oscillation operation. If oscillation is not set to stop in stop mode, the PLL does not
automatically stop. In this case, set operation stop before transition to stop mode as required.
82
CHAPTER 3 CPU and CONTROL UNIT
■ PLL Multiply-by Rate
Set the multiply-by rate of the main PLL in bit14 to bit12 (PLL1S2, PLL1S1, and PLL1S0 bits) of the
clock source control register (CLKR).
After a settings initialization reset (INIT), all bits are initialized to "0".
[PLL multiplication rate setting]
To change the PLL multiply-by rate setting from the initial value, do so before or as soon as the PLL is
enabled after the program has started execution. After changing the multiply-by rate, switch the source
clock after the lock wait time elapses. For the PLL lock wait time, use of a time-base timer interrupt is
recommended.
To change the PLL multiply-by rate setting during operation, switch the source clock to a clock other than
the PLL in question before making the change. After changing the multiply-by rate, switch the source
clock after the lock wait time has elapsed, as described above.
You can also change the PLL multiply-by rate setting while using a PLL. In this case, however, the
program stops running after the device automatically enters the oscillation stabilization wait state after the
multiply-by rate setting is rewritten and does not resume execution until the specified oscillation
stabilization wait time has elapsed.
The program does not stop running if the clock source is switched to a clock other than a PLL.
83
CHAPTER 3 CPU and CONTROL UNIT
3.9.2
Oscillation stability waiting and PLL lock waiting time
If a clock selected as the source clock is not already stabilized, an oscillation
stabilization wait time is required.
Lock waiting time is required for the PLL after operation is started until the output has
stabilized to the frequency that has been set.
This section describes the wait time used in various situations.
■ Wait Time after Power-on
After a power-on, Low level must be inputted to the INIT pin input (reset pin). Under this status, no PLL is
enabled for operation, so lock waiting time does not need to be considered at this stage.
■ Wait Time after Setting Initialization
If a settings initialization reset (INIT) is cleared, the device enters the oscillation stabilization wait state.
Here, the set oscillation stability waiting time is internally generated.
Under this status, no PLL is enabled for operation, so lock waiting time does not need to be considered at
this stage.
■ Wait Time after Enabling a PLL
If you enable a stopped PLL after a program starts execution, use the PLL output only after the lock wait
time elapses. If the PLL is not selected as the source clock, the program can run even during the lock wait
time. For the PLL lock wait time, use of a time-base timer interrupt is recommended.
■ Wait Time after Changing the PLL Multiply-by Rate
If you change the multiply-by rate setting of a running PLL after a program starts execution, use the PLL
output only after lock wait time elapses.
If the PLL is not selected as the source clock, the program can run even during the lock wait time.
For the PLL lock wait time, use of a time-base timer interrupt is recommended.
■ Wait Time after Returning from Stop Mode
If, after a program starts execution, the device enters stop mode and then stop mode is cleared, the
oscillation stabilization wait time specified in the program is internally generated. If the clock oscillation
circuit selected as the source clock is set to stop in stop mode, the oscillation stabilization wait time of the
oscillation circuit or the lock wait time of the PLL in use, whichever is longer, is required. Set the
oscillation stabilization wait time before entering stop mode.
If the clock oscillation circuit selected as the source clock is not set to stop in stop mode, the PLL does not
automatically stop. No oscillation stabilization wait time is required unless the PLL has stopped. Setting
the oscillation stabilization wait time to the minimum value before stop mode is entered is recommended.
■ Waiting Time to the Main Clock from Sub Clock
The PLL output cannot be used before the lock waiting time passes when PLL is used after it switches from
a sub clock to the main clock. This condition doesn't depend on the value of bit2-PLL1EN of CLKR (clock
source register).
If PLL that corresponds as a source clock has not been selected, the program operating can be used during
the lock waiting time.
Using the time-base timer interruption is recommended as PLL lock waiting time at this case.
84
CHAPTER 3 CPU and CONTROL UNIT
3.9.3
Clock Distribution
An operating clock for each function is generated based on the base clock generated
from the source clock.
A total of three internal operating clocks are provided. A divide-by rate can be set
independently for each of them.
This section describes these internal operating clocks.
■ CPU Clock (CLKB)
This clock is used for the CPU, internal memory, and internal buses.
It is used by the following circuits:
• CPU
• Built-in RAM and ROM
• Bit search module
• I-bus, D-bus, X-bus, and F-bus
• DMA controller
• DSU
Since 32 MHz is the upper-limit frequency for operation, do not set a combination of multiply-by rate and
divide-by rate that results in a frequency exceeding this limit.
■ Peripheral Clock (CLKP)
This clock is used for peripheral circuits and peripheral buses.
It is used by the following circuits:
• Peripheral (surrounding) bus
• Clock controller (only for the bus interface)
• Interrupt controller
• Peripheral I/O ports
• I/O port bus
• External interrupt input
• UART
• 16-bit timer
• A/D converter
• ICU
• Free-run timer
• Reload timer
• Up/down counter
• Input capture
• Output compare
• I2C interface
• PPG
Since 32 MHz is the upper-limit frequency for operation, do not set a combination of multiply-by rate and
divide-by rate that results in a frequency exceeding this limit.
85
CHAPTER 3 CPU and CONTROL UNIT
■ External Bus Clock (CLKT)
It is a clock used for the external bus interface.
It is used by the following circuits:
• External bus interface
• External CLK output (SYSCLK)
Since 16 MHz is the upper-limit frequency for operation, do not set a combination of multiply-by rate and
divide-by rate that results in a frequency exceeding this limit.
Note:
The processing capability of CPU is affected by the setting of the wait register (FLWC). Be sure to
set this register to an optimum value before using it. See also "26.2.2 Wait Register (FLWC)".
86
CHAPTER 3 CPU and CONTROL UNIT
3.9.4
Clock Division
A divide-by rate from base clock can be set independently for each of the internal
operating clocks. With this function, an optimal operating frequency can be set for
each circuit.
■ Setting of Divide-by Rate
The division rate is set up using basic clock division setup registers 0 (DIVR0) and 1 (DIVR1).
There are 4 setting bits that support each clock in each register, and (register set up value + 1) will be the
division rate for the base clock of that clock. Even if the ratio of dividing frequency setting is an odd
number, Duty always becomes 50.
If the setting value is changed, the new divide-by rate becomes valid at the leading edge of the next clock
after the setting is made.
■ Initialization of Dividing Frequency Ratio Setting
The divide-by rate setting is not initialized if an operation initialization reset occurs and the setting made
before the reset occurs is retained. The divide-by rate setting is initialized only if a settings initialization
reset occurs. In the initial state, all clocks other than the peripheral clock (CLKP) have a divide-by rate of
"1". Thus, be sure to set the divide-by rate before changing the source clock to a faster clock.
Note:
An upper-limit frequency for the operation is set for each clock. If you set a combination of source
clock, PLL multiply-by rate setting, and divide-by rate setting that results in a frequency exceeding
this upper-limit frequency, operation is not guaranteed. (Be extra careful of the order in which you
change settings to select the source clock and to configure the associated setting items.)
87
CHAPTER 3 CPU and CONTROL UNIT
3.9.5
Block Diagram of Clock Generation Controller
Figure 3.9-1 shows a block diagram of the clock generation controller.
Please refer to "3.9.6 Register of Clock Generation Controller" for a detailed
explanation of the register in figure.
■ Block Diagram of Clock Generation Controller
Figure 3.9-1 Block Diagram of Clock Generation Controller
Peripheral stop
control register
[Clock generation block]
External bus clock division
Main oscillation
stabilization wait timer
(for use with sub clock
selected)
X1
X0A*
X1A*
Oscillation
circuit
Oscillation
circuit
Each peripheral clock
Each block bus clock
PLL
Main
oscillation
Sub-oscillati
on
1/2
Selector
X0
CLKR register
Peripheral
stop control
Peripheral clock division
CPU clock
Stop control
R-bus
CPU clock division
Selector Selector Selector
DIVR0,DIVR1 register
Watch timer
[Stop and sleep control block]
Internal instruction
STCR register
Internal reset
Status
transfer
control
circuit
Stop state
SLEEP state
Reset generated
F/F
Reset generated
F/F
Internal reset (RST)
Internal reset (INIT)
[Reset factor circuit]
INIT pin
RS RR register
[Watchdog control block]
Watchdog F/F
WPR register
Time-base counter
CTBR register
TBCR register
Interrupt enabled
*: At MB91F273,MB91F278
88
Counter clock
Selector
Overflow detection F/F
Time-base timer
interrupt request
CHAPTER 3 CPU and CONTROL UNIT
3.9.6
Register of Clock Generation Controller
This section describes the functions of registers to be used in the clock generation
controller.
■ Reset Source Register/Watchdog Timer Control Register (RSRR)
The following shows the configuration of the reset source register/watchdog timer control register (RSRR).
RSRR
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000480H
R
R
WDOG
R
ERST
R
SRST
R
R
WT1
R/W
WT0
R/W
X***X*00B
R/W:
R:
*:
X:
Readable/Writable
Read only
Initialized by the factors
Undefined
This register retains reset factors that were generated just beforehand and performs cycle setting and
initiation control of the watchdog timer.
After reading, the maintained reset factor is cleared when this register is read. If a number of resets are
generated before reading, the reset factor flags accumulate, and a number of the flags will be set. The
watchdog timer is started by writing to this register. The watchdog timer keeps working until reset is
generated after that.
[bit15] Reserved: Reserved bit
This bit is reserved.
[bit14] Reserved: Reserved bit
This bit is reserved.
[bit13] WDOG: Watchdog reset generation flag
This bit indicates whether a reset occurred due to the watchdog timer.
Value
Description
0
No INIT occurred due to the watchdog timer.
1
INIT occurred due to watchdog timer.
• This bit is initialized to "0" after a reset due to INIT pin input at power on or just after it is read.
• This bit is readable; writing to the bit has no effect on the bit value.
89
CHAPTER 3 CPU and CONTROL UNIT
[bit12] ERST: External reset generation flag
This bit indicates whether a reset occurred due to INIT pin input.
Value
Description
0
No INIT occurred due to INIT pin input.
1
INIT occurred due to INIT pin input.
• This bit is initialized to "0" after it is read.
• This bit is readable; writing to the bit has no effect on the bit value.
• When the power supply is turned on, it should take 8ms or more (at the external oscillation frequency =
4MHz) to supply "L" level to INIT pin. The flag might not be set less than the time.
[bit11] SRST: Software reset generation flag
Indicates whether reset by writing the SRST bit (software reset) of the STCR register is generated or not.
Value
Description
0
No INIT occurred due to a software reset.
1
INIT occurred due to a software reset.
• This bit is initialized to "0" after a reset due to INIT pin input at power on or just after it is read.
• This bit is readable; writing to the bit has no effect on the bit value.
[bit10] Reserved: Reserved bit
This bit is reserved.
[bit9, bit8] WT1, WT0: Watchdog timer interval time selection bit
This bit sets the interval of the watchdog timer.
The values written to these bits determine the interval of the watchdog timer, which can be selected from
the four types shown in the following table.
Minimum required interval for writing to
the WPR to suppress a watchdog
reset
Time from writing the last 5AH to the
WPR until a watchdog reset occurs
0
φ × 216 (initial value)
φ × 216 to φ × 217
0
1
φ × 218
φ × 218 to φ × 219
1
0
φ × 220
φ × 20 to φ × 221
1
1
φ × 222
φ × 22 to φ × 223
WT1
WT0
0
φ: interval of the system base clock
• These bits are initialized to "00B" after a reset.
• These bits are readable, but are writable only once after a reset. Any further writing is disabled.
90
CHAPTER 3 CPU and CONTROL UNIT
■ Standby Control Register (STCR)
The following shows the configuration of the standby control register (STCR).
STCR
Address
bit7
bit6
bit5
bit4
bit3
bit2
000481H
STOP
R/W
SLEEP
R/W
HIZ
R/W
SRST
R/W
OS1
R/W
OS0
R/W
bit1
bit0
OSCD2 OSCD1
R/W
R/W
Initial value
00110011B
R/W: Readable/Writable
It is a register which controls the operation mode of the device.
This register controls the transition to the two standby modes of stop and sleep, pins when in stop mode,
and the oscillation stop. It also sets the oscillation stabilization wait time and issues software resets.
Note:
Please use the following sequences, if it is going to the standby mode.
(LDI#value_of_standby,R0) ;value_of_standby is write data to STCR
(LDI#_STCR,R12)
;_STCR is address (481H) of STCR
STB R0,@R12
;Writing in standby control register (STCR)
LDUB @R12,R0
;STCR read for synchronous standby
LDUB @R12,R0
;Dummy re-reading of STCR
NOP
;NOP for timing adjustment: x5
NOP
NOP
NOP
NOP
[bit7] STOP: STOP mode bit
This bit specifies entry into stop mode. If "1" is written to both bit6 (SLEEP bit) and this bit, this bit has
precedence and the device enters stop mode.
Value
Description
0
Stop mode not entered [Initial value]
1
Stop mode entered
• This bit is initialized to "0" by a reset and by a stop return source.
• This bit is readable and writable.
91
CHAPTER 3 CPU and CONTROL UNIT
[bit6] SLEEP: SLEEP mode bit
This bit specifies entry into stop mode. If "1" is written to both bit7 (STOP bit) and this bit, bit7 (STOP
bit) has precedence and the device enters stop mode.
Value
Description
0
Stop mode not entered [Initial value]
1
Stop mode entered
• This bit is initialized to "0" by a reset and by a sleep return source.
• This bit is readable and writable.
[bit5] HIZ: Hi-Z mode bit
The state of the terminal at the stop mode is controlled.
Value
Description
0
The state of the terminal before shifting the stop mode is maintained.
1
The state of terminal is set to the high impedance in the stop mode. [Initial value]
• This bit is initialized to "1" by a reset.
• This bit is readable and writable.
[bit4] SRST: Software reset bit
This bit specifies issuing of a software reset.
Value
Description
0
A software reset is issued.
1
A software reset is not issued [Initial value]
• This bit is initialized to "1" by a reset.
• This bit is readable and writable. The read value is always "1".
92
CHAPTER 3 CPU and CONTROL UNIT
[bit3, bit2] OS1, OS0: Oscillation stabilization wait time selection bit
These bits set the oscillation stabilization wait time used after a reset, return from stop mode, etc.
The values written to these bits determine the oscillation stabilization wait time, which can be selected
from the four types shown in the following table.
OS1
OS0
Oscillation Stabilization
Wait Time
At 4MHz source
oscillation
At 32kHz sub
oscillation
0
0
φ × 212
1.97ms
256ms
0
1
φ × 212
1.97ms
256ms
1
0
φ × 213
4.1ms
512ms
1
1
φ × 214
8.2ms
1024ms
φ: Interval of the system base clock; in this case, twice the cycle of the source oscillation input
• These bits are readable and writable.
[bit1] OSCD2: Sub oscillation stop bit
This bit controls stopping of the sub-oscillation in stop mode.
Value
Description
0
Not stopping the sub-oscillation in stop mode
1
Stopping the sub-oscillation in stop mode [initial value]
• Initialized to "1" by reset.
• These bits are readable and writable.
[bit0] OSCD1: Main oscillation stop bit
This bit controls stopping of main oscillation in stop mode.
Value
Description
0
Main clock oscillation does not stop in stop mode.
1
Main clock oscillation stops in stop mode [initial value]
• This bit is initialized to "1" by a reset.
• This bit is readable and writable.
93
CHAPTER 3 CPU and CONTROL UNIT
■ Time-base Counter Control Register (TBCR)
The register configuring of the time-base counter control register is as follows.
TBCR
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000482H
TBIF
R/W
TBIE
R/W
TBC2
R/W
TBC1
R/W
TBC0
R/W
R/W
R
R
00XXXX11B
R/W: Readable/Writable
R:
Read only
X:
Undefined
The time-base counter control register controls time-base timer interrupts, among other things.
Enables time-base timer interruption, selects interruption interval time.
[bit15] TBIF: Time-base timer interrupt flag
This bit is the time-base timer interrupt flag.
It indicates that the interval time (Set by TBC2 to TBC0 bits, which are bit13 to bit11) specified by the
time-base counter has elapsed.
A time-base timer interrupt request is generated if this bit is set to "1" when interrupts are enabled by
bit14 (TBIE bit, TBIE=1).
Clear factor
It is cleared when it is written "0" by instruction.
Set factor
It is set by specified interval time elapse (The time elapse is judged by detecting the
rising edge of the time-base counter output).
• Initialized to "0" by reset.
• This bit is readable and writable. Note, however, that only "0" can be written. Writing "1" will not
change the bit values.
• The value read by a read modify write instruction is always "1".
[bit14] TBIE: Time-base timer interrupt permission bit
It is a time-base timer interruption demand output permission bit.
It controls output of an interrupt request when the interval time of the time-base counter has elapsed. A
time-base timer interrupt request is generated if bit15 (TBIF bit) is set to 1 when this bit is set to "1".
Value
Description
0
Time-base timer interrupt request output is disabled. [initial value]
1
Time-base timer interrupt request output is enabled.
• Initialized to "0" by reset.
• This bit is readable and writable.
94
CHAPTER 3 CPU and CONTROL UNIT
[bit13 to bit11] TBC2, TBC1, TBC0: Time-base timer counter selection bit
The interval time of the time-base counter used with the time-base timer is set.
The values written to these bits determine the interval time, which can be selected from the eight types
shown in table below.
TBC2 TBC1 TBC0
Timer interval
If the source oscillation is
Assuming a sub clock
time
4 MHz and PLL is multiplied by 8 frequency of 32 kHz
0
0
0
φ × 211
64µs
61.4ms
0
0
1
φ × 212
128µs
123ms
0
1
0
φ × 213
256µs
246ms
0
1
1
φ × 222
131ms
126s
1
0
0
φ × 223
262ms
256s
1
0
1
φ × 224
524ms
512s
1
1
0
φ × 225
1049ms
1024s
1
1
1
φ × 226
2097ms
2048s
φ: Interval of the system base clock
• The initial value is undefined. Please set the value before permitting interrupting.
• These bits are readable and writable.
[bit10] Reserved: Reserved bit
This bit is reserved bit. The reading value is undefined. No effect on writing.
[bit9, bit8] Reserved: Reserved bits
These bits are reserved.
95
CHAPTER 3 CPU and CONTROL UNIT
■ Time-base Counter Clear Register (CTBR)
The register configuring of time-base counter clear register is as follows.
CTBR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000483H
D7
W
D6
W
D5
W
D4
W
D3
W
D2
W
D1
W
D0
W
XXXXXXXXB
W:
X:
Write only
Undefined
It is a register to initialize the time-base counter.
If {A5H} and {5AH} are written successively to this register, all the bits in the time-base counter are
cleared to "0" as soon as {5AH} is written. There is no time limit between writing of {A5H} and {5AH}.
However, if data other than {5AH} is written after {A5H} is written, {A5H} must be written again before
{5AH} is written. Otherwise, a clear operation will not occur.
The reading value of this register is undefined.
Note:
If the time-base counter is cleared using this register, the oscillation stabilization wait interval,
watchdog timer interval, and time-base timer interval temporarily vary.
96
CHAPTER 3 CPU and CONTROL UNIT
■ Clock Source Control Register (CLKR)
The register configuring of the clock source control register is as follows.
CLKR
Address
bit15
000484H
R/W
bit14
bit13
bit12
bit11
bit10
bit9
PLL1S2 PLL1S1 PLL1S0 PLL2EN PLL1EN CLKS1
R/W
R/W
R/W
R/W
R/W
R/W
bit8
Initial value
CLKS0
R/W
00000000B
R/W: Readable/Writable
The clock source control register is used to select the clock source that will be used as the base clock of the
system and control the PLL.
Use this register to select one of three clock sources. This register also enables the main PLL and each of
the sub-PLLs and selects the multiply-by rate for them.
[bit15] Reserved: Reserved bit
Reserved bit. Be sure to set this bit to "0".
[bit14 to bit12] PLL1S2, PLL1S1, PLL1S0: PLL multiply-by rate selection bits
These bits are the multiply-by rate selection bits for the main PLL.
Select one of the eight multiply-by rates for the main PLL shown in table.
Rewriting of this bit is disabled while the main PLL is selected as the clock source.
The upper-limit frequency for operation is 32 MHz. Do not set a multiply-by rate that results in a
frequency exceeding this limit.
PLL1S2 PLL1S1 PLL1S0
Main PLL multiplyby rate
System base clock cycle
× 1 (equal)
For source oscillator 4MHz, φ = 250ns (4MHz)
0
0
0
0
0
1
× 2 (multiplied by 2) For source oscillator 4MHz, φ = 125ns (8MHz)
0
1
0
× 3 (multiplied by 3) For source oscillator 4 MHz, φ = 83.3ns (12MHz)
0
1
1
× 4 (multiplied by 4) For source oscillator 4 MHz, φ = 62.5ns (16MHz)
1
0
0
× 5 (multiplied by 5) For source oscillator 4 MHz, φ = 50.0ns (20MHz)
1
0
1
× 6 (multiplied by 6) For source oscillator 4 MHz, φ = 41.7ns (24MHz)
1
1
0
× 7 (multiplied by 7) For source oscillator 4 MHz, φ = 35.7ns (28MHz)
1
1
1
× 8 (multiplied by 8) For source oscillator 4 MHz, φ = 31.3ns (32MHz)
φ: Interval of the system base clock
• Initialized to "000B" by reset.
• These bits are readable and writable.
97
CHAPTER 3 CPU and CONTROL UNIT
[bit11] PLL2EN: Sub clock selection enable bit
This is the selection enable bit for the sub clock.
Rewriting of this bit is disabled while the sub clock is selected as the clock source. Selection of the sub
clock as the clock source is disabled while this bit is set to "0" (because of the settings of bits 9 and 8
[bits CLKS1 and CLKS0]).
The sub clock stops in stop mode even when this bit is set to "1" as long as STCR bit1 (OSCD2) is set to
"1". After the device returns from the stop mode, the sub clock is enabled again.
Value
Description
0
Sub clock stopped [initial value]
1
Sub clock enabled
• Initialized to "0" by reset.
• This bit is readable and writable.
Note:
The PLL2EN bit is fixed to "0" in the product without the sub oscillation, and writing is invalid.
[bit10] PLL1EN: Main PLL enable bit
This bit is the operation enable bit of the main PLL.
Rewriting of this bit is disabled while the main PLL is selected as the clock source. Selection of the main
PLL as the clock source is disabled while this bit is set to "0" (because of the settings of bit9 and bit8
[bits CLKS1 and CLKS0]).
The main PLL stops in stop mode even when this bit is set to "1" as long as STCR bit 0 (OSCD1) is set
to "1". After the device returns from the stop mode, the main PLL is enabled again.
Value
Description
0
Main PLL stopped [initial value]
1
Main PLL enabled
• Initialized to "0" by reset.
• This bit is readable and writable.
98
CHAPTER 3 CPU and CONTROL UNIT
[bit9, bit8] CLKS1, CLKS0: Clock source selection bits
These bits set the clock source to be used.
The values written to these bits determine the clock source, which can be selected from the three types
shown in table.
While bit9 (CLKS1) is set to "1", the value of bit8 (CLKS0) cannot be changed.
Cannot be changed
Can be changed
"00B" --> "11B"
"00B" --> "01B" or "10B"
"01B" --> "10B"
"01B" --> "11B" or "00B"
"10B" --> "01B" or "11B"
"10B" --> "00B"
"11B" --> "00B" or "10B"
"11B" --> "01B"
To select the sub clock in the state after reset, first write "01B" and then write "11B".
CLKS1
CLKS0
Clock source setting
0
0
Source oscillation input from X0/X1 divided by 2 [initial value]
0
1
Source oscillation input from X0/X1 divided by 2
1
0
Main PLL
1
1
Sub clock
• Initialized to "00B" by reset.
• These bits are readable and writable.
99
CHAPTER 3 CPU and CONTROL UNIT
■ Watchdog Reset Postpone Register (WPR)
The register configuring of the watchdog reset generation postpone register is as follows.
WPR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000485H
D7
W
D6
W
D5
W
D4
W
D3
W
D2
W
D1
W
D0
W
XXXXXXXXB
W:
X:
Write only
Undefined
It is a register to postpone the generation of watchdog reset.
If {A5H} and {5AH} are written successively to this register, the detection FF for the watchdog timer is
cleared immediately after {5AH} is written and the watchdog reset is postponed. There is no time limit
between writing of {A5H} and {5AH}. However, if data other than {5AH} is written after {A5H} is
written, {A5H} must be written again before {5AH} is written. Otherwise, a clear operation will not occur.
Table 3.9-1 shows the relationship between time interval for the generation of the watchdog reset and value
of the RSRR register.
If writing both data is not finished in this period, watchdog reset is generated. Writing interval that is
necessary for time until generating watchdog reset and generation control changes by the state of WT1
(bit9) and WT0 (bit8) of RSRR register.
Table 3.9-1 Time Interval for Generation of a Watchdog Reset
Time elapsing between writing of
the last 5AH to the WPR and the
generation of a watchdog reset
WT1
WT0
Required minimum interval of writing to
the WPR to suppress the generation of
a watchdog reset of the RSRR
0
0
φ × 216 [initial value]
φ × 216 to φ × 217
0
1
φ × 218
φ × 218 to φ × 219
1
0
φ × 220
φ × 220 to φ × 221
1
1
φ × 222
φ × 222 to φ × 223
Note: φ is the interval of the system base clock. WT1 and WT0 are bit9 and bit8 of the RSRR and are used
to set the watchdog timer interval.
Clearing occurs automatically while the CPU is not running, such as in the stop, sleep, or DMA transfer
state. If one of these conditions occurs, a watchdog reset is automatically postponed.
The reading value of this register is undefined.
100
CHAPTER 3 CPU and CONTROL UNIT
■ Base Clock Division Setting Register 0 (DIVR0)
The register configuring of the basic clock dividing frequency setting register 0 is as follows.
DIVR0
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000486H
B3
R/W
B2
R/W
B1
R/W
B0
R/W
P3
R/W
P2
R/W
P1
R/W
P0
R/W
00000011B
R/W: Readable/Writable
Base clock division setting register 0 (DIVR0) controls the divide-by rate of an internal clock in relation to
the base clock. This register sets the divide-by rates of the CPU clock, the clocks of an internal bus
(CLKB) and a peripheral circuit, and the peripheral bus clock (CLKP).
Note:
An upper-limit frequency for the operation is prescribed for each clock. If the combination of source
clock selected, PLL multiply-by rate setting, and divide-by rate setting results in a frequency exceeding
this upper-limit frequency, operation is unpredictable. Be extremely careful of the order in which you
change the settings when selecting the source clock.
When settings for this register are modified, after the set up, the division rate after modification from the
next clock rate will be valid.
[bit15 to bit12] B3, B2, B1, B0: CLKB division selection bits
It is the CPU clock (CLKB) clock divide-by rate set bit. Set the clock divide-by rate of the CPU, internal
memory, and internal bus clock (CLKB).
The data written to this bit selects the division rate of the clock to the base clock (clock frequency) for the
CPU and internal bus from the 16 types shown in the following table.
The upper-limit frequency for operation is 32 MHz. Do not set a divide-by rate that results in a frequency
exceeding this limit.
B3
B2
B1
B0
Clock divide-by rate
Clock frequency: if the source oscillation is
4MHz and the PLL is multiplied by 8
0
0
0
0
φ
32.0MHz [initial value]
0
0
0
1
φ × 2 (divided by 2)
16.0MHz
0
0
1
0
φ × 3 (divided by 3)
10.7MHz
0
0
1
1
φ × 4 (divided by 4)
8.00MHz
0
1
0
0
φ × 5 (divided by 5)
6.40MHz
0
1
0
1
φ × 6 (divided by 6)
5.33MHz
0
1
1
0
φ × 7 (divided by 7)
4.57MHz
0
1
1
1
φ × 8 (divided by 8)
4.00MHz
...
...
...
...
...
...
1
1
1
1
φ × 16 (divided by 16)
2.00MHz
φ: Cycle of the system base clock
• Initialized to "0000B" by reset.
• These bits are readable and writable.
101
CHAPTER 3 CPU and CONTROL UNIT
[bit11 to bit8] P3, P2, P1, P0: CLKP division selection bits
It is a clock divide-by rate setting bit of the peripheral clock (CLKP). Set the clock divide-by rate of the
peripheral circuit and the peripheral bus clock (CLKP).
The values written to these bits determine the divide-by rate (clock frequency) of the peripheral circuit
and the peripheral bus clock in relation to the base clock, which can be selected from the 16 types shown
in table below.
The upper-limit frequency for operation is 32 MHz. Do not set a divide-by rate that results in a
frequency exceeding this limit.
P3
P2
P1
P0
Clock divide-by rate
Clock frequency: if the source oscillation is
4MHz and the PLL is multiplied by 8
0
0
0
0
φ
32.0MHz
0
0
0
1
φ × 2 (divided by 2)
16.0MHz
0
0
1
0
φ × 3 (divided by 3)
10.7MHz
0
0
1
1
φ × 4 (divided by 4)
8.00MHz [initial value]
0
1
0
0
φ × 5 (divided by 5)
6.40MHz
0
1
0
1
φ × 6 (divided by 6)
5.33MHz
0
1
1
0
φ × 7 (divided by 7)
4.57MHz
0
1
1
1
φ × 8 (divided by 8)
4.00MHz
...
...
...
...
...
...
1
1
1
1
φ × 16 (divided by 16)
2.00MHz
φ: Interval of the system base clock
• These bits are initialized to "0011B" by a reset.
• These bits are readable and writable.
102
CHAPTER 3 CPU and CONTROL UNIT
■ Base Clock Division Setting Register 1 (DIVR1)
The register configuring of the basic clock dividing frequency setting register 1 is as follows.
DIVR1
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000487H
T3
R/W
T2
R/W
T1
R/W
T0
R/W
-
-
-
-
00000000B
R/W: Readable/Writable
Base clock division setting register 1 controls the divide-by rate of an internal clock in relation to the base
clock.
This register sets the divide-by rate for the external extended bus interface clock (CLKT).
Note:
An operable upper-limit frequency is provided for by each clock. If the combination of source clock
selected, PLL multiply-by rate setting, and divide-by rate setting results in a frequency exceeding this
upper-limit frequency, operation is unpredictable. Be extremely careful of the order in which you
change the settings when selecting the source clock.
When settings for this register are modified, after the set up, the division rate after modification from the
next clock rate will be valid.
103
CHAPTER 3 CPU and CONTROL UNIT
[bit7 to bit4] T3, T2, T1, T0: CLKT division selection bits
It is a clock divide-by rate setting bit of external bus clock (CLKT).
Set the clock divide-by rate of the external bus interface clock (CLKT).
The value written to these bits selects the division rate (clock frequency) of the external bus interfaces
clock to the base clock from the 16 types shown in the following table.
The upper-limit frequency for operation is 16 MHz. Do not set a divide-by rate that results in a frequency
exceeding this limit.
T3
T2
T1
T0
Clock divide-by rate
Clock frequency: if the source oscillation is
4MHz and the PLL is multiplied by 8
0
0
0
0
φ
32.0MHz [initial value]
0
0
0
1
φ × 2 (divided by 2)
16.0MHz
0
0
1
0
φ × 3 (divided by 3)
10.7MHz
0
0
1
1
φ × 4 (divided by 4)
8.00MHz
0
1
0
0
φ × 5 (divided by 5)
6.40MHz
0
1
0
1
φ × 6 (divided by 6)
5.33MHz
0
1
1
0
φ × 7 (divided by 7)
4.57MHz
0
1
1
1
φ × 8 (divided by 8)
4.00MHz
...
...
...
...
...
...
1
1
1
1
φ × 16 (divided by 16)
2.00MHz
φ: Interval of the system base clock
• These bits are initialized to "0000B" by a reset.
• These bits are readable and writable.
[bit3 to bit0] Reserved: Reserved bits
These bits are reserved.
104
CHAPTER 3 CPU and CONTROL UNIT
■ Oscillation Control Register (OSCCR)
The register configuring of the oscillation control register is as follows.
OSCCR
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
00048AH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit8
Initial value
OSCDS1 XXXXXXX0B
R/W
R/W: Readable/Writable
X:
Undefined
The oscillation control register controls the main clock oscillation during operation of the sub clock.
[bit15 to bit9] Reserved: Reserved bits
These bits are reserved.
[bit8] OSCDS1: Main clock oscillation stop control bit (in sub run mode)
This bit is the stop bit for main clock oscillation while the sub clock is selected.
Writing "1" to this bit stops main clock oscillation while the sub clock is selected as the clock source.
Writing "1" to this bit is disabled while the main clock is selected.
Selection of the main clock is disabled while this bit is set to "1". Set this bit to "0", and wait for
stabilization of the main clock oscillation. Then, switch to the main clock. Use the main oscillation
stabilization wait timer to secure the oscillation stabilization wait time.
If INIT switches the clock source to the main clock when this bit stops main clock oscillation, the main
clock oscillation stabilization wait time is also required. If the settings of bit3 and bit2 (OS1 and OS0) of
the standby control register (STCR) do not satisfy the main oscillation stabilization wait time, the
operation after return is unpredictable. In this case, set values that satisfy both the sub clock oscillation
stabilization wait time and the main clock oscillation stabilization wait time in the STCR (OS1 and OS0)
bits.
For details about the oscillation stabilization wait, see "3.9.2 Oscillation stability waiting and PLL lock
waiting time".
Value
Description
0
Main clock oscillation is not stopped during execution of sub clock [initial value]
1
Main clock oscillation is stopped during execution of sub clock.
• This bit is initialized to "0" after a reset.
• This bit can be read and written.
105
CHAPTER 3 CPU and CONTROL UNIT
3.9.7
Peripheral Circuits of Clock Controller
This section describes the peripheral circuit functions of the clock controller.
■ Time-base Counter
The clock controller has a 26-bit time-base counter that runs on the system base clock.
The time-base counter is used to measure the oscillation stabilization wait time in addition to having the
uses listed below (For more information about the oscillation stabilization wait time, see "4.2 Reset Factors
and Oscillation Stabilization Wait Times").
• Watchdog timer
The watchdog timer, which is used to detect a system runaway, measures time using the bit output of the
time-base counter.
• Time-base timer
The time-base timer generates an interval interrupt using output from the time-base counter.
● Watchdog timer
The watchdog timer detects a runaway using output from the time-base counter. If postponement of the
watchdog reset is not generated between the intervals that have been set, due to a program overrun or such
like, the settings initialization reset request is generated as a watchdog reset.
[Startup and interval setting of the watchdog timer]
The watchdog timer is activated by writing to the 1st RSRR (reset factor register/watchdog timer control
register) after reset.
At this time, the interval time of the watchdog timer is set in bit9 and bit8 (WT1 and WT0 bits). Only the
time defined in this first write is valid as the interval time setting. Any further writing is ignored.
[Postponing a watchdog reset]
Once the watchdog timer is started, the program must write {A5H} and {5AH} in this order to the watchdog
reset postpone register (WPR).
The flag for the watchdog reset generation is initialized by this operation.
[Generation of a watchdog reset]
The watchdog reset generation flag is set at the trailing edge of the time-base counter output of the
specified interval. If the flag has already been set when a trailing edge is detected a second time, a settings
initialization reset request is generated as a watchdog reset.
[Stopping the watchdog timer]
The watchdog timer, once started, cannot be stopped until an operation initialization reset occurs.
Under the following status in which an operation initialization reset is generated, the watchdog timer is
stopped and does not function until activated by a re-program operation.
• State of operation initialization reset
• State of settings initialization reset
• Oscillation stabilization waiting reset state
106
CHAPTER 3 CPU and CONTROL UNIT
[Suspending the watchdog timer (automatic postponement)]
For the watchdog timer, if program operation stops on the CPU, the watchdog reset generation flag is
initialized and generation of a watchdog reset is postponed. The stop of the program operation concretely
shows the following operations.
• Sleep state
• Stop state
• Oscillation stabilization wait RUN state
• During a break taken when the emulator debugger or monitor debugger is being used
• Period from execution of INTE instruction to execution of RETI instruction
• Step trace trap
(Break of each instruction by T flag =1 of the PS register)
When the time-base counter is cleared, the flag for generating watchdog resets is simultaneously initialized,
and generation of a watchdog reset will be postponed.
A watchdog reset may not be generated in the above situation caused by the system running out of control.
In that case, please reset by external INIT pin.
● Time-base timer
The time-base timer generates an interval interrupt using output from the time-base counter. This timer is
appropriate for measurements that require a relatively long time (for example, a maximum interval of {base
clock × 227} cycles such as for the PLL lock wait time or the oscillation stabilization wait time of a sub
clock).
If the falling edge of the time-base counter output for the specified interval is detected, a time-base timer
interrupt request is generated.
[Startup and interval settings of the time-base timer]
For the time-base timer, the interval time is set in bit13 to bit11 (TBC2, TBC1, and TBC0 bits) of the timebase counter control register (TBCR). The trailing edge of the time-base counter output for the specified
interval is always detected. Thus, after setting the interval time, clear bit15 (TBIF bit) and then set bit14
(TBIE bit) to "1" to enable output of an interrupt request.
Before changing the interval time, set bit14 (TBIE bit) to "0" to disable interrupt request output.
As the time-base counter always counts without being influenced by these settings, clear the time-base
counter before enabling interruption in order to get accurate interval interruption times. Otherwise, the
interrupt request may be generated immediately after an interrupt is enabled.
[Clearing of the time-base counter due to a program]
If {A5H} and {5AH} are written in this order to the time-base counter clear register (CTBR), all bits of the
time-base counter are cleared to "0" immediately after {5AH} is written. There is no time limit between
writing of {A5H} and {5AH}. However, if data other than {5AH} is written after {A5H} is written, {A5H}
must be written again before {5AH} is written. Otherwise, no clear operation occurs.
If the time-base counter is cleared, the watchdog reset generation flag is initialized at the same time,
postponing generation of a watchdog reset.
107
CHAPTER 3 CPU and CONTROL UNIT
[Clearing of the time-base counter due to the device state]
All bits of the time-base counter are cleared to "0" at the same time if the device enters one of the following
states:
• Stop state
• State of settings initialization reset
Especially in the stop state, an interval interrupt of the time-base timer may unintentionally be generated
because the time-base counter is used to measure the oscillation stabilization wait time. Before setting stop
mode, therefore, disable time-base timer interrupts to prevent the time-base timer from being used.
For statuses other than that, time-base timer interruption is automatically disabled as operation initialization
reset is generated.
● Main Clock Oscillation Stabilization Wait Timer (for the sub clock select)
The main clock oscillation stabilization wait timer is a 26-bit timer that performs incremental counting in
synchronization with the main clock. The operation of this timer is not affected by the clock source
selection or the clock divide-by rate.
The main clock oscillation stabilization wait timer is used to measure the main clock oscillation
stabilization wait time during operation of the sub clock.
Main clock oscillation can be controlled by bit8:OSCDS1 of the oscillation control register (OSCCR) while
the device is operating on the sub clock. This timer is used to measure the oscillation stabilization wait
time when main clock oscillation is restarted after it has been stopped.
Follow the procedure below for switching the clock source to the main clock when the device is operating
on the sub clock with the main clock stopped.
1. Clear the main clock oscillation stabilization wait timer.
2. Set bit8:OSCDS1 of the oscillation control register (OSCCR) to "0" to start main clock oscillation.
3. Use the main clock oscillation stabilization wait timer to wait until the main clock oscillation is
stabilized.
4. After the main clock has been stabilized, use bit9 and bit8 (CLKS1 and CLKS0 bits) of the clock source
register (CLKR) to switch the clock source from the main clock to sub clock.
Note:
If the clock source is switched to the main clock before the main clock is stabilized, an unstable clock
is supplied and subsequent operation is unpredictable. Be sure to switch to the main clock after the
main clock has been stabilized.
For more information on the main clock oscillation stabilization wait timer, see "3.11 Main Clock
Oscillation Stabilization Wait Timer".
108
CHAPTER 3 CPU and CONTROL UNIT
3.10
Device state control
This section describes the states of the MB91270 series and their control.
■ Overview of Device State Control
The state of this device is indicated as follows.
• State of RUN (normal operation)
• Sleep state
• Stop state
• State of oscillation stability waiting RUN
• Oscillation Stabilization Waiting reset (RST) state
• State of operation initialization reset (RST)
• State of settings initialization reset (INIT)
It explains each details of above states and details of sleep mode and the stop mode that is the low-power
consumption mode at the following.
109
CHAPTER 3 CPU and CONTROL UNIT
3.10.1
State of device and each transition
Figure 3.10-1 shows the transition of device states.
■ Device States
Figure 3.10-1 Device States
1
2
3
4
5
6
7
8
9
10
11
12
13
INIT pin=0 (INIT)
INIT pin=1(INIT released)
Completion of oscillation stabilization wait
Reset (RST) released
Software reset (INIT)
Sleep (writing instruction)
Stop (writing instruction)
Interrupt
External interrupt which is not required clock
Switch from main to sub (writing instruction)
Switch from sub to main (writing instruction)
Watchdog reset (INIT)
Sub sleep (writing instruction)
Strongest
Power-on
1
Weakest
Setting initialization
(INIT)
2
Main clock mode
1
Main oscillation
stabilization wait reset
Main stop
1
3
Oscillation
stabilization wait
RUN
Program reset
(RST)
3
4
7
1
Main sleep
5, 12
Main RUN
8
*1
1
13
3
Oscillation
stabilization wait
RUN
9
Sub stop
110
11
8
Sub sleep
1
1
10
Sub clock mode
1
1
5, 12
Sub RUN
7
1
4
Program reset
(RST)
1
Priority order of transfer request
Settings initialization reset (INIT)
Oscillation stabilization wait end
Operation initialization reset (RST)
Interrupt request
Stop
CHAPTER 3 CPU and CONTROL UNIT
■ Operating State
Operating of this device is shown as follows.
● State of RUN (normal operation)
In the RUN state, a program is being executed.
All internal clocks are supplied and all circuits are enabled.
For the 16-bit peripheral bus, however, only the bus clock is stopped, when it is not being accessed.
Each status transition request is accepted.
● Sleep State
In the sleep state, a program is stopped. Program operation causes a transition to this state.
Only the program execution of CPU stops, and the peripheral circuit is operable. Built-in memory modules
and the internal and external buses are stopped unless the DMA controller issues a request.
If a settings initialization reset request occurs, the settings initialization reset (INIT) state is entered.
● Stop State
It is a stopped state of the device. Program operation causes a transition to this state.
All internal circuits stop. All internal clocks are stopped and the oscillation circuit and PLL can be stopped
if set to do so. In addition, the external pins (except some) can be set to high impedance via settings.
If a specific valid interrupt request (no clock required) and main oscillation stabilization wait timer
interrupt request during oscillation occur, the oscillation stabilization wait RUN state is entered.
If a settings initialization reset request occurs, the settings initialization reset (INIT) state is entered.
● State of oscillation stability waiting RUN
It is a stopped state of the device. This state occurs after a return from the stop state.
All internal circuits except the clock generation controller (time-base counter and device status controller)
are stopped. All internal clocks are stopped, but the oscillation circuit and the PLL that has been enabled
are running.
High impedance control of external pins in the stop or other state is cleared.
If the specified oscillation stabilization wait time elapses, the RUN state (normal operation) is entered.
If a settings initialization reset request occurs, the settings initialization reset (INIT) state is entered.
● Oscillation Stabilization Waiting reset (RST) state
It is a stopped state of the device. This state occurs after a return from the stop state or the settings
initialization reset (INIT) state.
All internal circuits except the clock generation controller (time-base counter and device status controller)
are stopped. All internal clocks are stopped, but the oscillation circuit and the PLL that has been enabled
are running.
High impedance control of external pins in the stop state, etc., is cleared.
Operation initialization reset (RST) is outputted to an internal circuit.
111
CHAPTER 3 CPU and CONTROL UNIT
If the specified oscillation stabilization wait time elapses, the oscillation stabilization wait reset (RST) state
is entered.
If a settings initialization reset request occurs, the settings initialization reset (INIT) state is entered.
● State of operation initialization reset (RST)
The program is being initialized. Transits by ending the oscillation stabilization waiting reset (RST) status.
The program execution of CPU stops, and the program counter is initialized. The peripheral circuit is
initialized excluding part. All internal clocks, the oscillation circuit and the PLL that has been enabled are
running.
Operation initialization reset (RST) is outputted to an internal circuit.
Transits to the RUN status (normal operation) by diminishing the operation initialization reset (RST)
request, and operation initialization reset sequence is executed. Settings initialization reset sequence is
executed after returning from the settings initialization reset (INIT) status.
Transits to the settings initialization reset (INIT) status by generating a settings initialization reset request.
● State of settings initialization reset (INIT)
All settings are being initialized. Transits by receiving the settings initialization reset request.
The program execution of CPU stops, and the program counter is initialized. All peripheral circuits are
initialized. PLL stops operating though the oscillation circuit operates. All internal clocks are stopped while
the "L" level is inputted to the external INIT pin; otherwise, they run.
A settings initialization reset (INIT) and an operation initialization reset (RST) are outputted to the internal
circuits.
This status is cancelled by diminishing the settings initialization reset request, and transits to the oscillation
stabilization waiting reset (RST) status. Then, the operation initialization reset (RST) state is entered and
the settings initialization reset sequence is executed.
● Priority level of each state transition demand
In any state, state transition requests conform to the priority listed below. However, some requests that
occur only in a specific state are valid only in that state
[Highest]
Settings initialization reset (INIT) request
End of oscillation stabilization wait time (occurs only in the oscillation
stabilization wait reset state and the oscillation stabilization wait RUN state)
Operation initialization reset (RST) request
Valid interrupt request (occurs only in the RUN, sleep, and stop states)
Stop mode request (writing to a register) (occurs only in the RUN state)
[Lowest]
112
Sleep mode request (writing to a register) (occurs only in the RUN state)
CHAPTER 3 CPU and CONTROL UNIT
3.10.2
Low-power Consumption Mode
This section describes the low-power consumption modes, some states, and how to
use the low-power consumption modes.
This device has the following two low-power consumption modes:
• Sleep mode: The device enters the sleep state due to writing to a register.
• Stop mode: The device enters the stop state due to writing to a register.
These modes are described below.
■ Sleep Mode
If "1" is set for bit6 (SLEEP bit) of the standby control register (STCR), sleep mode is initiated and the
device enters the sleep state. The sleep state is maintained until a source for return from the sleep state is
generated.
If "1" is set for both bit7 (STOP bit) and bit6 of the standby control register (STCR), bit7 (STOP bit) has
precedence and the device enters the stop state.
For more information about the sleep state, see "●Sleep State" in "3.10.1 State of device and each
transition".
[Transition to the sleep mode]
To enter the sleep mode, be sure to use the following sequence:
(LDI#value_of_sleep,R0)
;value_of_sleep is the write data to STCR
(LDI#_STCR, R12)
;_STCR is address (481H) of STCR.
STB
;Writing in standby control register (STCR)
R0, @R12
[email protected], R0
;STCR read for synchronous standby
[email protected], R0
;Dummy re-read of STCR
NOP
;for timing adjustment: x5
NOP
NOP
NOP
NOP
[Circuits that stop in the sleep state]
• Program execution on the CPU
• Bit search module (enabled if DMA transfer occurs)
• Various built-in memory (enabled if DMA transfer occurs)
• Internal and external buses (enabled if DMA transfer occurs)
[Circuits that do not stop in the sleep state]
• Oscillation circuit
• PLL that has been enabled
• Clock generation controller
• Interrupt controller
• Peripheral circuit
• DMA controller
113
CHAPTER 3 CPU and CONTROL UNIT
• DSU
• Main clock oscillation stabilization wait timer
[Sources of return from the sleep state]
• Generation of a valid interrupt request
If an interrupt request with an interrupt level other than interrupt disabled (1FH) occurs, sleep mode is
cleared and the RUN state (normal operation state) is entered.
To prevent sleep mode from being cleared even when an interrupt request occurs, set interrupt disabled
(1FH) as the interrupt level in the corresponding ICR.
• Generation of a settings initialization reset request
If a settings initialization reset request occurs, the settings initialization reset state is unconditionally
entered.
For information about the priority of sources, see "3.10.1 State of device and each transition".
[Synchronous standby operations]
Transition to the sleep state is not caused only by a write to the SLEEP bit.
Transition to the sleep state occurs when the STCR register is read after that.
To enter the sleep mode, be sure to use the sequence in (Transition to sleep mode).
■ Stop Mode
If "1" is set for bit7 (STOP bit) of the standby control register (STCR), stop mode is initiated and the device
enters the stop state. The stop state is maintained until a source for return from the stop state occurs.
If "1" is set for both bit6 (SLEEP bit) and bit7 bit of the standby control register (STCR), bit7 (STOP bit)
has precedence and the device enters the stop state.
For more information about the stop state, see "●Stop State" in "3.10.1
transition".
State of device and each
[Transition to the stop mode]
To enter the stop mode, be sure to use the following sequence:
(LDI#value_of_stop,R0)
;value_of_stop is the write data to STCR
(LDI#_STCR, R12)
;_STCR is address (481H) of STCR.
STB
;Writing in standby control register (STCR)
R0, @R12
[email protected], R0
;STCR read for synchronous standby
[email protected], R0
;Dummy re-read of STCR
NOP
;for timing adjustment: x5
NOP
NOP
NOP
NOP
[Circuits that stop in the stop state]
• Oscillation circuits set to stop
If "1" is set for bit1 (OSCD2 bit) of the standby control register (STCR), the sub clock oscillation circuit
in the stop state is stopped. If "1" is set for bit0 (OSCD1 bit) of the standby control register (STCR), the
main clock oscillation circuit in the stop state is stopped. In this case, the main clock oscillation
stabilization wait timer is also stopped.
• PLL connected to the oscillation circuit that is either disabled or set to stop
If "1" is set for bit0 (OSCD1 bit) of the standby control register (STCR) and "1" is set for bit10 (PLL1EN
bit) of the clock source control register (CLKR), the main clock PLL in the stop state is stopped.
• All internal circuits except those, described below, that do not stop in the stop state
114
CHAPTER 3 CPU and CONTROL UNIT
[Circuits that do not stop in the stop state]
• Oscillation circuits that are set not to stop
If "0" is set for bit1 (OSCD2 bit) of the standby control register (STCR), the sub clock oscillation circuit
in the stop state is not stopped.
If "0" is set for bit0 (OSCD1 bit) of the standby control register (STCR), the main clock oscillation
circuit in the stop state is not stopped. In this case, the main clock oscillation stabilization wait timer is
not stopped as well.
• PLL connected to the oscillation circuit that is enabled and is not set to stop
If "0" is set for bit0 (OSCD1 bit) of the standby control register (STCR) and "1" is set for bit10
(PLL1EN bit) of the clock source control register (CLKR), the main clock PLL in the stop state is not
stopped.
[High impedance control of a pin in the stop state]
If "1" is set for bit5 (HIZ bit) of the standby control register (STCR), the output of a pin in the stop state is
set to the high impedance state.
See "APPENDIX C Pin States in Each CPU State" for the pins subject this type of control.
If bit5 (HIZ bit) of the standby control register (STCR) is set to "0", the pin outputs in the stop state
maintain the values set before transition to the stop state.
For details see "APPENDIX C Pin States in Each CPU State".
[Sources of return from the stop state]
• Generation of a specific valid interrupt request (not requiring a clock)
Only the external interrupt input pins (INT0 to INT15 pins), main clock oscillation stabilization wait
timer interrupt during main clock oscillation, and watch interrupt during sub clock oscillation are
enabled.
If an interrupt request with an interrupt level other than interrupt disabled (1FH) occurs, stop mode is
cleared and the RUN state (normal operation state) is entered.
To prevent stop mode from being cleared even when an interrupt request occurs, set interrupt disabled
(1FH) as the interrupt level in the corresponding ICR register.
• Main clock oscillation stabilization wait timer interrupt: If the main clock oscillation stabilization wait
timer interrupt request occurs when "0" is set for bit8 (OSCDS1 bit) of the oscillation control register
(OSCCR) during main clock selection, the stop mode is released and the RUN state (normal operation
state) is entered.
To prevent stop mode from being cleared even when an interrupt request occurs, stop the main clock
oscillation stabilization wait timer or set interrupt enable bit of the main clock oscillation stabilization
wait timer to interrupt disabled.
• Generation of a settings initialization reset request
If a settings initialization reset request occurs, the settings initialization reset (INIT) state is
unconditionally entered.
For information about the priority of sources, see "●Priority level of each state transition demand" in
"3.10.1 State of device and each transition".
[Selecting a clock source in stop mode]
Select the main clock divided by 2 as the source clock before setting stop mode. For more information, see
"3.9 Clock Generation Control" especially Section "3.9.1 PLL Controls".
The same limitations as in the normal operation apply to the setting of a divide-by rate.
115
CHAPTER 3 CPU and CONTROL UNIT
■ Synchronous Standby Operations
Simply writing to the STOP bit does not cause a transition to the stop state. Instead, writing to the STOP
bit and then reading the STCR register causes a transition to the stop state.
In synchronous standby operation, the stop state occurs only after writing to the STOP bit actually occurs
and the reading of STCR register are completed. This is because the CPU uses the bus until the value read
from the STCR register is stored into the CPU. Thus, in any setting of relationship between divide-by rates
of the CPU clock (CLKB) and the peripheral clock (CLKP), insert only two NOP instructions after the
write instruction for the STOP bit and the read instruction for the STCR register to prevent any subsequent
instructions from being executed before transition to the stop state.
When using the stop mode, make sure that sequence in [Transition to the stop mode] is used.
116
CHAPTER 3 CPU and CONTROL UNIT
3.11
Main Clock Oscillation Stabilization Wait Timer
The main clock oscillation stabilization wait timer is a 23-bit counter that performs
incremental counting in synchronization with the main clock and has an interval timer
function to generate interrupts repeatedly for fixed time intervals.
This timer is used to secure main clock oscillation stabilization wait time when main
clock oscillation is restarted after it has been stopped by setting bit8 (OSCDS1) of the
oscillation control register (OSCCR) during operation with the sub clock.
■ Interval Time of Main Clock Oscillation Stabilization Wait Timer
Table 3.11-1 indicates the type of the interval time. Interval time can be selected from the following three
types.
Table 3.11-1 Time Intervals for Main Clock Oscillation Stabilization Wait Timer
Main clock interval
Interval time
211/FCL(512µs)
1/FCL(about 250 ns)
216/FCL(16.4ms)
223/FCL(2097ms)
Note: FCL indicates the main clock oscillation frequency.
117
CHAPTER 3 CPU and CONTROL UNIT
■ Block Diagram of Main Clock Oscillation Stabilization Wait Timer
Figure 3.11-1 indicates the block diagram of the main oscillating stabilization wait timer.
Figure 3.11-1 Block Diagram of the Main Clock Oscillation Stabilization Wait Timer
Counter for main oscillation
stabilization wait timer
FCL
0
2
1
1
2
2
3
2
2
3
4
2
4
5
6
7
8
10
5
6
7
8
9
11
2
2
2
2
2
15
2
2
22
16
223
(512µs)
Interval
timer
selector
WIF
(2097ms)
Reset
(INIT)
Main oscillation stabilization wait
timer interrupt
Main oscillation stabilization wait timer
control register (OSCR)
(16.4ms)
WIF
WEN
WS1
Counter clear
circuit
WS0
WCL
FCL: Main clock source oscillation
Numbers in parentheses are cycles when the main clock
oscillation is 4MHz.
● Main clock oscillation stabilization wait timer
The main clock oscillation stabilization wait timer is a 23-bit incremental counter that uses the main clock
source oscillation as the count clock.
● Counter clear circuit
The counter clear circuit clears the counter not only when the WCL bit of the OSCR register is set to "0"
but also when a reset is generated.
● Interval timer selector
The interval timer selector selects one of the three frequency-divide outputs of the main clock oscillation
stabilization wait timer counter for the interval timer. The falling edge of the selected frequency-divide
output becomes an interrupt source.
● Main clock oscillation stabilization wait timer control register (OSCR)
The main clock oscillation stabilization wait timer control register is used to select the interval time, clear
the counter, control interrupts, and check counter status.
118
CHAPTER 3 CPU and CONTROL UNIT
■ Main Clock Oscillation Stabilization Wait Timer Control Register
The register configuring of the main oscillation stabilization wait timer register is as follows.
OSCR
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000490H
WIF
R/W
WIE
R/W
WEN
R/W
R/W
R/W
WS1
R/W
WS0
R/W
WCL
W
00000000B
R/W: Readable/Writable
[bit15] WIF: Timer interrupt flag
This bit is the main clock oscillation stabilization wait interrupt request flag.
This bit is set to "1" at the trailing edge of the selected divided output for the interval timer.
If this bit and the main clock oscillation stabilization wait timer interrupt enable bit are "1", a main clock
oscillation stabilization wait timer interrupt request is outputted.
Value
Description
0
Main clock oscillation stabilization wait timer interrupt not requested [initial value]
1
Main clock oscillation stabilization wait timer interrupt requested
• This bit is cleared to "0" by a reset.
• Data can be written to and read from this bit. However, only "0" can be written. If an attempt is made
to write "1" to this bit, its value is not changed.
• If a read modify write instruction is issued, "1" is always read from this bit.
[bit14] WIE: Timer interrupt enable bit
This bit is used to allow and prohibit interrupt request output to the CPU. If this bit and main clock
oscillation stabilization wait timer interrupt request flag bit are "1", a main clock oscillation stabilization
wait timer interrupt request is outputted.
Value
Description
0
Output of main clock oscillation stabilization wait timer interrupt request is disabled.
[initial value]
1
Output of main clock oscillation stabilization wait timer interrupt request is enabled.
• This bit is cleared to "0" by a reset.
• Data can be written to and read from this bit.
119
CHAPTER 3 CPU and CONTROL UNIT
[bit13]WEN:Timer operation enable bit
This bit is the timer operation enable bit.
When this bit is "1", the timer is counted.
Value
Description
0
Timer operation is stopped. [initial value]
1
Timer is counted.
• The bit is initialized to "0" at a reset.
• Data can be written to and read from this bit.
[bit12, bit11] Reserved: Reserved bits
These bits are reserved. When writing data to these bits, be sure to write "0" to these bits. (Writing of
"1" to these bits is prohibited.)
Data read from these bits are undefined.
[bit10, bit9] WS1, WS0: Timer interval time selection bits
These bits select the interval of the interval timer.
One of the following three intervals is selected according to the output bits of the main clock oscillation
stabilization wait timer counter:
WS1
WS0
Interval timer interval (at FCL=4MHz)
0
0
Setting prohibited [initial value]
0
1
211/FCL(512µs)
1
0
216/FCL(16.4ms)
1
1
223/FCL(2097ms)
• These bits are cleared to "00B" by a reset.
• Data can be written to and read from these bits.
Please write data in this register when the main oscillation stabilization wait time timer is used.
[bit8] WCL: Timer clear bit
Writing "0" to this bit clears the main clock oscillation stabilization wait timer to "0".
Only "0" can be written to this bit. Writing "1" to this bit does not affect timer operation.
• The value read from this bit is always "1".
120
CHAPTER 3 CPU and CONTROL UNIT
■ Main Clock Oscillation Stabilization Wait Timer Interrupt
If the set interval time elapses while the main clock oscillation stabilization wait timer counter is counting
with the main clock, the main clock oscillation stabilization wait interrupt flag (WIF) is set to "1". Then, if
the interrupt request enable bit is enabled (WIE=1), an interrupt request is outputted to the CPU. Note that
main clock oscillation stabilization wait interrupts do not occur when main clock oscillation is stopped (see
the next item, "■Operations of the Interval Timer Functions") because counting is stopped.
To clear an interrupt request, write "0" to the WIF bit by the interrupt processing routine. Note that the
WIF bit is set to "1" at the trailing edge of the selected frequency-divide output regardless of the value of
the WIE bit.
Note:
The WIF and WCL bits must be cleared to "0" (WIF=WCL=0) at the same time if main clock
oscillation stabilization wait timer interrupt output is to be enabled (WIE = 1) or the value of the WS1
and WS0 bits are to be changed after release from the reset state.
Reference:
• If the WIE bit is changed from "0" to "1" to enable interrupt output when the WIF bit is "1", an
interrupt request is outputted immediately.
• If a counter clear (WCL bit of WPCR is "1") and overflow of selected bits occur at the same time,
the WIF bit is not set to "1".
■ Operations of the Interval Timer Functions
The main clock oscillation stabilization wait timer counter continues incremental counting while the main
clock is oscillated. When main clock oscillation stops, counting stops in the following case:
• When the WEN bit is "0"
• Counting is stopped throughout stop mode if this device is put into stop mode by stopping main clock
oscillation with bit0 [OSCD1 bit] of the standby control register [STCR] set to "1". To make the main
clock oscillation stabilization wait timer operate in stop mode, set the OSCD1 bit to "0" before entry
into the standby state because the OSCD1 bit is initialized to "1" at reset.
• The main oscillation stops when "1" is set to the bit8:OSCDS1 of OSCCR (oscillation control register)
in the sub clock mode.
The timer count operating stops, too.
If the counter is cleared (WCL bit is cleared to "0"), the counter starts counting from "000000H". When the
count reaches "7FFFFFH", the counter restarts counting from "000000H". If the trailing edge of the
frequency-divide output selected for the interval timer is detected at incremental counting, the main clock
oscillation stabilization wait timer interrupt flag (WIF) bit is set to "1". In other words, a main clock
oscillation stabilization wait timer interrupt request is generated at the selected intervals on the basis of the
cleared time.
121
CHAPTER 3 CPU and CONTROL UNIT
■ Operations of Clock Supply Function
This device uses a time-base counter to secure the oscillation stabilization wait time after INIT or stop
mode. On the other hand, this device uses the main clock oscillation stabilization wait timer to secure the
main clock oscillation stabilization wait time while the sub clock is selected as the clock source. This is
because the main clock oscillation stabilization wait timer operates on the main clock regardless of the
clock source selection.
Follow the procedure below to perform main clock oscillation stabilization wait operation from the main
clock oscillation stop state while the device is operating on the sub clock:
1. Set the time required for main clock oscillation stabilization with the WT1 and WT0 bits, and clear the
counter to "0" (by writing the oscillation stabilization wait time to the WS1 and WS0 bits and "0" to the
WCL bit).
If it is necessary to perform processing after the end of oscillation stabilization wait with an interrupt,
initialize the interrupt flag (by writing "0" to the WIF and WIE bits).
2. Start main clock oscillation (by writing "0" to bit8:OSCDS1 of OSCCR register).
3. In the program, wait until the WIF flag is set to "1".
4. Make sure that the WIF flag has been set to "1", then perform the processing to be done after the end of
oscillation stabilization wait. If interrupts are enabled, an interrupt is generated when the WIF flag is set
to "1". Then, perform the processing to be done after the end of oscillation stabilization wait by an
interrupt routine.
If it is necessary to switch the clock source from the sub clock to main clock, switch the clock source after
making sure that the 4) WIF flag has been set to "1" as described above. (If the clock source is switched to
the main clock before main clock oscillation is stabilized, an unstable clock is supplied to the entire device
and subsequent operation is unpredictable.)
■ Operation of the Main Clock Oscillation Stabilization Wait Timer
Figure 3.11-2 shows the counter states at switching to the main clock when starting main clock oscillation
stabilization wait timer.
Figure 3.11-2 Counter States at Switching to the Main Clock
When Starting Main Clock Oscillation Stabilization Wait Timer
7FFFFFH
Counter value
Main clock oscillation
stabilization wait time
• Timer clear (WCL=1) at other than 0
Clear in interrupt
• Interval time setting (WS1, WS0=11B)
routine
• Main oscillation start (OSCCR:OSCDS1=0)
WIF (interrupt request)
WIE (interrupt mask)
Clock mode
Sub clock
• Change from sub to main clock
122
Main clock
CHAPTER 3 CPU and CONTROL UNIT
■ Precautions on Using the Main Clock Oscillation Stabilization Wait Timer
Use the oscillation stabilization wait time as a reference value because the oscillation cycle is unstable
immediately after oscillation is started.
While the main clock oscillation is stopped, no main clock oscillation stabilization interrupt is generated
because the counter is stopped. Do not stop main clock oscillation if it is necessary to use the main clock
oscillation stabilization interrupt for processing.
If a WIF flag setting request occurs at the same time as a zero-clearance request from the CPU, the WIF
flag setting request has priority and the zero-clearance request is ignored.
123
CHAPTER 3 CPU and CONTROL UNIT
124
CHAPTER 4
RESET
This chapter describes reset.
4.1 Overview of Reset
4.2 Reset Factors and Oscillation Stabilization Wait Times
4.3 Reset Levels
4.4 External Reset Pin
4.5 Reset Operation
4.6 Reset Factor Bit
4.7 State of Each Pin at Reset
125
CHAPTER 4 RESET
4.1
Overview of Reset
When a reset occurs, the CPU immediately suspends the currently executing
processing and becomes the reset cancellation wait state. After the reset is canceled,
the processing is started from an address indicated by the reset vector.
Five factors of a reset are as follows.
• Reset request from external reset pin (INIT)
• Software reset request
• Watchdog timer overflow
• Hardware watchdog timer overflow
• Oscillation operating trouble
■ Reset Factor
Table 4.1-1 shows reset factor.
Table 4.1-1 Reset Factor
Oscillation stabilization wait
Reset
Factor
External reset
"L" input to INIT pin
Software reset
Writing "0" to SRST bit of standby
control register (STCR)
Watchdog timer
Watchdog timer overflow
Internal
generated
timing
Reset
level
Synchronous
(Asynchronous)
Main
oscillation
stop
STOP
state
Other than
described
in left
INIT
Yes
Yes
Yes
Synchronous
INIT
Yes
-
None
Synchronous
INIT
Yes
-
None
Hardware watchdog Hardware watchdog timer overflow
Synchronous
INIT
Yes
-
Yes
Clock supervisor
Synchronous
INIT
Yes
-
Yes
Oscillation operating trouble
When the reset factor is generated excluding clock supervisor reset, the machine clock of the main
oscillation clock is two dividing frequency clocks. Clock supervisor reset is generated by built-in RC
oscillation.
● External reset
The external reset generates a reset by inputting "L" level to the external reset (INIT) pin. Further, at power
on, set the input level of the INIT pin to "L" and perform setting initialization reset (INIT). Also, to assure
the oscillation stabilization wait time of the oscillation circuit and the stabilization wait time of step-down
circuit immediately after power on, hold "L" level input to the INIT pin for the time required for stabilization
wait time of the oscillation circuit.
126
CHAPTER 4 RESET
● Software reset
The software reset is an internal reset generated by writing "0" to the SRST bit of the standby control
register (STCR).
● Watchdog reset
The watchdog reset is a reset generated by the overflow of the watchdog timer when A5H or 5AH is not
written to the watchdog reset generation postpone register (WPR) continuously within the specified time
after starting of the watchdog timer.
● Hardware watchdog reset
The hardware watchdog reset generates a reset by the overflow of the hardware watchdog timer when "0" is
not written to the CL bit of the hardware watchdog timer control register (HWDCS) within the specified
time after power on.
● Clock supervisor reset
Clock supervisor reset observes the output trouble of the main oscillation and the sub oscillation. When the
trouble occurs, the clock supervisor reset generates reset.
Note:
At power on, if the reset factor occurs during a write operation (during transfer instruction execution),
the reset factor other than the generation of voltage drop is the reset cancellation wait state after the
instruction ends. Thus, the write process terminates normally even if a reset signal is input during
write operation.
However, because the multi load (LDM) or multi store (STM) instruction accepts the reset before the
transfer of the specified register is completed, it is not guaranteed that all data are transferred.
127
CHAPTER 4 RESET
4.2
Reset Factors and Oscillation Stabilization Wait Times
There are 5 types of reset factor, and the oscillation stabilization wait time at a reset
depends on the reset factor.
■ Reset Factors and Oscillation Stabilization Wait Times
Table 4.2-1 shows reset factor and oscillation stabilization wait times.
Table 4.2-1 Reset Factors and Oscillation Stabilization Wait Times
Oscillation stabilization wait time
Reset
Factor
Main oscillation stop
STOP
state
Other than
described in left
The time that
OS bit is "0"
Yes
External pin
"L" input to INIT pin
The time that OS bit is "0"
Software reset
Writing "0" to SRST bit of standby
control register (STCR)
Setting value of OS bit
-
None
Watchdog timer
Watchdog timer overflow
Setting value of OS bit
-
None
Hardware watchdog
Overflow of hardware watchdog
timer
The time that OS bit is "0"
-
Yes
Clock supervisor
Oscillation operating trouble
The time that OS bit is "0"
-
Yes
The oscillation stabilization wait time is acquired by setting of the OS bit in the standby control register
(STCR).
Table 4.2-2 shows setting of OS1 and OS0 and oscillation stabilization wait time.
Table 4.2-2 Oscillation Stabilization Wait Time by Setting of Standby Control Register (STCR)
Oscillation stabilization wait time
The corresponding time interval for an oscillation clock frequency of 4MHz is given in parentheses
OS1
OS0
0
0
φ×212 (approx. 1.97ms) (at power-on)
0
1
φ×212 (approx. 1.97ms)
1
0
φ×213 (approx. 4.1ms)
1
1
φ×214 (approx. 5.2ms)
φ: Cycle of system base clock
Note:
Ceramic and crystal oscillators generally require an oscillation stabilization wait time of several
milliseconds to some tens of milliseconds until stabilization at a natural frequency is attained after
the oscillation is started. For this reason, set the wait time value meeting the oscillator used.
128
CHAPTER 4 RESET
■ Oscillation Stabilization Wait Time at Power-on
Input level of INIT pin is set to "L" at power-on. "L" level input period after power on should be required at
least stabilization time (8ms) of step-down circuit.
Figure 4.2-1 External Reset and Internal Operation
Vcc
CLK
INIT
CPU operation
Stabilization wait time
of step-down circuit
Oscillation
stabilization wait time
When the "L" level input period of INIT is less than 8ms, the stabilization wait time of the step-down
circuit is acquired by the internal circuit.
After the stabilization wait time of the step-down circuit is passed or after "L" level input of the INIT pin is
released, the oscillation stabilization wait time is acquired.
■ Return by INIT Pin
Table 4.2-3 shows the oscillation stabilization wait time when the "L" level input to the INIT pin is
performed in the stop mode or sub-run mode.
Oscillation stabilization wait time is different depending on operation state of main oscillation.
Table 4.2-3 Reset Factors and Oscillation Stabilization Wait Times by INIT Pin
Factor
"L" input to
INIT pin
State
Oscillation stabilization wait time
The corresponding time interval for an oscillation clock
frequency of 4MHz is given in parentheses.
Main oscillation
enable
The time that OS bit is "00" + 27/HCLK
(approx. 32µs)
Main oscillation
disable
The time that OS bit is "00" + approx. 12µs
HCLK: oscillation clock frequency
129
CHAPTER 4 RESET
4.3
Reset Levels
The reset operations of the FR60Lite device are classified into two levels, each of which
has different causes and initialization operations. This section describes these reset
levels.
■ Setting Initialization Reset (INIT)
This is the highest-level reset that initializes all settings.
External pin input, watchdog reset, software reset, hardware watchdog reset and clock supervisor reset have
reset level of setting initialization reset (INIT). When setting initialization reset (INIT) occurs, operation
initialization reset (RST) occurs simultaneously.
A setting initialization reset (INIT) mainly performs the following initialization:
• Operation mode of device (setting of bus mode and external bus width)
• Setting concerning clock generation/control
- Clock source selection (CLKS: divided by 2 of main clock)
- Clock division setting (peripheral: × 4, CPU: × 1, external bus: × 1)
- Watchdog timer cycle (WT1, WT0: 216/base clock cycle) *1
- Oscillation stabilization wait time (OS1, OS0:215/HCLK) *2
- Oscillation control at stop (OSCD1 : stop the main clock oscillation in the stop)
- Time-base timer interrupt (TBIE: disable)
- Main PLL multiplier rate (PLL1S2 to PLL1S0: × 1)
- PLL operating enable (PLL1EN: PLL stop)
• All CS0 area settings of external buses
- Selecting area register (ASR0: starting address "0")
- Area size (ASZ1, ASZ0: 512KB)
- Data bus width (reflected the value of mode data)
- Access type (TYP3 to TYP0: normal access, using WR0 and WR1 pins as write strobe, disabled
WAIT insertion by RDY pin)
• All settings initialized in operation initialization reset (RST)
*1: The watchdog timer stops due to the setting initialization reset (INIT) and does not operate until it is
activated by the program operation again.
*2: It is initialized by the external INIT pin at power on.
130
CHAPTER 4 RESET
■ Operation Initialization Reset (RST)
A normal-level reset that initializes the operation of a program is called an operation initialization reset
(RST).
If a setting initialization reset (INIT) occurs, an operation initialization reset (RST) also occurs.
An operation initialization reset (RST) mainly initializes the following items:
• Program operation
• CPU and internal bus
• Setting concerning clock generation/control
- Watchdog timer cycle (WT1, WT0: 216/base clock cycle)
- Time-base timer interrupt (TBIE: disabled)
• Register setting value of peripheral circuits
• I/O port settings
• Operation mode of device (setting of bus mode and external bus width)
131
CHAPTER 4 RESET
4.4
External Reset Pin
The external reset pin (INIT pin), dedicated to reset input, generates an internal reset in
response to input of the "L" level signal. The external reset pin is reset in
synchronization with the machine clock, but the external pin is reset in asynchronous
with the machine clock.
■ Block Diagram of External Reset Pin
Figure 4.4-1 Block Diagram of Internal Reset
Machine clock
(PLL multiplication circuit, 2-division of HCLK)
INIT
pin
P-ch
P-ch
Synchronization
circuit
N-ch
Clock synchronous
internal reset signal
Input buffer
Note:
To prevent memory from being destroyed by a reset during a write operation, the initialization
operation of the internal circuit due to the INIT pin input is performed in a cycle that a memory is not
destroyed.
Also, the clock is required to initialize the internal circuits. To operate with the external clock, supply
the clock input at the reset input.
■ Reset Timing of External Pin
Each external pin is reset asynchronously for the INIT pin input of the external reset.
132
CHAPTER 4 RESET
4.5
Reset Operation
When the reset is released, the reset vector and mode data is fetched from the
predetermined locations depending on the setting of the mode pins. This operation, the
mode fetch, then defines the operation mode of the CPU and the execution start
address after a reset. For the power on, when returning by a reset from the stop mode,
the mode fetch is performed after the oscillation stabilization wait time is elapsed.
■ Overview of Reset Operation
Figure 4.5-1 shows reset operation flow.
Figure 4.5-1 Reset Operation Flow
External reset at power-on
External reset
Software reset
Watchdog timer reset
Hardware watchdog reset
Clock supervisor reset
During a reset
Stop
Main oscillation
Oscillation stabilization wait and reset state Operation
Fetching the mode data
Mode fetch
(Reset operation)
Normal operation
(Run state)
Fetching the reset vector
CPU executes an instruction, fetching instruction
codes from the address indicated by the reset vector.
■ Mode Pin
Mode pins (MD0 to MD2) specify the method of fetching reset vector and mode data. Fetching reset vector
and mode data is performed in reset sequence.
■ Mode Fetch
When the reset is cleared, the CPU fetches the reset vector and the mode data to the appropriate registers in
the CPU core. The reset vector and mode data are allocated from FFFFCH to FFFF8H, respectively. The
CPU outputs these addresses to the internal bus immediately after the reset is cleared and then fetches the
reset vector and mode data. The CPU starts the mode fetch process at the address pointed to by the reset
vector.
133
CHAPTER 4 RESET
4.6
Reset Factor Bit
Reset generating factor can be recognized when reset factor register/watchdog timer
control register (RSRR) is read.
■ Reset
As shown in Figure 4.6-1, a flip-frop is associated with each reset factor. The contents of the flip-flops are
obtained by reading the reset factor register/watchdog timer control register (RSRR). If the factor of a reset
must be identified after the reset has been cleared, the value read from the RSRR should be processed by
the software and a branch made to the appropriate program.
Figure 4.6-1 Block Diagram of Reset Factor Bits
Without periodically
clear
Hardware
watchdog
Oscillation output
abnormal
Clock
supervisor
INIT pin
Without periodically
clear
External reset
request detection
circuit
Watchdog timer
control register
(RSRR)
system base
clock
D CL
F/F
Q CK
D CL
F/F
Q CK
Watchdog timer
reset generated
detection circuit
SRST bit set
SRST bit
write detection
circuit
D CL
F/F
Q CK
Q CL
F/F
D CK
Internal
reset
Watchdog timer
control register
(RSRR) read
Internal data bus
134
CHAPTER 4 RESET
■ Correspondence of Reset Factor Bit and Reset Factor
Figure 4.6-2 shows the configuration of the reset factor bits of reset factor register/watchdog timer control
register (RSRR). Table 4.6-1 maps the correspondence between the reset factor bits and reset factors. See
"3.9 Clock Generation Control" for details.
Figure 4.6-2 Configuration of Reset Factor Bit (RSRR)
RSRR
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000480H
R
R
WDOG
R
ERST
R
SRST
R
R
WT1
R/W
WT0
R/W
00010000B
R/W: Readable/Writable
R:
Read only
Table 4.6-1 Correspondence of Reset Factor Bit and Reset Factor
Reset factor
ERST
WDOG
SRST
Generation of reset request by watchdog timer overflow
*1
1
*1
External reset request from INIT pin,
generation of clock supervisor reset request *2
generation of hardware watchdog reset request *3
1
*1
*1
Generation of software reset request
*1
*1
1
*1: The previous state is held.
*2: When the clock supervisor reset request is generated, the MM bit or the MS bit of the clock supervisor
control register (CSVCR) is set to "1".
*3: When the hardware watchdog reset request is generated, the CPUF bit of the hardware watchdog timer
control register (HWDCS) is set to "1".
■ Notes on Reset Factor Bit
● At generating two or more reset factors
When multiple reset factors are generated at the same time, the corresponding reset factor bits of the RSRR
are also set to "1". If, for example, an external reset request via the INIT pin and the watchdog timer
overflow occur at the same time, the ERST and the WDOG bits are both set to "1".
● Clearing of reset factor bit
The reset factor bit is cleared only when RSRR is read. The flag that generated to the bit corresponding to
each reset factor is not cleared even though other reset is generated (a setting of "1" is retained).
135
CHAPTER 4 RESET
4.7
State of Each Pin at Reset
This section explains the state of each pin at reset.
■ Pin Status During Reset
The pin status during reset is determined by setting of mode pins (MD2 to MD0 = 00xB).
● When internal vector mode is setting (M2, M1, M0 = 000B)
All I/O pins (peripheral function pins) are set to high impedance, and mode data is read from internal
ROM.
● When external vector mode is setting (M2, M1, M0 = 001B)
All I/O pins (peripheral function pins) are set to high impedance, and mode data is read from external
ROM.
Note:
MB91F273(S) and MB91F278(S) supports for internal vector mode only.
■ State of Pins After Mode Data Read
The pin state succeeding read of the mode data is determined by the mode data.
● When single-chip mode is selected
All I/O pins (peripheral function pins) are set to high impedance, and reset vector is read from internal
ROM.
● When selecting external bus mode
All I/O pins (peripheral function pins) except external bus shared pin are set to high impedance, and reset
vector is read from external ROM.
Note:
Ensure that any external devices connected to pins that go to high impedance when a reset is
present do not misoperate in this case.
136
CHAPTER 5
EXTERNAL BUS INTERFACE
The external bus interface controller controls the
interfaces with the internal bus for chips and with
external memory and I/O devices.
This chapter explains each function of the external bus
interface and its operation.
5.1 Features of External Bus Interface
5.2 External Bus Interface Registers
5.3 Chip Select Area
5.4 Endian and Bus Access
5.5 Ordinary Bus Interface
5.6 Address/Data Multiplex Interface
5.7 DMA Access
5.8 Procedure for Setting Registers
137
CHAPTER 5 EXTERNAL BUS INTERFACE
5.1
Features of External Bus Interface
This section explains the features of the external bus interface.
■ Features of External Bus Interface
• Addresses of up to 24 bits can be outputted.
• Various kinds of external memory (8-bit/16-bit modules) can be directly connected and multiple access
timings can be mixed and controlled.
- Asynchronous SRAM and asynchronous ROM/FLASH memory
(multiple write strobe method or byte enable method)
- Address/data multiplex bus (8-bit/16-bit width only)
• Four independent banks (chip select areas) can be set, and chip select corresponding to each bank can be
outputted.
- CS0 and CS1are in units of 64K/128K/256K/512KB and can set to the space assigned to the external
bus areas up to 003FFFFFH.
- CS2 and CS3 are in units of 1M/2M/4M/8MB and can set to the space between
00400000H and
00FFFFFFH.
- Boundaries may be limited depending on the size of the area.
• In each chip select area, the following functions can be set independently:
- Enabling and disabling of the chip select area (Disabled areas cannot be accessed)
- Setting of the access timing type to support various kinds of memory
- Detailed access timing setting
(individual setting of the access type such as the wait cycle)
- Setting of the data bus width (8-bit/16-bit)
• A different detailed timing can be set for each access timing type.
- For the same type of access timing, a different setting can be made in each chip select area.
- Auto-wait can be set to up to 7 cycles (asynchronous SRAM, ROM, FLASH, and I/O area).
- The bus cycle can be extended by external RDY input (asynchronous SRAM, ROM, FLASH, and I/O
area).
- Various kinds of idle/recovery cycles and setting delays can be inserted.
• Pins that are not used by the external interface can be used as general-purpose I/O ports through
settings.
138
CHAPTER 5 EXTERNAL BUS INTERFACE
■ Block Diagram of External Bus Interface
Figure 5.1-1 shows block diagram of external bus interface.
Figure 5.1-1 Block Diagram of External Bus Interface
Internal
Address Bus
32
Internal
Data Bus
32
External
Data Bus
MUX
Write Buffer
Switch
Read Buffer
Switch
Data Block
Address Block
+1 or +2
External
Address Bus
Address Buffer
ASR
CS0 to CS3
ASZ
comparator
External Pin Contorol Division
RD
WR0, WR1
All Block Control
Register & Control
AS
RDY
139
CHAPTER 5 EXTERNAL BUS INTERFACE
■ I/O Pins
I/O pins are external bus interface pins.
[Ordinary bus interface]
A23 to A16, AD15 to AD00
CS0, CS1, CS2, CS3,
AS, SYSCLK,
RD,
WR0, WR1,
RDY
■ Register List of External Bus Interface
Register configuration of external bus interface is as follows.
Address
bit31
bit24 bit23
bit16 bit15
00000640H
ASR0
ACR0
00000644H
ASR1
ACR1
00000648H
ASR2
ACR2
0000064CH
ASR3
ACR3
00000660H
AWR0
AWR1
00000664H
AWR2
AWR3
bit0
00000668H
CSER
Reserved
Reserved
Reserved
000007FCH
Reserved
MODR
Reserved
Reserved
Reserved: Reserved register. Be sure to set "0" at rewrite.
MODR cannot be accessed from user programs.
140
bit8 bit7
CHAPTER 5 EXTERNAL BUS INTERFACE
5.2
External Bus Interface Registers
This section explains the registers used in the external bus interface.
■ Register Types of External Bus Interface
The following four types of registers are used by the external bus interface:
• ASR0 to ASR3 (Area Select Register)
• ACR0 to ACR3 (Area Configuration Register)
• AWR0 to AWR3 (Area Wait Register)
• CSER (Chip Select Enable Register)
141
CHAPTER 5 EXTERNAL BUS INTERFACE
5.2.1
ASR0 to ASR3 (Area Select Register)
This section shows the details of area select register.
■ Register Configuration of ASR0 to ASR3 (Area Select Register)
Configuration of ASR0 to ASR3 is as follows.
ASR0
Address
bit15
---
bit8
bit7
bit6
---
bit1
bit0
Initial value
000640H
R/W
-----
R/W
A23
R/W
A22
R/W
-----
A17
R/W
A16
R/W
0000H
Address
bit15
---
bit8
bit7
bit6
---
bit1
bit0
Initial value
000644H
R/W
-----
R/W
A23
R/W
A22
R/W
-----
A17
R/W
A16
R/W
00XXH
Address
bit15
---
bit8
bit7
bit6
...
bit1
bit0
Initial value
000648H
R/W
-----
R/W
A23
R/W
A22
R/W
...
---
A17
R/W
A16
R/W
XXXXH
Address
bit15
---
bit8
bit7
bit6
---
bit1
bit0
Initial value
00064CH
R/W
-----
R/W
A23
R/W
A22
R/W
-----
A17
R/W
A16
R/W
00XXH
ASR1
ASR2
ASR3
R/W: Readable/Writable
X:
Undefined
[bit15 to bit8] Reserved: Reserved bits
Be sure to set these bits to "00H".
[bit7 to bit0] A23 to A16: Area start address
ASR0 to ASR3 (Area Select Register 0 to 3) specify the start address of each chip select area in CS0 to
CS3.
The start address can be set in the high-order 8 bits (bits A23 to A16). Each chip select area starts with
the address set in this register and covers the range set by the bits ASZ1, ASZ0 of the ACR0 to ACR3
registers.
The boundary of each chip select area obeys the setting of the bits ASZ1, ASZ0 of the ACR0 to ACR3
registers. For example, if an area of 1M bytes is set by the bits ASZ1, ASZ0, the low-order four bits of
the ASR0 to ASR3 registers are ignored and only bits A23 to A20 are valid.
The ASR0 register is initialized to "00H" by reset. ASR1 to ASR3 are not initialized by reset and are
therefore undefined. After starting chip operation, be sure to set the corresponding ASR register before
enabling each chip select area with the CSER register.
142
CHAPTER 5 EXTERNAL BUS INTERFACE
5.2.2
ACR0 to ACR3 (Area Configuration Register)
This section explains the details of area configuration register.
■ Register Configuration of ACR0 to ACR3 (Area Configuration Register)
Configuration of ACR0 to ACR3 is as follows.
ACR0H
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000642H
R/W
R/W
ASZ1
R/W
ASZ0
R/W
R/W
DBW0
R/W
R/W
R/W
00110*00B
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000643H
R/W
R/W
WREN
R/W
0
R/W
TYPE3
R/W
TYPE2
R/W
TYPE3
R/W
TYPE0
R/W
00000000B
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000646H
R/W
R/W
ASZ1
R/W
ASZ0
R/W
R/W
DBW0
R/W
R/W
R/W
XXXX0X00B
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000647H
R/W
R/W
WREN
R/W
R/W
TYPE3
R/W
TYPE2
R/W
TYPE3
R/W
TYPE0
R/W
00X0XXXXB
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00064AH
R/W
R/W
ASZ1
R/W
ASZ0
R/W
R/W
DBW0
R/W
R/W
R/W
XXXX0X00B
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00064BH
R/W
R/W
WREN
R/W
R/W
TYPE3
R/W
TYPE2
R/W
TYPE3
R/W
TYPE0
R/W
00X0XXXXB
ACR0L
ACR1H
ACR1L
ACR2H
ACR2L
R/W: Readable/Writable
X:
Undefined
*:
Automatic setting in the same value as the WTH bit of the mode vector
143
CHAPTER 5 EXTERNAL BUS INTERFACE
ACR3H
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00064EH
R/W
R/W
ASZ1
R/W
ASZ0
R/W
R/W
DBW0
R/W
R/W
R/W
01XX0X00B
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00064FH
R/W
R/W
WREN
R/W
R/W
TYPE3
R/W
TYPE2
R/W
TYPE3
R/W
TYPE0
R/W
00X0XXXXB
ACR3L
R/W: Readable/Writable
X:
Undefined
ACR0 to ACR3 (Area Configuration Register 0 to 3) set the functions of each chip select area.
Note:
Set ASR and ACR simultaneously in word access. When accessing ASR and ACR in half word, set
ACR after setting ASR.
[bit15, bit14] Reserved; Reserved bits
Be sure to set these bits to "00B".
144
CHAPTER 5 EXTERNAL BUS INTERFACE
[bit13, bit12] ASZ1, ASZ0 = Area Size bit1 to bit0
Table 5.2-1 shows the size of each chip select area.
Table 5.2-1 Size of Each Chip Select Area of Area Size Bit
Register ASZ1 ASZ0
ASR0/
ASR1
ASR2/
ASR3
Size of each chip select area
0
0
0
1
64K bytes (00010000H byte, ASR A23 to A16 bits are valid)
128K bytes (00020000H byte, ASR A23 to A17 bits are valid)
1
0
256K bytes (00040000H byte, ASR A23 to A18 bits are valid)
1
1
512K bytes (00080000H byte, ASR A23 to A19 bits are valid)
0
0
0
1
1M bytes (00100000H byte, ASR A23 to A20 bits are valid)
2M bytes (00200000H byte, ASR A23 to A21 bits are valid)
1
0
1
1
4M bytes (00400000H byte, ASR A23 to A22 bits are valid)
8M bytes (00800000H byte, ASR A23 bits are valid)
Setting
Only CS0
and CS1
are valid.
Only CS2
and CS3
are valid.
ASZ1, ASZ0 are used to set the size of each area by modifying the number of bits for address
comparison to a value different from ASR. Thus, an ASR contains bits that are not compared.
Bits ASZ1, ASZ0 of ACR0 are initialized to 11B by reset. Despite this setting, however, the CS0 area
just after reset is executed is specially set from 00000000H to 00FFFFFFH (setting of entire area). The
entire-area setting is reset after the first write to ACR0 and an appropriate size is set as indicated in Table
5.2-1.
[bit11] Reserved: Reserved bit
Be sure to set this bit to "0".
[bit10] DBW0 = Data Bus Width[0]
Data bus width of each chip select area is set as follows.
DBW0
Data bus width
0
8 bits (byte access)
1
16 bits (halfword access)
Note:
The same values as those of the WTH bits of the mode vector are written automatically to bits DBW0
of ACR0 during the reset sequence.
[bit9, bit8] Reserved: Reserved bits
Be sure to set these bits to "00B".
[bit7, bit6] Reserved: Reserved bits
Be sure to set these bits to "00B".
145
CHAPTER 5 EXTERNAL BUS INTERFACE
[bit5] WREN = WRite ENable
This bit sets enabling and disabling of writing to each chip select area.
WREN
Write enable/disable
0
Disable write
1
Enable write
If an area for which write operations are disabled is accessed for a write operation from the internal bus,
the access is ignored and no external access at all is performed.
Set the WREN bit of areas for which write operations are required, such as data areas, to "1".
[bit4] Reserved: Reserved bit
Be sure to set this bit to "0".
[bit3 to bit0] TYP[3:0]= TYPe select
Access type of each chip select area is set as follows.
TYP3
TYP2
TYP1
TYP0
Access type
0
x
x
Normal access (asynchronous SRAM, I/O, ROM/FLASH)
1
x
x
Address data multiplex access (8/16-bit bus width only)
x
0
Disable WAIT insertion by the RDY pin.
x
1
Enable WAIT insertion by the RDY pin
0
x
Use the WR0 and WR1 pins as write strobes.
1
x
Setting disabled
0
Setting disabled
1
Setting disabled
0
x
0
1
0
0
1
0
Setting disabled
0
1
1
Setting disabled
1
0
0
Setting disabled
1
0
1
Setting disabled
1
1
0
Setting disabled
1
1
1
Mask area setting (The access type is the same as that of the
overlapping area) *
Set the access type as the combination of all bits.
*: CS area mask setting function
If you want to set an area some of whose operation settings are changed for a certain CS area (referred to
as the base setting area), you can set TYP3 to TYP0 of ACR in another CS area to "1111B" so that the
area can function as a mask setting area.
If you do not use the mask setting function, disable any overlapping area settings for multiple CS areas.
146
CHAPTER 5 EXTERNAL BUS INTERFACE
Access operations to the mask setting area are as follows:
- CS corresponding to a mask setting area is not asserted.
- CS corresponding to a base setting area is asserted.
- For the following ACR settings, the settings on the mask setting area side are valid:
Bit10 DBW0: Bus width setting
Bit5 WREN: Write-enable setting (Note: For this setting only, a setting that is different from that of
the base setting area is not allowed.)
- For the following ACR setting, the setting on the base setting area side is valid:
Bit3 to bit0 (TYP3 to TYP0): Access type setting
- For the AWR settings, the settings on the mask setting area side are valid.
A mask setting area can be set for only part of another CS area (base setting area). You cannot set a mask
setting area for an area without a base setting area. Do not overlap multiple mask setting areas. Use care
when setting ASR and bits ASZ1, ASZ0 of ACR.
Note:
The following restrictions apply for bit3 to bit0 (TYP3 to TYP0):
• A write-enable setting cannot be implemented by a mask.
• Write-enable settings in the base CS area and the mask setting area must be identical.
• If write operations to a mask setting area are disabled, the area is not masked and operates as a
base CS area.
• If write operations to the base CS area are disabled but are enabled to the mask setting area, the
area has no base, resulting in malfunctions.
147
CHAPTER 5 EXTERNAL BUS INTERFACE
5.2.3
AWR0 to AWR3 (Area Wait Register)
This section explains the details of area wait register.
■ Register Configuration of AWR0 to AWR3 (Area Wait Register)
Configuration of AWR0 to AWR3 registers is as follows.
AWR0H
Address
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Initial value
000660H
-
W14
W13
W12
-
-
-
-
01110000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
Initial value
000661H
-
W06
-
W04
-
W02
W01
W00
01011011B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
XXXX0000B
AWR0L
AWR1H
Address
-
W14
W13
W12
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000663H
-
W06
-
W04
-
W02
W01
W00
XX0X1XXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Initial value
000664H
-
W14
W13
W12
-
-
-
-
0XXX0000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
Initial value
000665H
-
W06
-
W04
-
W02
W01
W00
XX0X1XXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
000662H
AWR1L
AWR2H
AWR2L
R/W: Readable/Writable
X:
Undefined
(Continued)
148
CHAPTER 5 EXTERNAL BUS INTERFACE
(Continued)
AWR3H
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000666H
-
W14
W13
W12
-
-
-
-
0XXX0000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000667H
-
W06
-
W04
-
W02
W01
W00
0X0X1XXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
AWR3L
R/W: Readable/Writable
X:
Undefined
AWR0 to AWR3 specify various kinds of wait cycles for each chip select area.
The function of each bit changes according to the access type (TYP3 to TYP0 bits) setting of the ACR0 to
ACR3 registers.
149
CHAPTER 5 EXTERNAL BUS INTERFACE
■ Normal Access or a Address/Data Multiplex Access Operation
A chip select area determined by either of the following settings for the access type (TYP3 to TYP0 bit) of
ACR0 to ACR3 registers becomes the area for normal access or a address/data multiplex access operation.
TYP3
TYP2
TYP1
TYP0
Access type
0
0
x
x
Normal access (asynchronous SRAM, I/O, ROM/FLASH)
0
1
x
x
Address data multiplex access (8/16-bit bus width only)
The following lists the functions of each AWR0 to AWR3 bit for a normal access or address/data multiplex
access area. Since the initial values of registers other than AWR0 are undefined, set them to their initial
values before enabling each area with the CSER register.
[bit15] Reserved: Reserved bit
Be sure to set this bit to "0".
[bit14 to bit12] W14 to W12 = First access wait cycle
These bits set the number of auto-wait cycles to be inserted into the first access cycle of each cycle.
Except for the burst access cycles, only this wait setting is used.
The initial value of the CS0 area is set to 7 (wait). The initial values of other areas are undefined.
W14
W13
W12
First access wait cycle
0
0
0
Auto-wait cycle 0
0
0
1
Auto-wait cycle 1
...
1
1
...
1
Auto-wait cycle 7
[bit11 to bit8] Reserved: Reserved bits
Be sure to set these bits to "0000B".
[bit7] Reserved: Reserved bit
Be sure to set this bit to "0".
150
CHAPTER 5 EXTERNAL BUS INTERFACE
[bit6] W06 = Read → Write idle cycle
The read → write idle cycle is set to prevent collision of read data and write data on the data bus when a
write cycle follows a read cycle. During an idle cycle, all chip select signals are negated and the data
terminals maintain the high impedance state.
If a write cycle follows a read cycle or an access operation to another chip select area occurs after a read
cycle, the specified idle cycle is inserted.
Read →write idle cycles
W06
0
0 cycle
1
1 cycle
[bit5] Reserved: Reserved bit
Be sure to set this bit to "0".
[bit4] W04 = Write recovery cycle
The write recovery cycle is set if a device that limits the access period after write access is to be
controlled. During a write recovery cycle, all chip select signals are negated and the data pins maintain
the high impedance state.
If the write recovery cycle is set to "1" or more, a write recovery cycle is always inserted after write
access.
W04
Write recovery cycles
0
0 cycle
1
1 cycle
[bit3] Reserved: Reserved bit
Be sure to set this bit to "1".
[bit2] W02 = Address → CS Delay
The address → CS delay setting is made when a certain type of setup is required for the address when
CS falls or CS edges are needed for successive accesses to the same chip select area.
Set the address and set the delay from AS output to CS0 to CS3 output.
Address → CS delay
W02
0
No delay
1
Delay
If no delay is selected by setting "0", assertion of CS0 to CS3 starts at the same timing that AS is
asserted. If, at this point, successive accesses are made to the same chip select area, assertion of CS0 to
CS3 without change between two access operations may continue.
If delay is specified by selecting "1", assertion of CS0 to CS3 starts when the external memory clock
SYSCLK output rises. If, at this point, successive accesses are made to the same chip select area, CS0 to
CS3 are negated at a timing between two access operations.
If CS delay is selected, one setup cycle is inserted before asserting the read/write strobe after assertion of
the delayed CS (operation is the same as the CS →RD/WR setup setting of W01).
151
CHAPTER 5 EXTERNAL BUS INTERFACE
[bit1] W01=CS → RD/WR setup extension cycle
The CS → RD/WR setup extension cycle is set to extend the period before the read/write strobe is
asserted after CS is asserted. At least one setup extension cycle is inserted before the read/write strobe is
asserted after CS is asserted.
CS → RD/WR setup delay cycle
W01
0
0 cycle
1
1 cycle
If 0 cycle is selected by setting "0", RD/WR0 and WR1 are outputted at the earliest when external
memory clock SYSCLK output rises just after CS is asserted. WR0, WR1 may be delayed one cycle or
more depending on the internal bus state.
If 1 cycle is selected by setting "1", RD/WR0, WR1 are always outputted 1 cycle or more later.
When successive accesses are made within the same chip select area without negating CS, a setup
extension cycle is not inserted. If a setup extension cycle for determining the address is required, set the
W02 bit and insert the address → CS delay. Since CS is negated for each access operation, the setup
extension cycle is enabled.
If the CS delay set by W02 is inserted, this setup cycle is always enabled regardless of the setting of the
W01 bit.
[bit0] W00=RD/WR → CS hold extension cycle
The RD/WR → CS hold extension cycle is set to extend the period before negating CS after the read/
write strobe is negated. One hold extension cycle is inserted before CS is negated after the read/write
strobe is negated.
RD/WR → CS hold extension cycle
W00
0
0 cycle
1
1 cycle
If 0 cycle is selected by setting "0", CS0 to CS3 are negated after the hold delay from the rising edge of
external memory clock SYSCLK output after RD/WR0, WR1 are negated.
If 1 cycle is selected by setting "1", CS0 to CS3 are negated one cycle later.
When making successive accesses within the same chip select area without negating CS, the hold
extension cycle is not inserted. If a hold extension cycle for determining the address is required, set the
W02 bit and insert the address → CS delay. Since CS is negated for each access operation, this hold
extension cycle is enabled.
152
CHAPTER 5 EXTERNAL BUS INTERFACE
5.2.4
CSER (Chip Select Enable Register)
This section explains the details of chip select enable register.
■ Register Configuration of CSER (Chip Select Enable Register)
Configuration of CSER registers is as follows.
CSER
Address
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
Initial value
00 0680H
R/W
R/W
R/W
R/W
CSE3
R/W
CSE2
R/W
CSE1
R/W
CSE0
R/W
0000001B
R/W: Readable/Writable
The chip select enable register enables and disables each chip select area.
[bit31 to bit28] Reserved: Reserved bits
Be sure to set these bits to "0000B".
[bit27 to bit24] CSE3 to CSE0 = Chip select area enable (chip select enable 0 to 3)
These bits are the chip select area enable bits for CS0 to CS3.
The initial value is "0001B", which enables only the CS0 area.
When "1" is written, a chip select area operates according to the settings of ASR0 to ASR3, ACR0 to
ACR3, and AWR0 to AWR3.
Before setting this register, be sure to make all settings required for the corresponding chip select areas.
CSE[3:0]
Area control
0
Interdiction
1
Permission
Table 5.2-2 shows CSE bits and corresponding CS.
Table 5.2-2 CSE Bit and Corresponding CS
CSE bit
Corresponding CS
bit24:CSE0
CS0
bit25:CSE1
CS1
bit26:CSE2
CS2
bit27:CSE3
CS3
153
CHAPTER 5 EXTERNAL BUS INTERFACE
5.3
Chip Select Area
In the external bus interface, a total of four chip select areas can be set.
The address space of each area can be set in 16MB space using ASR0 to ASR3 (Area
Select Register) and ACR0 to ACR3 (Area Configuration Register). CS0 and CS1 can be
set in the space assigned to external bus areas between 00000000H and 003FFFFFH in
units of 64K/128K/256K/512KB. CS2 and CS3 can be set in the space between
00400000H to 00FFFFFFH in units of 1M/2M/4M/8MB.
When bus access is made to an area specified by these registers, the corresponding
chip select signals (CS0 to CS3) are activated ("L" output) during the access cycle.
■ Example of Setting ASR and ASZ1, ASZ0
1. ASR1=0001H ACR1 → ASZ1, ASZ0=00B
Chip select area 1 is assigned to 00100000H to 0010FFFFH.
2. ASR2=0040H ACR2 → ASZ1, ASZ0=00B
Chip select area 2 is assigned to 00400000H to 004FFFFFH.
3. ASR3=0081H ACR3 → ASZ1, ASZ0=11B
Chip select area 3 is assigned to 00800000H to 00FFFFFFH.
Since at this point 8 MB is set for bits ASZ1, ASZ0 of the ACR, the unit for boundaries is 8 MB and bit22
to bit16 of ASR3 are ignored. Before there is any writing to ACR0 after a reset, 00000000H to 00FFFFFFH
is assigned to chip select area 0.
Note:
Set the chip select areas so that there is no overlap.
154
CHAPTER 5 EXTERNAL BUS INTERFACE
Figure 5.3-1 shows chip select area.
Figure 5.3-1 Chip Select Area
00000000H
00000000H
00100000H
Area 1
00400000H
Area 2
00800000H
Area 3
64Kbyte
Area 0
1Mbyte
8Mbyte
00FFFFFFH
00FFFFFFH
155
CHAPTER 5 EXTERNAL BUS INTERFACE
5.4
Endian and Bus Access
This section explains endian and bus access.
■ Overview of Endian
FR60Lite family only supports for big endian as byte ordering.
156
CHAPTER 5 EXTERNAL BUS INTERFACE
5.4.1
Relationship between Data Bus Width and Control Signal
There is a one-to-one correspondence between the WR0/WR1 control signal and the
byte location on the data bus regardless of the data bus width.
The following summarizes the location of bytes on the data bus used according to the
specified data bus width and the corresponding control signal for each bus mode.
■ Control Signal of Ordinary Bus Interface
Figure 5.4-1 shows control signal of 16-bit bus width and 8-bit bus width in ordinary bus interface.
Figure 5.4-1 Control Signal of Ordinary Bus Interface
a)16-bit bus width
Data bus
Control
signal
b)8-bit bus width
Data bus
WR0
Control
signal
WR0
WR1
−
−
−
−
−
−
−
−
−
−
(D23 to 16 are not used)
■ Control Signal of Time Division I/O Interface
Figure 5.4-2 shows control signal of 16-bit bus width and 8-bit bus width in time division I/O interface.
Figure 5.4-2 Control Signal of Time Division I/O Interface
a)16-bit bus width
Data bus
D15
D0
Output
address
b)8-bit bus width
Control
signal
Data bus
Output
address
Control
signal
A15 to A8
WR0
A7 to A0
WR1
−
−
−
A7 to A0
WR0
−
−
−
−
−
−
−
−
−
−
−
−
157
CHAPTER 5 EXTERNAL BUS INTERFACE
5.4.2
Bus Access
FR60Lite family is big endian and performs external bus access.
■ Data Format
Figure 5.4-3 shows the relationship between the internal register and the external data bus by data format of
halfword access (when LDUH, STH instruction executed).
Figure 5.4-3 Halfword Access (When LDUH, STH Instruction Executed)
Internal
register
External
bus
D31
D23
D15
D15
AA
AA
BB
BB
D7
D7
D0
D0
Figure 5.4-4 shows the relationship between the internal register and the external data bus by data format of
byte access (when LDUB, STB instruction executed).
Figure 5.4-4 Byte Access (When LDUB, STB Instruction Executed)
a) Output address lower "0"
Internal
External
register
bus
D31
b) Output address lower "1"
Internal
External
register
bus
D31
D23
D23
D15
D15
D15
D7
D7
D15
AA
D7
AA
D0
158
D7
AA
D0
D0
AA
D0
CHAPTER 5 EXTERNAL BUS INTERFACE
■ Data Bus Width
Figure 5.4-5 shows data bus width of 16-bit bus width.
Figure 5.4-5 Data Bus Width of 16-bit Bus Width
Internal register
External bus
Output address lower
"00" "10"
D31
AA
D23
Read/Write
BB
D15
AA
CC
BB
DD
D15
D7
CC
D07
DD
Figure 5.4-6 shows data bus width of 8-bit bus width.
Figure 5.4-6 Data Bus Width of 8-bit Bus Width
Internal register
External bus
Output address lower
D31
D23
D15
D07
AA
Read/Write
"00"
"01"
"10"
"11"
AA
BB
CC
DD
D15
BB
CC
DD
■ External Bus Access
In the following, the external bus access is summarized to 16-bit/8-bit bus width, word/halfword/byte
access.
• Access byte location
• Program address and output address
• Bus access count
PA1/PA0
:
Lower 2 bits of address specified by program
Output A1/A0
:
Lower 2 bits of output address
:
The top byte location of output address
+
:
The data byte location to access
(1) to (4)
:
Bus access count
The FR family does not detect misalignment errors.
Therefore, for word access, the lower two bits of the output address are always "00B" regardless of whether
"00B", "01B", "10B", or "11B" is specified as the lower two bits by the program. For halfword access, the
lower two bits of the output address are "00B" if the lower two bits specified by the program are "00B" or
"01B", and are "10B" if "10B" or "11B".
159
CHAPTER 5 EXTERNAL BUS INTERFACE
● 16-bit bus width
Figure 5.4-7 shows each access of 16-bit bus width.
Figure 5.4-7 Each Access of 16-bit Bus Width
(A) Word Access
(a) PA1/PA0=00
(b) PA1/PA0=01
(c) PA1/PA0=10
(d) PA1/PA0=11
→(1)Output A1/A0=00
→(1)Output A1/A0=00
→(1)Output A1/A0=00
→(1)Output A1/A0=00
(2)Output A1/A0=10
(2)Output A1/A0=10
(2)Output A1/A0=10
(2)Output A1/A0=10
MSB
LSB
(1)
00
01
(1)
00
01
(1)
00
01
(1)
00
01
(2)
10
11
(2)
10
11
(2)
10
11
(2)
10
11
16-bit
(B) Halfword Access
(a) PA1/PA0=00
(b) PA1/PA0=01
(c) PA1/PA0=10
→(1)Output A1/A0=00
→(1)Output A1/A0=00
→(1)Output A1/A0=10
(d) PA1/PA0=11
→(1)Output A1/A0=10
00
01
00
01
00
01
00
01
10
11
10
11
10
11
10
11
(C) Byte Access
(a) PA1/PA0=00
→(1)Output A1/A0=00
(1)
160
00
01
10
11
(b) PA1/PA0=01
(c) PA1/PA0=10
→(1)Output A1/A0=01
→(1)Output A1/A0=10
(1)
00
01
10
11
(1)
00
01
10
11
(d) PA1/PA0=11
→(1)Output A1/A0=11
(1)
00
01
10
11
CHAPTER 5 EXTERNAL BUS INTERFACE
● 8-bit bus width
Figure 5.4-8 shows each access of 8-bit bus width.
Figure 5.4-8 Each Access of 8-bit Bus Width
(A) Word Access
(a) PA1/PA0=00
(b) PA1/PA0=01
(c) PA1/PA0=10
(d) PA1/PA0=11
→(1)Output A1/A0=00
→(1)Output A1/A0=00
→(1)Output A1/A0=00
→(1)Output A1/A0=00
(2)Output A1/A0=01
(2)Output A1/A0=01
(2)Output A1/A0=01
(2)Output A1/A0=01
(3)Output A1/A0=10
(3)Output A1/A0=10
(3)Output A1/A0=10
(3)Output A1/A0=10
(4)Output A1/A0=11
(4)Output A1/A0=11
(4)Output A1/A0=11
(4)Output A1/A0=11
MSB
LSB
(1)
00
(1)
00
(1)
00
(1)
00
(2)
01
(2)
01
(2)
01
(2)
01
(3)
10
(3)
10
(3)
10
(3)
10
(4)
11
(4)
11
(4)
11
(4)
11
8-bit
(B) Halfword Access
(a) PA1/PA0=00
→(1)Output A1/A0=00
(2)Output A1/A0=01
(b) PA1/PA0=01
→(1)Output A1/A0=00
(2)Output A1/A0=01
(c) PA1/PA0=10
→(1)Output A1/A0=10
(2)Output A1/A0=11
(d) PA1/PA0=11
→(1)Output A1/A0=10
(2)Output A1/A0=11
(1)
00
(1)
00
00
00
(2)
01
(2)
01
01
01
10
10
(1)
10
(1)
10
11
11
(2)
11
(2)
11
(C) Byte Access
(a) PA1/PA0=00
→(1)Output A1/A0=00
(1)
(b) PA1/PA0=01
→(1)Output A1/A0=01
00
01
(c) PA1/PA0=10
(d) PA1/PA0=11
→(1)Output A1/A0=10
→(1)Output A1/A0=11
00
(1)
01
10
10
11
11
(1)
00
00
01
01
10
10
11
(1)
11
161
CHAPTER 5 EXTERNAL BUS INTERFACE
■ Example of Connection with External Devices
Figure 5.4-9 shows an example of connection to LSI and external devices.
Figure 5.4-9 Example of Connecting to External Devices
This LSI
D15
D07
to WR0 to WR1
D08
D00
*: For 16/8-bit devices, use the data bus
on the MSB side of this LSI.
0
1
D15 D08 D07 D00
16-bit device*
0
D07 D00
8-bit device*
("0"/"1" address lower 1-bit)
162
CHAPTER 5 EXTERNAL BUS INTERFACE
5.4.3
External Access
The relationship between the internal register and the external data bus by bus width is
explained.
■ Word Access
The following is for word access.
Big endian mode
Bus width of 16 bits
Internal
register
External
pin
Control
pin
Address: "0" "2"
D31
D15
AA
AA CC
WR0
BB
BB DD
WR1
D00
CC
DD
D00
(1) (2)
Bus width of 8 bits
Internal
register
Address:
D31
External
pin
Control
pin
"0" "1" "2" "3"
D15
AA
AA BB CC DD
WR0
D08
D08
BB
CC
DD
D00
(1)
(2)
(3)
(4)
163
CHAPTER 5 EXTERNAL BUS INTERFACE
■ Halfword Access
The following is for halfword access.
Big endian mode
Bus width of 16 bits
Internal
register
External
pin
Control
pin
Address: "0"
D15
AA
WR0
BB
WR1
D31
D00
AA
BB
D00
(1)
Internal
register
D31
External
pin
Control
pin
Address: "2"
D15
CC
WR0
DD
WR1
D00
D00
CC
DD
D00
(1)
Bus width of 8 bits
Internal
register
External
pin
Address: "0" "1"
D31
D15
AA BB
D08
D08
Control
pin
WR0
AA
BB
D00
(1) (2)
Internal
register
External
pin
Address: "2" "3"
D31
D15
CC DD
D08
D08
CC
DD
D00
164
(1) (2)
Control
pin
WR0
CHAPTER 5 EXTERNAL BUS INTERFACE
■ Byte Access
The following is for byte access.
Big endian mode
Bus width of 16 bits
Internal
register
External
pin
Address: "0"
D31
D15
AA
Control
pin
WR0
D00
AA
D00
(1)
Internal
register
External
pin
Control
pin
Address: "1"
D31
D15
BB
WR1
D00
D00
BB
D00
(1)
Internal
register
External
pin
Address: "2"
D31
D15
CC
Control
pin
WR0
D00
D00
CC
D00
Internal
register
External
pin
Control
pin
Address: "3"
D31
D15
DD
WR1
D00
D00
DD
D00
165
CHAPTER 5 EXTERNAL BUS INTERFACE
Big endian mode
Bus width of 8 bits
Internal
register
External
pin
Control
pin
Address: "0"
D31
D15
AA
WR0
D08
AA
D00
(1)
Internal
register
External
pin
Address: "1"
D31
D15
BB
D08
Control
pin
WR0
BB
D00
(1)
Internal
register
External
pin
Address: "2"
D31
D15
CC
D08
Control
pin
WR0
CC
D00
(1)
Internal
register
External
pin
Address: "3"
D31
D15
DD
D08
DD
D00
(1)
166
Control
pin
WR0
CHAPTER 5 EXTERNAL BUS INTERFACE
5.5
Ordinary Bus Interface
For the ordinary bus interface, two clock cycles are the basic bus cycles for both read
access and write access.
■ Basic Timing (For Successive Accesses) (TYP3 to TYP0= 0000B, AWR=0008H)
Figure 5.5-1 shows basic timing for successive accesses.
Figure 5.5-1 Basic Timing for Successive Accesses
SYSCLK
A23 to A0
#2
#1
AS
CSn
RD
READ
D15 to D0
#2
#1
WRn
WRITE
D15 to D0
#1
#2
• AS is asserted for one cycle in the bus access start cycle.
• A23 to A0 continues to output the address of the start byte location in word/halfword/byte access from
the bus access start cycle to the bus access end cycle.
• If the W02 bit of the AWR0 to AWR3 registers is 0, CS0 to CS3 are asserted at the same timing as AS.
For successive accesses, CS0 to CS3 are not negated. If the W00 bit of the AWR register is "0", CS0 to
CS3 are negated after the bus cycle ends. If the W00 bit is "1", CS0 to CS3 are negated one cycle after
bus access ends.
• RD, WR0, and WR1 are asserted from the 2nd cycle of the bus access. Negation occurs after the wait
cycle of bits W14 to W12 of the AWR register is inserted. The timing of asserting RD, WR0, and WR1
can be delayed by one cycle by setting the W01 bit of the AWR register to "1".
• For read access, D15 to D0 is read when SYSCLK rises in the cycle in which the wait cycle ended after
RD was asserted.
• For write access, data output to D15 to D0 starts at the timing at which WR0 and WR1 are asserted.
167
CHAPTER 5 EXTERNAL BUS INTERFACE
■ WRn + Byte Control Type (TYP3 to TYP0 = 0010B, AWR = 0008H)
Figure 5.5-2 shows WRn+ byte control type.
Figure 5.5-2 WRn + Byte Control Type
SYSCLK
A23 to A0
AS
CSn
RD
WR0
READ
WR1
D15 to D0
WR0
WRITE WR1
D15 to D0
• Operation of AS, CSn, RD, A23 to A0 and D15 to D0 is the same as that described in "(1) Basic
Timing".
• The timing of asserting RD, WR0, and WR1 can be delayed by one cycle by setting the W01 bit of the
AWR register to "1". (Operation is the same as that for WR0 and WR1 described in "(1) Basic
Timing".)
• WR0 and WR1 indicate the byte location expressed with negative logic when they are used for access as
the byte enable signal. Assertion continues from the bus access start cycle to the bus access end cycle
and changes at the same timing as the address timing. The byte location for access is indicated for both
read access and write access.
168
CHAPTER 5 EXTERNAL BUS INTERFACE
■ Read --> Write Timing (TYP3 to TYP0=0000B, AWR=0048H)
Figure 5.5-3 shows read →write timing.
Figure 5.5-3 Read →Write Timing
Read
Idle
Write
SYSCLK
A23 to A0
AS
CSn
RD
WRn
D15 to D0
• Setting of the W06 bits of the AWR register enables 0 or 1 idle cycle to be inserted.
• Settings in the CS area on the read side are enabled.
• This idle cycle is inserted if the next access after a read access is write access or access to another area.
169
CHAPTER 5 EXTERNAL BUS INTERFACE
■ Write →Write Timing (TYP3 to TYP0=0000B, AWR=0018H)
Figure 5.5-4 shows write →write timing.
Figure 5.5-4 Write →Write Timing
Write
Write recovery
Write
SYSCLK
A23 to A0
AS
CSn
WRn
D15 to D0
• Setting of the W04 bits of the AWR register enables 0 or 1 write recovery cycle to be inserted.
• After all of the write cycles, recovery cycles are generated.
• Write recovery cycles are also generated if write access is divided into phases for access with a bus
width wider than that specified.
170
CHAPTER 5 EXTERNAL BUS INTERFACE
■ Auto-Wait Timing (TYP3 to TYP0=0000B, AWR=2008H)
Figure 5.5-5 shows auto-wait timing.
Figure 5.5-5 Auto-Wait Timing
Basic cycle
Wait cycle
SYSCLK
A23 to A0
AS
CSn
RD
READ
D15 to D0
WRn
WRITE
D15 to D0
• Setting of the W14 to W12 bits (first wait cycles) of the AWR register enables 0 to 7 auto-wait cycles to
be set.
• In Figure 5.5-5, two auto-wait cycles are inserted, making a total of four cycles for access. If auto-wait
is set, the minimum number of bus cycles is 2 cycles + (first wait cycles). For a write operation, the
minimum number of bus cycles may be still longer depending on the internal state.
171
CHAPTER 5 EXTERNAL BUS INTERFACE
■ External Wait Timing (TYP3 to TYP0=0001B, AWR=2008H)
Figure 5.5-6 shows the operation timing for the external wait.
Figure 5.5-6 External Wait Timing
Basic cycle
Automatic wait 2 cycle
Wait cycle by RDY
SYSCLK
A23 to A0
AS
CSn
RD
READ
D15 to D0
WRn
WRITE
D15 to D0
clear
RDY
wait
• Setting "1" for the TYP0 bit of the ACR register and enabling the external RDY input pin enable
external wait cycles to be inserted. In the figure above, because waiting using the auto-wait cycle is
enabled, the section of the RDY pin indicated by hatching is disabled. The value at the RDY input pin is
evaluated from the last automatic wait cycle on. Also, after a wait cycle is completed, the value of the
RDY input pin is disabled until the next access cycle starts.
172
CHAPTER 5 EXTERNAL BUS INTERFACE
■ CS Delay Setting (TYP3 to TYP0=0000B, AWR=000CH)
Figure 5.5-7 shows CS delay setting.
Figure 5.5-7 CS Delay Setting
SYSCLK
A23 to A0
AS
CSn
RD
READ
D15 to D0
WRn
WRITE
D15 to D0
• If the W02 bit is "1", assertion starts in the cycle following the cycle in which AS is asserted. For
successive accesses, a negation period is inserted.
173
CHAPTER 5 EXTERNAL BUS INTERFACE
■ CS --> RD/WR Setup and RD/WR --> CS Hold Setting (TYP3 to TYP0=0000B,AWR=000BH)
Figure 5.5-8 shows CS →RD/WR setup and RD/WR →CS hold settings.
Figure 5.5-8 CS →RD/WR Setup and RD/WR →CS Hold Settings
SYSCLK
A23 to A0
AS
CSn
CS->RD/WR
Delay
RD/WR->CS
Delay
RD
READ
D15 to D0
WRn
WRITE
D15 to D0
• Setting "1" for the W01 bit of the AWR register enables the CS -> RD/WR setup delay to be set. Set this
bit to extend the period between chip select assertion and read/write strobe.
• Setting "1" for the W00 bit of the AWR register enables the RD/WR -> CS hold delay to be set. Set this
bit to extend the period between read/write strobe negation and chip select negation.
• The CS -> RD/WR setup delay (W01 bit) and RD/WR -> CS hold delay (W00 bit) can be set
independently.
• When making successive accesses within the same chip select area without negating the chip select,
neither a CS -> RD/WR setup delay nor an RD/WR -> CS hold delay is inserted.
• If a setup cycle for determining the address or a hold cycle for determining the address is needed, set "1"
for the address -> CS delay setting (W02 bit of the AWR register).
174
CHAPTER 5 EXTERNAL BUS INTERFACE
5.6
Address/Data Multiplex Interface
This section explains setting of the address/data multiplex interface.
■ Without External Wait (TYP3 to TYP0=0100B, AWR=0008H)
Figure 5.6-1 shows a setting for the address/data multiplex interface (without external wait).
Figure 5.6-1 Setting for the Address/Data Multiplex Interface (without External Wait)
SYSCLK
A23 to A0
address[23:0]
AS
CSn
RD
READ
D15 to D0
address[15:0]
data
[15:0]
WR
WRITE
D15 to D0
address[15:0]
data
[15:0]
• Making a setting such as TYP3 to TYP0=01xxB in the ACR register enables the address/data multiplex
interface to be set.
• If the address/data multiplex interface is set, set 8 bits or 16 bits for the data bus width (DBWO1,
DBWO0 bits).
• In the address/data multiplex interface, the total of 3 cycles of 2 address output cycles + 1 data cycle
becomes the basic number of access cycles.
• In the address output cycles, AS is asserted as the output address latch enable signal. However, when CS
→ RD/WR setup delay (AWR:W01) is set to "0", the multiplex address output cycle consists of only
one cycle as shown in the figure above. Since the address cannot be directly latched at the rising edge of
AS, fetch the address at the rising edge of SYSCLK of the cycle in which AS is asserted (Low). When
the address is directly latched at the rising edge of AS, see Setting of CS →RD/WR setup.
• As with a normal interface, the address indicating the start of access is outputted to A23 to A0 during
the time division bus cycle. Use this address if you want to use an address more than 8/16 bits in the
address/data multiplex interface.
• As with the normal interface, auto-wait (AWR:W14 to AWR:W12), read -> write idle cycle
(AWR:W06), write recovery (AWR:W04), address -> CS delay (AWR:W02), CS -> RD/WR setup
delay (AWR:W01), and RD/WR -> CS hold delay (AWR:W00) can be set.
175
CHAPTER 5 EXTERNAL BUS INTERFACE
■ With External Wait (TYP3 to TYP0=0101B, AWR=1008H)
Figure 5.6-2 shows a setting for the address/data multiplex interface (with external wait).
Figure 5.6-2 Setting for the Address/Data Multiplex Interface (with External Wait)
SYSCLK
A23 to A0
address[23:0]
AS
CSn
RD
READ
D15 to D0
data
[15:0]
address[15:0]
WR
WRITE
D15 to D0
data[15:0]
address[15:0]
external wait
clear
RDY
• Making a setting such as TYP3 to TYP0=01x1B in the ACR register enables RDY input in the address/
data multiplex interface.
176
CHAPTER 5 EXTERNAL BUS INTERFACE
■ Setting of CS →RD/WR Setup (TYP3 to TYP0=0101B, AWR=100BH)
Figure 5.6-3 shows a setting of CS →RD/WR setup.
Figure 5.6-3 Setting of CS →RD/WR Setup
SYSCLK
A23 to A0
address[23:0]
AS
CSn
RD
READ
D15 to D0
address[15:0]
data
[15:0]
WR
WRITE
D15 to D0
address[15:0]
data[15:0]
• Setting "1" for the CS →RD/WR setup delay (AWR:W01) enables the multiplex address output cycle
to be extended by one cycle as shown in Figure 5.6-3, allowing the address to be latched directly to the
rising edge of AS. Use this setting if you want to use AS as an ALE (Address Latch Enable) strobe
without using SYSCLK.
177
CHAPTER 5 EXTERNAL BUS INTERFACE
5.7
DMA Access
This section explains setting of DMA access.
■ 2-Cycle Transfer (The Timing is the Same as for Internal RAM --> External I/O, RAM,
External I/O, RAM --> Internal RAM.) (TYP3 to TYP0=0000B, AWR=0008H)
Figure 5.7-1 shows a setting of 2-cycle transfer.
Figure 5.7-1 Setting of 2-cycle Transfer (When a Wait is not Set on the I/O Side)
SYSCLK
A23 to A0
I/O address
AS
CSn (I/O side)
WRn
D15 to D0
• Bus access is the same as that of the interface for non-DMAC transfer.
178
CHAPTER 5 EXTERNAL BUS INTERFACE
■ 2-Cycle Transfer (External --> I/O) (TYP3 to TYP0=0000B, AWR=0008H)
Figure 5.7-2 shows a setting of 2-cycle transfer (external →I/O).
Figure 5.7-2 Setting of 2-cycle Transfer (External →I/O) (When a Wait is not Set for Memory and I/O)
SYSCLK
A23 to A0
memory address
idle
I/O address
AS
CSn
RD
CSn
WRn
D15 to D0
• Bus access is the same as that of the interface for non-DMAC transfer.
179
CHAPTER 5 EXTERNAL BUS INTERFACE
■ 2-Cycle Transfer (I/O --> External) (TYP3 to TYP0=0000B, AWR=0008H)
Figure 5.7-3 shows a setting of 2-cycle transfer (I/O →external).
Figure 5.7-3 Setting of 2-cycle Transfer (I/O →External) (When a Wait is not Set for Memory and I/O)
SYSCLK
A23 to A0
I/O address
idle
memory address
AS
CSn
WRn
CSn
RD
D15 to D0
• Bus access is the same as that of the interface for non-DMAC transfer.
180
CHAPTER 5 EXTERNAL BUS INTERFACE
5.8
Procedure for Setting Registers
For setting procedure concerning with external bus interface, follow the principle
described below.
■ Procedure for External Bus Interface
1. Before rewriting the contents of a register, be sure to set the CSER register so that the corresponding
area is not used (0). If you change the settings while "1" is set, access before and after the change cannot
be guaranteed.
2. Use the following procedure to change a register:
1)
Set "0" for the CSER bit corresponding to the applicable area.
2)
Set both ASR and ACR at the same time using word access. When accessing ASR and ACR in half
word, set ACR after setting ASR.
3)
Set AWR.
4)
Set the CSER bit corresponding to the applicable area.
3. The CS0 area is enabled after a reset is released. If the area is used as a program area, the register
contents need to be rewritten while the CSER bit is "1". In this case, make the settings described in 2) to
3) above in the initial state with a low-speed internal clock. Then, switch the clock to a high-speed
clock.
181
CHAPTER 5 EXTERNAL BUS INTERFACE
182
CHAPTER 6
I/O PORT
This chapter describes the I/O ports and the
configuration and functions of registers.
6.1 Overview of I/O Ports
6.2 Port Data Register (PDR)/Data Direction Register (DDR)
6.3 Setting of the Port Function Register
6.4 Rearrangement of External Interrupt Input
6.5 Selection of Pin Input Level
6.6 Pull-up and Pull-down Control Register
6.7 Input Data Direct Read Register
183
CHAPTER 6 I/O PORT
6.1
Overview of I/O Ports
This section provides an overview of the I/O port.
■ Basic Block Diagram of the I/O Port
This LSI can be used as an I/O port if settings are made so that the external bus interfaces or peripherals
corresponding to pins do not use the pins as input/output pins.
Figure 6.1-1 shows the basic configuration of the I/O port.
Figure 6.1-1 Basic Block Diagram of The I/O Port
R-bus
TTL
1
External Bus Interface Input
PILR
0
Peripheral Input
PIDR Read
0
PDR Read
PPER
PPCR
1
184
Automotive
50kΩ
P-ch
Output
Driver
Pin
Output
MUX
50kΩ
N-ch
DDR
EPFR
1
Pull Up/
Down
Control
PDR
PFR
0
PIDR
(Input
CLKP
Sample)
Peripheral Output
Peripheral Output
CMOS
Schmitt
Port
Direction
Control
CHAPTER 6 I/O PORT
■ General Specification of Ports
• Each port has the port data register (PDR) and stores the output data. The content of the PDR register is
not initialized after a reset.
• Each port has the data direction register (DDR) and switches the I/O direction of the port. All ports are
inputted after a reset (DDR=00H).
- Port input mode (PFR=0 & DDR=0)
PDR read : Reads the level of the corresponding external pin.
PDR write : Writes a setting value to the PDR.
- Port output mode (PFR=0 & DDR=1)
PDR read : Reads the value of the PDR.
PDR write : Writes the setting value to the PDR and outputs to the corresponding
external pin.
- Peripheral output mode (PFR=1)
PDR read : Reads the value of the corresponding peripheral output.
PDR write : Writes a setting value to the PDR.
- The setting value of the register is read at read-modify-write instruction to the port data register
regardless of the port state.
- The input to the peripheral is always connected to the pin except the special purpose. Perform the
input to the peripheral in the port input mode normally.
• Each port has the input data direct read register (PIDR). This register is read only and is used to read the
input value directly even if the port is output state.
• Each port has the port input level register (PILR) that can switch the pin input level with software. The
CMOS Schmitt trigger or CMOS Automotive Schmitt trigger can be selected for the input level. Also,
in the external bus mode, the pin set as the external bus interface input can select the TTL input level.
• Each port (except part of the ports) has the pull-up/-down enable register (PPER) and
control register, and can set the pull-up/-down of 50kΩ per pin.
pull-up/-down
• The ports have the port function register (PFR), and some have the extended port function register
(EPFR). They mainly control the peripheral output.
• In the external bus mode, the pin assigned to the external bus interface invalidates the setting of DDR
and PFR, and the function of the bus interface is prioritized. When these pins are used as the generalpurpose port/peripheral output in the external bus mode, set the EPFR and disable the function of the
bus interface.
• When the HIZ bit of the STCR register is set in STOP mode, input is fixed to "0". However, the external
interrupt input is not fixed when the corresponding interrupt is enabled (setting of ENIR bit and input
pin selection by EISSR/EPFR), but input to the pin can be used as the interrupt.
• Bidirectional signal of the peripheral (such as SCK of LIN-UART) is valid by the PFR.
See corresponding chapters for switching of I/O.
Note:
There is no register for switching between general-purpose port input and peripheral input.
A value input from an external pin is always transmitted to a general-purpose port and a peripheral
circuit.
To use ports as peripheral input, set DDR to input to enable input signals from each peripheral.
185
CHAPTER 6 I/O PORT
6.2
Port Data Register (PDR)/Data Direction Register (DDR)
This section shows the port data register (PDR) and data direction register (DDR).
■ Port Data Register (PDR)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PDR0 000000H
PDR07
PDR06
PDR05
PDR04
PDR03
PDR02
PDR01
PDR00
XXXXXXXXB
PDR1 000001H
PDR17
PDR16
PDR15
PDR14
PDR13
PDR12
PDR11
PDR10
XXXXXXXXB
PDR2 000002H
PDR27
PDR26
PDR25
PDR24
PDR23
PDR22
PDR21
PDR20
XXXXXXXXB
PDR3 000003H
PDR37
PDR36
PDR35
PDR34
PDR33
PDR32
PDR31
PDR30
XXXXXXXXB
PDR4 000004H
PDR47
PDR46
PDR45
PDR44
PDR43
PDR42
PDR41
PDR40
XXXXXXXXB
PDR5 000005H
PDR57
PDR56
PDR55
PDR54
PDR53
PDR52
PDR51
PDR50
XXXXXXXXB
PDR6 000006H
PDR67
PDR66
PDR65
PDR64
PDR63
PDR62
PDR61
PDR60
XXXXXXXXB
PDR7 000007H
PDR77
PDR76
PDR75
PDR04
PDR73
PDR72
PDR71
PDR70
XXXXXXXXB
PDR8 000008H
PDR87
PDR86
PDR85
PDR84
PDR83
PDR82
PDR81
PDR80
XXXXXXXXB
PDR9 000009H
PDR97
PDR96
PDR95
PDR94
PDR93
PDR92
PDR91
PDR90
XXXXXXXXB
PDRA 00000AH
-
-
-
-
-
-
PDRA1
PDRA0
------XXB
PDRB 00000BH
-
-
PDRB5
PDRB4
PDRB3
PDRB2
PDRB1
PDRB0
--XXXXXXB
PDRC 00000CH
PDRC7 PDRC6 PDRC5 PDRC4 PDRC3 PDRC2 PDRC1 PDRC0
PDRD 00000DH
PDRD7 PDRD6 PDRD5 PDRD4 PDRD3 PDRD2 PDRD1 PDRD0
XXXXXXXXB
PDRE 00000EH
PDRE7
PDRE6
PDRE5
PDRE4
PDRE3
PDRE2
PDRE1
PDRE0
XXXXXXXXB
PDRF 00000FH
PDRF7
PDRF6
PDRF5
PDRF4
PDRF3
PDRF2
PDRF1
PDRF0
XXXXXXXXB
PDRG 000010H
PDRG7 PDRG6 PDRG5 PDRG4 PDRG3 PDRG2 PDRG1 PDRG0
XXXXXXXXB
R/W
R/W
R/W
R/W: Readable/Writable
X:
Undefined
Note: PDRB to PDRG can use only MB91V280.
186
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
CHAPTER 6 I/O PORT
■ Data Direction Register (DDR)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
DDR0 000000H
DDR07
DDR06
DDR05
DDR04
DDR03
DDR02
DDR01
DDR00
00000000B
DDR1 000001H
DDR17
DDR16
DDR15
DDR14
DDR13
DDR12
DDR11
DDR10
00000000B
DDR2 000002H
DDR27
DDR26
DDR25
DDR24
DDR23
DDR22
DDR21
DDR20
00000000B
DDR3 000003H
DDR37
DDR36
DDR35
DDR34
DDR33
DDR32
DDR31
DDR30
00000000B
DDR4 000004H
DDR47
DDR46
DDR45
DDR44
DDR43
DDR42
DDR41
DDR40
00000000B
DDR5 000005H
DDR57
DDR56
DDR55
DDR54
DDR53
DDR52
DDR51
DDR50
00000000B
DDR6 000006H
DDR67
DDR66
DDR65
DDR64
DDR63
DDR62
DDR61
DDR60
00000000B
DDR7 000007H
DDR77
DDR76
DDR75
DDR04
DDR73
DDR72
DDR71
DDR70
00000000B
DDR8 000008H
DDR87
DDR86
DDR85
DDR84
DDR83
DDR82
DDR81
DDR80
00000000B
DDR9 000009H
DDR97
DDR96
DDR95
DDR94
DDR93
DDR92
DDR91
DDR90
00000000B
DDRA 00000AH
-
-
-
-
-
-
DDRB 00000BH
-
-
DDRA1 DDRA0
------00B
DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
--000000B
DDRC 00000CH
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
00000000B
DDRD 00000DH
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
00000000B
DDRE 00000EH
DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
00000000B
DDRF 00000FH
DDRF7
DDRF0
00000000B
DDRG 000010H
DDRG7 DDRG6 DDRG5 DDRG4 DDRG3 DDRG2 DDRG1 DDRG0
00000000B
R/W
DDRF6
R/W
DDRF5
R/W
DDRF4
R/W
DDRF3
R/W
DDRF2
R/W
DDRF1
R/W
R/W
R/W: Readable/Writable
Note: DDRB to DDRG can use only MB91V280.
187
CHAPTER 6 I/O PORT
6.3
Setting of the Port Function Register
This section explains the function of the port function register.
■ Port 0
Port 0 is controlled by PFR0.
In the external bus mode, port 0 is D7 to D0 of bus interface. In other mode, it is assigned to LIN-UART5
and UART6.
Input signal to external interrupt INT15 to INT8 and input signal to LIN-UART (SIN5, SIN6) are always
connected with pins.
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PFR0 000420H
R/W
R/W
PFR05
R/W
PFR04
R/W
R/W
PFR02
R/W
PFR01
R/W
R/W
--00-00-B
R/W: Readable/Writable
Bit
Value
Function
0
General-purpose port
1
SCK of LIN-UART6
I/O direction of SCK is switched with SCKE bit of LIN-UART6.
0
General-purpose port
1
SOT output of LIN-UART6
0
General-purpose port
1
SCK of LIN-UART5
I/O direction of SCK is switched with SCKE bit of LIN-UART5.
0
General-purpose port
1
SOT output of LIN-UART5
PFR05
PFR04
PFR02
PFR01
188
CHAPTER 6 I/O PORT
■ Port 1
Port 1 is controlled by PFR1 and EPFR1.
In the external bus mode, port 1 is D15 to D8 of bus interface. In other mode, it is assigned to LIN-UART5
and 6 and reload timer 1.
To enable INT11R of P12 as an external interrupt pin, set EISSR11.
Input signal (SIN3, SIN4) to LIN-UART is always connected with pins.
Address
PFR1 000421H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PFR17
PFR16
-
PFR14
PFR13
-
-
-
00-00---B
R/W
R/W
R/W
R/W
R/W
R/W
EPFR11
R/W
R/W
------0-B
EPFR1 000601H
R/W: Readable/Writable
Bit
Value
Function
0
General-purpose port
1
SCK of LIN-UART4
I/O direction of SCK is switched with SCKE bit of LIN-UART4
0
General-purpose port
1
SOT output of LIN-UART4
0
General-purpose port
1
SCK of LIN-UART3
I/O direction of SCK is switched with SCKE bit of LIN-UART3
0
General-purpose port
1
SOT output of LIN-UART3
0
General-purpose port
1
TOT output of reload timer 1
PFR17
PFR16
PFR14
PFR13
EPFR11
189
CHAPTER 6 I/O PORT
■ Port 2
Port 2 is controlled by PFR2 and EPFR2.
In the external bus mode, port 2 is A23 to A16 of bus interface. In other mode, it is assigned to input
capture 0 to capture 3, PPGF, PPGD, PPGB, and PPG9.
Address
PFR2 000422H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PFR27
PFR26
PFR25
PFR24
PFR23
PFR22
PFR21
PFR20
00000000B
EPFR2 000602H EPFR27 EPFR26 EPFR25 EPFR24 EPFR23 EPFR22 EPFR21 EPFR20
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
R/W
R/W: Readable/Writable
Bit
Value
Function
0
General-purpose port
1
LSYN output of LIN-UART3 is connected to ICU3.
0
General-purpose port
1
LSYN output of LIN-UART2 is connected to ICU2.
0
General-purpose port
1
LSYN output of LIN-UART1 is connected to ICU1.
0
General-purpose port
1
LSYN output of LIN-UART0 is connected to ICU0.
0
General-purpose port
1
PPGF output
0
General-purpose port
1
PPGD output
0
General-purpose port
1
PPGB output
0
General-purpose port
1
PPG9 output
PFR27
PFR26
PFR25
PFR24
PFR23
PFR22
PFR21
PFR20
The external bus address output can be disabled by setting of the EPFR even in the external bus mode.
Bit
EPFR27 to
EPFR20
190
Value
Function (external bus mode)
0
External bus address output A23 to A16
1
Controlled by PFR27 to PFR20
CHAPTER 6 I/O PORT
■ Port 3
Port 3 is controlled by PFR3 and EPFR3.
In the external bus mode, port 3 is a control pin of bus interface. In other mode, it is assigned to output
compare 4 to compare 7, CAN2, and input 4 and capture 5.
To enable INT10R of P32 as an external interrupt pin, set EISSR10.
Address
PFR3 000423H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PFR37
PFR36
PFR35
PFR34
PFR33
-
PFR31
PFR30
00000-00B
EPFR3 000603H EPFR37 EPFR36 EPFR35 EPFR34 EPFR33 EPFR32 EPFR31 EPFR30
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
R/W
R/W: Readable/Writable
Bit
Value
Function
0
General-purpose port
1
OCU7 output
0
General-purpose port
1
OCU6 output
0
General-purpose port
1
OCU5 output
0
General-purpose port
1
OCU4 output
0
General-purpose port
1
TX output of CAN2
0
General-purpose port
1
LSYN output of LIN-UART5 is connected to ICU5.
0
General-purpose port
1
LSYN output of LIN-UART4 is connected to ICU4.
PFR37
PFR36
PFR35
PFR34
PFR33
PFR31
PFR30
191
CHAPTER 6 I/O PORT
The external bus control signal can be disabled by setting of EPFR even in the external bus mode. In the
external bus mode of MB91F273(S) and MB91F278(S), be sure to set EPFR35 and EPFR34 to "1".
Bit
Value
Function (external bus mode)
0
SYSCLK output
1
Controlled by PFR37
0
RDY input
1
Controlled by PFR36
0
BGRNT output (MB91V280 only)
1
Controlled by PFR35
0
BRQ input (MB91V280 only)
1
Controlled by PFR34
0
WR1 output
1
Controlled by PFR33
0
WR0 output
1
Controlled by PFR32
0
RD output
1
Controlled by PFR31
0
AS output
1
Controlled by PFR30
EPFR37
EPFR36
EPFR35
EPFR34
EPFR33
EPFR32
EPFR31
EPFR30
192
CHAPTER 6 I/O PORT
■ Port 4
Port 4 is controlled by PFR4 and EPFR4.
Input signal (ZIN2, BIN2, AIN2) of up/down counter 2/3 and external clock input (FRCK0, FRCK1) of
free-run timer are always connected with pins.
To enable INT9R of P42 as an external interrupt pin, set EISSR[9].
EPFR42 and EPFR43 are reserved bits. Be sure to set these bits to "00B".
Address
PFR4 000424H
EPFR4 000604H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PFR47
PFR46
PFR45
PFR44
PFR43
PFR42
-
-
000000--B
R/W
R/W
R/W
R/W
R/W
R/W
----00--B
EPFR43 EPFR42
R/W
R/W
R/W: Readable/Writable
Bit
Value
Function
0
General-purpose port
1
SCL I/O of I2C1
Output is N-ch open-drain.
0
General-purpose port
1
SDA I/O of I2C1
Output is N-ch open-drain.
0
General-purpose port
1
SCL I/O of I2C0
Output is N-ch open-drain.
0
General-purpose port
1
SDA I/O of I2C0
Output is N-ch open-drain.
0
General-purpose port
1
TX output of CAN1
LSYN output of LIN-UART6 is connected to ICU7.
0
General-purpose port
1
LSYN output of LIN-UART6 is connected to ICU6.
Pin can be used as RX input of CAN1.
PFR47
PFR46
PFR45
PFR44
PFR43
PFR42
193
CHAPTER 6 I/O PORT
■ Port 5
Port 5 is controlled by PFR5 and A/D converter/D/A converter.
Input signal (ZIN1, BIN1, AIN1) of up/down counter 0/1 and input signal (SIN2) to LIN-UART2 are
always connected with pins.
Port 5 is shared with analog input of A/D converter for all pins. When the corresponding bit of the ADER
register is set, the port setting is invalid and sets to the analog input pin. In this case, all input values to the
pin are handled as 0.
P57 and P56 are shared with analog output of D/A converter. When the output of D/A converter is enabled,
they are set to analog output the same way as mentioned above, and the input value is handled as "0".
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PFR5 000425H
R/W
R/W
R/W
R/W
R/W
PFR52
R/W
PFR51
R/W
R/W
-----00-B
R/W: Readable/Writable
Bit
Value
Function
0
General-purpose port
1
SCK of LIN-UART2
I/O direction of SCK is switched with SCKE bit of LIN-UART2.
0
General-purpose port
1
SOT output of LIN-UART2
PFR52
PFR51
Note:
The D/A converter has been provided only for MB91V280.
194
CHAPTER 6 I/O PORT
■ Port 6
Port 6 is controlled by PFR6 and A/D converter.
Port 6 is shared with analog input of A/D converter for all pins. When the corresponding bit of the ADER
register is set, the port setting is invalid and sets to the analog input pin. In this case, all input values to the
pin are handled as "0".
Address
PFR6 000426H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PFR67
R/W
PFR66
R/W
PFR65
R/W
PFR64
R/W
PFR63
R/W
PFR66
R/W
PFR61
R/W
PFR60
R/W
00000000B
R/W: Readable/Writable
Bit
Value
Function
0
General-purpose port
1
PPGE output
0
General-purpose port
1
PPGC output
0
General-purpose port
1
PPGA output
0
General-purpose port
1
PPG8 output
0
General-purpose port
1
PPG6 output
0
General-purpose port
1
PPG4 output
0
General-purpose port
1
PPG2 output
0
General-purpose port
1
PPG0 output
PFR67
PFR66
PFR65
PFR64
PFR63
PFR62
PFR61
PFR60
195
CHAPTER 6 I/O PORT
■ Port 7
Port 7 is controlled by PFR7 and A/D converter.
Port 7 is shared with analog input of A/D converter for all pins. When the corresponding bit of the ADER
register is set, the port setting is invalid and sets to the analog input pin. In this case, all input values to the
pin are handled as "0".
Input signal to external interrupt INT7 to INT0 is always connected with pins except the analog input of A/D
converter the same way as mentioned above.
Address
PFR7 000427H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PFR77
R/W
PFR76
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00------B
R/W: Readable/Writable
Bit
Value
0
General-purpose port
1
SCL I/O of I2C2
Output is open-drain.
0
General-purpose port
1
SDA I/O of I2C2
Output is open-drain.
PFR77
PFR76
196
Function
CHAPTER 6 I/O PORT
■ Port 8
Port 8 is controlled by PFR8 and EPFR8.
Input signal (TIN0, TIN2) of reload timer 0/2, input signal (SIN0, SIN1) of LIN-UART0/UART1, and
external trigger input (ADTG) of A/D converter are always connected with pins.
To enable INT15R to INT12R of P84 to P80 as an external interrupt pin, set a corresponding bit of
EISSR15 to EISSR12.
Address
PFR8 000428H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PFR87
PFR86
-
PFR84
PFR83
-
PFR81
-
00-00-0-B
R/W
R/W
R/W
R/W
EPFR83
R/W
R/W
EPFR81
R/W
R/W
----0-0-B
EPFR8 000608H
R/W: Readable/Writable
Bit
Value
Function
0
General-purpose port
1
SCK of LIN-UART1
I/O direction of SCK is switched with SCKE bit of LIN-UART1.
0
General-purpose port
1
SOT of LIN-UART1
0
General-purpose port
1
SCK of LIN-UART0
I/O direction of SCK is switched with SCKE bit of LIN-UART0.
00
General-purpose port
10
SOT of LIN-UART0
x1
TOT output of reload timer 2
00
General-purpose port
10
Clock monitor output (CKOT)
x1
TOT output of reload timer 0
PFR87
PFR86
PFR84
PFR83
EPFR83
PFR81
EPFR81
197
CHAPTER 6 I/O PORT
■ Port 9
Port 9 is controlled by PFR9 and EPFR9.
In the external bus mode, P93 to P90 are CS3 to CS0. In other mode, it is assigned to PPG7, PPG5, PPG3
and PPG1 output and input signal of up/down counter 2/3.
Address
PFR9 000429H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PFR97
PFR96
PFR95
PFR94
PFR93
PFR92
PFR91
PFR90
00000000B
R/W
R/W
R/W
R/W
EPFR9 000609H
EPFR93 EPFR92 EPFR91 EPFR90
R/W
R/W
R/W
R/W
----0000B
R/W: Readable/Writable
Bit
PFR97
PFR96
PFR95
PFR94
PFR93
PFR92
PFR91
PFR90
Value
Function
0
General-purpose port
1
OCU3 output
0
General-purpose port
1
OCU2 output
0
General-purpose port
1
OCU1 output
0
General-purpose port
1
OCU0 output
0
General-purpose port
1
PPG7 output
0
General-purpose port
1
PPG5 output
0
General-purpose port
1
PPG3 output
0
General-purpose port
1
PPG1 output
CS that is the external bus control signal can be disabled by setting of EPFR even in the external bus mode.
Bit
EPFR93
EPFR92
EPFR91
EPFR90
198
Value
Function (external bus mode)
0
CS3 output
1
Controlled by PFR93
0
CS2 output
1
Controlled by PFR92
0
CS1 output
1
Controlled by PFR91
0
CS0 output
1
Controlled by PFR90
CHAPTER 6 I/O PORT
■ Port A
Port A is controlled by PFRA.
To enable INT8R of PA0 as an external interrupt pin, set EISSR8.
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PFRA 00042AH
R/W
R/W
R/W
R/W
R/W
R/W
PFRA1
R/W
PFRA0
R/W
------00B
R/W: Readable/Writable
Bit
Value
Function
0
General-purpose port
1
TX output of CAN0
0
General-purpose port
1
When CAN is used, set this bit to "1".
PFRA1
PFRA0
Note:
Be sure to set PFRA0/PFRA1 to "1" when CAN is used.
If PFRA0/PFRA1 is set to "1", setting the DDR register to output ("1") has no effect on the CAN
communication pins (TX, RX).
199
CHAPTER 6 I/O PORT
■ Port B (Only for MB91V280)
Port B is controlled by PFRB and EPFRB.
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
PFRB5
PFRB4
PFRB3
PFRB2
PFRB1
PFRB0
--000000B
R/W
R/W
PFRB 00042BH
EPFRB 00060BH
EPFRB5 EPFRB4 EPFRB3 EPFRB2 EPFRB1 EPFRB0
R/W
R/W
R/W
R/W
R/W
R/W
--000000B
R/W: Readable/Writable
Bit
Value
Function
0
General-purpose port
1
SCK (SCK6-2) of LIN-UART6
I/O direction of SCK is switched with SCKE bit of LIN-UART6.
0
General-purpose port
1
SOT(SOT6-2) of LIN-UART6
This bit and SOT6 of P04 can be outputted simultaneously.
0
General-purpose port
1
SIN valid (SIN6-2) of LIN-UART6
P03 (SIN6) that is original input is cut off from LIN-UART6.
0
General-purpose port
1
SCK(SCK5-2) of LIN-UART5
I/O direction of SCK is switched with SCKE bit of LIN-UART5.
0
General-purpose port
1
SOT(SOT5-2) of LIN-UART5
This bit and SOT5 of P01 can be outputted simultaneously.
0
General-purpose port
1
SIN valid (SIN5-2) of LIN-UART5
P00 (SIN5) that is original input is cut off from LIN-UART5.
PFRB5
PFRB4
PFRB3
PFRB2
PFRB1
PFRB0
EPFR is used for the selection of external interrupt input pin.
200
Bit
Value
Function
EPFRB5 to
EPFRB0
0
INT13 to INT8, P05 to P00 are enabled as external interrupt input pin.
1
INT13-2 to INT8-2 of PB5 to PB0 are enabled as external interrupt input pin.
CHAPTER 6 I/O PORT
■ Port C (Only for MB91V280)
Port C is controlled by PFRC.
To enable INT7R to INT0R of PC7 to PC0 as an external interrupt pin, set a corresponding bit of EISSR7
to EISSR0.
Address
PFRC 00042CH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PFRC7
R/W
PFRC6
R/W
PFRC5
R/W
PFRC4
R/W
PFRC3
R/W
PFRC2
R/W
PFRC1
R/W
PFRC0
R/W
00000000B
R/W: Readable/Writable
Bit
Value
Function
0
General-purpose port
1
SCK (SCK4-2) of LIN-UART4
I/O direction of SCK is switched with SCKE bit of LIN-UART4.
0
General-purpose port
1
SOT (SOT4-2) of LIN-UART4
This bit and SOT4 of P16 can be outputted simultaneously.
0
General-purpose port
1
SIN valid (SIN4-2) of LIN-UART4
P15 (SIN4) that is original input is cut off from LIN-UART4.
0
General-purpose port
1
SCK (SCK3-2) of LIN-UART3
I/O direction of SCK is switched with SCKE bit of LIN-UART3.
0
General-purpose port
1
SOT (SOT3-2) of LIN-UART3
This bit and SOT3 of P13 can be outputted simultaneously.
0
General-purpose port
1
SIN valid (SIN3-2) of LIN-UART3
P12 (SIN3) that is original input is cut off from LIN-UART3.
0
General-purpose port
1
OCU5 output (OUT5-2)
This bit and OUT5 of P35 can be outputted simultaneously.
0
General-purpose port
1
OCU4 output (OUT4-2)
This bit and OUT4 of P34 can be outputted simultaneously.
PFRC7
PFRC6
PFRC5
PFRC4
PFRC3
PFRC2
PFRC1
PFRC0
201
CHAPTER 6 I/O PORT
■ Port D (Only for MB91V280)
Port D is controlled by PFRD.
Input signal to external interrupt INT23 to INT16 is always connected with pins.
Address
PFRD 00042DH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PFRD7
R/W
PFRD6
R/W
PFRD5
R/W
PFRD4
R/W
PFRD3
R/W
PFRD2
R/W
PFRD1
R/W
PFRD0
R/W
00000000B
R/W: Readable/Writable
Bit
Value
0
General-purpose port
1
Input of ICU3 is enabled (IN3-2).
P27 (IN3) that is original input is cut off from ICU3.
0
General-purpose port
1
Input of ICU2 is enabled (IN2-2).
P26 (IN2) that is original input is cut off from ICU2.
0
General-purpose port
1
Input of ICU1 is enabled (IN1-2).
P25 (IN1) that is original input is cut off from ICU1.
0
General-purpose port
1
Input of ICU0 is enabled (IN0-2).
P24 (IN0) that is original input is cut off from ICU0.
0
General-purpose port
1
PPGF output (PPGF-2)
This bit and PPGF of P23 can be outputted simultaneously.
0
General-purpose port
1
PPGD output (PPGD-2)
This bit and PPGD of P22 can be outputted simultaneously.
0
General-purpose port
1
PPGB output (PPGB-2)
This bit and PPGB of P21 can be outputted simultaneously.
0
General-purpose port
1
PPGF output (PPG9-2)
This bit and PPG9 of P21 can be outputted simultaneously.
PFRD7
PFRD6
PFRD5
PFRD4
PFRD3
PFRD2
PFRD1
PFRD0
202
Function
CHAPTER 6 I/O PORT
■ Port E (Only for MB91V280)
Port E is controlled by EPFRE.
In the external bus mode, port E is A7 to A0 of bus interface. In other mode, it is a general-purpose port.
Input signal to external interrupt INT31 to INT24 is always connected with pins.
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EPFRE 00060EH EPFRE7 EPFRE6 EPFRE5 EPFRE4 EPFRE3 EPFRE2 EPFRE1 EPFRE0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
R/W: Readable/Writable
The external bus address output can be disabled by setting of EPFR even in the external bus mode.
Valu
e
Bit
EPFRE7 to
EPFRE0
Function (external bus mode)
0
External bus address output A7 to A0
1
General-purpose port
■ Port F (Only for MB91V280)
Port F is controlled by EPFRF.
In the external bus mode, port F is A15 to A8 of bus interface. In other mode, it is a general- purpose port.
Input signal to external interrupt INT39 to INT32 is always connected with pins.
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EPFRF 00060FH EPFRF7 EPFRF6 EPFRF5 EPFRF4 EPFRF3 EPFRF2 EPFRF1 EPFRF0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
R/W: Readable/Writable
The external bus address output can be disabled by setting of EPFR even in the external bus mode.
Bit
Value
Function (external bus mode)
EPFRF7 to
EPFRF0
0
External bus address output A15 to A8
1
General-purpose port
■ Port G (Only for MB91V280)
Port G does not contain PFR and is controlled by A/D converter.
Port G is shared with analog input of A/D converter for all pins. When the corresponding bit of the ADER
register is set, the port setting is invalid and sets to the analog input pin. In this case, all input values to the
pin are handled as "0".
Otherwise, port G is always a general- purpose port.
203
CHAPTER 6 I/O PORT
6.4
Rearrangement of External Interrupt Input
The MB91270 series contain external interrupt input of up to 40 channels (INT0 to
INT39). Moreover, INT0 to INT15 can rearrange from the pin assigned at the initial state
to other pin. This rearrangement is implemented by setting the external interrupt input
pin select register (EISSR).
■ External Interrupt Input Pin Select Register (EISSR)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
EISSRH 0001AAH EISSR15 EISSR14 EISSR13 EISSR12 EISSR11 EISSR10 EISSR9 EISSR8
00000000B
EISSRL 0001ABH EISSR7 EISSR6 EISSR5 EISSR4 EISSR3 EISSR2 EISSR1 EISSR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
R/W: Readable/Writable
Table 6.4-1 shows rearrangement of an external interrupt input pin.
P32, P42, and PA0 are shared with RX input of CAN and can be used as the CAN wake up.
Table 6.4-1 Rearrangement of External Interrupt Input Pin
Bit
External interrupt input pin
0 [initial value]
1
EISSR15
INT15
P07
P84
EISSR14
INT14
P06
P82
EISSR13
INT13
P05 (PB5*)
P81
EISSR12
INT12
P04 (PB4*)
P80
EISSR11
INT11
P03 (PB3*)
P12
EISSR10
INT10
P02 (PB2*)
P32
EISSR9
INT9
P01 (PB1*)
P42
EISSR8
INT8
P00 (PB0*)
PA0
EISSR7
INT7
P77
PC7*
EISSR6
INT6
P76
PC6*
EISSR5
INT5
P75
PC5*
EISSR4
INT4
P74
PC4*
EISSR3
INT3
P73
PC3*
EISSR2
INT2
P72
PC2*
EISSR1
INT1
P71
PC1*
EISSR0
INT0
P70
PC0*
*: Only for MB91V280
204
External interrupt
channels
CHAPTER 6 I/O PORT
Reference:
INT13 to INT8 can select the input terminal with PB5 to PB0 with EPFRB of port B. In this case, set
the corresponding EISSR bit to "0".
Before switching an external interrupt input pin by setting EISSR and EPFRB, set the ENIR register bit of
corresponding channel to "0" (interrupt disabled). When switching at "1" (interrupt enabled), interrupts may
occur immediately.
205
CHAPTER 6 I/O PORT
6.5
Selection of Pin Input Level
CMOS Schmitt trigger or CMOS automotive Schmitt trigger can be selected for the pin
input level with software per pin.
In the external bus mode, CMOS Schmitt trigger or TTL can be selected for the input
signal of the external bus interface.
■ Pin Input Level
Table 6.5-1 shows the input level.
Table 6.5-1 Input Level
Name
VIH
VIL
CMOS Schmitt trigger
VIL = 0.3 × VCC
VIH = 0.7 × VCC
CMOS automotive Schmitt trigger
VIL = 0.5 × VCC
VIH = 0.8 × VCC
TTL
VIL = 0.8 V
VIH = 2.1 V
■ Selection of Pin Input Level
The pin input level select register (PILR) is used for selecting the input level per pin. Table 6.5-2 shows the
setting value of registers.
Table 6.5-2 Setting of Pin Input Level Select Register
Pin input level
Bit
Input signal
0 [initial value]
1
General-purpose port
peripheral input
CMOS Schmitt trigger
CMOS automotive Schmitt
trigger
External bus input
(D00 to D15, RDY)
CMOS Schmitt trigger
TTL
PILRxy
206
CHAPTER 6 I/O PORT
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PILR0 000540H
PILR07
PILR06
PILR05
PILR04
PILR03
PILR02
PILR01
PILR00
00000000B
PILR1 000541H
PILR17
PILR16
PILR15
PILR14
PILR13
PILR12
PILR11
PILR10
00000000B
PILR2 000542H
PILR27
PILR26
PILR25
PILR24
PILR23
PILR22
PILR21
PILR20
00000000B
PILR3 000543H
PILR37
PILR36
PILR35
PILR34
PILR33
PILR32
PILR31
PILR30
00000000B
PILR4 000544H
PILR47
PILR46
PILR45
PILR44
PILR43
PILR42
PILR41
PILR40
00000000B
PILR5 000545H
PILR57
PILR56
PILR55
PILR54
PILR53
PILR52
PILR51
PILR50
00000000B
PILR6 000546H
PILR67
PILR66
PILR65
PILR64
PILR63
PILR62
PILR61
PILR60
00000000B
PILR7 000547H
PILR77
PILR76
PILR75
PILR04
PILR73
PILR72
PILR71
PILR70
00000000B
PILR8 000548H
PILR87
PILR86
PILR85
PILR84
PILR83
PILR82
PILR81
PILR80
00000000B
PILR9 000549H
PILR97
PILR96
PILR95
PILR94
PILR93
PILR92
PILR91
PILR90
00000000B
PILRA 00054AH
-
-
-
-
-
-
PILRB 00054BH
-
-
PILRA1 PILRA0
------00B
PILRB5 PILRB4 PILRB3 PILRB2 PILRB1 PILRB0
--000000B
PILRC 00054CH
PILRC7 PILRC6 PILRC5 PILRC4 PILRC3 PILRC2 PILRC1 PILRC0
00000000B
PILRD 00054DH
PILRD7 PILRD6 PILRD5 PILRD4 PILRD3 PILRD2 PILRD1 PILRD0
00000000B
PILRE 00054EH
PILRE7 PILRE6 PILRE5 PILRE4 PILRE3 PILRE2 PILRE1 PILRE0
00000000B
PILRF 00054FH
PILRF7 PILRF6 PILRF5 PILRF4 PILRF3 PILRF2 PILRF1 PILRF0
00000000B
PILRG 000550H
PILRG7 PILRG6 PILRG5 PILRG4 PILRG3 PILRG2 PILRG1 PILRG0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/Writable
Note: PILRB to PILRG can use only MB91V280.
207
CHAPTER 6 I/O PORT
6.6
Pull-up and Pull-down Control Register
The pin has a function that adds the pull-up or pull-down of 50kΩ. This function can be
controlled by software in unit of bit.
■ Pull-up and Pull-down Control
The pull-up and pull-down functions are enabled by the port pull-up and pull-down enable register (PPER),
and the pull-up and pull-down is controlled by the port pull-up and pull-down control register (PPCR).
The pull-up or pull-down of the pin is automatically disabled as follows:
• Port is in the output state.
• At STOP mode
■ Port Pull-up and Pull-down Enable Register
Table 6.6-1 shows setting of port pull-up and pull-down enable register.
The bit corresponding to all ports other than the port that shares with I2C interface (P47 to P44, P77, P76)
and port that shares with D/A converter output (P57, P56) exists in this register.
Table 6.6-1 Setting of Port Pull-up and Pull-down Enable Register
Port pull-up and pull-down enable register
Bit
0 [initial value]
PPERxy
Pull-up and pull-down are invalid.
Note:
The D/A converter has been provided only for MB91V280.
208
1
Pull-up and pull-down are valid.
CHAPTER 6 I/O PORT
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PPER0 000500H PPER07 PPER06 PPER05 PPER04 PPER03 PPER02 PPER01 PPER00
00000000B
PPER1 000501H PPER17 PPER16 PPER15 PPER14 PPER13 PPER12 PPER11 PPER10
00000000B
PPER2 000502H PPER27 PPER26 PPER25 PPER24 PPER23 PPER22 PPER21 PPER20
00000000B
PPER3 000503H PPER37 PPER36 PPER35 PPER34 PPER33 PPER32 PPER31 PPER30
00000000B
PPER4 000504H
-
-
PPER5 000505H
-
-
PPER43 PPER42 PPER41 PPER40
----0000B
PPER55 PPER54 PPER53 PPER52 PPER51 PPER50
--000000B
PPER6 000506H PPER67 PPER66 PPER65 PPER64 PPER63 PPER62 PPER61 PPER60
00000000B
PPER7 000507H
PPER75 PPER04 PPER73 PPER72 PPER71 PPER70
00000000B
PPER8 000508H PPER87 PPER86 PPER85 PPER84 PPER83 PPER82 PPER81 PPER80
00000000B
PPER9 000509H PPER97 PPER96 PPER95 PPER94 PPER93 PPER92 PPER91 PPER90
00000000B
-
-
PPERA 00050AH
-
-
PPERB 00050BH
-
-
-
-
-
-
-
-
PPERA1 PPERA0
------00B
PPERB5 PPERB4 PPERB3 PPERB2 PPERB1 PPERB0
--000000B
PPERC 00050CH PPERC7 PPERC6 PPERC5 PPERC4 PPERC3 PPERC2 PPERC1 PPERC0
00000000B
PPERD 00050DH PPERD7 PPERD6 PPERD5 PPERD4 PPERD3 PPERD2 PPERD1 PPERD0
00000000B
PPERE 00050EH PPERE7 PPERE6 PPERE5 PPERE4 PPERE3 PPERE2 PPERE1 PPERE0
00000000B
PPERF 00050FH PPERF7 PPERF6 PPERF5 PPERF4 PPERF3 PPERF2 PPERF1 PPERF0
00000000B
PPERG 000510H PPERG7 PPERG6 PPERG5 PPERG4 PPERG3 PPERG2 PPERG1 PPERG0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/Writable
Note: PPERB to PPERG can use only MB91V280.
209
CHAPTER 6 I/O PORT
■ Port Pull-up and Pull-down Control Register
Table 6.6-2 shows setting of port pull-up and pull-down control register. The set value of each bit is
enabled only when the corresponding PPER is set.
The bit corresponding to all ports other than the port that shares with I2C interface (P47 to P44, P77, P76)
and port that shares with D/A converter output (P57, P56) exists in this register.
Table 6.6-2 Setting of Port Pull-up and Pull-down Control Register
Port pull-up and pull-down control register
Bit
0
PPCRxy
Address
1 [initial value]
Pull-down
bit7
bit6
Pull-up
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PPCR0 000520H PPCR07 PPCR06 PPCR05 PPCR04 PPCR03 PPCR02 PPCR01 PPCR00
11111111B
PPCR1 000521H PPCR17 PPCR16 PPCR15 PPCR14 PPCR13 PPCR12 PPCR11 PPCR10
11111111B
PPCR2 000522H PPCR27 PPCR26 PPCR25 PPCR24 PPCR23 PPCR22 PPCR21 PPCR20
11111111B
PPCR3 000523H PPCR37 PPCR36 PPCR35 PPCR34 PPCR33 PPCR32 PPCR31 PPCR30
11111111B
PPCR4 000524H
-
-
PPCR5 000525H
-
-
PPCR43 PPCR42 PPCR41 PPCR40
----1111B
PPCR55 PPCR54 PPCR53 PPCR52 PPCR51 PPCR50
--111111B
PPCR6 000526H PPCR67 PPCR66 PPCR65 PPCR64 PPCR63 PPCR62 PPCR61 PPCR60
11111111B
PPCR7 000527H
PPCR75 PPCR04 PPCR73 PPCR72 PPCR71 PPCR70
11111111B
PPCR8 000528H PPCR87 PPCR86 PPCR85 PPCR84 PPCR83 PPCR82 PPCR81 PPCR80
11111111B
PPCR9 000529H PPCR97 PPCR96 PPCR95 PPCR94 PPCR93 PPCR92 PPCR91 PPCR90
11111111B
-
-
PPCRA 00052AH
-
-
PPCRB 00052BH
-
-
-
-
-
-
-
-
PPCRA1 PPCRA0
------11B
PPCRB5 PPCRB4 PPCRB3 PPCRB2 PPCRB1 PPCRB0
--111111B
PPCRC 00052CH PPCRC7 PPCRC6 PPCRC5 PPCRC4 PPCRC3 PPCRC2 PPCRC1 PPCRC0
11111111B
PPCRD 00052DH PPCRD7 PPCRD6 PPCRD5 PPCRD4 PPCRD3 PPCRD2 PPCRD1 PPCRD0
11111111B
PPCRE 00052EH PPCRE7 PPCRE6 PPCRE5 PPCRE4 PPCRE3 PPCRE2 PPCRE1 PPCRE0
11111111B
PPCRF 00052FH PPCRF7 PPCRF6 PPCRF5 PPCRF4 PPCRF3 PPCRF2 PPCRF1 PPCRF0
11111111B
PPCRG 000530H PPCRG7 PPCRG6 PPCRG5 PPCRG4 PPCRG3 PPCRG2 PPCRG1 PPCRG0
11111111B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/Writable
Note: PPCRB to PPCRG can use only MB91V280.
Notes:
• For the period that pull-up or pull-down is allowed (PPER=1), write access to the PPCR is invalid
and the register value is not updated. Changing the set value of the PPCR is valid when the
corresponding PPER is "0".
• The D/A converter has been provided only for MB91V280.
210
CHAPTER 6 I/O PORT
6.7
Input Data Direct Read Register
When the input data direct read register is read, the level of the pin can be read
regardless of the port state.
■ Input Data Direct Read Register (PIDR)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PIDR0 000620H
PIDR07 PIDR06 PIDR05 PIDR04 PIDR03 PIDR02 PIDR01 PIDR00
XXXXXXXXB
PIDR1 000621H
PIDR17 PIDR16 PIDR15 PIDR14 PIDR13 PIDR12 PIDR11 PIDR10
XXXXXXXXB
PIDR2 000622H
PIDR27 PIDR26 PIDR25 PIDR24 PIDR23 PIDR22 PIDR21 PIDR20
XXXXXXXXB
PIDR3 000623H
PIDR37 PIDR36 PIDR35 PIDR34 PIDR33 PIDR32 PIDR31 PIDR30
XXXXXXXXB
PIDR4 000624H
PIDR47 PIDR46 PIDR45 PIDR44 PIDR43 PIDR42 PIDR41 PIDR40
----XXXXB
PIDR5 000625H
PIDR57 PIDR56 PIDR55 PIDR54 PIDR53 PIDR52 PIDR51 PIDR50
--XXXXXXB
PIDR6 000626H
PIDR67 PIDR66 PIDR65 PIDR64 PIDR63 PIDR62 PIDR61 PIDR60
XXXXXXXXB
PIDR7 000627H
PIDR77 PIDR76 PIDR75 PIDR04 PIDR73 PIDR72 PIDR71 PIDR70
XXXXXXXXB
PIDR8 000628H
PIDR87 PIDR86 PIDR85 PIDR84 PIDR83 PIDR82 PIDR81 PIDR80
XXXXXXXXB
PIDR9 000629H
PIDR97 PIDR96 PIDR95 PIDR94 PIDR93 PIDR92 PIDR91 PIDR90
XXXXXXXXB
PIDRA 00062AH
-
-
PIDRB 00062BH
-
-
-
-
-
-
PIDRA1 PIDRA0
PIDRB5 PIDRB4 PIDRB3 PIDRB2 PIDRB1 PIDRB0
------XXB
--XXXXXXB
PIDRC 00062CH PIDRC7 PIDRC6 PIDRC5 PIDRC4 PIDRC3 PIDRC2 PIDRC1 PIDRC0 XXXXXXXXB
PIDRD 00062DH PIDRD7 PIDRD6 PIDRD5 PIDRD4 PIDRD3 PIDRD2 PIDRD1 PIDRD0 XXXXXXXXB
PIDRE 00062EH
PIDRE7 PIDRE6 PIDRE5 PIDRE4 PIDRE3 PIDRE2 PIDRE1 PIDRE0
XXXXXXXXB
PIDRF 00062FH
PIDRF7 PIDRF6 PIDRF5 PIDRF4 PIDRF3 PIDRF2 PIDRF1 PIDRF0
XXXXXXXXB
PIDRG 000010H PIDRG7 PIDRG6 PIDRG5 PIDRG4 PIDRG3 PIDRG2 PIDRG1 PIDRG0 XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/Writable
Note: PIDRB to PIDRG can use only MB91V280.
211
CHAPTER 6 I/O PORT
212
CHAPTER 7
INTERRUPT CONTROLLER
This chapter describes the overview of the interrupt
controller, the configuration and functions of registers,
and interrupt controller operation.
7.1 Overview of the Interrupt Controller
7.2 Interrupt Controller Registers
7.3 Interrupt Controller Operation
213
CHAPTER 7 INTERRUPT CONTROLLER
7.1
Overview of the Interrupt Controller
The interrupt controller controls interrupt acceptance and arbitration processing.
■ Hardware Configuration of the Interrupt Controller
The interrupt controller consists of the following components:
• ICR register
• Interrupt priority decision circuit
• Interrupt level and interrupt number (vector) generator
• Hold request cancellation request generator
■ Major Functions of the Interrupt Controller
The interrupt controller has the following major functions:
• Detecting NMI requests and interrupt requests
• Deciding priority (using a level or number)
• Passing to the CPU an interrupt level based on the decision result to provide information about the
interrupt source
• Passing to the CPU an interrupt number based on the decision result to provide information about the
interrupt source
• Instruction for return from stop mode due to the occurrence of an interrupt with an NMI/interrupt level
other than "11111B" (to CPU)
• Generating a hold request cancellation request for the bus master
Note:
This series does not support NMI.
214
CHAPTER 7 INTERRUPT CONTROLLER
■ Interrupt Controller Registers
Figure 7.1-1 shows the registers used by the interrupt controller.
Figure 7.1-1 Interrupt Controller Registers
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
000440H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR00
000441H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR01
000442H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR02
000443H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR03
000444H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR04
000445H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR05
000446H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR06
000447H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR07
000448H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR08
000449H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR09
00044AH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR10
00044BH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR11
00044CH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR12
00044DH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR13
00044EH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR14
00044FH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR15
000450H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR16
000451H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR17
000452H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR18
000453H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR19
000454H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR10
000455H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR21
000456H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR22
000457H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR23
000458H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR24
000459H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR25
00045AH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR26
00045BH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR27
00045CH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR28
00045DH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR29
00045EH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR30
00045FH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR31
R
R/W
R/W
R/W
R/W
R/W: Readable/Writable
R:
Read only
(Continued)
215
CHAPTER 7 INTERRUPT CONTROLLER
(Continued)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
000460H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR32
000461H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR33
000462H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR34
000463H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR35
000464H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR36
000465H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR37
000466H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR38
000467H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR39
000468H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR40
000469H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR41
00046AH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR42
00046BH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR43
00046CH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR44
00046DH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR45
00046EH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR46
00046FH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR47
R
R/W
R/W
R/W
R/W
LVL4
LVL3
LVL2
LVL1
LVL0
R
R/W
R/W
R/W
R/W
000045H
MHALTI
-
-
R/W
HRCL
R/W: Readable/Writable
R:
Read only
■ Block Diagram of the Interrupt Controller
Figure 7.1-2 is a block diagram of the interrupt controller.
Figure 7.1-2 Block Diagram of the Interrupt Controller
UNMI
WAKEUP(LEVEL ≠ 11111 : "1")
Priority decision
NMI
processing
LEVEL 4 to
LEVEL 0
5
HLDREQ
cancellation
request
LEVEL
decision
ICR00
RI00
VECTOR
decision
to
ICR47
RI47
(DLYIRQ)
R-bus
216
6
LEVEL
and
VECTOR
generation
MHALT1
VCT5 to VCT0
CHAPTER 7 INTERRUPT CONTROLLER
7.2
Interrupt Controller Registers
This section describes the configuration and functions of the registers used by the
interrupt controller.
■ Interrupt Controller Registers
The interrupt controller has the following two registers:
• Interrupt control register (ICR)
• Hold request cancellation request level setting register (HRCL)
217
CHAPTER 7 INTERRUPT CONTROLLER
7.2.1
Interrupt Control Register (ICR)
An interrupt control register (ICR) is provided for each of the interrupt input and sets
the interrupt level of the corresponding interrupt request.
■ Bit Configuration of the Interrupt Control Register (ICR)
The following shows the bit configuration of the interrupt control register (ICR).
ICR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000440H
to
00046FH
-
-
-
ICR4
R
ICR3
R/W
ICR2
R/W
ICR1
R/W
ICR0
R/W
---11111B
R/W: Readable/Writable
R:
Read only
[bit4 to bit0] ICR4 to ICR0
These bits, which are the interrupt level setting bits, specify the interrupt level of the corresponding
interrupt request.
If an interrupt level defined in this register is higher than the level mask value defined in the ILM register
of the CPU, the interrupt request is masked by the CPU.
These bits are initialized to "11111B" by reset.
Table 7.2-1 shows the correspondence between possible interrupt level setting bits and interrupt levels.
Table 7.2-1 Correspondence Between the Interrupt Level Setting Bits and Interrupt Levels
ICR4*
ICR3
ICR2
ICR1
ICR0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*: ICR4 is always 1; 0 cannot be written to this bit.
218
Interrupt level
0
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
System reservation
NMI
Maximum level that can be set
(High)
(Low)
Disables the interrupt
CHAPTER 7 INTERRUPT CONTROLLER
7.2.2
Hold Request Cancellation Request Level Setting
Register (HRCL)
The hold request cancellation request level setting register (HRCL) is a level setting
register used to generate a hold request cancellation request.
■ Bit Configuration of the Hold Request Cancellation Request Level Setting Register
(HRCL)
The following shows the bit configuration of the hold request cancellation request level setting register
(HRCL).
HRCL
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
000045H
MHALTI
-
-
LVL4
R
LVL3
R/W
LVL2
R/W
LVL1
R/W
LVL0
R/W
0--11111B
R/W
R/W: Readable/Writable
R:
Read only
[bit7] MHALTI
This bit is the DMA transfer disable bit controlled by an NMI request. An NMI request sets this bit to
"1". Write "0" to this bit to clear it. At the end of an NMI routine, clear this bit the same way it would be
cleared in a normal interrupt routine.
Note:
This series does not support NMI.
[bit4 to bit0] LVL4 to LVL0
These bits set the interrupt level used to issue a hold request cancellation request to the bus master.
If an interrupt request with a higher level than the level defined in the HRCL register occurs, a hold
request cancellation request is issued to the bus master.
The LVL4 bit is always "1"; "0" cannot be written to this bit.
219
CHAPTER 7 INTERRUPT CONTROLLER
7.3
Interrupt Controller Operation
This section describes the following items regarding operation of the interrupt
controller.
■ Priority Decision
The interrupt controller selects the interrupt source with the highest priority from among those that exist
simultaneously and outputs the interrupt level and the interrupt number of this source to the CPU.
The following shows the priority decision criteria for interrupt sources:
1. NMI
2. Source that meets the following conditions:
- Source with a value other than 31 as the interrupt level (31 means interrupts disabled)
- Source with the smallest value for the interrupt level
- Source with the smallest interrupt number that satisfies the both conditions above
If no interrupt source is selected according to the above decision criteria, 31 (11111B) is outputted as the
interrupt level. The interrupt number at this time is undefined.
Table 7.3-1 lists the relationship among the interrupt sources, interrupt number, and interrupt level.
Note:
This series does not support NMI.
220
CHAPTER 7 INTERRUPT CONTROLLER
Table 7.3-1 Relationship Among Interrupt Sources, Interrupt Numbers, and Interrupt Level. (1 / 3)
Interrupt number
Interrupt source
Reset
Mode vector
System reservation
System reservation
System reservation
System reservation
System reservation
Coprocessor absent trap
Coprocessor error trap
INTE instruction
System reservation
System reservation
Step trace trap
NMI demand (tool)
Undefined instruction exception
NMI demand
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
External interrupt 7
Reload timer 0
Reload timer 1
Reload timer 2
LIN-UART0 (reception completed)
LIN-UART0 (transmission completed)
LIN-UART1 (reception completed)
LIN-UART1 (transmission completed)
LIN-UART2 (reception completed)
LIN-UART2 (transmission completed)
CAN0
CAN1 / ICU6/ICU7
CAN2
LIN-UART3/UART5
(reception completed)
LIN-UART3/UART5
(transmission completed)
Interrupt
level
Offset
TBR default
address
Resource
No.
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
ICR16
ICR17
ICR18
ICR19
3FCH
3F8H
3F4H
3F0H
3ECH
3E8H
3E4H
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
3C0H
3BCH
3B8H
3B4H
3B0H
3ACH
3A8H
3A4H
3A0H
39CH
398H
394H
390H
38CH
388H
384H
380H
37CH
378H
374H
370H
000FFFFCH
000FFFF8H
000FFFF4H
000FFFF0H
000FFFECH
000FFFE8H
000FFFE4H
000FFFE0H
000FFFDCH
000FFFD8H
000FFFD4H
000FFFD0H
000FFFCCH
000FFFC8H
000FFFC4H
000FFFC0H
000FFFBCH
000FFFB8H
000FFFB4H
000FFFB0H
000FFFACH
000FFFA8H
000FFFA4H
000FFFA0H
000FFF9CH
000FFF98H
000FFF94H
000FFF90H
000FFF8CH
000FFF88H
000FFF84H
000FFF80H
000FFF7CH
000FFF78H
000FFF74H
000FFF70H
6
7
11
8
9
10
0
1
2
3
4
5
-
24
ICR20
36CH
000FFF6CH
-
25
ICR21
368H
000FFF68H
-
Decimal
Hexadecimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
15(FH) fixed
36
37
221
CHAPTER 7 INTERRUPT CONTROLLER
Table 7.3-1 Relationship Among Interrupt Sources, Interrupt Numbers, and Interrupt Level. (2 / 3)
Interrupt number
Interrupt source
LIN-UART4/UART6
(reception completed)
LIN-UART4/UART6
(transmission completed)
I2C0
2
I C1 / up/down counter 2
2
I C2
A/D converter
Real time clock
Up/down counter 1
Main oscillation stabilization wait timer
TBT overflow
PPG0/PPG1/PPG4/PPG5
PPG2/PPG3/PPG6/PPG7
PPG8/PPG9/PPGC/PPGD
PPGA/PPGB/PPGE/PPGF
Free-run timer 0/1
Free-run timer 2/3
Input capture 0 to 3
Input capture 4/5
Output compare 0 to 3 / UDC3
Output compare 4 to 7
Up/down counter 0
External interrupt 8 to 11
External interrupt 12 to 39
ROM correction interrupt
DMA
Delayed interrupt source bit
System reservation (used in REALOS)
System reservation (used in REALOS)
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
222
Interrupt
level
Offset
TBR default
address
Resource
No.
Decimal
Hexadecimal
38
26
ICR22
364H
000FFF64H
-
39
27
ICR23
360H
000FFF60H
-
40
28
ICR24
35CH
000FFF5CH
-
ICR25
358H
000FFF58H
-
000FFF54H
-
000FFF50H
000FFF4CH
000FFF48H
000FFF44H
000FFF40H
000FFF3CH
000FFF38H
000FFF34H
000FFF30H
000FFF2CH
000FFF28H
000FFF24H
000FFF20H
000FFF1CH
000FFF18H
000FFF14H
000FFF10H
000FFF0CH
000FFF08H
000FFF04H
000FFF00H
000FFEFCH
000FFEF8H
000FFEF4H
000FFEF0H
000FFEECH
000FFEE8H
000FFEE4H
000FFEE0H
000FFEDCH
000FFED8H
000FFED4H
000FFED0H
000FFECCH
14
-
41
29
42
2A
ICR26
354H
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
ICR27
ICR28
ICR29
ICR30
ICR31
ICR32
ICR33
ICR34
ICR35
ICR36
ICR37
ICR38
ICR39
ICR40
ICR41
ICR42
ICR43
ICR44
ICR45
ICR46
ICR47
-
350H
34CH
348H
344H
340H
33CH
338H
334H
330H
32CH
328H
324H
320H
31CH
318H
314H
310H
30CH
308H
304H
300H
2FCH
2F8H
2F4H
2F0H
2ECH
2E8H
2E4H
2E0H
2DCH
2D8H
2D4H
2D0H
2CCH
CHAPTER 7 INTERRUPT CONTROLLER
Table 7.3-1 Relationship Among Interrupt Sources, Interrupt Numbers, and Interrupt Level. (3 / 3)
Interrupt number
Interrupt source
Interrupt
level
Decimal
Hexadecimal
System reservation
System reservation
System reservation
77
78
79
4D
4E
4F
-
Used in INT instruction
80
to
255
50
to
FF
-
Offset
TBR default
address
Resource
No.
2C8H
2C4H
2C0H
2BCH
to
000H
000FFEC8H
000FFEC4H
000FFEC0H
000FFEBCH
to
000FFC00H
-
■ NMI (Non Maskable Interrupt)
An NMI (Non Maskable Interrupt) has the highest priority among the interrupt sources handled by this
module.
Thus, an NMI is always selected if it occurs at the same time as other interrupt sources.
● Generating an MMI
If an NMI occurs, the following information is reported to the CPU:
Interrupt level: 15(01111B)
Interrupt number: 15(0001111B)
● Detecting an NMI
The external interrupt and NMI module sets and detects an NMI. This module only generates an interrupt
level, interrupt number, and MHALTI in response to an NMI request.
● Preventing a DMA transfer occurring due to an NMI
If an NMI request occurs, the MHALTI bit of the HRCL register is set to "1" to prevent DMA transfer. To
clear the state preventing DMA transfer, clear the MHALTI bit to "0" at the end of the NMI routine.
Note:
This series does not support NMI.
■ Hold Request Cancellation Request (Hold Request Cancel Request)
For an interrupt with a higher priority to be processed during CPU hold (during DMA transfer), the device
that has generated the hold request must cancel the request. Set the interrupt level to be used as the criterion
of generating a cancellation request in the HRCL register.
● Generation criteria
If an interrupt source with a higher interrupt level than the level defined in the HRCL register occurs, a
hold request cancellation request is generated.
If the interrupt level of the HRCL register is greater than the interrupt level after a priority decision, a
cancellation request occurs.
If the interrupt level of the HRCL register is equal to or less than the interrupt level after a priority
decision, no cancellation request occurs.
223
CHAPTER 7 INTERRUPT CONTROLLER
Because the cancellation request remains valid, no DMA transfer occurs unless the interrupt source that has
caused the cancellation request is cleared. Be sure to clear the corresponding interrupt source.
If an NMI is used, the cancellation request is valid because the MHALTI bit of the HRCL register is set to
"1".
● Possible levels
Values that can be set in the HRCL register range from 10000B to 11111B, which is the same range as for
the ICR.
If this register is set to 11111B, a cancellation request is issued for all the interrupt levels. If this register is
set to 10000B, a cancellation request is issued only for an NMI.
Table 7.3-2 shows the settings of interrupt levels at which a hold request cancellation request occurs.
Table 7.3-2 Settings of Interrupt Levels at which Hold Request Cancellation Request
Occurs
HRCL register
Interrupt levels at which a cancellation request occurs
16
NMI only
17
NMI, Interrupt level 16
18
NMI, Interrupt level 16 and 17
31
NMI, Interrupt levels 16 to 30 [Initial value]
After a reset, since DMA transfer is not allowed at any interrupt level, no DMA transfer is performed if an
interrupt has occurred. Be sure to set the HRCL register to the necessary value.
■ Return from Standby Mode (Sleep/Stop)
This module implements a function that causes a return from stop mode if an interrupt request occurs. If at
least one interrupt request that includes NMI from the peripheral occurs (with an interrupt level other than
11111), a return request from stop mode is generated for the clock controller.
Since the priority decision unit restarts operation when a clock is supplied after returning from stop, the
CPU executes instructions until the result of the priority decision unit is obtained.
The same operation occurs after a return from the sleep state.
Registers in this module can be accessed even in the sleep state.
Notes:
• The device returns from stop mode if an NMI request is issued. However, set an NMI so that valid
input can be detected in the stop state.
• Provide an interrupt level of "11111B" in the corresponding peripheral control register for an
interrupt source that you do not want to cause return from stop or sleep.
• This series does not support NMI. There is a limitation between the instruction for the interruption
factor release and the instruction of RETI in "(5) Release of interruption factor the interruption routine".
See the section of CPU for the details.
224
CHAPTER 7 INTERRUPT CONTROLLER
■ Example of Using the Hold Request Cancellation Request Function (HRCR)
To allow the CPU to perform high-priority processing during DMA transfer, cancel a hold request for
DMA and clear the hold state. In this example, an interrupt is used to cancel a hold request to the DMA,
allowing the CPU to perform priority operations.
● Control Register
1. Hold request cancellation level setting register (HRCL): This module
If an interrupt with a higher interrupt level than the level defined in this register occurs, a hold request
cancellation request is issued to DMA. This register sets the level to be used as the criterion for this
purpose.
2. ICR: This module
This register sets a higher level than the level in the HRCL register for the ICR corresponding to the
interrupt source that will be used.
● Hardware Configuration
Figure 7.3-1 shows the flow of each signal for hold request.
Figure 7.3-1 Flow of Each Signal for Hold Request
This module
IRQ
Bus access request
MHALTI
I-UNIT
(ICR)
(HRCL)
DHREQ
DMA
B-UNIT
CPU
DHREQ : D-bus hold request
DHACK : D-bus hold acknowledge
IRQ : Interrupt request
MHALTI : Hold request cancellation
request
DHACK
● Hold Request Cancellation Request Sequence
Figure 7.3-2 shows the INTC-2 interrupt level that is higher than one set in the HRCL register.
Figure 7.3-2 Interrupt Level HRCL < ICR (LEVEL)
RUN
CPU
Bus access request
Bus hold
Interrupt processing
(1)
(2)
Bus hold (DMA transfer)
Example of interrupt
routine
(1)Interrupt source clear
DHREQ
DHACK
(2)RETI
IRQ
LEVEL
MHALTI
If an interrupt request occurs, the interrupt level changes. If the interrupt level is higher than the level
defined in the HRCL register, MHALT1 becomes active for DMA. This causes DMA to cancel an access
request and the CPU to return from the hold state to perform the interrupt processing.
225
CHAPTER 7 INTERRUPT CONTROLLER
Figure 7.3-3 shows the INTC-3 interrupt level for multiple interrupts.
Figure 7.3-3 Example of INTC-3 Interrupt Level HRCL < ICR (Interrupt I) < ICR (Interrupt II)
RUN
Bus hold
CPU
Interrupt I
(3)
Interrupt
processing II
(4)
Interrupt
processing I
(1)
Bus hold
(DMA transfer)
(2)
Bus access request
DHREQ
DHACK
IRQ1
IRQ2
LEVEL
MHALTI
[Example of Interrupt Routine]
(1), (3) Interrupt source clear
to
(2), (4) RETI
In the above example, while Interrupt Routine I is being executed, an interrupt with a higher priority
occurs.
While the interrupt with a higher level than the level in the HRCL register remains, DHREQ is low.
Note:
Be especially careful about the relationship between interrupt levels defined in the HRCL register
and ICR.
226
CHAPTER 8
EXTERNAL INTERRUPT
This chapter describes the overview of the external
interrupt, the configuration and functions of registers,
and operation of the external interrupt.
8.1 Overview of the External Interrupt
8.2 External Interrupt Registers
8.3 Operation of the External Interrupt
227
CHAPTER 8 EXTERNAL INTERRUPT
8.1
Overview of the External Interrupt
The external interrupt controller is a block that controls external interrupt requests
input to INT pin.
"H" level, "L" level, rising edge, or falling edge can be selected as the level of a request
to be detected.
• "H" level
• "L" level
• Rising edge
• Falling edge
■ External Interrupt Registers
The following shows the registers used by the external interrupt.
External interrupt enable register
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
(ENIR)
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
External interrupt factor register
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
(EIRR)
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
Request level setting register
(EVLR)
■ Block Diagram of the External Interrupt
Figure 8.1-1 is a block diagram of the external interrupt.
Figure 8.1-1 Block Diagram of the External Interrupt
R-bus
8
Interrupt
request
Interrupt enable register
16
8
16
228
Gate
Factor F/F
Interrupt source register
Request level setting register
Edge detection
circuit
16
INT0 to
INT15
CHAPTER 8 EXTERNAL INTERRUPT
8.2
External Interrupt Registers
This section describes the configuration and functions of the registers used by the
external interrupt.
■ External Interrupt Registers
The register of the external interruption control part has the following three types.
• Interrupt enable register (ENIR)
• External interrupt factor register (EIRR)
• External interrupt request level setting register (ELVR)
229
CHAPTER 8 EXTERNAL INTERRUPT
8.2.1
Interrupt Enable Register (ENIR)
The interrupt enable register (ENIR) controls the masking of external interrupt request
output.
■ Bit Configuration of the Interrupt Enable Register (ENIR)
The following shows the bit configuration of the interrupt enable register (ENIR).
ENIR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ENIR0: 000041H
ENIR1: 0000D1H
EN7
R/W
EN6
R/W
EN5
R/W
EN4
R/W
EN3
R/W
EN2
R/W
EN1
R/W
EN0
R/W
00000000B
R/W: Readable/Writable
Output for an interrupt request is enabled based on the bit in this register to which "1" has been written
(INT0 enable is controlled by EN0), after which the interrupt request is outputted to the interrupt controller.
The pin corresponding to the bit to which "0" is written holds the interrupt source but does not generate a
request to the interrupt controller.
Clear the corresponding external interrupt factor bit (EIRR:ER) immediately before the external interrupt is
enabled (ENIR:EN=1).
In stop mode, input is enabled with external interrupts enabled (ENIR:EN=1). With any other setting, the
input is masked and the "L" level is transmitted to the inside.
Note:
Clear the corresponding external interrupt factor flag bit (EIRR:ER) immediately before the external
interrupt is enabled (ENIR:EN=1).
230
CHAPTER 8 EXTERNAL INTERRUPT
8.2.2
External Interrupt Factor Register (EIRR)
The external interrupt factor register (EIRR) indicates the presence or absence of a
corresponding external interrupt request when reading from this register and clears the
contents of the flip-flop that indicates this interrupt request when writing to this
register.
■ External Interrupt Factor Register (EIRR)
The following shows the bit configuration of the external interrupt factor register (EIRR).
EIRR
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
EIRR0: 000040H
EIRR1: 0000D0H
ER7
R/W
ER6
R/W
ER5
R/W
ER4
R/W
ER3
R/W
ER2
R/W
ER1
R/W
ER0
R/W
00000000B
R/W: Readable/Writable
When this EIRR register is read, the operation is different depending on the value below.
If the read value of this EIRR register is "1", there is an external interrupt request at the pin corresponding
to this bit.
Write "0" to this register to clear the request flip-flop of the corresponding bit.
Writing "1" is invalid.
For a read by a read modify write instruction, "1" is read.
• The value of the external interrupt factor bit (EIRR:ER) is enabled only when the corresponding
external interrupt enable bit (ENIR:EN) is set to "1". For the state that the external interrupt is disabled
(ENIR:EN=0), the external interrupt enable bit may be set whether the external interrupt factor is
enabled or not.
• Clear the corresponding external interrupt factor bit (EIRR:ER) immediately before the external
interrupt is enabled (ENIR:EN=1).
Notes:
• The value of the external interrupt request flag bit (EIRR:ER) is enabled only when the
corresponding external interrupt request enable bit (ENIR:EN) is set to "1". In the state where
external interrupt is disabled (ENIR:EN=0), the external request flag bit may be set regardless of
whether an external interrupt factor exists or not.
• Clear the corresponding external interrupt factor flag bit (EIRR:ER) immediately before the
external interrupt is enabled (ENIR:EN=1).
231
CHAPTER 8 EXTERNAL INTERRUPT
8.2.3
External Interrupt Request Level Setting Register (ELVR)
The external interrupt request level setting register (ELVR) specifies how a request is
detected.
■ Bit Configuration of the External Interrupt Request Level Setting Register (ELVR)
The following shows the bit configuration of the external interrupt request level setting register (ELVR).
ELVR
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
ELVR0: 000042H
ELVR1: 0000D2H
LB7
R/W
LA7
R/W
LB6
R/W
LA6
R/W
LB5
R/W
LA5
R/W
LB4
R/W
LA4
R/W
00000000B
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ELVR0: 000043H
ELVR1: 0000D3H
LB3
R/W
LA3
R/W
LB2
R/W
LA2
R/W
LB1
R/W
LA1
R/W
LB0
R/W
LA0
R/W
00000000B
R/W: Readable/Writable
In ELVR, two bits each are assigned to interrupt channel, which results in the settings shown in Table 8.2-1.
Even though the bits of the EIRR are cleared while the request input is level-base operation, the pertinent
bits are set again as long as the input is at the level that is active.
Table 8.2-1 Assignment of ELVR
LBxLAx
Operation
00
There is a demand at L level [initial value]
01
There is a demand at H level
10
A rising edge indicates the existence of a request.
11
A falling edge indicates the existence of a request.
The pin that can be inputted in the stop mode is used in the stop mode. For the pin cut off the input in the
stop mode, the input signal is masked, "L" level is internally transferred to the pin when CMOS/
Automotive is selected and "H" level when TTL is selected. Thus, ERn bit in the external interrupt factor
register (EIRR) may be set to "1" by setting of the external interrupt setting register (ELVR) regardless of
input from the outside.
232
CHAPTER 8 EXTERNAL INTERRUPT
8.3
Operation of the External Interrupt
This section explains operation of the external interruption control part.
■ Operation of an External Interrupt
If, after a request level and an enable register are defined, a request defined in the ELVR register is inputted
to the corresponding pin, this module generates an interrupt request signal to the interrupt controller. For
simultaneous interrupt requests from resources, the interrupt controller determines the interrupt request
with the highest priority and generates an interrupt for it.
Figure 8.3-1 shows external interrupt operation.
Figure 8.3-1 External Interrupt Operation
Resource
ELVR
Request
IL
ICR y y
EIRR
ENIR
CPU
Interrupt controller
External interrupt
CMP
CMP
ICR X X
ILM
Factor
■ Operation Procedure of External Interrupt
Set up a register located inside the external interrupt controller as follows:
1. Set that general-purpose I/O port as an input port which also serves as a pin to be used as an external
interrupt input.
2. Set the relevant bit in the interrupt enable register (ENIR) to disable interrupts.
3. Set the relevant bit in the external interrupt request level setting register (ELVR).
4. Read the external interrupt request level setting register (ELVR).
5. Clear the relevant bit in the external interrupt factor register (EIRR).
6. Set the relevant bit in the interrupt enable register (ENIR) to enable interrupts.
In steps 5 and 6, data can be written simultaneously in 16 bits.
Before setting a register in this module, you must disable the enable register. In addition, before enabling
the enable register, you must clear the interrupt factor register. This procedure is required to prevent an
interrupt source from occurring by mistake while a register is being set or an interrupt is enabled.
233
CHAPTER 8 EXTERNAL INTERRUPT
■ External Interrupt Request Level
If the request level is an edge request, a pulse width of at least three machine cycles (peripheral clock
machine cycles) is required to detect an edge.
If the request input level is a level setting, a pulse width of at least three machine cycles is required. In
addition, interrupt requests to the interrupt controller keep occurring even if the external interrupt factor
register (ENIR) is cleared as long as the interrupt input pin keeps holding an active level.
If the request input level is a level setting and request input arrives from outside and is then cancelled, the
request to the interrupt controller remains active because a source holding circuit exists internally.
The interrupt factor register must be cleared to cancel a request to the interrupt controller.
Figure 8.3-2 shows clearing of the source holding circuit when a level is set.
Figure 8.3-2 Clearing the Source Holding Circuit When a Level is Set
Interrupt input
Level
detection
Factor F/F
(source holding circuit)
Enable gate
Interrupt controller
Continuing to retain factors as far as it's not cleared
Figure 8.3-3 shows an interrupt source and an interrupt request to the interrupt controller when interrupts
are enabled.
Figure 8.3-3 Interrupt Source and Interrupt Request to Interrupt Controller When Interrupts are Enabled
"H" level
Interrupt input
Interrupt request to
interrupt controller
Clear of factor F/F makes this inactive.
234
CHAPTER 8 EXTERNAL INTERRUPT
■ Notes If Restoring from STOP Status Performed Using an External Interrupt
During STOP status, external interrupt signals that are first entered to the INT pin are entered
asynchronously, to enable recovery from the STOP status. The period from that STOP being released to the
passage of oscillation stabilization wait time, however, there is a period during which other external
interrupt signal inputs cannot be identified (Period b+c+d for Figure 8.3-4). To synchronize external input
signals after the STOP has been released with the internal clock, while the clock is not stable, interrupt
sources cannot be stored.
If sending external interrupt inputs after the STOP has been released, input external interrupt signals after
the oscillation stabilization wait time has elapsed.
Figure 8.3-4 Recovery Operation Sequence Using External Interrupts from STOP Status
INT1
INT0
Internal
STOP
Regulator
12µs
"H"
"L"
Internal
operation
(RUN)
Implement command (RUN)
X0
Internal
clock
Interrupt flag clear
INTR0
INTE0
"1" (Set to enable before switching to STOP mode)
INTR1
INTE1
"1" (Set to enable before switching to STOP mode)
(e)RUN
(a) STOP (b) Regulator stabilization wait time (d) Oscillation stabilization wait time
(c) Oscillator oscillation time
235
CHAPTER 8 EXTERNAL INTERRUPT
■ Recovery Operations from STOP Status
The STOP recovery operation using external interrupts from existing circuits is performed as described
below.
● Processing before transiting to STOP
Settings of External Interrupt Path
An external interrupt input path for canceling STOP status needs to be set. before the device transits to
STOP status. These configuration are made using the PFR (Port Function Register). Under normal
conditions (i.e., any status other than STOP), the interrupt input path is permitted, so there is no need for
special recognition. In STOP status, however, the input path is controlled by the PFR register value.
External Interrupt Inputs
If recovering from STOP status, the external interrupt signals send an input signal asynchronously.
When this interrupt signal is enabled, the internal STOP signal is immediately turned OFF. At the same
time, the external interrupt circuit is switched so as to synchronize other level interrupt inputs.
● Regulator Stabilization Wait Time
When the internal STOP signal is turned OFF, the switching operation from the regulator on STOP to
the regulator on RUN will start. If the internal operations start before the voltage output of the regulator
on RUN has stabilized, stabilization wait time for the internal outputs voltage will be required due to
operational instability, and stabilization wait time for the internal outputs voltage is secured. During this
time, the clock will stop.
● Oscillator Oscillation Time
After the regulator stabilization wait time has ended, the clock will start to oscillate. The oscillator
oscillation time depends on the oscillator used.
● Oscillation Stabilization Wait Time
After the oscillator oscillation time, an oscillation stabilization wait time is taken inside the device. The
oscillation stabilization wait time is specified by bits OS1 and OS0 on the standby control register. After
the oscillation stabilization wait time has ended, the internal clock is supplied, and in addition to the
activation of interrupt instruction operations from the external interrupt, it also becomes possible to
receive external interrupt sources other than the recovery from STOP request.
236
CHAPTER 9
REALOS-RELATED
HARDWARE
REALOS-related hardware is used by the real-time OS.
Therefore, when REALOS is used, the hardware cannot
be used with the user program.
9.1 Delayed Interrupt Module
9.2 Bit Search Module
237
CHAPTER 9 REALOS-RELATED HARDWARE
9.1
Delayed Interrupt Module
This section describes the overview, register configuration/functions, and operation of
the delayed interrupt module.
■ Overview of the Delayed Interrupt Module
The delayed interrupt module generates an interrupt for switching tasks. Usage of this module allows a
software program to generate or clear an interrupt request for the CPU.
238
CHAPTER 9 REALOS-RELATED HARDWARE
9.1.1
Overview of the Delayed Interrupt Module
This section describes the register list, details, and operation of the delayed interrupt
module.
■ Register List of the Delayed Interrupt Module
Register list of the delayed interrupt module is as follows.
DICR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
000044H
-
-
-
-
-
-
-
DLYI
R/W
R/W: Readable/Writable
■ Block Diagram of the Delayed Interrupt Module
Figure 9.1-1 shows a block diagram of the delayed interrupt module.
Figure 9.1-1 Block Diagram of the Delayed Interrupt Module
R-bus
DLYI
Interrupt request
239
CHAPTER 9 REALOS-RELATED HARDWARE
9.1.2
Delayed Interrupt Module Registers
This section describes the configuration and functions of the registers used by the
delayed interrupt module.
■ DICR (Delayed Interrupt Module Registers)
The delayed interrupt module register (DICR) controls the delayed interrupt.
The following shows the bit configuration of the delayed interrupt module register (DICR).
DICR
Address
bit7
000044H
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-------0B
-
-
-
-
-
-
-
DLYI
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/Writable
[bit0] DLYI
DLYI
Description
0
No release and request of delayed interrupt factor [initial value]
1
Generated delayed interrupt factor
This bit controls generating and releasing the corresponding interrupt factors.
240
CHAPTER 9 REALOS-RELATED HARDWARE
9.1.3
Operation of the Delayed Interrupt Module
A delayed interrupt is an interrupt generated for switching tasks. Use this function to
allow a software program to generate an interrupt request for the CPU or to clear an
interrupt request.
■ Interrupt Number
A delayed interrupt is assigned to the interrupt source corresponding to the largest interrupt number.
On this product, a delayed interrupt is assigned to interrupt number 63 (3FH).
■ DLYI Bit of DICR
Write "1" to this bit to generate a delayed interrupt source. Write "0" to it to clear a delayed interrupt
source.
This bit is the same as the interrupt source flag for a normal interrupt. Therefore, clear this bit and switch
tasks in the interrupt routine.
241
CHAPTER 9 REALOS-RELATED HARDWARE
9.2
Bit Search Module
This section describes the overview of the bit search module, the configuration and
functions of its registers, and bit search module operation.
■ Overview of the Bit Search Module
The bit search module searches for "0", "1", or any points of change for data written to the input register
and then returns the detected bit locations.
242
CHAPTER 9 REALOS-RELATED HARDWARE
9.2.1
Overview of the Bit Search Module
This section describes the configuration and functions of registers used by the bit
search module.
■ Register List of the Bit Search Module
Following is the register list of the bit search module.
bit31
bit0
Address: 0003F0H
BSD0
0 data register for detection
Address: 0003F4H
BSD1
1 data register for detection
Address: 0003F8H
BSDC
Data register for checking changes
Address: 0003FCH
BSRR
Detection result register
■ Block Diagram of the Bit Search Module
Figure 9.2-1 shows a block diagram of the bit search module.
Figure 9.2-1 Block Diagram of the Bit Search Module
D-bus
Input latch
Address decoder
Detection
mode
1 detection data
Bit search circuit
Detection result
243
CHAPTER 9 REALOS-RELATED HARDWARE
9.2.2
Bit Search Module Registers
This section describes the configuration and functions of the bit search module
registers.
■ 0 Detection Data Register (BSD0)
0 detection is performed for written value.
Shown below is the configuration of the 0 detection data register (BSD0).
bit31
Address:
bit0
0003F0H
Read/write → W
Initial value → Undefined
The initial value after a reset is undefined. The read value is undefined.
Use a 32-bit length data transfer instruction for data transfer. (Do not use 8-bit or 16-bit length data transfer
instructions.)
■ 1 Detection Data Register (BSD1)
Shown below is the configuration of the 1 detection data register (BSD1).
bit31
Address:
bit0
0003F4H
Read/write → R/W
Initial value → Undefined
Use a 32-bit length data transfer instruction for data transfer. (Do not use 8-bit or 16-bit length data transfer
instructions.)
• Writing:
"1" detection is performed for the written data.
• Reading:
Saved data of the internal state in the bit search module is read. This register is used to save and restore
to the original state when the bit search module is used by, for example, an interrupt handler.
Even though data is written to the 0 detection, change point detection, or data register, data can be saved
and restored only by using the 1 detection data register. The initial value after a reset is undefined.
244
CHAPTER 9 REALOS-RELATED HARDWARE
■ Change Point Detection Data Register (BSDC)
Point of change is detected in the written value.
Shown below is the configuration of the change point detection data register (BSDC).
bit31
Address:
bit0
0003F8H
Read/write → W
Initial value → Undefined
The initial value after a reset is undefined.
The read value is undefined.
Use a 32-bit length data transfer instruction for data transfer. (Do not use 8-bit or 16-bit length data transfer
instructions.)
■ Detection Result Register (BSRR)
The result of 0 detection, 1 detection, or change point detection is read.
Which detection result is to be read is determined by the data register that has been written to last.
Shown below is the configuration of the detection result register (BSRR).
bit31
Address:
bit0
0003FCH
Read/write → R
Initial value → Undefined
245
CHAPTER 9 REALOS-RELATED HARDWARE
9.2.3
Bit Search Module Operation
This section explains the operation of bit search module.
■ 0 Detection
The bit search module scans data written to the 0 detection data register from the MSB to the LSB and
returns the location where the first "0" is detected.
The detection result can be obtained by reading the detection result register. The relationship between the
detected location and the return value is given in Table 9.2-1.
If a "0" is not found (that is, the value is FFFFFFFFH), 32 is returned as the search result.
[Execution example]
Write data
Read value (decimal)
11111111111111111111000000000000B (FFFFF000H)
→
20
11111000010010011110000010101010B (F849E0AAH)
→
5
10000000000000101010101010101010B (8002AAAAH)
→
1
11111111111111111111111111111111B (FFFFFFFFH)
→
32
■ 1 Detection
The bit search module scans data written to the 1 detection data register from the MSB to the LSB and
returns the location where the first "1" is detected.
The detection result can be obtained by reading the detection result register. The relationship between the
detected location and the return value is given in Table 9.2-1.
If a "1" is not found (that is, the value is 00000000H), 32 is returned as the search result.
[Execution example]
Write data
246
Read value (decimal)
00100000000000000000000000000000B (20000000H)
→
2
00000001001000110100010101100111B (01234567H)
→
7
00000000000000111111111111111111B (0003FFFFH)
→
14
00000000000000000000000000000001B (00000001H)
→
31
00000000000000000000000000000000B (00000000H)
→
32
CHAPTER 9 REALOS-RELATED HARDWARE
■ Change Point Detection
The bit search module scans data written to the change point detection data register from bit30 to the LSB
for comparison with the MSB value.
The first location where a value that is different from that of the MSB is detected is returned. The detection
result can be obtained by reading the detection result register.
The relationship between the detected location and the return value is given in Table 9.2-1.
If a change point is not detected, 32 is returned. In change point detection, "0" is never returned as a result.
[Execution example]
Write data
Read value (decimal)
00100000000000000000000000000000B (20000000H)
→
2
00000001001000110100010101100111B (01234567H)
→
7
00000000000000111111111111111111B (0003FFFFH)
→
14
00000000000000000000000000000001B (00000001H)
→
31
00000000000000000000000000000000B (00000000H)
→
32
11111111111111111111000000000000B (FFFFF000H)
→
20
11111000010010011110000010101010B (F849E0AAH)
→
5
10000000000000101010101010101010B (8002AAAAH)
→
1
11111111111111111111111111111111B (FFFFFFFFH)
→
32
Table 9.2-1 shows the bit locations and return values (decimal).
Table 9.2-1 Bit Locations and Return Values (Decimal)
Detected bit
location
Return
value
Detected bit
location
Return Detected bit
value
location
Return
value
Detected bit
location
Return
value
31
0
23
8
15
16
7
24
30
1
22
9
14
17
6
25
29
2
21
10
13
18
5
26
28
3
20
11
12
19
4
27
27
4
19
12
11
20
3
28
26
5
18
13
10
21
2
29
25
6
17
14
9
22
1
30
24
7
16
15
8
23
0
31
Does not exist
32
247
CHAPTER 9 REALOS-RELATED HARDWARE
■ Save/Restore Processing
If it is necessary to save and restore the internal state of the bit search module, such as when the bit search
module is used in an interrupt handler, use the following procedure:
1. Read the 1 detection data register and save its contents (save).
2. Use the bit search module.
3. Write the data saved in 1) to the 1 detection data register (restore).
With the above operation, the value obtained when the detection result register is read the next time
corresponds to the value written to the bit search module before 1).
If the data register written to last is the 0 detection or change point detection register, the value is restored
correctly with the above procedure.
248
CHAPTER 10
DMA CONTROLLER (DMAC)
This chapter describes the overview of the DMA
controller (DMAC), the configuration and functions of
registers, and DMAC operation.
10.1 Overview of the DMA Controller (DMAC)
10.2 Register Details Explanation
10.3 DMA Controller Operation
10.4 Operation Flowcharts
10.5 Data Path
249
CHAPTER 10 DMA CONTROLLER (DMAC)
10.1
Overview of the DMA Controller (DMAC)
This module is used to implement DMA (Direct Memory Access) transfer in FR family
devices. This module can be used to increase system performance by using DMA
transfer to perform various types of data transfer at high speed without going via the
CPU.
■ Hardware Configuration of DMAC
The module consists of the following main components.
• Five independent DMA channels
• 5ch independent access control circuit
• 20-bit address registers (reload specifiable, ch.0 to ch.3)
• 24-bit address registers (reload specifiable, ch.4)
• 16-bit rotation count register (reload specifiable, one register for each channel)
• 4-bit block count registers (one per channel)
• 2-cycle transfer
■ Main Functions of DMAC
The following are the main functions related to data transfer by the DMA controller (DMAC):
● Independent data transfer can be performed for multiple channels (5ch)
• Priority (ch.0>ch.1>ch.2>ch.3>ch.4.)
• The priority can be rotated between ch.0 and ch.1.
• DMAC startup factor
- Request from internal peripheral (uses interrupt requests, including the external interrupts)
- Software request (register write)
• Transfer mode
- Burst transfer, step transfer, and block transfer
- Addressing mode: 20-bit (24-bit) addressing (increment/decrement/fixed: the address increment/
decrement range is fixed to ± 1, 2, 4)
- Data types: Byte, halfword, and word length
- Selectable single-shot or reload
250
CHAPTER 10 DMA CONTROLLER (DMAC)
■ DMA Controller (DMAC) Registers
Figure 10.1-1 shows the registers used by the DMA controller (DMAC).
Figure 10.1-1 DMA Controller (DMAC) Registers
ch.0 control/status register A
at RST
DMACA0
ch.0 control/status register B
DMACB0
000204H
00000000
[R/W]
ch.1 control/status register A
DMACA1
000208H
00000000
[R/W]
ch.1 control/status register B
DMACB1
00020CH
00000000
[R/W]
ch.2 control/status register A
DMACA2
000210H
00000000
[R/W]
ch.2 control/status register B
DMACB2
000214H
00000000
[R/W]
ch.3 control/status register A
DMACA3
000218H
00000000
[R/W]
ch.3 control/status register B
DMACB3
00021CH
00000000
[R/W]
ch.4 control/status register A
DMACA4
000220H
00000000
[R/W]
ch.4 control/status register B
DMACB4
000224H
00000000
[R/W]
DMACR
000240H
00000000
[R/W]
ch.0 transfer source address register
DMASA0
001000H
00000000
[R/W]
ch.0 transfer source address register
DMADA0
001004H
00000000
[R/W]
ch.1 transfer source address register
DMASA1
001008H
00000000
[R/W]
ch.1 transfer source address register
DMADA1
00100CH
00000000
[R/W]
ch.2 transfer source address register
DMASA2
001010H
00000000
[R/W]
ch.2 transfer source address register
DMADA2
001014H
00000000
[R/W]
ch.3 transfer source address register
DMASA3
001018H
00000000
[R/W]
ch.3 transfer source address register
DMADA3
00101CH
00000000
[R/W]
ch.4 transfer source address register
DMASA4
001020H
00000000
[R/W]
ch.4 transfer source address register
DMADA4
001024H
00000000
[R/W]
Overall control register A
Address (bit) 31
000200H
24 23
16 15
87
0
00000000
[R/W]
251
CHAPTER 10 DMA CONTROLLER (DMAC)
■ Block Diagram of DMA Controller (DMAC)
Figure 10.1-2 is a block diagram of the DMA controller (DMAC).
Figure 10.1-2 Block Diagram of the DMA Controller (DMAC)
DTC2 step register DTCR
Counter
DSS[3:0]
Buffer
Selector
Read/write
control
Counter buffer
Selector
Selector
Access
Address
Selector
ERIR,EDIR
To interrupt controller
Peripheral interrupt clear
BLK register
Status
transfer
circuit
TYPE.MOD,
WS
DDN0 register
DSAD2 step register
SADM, SASZ[7:0] SADR
DDAD2 step register
DADM,DASZ[7:0] DADR
Write back
Write back
252
Priority level
circuit
DMA control
Counter buffer
DDN0
Address counter
To bus
controller
Bus control block
Read
Write
Peripheral startup request/stop input
X-bus
Selector
DMA startup
factor select
circuit &
request
reception
control
Bus control block
Buffer
Write back
Counter
DMA transfer request
to bus controller
IRQ[4:0]
MCLREQ
CHAPTER 10 DMA CONTROLLER (DMAC)
10.2
Register Details Explanation
This section explains details of each register of DMAC.
■ Notes on Setting Registers
Some bits in the DMAC may only be set when the DMA is halted. If set during operation (transfer), correct
operation cannot be guaranteed.
An asterisk ( * ) indicates bits that will affect operation if set during DMA transfer. Rewrite this bit while
DMAC transfer is stopped (start is disabled or temporarily stopped).
Values set while DMA transfer start is disabled (DMACR:DMAE=0 or DMACA:DENB=0) become active
when DMA start is re-enabled.
Values set while DMA transfer is paused (DMACR:DMAH(3:0) ≠ 0000 or DMACA:PAUS=1) become
active when DMA is restarted.
253
CHAPTER 10 DMA CONTROLLER (DMAC)
10.2.1
Control/Status Registers A (DMACA0 to DMACA4)
Control/status registers A (DMACA0 to DMACA4) control the operation of each channel.
There is a separate register for each channel.
■ Bit Function of DMACA0 to DMACA4
Each bit function of DMACA0 to DMACA4 is indicated as follows.
bit
31
30
29
28
27
DENB PAUS STRG
bit
15
14
13
26
25
24
23
11
10
21
20
19
Reserved
IS[4:0]
11
22
9
8
7
6
5
18
17
16
BLK[3:0]
4
3
2
1
0
DTC[15:0]
Initial value: 00000000_00000000_00000000_00000000B
[bit31] DENB (Dma ENaBle): DMA operation enable bit
Enables or disables DMA transfer start for each transfer channel.
Once a channel is enabled, DMA transfer starts when a transfer request is received. All transfer requests
that are generated for a deactivated channel are disabled.
When the transfer on an activated channel reaches the specified count, this bit is set to "0" and transfer
stops.
The transfer can be forced to stop by writing "0" to this bit. Be sure to stop a transfer forcibly ("0" write)
only after temporarily stopping DMA using the PAUS bit [bit30:DMACA]. If the transfer is forced to
stop without first temporarily stopping DMA, DMA stops but the transferred data cannot be guaranteed.
Check whether DMA is stopped using the DSS2 to DSS0 bits [bit18 to bit16:DMACB].
DENB
Function
0
Disables operation of DMA on the corresponding channel [initial value]
1
Enables operation of DMA on the corresponding channel.
• After a reset or when a halt request is received: Initialized to "0".
• The read/write is possible.
If the operation of all channels is disabled by bit31 (DMAE bit) of the DMAC all-channel control register
(DMACR), writing "1" to this bit is disabled and the stopped state is maintained. If the operation is
disabled by the above bit while it is enabled by this bit, "0" is written to this bit and the transfer is
stopped (forced stop).
254
CHAPTER 10 DMA CONTROLLER (DMAC)
[bit30] PAUS (PAUSe): Temporary stop instruction
Pauses DMA transfer for the corresponding channel.If this bit is set, DMA transfer is not performed
before this bit is cleared (While DMA is stopped, the DSS bits are 1xx).
If this bit is set before DMA is enabled, DMA remains paused.
New transfer requests that occur while this bit is set are accepted, but no transfer starts before this bit is
cleared (See "10.3.10 Transfer Request Acceptance and Transfer").
PAUS
Function
0
Enables operation of the corresponding channel DMA [initial value]
1
Temporarily stops DMA on the corresponding channel.
• When reset: Initialized to "0".
• The read/write is possible.
[bit29] STRG (Software TRiGger): Transfer request
Generates a DMA transfer request for the corresponding channel. Writing "1" to this bit generates a
transfer request as soon as the register write completes and starts the transfer on the corresponding
channel.
However, if the corresponding channel is not enabled, writing to this bit is ignored.
Reference:
If a transfer request is set via this bit at the same time as transfer is enabled by writing the DMAE bit,
the transfer request is valid and transfer starts. If this bit is written to at the same time as writing "1"
to the PAUS bit, the transfer request is valid but DMA transfer does not start until the PAUS bit is
cleared to "0".
STRG
Function
0
Disabled [initial value]
1
DMA starting request
• When reset: Initialized to "0".
• Reading always returns "0".
• Only writing "1" is meaningful. Writing "0" has no effect on the operation.
255
CHAPTER 10 DMA CONTROLLER (DMAC)
[bit28 to bit24] IS4 to IS0 (Input Select): Transfer source selection
These bits select the source of a transfer request as shown in table. However, the software transfer request
triggered by the STRG bit remains available regardless of this setting.
IS
Function
00000
Hardware
00001
Setting disabled
01111
Setting disabled
10000
LIN-UART0 (reception completed)
10001
LIN-UART1 (reception completed)
10010
LIN-UART2 (reception completed)
10011
LIN-UART0 (transmission completed)
10100
LIN-UART1 (transmission completed)
10101
LIN-UART2 (transmission completed)
10110
External interrupt 0
10111
External interrupt 1
11000
Reload timer 0
11001
Reload timer 1
11010
Reload timer 2
11011
None
11100
None
11101
None
11110
A/D converter
11111
None
• When reset: Initialized to "00000B".
• The read/write is possible.
If DMA start resulting from an interrupt from a peripheral function is set (IS=1xxxxB), disable interrupts
from the selected peripheral function with the ICR register.
When the DMA transfer is started by the software transfer request with the DMA start by the interrupt of
the peripheral function set, the factor is cleared to corresponding peripherals after transfer ends.
Therefore, please do not start by the software transfer request, when the DMA transfer by the interrupt of
the peripheral function was set. Because there is a possibility of clearing an original transfer request.
256
CHAPTER 10 DMA CONTROLLER (DMAC)
[bit23 to bit20](Reserved): Reserved bits
Read value is fixed to "0000B". Writing has no effect.
[bit19 to bit16] BLK3 to BLK0 (BLocK size): Block size specification
Specifies the size for block transfer on the corresponding channel. The value specified by these bits
becomes the number of words in one transfer unit (more exactly, the repetition count of the data width
setting).
Always set "01H" (size 1) when not performing block transfer.
BLK
XXXX
Function
Block size of the corresponding channel
• When reset: Initialized to "0000B".
• The read/write is possible.
• If "0" is specified for all bits, the block size becomes 16 words.
• Reading always returns the block size (reload value).
[bit15 to bit0] DTC (DMA Terminal Count register): Transfer count register
This register stores the number of transfers performed. Each register consists of 16-bit length.
All registers have a dedicated reload register. On channels that allow the transfer count register to be
reloaded, the initial value is automatically reloaded to the register when the transfer completes.
DTC
XXXX
Function
Transfer count for the corresponding channel
When DMA transfer starts, the data in this register is copied to the counter buffer in the dedicated DMA
transfer counter and the value decremented by one after each transfer. When DMA transfer completes,
the value of the counter buffer is written back to this register and the DMA operation ends. Thus, the
transfer count value during DMA operation cannot be read.
• When reset: Initialized to "00000000_00000000B".
• The read/write is possible. Always access DTC using halfword length or word length.
• Reading the register returns the counter value. You cannot read the reload value.
257
CHAPTER 10 DMA CONTROLLER (DMAC)
10.2.2
Control/Status Registers B (DMACB0 to DMACB4)
Control/status registers B (DMACB0 to DMACB4) control the operation of each DMACB
channel and exist independently for each channel.
■ Bit Function of Control/Status Register B (DMACB0 to DMACB4)
Each bit function of DMACB0 to DMACB4 are following.
bit
bit
31
30
29
28
27
26
TYPE[1:0]
MOD[1:0]
WS[1:0]
15
13
11
14
11
25
24
23
22
21
20
19
18
9
8
7
6
5
SASZ[7:0]
4
3
16
DSS[2:0]
SADM DADM DTCR SADR DADR ERIE EDIE
10
17
2
1
0
DASZ[7:0]
Initial value: 00000000_00000000_00000000_00000000B
[bit31, bit30] TYPE (TYPE): Transfer type setting
These bits specify the operation type of the corresponding channel as described below.
2-cycle transfer mode:
In this mode, the transfer source address (DMASA) and transfer destination address (DMADA) are set
and transfer is performed by repeating the read operation and write operation for the number of times
specified by the transfer count.
TYPE
Function
00
2-cycle transfer [initial value]
01
Setting disabled
10
Setting disabled
11
Setting disabled
• When reset: Initialized to "00B".
• The read/write is possible.
• Always set this bit to "00B".
[bit29, bit28] MOD (MODe): Transfer mode setting
The operating mode of the correspondence channel is set as follows.
MOD
Function
00
Block/step transfer mode [initial value]
01
Burst transfer mode
10
Setting disabled
11
Setting disabled
• When reset: Initialized to "00B".
• The read/write is possible.
258
CHAPTER 10 DMA CONTROLLER (DMAC)
[bit27, bit26] WS (Word Size): Transfer data width selection
Sets the transfer data width for the corresponding channel as follows. DMA performs the specified
number of transfers using the data width specified in this register.
WS
Function
00
Byte-width transfer [initial value]
01
Halfword-width transfer
10
Word-width transfer
11
Setting disabled
• When reset: Initialized to "00B".
• The read/write is possible.
[bit25] SADM (Source-ADdr. Count-Mode select):
Transfer source address count mode specification
Specifies what to do to the transfer source address for the corresponding channel after each transfer.
An address increment is added or an address decrement is subtracted after each transfer operation
according to the specified transfer source address count width (SASZ). When the transfer is completed,
the next access address is written to the corresponding address register (DMASA).
As a result, the transfer source address register is not updated until DMA transfer is completed.
To use a fixed address, set this bit to "0" or "1", and set the address count width (SASZ and DASZ) to
"0".
SADM
Function
0
Increments the transfer source address.[initial value]
1
Decrements the transfer source address.
• When reset: Initialized to "0".
• The read/write is possible.
[bit24] DADM (Destination-ADdr. Count-Mode select):
Transfer destination address count mode specification
Specifies what to do to the transfer destination address for the corresponding channel after each transfer.
An address increment is added or an address decrement is subtracted after each transfer operation
according to the specified transfer destination address count width (DASZ). When the transfer is
completed, the next access address is written to the corresponding address register (DMADA).
As a result, the transfer destination address register is not updated until the DMA transfer is completed.
To use a fixed address, set this bit to "0" or "1", and set the address count width (SASZ and DASZ) to
"0".
259
CHAPTER 10 DMA CONTROLLER (DMAC)
DADM
Function
0
Increments the transfer destination address. [initial value]
1
Decrements the transfer destination address.
• When reset: Initialized to "0".
• The read/write is possible.
[bit23] DTCR (DTC-reg. Reload): Transfer count register reload specification
Controls the reload function for the transfer count register in the corresponding channel.
If reloading operation is enabled by this bit, the count register value is restored to its initial value after
transfer is completed, then DMAC stops and starts waiting for a new transfer request (an activation
request by STRG or IS setting). (If this bit is "1", the DENB bit is not cleared.)
Transfer is forcibly halted when DENB=0 or DMAE=0 is set.
Disabling reloading of the transfer counter results in a single-shot transfer. That is, DMA halts when the
transfer is completed even if reloading is specified in the address register. In this case, the DENB bit is
cleared.
DTCR
Function
0
Disables transfer count register reloading. [initial value]
1
Enables transfer count register reloading.
• When reset: Initialized to "0".
• The read/write is possible.
[bit22] SADR (Source-ADdr.-reg. Reload):
Transfer source address register reload specification
Controls the reload function for the transfer source address register in the corresponding channel.
When reloading is enabled by this bit, the transfer source address register is reloaded with its initial value
when transfer completes.
Disabling reloading of the transfer counter results in a single-shot transfer. That is, DMA halts when the
transfer is completed even if reloading is specified in the address register. In this case, the address
register stops while the initial value is being reloaded.
When this bit disables reloading, the value of the address register when transfer completes is the next
access address after the final address (that is, if incrementing is enabled, it is the incremented address).
SADR
Function
0
Disables transfer source address register reloading. [initial value]
1
Enables transfer source address register reloading.
• When reset: Initialized to "0".
• The read/write is possible.
260
CHAPTER 10 DMA CONTROLLER (DMAC)
[bit21] DADR (Dest.-ADdr.-reg. Reload):
Transfer destination address register reload specification
Controls the reload function for the transfer destination address register in the corresponding channel.
When reloading is enabled by this bit, the transfer destination address register contains its initial value
when transfer completes.
The details of other functions are the same as those described for bit22 (SADR).
DADR
Function
0
Disables transfer destination address register reloading. [initial value]
1
Enables transfer destination address register reloading.
• When reset: Initialized to "0".
• The read/write is possible.
[bit20] ERIE (ERror Interrupt Enable): Error interrupt output enable
This bit controls the occurrence of an interrupt for termination after an error occurs. The nature of the
error is indicated by bits DSS2 to DSS0. Note that an interrupt occurs only for specific termination
causes and not for all termination causes. (Refer to an explanation bits DSS2 to DSS0, which are bit18 to
bit16.)
ERIE
Function
0
Disables error interrupt request output. [initial value]
1
Enables error interrupt request output.
• When reset: Initialized to "0".
• The read/write is possible.
[bit19] EDIE (EnD Interrupt Enable): End interrupt output enable
Controls whether to output an interrupt when transfer ends normally.
EDIE
Function
0
Disables end interrupt request output. [initial value]
1
Enables end interrupt request output.
• When reset: Initialized to "0".
• The read/write is possible.
261
CHAPTER 10 DMA CONTROLLER (DMAC)
[bit18 to bit16] DSS2 to DSS0 (DMA Stop Status): Transfer stop source indication
These bits indicate a code (end code) of 3 bits that indicates the source of stopping or termination of
DMA transfer on the corresponding channel.
Contents of the end code are as follow.
DSS
000
Function
Interrupt
Initial value
None
x01
-
None
x10
Transfer halt request
Error
x11
Successful completion
End
1xx
DMA stopped temporarily (due, for example, DMAH bits, PAUS bit,
and an interrupt)
None
The transfer stop request is only be set when a request from a peripheral circuit is used.
The Interrupt column indicates the type of interrupt requests that can occur.
• When reset: Initialized to "000B".
• Writing "000B" clears the bits.
• Although both reading and writing are permitted, only "000B" is meaningful when writing to the bits.
[bit15 to bit8] SASZ (Source Addr count SiZe):
Transfer source address count size specification
Specifies how much to increment or decrement the transfer source address (DMASA) for the
corresponding channel after each transfer. The value set by these bits becomes the address increment/
decrement width for each transfer unit. The address increment/decrement width conforms to the
instruction in the transfer source address count mode (SADM).
SASZ
Function
00H
Address fixed
01H
Byte-width transfer
02H
Halfword-width transfer
04H
Word-width transfer
without above-mentioned
Setting disabled
• When reset: Initialized to "00000000B".
• The read/write is possible.
• If setting other than a fixed address, ensure that the setting matches the transfer data width (WS).
262
CHAPTER 10 DMA CONTROLLER (DMAC)
[bit7 to bit0] DASZ (Des Addr count SiZe):
Transfer destination address count size specification
Specifies how much to increment or decrement the transfer destination address (DMADA) for the
corresponding channel after each transfer. The value set by these bits becomes the address increment/
decrement width for each transfer unit. The address increment/decrement width conforms to the
instruction in the transfer destination address count mode (DADM).
DASZ
Function
00H
Address fixed
01H
Byte-width transfer
02H
Halfword-width transfer
04H
Word-width transfer
without above-mentioned
Setting disabled
• When reset: Initialized to "00000000B".
• The read/write is possible.
• If setting other than a fixed address, ensure that the setting matches the transfer data width (WS).
263
CHAPTER 10 DMA CONTROLLER (DMAC)
10.2.3
Transfer Source/Transfer Destination Address Setting
Registers (DMASA0 to DMASA4/DMADA0 to DMADA4)
The transfer source/transfer destination address setting registers (DMASA0 to
DMASA4/DMADA0 to DMADA4) control the operation of the DMAC channels. There is a
separate register for each channel.
■ Bit Function of Transfer Source/Transfer Destination Address Setting Registers
(DMASA0 to DMASA4/DMADA0 to DMADA4)
Each bit function of DMASA0 to DMASA4 / DMADA0 to DMADA4 are indicated as follows.
bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
DMASA[31:16]
bit
15
14
13
11
11
10
9
8
7
DMASA[15:0]
Initial value: 00000000_00000000_00000000_00000000B
bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
DMADA[31:16]
bit
15
14
13
11
11
10
9
8
7
DMADA[15:0]
Initial value: 00000000_00000000_00000000_00000000B
These registers store the transfer source and destination addresses. Ch.0 to ch.3 is 20-bit length, and ch.4 is
24-bit length.
[bit31 to bit0] DMASA (DMA Source Addr): Transfer source address setting
Sets the transfer source address.
[bit31 to bit0] DMADA (DMA Destination Addr): Transfer destination address setting
Sets the transfer destination address.
When the DMA transfer is started, a data of this register is stored to the counter buffer of the address
counter for DMA and the address is counted according to setting of the DMACA register for each transfer.
When the DMA transfer is completed, the contents of the counter buffer are written back to this register
and then DMA ends. Thus, the address counter value during DMA operation cannot be read.
All registers have a dedicated reload register. When used on channels for which reloading the transfer
source and destination address registers is enabled, the registers are automatically reloaded with their
initial values when transfer completes. In this case, other address register are not affected.
• When reset: Initialized to "00000000_00000000_00000000_00000000B".
• The read/write is possible. Always use 32-bit access to read or write to this register.
• During transfer, reading returns the address setting from before transfer started. After transfer
completes, reading returns the next access address. You cannot read the reload value. Because the
reload value cannot be read, it is not possible to read the transfer address in real time.
• Please set "0" to no existence upper bit.
264
CHAPTER 10 DMA CONTROLLER (DMAC)
Note:
Do not set any of the DMAC’s registers using this register. Performing DMA transfer to registers in
the DMAC is not permitted.
265
CHAPTER 10 DMA CONTROLLER (DMAC)
10.2.4
All-Channel Control Register (DMACR)
The all-channel control register (DMACR) controls the operation of all the five DMAC
channels. Be sure to access this register using byte length.
■ Bit Function of All-Channel Control Register (DMACR)
Each bit function of DMACR is following.
bit
bit
31
30
29
28
27
26
25
DMAE
-
-
PM01
15
14
13
11
11
10
9
-
-
-
-
-
-
-
24
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
DMAH[3:0]
Initial value:0XX00000_XXXXXXXX_XXXXXXXX_XXXXXXXXB
[bit31] DMAE: (DMA Enable): DMA operation enable
Controls operation for all DMA channels.
If DMA operation is disabled with this bit, transfer operations on all channels are disabled regardless of
the start/stop settings for each channel and the operating status. Any requests on channels for which
transfer is in progress are cancelled and transfer halts at the block boundary. When disabled, any
operation to start transfer on any channel is ignored.
If this bit enables DMA operation, start/stop operations are enabled for all channels. Using this bit to
enable DMA operation does not actually start transfer for any channel.
DMA operation can be forced to stop by writing "0" to this bit. However, be sure to force stopping ("0"
write) only after temporarily stopping DMA using the DMAH3 to DMAH0 bits [bit27 to bit24:
DMACR]. If forced stopping is carried out without temporarily stopping DMA, DMA stops, but the
transfer data cannot be guaranteed. Check whether DMA is stopped using the DSS2 to DSS0 bits [bit18
to bit16: DMACB].
DMAE
Function
0
Disables DMA operation on all channels. [initial value]
1
Enables DMA operation on all channels.
• When reset: Initialized to "0".
• The read/write is possible.
[bit28] PM01 (Priority mode ch.0, ch.1 robin): Channel priority rotation
This bit is set to alternate priority for each transfer between ch.0 and ch.1.
PM01
Function
0
Fixes the priority. (ch.0 > ch.1) [initial value]
1
Alternates priority. (ch.1 > ch.0)
• When reset: Initialized to "0".
• The read/write is possible.
266
CHAPTER 10 DMA CONTROLLER (DMAC)
[bit27 to bit24] DMAH (DMA Halt): DMA temporary stop
Pauses DMA for all DMA channels. Setting these bits pauses DMA transfer on all channels until the bits
are cleared again.
If these bits are set before enabling DMA, all channels remain paused.
Any transfer requests that occur for channels with DMA transfer enabled (DENB=1) while these bits are
set are valid but transfer does not start until the bits are cleared.
DMAH
0000
Other than "0000"
Function
Enables the DMA operation on all channels. [initial value]
Temporarily stops DMA operation on all channels.
• When reset: Initialized to "0000B".
• The read/write is possible.
[bit30, bit29, and bit23 to bit0] Reserved: Reserved bits
The read value is undefined.
267
CHAPTER 10 DMA CONTROLLER (DMAC)
10.3
DMA Controller Operation
This section explains the operating overview, the transfer request setting, the transfer
sequence, and operating of DMAC in detail.
■ OVERVIEW of DMAC
A DMA controller (DMAC) is built into FR family devices. The FR family DMAC is a multi-functional
DMAC that controls data transfer at high speed without the use of CPU instructions.
268
CHAPTER 10 DMA CONTROLLER (DMAC)
10.3.1
DMA Controller Operation
This section explains the operating overview of DMAC.
■ Principal Operations of DMAC
The operation of each function can be set independently for each transfer channel.
Once enabled, a channel does not actually start transfer until the specified transfer request is detected.
On detecting a transfer request, the DMAC outputs a DMA transfer request to the bus controller and starts
transfer on receiving bus access rights from the bus controller. The transfer is carried out as a sequence
conforming to the mode settings made independently for the channel being used.
■ Transfer Mode
Each DMA channel performs transfer according to the transfer mode set by the MOD1 to MOD0 bits of its
DMACB register.
● Block/step transfer
Only a single block transfer unit is transferred in response to one transfer request. DMA then stops
requesting the bus controller for transfer until the next transfer request is received.
The block transfer unit is the specified block size (DMACA: BLK3 to BLK0).
● Burst transfer
On receiving a transfer request, transfer continues for the specified number of transfers.
Specified number of transfers: Block size × transfer count
(DMACA:BLK3 to BLK0 × DMACA:DTC15 to DTC0)
■ Transfer Type
● 2-cycle transfer (normal transfer)
The DMA controller operates using as its unit of operation a read operation and a write operation.
The DMAC reads the value from the address set in the transfer source register and then writes it to the
address in the transfer destination register.
269
CHAPTER 10 DMA CONTROLLER (DMAC)
■ Transfer Address
The following types of addressing are available and can be set independently for each channel transfer
source and transfer destination.
● Specifying the address for a 2-cycle transfer
The value read from a register (DMASA/DMADA) in which an address has been set in advance is used as
the address for access. After receiving a transfer request, DMA stores the address from the register in the
temporary storage buffer and then starts transfer.
After each transfer (access), the address counter is used to generate the next access address (based on
whether incrementing, decrementing, or constant-address is specified) and this new value is set in the
temporary storage buffer.
Because the contents of the temporary storage buffer are written back to the register (DMASA/DMADA)
after each block transfer unit is completed, the address register (DMASA/DMADA) value is updated after
each block transfer unit is completed, making it impossible to determine the address in real time during
transfer.
■ Number of Transfers and Ending Transfer
● Number of transfers
The transfer count register is decremented (-1) after transfer of each block completes. When the transfer
count register reaches zero indicating that the specified number of transfers have been performed, the
DMAC displays the termination code and halts or restarts DMA.
Like the address registers, the transfer count register is only updated after each block is transferred.
If reloading the transfer count register is disabled, transfer ends. If enabled, the register is reloaded with its
initial value and the DMAC waits for transfer to restart (DMACB: DTCR).
● The end of transfer
Listed below are the sources for transfer end. When transfer ends, a source is indicated as the end code
(DMACB:DSS2 to DSS0).
• End of the specified transfer count (DMACA:BLK3 to BLK0 × DMACA:DTC15 to DTC0) => Normal
end
• A transfer stop request from a peripheral circuit occurred => Error
• An address error occurred => Error
• A reset occurred => Reset
A transfer halt cause code (DSS) is set for each end condition and a transfer complete interrupt or transfer
error interrupt can be generated.
270
CHAPTER 10 DMA CONTROLLER (DMAC)
10.3.2
Setting up Transfer Requests
The following two types of transfer requests can be used to start DMA transfer.
• Internal peripheral request
• Software request
Software requests can always be used regardless of the settings of other requests.
■ Internal Peripheral Request
The transfer request is generated by an interrupt from an internal peripheral circuit.
For each channel, set the peripheral’s interrupt by which a transfer request is generated (when the
DMACA: IS4 to IS0 bits of are 1xxxxB).
Note:
Because an interrupt request used in a transfer request seems like an interrupt request to the CPU,
disable interrupts from the interrupt controller (ICR register).
■ Software Request
Writing to the trigger bit in the register generates the transfer request.(DMACA:STRG)
This is independent of the above transfer requests from peripherals and is always available.
If a software request occurs concurrently with activation (transfer enable request), a DMA transfer request
is outputted to the bus controller immediately and transfer is started.
271
CHAPTER 10 DMA CONTROLLER (DMAC)
10.3.3
Transfer Sequence
The transfer type and the transfer mode that determine, for example, the operation
sequence after DMA transfer has started can be set independently for each channel
(Settings for TYPE1, TYPE0 and MOD1, MOD0 of DMACB).
■ Selection of the Transfer Sequence
The following sequences can be selected by register settings.
• Burst 2-cycle transfer
• Block/step 2-cycle transfer
■ Burst 2-Cycle Transfer
The specified number of transfers is performed each time transfer is invoked. For a 2-cycle transfer, 20-bit
areas (ch.0 to ch.3) or 24-bit areas (ch.4) can be specified using a transfer source/transfer destination
address.
Either a transfer request from a peripheral function or a software request can be used to invoke transfer.
Table 10.3-1 shows the specifiable transfer addresses.
Table 10.3-1 Specifiable Transfer Addresses (for Burst 2-cycle Transfer)
Transfer source addressing
Direction
Transfer destination addressing
All 20(24)-bit areas specifiable
=>
All 20(24)-bit areas specifiable
[Burst transfer characteristics]
• Each time a transfer request is received, transfer continues until the transfer count register reaches zero.
The number of transfers is the block size multiplied by the number of blocks to be
transferred.(DMACA:BLK3 to BLK0 × DMACA:DTC15 to DTC0)
• If another transfer request is received during a transfer, the request is ignored.
• When the reload function is enabled for the transfer count register, a subsequent transfer request is
accepted only after transfer completes.
• If a transfer request for another channel with a higher priority is received during transfer, the channel is
switched at the boundary of the block transfer unit. Processing resumes only after the transfer request
for the other channel is cleared.
272
CHAPTER 10 DMA CONTROLLER (DMAC)
■ Step/Block Transfer 2-Cycle Transfer
For a step/block transfer (Transfer for each transfer request is performed as many times as the specified
block count), 20-bit areas (ch.0 to ch.3) or 24-bit areas (ch.4) can be specified as the transfer source/transfer
destination address.
Table 10.3-2 shows the specifiable transfer addresses.
Table 10.3-2 Specifiable Transfer Addresses (for Step/Block Transfer 2-Cycle Transfer)
Transfer source addressing
Direction
Transfer destination addressing
All 20(24)-bit areas specifiable
=>
All 20(24)-bit areas specifiable
■ Step Transfer
If 1 is set as the block size, a step transfer sequence is generated.
[Step transfer characteristics]
• If a transfer request is received, the transfer request is cleared after one transfer operation and then the
transfer is stopped (The DMA transfer request to the bus controller is canceled).
• If another transfer request is received during a transfer, the request is ignored.
• If a transfer request for another channel with a higher priority is received during transfer, the channel is
switched after the transfer is stopped and then restarted. For step transfer, priority is only meaningful for
the case when transfer requests are generated simultaneously.
■ Block Transfer
If any value other than 1 is specified as the block size, a block transfer sequence is generated.
[Block transfer characteristics]
Except for the fact that each transfer consists of multiple transfer cycles (specified by the number of
blocks), the operation is the same as for step transfer.
273
CHAPTER 10 DMA CONTROLLER (DMAC)
10.3.4
General Aspects of DMA Transfer
This section describes the DMA transfer operation.
■ Block Size
The unit of transfer data is the volume of data for the value set in the block size setting register (× data
width).
Since the data to be transferred in one transfer cycle is fixed to the value specified by the data width, one
transfer unit consists of the number of transfer cycles for the specified block size.
During a transfer, if a transfer request with higher priority is received or if a transfer pause request is
issued, the transfer stops only at the transfer unit boundary whether or not the transfer is a block transfer.
Although this prevents undesirable splitting or pausing within a data block, it causes the response to be
slower if the block size is large.
Transfer stops immediately only when a reset occurs, in which case the data being transferred cannot be
guaranteed.
■ Reload Operation
In this module, the following three types of reloading can be set for each channel:
(1) Transfer count register reloading
After transfer is performed the specified number of times, the initial value is set in the transfer count
register again and waiting for a transfer request. Use this setting to perform any of the transfer sequences
repeatedly. If reloading is not enabled, the count register remains at zero after the specified number of
transfers complete and no further transfers are performed.
(2) Transfer source address register reloading
After transfer is performed the specified number of times, the initial value is set in the transfer source
address register again.
Use this setting if repeatedly performing a transfer from a fixed region in the transfer source address
range. If reloading is not enabled, the value of the next transfer address remains set in the transfer source
address register after the specified number of transfers complete. Use this setting if the address range is
not fixed.
(3) Transfer destination address register reloading
After transfer is performed the specified number of times, the initial value is set in the transfer
destination address register again. Use this setting if repeatedly performing a transfer to a fixed region in
the transfer destination address range. (Other features are the same as (2).)
Enabling the reload functions for transfer source and destination address registers does not on its own cause
transfer to restart after the specified number of transfers complete. It only causes the address registers to be
reloaded with their initial values.
[Special operation modes and reload operation cases]
When using burst, block, or step transfer modes, transfer halts after the reload is performed at the end of the
transfer operation, and no further transfer is performed until a new transfer request input is detected.
274
CHAPTER 10 DMA CONTROLLER (DMAC)
10.3.5
Addressing Mode
Specify the transfer destination/transfer source address independently for each transfer
channel. The following two methods are provided to specify an address register. The
method specified depends on the transfer sequence.
■ Address Register Specifications
In 2-cycle transfer mode, set the transfer source address in the transfer source address setting register
(DMASA) and the transfer destination address in the transfer destination address setting register
(DMADA).
[Features of the Address Register]
• 20-bit (ch.0 to ch.3) or 24-bit (ch.4) length register is available.
[Function of the Address Register]
• The registers are read each time an access is performed and output on the address bus.
• At the same time, the address counter is used to calculate the address for the next access and the result
of this calculation is set in the address register.
• The address calculation is performed independently for each channel, source, and destination. Either
incrementing or decrementing can be selected. The width of the address increment or decrement is
specified by the address count size setting register. (DMACB: SASZ,DASZ)
• When the reload function is not enabled for an address register, the result of the final address calculation
remains in the register after the transfer ends.
• If the reload function is enabled, the initial value of the address is reloaded.
Reference:
If an overflow or underflow occurs as a result of 20-bit or 24-bit length address calculation, an
address error is detected and transfer on the relevant channel is stopped. (Refer to the description
for the items related to the end code).
Notes:
• Do not set the addresses of registers in the DMAC in the address registers.
• Do not transfer data to any of the DMAC’s registers using the DMAC.
275
CHAPTER 10 DMA CONTROLLER (DMAC)
10.3.6
Data Types
Select the data length (data width) transferred in one transfer operation from the
following:
• Byte
• Halfword
• Word
■ Access Address
Since the word boundary specification is also observed in DMA transfer, different low-order bits are
ignored if an address with a different data length is specified for the transfer destination/transfer source
address.
• Word: The actual access address has a 4-byte length starting with "00B" as the lowest-order 2bits.
• Halfword: The actual access address has 2-byte length starting with "0" as the lowest-order 1bit.
• Byte: The actual access address and the addressing match.
If the lowest-order bits in the transfer source address and transfer destination address are different, the
addresses as set are outputted on the internal address bus. However, each transfer target on the bus is
accessed after the addresses are corrected according to the above rules.
276
CHAPTER 10 DMA CONTROLLER (DMAC)
10.3.7
Control of the Transfer Count
Specify the transfer count within the range of the maximum 16-bit length (1 to 65536).
Set the number of transfers in the transfer count register (DMACA:DTC).
■ Transfer Count Register and Reload Operation
The register value is copied to a temporary storage buffer when transfer starts, and is decremented by the
transfer counter. When the counter value becomes "0", end of transfer for the specified count is detected,
and the transfer on the channel is stopped or waiting for a restart request starts (when reload is specified).
[Features of Transfer count register]
• Each register has 16-bit length.
• Each register has its own reload register.
• Setting the register to "0" results in transfer being performed 65536 times.
[Reload operation]
• Only used for registers with a reload function and for which the reload function is enabled.
• The initial value of the count register is saved in the reload register when transfer starts.
• Once the operation of the transfer counter causes the count to reach zero, a signal indicating transfer
completion is outputted, and then the initial value is read from the reload register and written to the
count register.
277
CHAPTER 10 DMA CONTROLLER (DMAC)
10.3.8
CPU Control
When a DMA transfer request is received, DMA issues a transfer request to the bus
controller.
The bus controller passes the right to use the internal bus to DMA at a break in bus
operation and DMA transfer starts.
■ DMA Transfer and Interrupts
During DMA transfer, if an NMI request or an interrupt request with a higher level than the hold suppress
level set by the HRCL register of the interrupt controller occurs, DMAC temporarily cancels the transfer
request via the bus controller at a transfer unit boundary (one block) to temporarily stop the transfer until
the interrupt request is cleared. In the meantime, the transfer request is retained internally. After the
interrupt request is cleared, DMAC issues a transfer request to the bus controller again to acquire the right
to use the bus and then restarts DMA transfer.
When the interrupt level is lower then that set to the HRCL register, an interrupt is not accepted until the
DMA transfer is completed. Also, if the DMA transfer request is generated during the interrupt processing
operation of the level lower than the specified value of the HRCL register, the transfer request is accepted,
and the interrupt processing operation stops until the transfer is completed.
DMA transfer request level is lowest at the default. The transfer is suspended for all interrupt requests, and
the interrupt processing is given precedence.
■ Overriding DMA
When an interrupt source with a higher priority occurs during DMA transfer, an FR family device
interrupts the DMA transfer and branches to the relevant interrupt routine. This feature is valid as long as
there are any interrupt requests. When all interrupt sources are cleared, the suppression feature no longer
works and the DMA transfer is restarted by the interrupt processing routine. Thus, if you want to suppress
restart of DMA transfer after clearing interrupt sources in the interrupt source processing routine at a level
that interrupts DMA transfer, use the DMA suppress function.
The DMA halt function is invoked by writing a non "0" value to the DMAH3 to DMAH0 bits in the DMA
overall control register. The override is cleared by setting the bits back to "0".
This function is mainly used in the interrupt processing routines. Before the interrupt sources in an interrupt
processing routine are cleared, the DMA suppress register is incremented by 1. If this is done, then no DMA
transfer is performed. After interrupt processing, decrement the DMAH3 to DMAH0 bits by 1 before returning.
If multiple interrupts have occurred, DMA transfer continues to be suppressed since the DMAH3 to
DMAH0 bits are not "0" yet. If a single interrupt has occurred, the DMAH3 to DMAH0 bits become "0".
DMA requests are then enabled immediately.
Notes:
• Since the register has only four bits, this function cannot be used for multiple interrupts exceeding
15 levels.
• Be sure to assign the priority of the DMA tasks at a level that is at least 15 levels higher than
other interrupt levels.
278
CHAPTER 10 DMA CONTROLLER (DMAC)
10.3.9
Operation Start
Starting of DMA transfer is controlled independently for each channel, but before
transfer starts, the operation of all channels needs to be enabled.
■ Enabling Operations for All Channels
Before activating each DMAC channel, operation for all channels needs to be enabled in advance with the
DMA operation enable bit (DMACR:DMAE).
All start settings and transfer requests that occurred before operation is enabled are invalid.
■ Starting Transfer
The transfer operation can be started by the operation enable bit of the control register for each channel. If a
transfer request to an activated channel is accepted, the DMA transfer operation is started in the specified
mode.
■ Starting from a Temporary Stop
If a temporary stop occurs before starting with channel-by-channel or all-channel control, the temporary
stopped state is maintained even though the transfer operation is started. If transfer requests occur in the
meantime, they are accepted and retained.
When temporary stopping is released, transfer is started.
279
CHAPTER 10 DMA CONTROLLER (DMAC)
10.3.10
Transfer Request Acceptance and Transfer
This section explains acceptance of transfer request and the contents of transfer.
■ Transfer Request Acceptance and Transfer
Sampling for transfer requests set for each channel starts after starting.
When start of peripheral interrupts is selected, the DMAC continues the transfer operation until the transfer
request is cleared. If it is cleared, the transfer is stopped in each transfer unit (start of peripheral interrupts).
Since peripheral interrupts are handled as level detection, use interrupt clear by DMA to handle the
interrupts.
Transfer requests are always accepted while other channel requests are being accepted and transfer
performed. The channel that will be used for transfer is determined for each transfer unit after priority has
been checked.
280
CHAPTER 10 DMA CONTROLLER (DMAC)
10.3.11
Clearing Peripheral Interrupts by DMA
This DMA has a function that clears peripheral interrupts. This function works when
peripheral interrupt is selected as the DMA start source (when IS4 to IS0 = 1xxxxB).
Peripheral interrupts are cleared only for the set start sources. That is, only the
peripheral functions set by IS4 to IS0 are cleared.
■ Timing for Clearing an Interrupt by DMA
The timing for clearing an interrupt depends on the transfer mode. (See "10.4 Operation Flowcharts").
[Block/step transfer]
If block transfer is selected, a clear signal is generated after one block (step) transfer.
[Burst transfer]
If burst transfer is selected, a clear signal is generated after transfer is performed the specified number of
times.
281
CHAPTER 10 DMA CONTROLLER (DMAC)
10.3.12
Temporary Stopping
This section explains the case when the DMA transfer stops temporarily.
■ Setting of Temporary Stopping by Writing to the Control Register
(Set Independently for Each Channel or All Channels Simultaneously)
If temporary stopping is set using the temporary stop bit, transfer on the corresponding channel is stopped
until release of temporary stopping is set again. You can check the DSS bits for temporary stopping.
Transfer is restarted when temporary stopping is canceled.
■ NMI/Hold Suppress Level Interrupt Processing
If an NMI request or an interrupt request with a higher level than the hold suppress level occurs, all
channels on which transfer is in progress are temporarily stopped at the boundary of the transfer unit and
the bus right is opened to give priority to NMI/interrupt processing. Transfer requests accepted during
NMI/interrupt processing are retained, initiating a wait for completion of NMI processing.
Channels for which requests are retained restart transfer after NMI/interrupt processing is completed.
282
CHAPTER 10 DMA CONTROLLER (DMAC)
10.3.13
Operation End/Stopping
The end of DMA transfer is controlled independently for each channel. It is also
possible to disable operation for all channels at once.
■ The End of Transfer
If reloading is disabled, transfer is stopped, "Normal end" is displayed at the end code, and all transfer
requests are disabled after the transfer count register becomes 0 (Clear the DENB bit of DMACA).
If reloading is enabled, the initial value is reloaded, "Normal end" is displayed at the end code, and a wait
for transfer requests starts after the transfer count register becomes 0 (Do not clear the DENB bit of
DMACA).
■ Disabling All Channels
If the operation of all channels is disabled with the DMA operation enable bit DMAE, all DMAC
operations, including operations on active channels, are stopped. Then, even if the operation of all channels
is enabled again, no transfer is performed unless a channel is restarted. In this case, no interrupt whatever
occurs.
283
CHAPTER 10 DMA CONTROLLER (DMAC)
10.3.14
Stopping Due To an Error
In addition to normal end after transfer for the number of times specified, stopping as
the result of various types of errors and the forced stopping are provided.
■ Transfer Stop Requests from Peripheral Circuits
Depending on the peripheral circuit that outputs a transfer request, a transfer stop request is issued when an
error is detected (Example: Error when data is received at or sent from a communications system
peripheral).
The DMAC, when it receives such a transfer stop request, displays "Transfer stop request" at the end code
and stops the transfer on the corresponding channel.
■ Occurrence of an Address Error
If inappropriate addressing, as shown below in parenthesis, occurs in an addressing mode, an address error
is detected (if an overflow or underflow occurs in the address counter when a 20-bit address is specified).
If an address error is detected, "An address error occurred" is displayed at the end code and transfer on the
corresponding channel is stopped.
284
CHAPTER 10 DMA CONTROLLER (DMAC)
10.3.15
DMAC Interrupt Control
Independent of peripheral interrupts that become transfer requests, interrupts can also
be outputted for each DMAC channel.
■ DMAC Interrupt Control
• Transfer end interrupt: Occurs only when operation ends normally.
• Error interrupt:
Transfer stop request due to a peripheral circuit (error due to a peripheral)
Occurrence of address error (error due to software)
All of these interrupts are output according to the meaning of the end code.
An interrupt request can be cleared by writing "000B" to DSS2 to DSS0 (end code) of DMACB. Be sure to
clear the end code by writing "000B" before restarting.
If reloading is enabled, the transfer is automatically restarted. At this point, however, the end code is not
cleared and is retained until a new end code is written when the next transfer ends.
Since only one end source can be displayed in an end code, the result after considering the order of priority
is displayed when multiple sources occur simultaneously. The interrupt that occurs at this point conforms to
the displayed end code.
The following shows the priority for displaying end codes (in order of decreasing priority):
• Reset
• Clearing by writing "000B"
• Peripheral stop request
• Normal end
• Stopping when address error detected
• Channel selection and control
285
CHAPTER 10 DMA CONTROLLER (DMAC)
10.3.16
DMA Transfer during Sleep Mode
The DMAC can also operate in sleep mode.
This section explains the DMA transfer at the state of the sleep.
■ Note of DMA Transfer in Sleep Mode
If you anticipate operations during sleep mode, note the following:
1. Since the CPU is stopped, DMAC registers cannot be rewritten. Make settings before sleep mode is
entered.
2. The sleep mode is released by an interrupt. Thus, if a peripheral interrupt is selected as the DMAC start
source, interrupts must be disabled by the interrupt controller.
Similarly, if you do not want to release sleep mode with a DMAC end interrupt, disable DMAC end
interrupts.
286
CHAPTER 10 DMA CONTROLLER (DMAC)
10.3.17
Channel Selection and Control
Up to five channels can be simultaneously set as transfer channels. In general, an
independent function can be set for each channel.
■ Priority Among Channels
Since DMA transfer is possible only on one channel at a time, priority must be set for the channels. Two
modes, fixed and rotation, are provided as the priority settings and can be selected for each channel group
(described later).
● Fixed mode
The priority is fixed by channel number in ascending order.
(ch.0 > ch.1 > ch.2 > ch.3 > ch.4)
If a transfer request with a higher priority is received during a transfer, the transfer channel becomes the
channel with the higher priority when the transfer for the transfer unit (number set in the block size
specification register × data width) ends.
When higher priority transfer is completed, transfer is restarted on the previous channel.
Figure 10.3-1 shows the timing diagram for the DMA transfer operation in fixed mode
Figure 10.3-1 Timing Diagram for the DMA Transfer Operation in Fixed Mode
ch.0 transfer request
ch.1 transfer request
Bus operation
CPU
SA
Transfer ch
DA
ch.1
SA
DA
SA
ch.0
DA
SA
ch.0
DA
CPU
ch.1
ch.0 transfer end
ch.1 transfer end
● Rotation mode (ch.0, ch.1 only)
When operation is enabled, the initial states have the same order that they would have in fixed mode, but at
the end of each transfer operation, the priority of the channels is reversed. Thus, if more than one transfer
request is outputted at the same time, the channel is switched after each transfer unit.
This mode is effective when continuous or burst transfer is set.
Figure 10.3-2 shows the timing diagram for the DMA transfer operation in rotation mode.
Figure 10.3-2 Timing Diagram for the DMA Transfer Operation in Rotation Mode
ch.0 transfer request
ch.1 transfer request
Bus operation
Transfer ch
CPU
SA
DA
ch.1
SA
DA
ch.0
SA
DA
ch.0
SA
DA
CPU
ch.1
ch.0 transfer end
ch.1 transfer end
287
CHAPTER 10 DMA CONTROLLER (DMAC)
■ Channel Group
Set the selection priority as explained in the table below.
Table 10.3-3 shows the selection priority of channel groups.
Table 10.3-3 Selection Priority of Channel Groups
Mode
Priority
Fixed
ch.0 > ch.1
ch.0 > ch.1
Rotation
ch.0 < ch.1
288
Remark
The initial state is the top row.
If transfer occurs for the top row, the priority is
reversed.
CHAPTER 10 DMA CONTROLLER (DMAC)
10.4
Operation Flowcharts
Figure 10.4-1 and Figure 10.4-2 show the operation flowchart for DMA transfer.
■ Operation Flowchart for Block Transfer
Figure 10.4-1 Operation Flowchart for Block Transfer
DENB=>0
DMA stop
DENB=1
Startup request
wait
Reload enabled
Startup request
initial
address, transfer number,
block number load
Transfer source address
access address calculation
Transfer destination address
access address calculation
Block number
-1
BLK=0
Transfer number-1
Address, transfer number,
block number, write back
Only when peripheral interrupt
startup factor is selected
Interrupt clear
Interrupt clear generated
DTC=0
DMA transfer end
DMA interrupt generated
Block transfer
Startup is enabled by all startup factors (select).
Access is enabled to all areas.
Block number is setable.
Interrupt clear is issued after the completion of block number.
DMA interrupt is issued after the completion of specified transfer number.
289
CHAPTER 10 DMA CONTROLLER (DMAC)
■ Operation Flowchart for Burst Transfer
Figure 10.4-2 Operation Flowchart for Burst Transfer
DMA stop
DENB=>0
DENB=1
Startup request
wait
Reload enabled
initial
address, transfer number,
block number load
Transfer source address
access address calculation
Transfer destination address
access address calculation
Block number
-1
BLK=0
Transfer number-1
DTC=0
Address, transfer number,
block number, write back
Only when peripheral interrupt startup factor is selected
Interrupt clear
DMA transfer end
Burst transfer
Startup is enabled by all startup factors (select).
Access is enabled to all areas.
Block number is setable.
Interrupt clear and DMA interrupt are issued after the completion of specified transfer number.
290
Interrupt clear generated
DMA interrupt generated
CHAPTER 10 DMA CONTROLLER (DMAC)
10.5
Data Path
This section shows the flow of data during 2-cycle transfer.
■ Flow of Data During 2-Cycle Transfer
Figure 10.5-1 to Figure 10.5-6 show examples of six types of transfer during 2-cycle transfer.
Figure 10.5-1 External Area => External Area Transfer
X-bus
Bus controller
D-bus
Data buffer
I-bus
X-bus
Bus controller
D-bus
Data buffer
F-bus
RAM
External bus I/F
CPU
I-bus
DMAC
Write cycle
CPU
DMAC
Read cycle
External bus I/F
External area => External area transfer
F-bus
I/O
RAM
I/O
Figure 10.5-2 External Area => Internal RAM Area Transfer
X-bus
Bus controller
D-bus
Data buffer
I-bus
X-bus
Bus controller
D-bus
Data buffer
F-bus
RAM
External bus I/F
CPU
I-bus
DMAC
Write cycle
CPU
DMAC
Read cycle
External bus I/F
External area => Internal RAM area transfer
F-bus
RAM
I/O
I/O
Figure 10.5-3 External Area => Built-in I/O Area Transfer
X-bus
Bus controller
D-bus
Data buffer
I-bus
X-bus
Bus controller
D-bus
Data buffer
F-bus
F-bus
RAM
I/O
External bus I/F
CPU
I-bus
DMAC
Write cycle
CPU
DMAC
Read cycle
External bus I/F
External area => built-in I/O area transfer
RAM
I/O
291
CHAPTER 10 DMA CONTROLLER (DMAC)
Figure 10.5-4 Built-in I/O Area => Built-in RAM Area Transfer
X-bus
Bus controller
D-bus
Data buffer
I-bus
X-bus
Bus controller
D-bus
F-bus
RAM
External bus I/F
CPU
I-bus
DMAC
Write cycle
CPU
DMAC
Read cycle
External bus I/F
Built-in I/O area => Built-in RAM area transfer
F-bus
I/O
RAM
I/O
Figure 10.5-5 Internal RAM Area => External Area Transfer
X-bus
Bus controller
D-bus
Data buffer
I-bus
X-bus
Bus controller
D-bus
Data buffer
F-bus
RAM
External bus I/F
CPU
I-bus
DMAC
Write cycle
CPU
DMAC
Read cycle
External bus I/F
Internal RAM area => External area transfer
F-bus
RAM
I/O
I/O
Figure 10.5-6 Internal RAM Area => Built-in I/O Area Transfer
CPU
Bus controller
D-bus
Data buffer
X-bus
I-bus
Bus controller
D-bus
Data buffer
F-bus
F-bus
RAM
292
I/O
RAM
I/O
External bus I/F
X-bus
I-bus
DMAC
Write cycle
CPU
DMAC
Read cycle
External bus I/F
Internal RAM area => Built-in I/O area transfer
CHAPTER 11
CAN CONTROLLER
This chapter explains the functions and operations of
CAN controller.
11.1 Feature of CAN
11.2 CAN Block Diagram
11.3 Register of CAN
11.4 Functions of CAN Registers
11.5 CAN Functions
293
CHAPTER 11 CAN CONTROLLER
11.1
Feature of CAN
CAN is compliant with the CAN protocol ver2.0 A/B, a standard protocol for the serial
communication, and is widely used in industrial fields like automobile or FA.
■ Features of CAN
CAN has the following features.
• Support for CAN protocol ver2.0A/B
• Support for bit rate up to 1Mbps.
• Identifier mask of each message object
• Support for programmable FIFO mode
• Maskable interrupt
• Support for programmable loop back mode for self test
• Read/write to message buffer by using of interface register
294
CHAPTER 11 CAN CONTROLLER
11.2
CAN Block Diagram
Figure 11.2-1 shows CAN block diagram.
■ CAN Block Diagram
Figure 11.2-1 CAN Block Diagram
CAN_TX CAN_RX
C_CAN
Message RAM
Message handler
CAN controller
Register group
Interrupt
DataOUT
DataIN
Address[7:0]
Control
Reset
Clock
CPU interface
■ CAN Controller
Controls the serial register for serial/parallel conversion to transfer CAN protocol and transmission/
reception message
■ Message RAM
Stores the message object
■ Register Group
All registers used in CAN
■ Message Handler
Controls message RAM and CAN controller
■ CPU Interface
Controls FR internal bus interface
295
CHAPTER 11 CAN CONTROLLER
11.3
Register of CAN
CAN has the following registers.
• CAN control register (CTRLR)
• CAN status register (STATR)
• CAN error counter (ERRCNT)
• CAN bit timing register (BTR)
• CAN interrupt register (INTR)
• CAN test register (TESTR)
• BRP extension register (BRPER)
• IFx command request register (IFxCREQ)
• IFx command mask register (IFxCMSK)
• IFx mask register 1 and 2 (IFxMSK1, IFxMSK2)
• IFx arbitration 1 and 2(IFxARB1, IFxARB2)
• IFx message control register (IFxMCTR)
• IFx data register A1, A2, B1, B2(IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2)
• CAN transmission request register 1 and 2 (TREQR1, TREQR2)
• CAN New Data register 1 and 2(NEWDT1, NEWDT2)
• CAN interrupt pending register 1 and 2 (INTPND1, INTPND2)
• CAN message valid register 1 and 2(MSGVAL1, MSGVAL2)
• CAN clock prescaler register (CANPRE)
■ List of Overall Control Registers
Table 11.3-1 List of Overall Control Registers
Address
Base-addr + 00H
Initial value
Base-addr + 04H
Initial value
Base-addr + 08H
Initial value
Base-addr + 0CH
Initial value
296
Registers
+0
+1
+2
+3
Comment
CAN control register
bit15 to bit8
bit7 to bit0
Reserved
CTRLR
00000001B
00000000B
CAN status register
bit15 to bit8
bit7 to bit0
Reserved
STATR
00000000B
00000000B
CAN error counter
bit15 to bit8
bit7 to bit0
CAN bit timing register
bit15 to bit8
bit7 to bit0
TSeg2[2:0],
SJW[1:0],
TSeg1[3:0]
BRP[5:0]
00100011B
00000001B
Error counter is read only.
Bit timing register is writable
by CCE.
CAN test register
bit15 to bit8
bit7 to bit0
Reserved
TESTR
00000000B
00000000B
F0000000B
Interrupt register is read only.
Test register can be used by
TEST.
"r" of TESTR means the value
of CAN_RX pin.
Reserved
bit15 to bit8
bit7 to bit0
Reserved
Reserved
00000000B
00000000B
BRP extension register is
writable by CCE.
RP, REC[6:0]
TEC[7:0]
00000000B
00000000B
CAN interrupt register
bit15 to bit8
bit7 to bit0
Int-Id15 to Int-Id8 Int-Id7 to Int-Id0
00000000B
00000000B
BRP extension register
bit15 to bit8
bit7 to bit0
Reserved
BRP3 to BRP0
00000000B
00000000B
CHAPTER 11 CAN CONTROLLER
■ Message Interface Register List
Table 11.3-2 Message Interface Register List (1 / 2)
Address
Base-addr + 10H
Initial value
Base-addr + 14H
Initial value
Base-addr + 18H
Initial value
Base-addr + 1CH
Initial value
Base-addr + 20H
Initial value
Base-addr + 24H
Initial value
Base-addr + 30H
Initial value
Base-addr + 34H
Initial value
Base-addr + 40H
Initial value
Registers
+0
+1
IF1 command request register
bit15 to bit8
bit7 to bit0
BUSY
Mess.No.5 to No.0
00000001B
00000000B
IF1 mask register 2
bit15 to bit8
bit7 to bit0
MXtd. MDir, Msk28
Msk23 to Msk16
to Msk24
11111111B
11111111B
IF1 arbitration register 2
bit15 to bit8
bit7 to bit0
MsgVal, Xtd,
ID23 to ID16
Dir,ID28 to ID24
00000000B
00000000B
+2
+3
Comment
IF1 command mask register
bit15 to bit8
bit7 to bit0
Reserved
IF1CMSK
00000000B
00000000B
IF1 mask register 1
bit15 to bit8
bit7 to bit0
Msk15 to Msk8
Msk7 to Msk0
11111111B
11111111B
IF1 arbitration register 1
bit15 to bit8
bit7 to bit0
ID15 to ID8
ID7 to ID0
00000000B
00000000B
IF1 message control register
bit15 to bit8
bit7 to bit0
IF1MCTR
IF1MCTR
00000000B
00000000B
bit15 to bit8
Reserved
00000000B
Reserved
IF1 data register A1
bit7 to bit0
bit15 to bit8
Data[0]
Data[1]
00000000B
00000000B
IF1 data register A2
bit7 to bit0
bit15 to bit8
Data[2]
Data[3]
00000000B
00000000B
Big endian
byte
IF1 data register B1
bit7 to bit0
bit15 to bit8
Data[4]
Data[5]
00000000B
00000000B
IF1 data register B2
bit7 to bit0
bit15 to bit8
Data[6]
Data[7]
00000000B
00000000B
Big endian
byte
IF1 data register A2
bit15 to bit8
bit7 to bit0
Data[3]
Data[2]
00000000B
00000000B
IF1 data register A1
bit15 to bit8
bit7 to bit0
Data[1]
Data[0]
00000000B
00000000B
Little endian
byte
IF1 data register B2
bit15 to bit8
bit7 to bit0
Data[7]
Data[6]
00000000B
00000000B
IF1 data register B1
bit15 to bit8
bit7 to bit0
Data[5]
Data[4]
00000000B
00000000B
Little endian
byte
IF2 command request register
bit15 to bit8
bit7 to bit0
BUSY
Mess.No.5 to 0
00000001B
00000000B
IF2 command mask register
bit15 to bit8
bit7 to bit0
Reserved
IF2CMSK
00000000B
00000000B
bit7 to bit0
Reserved
00000000B
297
CHAPTER 11 CAN CONTROLLER
Table 11.3-2 Message Interface Register List (2 / 2)
Address
Registers
+0
+1
IF2 mask register 2
Base-addr + 44H
Initial value
bit15 to bit8
MXtd. MDir, Msk28
to Msk24
11111111B
Initial value
bit15 to bit8
MsgVal, Xtd,
Dir,ID28 to ID24
00000000B
Initial value
bit15 to bit8
IF2MCTR
00000000B
bit15 to bit8
bit7 to bit0
Msk23 to Msk16
Msk15 to Msk8
Msk7 to Msk0
11111111B
11111111B
11111111B
IF2 arbitration register 1
bit7 to bit0
bit15 to bit8
bit7 to bit0
ID23 to ID16
ID15 to ID8
ID7 to ID0
00000000B
00000000B
00000000B
bit7 to bit0
IF2MCTR
00000000B
IF2 data register A1
Base-addr + 50H
Initial value
bit7 to bit0
Data[0]
00000000B
bit15 to bit8
Data[1]
00000000B
IF2 data register B1
Base-addr + 54H
Initial value
bit7 to bit0
Data[4]
00000000B
bit15 to bit8
Data[5]
00000000B
IF2 data register A2
Base-addr + 60H
Initial value
bit15 to bit8
Data[3]
00000000B
bit7 to bit0
Data[2]
00000000B
IF2 data register B2
Base-addr + 64H
Initial value
298
bit15 to bit8
Data[7]
00000000B
bit7 to bit0
Data[6]
00000000B
Comment
IF2 mask register 1
IF2 message control register
Base-addr + 4CH
+3
bit7 to bit0
IF2 arbitration register 2
Base-addr + 48H
+2
Reserved
bit15 to bit8
Reserved
00000000B
bit7 to bit0
Reserved
00000000B
IF2 data register A2
bit7 to bit0
Data[2]
00000000B
bit15 to bit8
Data[3]
00000000B
Big endian
byte
IF2 data register B2
bit7 to bit0
Data[6]
00000000B
bit15 to bit8
Data[7]
00000000B
Big endian
byte
IF2 data register A1
bit15 to bit8
Data[1]
00000000B
bit7 to bit0
Data[0]
00000000B
Little endian
byte
IF2 data register B1
bit15 to bit8
Data[5]
00000000B
bit7 to bit0
Data[4]
00000000B
Little endian
byte
CHAPTER 11 CAN CONTROLLER
■ Message Handler Register List
Table 11.3-3 Message Handler Register List
Address
Registers
+0
+1
+2
CAN transmission request register 2
Base-addr + 80H
Initial value
Base-addr + 84H
bit15 to bit8
TxRqst32 to
TxRqst25
00000000B
Initial value
Base-addr + 94H
bit7 to bit0
TxRqst24 to
TxRqst17
00000000B
bit15 to bit8
TxRqst16 to
TxRqst9
00000000B
Initial value
Base-addr + A4H
Base-addr +B0H
Base-addr + B4H
Transmission
request register
TxRqst8 to TxRqst1 is read only.
bit7 to bit0
00000000B
Reserved (used when the number of message buffer is 33 or more)
bit15 to bit8
NewDat32 to
NewData25
00000000B
CAN new data register 1
bit7 to bit0
NewDat24 to
NewData17
00000000B
bit15 to bit8
NewData16 to
NewData9
00000000B
bit7 to bit0
NewData8 to
NewData1
00000000B
New data
register is read
only.
Reserved (used when the number of message buffer is 33 or more)
CAN interrupt pending register 2
Base-addr + A0H
Comment
CAN transmission request register 1
CAN new data register 2
Base-addr + 90H
+3
bit15 to bit8
IntPnd32 to
IntPnd25
00000000B
bit7 to bit0
IntPnd24 to
IntPnd17
00000000B
CAN interrupt pending register 1
Interrupt
pending register
IntPnd16 to IntPnd9 IntPnd8 to IntPnd1 is read only.
bit15 to bit8
bit7 to bit0
00000000B
00000000B
Reserved (used when the number of message buffer is 33 or more)
CAN message valid register 2
bit15 to bit8
bit7 to bit0
MsgVal24 to
MsgVal32 to
MsgVa25
MsgVa17
00000000B
00000000B
CAN message valid register 1
bit15 to bit8
bit7 to bit0
MsgVal16 to
MsgVal8 to
MsgVa9
MsgVa1
00000000B
00000000B
Message valid
register is read
only.
Reserved (used when the number of message buffer is 33 or more)
■ Clock Prescaler Register
Table 11.3-4 Clock Prescaler Register
Address
0001A8H
Initial value
Registers
+0
CAN prescaler
register
bit3 to bit0
CANPRE[3:0]
00000000B
+1
+2
+3
-
-
-
-
-
-
Comment
CAN prescaler
299
CHAPTER 11 CAN CONTROLLER
11.4
Functions of CAN Registers
As for the CAN register, the address space in 256 bytes (64 words) is allocated. CPU
accesses the message RAM through the message interface register.
This section lists the CAN registers and describes the function of each register in detail.
■ Overall Control Registers
• CAN control register (CTRLR)
• CAN status register (STATR)
• CAN error counter (ERRCNT)
• CAN bit timing register (BTR)
• CAN interrupt register (INTR)
• CAN test register (TESTR)
• BRP extension register (BRPER)
■ Message Interface Register
• IFx command request register (IFxCREQ)
• IFx command mask register (IFxCMSK)
• IFx mask register 1 and 2 (IFxMSK1, IFxMSK2)
• IFx arbitration register 1 and 2 (IFxARB1, IFxARB2)
• IFx message control register (IFxMCTR)
• IFx data register A1, A2, B1 and B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2)
■ Message Handler Register
• CAN transmission request register 1 and 2 (TREQR1, TREQR2)
• CAN new data register 1 and 2 (NEWDT1, NEWDT2)
• CAN interrupt pending register 1 and 2 (INTPND1, INTPND2)
• CAN message valid register 1 and 2 (MSGVAL1, MSGVAL2)
■ Prescaler Register
CAN clock prescaler register (CANPRE)
300
CHAPTER 11 CAN CONTROLLER
11.4.1
Overall Control Registers
Overall control registers control the CAN protocol control and the operation mode and
offer the status information.
■ Overall Control Registers
• CAN control register (CTRLR)
• CAN status register (STATR)
• CAN error counter (ERRCNT)
• CAN bit timing register (BTR)
• CAN interrupt register (INTR)
• CAN test register (TESTR)
• BRP extension register (BRPER)
301
CHAPTER 11 CAN CONTROLLER
11.4.1.1
CAN Control Registers (CTRLR0, CTRLR1)
CAN control registers (CTRLR0, CTRLR1) control the operation mode of CAN controller.
■ Register Configuration
CAN control register (Upper byte)
Address
bit15
Base+00H
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
R
R
R
R
R
R
R
R
Initial value
00000000B
CAN control register (Lower byte)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
Base+01H
Test
R/W
CCE
R/W
DAR
R/W
Reserved
EIE
R/W
SIE
R/W
IE
R/W
Init
R/W
00000001B
R
R/W: Readable/Writable
R:
Read only
■ Register Function
[bit15 to bit8] Reserved: Reserved bit
"00000000B" is read from these bits.
Set "00000000B" at writing.
[bit7] Test: Test mode enable bit
Test
Function
0
Normal Operation [Initial value]
1
Test mode
[bit6] CCE: Configuration change enable bit
CCE
Function
0
Writing to CAN bit timing register and BRP extension register is disabled. [initial value]
1
Writing to CAN bit timing register and BRP extension register is enabled. It is enabled
when Init bit is "1".
[bit5] DAR: Automatic re-transmission disable bit
DAR
302
Function
0
Automatic re-transmission of message is enabled in case of arbitration lost or error
detection. [initial value]
1
Automatic re-transmission is disabled.
CHAPTER 11 CAN CONTROLLER
According to the CAN Specification (see ISO11898,6.3.3 Recovery Management), the CAN controller
automatically re-sends the frame when a transfer error or arbitration lost is detected. The DAR bit is reset
to "0" when sending it again automatically. To run the CAN under the Time Triggered CAN (see
TTCAN, ISO11898-1) environment, the DAR bit should be set to "1".
In a mode with the DAR bit set to 1, the TxRqst and NewDat bits in message object (see "11.4.3
Message Object" for information about message object) operate differently.
• TxRqst in the message object is reset to "0" when the frame starts to be sent, while the NewDat bit is
kept set.
• When the frame transmission ends normally, NewDat is reset to "0".
• NewDat is kept set when an arbitration lost or transfer error is detected in the send operation. It is
necessary to set one to TxRqst with CPU to restart the transmission.
[bit4] Reserved: Reserved bit
This bit reads "0".
Set "0" at writing.
[bit3] EIE: Error interrupt code enable bit
EIE
Function
0
Change of Boff or EWarn bit of CAN status register disables setting of interrupt code to
CAN status interrupt register. [Initial value]
1
Change of Boff or EWarn bit of CAN status register enables setting of status interrupt
code to CAN interrupt register.
[bit2] SIE: Status interrupt code enable bit
SIE
Function
0
Change of TxOk, RxOk or LEC bit of CAN status register disables setting of interrupt
code to CAN status interrupt register. [Initial value]
1
Change of TxOk, RxOk or LEC bit of CAN status register enables setting of status
interrupt code to CAN interrupt register.
Change of TxOk, RxOk or LEC bit that is generated by writing from CPU is not set in
CAN interrupt register.
[bit1] IE: Interrupt enable bit
IE
Function
0
Interrupt generation is disabled. [Initial value]
1
Interrupt generation is enabled.
[bit0] Init: Initialization bit
Init
Function
0
CAN controller operation enable
1
Initialization [Initial value]
303
CHAPTER 11 CAN CONTROLLER
• The bus-off recovery sequence (see the CAN Specification Rev.2.0) cannot be shortened by
activating/deactivating the Init bit. When the device is in the bus off state, the CAN controller sets
the Init bit to "1" and stops all the bus operations. When the Init bit is cleared to "0" in bus off, it
keeps stopping the bus operation until the bus idle occurs 129 times (an 11-bit recessive is 1 time) in
a row. After the bus-off recovery sequence is performed, the error counter is reset.
• Write into the CAN bit-timing register after you set the Init and CCE bits to "1".
• If you want to use the low-power consumption modes (the stop or clock mode), initialize the CAN
controller by writing "1" to the Init bit before moving to the low-power consumption mode.
• If you want to modify a dividing ratio of the clock provided to the CAN interface in the CAN
prescaler register, change the CAN prescaler register after setting the Init bit to "1".
304
CHAPTER 11 CAN CONTROLLER
11.4.1.2
CAN Status Register (STATR)
CAN status register (STATR) displays CAN status and CAN bus state.
■ Register Configuration
CAN status register (Upper byte)
Address
bit15
Base+02H
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
R
R
R
R
R
R
R
R
Initial value
00000000B
CAN status register (Lower byte)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Base+03H
BOff
R
EWarn
R
EPass
R
RxOk
R/W
TxOk
R/W
R/W
LEC
R/W
R/W
Initial value
00000000B
R/W: Readable/Writable
R:
Read only
■ Register Function
[bit15 to bit8] Reserved: Reserved bits
These bits read "0".
Set "0" at writing.
[bit7] BOff: Bus off bit
BOff
Function
0
CAN controller is not in the state of bus off (bus active) [Initial value]
1
CAN controller is in the state of bus off.
[bit6] EWarn: Warning bit
EWarn
Function
0
Both transmission and reception counter are less than 96. [Initial value]
1
Transmission or reception counter is 96 or more.
[bit5] EPass: Error passive bit
EPass
Function
0
Both transmission and reception counter are less than 128.
(error active state) [Initial value]
1
The reception counter: RP bit = 1 and the transmission counter ≥ 128
(error passive state)
305
CHAPTER 11 CAN CONTROLLER
[bit4] RxOk: Message normal reception bit
RxOk
Function
0
Message reception is abnormal or in the state of bus idle. [Initial value]
1
Message reception is normal.
[bit3] TxOk: Message normal transmission bit
TxOk
Function
0
Message transmission is abnormal or in the state of bus idle. [Initial value]
1
Message transmission is normal.
Note:
Only CPU resets RxOk and TxOk bits.
[bit2 to bit0] LEC: Last error code bits
LEC
Function
0
Normal
It is indicated normally to have been transmitted or received.
[Initial value]
1
Stuff error
Indicates that dominants or recessives were detected in more than the
sixth straight bit in a message.
2
Form error
Indicates that the fixed format part of a received frame was received by
mistake.
3
Ack error
Indicates that the transmission message was not acknowledged by other
nodes.
4
Bit1 error
Indicates that the recessive was sent but the dominant was detected on a
transmission data of message except the arbitration field.
5
Bit0 error
Indicates that the dominant was sent but the recessive was detected on a
transmission data of message.
It is set every time the 11-bit recessive is detected during the bus
recovery. The bus recovery sequence can be monitored by reading this bit.
6
CRC error
Indicates that the CRC data of received message does not match the result
of the CRC calculation.
Undetection
Indicates that the send or receive operations were not performed if the
read value of the LEC bit was "7" after the value "7" was written to the
LEC bit by CPU.
(Bus idle state)
7
306
State
CHAPTER 11 CAN CONTROLLER
The LEC bits maintain a code for the last error occurred on the CAN bus. It is set to 0H when the
message is transferred (received/sent) without an error. The undetected code 7H must be set by CPU to
check a code update.
• The status interrupt code (8000H) is set in the CAN interrupt register, if the BOff or EWarn bit
changes when the EIE bit is "1" or if the RxOk, TxOk, or LEC bits changes when the SIE bit is "1".
• The RxOk or TxOk bit is updated by the write operation of CPU; therefore, the RxOk or TxOk bit,
which is set by the CAN controller, will not be maintained. If you want to use the RxOk or TxOk bit,
clear it within (45 × BT) hours after the RxOk or TxOk bit is set to "1". BT indicates one bit time.
• If an interrupt occurs by a change of the LEC bits when the SIE bit is "1", do not write into the CAN
status register.
• It is not generated in CPU writing operating to the change in the EPass bit or RxOk, TxOk, and the
LEC bits.
• The EWarn bit is set to one though the BOff bit or the EPass bit becomes one.
• By reading this register, the status interrupt (8000H) in the CAN interrupt register is cleared.
307
CHAPTER 11 CAN CONTROLLER
11.4.1.3
CAN Error Counter (ERRCNT0 to ERRCNT2)
CAN error counter (ERRCNT0 to ERRCNT2) shows reception error passive display,
reception error counter, and transmission error counter.
■ Register Configuration
CAN error counter register (Upper byte)
Address
bit15
bit14
bit13
bit12
RP
R
R
R
R
Base+04H
bit11
bit10
bit9
bit8
R
R
bit2
bit1
bit0
R
R
R
REC6 to REC0
R
R
Initial value
00000000B
CAN error counter register (Lower byte)
Address
bit7
bit6
bit5
R
R
R
Base+05H
R:
bit4
bit3
TEC7 to TEC0
R
R
Initial value
00000000B
Read only
■ Register Function
[bit15] RP: Reception error passive display
RP
Function
0
The reception error counter is not the error passive state in the CAN specification.
[Initial value]
1
The reception error counter is the error passive state in the CAN specification.
[bit14 to bit8] REC6 to REC0: Reception error counter
Receive error counter value. The range of reception error counter value is 0 to 127.
[bit7 to bit0] TEC7 to TEC0: Transmission error counter
Transmit error counter value. The range of transmit error counter value is 0 to 255.
308
CHAPTER 11 CAN CONTROLLER
11.4.1.4
CAN Bit Timing Register (BTR0 to BTR2)
CAN bit timing register (BTR0 to BTR2) sets prescaler and bit timing.
■ Register Configuration
CAN bit timing register (Upper byte)
Address
bit15
Base+06H
bit14
bit13
bit12
bit11
bit10
R/W
TSeg2
R/W
R/W
R
R
R
R
bit2
bit1
bit0
R/W
R/W
R/W
Reserved
R
bit9
bit8
TSeg1
Initial value
00100011B
CAN bit timing register (Lower byte)
Address
bit7
Base+07H
bit6
bit5
bit4
bit3
R/W
R/W
R/W
R/W
SJW
R/W
BRP
Initial value
00000001B
R/W: Readable/Writable
R:
Read only
The CAN bit-timing register and BRP extension register must be set when the CCE and Init bits in the
CAN control register are set to "1".
■ Register Function
[bit15] Reserved: Reserved bit
This bit reads "0".
Set "0" at writing.
[bit14 to bit12] TSeg2: Time segment 2 setting bits
The valid setting value is 0 to 7. The value of TSeg2+1 becomes time segment 2.
The time segment 2 corresponds to the phase buffer segment (PHASE_SEG2) of the CAN specification.
[bit11 to bit8] TSeg1: Time segment 1 setting bits
The valid setting value is 1 to 15. "0" is disabled to set. The value of TSeg1+1 becomes time segment 1.
Time segment 1 is equivalent to propagation segment (PROP_SEG) and phase buffer segment 1
(PHASE_SEG1) based on CAN specifications.
[bit7, bit6] SJW: Re-synchronization jump width setting bits
The valid setting value is 0 to 3. The value of SJW+1 is re-synchronous jump width.
[bit5 to bit0] BRP: Baud rate prescaler setting bits
The valid setting value is 0 to 63. The value of BRP+1 becomes baud rate prescaler.
Divide the system clock (fsys) and determine the basic unit time (tq) of the CAN controller.
309
CHAPTER 11 CAN CONTROLLER
11.4.1.5
CAN Interrupt Register (INTR0 to INTR2)
CAN interrupt register (INTR0 to INTR2) displays message interrupt code and status
interrupt code.
■ Register Configuration
CAN interrupt register (Upper byte)
Address
bit15
bit14
bit13
R
R
R
Base+08H
bit12
bit11
IntId15 to IntId8
R
R
bit10
bit9
bit8
R
R
R
bit2
bit1
bit0
R
R
R
Initial value
00000000B
CAN interrupt register (Lower byte)
Address
bit7
bit6
bit5
R
R
R
Base+09H
R:
bit4
bit3
IntId7 to IntId0
R
R
Initial value
00000000B
Read only
■ Register Function
IntId
Function
0000H
No interrupt
0001H to 0020H
Message interrupt code
(Interrupt factor is the number of message object.)
0021H to 7FFFH
Unused
8000H
Status interrupt code
(Interrupt by change of CAN status register)
8001H to FFFFH
Unused
If multiple interrupt codes are pending, the CAN interrupt register points to an interrupt code with the
highest priority. When an interrupt code with higher priority occurs, the CAN interrupt register is updated
to the interrupt code, even if the interrupt code is set in the CAN interrupt register.
Priorities of interrupt codes are the status interrupt code (8000H) and the message interrupts (0001H, 0002H,
0003H, ...,0020H), in that order.
If the IE bit in the CAN control register is set to "1" when the IntId bit is other than 0000H, the interrupt
signal to CPU becomes active. If the IntId bit becomes 0000H (meaning that the interrupt trigger is reset) or
the IE bit in the CAN control register is reset to "0", the interrupt signal to CPU becomes inactive.
If the IntPnd bit in the target message object (see "11.4.3 Message Object" for information about message
object) is cleared to "0", the message interrupt code is cleared.
The status interrupt code is cleared when the CAN status register is loaded.
310
CHAPTER 11 CAN CONTROLLER
11.4.1.6
CAN Test Register (TESTR0 to TESTR2)
The CAN test register (TESTR0 to TESTR2) sets the test mode and monitors the RX
terminal. Please refer to section "11.5.7 Test Mode" for operating.
■ Register Configuration
CAN test register (Upper byte)
Address
bit15
Base+0AH
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
R
R
R
R
R
R
R
R
bit1
bit0
Initial value
00000000B
CAN test register (Lower byte)
Address
bit7
bit6
bit5
bit4
bit3
bit2
Base+0BH
Rx
R
Tx1
R/W
Tx0
R/W
LBack
R
Silent
R/W
Basic
R/W
Reserved Reserved
R
Initial value
00000000B
R
R/W: Readable/Writable
R:
Read only
As for initial value (r) of Rx of bit7, the level on the CAN bus is displayed.
The write operation to the CAN test register (TESTR) must be performed after the Test bit in the CAN
control register (CTRLR) is set to "1". The test mode is valid, at the Test bit of the CAN control register =
1. If the Test bit in the CAN control register is set to "0" during the test mode, the mode becomes the
normal mode.
■ Register Function
[bit15 to bit8] Reserved: Reserved bits
"00000000B" is read from these bits.
Set "00000000B" at write.
[bit7] Rx: Rx pin monitor bit
Rx
Function
0
CAN bus shows it is dominant.
1
CAN bus shows it is recessive.
[bit6, bit5] Tx1, Tx0: TX pin control bits
Tx1, Tx0
Function
00
Normal Operation [Initial value]
01
Sampling point is outputted to Tx pin.
10
Dominant is outputted to TX pin.
11
Recessive is outputted to TX pin.
When setting Tx bit to other than "00B", the message cannot be transmitted.
311
CHAPTER 11 CAN CONTROLLER
[bit4] LBack: Loop back mode
LBack
Function
0
Loop back mode is disabled. [Initial value]
1
Loop back mode is enabled.
[bit3] Silent: Silent mode
Silent
Function
0
Silent mode is disabled. [Initial value]
1
Silent mode is enabled.
[bit2] Basic: Basic mode
Basic
Function
0
Basic mode is disabled. [Initial value]
1
Basic mode is enabled.
IF1 register and IF2 register are used as transmission message and reception message
respectively.
[bit1, bit0] Reserved: Reserved bits
These bits read "00B".
Set "00B" at writing.
312
CHAPTER 11 CAN CONTROLLER
11.4.1.7
BRP Extension Register (BRPER0 to BRPER2)
BRP extension register (BRPER0 to BRPER2), extends the prescaler used in the CAN
controller, by combining with the prescaler that is set in the CAN bit timing.
■ Register Configuration
CAN prescaler extended register (Upper byte)
Address
bit15
Base+0CH
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
R
R
R
R
R
R
R
R
bit4
bit3
bit2
bit1
bit0
R/W
BRPE
R/W
R/W
R/W
Initial value
00000000B
CAN prescaler extended register (Lower byte)
Address
bit7
Base+0DH
bit6
bit5
Reserved Reserved Reserved Reserved
R
R
R
R
Initial value
00000000B
R/W: Readable/Writable
R:
Read only
■ Register Function
[bit15 to bit4] Reserved: Reserved bits
These bits read "00000000_0000B".
Set "00000000_0000B" at writing.
[bit3 to bit0] BRPE: Baud rate prescaler extended bits
By combining BRP and BRPE in the CAN bit-timing register, you can extend the baud rate prescaler up
to 1023.
The value of {BRPE (MSB:4 bit), BRP (LSB:6 bit)} + 1 becomes the value of prescaler CAN controller.
313
CHAPTER 11 CAN CONTROLLER
11.4.2
Message Interface Register
There are two pairs of the message interface registers to control CPU access to the
message RAM.
There are two pairs of the message interface registers used to control CPU access to the message RAM.
These two pairs are provided to avoid a conflict of the CPU access to the message RAM and the access
from CAN controller, by buffering the data (message object) that is already transferred or is waiting to be
transferred. The message object (see "11.4.3 Message Object" for information about message object)
transfers the data at a time between the message interface register and the message RAM.
Except for the test basic mode, the two pairs of the message interface registers have the same function and
can operate independently. For example, while the IF1 message interface register is used for the write
operation to the message RAM, the IF2 message interface register can be used for the read operation from
the message RAM. Two message interface registers are indicated in Table 11.4-1.
The message interface register consists of the command registers (the command request and command
mask registers) and the message buffer registers (the mask, arbitration, message control, and data registers)
controlled by the command register. The command mask register indicates which direction the data is
transferred in and what part of the message object is transferred. The command request register selects the
message number and performs the action as specified in the command mask register.
Table 11.4-1 IF1 and IF2 Message Interface Register
Address
314
IF1 register set
Address
IF2 register set
Base + 10H
IF1 command request
Base + 40H
IF2 command request
Base + 12H
IF1 command mask
Base + 42H
IF2 command mask
Base + 14H
IF1 mask 2
Base + 44H
IF2 mask 2
Base + 16H
IF1 mask 1
Base + 46H
IF2 mask 1
Base + 18H
IF1 arbitration 2
Base + 48H
IF2 arbitration 2
Base + 1AH
IF1 arbitration 1
Base + 4AH
IF2 arbitration 1
Base + 1CH
IF1 message control
Base + 4CH
IF2 message control
Base + 20H
IF1 data A1
Base + 50H
IF2 data A1
Base + 22H
IF1 data A2
Base + 52H
IF2 data A2
Base + 24H
IF1 data B1
Base + 54H
IF2 data B1
Base + 26H
IF1 data B2
Base + 56H
IF2 data B2
CHAPTER 11 CAN CONTROLLER
11.4.2.1
IFx Command Request Register (IFxCREQ)
The IFx command request register (IFxCREQ) selects the message number in the
message RAM and performs the transfer operation between the message RAM and the
message buffer register. In addition, for the test basic mode, IF1 is used to control the
send process, and IF2 is used to control the receive process.
■ Register Configuration
IFx command request register (Upper byte)
Address
bit15
Base+10H &
Base+40H
BUSY
R/W
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
R
R
R
R
R
R
R
bit5
bit4
bit3
bit2
bit1
bit0
R/W
R/W
R/W
R/W
Initial value
00000000B
IFx command request register (Lower byte)
Address
bit7
Base+11H &
Base+41H
bit6
Reserved Reserved
R/W
R/W
Message Number
R/W
R/W
Initial value
00000000B
R/W: Readable/Writable
R:
Read only
■ Register Function
The message transfer starts between the message RAM and the message buffer registers (the mask,
arbitration, message control, and data registers) immediately after the message number is written to the IFx
command request register. This write operation sets the BUSY bit to "1" and indicates that the transfer is in
progress. When the transfer ends, the BUSY bit is reset to "0".
If a CPU access to the message interface register occurs when the BUSY bit is "1", the operation makes
CPU wait until the BUSY bit becomes "0" (during the 3 to 6 cycle period after the write operation of the
command request register).
In a test basic mode, the usage of the BUSY bit is different. The IF1 command request register is used as a
transmission message. It orders to start sending message, by setting the BUSY bit to "1". When the
message transfer ends normally, the BUSY bit is reset to "0". It also can halt the transfer of message at
anytime by resetting the BUSY bit to "0".
The IF2 command request register is used as a receive message and stores received message in the IF2
message interface register by setting the BUSY bit to "1".
[bit15] BUSY: Busy flag bit
• Other than test basic mode
BUSY
Function
0
Indicates that the data transfer was not processed between the message interface register
and the message RAM. [Initial value]
1
Indicates that the data transfer is being processed between the message interface register
and the message RAM.
315
CHAPTER 11 CAN CONTROLLER
• Test basic mode
- IF1 command request register
BUSY
Function
0
Message transmission is disabled.
1
Message transmission is enabled.
- IF2 command request register
BUSY
Function
0
Message reception is disabled.
1
Message reception is enabled.
BUSY bit is enabled to read and write. Except for the test basic mode, writing any value to this bit does
not have an effect on operation. (Please refer to "11.5.7 Test Mode" for a basic mode.)
[bit14 to bit6] Reserved: Reserved bits
These bits read "0000000000B".
Set "0000000000B" at writing.
[bit5 to bit0] Message Number: Message number (for 32 message buffer CAN)
Message Number
Function
00H
Setting disabled.
When setting it, it is interpreted as 20H. So 20H is read.
01H to 20H
The processed message number is set.
21H to 3FH
Setting disabled.
When setting it, it is interpreted as 01H to 1FH. So the interpreted value is read.
[bit4 to bit0] Message Number: Message number (for 128 message buffer CAN) *
Message Number
00H
Setting disabled.
When setting it, it is interpreted as 20H. So 20H is read.
01H to 80H
The processed message number is set.
81H to FFH
Setting disabled.
When setting it, it is interpreted as 01H to 7FH. So the interpreted value is read.
*: Only for MB91V280
316
Function
CHAPTER 11 CAN CONTROLLER
11.4.2.2
IFx Command Mask Register (IFxCMSK)
The IFx command mask register (IFxCMSK) controls the direction of the transfer
between the message interface register and the message RAM and determines the data
to be updated. Moreover, this register becomes invalid in a test basic mode.
■ Register Configuration
IFx command mask register (Upper byte)
Address
bit15
Base+12H &
Base+42H
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
R
R
R
R
R
bit4
Initial value
00000000B
R
R
R
bit3
bit2
bit1
bit0
Initial value
Data A
Data B
00000000B
R/W
R/W
IFx command mask register (Lower byte)
Address
bit7
Base+13H &
Base+43H
bit6
bit5
WR/RD
Mask
Arb
Control
CIP
TxRqst/
NewDat
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/Writable
R:
Read only
This register setting is invalid in the test basic mode.
■ Register Function
[bit15 to bit8] Reserved: Reserved bits
These bits read "00000000B".
Set "00000000B" at writing.
[bit7] WR/RD: Write/read control bit
WR/RD
Function
0
It is indicated to read data from message RAM. The read operation from the message
RAM is performed by writing into the IFx command request register. The data read from
message RAM depends on the setting of Mask, Arb, Control, CIP, TxRqst/NewDat,
DataA, and the DataB bits.
[Initial value]
1
It is indicated to write data to message RAM. The write operation to the message RAM is
performed by writing into the IFx command request register. The writing data to message
RAM depends on the setting of Mask, Arb, Control, CIP, TxRqst/NewDat, DataA, and
the DataB bits.
After reset it, the data of message RAM is undefined. Reading message RAM data is prohibited when the
data is uncertain.
317
CHAPTER 11 CAN CONTROLLER
The bit6 to bit0 of the IFx command mask register have different meanings, depending on the settings of
the transmission direction (the WR/RD bits).
● When transmission direction is write (WR/RD=1)
[bit6] Mask: Mask data renewal bit
Mask
Function
0
Mask data (ID mask + MDir + MXtd) of message object* is not renewed. [Initial value]
1
Mask data (ID mask + MDir + MXtd) of message object* is renewed.
*: Refer to "11.4.3 Message Object".
[bit5] Arb: Arbitration data renewal bit
Arb
Function
0
Arbitration data (ID + Dir + Xtd + MsgVal) of message object* is not renewed.
[Initial value]
1
Arbitration data (ID + Dir + Xtd + MsgVal) of message object* is renewed.
*: Refer to "11.4.3 Message Object".
[bit4] Control: Control data renewal bit
Control
Function
0
Control data (IFx message control register) of message object* is not renewed.
[Initial value]
1
Control data (IFx message control register) of message object* is renewed.
*: Refer to "11.4.3 Message Object".
[bit3] CIP: Interrupt clear bit
Setting "0" or "1" to this bit is no effect to CAN controller operation.
318
CHAPTER 11 CAN CONTROLLER
[bit2] TxRqst/NewDat: Message transmission request bit
TxRqst/NewDat
Function
0
Set "0" to message object* and TxRqst bit of CAN transmission request register.
[initial value]
1
Set "1" to message object* and TxRqst bit of CAN transmission request register.
(transmission request)
*: Refer to "11.4.3 Message Object".
When TxRqst/NewDat bit of IFx command mask register is set to "1", setting of TxRqst bit of IFx
message control register is invalid.
[bit1] Data A: Data 0 to Data 3 renewal bit
Data A
Function
0
Data 0 to Data 3 of message object * is not renewed. [Initial value]
1
Data 0 to Data 3 of message object * is renewed.
*: Refer to "11.4.3 Message Object".
[bit0] Data B: Data 4 to data 7 renewal bit
Data B
Function
0
Data 4 to Data 7 of message object * is not renewed. [Initial value]
1
Data 4 to Data 7 of message object * is renewed.
*: Refer to "11.4.3 Message Object".
319
CHAPTER 11 CAN CONTROLLER
● When transmission direction is read (WR/RD=0)
The IntPnd and NewDat bits can be reset to "0" by the read access to message object. However, the IntPnd
and NewDat bits in the IFx message control register store the previous IntPnd and NewDat bits before they
were reset by the read access.
It becomes invalid in a test basic mode.
[bit6] Mask: Mask data renewal bit
Mask
Function
0
The data (ID mask + MDir + MXtd) is not transmitted from message object* to IFx mask
register 1 and 2. [Initial value]
1
The data (ID mask + MDir + MXtd) is transmitted from message object* to IFx mask
register 1 and 2.
*: Refer to "11.4.3 Message Object".
[bit5] Arb: Arbitration data renewal bit
Arb
Function
0
The data (ID+ Dir + Xtd + MsgVal) is not transmitted from message object* to IFx
arbitration register 1 and 2. [Initial value]
1
The data (ID+ Dir + Xtd + MsgVal) is transmitted from message object* to IFx arbitration
register 1 and 2.
*: Refer to "11.4.3 Message Object".
[bit4] Control: Control data renewal bit
Control
Function
0
The data is not transmitted from message object* to IFx message control register. [Initial
value]
1
The data is transmitted from message object* to IFx message control register.
*: Refer to "11.4.3 Message Object".
320
CHAPTER 11 CAN CONTROLLER
[bit3] CIP: Interrupt clear bit
CIP
Function
0
Message object* and IntPnd bit of CAN interrupt pending register are retained.
[Initial value]
1
Message object* and IntPnd bit of CAN interrupt pending register are cleared to "0".
*: Refer to "11.4.3 Message Object".
[bit2] TxRqst/NewDat: Data renewal bit
TxRqst/NewDat
Function
0
Message object* and NewDat bit of CAN data renewal register are retained.
[Initial value]
1
Message object* and NewDat bit of CAN data renewal register are cleared to "0".
*: Refer to "11.4.3 Message Object".
[bit1] Data A: Data 0 to Data 3 renewal bit
Data A
Function
0
Message object* and data of CAN data register A1 and A2 are retained. [Initial value]
1
Message object* and data of CAN data register A1 and A2 are renewed.
*: Refer to "11.4.3 Message Object".
[bit0] Data B: Data 4 to Data 7 renewal bit
Data B
Function
0
Message object* and data of CAN data register B1 and B2 are retained. [Initial value]
1
Message object* and data of CAN data register B1 and B2 are renewed.
*: Refer to "11.4.3 Message Object".
321
CHAPTER 11 CAN CONTROLLER
11.4.2.3
IFx Mask Register 1 and 2 (IFxMSK1, IFxMSK2)
The IFx mask registers (IFxMSK1 and IFxMSK2) are used to write/read the message
object mask data in the message RAM. Also, in the test basic mode, the set mask data
has no effect. For function of each bit, refer to "11.4.3 Message Object".
■ Register Configuration
IFx mask register 2 (Upper byte)
Address
bit15
bit14
bit13
bit12
bit11
Base+12H &
Base+42H
MXtd
R/W
MDir
R/W
Reserved
bit10
bit9
bit8
R
R/W
Msk28 to Msk24
R/W
R/W
R/W
R/W
bit4
bit3
Initial value
11111111B
IFx mask register 2 (Lower byte)
Address
bit7
bit6
bit5
Base+15H &
Base+45H
R/W
R/W
R/W
Msk23 to Msk16
R/W
R/W
bit2
bit1
bit0
R/W
R/W
R/W
Initial value
11111111B
IFx mask register 1 (Upper byte)
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Base+16H &
Base+46H
R/W
R/W
R/W
Msk15 to Msk8
R/W
R/W
R/W
R/W
R/W
Initial value
11111111B
IFx mask register 1 (Lower byte)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Base+17H &
Base+47H
R/W
R/W
R/W
Msk7 to Msk0
R/W
R/W
R/W
R/W
R/W
Initial value
11111111B
R/W: Readable/Writable
R:
Read only
For the bit explanation of IFx mask register, refer to "11.4.3 Message Object".
"1" is read from reserved bit (bit13 of IFx mask register 2) of register. Write "1" at writing.
322
CHAPTER 11 CAN CONTROLLER
11.4.2.4
IFx Arbitration Register 1 and 2 (IFxARB1, IFxARB2)
The IFx arbitration registers (IFxARB1 and IFxARB2) are used to write/read the message
object arbitration data in the message RAM. Moreover, it becomes invalid in a test basic
mode. For function of each bit, refer to "11.4.3 Message Object".
■ Register Configuration
IFx arbitration register 2 (Upper byte)
Address
Base+18H &
Base+48H
bit15
bit14
bit13
bit12
bit11
MsgVal
R/W
Xtd
R/W
Dir
R/W
R/W
R/W
bit10
bit9
bit8
ID28 to ID24
R/W
R/W
R/W
Initial value
00000000B
IFx arbitration register 2 (Lower byte)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Base+19H &
Base+49H
R/W
R/W
R/W
ID23 to ID16
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
IFx arbitration register 1 (Upper byte)
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Base+1AH &
Base+4AH
R/W
R/W
R/W
ID15 to ID8
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
IFx arbitration register 1 (Lower byte)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Base+1BH &
Base+4BH
R/W
R/W
R/W
ID7 to ID0
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
R/W: Readable/Writable
For the bit explanation of IFx arbitration register, refer to "11.4.3 Message Object".
If you clear the MsgVal bit in the message object to "0" during the send operation, the TxOk bit in the
CAN status register becomes "1" when the send has completed, but the TxRqst bit in the message object
and the CAN send request register is not cleared to "0". The TxRqst bit must be cleared to "0" through the
message interface register.
323
CHAPTER 11 CAN CONTROLLER
11.4.2.5
IFx Message Control Register (IFxMCTR)
The IFx message control register (IFxMCTR) is used to write/read the message object
control data in the message RAM. Also, in the test basic mode, the IF1 message control
register has no effect. NewDat and MsgLst in the IF2 message control register operate
as usual, and the DLC bit indicates the DLC of received message. Other control bits
operate as invalidity ("0"). For function of each bit, refer to "11.4.3 Message Object".
■ Register Configuration
IFx message control register (Upper byte)
Address
Base+1CH &
Base+4CH
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
NewDat
MsgLst
IntPnd
UMask
TxIE
RxIE
RmtEn
TxRqst
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit4
bit3
bit2
bit1
bit0
R/W
DLC3 to DLC0
R/W
R/W
R/W
IFx message control register (Lower byte)
Address
bit7
Base+1DH &
Base+4DH
EoB
R/W
bit6
bit5
Reserved Reserved Reserved
R
R
R
Initial value
00000000B
R/W: Readable/Writable
R:
Read only
For the bit explanation of IFx message control register, refer to "11.4.3 Message Object".
The TxRqst, NewDat, and IntPnd bits operate as follows, based on the settings of the WR/RD bit in the IFx
command mask register:
● When transmission direction is write (IFx command mask register: WR/RD=1)
The TxRqst bit in this register can be active, only if TxRqst/NewDat in the IFx command mask register is
set to "0".
● When transmission direction is read (IFx command mask register: WR/RD=0)
This register stores the previous IntPnd bit before it is reset, if the CIP bit in the IFx command mask
register is set to "1" and the IntPnd bit in the message object and the CAN interrupt pending register is reset
by the write operation to the IFx command request register.
This register stores the previous NewDat bit before it is reset, if the TxRqst/NewDat bits in the IFx
command mask register are set to "1" and the NewDat bit in the message object and the CAN data update
register is reset by the write operation to the IFx command request register.
324
CHAPTER 11 CAN CONTROLLER
11.4.2.6
IFx Data Register A1,A2,B1,B2
(IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2)
The IFx data registers (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2) are used to write/read the
message object send/receive data in the message RAM. They are used only for the
send/receive for data frame, not for remote frame.
■ Register Configuration
IFx message data A1 (Address 20H & 50H)
addr+0
addr+1
Data(0)
Data(1)
IFx message data A2 (Address 22H & 52H)
IFx message data B1 (Address 24H & 54H)
Data(4)
Data(3)
Data(7)
Data(2)
Data(3)
Data(6)
Data(7)
Data(1)
Data(0)
Data(5)
Data(4)
Data(2)
IFx message data A1 (Address 32H & 62H)
IFx message data B2 (Address 34H & 64H)
addr+3
Data(5)
IFx message data B2 (Address 26H & 56H)
IFx message data A2 (Address 30H & 60H)
addr+2
Data(6)
IFx message data B1 (Address 36H & 66H)
IFx data register
bit15
bit14
13bit
bit12
bit11
bit10
9bit
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Data
R/W
R/W
R/W
R/W
R/W
Initial value
R/W
R/W
R/W
00000000B
R/W: Readable/Writable
■ Register Function
● Setting of transmission message data
The set data is sent Data(0), Data(1) ... Data(7) in this order starting from MSB (bit7 and bit15).
● Reception message data
The reception message data is stored Data(0), Data(1) ... Data(7) in this order starting from MSB (bit7 and
bit15).
If the receive message data is less than 8 bytes, the remaining bytes in the data register is undefined.
The message object is transferred on a 4-byte basis of DataA or DataB, thus not allowed to update only a
part of the 4-byte data.
325
CHAPTER 11 CAN CONTROLLER
11.4.3
Message Object
The message RAM contains 32 (or up to 128, depending on its type) message objects.
To avoid a conflict between the CPU access to the message RAM and the access from
the CAN controller, CPU cannot access directly to the message object. These accesses
must be done through the IFx message interface register.
This section explains the configuration and functions of message object.
■ Configuration of Message Object
Massage object
UMask
Msk28 to
Msk0
MXtd
MDir
EoB
MsgVal
ID28 to
ID0
Xtd
Dir
DLC3 to
DLC0
NewDat
MsgLst
RxIE
TxIE
IntPnd RmtEn TxRqst
Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7
Note:
The message object is not initialized by the Init bit in the CAN control register or the resetting of
hardware. For the resetting of hardware, either initialize the message RAM in CPU or set MsgVal in
the message RAM to 0 after the resetting of hardware is unlocked.
■ Functions of Message Object
When sending a message, the ID28 to ID0, Xtd, and Dir bits are used for the ID and type of the message.
When receiving a message, the ID28 to ID0, Xtd, and Dir bits, along with the Msk28 to Msk0, MXtd, and
MDir bits, are used in the acceptance filter.
The data frame or remote frame is stored in the message object after the frame has passed through the
acceptance filter. Xtd indicates either the extended frame or the standard frame. If Xtd is "1", the 29-bit ID
(extended frame) is received, and if Xtd is "0", the 11-bit ID (standard frame) is received.
If the received data frame or remote frame matches one or more message objects, it is stored in the least
number of the matched messages. For details, see "11.5.3 Message Reception Operation" for the
acceptance filter for received message.
MsgVal: Valid message bit
MsgVal
Function
0
The message object is invalid.
The message is not sending and receiving.
1
The message object is valid.
The message is able to be sending and receiving.
• During the initialization before the Init bit of the CAN control register is reset to "0", the MsgVal bit
of all unused message objects must be reset by CPU.
• Before you modify ID28 to ID0, Xtd, Dir, and DLC3 to DLC0, or if you do not need the message
object, be sure to reset the MsgVal bit to "0".
326
CHAPTER 11 CAN CONTROLLER
• If you set the MsgVal bit to "0" during the send operation, the TxOk bit of the CAN status register
becomes "1" when the send has completed, but the TxRqst bit of the message object and the CAN
send request register is not cleared to "0". The TxRqst bit must be cleared to "0" through the message
interface register.
UMask: Acceptance mask enable bit
UMask
Function
0
Msk28 to Msk0, MXtd, and MDir are not used.
1
Msk28 to Msk0, MXtd, and MDir are used.
• Modify the UMask bit when the Init bit of the CAN control register is "1", or when the MsgVal bit is
"0".
• When Dir bit is "1" and the RmtEn bit is "0", operating is different according to the setting of UMask.
- If UMask is "1", the TxRqst bit is reset to "0" when the remote frame is received after passing
through the acceptance filter. The received ID, IDE, RTR, and DLC are stored in the message
object, and the NewDat bit is set to "1", while the data is not modified. (It handles the same way as
the data frame. )
- If UMask is "0", the TxRqst bit is kept as it is when receiving the remote frame, and the remote
frame is ignored.
ID28 to ID0: Message ID
Function
ID28 to ID0
Specify 29-bit ID (extended frame)
ID28 to ID18
Specify 11-bit ID (standard frame)
Msk28 to Msk0: ID mask
Msk
Function
0
Masking the bit that corresponds to ID of the message object
1
No masking the bit that corresponds to ID of the message object
When 11-bit ID (standard frame) is set to message object, ID of received data frame is written to ID28 to
ID18. For ID mask, Msk28 to Msk18 are used.
Xtd: Extended ID enable bit
Xtd
Function
0
Message object is 11-bit ID (standard frame)
1
Message object is 29-bit ID (extended frame)
327
CHAPTER 11 CAN CONTROLLER
MXtd: Extended ID mask bit
MXtd
Function
0
Masking the extended ID bit (IDE) for the acceptance filter
1
No masking the extended ID bit (IDE) for the acceptance filter
Dir: Message direction bit
Dir
Function
0
It is the direction of the reception.
Sends the remote frame if TxRqst is set to "1", and receives the data frame that has
passed through the acceptance filter, if TxRqst is 0.
1
It is the direction of the transmission.
Sends the data frame if TxRqst is set to "1", and the CAN controller sets TxRqst to "1" by
receiving the remote frame that has passed through the acceptance filter, if TxRqst is set
to "0" and RmtEn is set to "1".
MDir: Message direction mask bit
MDir
Function
0
Masking the message direction bit (Dir) on the acceptance filter
1
No masking the message direction bit (Dir) on the acceptance filter
Note:
Be sure to set MDir bit to "1".
EoB: End of buffer bit
(For details, refer to "11.5.4 FIFO Buffer Function".)
EoB
Function
0
Message object is used as FIFO buffer and not the last message.
1
Single message object or the last message object of FIFO buffer.
EoB bit is used for configuring the FIFO buffer of 2 to 32 messages.
For a single message object with FIFO not used, be sure to set the EoB bit to "1".
328
CHAPTER 11 CAN CONTROLLER
NewDat: Data renewal bit
NewDat
Function
0
Without valid data
1
With valid data
MsgLst: Message lost
MsgLst
Function
0
Without generation of message lost
1
With generation of message lost
MsgLst bit is enabled when Dir bit is "0" (received direction) only.
RxIE: Reception interrupt flag enable bit
RxIE
Function
0
After the frame reception succeeds, IntPnd is not changed.
1
After the frame reception succeeds, IntPnd is set to "1".
TxIE: Transmission interrupt flag enable bit
TxIE
Function
0
After the frame transmission succeeds, IntPnd is not changed.
1
After the frame transmission succeeds, IntPnd is set to "1".
IntPnd: Interrupt pending bit
IntPnd
Function
0
Without interrupt cause
1
With interrupt cause
The IntId bit in the CAN interrupt register indicates this message object, if other
interruption with high priority was not found.
329
CHAPTER 11 CAN CONTROLLER
RmtEn: Remote enable
RmtEn
Function
0
TxRqst is not changed by receiving the remote frame.
1
When the Dir bit receives a remote frame by "1", TxRqst is set to "1".
When the Dir is "1" and the RmtEn bit is "0", operating is different according to the setting of UMask.
- If UMask is "1", the TxRqst bit is reset to "0" when the remote frame is received after passing
through the acceptance filter. The received ID, IDE, RTR, and DLC are stored in the message
object, and the NewDat bit is set to "1", while the data is not updated. (It handles the same way as
the data frame. )
- If UMask is "0", the TxRqst bit is kept as it is when receiving the remote frame, and the remote
frame is ignored.
TxRqst: Transmission request bit
TxRqst
Function
0
Transmission idle state (No transmitting and no transmission waiting state)
1
Transmitting or transmission waiting state
DLC3 to DLC0: Data length code
DLC3 to DLC0
Function
0 to 8
Data frame length is 0 to 8 byte.
9 to 15
Setting disabled
It becomes eight byte lengths when set.
When data frame is received, received DLC is stored in DLC bits.
Data 0 to Data 7: Data 0 to Data 7
Function
Data 0
The first data byte of CAN data frame
Data 1
The second data byte of CAN data frame
Data 2
The third data byte of CAN data frame
Data 3
The fourth data byte of CAN data frame
Data 4
The fifth data byte of CAN data frame
Data 5
The sixth data byte of CAN data frame
Data 6
The seventh data byte of CAN data frame
Data 7
The eighth data byte of CAN data frame
• Serial output to CAN bus is outputted from MSB (bit7 or bit15).
• When received message data is less than 8 bytes, byte data which is the rest of data register is
undefined.
• The message object is transferred on a 4-byte basis of DataA or DataB, thus not allowed to update
only a part of the 4-byte data.
330
CHAPTER 11 CAN CONTROLLER
11.4.4
Message Handler Register
All of the message handler registers are for reading only. TxRqst, NewDat, IntPnd,
MsgVal, and the IntId bits of the message object display status.
■ Message Handler Register
• CAN transmission request register 1 and 2 (TREQR1,TREQR2)
• CAN new data register 1 and 2 (NEWDT1,NEWDT2)
• CAN interrupt pending register 1 and 2 (INTPND1,INTPND2)
• CAN message valid register 1 and 2 (MSGVAL1,MSGVAL2)
331
CHAPTER 11 CAN CONTROLLER
11.4.4.1
CAN Transmission Request Register
(TREQR1, TREQR2)
The CAN transmission request registers (TREQR1 and TREQR2) indicate the TxRqst bit
of all the message objects. It is possible to check which transmission requests of
message object is pending, by reading the TxRqst bit.
■ Register Configuration
CAN transmission request register 2 (Upper byte)
Address
bit15
bit14
bit13
R
R
R
Base+80H
bit12
bit11
TxRqst32 to TxRqst25
R
R
bit10
bit9
bit8
R
R
R
bit2
bit1
bit0
R
R
R
bit10
bit9
bit8
Initial value
00000000B
CAN transmission request register 2 (Lower byte)
Address
bit7
bit6
bit5
R
R
R
Base+81H
bit4
bit3
TxRqst24 to TxRqst17
R
R
Initial value
00000000B
CAN transmission request register 1 (Upper byte)
Address
bit15
bit14
bit13
Base+82H
R
R
R
bit12
bit11
TxRqst16 to TxRqst9
R
R
Initial value
00000000B
R
R
R
bit2
bit1
bit0
CAN transmission request register 1 (Lower byte)
Address
bit7
bit6
bit5
Base+83H
R
R:
332
Read only
R
R
bit4
bit3
TxRqst8 to TxRqst1
R
R
Initial value
00000000B
R
R
R
CHAPTER 11 CAN CONTROLLER
■ Registers Function
TxRqst32 to TxRqst1: Transmission request bits
TxRqst
Function
0
Transmission idle state (No transmitting and no transmission waiting state)
1
Transmitting or transmission waiting state
Set and reset conditions of TxRqst bit are shown in the following.
• Set condition
- With WR/RD set to "1" and TxRqst to "1" in the IFx command mask register, TxRqst for particular
object can be set by writing into the IFx command request register.
- With WR/RD set to "1" and TxRqst to "0" in the IFx command mask register, and TxRqst set to "1"
in the IFx message control register, TxRqst for particular object can be set by writing into the IFx
command request register.
- With the Dir bit set to "1" and the RmtEn bit to "1", TxRqst is set when the remote frame, having
passed through the acceptance filter, is received.
• Reset condition
- With WR/RD set to "1" and TxRqst to "0" in the IFx command mask register, and TxRqst set to "0"
in the IFx message control register, TxRqst for particular object can be reset by writing into the IFx
command request register.
- It is reset that the transmission of the frame ends normally.
- With Dir set to "1", RmtEn to "0", and UMask to "1", TxRqst is reset when the remote frame, having
passed through the acceptance filter, is received.
See the table below for the transmission request bit in the CAN macro which has the 32 message buffer or
more:
addr + 0
addr + 1
addr + 2
addr + 3
TREQR4 &
TREQR3
TxRqst64 to
TxRqst33
(address 84H)
TxRqst64 to
TxRqst57
TxRqst56 to
TxRqst49
TxRqst48 to
TxRqst41
TxRqst40 to
TxRqst33
TREQR6 &
TREQR5
TxRqst96 to
TxRqst65
(address 88H)
TxRqst96 to
TxRqst89
TxRqst88 to
TxRqst81
TxRqst80 to
TxRqst73
TxRqst72 to
TxRqst65
TREQR8 &
TREQR7
TxRqst128 to
TxRqst97
(address 8CH)
TxRqst128 to
TxRqst121
TxRqst120 to
TxRqst113
TxRqst112 to
TxRqst105
TxRqst104 to
TxRqst97
333
CHAPTER 11 CAN CONTROLLER
11.4.4.2
CAN New Data Register (NEWDT1, NEWDT2)
The CAN new data registers (NEWDT1 and NEWDT2) indicate the NewDat bit of all the
message objects. It is possible to check which data of message object has been
updated, by reading the NewDat bit.
■ Register Configuration
CAN data renewal register 2 (Upper byte)
Address
bit15
bit14
bit13
R
R
R
Base+90H
bit12
bit11
bit10
bit9
bit8
R
R
bit1
bit0
R
R
bit10
bit9
bit8
R
R
R
bit2
bit1
bit0
R
R
R
NewDat32 to NewDat25
R
R
R
Initial value
00000000B
CAN data renewal register 2 (Lower byte)
Address
bit7
bit6
bit5
R
R
R
Base+91H
bit4
bit3
bit2
NewDat24 to NewDat17
R
R
R
Initial value
00000000B
CAN data renewal register 1 (Upper byte)
Address
bit15
bit14
bit13
R
R
R
Base+92H
bit12
bit11
NewDat16 to NewDat9
R
R
Initial value
00000000B
CAN data renewal register 2 (Lower byte)
Address
bit7
bit6
bit5
R
R
R
Base+93H
R:
334
Read only
bit4
bit3
NewDat8 to NewDat1
R
R
Initial value
00000000B
CHAPTER 11 CAN CONTROLLER
NewDat16 to NewDat1: Data renewal bits
NewDat16 to NewDat1
Function
0
Without new data
1
With new data
Set and reset conditions of NewDat bit are shown in the following.
• Set condition
- With WR/RD set to "1" in the IFx command mask register, and NewDat to "1" in the IFx message
control register, NewDat for particular object can be set by writing of the IFx command request
register.
- NewDat is set when the data frame, having passed through the acceptance filter, is received.
- With Dir set to "1", RmtEn to "0", and UMask to "1", NewDat is set when the remote frame, having
passed through the acceptance filter, is received.
• Reset condition
- With WR/RD set to "0" and NewDat to "1" in the IFx command mask register, NewDat for particular
object can be reset by writing of the IFx command request register.
- With WR/RD set to "1" in the IFx command mask register, and NewDat to "0" in the IFx message
control register, NewDat for particular object can be reset by writing of the IFx command request
register.
- NewDat is reset after transferring the data to the send shift register (internal register).
See the table below for the data renewal bit in the CAN macro which loads the 32 message buffer or more:
addr + 0
addr + 1
addr + 2
addr + 3
NEWDT4 &
NEWDT3
NewDat64 to
NewDat33
(address 94H)
NewDat64 to
NewDat57
NewDat56 to
NewDat49
NewDat48 to
NewDat41
NewDat40 to
NewDat33
NEWDT6 &
NEWDT5
NewDat96 to
NewDat65
(address 98H)
NewDat96 to
NewDat89
NewDat88 to
NewDat81
NewDat80 to
NewDat73
NewDat72 to
NewDat65
NEWDT8 &
NEWDT7
NewDat128 to
NewDat97
(address 9CH)
NewDat128 to
NewDat121
NewDat120 to
NewDat113
NewDat112 to
NewDat105
NewDat104 to
NewDat97
335
CHAPTER 11 CAN CONTROLLER
11.4.4.3
CAN Interrupt Pending Register (INTPND1, INTPND2)
The CAN interrupt pending registers (INTPND1 and INTPND2) indicate the IntPnd bit of
all the message objects. It is possible to check which message object is in interrupt
pending, by reading the IntPnd bit.
■ Register Configuration
CAN interrupt pending register 2 (Upper byte)
Address
bit15
bit14
bit13
R
R
R
Base+A0H
bit12
bit11
IntPnd32 to IntPnd25
R
R
bit10
bit9
bit8
R
R
R
bit2
bit1
bit0
R
R
R
bit10
bit9
bit8
R
R
R
bit2
bit1
bit0
R
R
R
Initial value
00000000B
CAN interrupt pending register 2 (Lower byte)
Address
bit7
bit6
bit5
R
R
R
Base+A1H
bit4
bit3
IntPnd24 to IntPnd17
R
R
Initial value
00000000B
CAN interrupt pending register 1 (Upper byte)
Address
bit15
bit14
bit13
R
R
R
Base+A2H
bit12
bit11
IntPnd16 to IntPnd9
R
R
Initial value
00000000B
CAN interrupt pending register 1 (Lower byte)
Address
bit7
bit6
bit5
R
R
R
Base+A3H
R:
336
Read only
bit4
bit3
IntPnd8 to IntPnd1
R
R
Initial value
00000000B
CHAPTER 11 CAN CONTROLLER
■ Register Function
IntPnd16 to IntPnd1: Interrupt pending bits
IntPnd16 to IntPnd1
Function
0
Without interrupt cause
1
With interrupt cause
Set and reset conditions of IntPnd bit are shown in the following.
• Set condition
- With TxIE set to "1", IntPnd is set when the frame is successfully sent.
- With RxIE set to "1", IntPnd is set when reception of the frame, having passed through the
acceptance filter, is successfully completed.
• Reset condition
- With WR/RD set to "1" and IntPnd to "1" in the IFx command mask register, IntPnd for particular
object can be reset by writing of the IFx command request register.
See the table below for the interrupt pending bit in the CAN macro which loads the 32 message buffer or
more:
addr + 0
addr + 1
addr + 2
addr + 3
INTPND4 &
INTPND3
IntPnd64 to
IntPnd33
(address A4H)
IntPnd64 to
IntPnd57
IntPnd56 to
IntPnd49
IntPnd48 to
IntPnd41
IntPnd40 to
IntPnd33
INTPND6 &
INTPND5
IntPnd96 to
IntPnd65
(address A8H)
IntPnd96 to
IntPnd89
IntPnd88 to
IntPnd81
IntPnd80 to
IntPnd73
IntPnd72 to
IntPnd65
INTPND8 &
INTPND7
IntPnd128 to
IntPnd97
(address ACH)
IntPnd128 to
IntPnd121
IntPnd120 to
IntPnd113
IntPnd112 to
IntPnd105
IntPnd104 to
IntPnd97
337
CHAPTER 11 CAN CONTROLLER
11.4.4.4
CAN Message Valid Register (MSGVAL1, MSGVAL2)
The CAN message valid registers (MSGVAL1 and MSGVAL2) indicate the MsgVal bit of
all the message objects. It is possible to check which message object is valid, by
reading the MsgVal bit.
■ Register Configuration
CAN message enable register 2 (Upper byte)
Address
bit15
bit14
bit13
R
R
R
Base+B0H
bit12
bit11
MsgVal32 to MsgVal25
R
R
bit10
bit9
bit8
R
R
R
bit2
bit1
bit0
R
R
R
bit10
bit9
bit8
R
R
R
bit2
bit1
bit0
R
R
R
Initial value
00000000B
CAN message enable register 2 (Lower byte)
Address
bit7
bit6
bit5
R
R
R
Base+B1H
bit4
bit3
MsgVal24 to MsgVal17
R
R
Initial value
00000000B
CAN message enable register 1 (Upper byte)
Address
bit15
bit14
bit13
R
R
R
Base+B2H
bit12
bit11
MsgVal16 to MsgVal9
R
R
Initial value
00000000B
CAN message enable register 1 (Lower byte)
Address
bit7
bit6
bit5
R
R
R
Base+B3H
R:
338
Read only
bit4
bit3
MsgVal8 to MsgVal1
R
R
Initial value
00000000B
CHAPTER 11 CAN CONTROLLER
■ Register Function
MsgVal16 to MsgVal1: Message enable bit
MsgVal16 to MsgVal1
Function
0
Message object is invalid.
The message is not sending and receiving.
1
Message object is valid.
The message is able to be sending and receiving.
Set and reset conditions of MsgVal bit are shown in the following.
• Set condition
- With MsgVal set to "1" in the IFx arbitration register 2, MsgVal for particular object can be set by
writing into the IFx command request register.
• Reset condition
- With MsgVal set to "0" in the IFx arbitration register 2, MsgVal for particular object can be reset by
writing of the IFx command request register.
See the table below for the message enable bit in the CAN macro which loads the 32 message buffer or
more:
addr + 0
addr + 1
addr + 2
addr + 3
MSGVAL4 &
MSGVAL3
MsgVal64 to
MsgVal33
(address A4H)
MsgVal64 to
MsgVal57
MsgVal56 to
MsgVal49
MsgVal48 to
MsgVal41
MsgVal40 to
MsgVal33
MSGVAL6 &
MSGVAL5
MsgVal96 to
MsgVal65
(address A8H)
MsgVal96 to
MsgVal89
MsgVal88 to
MsgVal81
MsgVal80 to
MsgVal73
MsgVal72 to
MsgVal65
MSGVAL8 &
MSGVAL7
MsgVal128 to
MsgVal97
(address ACH)
MsgVal128 to
MsgVal121
MsgVal120 to
MsgVal113
MsgVal112 to
MsgVal105
MsgVal104 to
MsgVal97
339
CHAPTER 11 CAN CONTROLLER
11.4.5
CAN Prescaler Register (CANPRE)
The CAN prescaler register (CANPRE) defines the division ratio of the clock provided to
the CAN interface. If you change the value of this register, set the initialize bit (Init) in
the CAN control register (CTRLR) to "1" and stop all the bus operations.
■ Register Configuration
CAN prescaler register
Address
01A8H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved Reserved Reserved Reserved CANPRE3 CANPRE2 CANPRE1 CANPRE0
R
R
R
R
R/W
R/W
R/W
Initial value
00000000B
R/W
R/W: Readable/Writable
R:
Read only
■ Register Function
[bit15 to bit12] Reserved: Reserved bits
These bits read "0000B".
Write is not reflected to registers.
[bit11 to bit8] CAN prescaler setting bits
CANPRE[3:0]
Function
0000
System clock is selected as CAN clock. [initial value]
0001
1/2-cycle of system clock is selected as CAN clock.
001x
1/4-cycle of system clock is selected as CAN clock.
01xx
1/8-cycle of system clock is selected as CAN clock.
1000
2/3-cycle of system clock is selected as CAN clock.
Duty of clock is 67%.
1001
1/3-cycle of system clock is selected as CAN clock.
101x
1/6-cycle of system clock is selected as CAN clock.
11xx
1/12-cycle of system clock is selected as CAN clock.
• If you want to modify the CAN prescaler setting bit, you must first set the initialize bit in the CAN
control register to "1" and stop all the bus operations.
• The clock provided to the CAN interface must be 16MHz or less, according to the settings of this
register.
340
CHAPTER 11 CAN CONTROLLER
11.5
CAN Functions
This section explains the operation and functions of CAN controller.
■ The Following Functions are Explained.
• Message Object
• Message Transmission Operation
• Message Reception Operation
• FIFO Buffer Function
• Interrupt Function
• Bit Timing
• Test Mode
• Software Initialization
• CAN Clock Prescaler
341
CHAPTER 11 CAN CONTROLLER
11.5.1
Message Object
This section describes the message objects and interfaces of the message RAM.
■ Message Object
The message object settings for the message RAM (except the MsgVal, NewDat, IntPnd, and TxRqst bits)
are not initialized by the resetting of hardware. Therefore, initialize message objects by the CPU or set the
MsgVal bit to invalid (MsgVal=0). Also, set the CAN bit timing register when the Init bit in the CAN
control register is "0".
After setting a message object in the message interface registers (IFx mask register, IFx arbitration register,
IFx message control register, IFx Data Register), the message number is written into the IFx command
request register so that the data in the interface register is transferred to the specified message object.
CAN controller starts the operation after clearing Init bit in the CAN control register to "0". After passing
through the acceptance filter, a receive message is stored in the message RAM. When a transmission
request for a message is pending, the message is transferred from the message RAM to the shift register in
the CAN controller, and transmitted to the CAN bus.
The CPU reads a receive message and updates a transmit message via message interface register. Also, the
CPU is interrupted depending on the settings of the CAN control register and IFx message control register
(message object).
342
CHAPTER 11 CAN CONTROLLER
■ Data Sending and Receiving with Message RAM
BUSY bit in the IFx command request register is set to "1" when data transfer is started between the
message interface register and the message RAM. After transmission is completed, the BUSY bit is cleared
to "0". (See Figure 11.5-1.)
The IFx command mask register sets either full or partial data transfer method for transferring a message
object. Because of the message RAM structure, a message object is always written full data, not a single
bit/byte, into the message RAM. Therefore, the data transfer from the message interface register to the
message RAM requires a read-modify-write execution cycle.
Figure 11.5-1 Data Transmission of Message Interface Register and Message RAM
Start
NO
Write to IFx command
request register
YES
BUSY = 1
Interrupt = 0
NO
WR/RD = 1
YES
Read from message RAM to message
interface register
Read from message RAM to message
interface register
Write from message interface register to
message RAM
BUSY = 0
Interrupt = 1
343
CHAPTER 11 CAN CONTROLLER
11.5.2
Message Transmission Operation
Setting method and transmission operation of transmission message object are
explained.
■ Message Transmission
If no data is transferred between the message interface register and the message RAM, a MsgVal bit in the
CAN message enable register and a TxRqst bit in the CAN transmission request register are evaluated.
While a transmission request is pending, the valid message object with the highest priority is transferred to
the shift register used for transmission. At that time, the NewDat bit of the message object is reset to "0".
When the transmission is completed successfully, the TxRqst bit will be reset to "0" if no new data is found
in the message object (NewDat=0). If TxIE is "1", IntPnd bit will be set to "1" after the transmission is
completed successfully. If the CAN controller has lost the arbitration on the CAN bus or if an error
occurred during the transmission, the message will be retransmitted as soon as the CAN bus becomes idle
again.
■ Transmission Priority
The transmission priority of the message object is determined by the message number. Message object 1 is
the highest priority and message object 32 (or the number of the maximum message objects installed) is the
lowest priority. So if two or more transmission requests are pending, the message object with the smaller
number is transferred first.
344
CHAPTER 11 CAN CONTROLLER
■ Setting of Transmission Message Object
Figure 11.5-2 shows initialization method of transmission object.
Figure 11.5-2 Initialization of Transmission Message Object
MsgVal
Arb
Data
Mask
EoB
Dir
1
appl.
appl.
appl.
1
1
NewDat MsgLst RxIE
0
0
0
TxIE
appl.
IntPnd RmtEn TxRqst
0
appl.
0
IFx arbitration registers (ID28 to ID0 and Xtd bits) are given by the application, and define the ID and type
of the transmission message.
When a standard frame (11-bit ID) is set, ID28 to ID18 are valid for use and ID17 to ID0 are invalid. When
the extended frame (29-bit ID) is set, ID28 to ID0 are valid for use.
If the TxIE bit is set to "1", the IntPnd bit will be set to "1" after the transmission of the message object is
completed successfully.
If the RmtEn bit is set to "1", the TxRqst bit will be set to "1" and the data frame is transmitted
automatically after the matching remote frame is received.
The application sets the setting of data registers (DLC3 to DLC0, Data0 to Data7).
If Umask=1, IFx mask registers (Msk28 to Msk0, UMask, MXtd, MDir bits) are used to receive the remote
frames, which have an ID grouped according to the mask setting, and then used to allow the transmission
(set TxRqst bit to "1"). For details, see remote frame section in section "11.5.3 Message Reception
Operation".
Note:
It is prohibited to set the Dir bit of the IFx mask register to mask enabled.
■ Update of Transmission Message Object
CPU can update the transmit message object data via the message interface registers.
The transmit message object data is written in 4-byte units of the corresponding IFx data registers (IFx data
register A, IFx data register B unit). For this reason, the transmit message object cannot be changed in 1byte units.
When only 8-byte data is updated, first of all, 0087H is written to the IFx command mask register. And
then, the transmit message object data (8-byte data) is updated and the TxRqst bit is set to "1" concurrently
by writing the message number into the IFx command request register.
To transmit uninterruptedly the message number during transmission, set the TxRqst bit and NewDat to
"1". A continuous transmission becomes possible without resetting the TxRqst bit to "0".
When both NewDat bit and TxRqst bit are "1", the NewDat bit will be reset to "0" as soon as the new
transmission starts.
• When updating data, it must be done by 4-byte units of the IFx data register A or IFx data register B.
• If only data is to be updated, set NewDat bit and TxRqst bit to "1".
345
CHAPTER 11 CAN CONTROLLER
11.5.3
Message Reception Operation
The setup method and reception operation of the message reception object are
described below.
■ Acceptance Filter of Reception Message
When the arbitration/control fields (ID + IDE + RTR + DLC) of a message are completely shifted into the
shift register in the CAN controller for reception, a scan on the message RAM starts for matching with
valid message objects.
At this time, arbitration field and mask data (including MsgVal, UMask, NewDat, and EoB) are loaded
from the message object of the message RAM, and the message object and arbitration field of the shift
register are compared including the mask data.
This is repeated until a matching between the message object and the arbitration field of the shift register is
found or until the end word of the message RAM is reached. If a match is found, the scan on the message
RAM is stopped and the CAN controller proceeds its process depending on the reception frame type (data
frame or remote frame).
■ Reception Priority
The priority of the message object reception is determined by the message number. Message object 1 is the
highest priority and message object 32 (or the number of the maximum message objects installed) is the
lowest priority. So if two or more objects are matched with the acceptance filter, the message object with
the smaller number becomes a receive message object.
■ Data Frame Reception
CAN controller transfers a received message from the shift register to the message RAM of the message
object which matched with the acceptance filter, and stores it in the RAM. Not only the data bytes, but also
all arbitration fields and data length codes are stored as data. This is executed even if a mask is set to the
IFx mask register (It is stored to keep ID and data bytes).
The NewDat bit is set to "1" when new data is received. Reset NewDat bit to "0" when CPU reads the
message object. When receiving a message if the NewDat bit is already set to "1", this indicates the
previous data has been lost and the MsgLst will be set to "1".
If the RxIE bit is set to "1", the IntPnd bit in the CAN interrupt pending register is set to "1" when a
message buffer is received. At that time, TxRqst bit of the message object is reset to "0". This is performed
to prevent the transmission process when receiving the requested data frame while the transmission of
remote frame is processing.
346
CHAPTER 11 CAN CONTROLLER
■ Remote Frame
Operating when a remote frame is received has the following three processes. The process for the remote
frame reception is selected by the setting of the matched message object.
1) Dir=1 (direction of transmission), RmtEn=1, UMask=1 or 0
The matched remote frame is received and only the TxRqst bit for this message object is set to "1", and
then the data frame corresponding to the remote frame replies (transmits) automatically (Message objects
other than the TxRqst bit are not changed).
2) Dir=1 (direction of transmission), RmtEn=0, UMask=0
Even if the received remote frame matches with the message object, the remote frame is not received and
invalidated (The TxRqst bit of this message object is not changed).
3) Dir=1 (direction of transmission), RmtEn=0, UMask=1
If the received remote frame matches with the message object, the TxRqst bit of this message object is
reset to "0", and the remote frame is processed like a received data frame. The received arbitration field
and control field (ID + IDE + RTR + DLC) are stored in the message object of the Message RAM, and
the NewDat bit of this message object is set to "1". The data field of the message object is not changed.
■ Setting of Reception Message Object
The method of initializing the reception message object is indicated in Figure 11.5-3.
Figure 11.5-3 Initialization of Reception Message Object
MsgVal
Arb
Data
Mask
EoB
Dir
1
appl.
appl.
appl.
1
0
NewDat MsgLst
0
0
RxIE
TxIE
appl.
0
IntPnd RmtEn TxRqst
0
0
0
IFx arbitration registers (ID28 to ID0 and Xtd bits) are given by the application, and define the ID and type
of reception message used in the acceptance filter.
When a standard frame (11-bit ID) is set, ID28 to ID18 are valid use and ID17 to ID0 are invalid.
Moreover, when a standard frame is received, ID17 to ID0 are reset to "0". When the extended frame (29bit ID) is set, ID28 to ID0 are valid for use.
If the RxIE bit is set to "1", the IntPnd bit will be set to "1" after the received data frame is stored in the
message object.
Data length codes (DLC3 to DLC0) are given by the application. When the CAN controller stores a
received data frame into the message object, a received data length code and 8-byte data are stored. If the
data length code is less than 8, undefined data will be written into the remaining datas of the message
object.
If Umask=1, IFx Mask Registers (Msk28 to Msk0, UMask, MXtd, MDir bit) are used to allow the
reception of the data frames which have IDs grouped by the mask setting. For details, see data frame
reception in "11.5.3 Message Reception Operation".
Note:
The mask setting of the Dir bit of the IFx mask register is prohibited.
347
CHAPTER 11 CAN CONTROLLER
■ Message Reception Process
CPU can read the received message at any time via the message interface registers.
Usually "007FH" is written in the IFx command mask register. Then, the message number of the message
object is written into the IFx command request register. In this order, the received message with the
specified message number is transferred from the message RAM to the message interface register. At this
time, NewDat bit and IntPnd bit of the message object can be cleared to "0" by setting the IFx command
mask register to do so.
In the process of receiving a message, a message is received when it is matched with the acceptance filter.
If the acceptance filter mask is used in the message object, the data with mask setting is excluded and the
filter determines whether or not to receive the message.
NewDat bit shows whether a new message has been received since the message object was read last time.
MsgLst bit shows the previous data has been lost because a new receive data was received before the
received data from the message object was read. The MsgLst bit is not automatically reset.
During the remote frame transmission process, if the matching data frame is received by the acceptance
filter, the TxRqst bit will be automatically reset to "0".
348
CHAPTER 11 CAN CONTROLLER
11.5.4
FIFO Buffer Function
The structure and the operation of the FIFO buffer of the message object in receive
message process are described below.
■ Configuration of The FIFO Buffer
With the exception of the EoB bit, the configuration of a received message object of the FIFO buffer is the
same as the configuration of a received message object (For details, see receive message object settings in
"11.5.3 Message Reception Operation").
The FIFO buffer uses two or more received message objects by connecting them. To store the received
message into this FIFO buffer, the settings of the received message object ID and mask must be matched
when the ID and mask are used.
The first received message object of the FIFO buffer is the message object with the lowest message
number, higher priority. The last received message object of the FIFO buffer needs to show the ending of
the FIFO buffer block by setting EoB bit to "1" (The EoB bit of all message objects with a FIFO buffer
configuration except the last one have to be set to "0").
• The settings of the message object ID and the mask should be same when the ID and mask are used in
the FIFO buffer.
• Please set "1" to the EoB bit when you do not use the FIFO buffer.
■ Message Reception with FIFO Buffer
When a received message matches with the FIFO buffer ID, the message is stored into the received
message object of the FIFO buffer with the lowest message number.
After a message is stored into the received message object of the FIFO buffer, the NewDat bit of this
receive message object is set to "1". If a NewDat bit is set to the received message object which EoB bit is
"0", the received message object will be protected and not be written until reaching the last received
message object (EoB bit=1) when writing into the FIFO buffer by the CAN controller.
If the valid data is stored through to the last FIFO buffer but the NewDat bit of the received message object
has not been set to "0" (canceling of the writing protection), the next received message will be written into
the last message object and so the message will be overwritten.
349
CHAPTER 11 CAN CONTROLLER
■ Reading from FIFO Buffer
CPU can read the contents of the received message object by writing the received message number to the
IFx command request register so that the contents are transferred to the message interface register and
retrieved. At this time, set WR/RD of the IFx command mask register to "0" (read), TxRqst/NewDat to "1",
and IntPnd to "1", and reset the NewDat bit and IntPnd bit to "0".
To ensure the FIFO buffer function, the received message object of the FIFO buffer should be read from
the one having the smallest message number. The CPU process method of the message object connected by
the FIFO buffer is shown in Figure 11.5-4.
Figure 11.5-4 CPU Processing in FIFO Buffer
Start
Message interrupt
Read CAN interrupt
register
8000H
0000H
Value of CAN
interrupt register
Other than 8000H, 0000H
State interrupt
processing execution
End
(normal process)
Message number =
CAN interrupt register value
Writing of IFx command request register
(message number)
Reading of message interface register
(Reset: NewDat=0, IntPnd=0)
Reading of IFx message control register
NO
NewDat = 1
YES
Reading of IFx message data register
A and B
YES
EoB = 1
NO
Message number = message number +1
350
CHAPTER 11 CAN CONTROLLER
11.5.5
Interrupt Function
The interrupt processes by a status interrupt (IntId=8000H) and a message interrupt
(IntId message number) are described below.
If more than one interrupts are pending, CAN interrupt register shows the interrupt code with the highest
priority in pending status. The time orders set in the interrupt codes are ignored, the interrupt code with the
highest priority is always displayed. The interruption code is kept until CPU clears.
The status interruption (IntId bit = 8000H) becomes the highest priority.
The priority of the message interrupt is higher for a message with a smaller message number, and lower for
a message with a bigger message number.
The message interrupt is cleared by clearing the IntPnd bit of the message object. The status interrupt is
cleared by reading the CAN status register.
The IntPnd bit of the CAN interruption pending register indicates the existence of the interruption. The
IntPnd bit indicates "0" when there is no interruption during a pending state.
When the IE bit in the CAN control register, and the TxIE bit and RxIE bit in the IFx message control
register are all "1", the interrupt signal to the CPU is active by setting the IntPnd bit to "1". The interrupt
signal remains active until the CAN interrupt pending register is cleared to "0" (interrupt factor reset) or the
IE bit in the CAN control register is reset to "0".
If the CAN interrupt register is 8000H, the CAN status register shows the updates by the CAN controller,
and this interruption becomes the highest priority. The interruption by the update of the CAN status register
can control the permission or prohibition of settings in the CAN interrupt register by EIE bit and SIE bit in
the CAN control register. Also, the IE bit of the CAN control register can control interrupt signals to the
CPU.
RxOk bit, TxOk bit and LEC bit in the CAN status register can be updated (reset) by writing from the CPU,
but the writing cannot set or reset the interruptions.
When the CAN interrupt register is any value except 8000H and 0000H, it shows the message interrupt is
pending and shows a pending message interruption with the highest priority.
Even when IE is reset, the CAN interruption register is updated.
The factors of the message interrupt to the CPU can be identified by the CAN interrupt register or CAN
interrupt pending register (See "11.4.4 Message Handler Register"). When the message interrupt is cleared,
a message data can be read at the same time. When the message interrupt shown in the CAN interrupt
register is cleared, the next interruption with the second highest priority will be set into the CAN interrupt
register and wait for the next interruption process. The CAN interruption register indicates 0000H when
there is no interruption.
• The status interrupt (IntId=8000H) is cleared by accessing to the CAN status register for reading.
• The status interrupt (IntId=8000H) is not generated by accessing to the CAN status register for writing.
351
CHAPTER 11 CAN CONTROLLER
11.5.6
Bit Timing
The overview of the bit timing and the bit timing in the CAN controller are described
below.
Each CAN node of the CAN network has its own clock generator (usually a quartz oscillator). The time
parameter of the bit time can be configured individually for each CAN node. A common bit rate is created
even if the CAN node oscillator periods (fosc) are different.
The frequencies of these oscillators are slightly variant due to the temperature or voltage changes, and
components deterioration. As long as the variations remain in the oscillator tolerance range (df), the CAN
nodes are able to compensate for the different bit rates by resynchronizing to the bit stream.
According to the CAN specification, the bit time is divided into four segments (see Figure 11.5-5),
comprising a Synchronization Segment (Sync_Seg), a Propagation Time Segment (Prop_Seg), a Phase
Buffer Segment 1(Phase_Seg1), and a Phase Buffer Segment 2 (Phase_Seg2). Each segment consists of a
programmable number of time quanta (see Table 11.5-1). The length of the time quantum (tq), which is the
basic time unit of the bit time, is defined by the CAN controller system clock fsys and the Baud Rate
Prescaler (BRP):
tq = BRP / fsys
The CAN system clock fsys is the frequency of its clock input (See Figure 11.5-6). The Synchronization
Segment Sync_Seg is the timing in the bit time where edges of the CAN bus are expected. Prop_Seg in the
propagation time segment makes amends for physical delay time in the CAN network. Phase_Seg1 and
Phase_Seg2 in the phase buffer segment specify the sampling point. The Resynchronization Jump Width
(SJW) defines how far a resynchronization may move the Sample Point to compensate edge phase errors.
Figure 11.5-5 Bit Timing
1-bit time (BT)
Sync
_Seg
Prop_Seg
1 time quanta
(tq)
352
Phase_Seg1
Phase_Seg2
Sampling point
CHAPTER 11 CAN CONTROLLER
Table 11.5-1 Parameter of CAN Bit Time
Parameter
Range
Function
BRP
[1 to 32]
Sync_Seg
1 tq
Prop_Seg
[1 to 8] tq
Physical delay time compensation
Phase_Seg1
[1 to 8] tq
Edge phase error guarantee before sample point
There is a possibility to be lengthened temporarily by synchronization.
Phase_Seg2
[1 to 8] tq
Edge phase error guarantee after point of sample
There is a possibility to be shortened temporarily by synchronization.
SJW
[1 to 4] tq
Jump width of re-synchronization
It does not become longer than either phase buffer.
Definition of tq in length of time quantum
Synchronization to the fixed length system clock
The bit timing in the CAN controller is indicated as follows.
Figure 11.5-6 Bit Timing on CAN Controller
1-bit time (BT)
Sync
_Seg
TEG1
1 time quanta
(tq)
TEG2
Sampling point
Table 11.5-2 Parameter of CAN Controller
Parameter
Range
Function
BRPE,BRP
[0 to 1023]
Definition of tq in length of time quantum
The prescaler can be extended up to 1024 by the bit-timing register and
BRP extension register.
Sync_Seg
1 tq
TSEG1
[1 to 15] tq
It is a time segment before the sampling point.
It corresponds to Prop_Seg and Phase_Seg1.
It is controlled by a bit timing register.
TSEG2
[0 to 7] tq
It is a time segment after the point of sampling.
It corresponds to Phase_Seg2.
It is controlled by a bit timing register.
SJW
[0 to 3] tq
Jump width of re-synchronization.
It is controlled by a bit timing register.
Synchronization to the system clock.
Fixed length.
353
CHAPTER 11 CAN CONTROLLER
The relation of each parameter is indicated as follows.
tq
= ([BRPE,BRP]+1) / fsys
BT
= SYNC_SEG + TEG1 + TEG2
= (1 + (TSEG1 + 1) + (TSEG2 + 1)) × tq
= (3 + TSEG1 + TSEG2) × tq
354
CHAPTER 11 CAN CONTROLLER
11.5.7
Test Mode
It explains the setting method and operation of the test mode.
■ Test Mode Setting
The test mode is entered by setting the Test bit in the CAN control register to 1. In the test mode, the Tx1,
Tx0, LBack, Silent, Basic bits in the CAN test register become valid.
All test register functions are disabled when the Test bit in the CAN control register is reset to "0".
■ Silent Mode
CAN controller is set to the silent mode when the Silent bit in the CAN test register is set to "1".
In silent mode, the data frames and remote frames can be received, but outputting only recessive bits on the
CAN bus and the transmission of messages and ACK will not occur.
If the CAN controller is required to send dominant bits (ACK bit, overload flag, active error flag), they are
transmitted to the RX side with the return circuit in the CAN controller. In this operation, the receiving side
receives dominant bits which are transmitted by return in the CAN controller, even being recessive state on
the CAN bus.
The silent mode can be used to analyze the traffic on a CAN bus without effect from the transmission of
dominant bits (ACK bits, error flags).
Figure 11.5-7 shows the connection of signals CAN_TX and CAN_RX to the CAN controller in silent
mode.
Figure 11.5-7 CAN Controller at Silent Mode
CAN_TX
CAN_RX
CAN controller
Silent bit = 1
Tx
Rx
CAN Core
355
CHAPTER 11 CAN CONTROLLER
■ Loop Back Mode
The CAN controller can be set in loop back mode by setting the LBack bit in the CAN test register to "1".
The loop back mode can be used for the self-diagnosis function.
In loop back mode, TX side and RX side are connected within the CAN controller, the messages
transmitted by the CAN controller are treated as received messages at RX side, and stores them into a
reception buffer if they pass the acceptance filter.
Figure 11.5-8 shows the connection of signals CAN_TX and CAN_RX to the CAN controller in loop back
mode.
Figure 11.5-8 CAN Controller at Loop Back Mode
CAN_TX
CAN_RX
Tx
Rx
CAN controller
CAN Core
To be independent from external signals, dominant bits are not sampled in the acknowledge slot of the data/
remote frame in loop back mode. Therefore, the CAN controller normally makes acknowledge errors, but
in the test mode acknowledge errors will not occur.
356
CHAPTER 11 CAN CONTROLLER
■ Loop Back Combined with Silent Mode
It is also possible to operate loop back mode and silent mode conjointly by setting the LBack bit and Silent
bit in the CAN test register to "1" at the same time.
This mode can be used for the hot self-test. A hot self-test means that the CAN system's operation will not
be affected because recessive fixed output or input from the CAN_RX terminal is disabled for the
CAN_TX terminal during the CAN controller's testing in loop back mode.
Figure 11.5-9 shows connection of signals CAN_TX and CAN_RX to the CAN controller when silent and
loop back modes are combined.
Figure 11.5-9 CAN Controller with Combined Silent and Loop Back Modes
CAN_TX
CAN_RX
CAN controller
LBack bit and Silent bit = 1
Tx
Rx
CAN Core
357
CHAPTER 11 CAN CONTROLLER
■ Basic Mode
The CAN controller can be set in basic mode by setting the CAN test register's Basic bit to "1".
The CAN controller operates without message RAM in basic mode.
The IF1 message interface register is used for transmission control.
For message transmission, first, set what is transmitted to the IF1 message interface register. Then request
transmission by setting the IF1 command request register's BUSY bit to "1". The BUSY bit set to "1"
indicates that the IF1 message interface register is locked, or that transmission is on hold.
The CAN controller operates as follows when "1" is set to the BUSY bit.
As soon as the CAN bus becomes bus idle, the content of the IF1 message interface register is loaded for
the shift register for transmission, and then transmission begins. After transmission is normally completed,
the Busy bit is reset to "0" to free the IF1 message interface register to be locked.
When transmission is on hold, discontinuation is available any time by resetting the IF1 command request
register's BUSY bit to "0". In addition, resetting the BUSY bit to "0" during transmission will stop
retransmission that may occur due to arbitration lost or errors.
The IF2 message interface register is used for reception control.
All the receptions of the message are received without using the acceptance filter. The content of the
received message can be read by setting the IF2 command request register's Busy bit to "1".
The CAN controller operates as follows when "1" is set in the Busy bit.
• Received messages (content of the shift register for reception) are stored in the IF2 message interface
register without acceptance filter.
When a new message is stored in the IF2 message interface register, the CAN controller set the NewDat bit
to "1". In addition, in the case where an additional new message is received when the NewDat bit is 1, the
CAN controller sets the MsgLst to "1".
• In basic mode, all the message objects related with the control/status bits and control mode setting for
IFx command mask registers are invalid.
• The message number of the command request register is invalid.
• The IF2 message control register's NewDat bit and MsgLst bit operate as ordinary time. DLC3 to DLC0
indicate the received DLC, and other control bits are read as "0".
■ Software Control of CAN_TX Pin
Four output functions are provided in CAN_TX that is the CAN transmission pin.
• Serial data output (Normal output)
• CAN sampling point signal output to monitor the bit timing of the CAN controller
• Dominant fixed output
• Recessive fixed output
Dominant and recessive fixed output can be used to check the physical layer of the CAN bus along with the
CAN_RX monitoring function of the CAN reception terminal.
Output mode of the CAN_TX terminal can be controlled by the CAN test register's Tx1 and Tx0 bits.
Use of CAN message transmission or loop back, silent, and basic modes requires to set the CAN_TX to
serial data output.
358
CHAPTER 11 CAN CONTROLLER
11.5.8
Software Initialization
This section explains initialization with software.
The initialized factor by software is shown below.
• Hardware reset
• Setting of Init bit of CAN control register
• Transition to bus off state
Reset by hardware initializes everything except the message RAM (excluding MsgVal, NewDat, IntPnd
and TxRqst bits). Initialize the message RAM through the CPU or change the message RAM's MsgVal to
"0" after reset by hardware. Set the bit timing register, if applicable, before changing the CAN control
register's Init bit to "0".
The Init bit of the CAN control register is set to one on the following conditions.
• Write "1" from CPU
• Hardware reset
• Bus off
Setting the Init bit to "1" halts all the message transmission and reception in the CAN bus and changes the
CAN_TX terminal of CAN bus output to recessive output. (CAN_TX test mode is excluded.)
Setting the Init bit to "1" will change neither the error counter nor registers.
Setting the CAN control register's Init and CCE bits to "1" allows for setting of the bit timing register for
baud rate control and the BRP extension register.
Resetting the Init bit to "0" ends software initialization. Moreover, it can be executed to adjust the Init bit to
"0" only by the access from CPU.
Messages are transferred following synchronization with data transfer on the CAN bus by waiting for the
consecutive 11-bit recessive occurrence (= bus idle) after resetting the Init bit to "0".
Change the mask, ID, XTD, EoB, and RmtEn of message object during normal operation, if applicable,
after the MsgVal is set invalid.
359
CHAPTER 11 CAN CONTROLLER
11.5.9
CAN Clock Prescaler
This section explains the CAN clock switch during PLL's operating.
■ Block Diagram
The overview of CAN clock prescaler is indicated in the following block diagram.
The divide ratio of the clock supplied to the CAN interface will be determined in accordance with the
setting of the CANPRE bit in the CAN clock prescaler register.
CAN clock4
PLL
CAN clock3
Clock
Divider
CAN clock2
X0
Div by
CAN clock1
CANPRE
360
CAN clock0
CHAPTER 11 CAN CONTROLLER
■ Clock Switch Procedure
For how to switch the clock using the CAN clock prescaler, the following procedures are recommended.
Switching CAN clock :
OSCILLATOR -> PLL
Set bit Init in the CAN
Control Register
Switching CAN clock :
PLL -> OSCILLATOR
Set bit Init in the CAN
Control Register
Enable PLL
Set prescaler value
Wait for PLL Lock Time
Disable PLL
Set prescaler value
Reset bit Init in the CAN
Control Register
Reset bit Init in the CAN
Control Register
361
CHAPTER 11 CAN CONTROLLER
■ CAN Clock Prescaler Setting
The value that can be set to CAN clock prescaler is indicated.
The clock supplied to the CAN interface is the divided system clock in accordance with the set value of the
CAN clock prescaler.
CANPRE[3:0]
Function
At 32MHz system clock
32MHz
(Setting prohibited)
0000
The system clock is selected as the CAN clock. [initial value]
0001
1/2 cycles of the system clock is selected as CAN clock.
16MHz
001x
1/4 cycles of the system clock is selected as CAN clock.
8MHz
01xx
1/8 cycles of the system clock is selected as CAN clock.
4MHz
1000
2/3 cycles of the system clock is selected as CAN clock.
Duty of the clock is 67%.
21.33MHz
(Setting prohibited)
1001
1/3 cycles of the system clock is selected as CAN clock.
10.67MHz
101x
1/6 cycles of the system clock is selected as CAN clock.
5.33MHz
11xx
1/12 cycles of the system clock is selected as CAN clock.
2.67MHz
• If you want to modify the CAN prescaler setting bit, you must first set the initialize bit to "1" in the
CAN control register and stop all the bus operations.
• The clock provided to the CAN interface must be 16MHz or less, according to the settings of this
register.
362
CHAPTER 12
LIN-UART
This chapter explains functions and operation of LINUART.
12.1 Overview
12.2 Configuration of UART
12.3 Register of UART
12.4 UART Interrupt
12.5 UART Baud Rate
12.6 Operation of UART
12.7 Precautions when Using UART
363
CHAPTER 12 LIN-UART
12.1
Overview
UART (Universal Asynchronous Receiver and Transmitter) with LIN (Local Interconnect
Network) function is a general-purpose serial data communication interface to perform
asynchronous/synchronous communication with external devices. UART supports
bidirectional communication function (normal mode), master-slave communication
function (multiprocessor mode in master system), and LIN bus system (operating both
as master or slave device).
■ Overview
UART is a general-purpose serial data communication interface used for another CPU or the peripheral
circuit. UART is especially used for the data sending and receiving with the LIN device. Table 12.1-1
shows the UART functions.
Table 12.1-1 Functions of The UART (1 / 2)
Item
364
Function
Data buffer
Full-duplex double buffer
Serial input
Execute 5 times over-sampling and determine reception value in
asynchronous mode.
Transfer mode
• Clock synchronous
(Start/stop synchronous, start/stop bit selection)
• Clock asynchronous (using start/stop bit)
Transfer rate
• Dedicated 15-bit baud rate generator is contained.
• External clock input can be used and regulate in reload counter.
Data length
• 7 bits (unused in synchronous mode and LIN mode)
• 8 bits
Signal mode
NRZ
Start bit timing
Falling edge of start bit and clock synchronization in asynchronous
mode
Detection of receive error
• Framing error
• Overrun error
• Parity error
Interrupt request
•
•
•
•
Master-Slave communication
function (Multiprocessor mode)
One to multiple communication (one master to multiple slaves)
(This function is supported both for master and slave system.)
Synchronization mode
Functions as master or slave UART
Transmission/reception line
Direct access is enabled.
Receive interrupt (receive complete, detection of receive error)
Transmission interrupt (transmission complete)
Bus idle interrupt (belongs to reception interrupt)
LIN-Synch-Break interrupt (belongs to reception interrupt)
CHAPTER 12 LIN-UART
Table 12.1-1 Functions of The UART (2 / 2)
Item
Function
LIN bus option
•
•
•
•
•
Operation as master device
Operation as slave device
Generation of LIN-Synch-Break
LIN-Synch-Break detection
Start/Stop edge of LIN-Synch-Field is detected in ICU.
Synchronous serial clock
Synchronous serial clock can be outputted from SCK pin
continuously for synchronous communication using start/stop bit.
Clock delay option
Special synchronous clock mode for clock delay (for SPI)
■ UART Operation Modes
The UART operates in four different modes, which are set by the MD0 and MD1 bits of the serial mode
register (SMR). Mode 0 and mode 2 are used for bidirectional serial communication, mode 1 for master/
slave communication, and mode 3 for LIN master/slave communication.
Table 12.1-2 UART Operation Modes
Data length
Operating mode
Parity disable
0
Normal mode
1
Multiprocessor mode
2
Normal mode
3
LIN mode
Parity enable
7 or 8
7 or 8 + 1 *2
-8
8
--
Synchronization
mode
Length of
stop bit
Data bit
detection*1
Asynchronous
1 or 2
L/M
Asynchronous
1 or 2
L/M
Synchronous
0, 1 or 2
L/M
Asynchronous
1
L
*1: means the transfer format from LSB or MSB.
*2: "+1" means switching of address/data instead of a parity bit in the multiprocessor mode.
Note:
Mode 1 (multiprocessor mode) is supported both for master-slave operation of UART in a masterslave system. In Mode 3, the UART function is locked to 8N1-Format, LSB first.
365
CHAPTER 12 LIN-UART
If the mode is changed, UART stops the transmission or reception, waits and then transits to new operation.
Table 12.1-3 describes the operation mode set by MD1 and MD0 bits of the serial mode register (SMR).
Table 12.1-3 Setting of Mode Bit
366
MD1
MD0
Mode
Function
0
0
0
Asynchronous (Normal mode)
0
1
1
Asynchronous (Multiprocessor mode)
1
0
2
Synchronous (Normal mode)
1
1
3
Asynchronous (LIN mode)
CHAPTER 12 LIN-UART
12.2
Configuration of UART
This section explains the configuration of UART.
■ UART Block Diagram
UART is configured of the following blocks:
• Reload counter
• Reception control circuit
• Receive shift register
• Receive data register (RDR)
• Transmission control circuit
• Transmission shift register
• Transmit data register (TDR)
• Error detection circuit
• Over-sampling unit
• Interruption generation circuit
• LIN-Synch-Break and Sync-Field detection circuit
• Bus idle detection circuit
• Serial mode register (SMR)
• Serial control register (SCR)
• Serial status register (SSR)
• Extended communication control register (ECCR)
• Extended communication status/control register (ESCR)
367
CHAPTER 12 LIN-UART
■ UART Block Diagram
Figure 12.2-1 UART Block Diagram
PE
ORE
FRE
transmission clock
CLK
TIE
reception clock
Reload
Counter
SCK
RIE
RECEPTION
CONTROL
CIRCUIT
Pin
SIN
TRANSIMISSION
CONTROL
CIRCUIT
LBIE
LBD
Interrupt Generation
circuit
Start bit
Detetion circuit
Transmission
Start circuit
Received Bit
counter
Transmission
Bit counter
Received
Parity counter
Transmission
Parity counter
BIE
RBI
TBI
Pin
Restart Reception
Reload Counter
Oversampling
Unit
reception.
IRQ
TDRE
transmit.
IRQ
SOT
Pin
RDRF
reception
complete
SIN
Signal to
ICU
Reception
shift register
LIN break and
Synch Field
Detection circuit
SOT
SIN
Transmission
shift register
LIN break
generation
circuit
transmission
start
Error
Detection
RDR
Bus Idle
Detection circuit
TDR
STR
PE
ORE
FRE
RBI
TBI
LBD
Internal data bus
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
368
SSR
register
MD1
MD0
OTO
EXT
REST
UPCL
SCKE
SOE
SMR
register
PEN
P
SBL
CL
AD
CRE
RXE
TXE
SCR
register
LBIE
LBD
LBL1
LBL0
SOPE
SIOP
CCO
SCES
LBR
MS
ESCR
register
SSM
BIE
RBI
TBI
ECCR
register
LBR
LBL1
LBL0
CHAPTER 12 LIN-UART
■ Explanation of the Different Blocks
● Reload counter
The reload counter functions as the dedicated baud rate generator. Transmission/reception clock is
generated from external clock or internal clock. Reload counter has 15-bit registers for the reload value.
Actual count value of transmission reload counter can be read from the value of BGR0/BGR1.
● Reception control circuit
Reception control circuit consists of reception bit counter, start bit detection circuit and reception parity
counter.
Reception bit counter counts the reception data. When one data reception of specified data length is
completed, reception bit counter sets the reception data register full flag.
The start bit detection circuit detects start bits from the serial input signal and sends a signal to the reload
counter to synchronize it to the falling edge of these start bits.
The received parity counter calculates the parity of the received data.
● Receive shift register
The receive shift register fetches reception data input from the SIN pin, shifting the data bit by bit. When
reception is completed, the receive shift register transfers receive data to the receive data register (RDR).
● Receive data register (RDR)
This register retains reception data. Serial input data is converted and stored in this register.
● Transmission control circuit
The transmission control circuit consists of a transmission bit counter, transmission start circuit, and
transmission party counter.
The transmission bit counter counts transmission data bits. When the transmission of one data item of the
specified data length is completed, the transmission bit counter sets the transmission data register empty
flag. The transmission start circuit starts transmission when data is written to TDR. The transmission parity
counter generates a parity bit for data to be transmitted if parity is enabled.
● Transmission shift register
The transmission shift register shifts data written to the transmit data register (TDR) register and outputs
the data to the SOT pin in units of bit.
● Transmit data register (TDR)
The transmit data register sets transmission the transmit data. Data written to this register is converted to
serial data and outputted.
● Error detection circuit
The error detection circuit checks if there was any error during the last reception. If an error occurs, the
corresponding error flag is set.
369
CHAPTER 12 LIN-UART
● Over-sampling unit
The over-sampling unit over-samples the incoming data at the SIN pin for five times. It is switched off in
synchronous operation mode.
● Interruption generation circuit
The interruption generation circuit administers all cases of generating interrupt. If an interrupt is enabled,
the interrupt is generated immediately when the corresponding interrupt cause occurs.
● LIN-Break and Sync-Field detection circuit
The LIN-Break and LIN-Sync-Break detection circuit detects a LIN-Break, if a LIN master node is sending
a message handler. If a LIN-Break is detected a LBD flag bit is generated. The first and the fifth falling
edge of the Sync-Field is recognized by this circuit by generating an internal signal for the input capture
unit to measure the correct serial clock cycle of the transmitting master node.
● LIN-Break generation circuit
The LIN-Break generation circuit generates a LIN-Synch-Break of a determined length.
● Bus idle detection circuit
The bus idle detection circuit recognizes if neither reception nor transmission is going on (bus idle). In this
case, the circuit generates the flag bits TBI and RBI.
● Serial mode register (SMR)
The following operation is performed by the serial mode register.
- Selecting the UART operation mode
- Selecting the clock input
- Selecting whether the external clock is 1 to 1 connection or reload counter connection
- Restarting of dedicated reload timer
- Reset of UART (Register setting is saved.)
- Output enable of serial output pin (SOT)
- I/O switching of serial clock pin (SCK)
● Serial control register (SCR)
The following operations are performed by the serial control register.
- Specifying whether to provide parity bits
- Selecting parity bits
- Specifying a stop bit length
- Specifying data length
- Specifying a frame data format in mode 1
- Clears an error flag
- Enable transmission
- Enable reception
370
CHAPTER 12 LIN-UART
● Serial status register (SSR)
Serial status register is used for check of transmission/reception state and error state. This enables
transmission/reception interrupt and sets transmission direction (LSB first/MSB first).
● Extended status/control register (ESCR)
Extended status/control register is enabled to set the LIN function. Direct access to SIN and SOT pins and
the UART synchronous clock mode can be set.
● Extended communication control register (ECCR)
Extended communication control register is enabled to set the bus idle detection interrupt and synchronous
clock and to generate the LIN-Break.
371
CHAPTER 12 LIN-UART
12.3
Register of UART
Figure 12.3-1 shows a register of UART.
■ Register of UART
Figure 12.3-1 Register of UART
SCR
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
PEN
R/W
P
R/W
SBL
R/W
CL
R/W
AD
R/W
CRE
W
RXE
R/W
TXE
R/W
00000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
MD1
R/W
MD0
R/W
OTO
R/W
EXT
R/W
REST
W
UPCL
W
SCKE
R/W
SOE
R/W
00000000B
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
PE
R
ORE
R
FRE
R
RDRF
R
TDRE
R
BDS
R/W
RIE
R/W
TIE
R/W
00001000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D7
R/W
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
R/W
00000000B
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
LBIE
R/W
LBD
R/W
LBL1
R/W
LBL0
R/W
SOPE
R/W
SIOP
R/W
CCO
R/W
SCES
R/W
00000100B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
LBR
W
MS
R/W
SCDE
R/W
SSM
R/W
BIE
R/W
RBI
R
TBI
R
000000XXB
SMR
SSR
RDR / TDR
ESCR
ECCR
R/W:
R:
W:
X:
Readable/Writable
Read only
Write only
Undefined
(Continued)
372
CHAPTER 12 LIN-UART
(Continued)
BGR1
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
-
B14
R/W
B13
R/W
B12
R/W
B11
R/W
B10
R/W
B09
R/W
B08
R/W
00000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
B07
R/W
B06
R/W
B05
R/W
B04
R/W
B03
R/W
B02
R/W
B01
R/W
B00
R/W
00000000B
BGR0
R/W: Readable/Writable
373
CHAPTER 12 LIN-UART
12.3.1
Serial Control Register (SCR)
Serial control register (SCR) specifies the parity bit, selects the length of stop bit and
data, selects the frame data format in mode 1, clears the reception error flag, and
enables the transmission/reception.
■ Serial Control Register (SCR)
Figure 12.3-2 Bit Configuration of Serial Control Register (SCR)
SCR
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00000000B
PEN
P
SBL
CL
AD
CRE
RXE
TXE
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
R/W: Readable/Writable
W: Write only
[bit15] PEN: Parity enable bit
PEN
Parity enable
0
No Parity [Initial value]
1
With Parity
This bit selects to add to the transmission data in the serial asynchronous mode. The parity is detected at
reception.
The parity is added in mode 0. It is also added in mode 2 when the SSM bit of the ECCR is set. This bit
is fixed to "0" (without parity) in mode 3 (LIN mode).
[bit14] P: Parity selection bit
P
Parity selection
0
Even parity [Initial value]
1
Odd parity
If the parity is enabled, this bit selects the even parity (0) or odd parity (1).
[bit13] SBL: Stop-bit length select bit
SBL
Length of stop bit
0
1 bit [Initial value]
1
2 bits
This bit selects the stop bit length of the asynchronous data frame. When the SSM bit of the ECCR is set,
the stop bit length is selected by synchronous data frame. This bit is fixed to "0" (1 bit) in mode 3 (LIN
mode).
374
CHAPTER 12 LIN-UART
[bit12] CL: Data-length select bit
CL
Word (data frame) length
0
7 bits [Initial value]
1
8 bits
This bit specifies transmission/reception data length. In mode2 and mode3, this bit is fixed to "1" (8 bits).
[bit11] AD: Address/data select bit
AD
Address/data bit
0
Data bit [Initial value]
1
Address bit
This bit specifies the data format in multiprocessor mode 1. Writing to this bit is for master CPU, and
reading is for slave CPU. "1" and "0" show address frame and data frame respectively.
Note:
For using of AD bit, refer to "12.7 Precautions when Using UART".
[bit10] CRE: Receive error flag clear bit
Receive error clear
CRE
Write
Read
0
No effect [Initial value]
1
Clear all reception errors (PE, FRE, ORE).
Reading value is always "0".
This bit clears PE, FRE, and ORE flags of serial status register (SSR). This bit also clears reception error
interrupt factors.
Writing "1" clears the error flag. Writing "0" is no effect.
Reading always returns "0".
[bit9] RXE: Reception enable bit
RXE
Enable reception
0
Disable reception [Initial value]
1
Enable reception
This bit enables UART reception. When this bit is set to "0", UART stops reception of data frame. In
mode 0 and LIN-Break detection in mode 3 is invalid.
375
CHAPTER 12 LIN-UART
[bit8] TXE: Transmission enable bit
TXE
Enable transmission
0
Transmission disabled [Initial value]
1
Transmission enabled
This bit enables the transmission of UART. When this bit is set to "0", UART stops transmission of data
frame.
376
CHAPTER 12 LIN-UART
12.3.2
Serial Mode Register (SMR)
Serial mode register (SMR) selects the operation mode and baud rate clock. This
register specifies I/O direction of serial clock (SCK) and sets serial output enable also.
■ Serial Mode Register (SMR)
Figure 12.3-3 Bit Layout for The Serial Mode Register (SMR)
SMR
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
MD1
R/W
MD0
R/W
OTO
R/W
EXT
R/W
REST
W
UPCL
W
SCKE
R/W
SOE
R/W
00000000B
R/W: Readable/Writable
W: Write only
[bit7, bit6] MD1, MD0: Operation mode select bits
MD0
MD1
Operation mode setting
0
0
Mode 0: Asynchronous normal mode [Initial value]
1
0
Mode 1: Asynchronous multiprocessor mode
0
1
Mode 2: Synchronization mode
1
1
Mode 3: Asynchronous LIN mode
These bits set the operation mode of UART.
[bit5] OTO: 1 to 1 external clock select bit
OTO
External clock selection
0
External clock is used for baud rate generator (reload counter) [Initial value]
1
External clock is used as serial clock
When this bit is set, external clock is directly used as serial clock of UART. This function is used in
synchronous slave mode operating.
[bit4] EXT: External clock select bit
EXT
External serial clock enable
0
Built-in baud rate generator (reload counter) is used. [Initial value]
1
External clock is used as serial clock
This bit can select the clock for reload counter.
377
CHAPTER 12 LIN-UART
[bit3] REST: Transmission reload counter restart bit
Reload counter restart
REST
Write
0
No effect [Initial value]
1
Counter restart
Read
Reading value is always "0".
When "1" is written to this bit, reload counter is restarted. Writing "0" is no effect.
Reading is always "0".
[bit2] UPCL: UART clear bit (software reset)
UART clear (Software reset)
UPCL
Write
0
No effect [Initial value]
1
UART reset
Read
Reading value is always "0".
When "1" is written to this bit, UART is immediately reset but setting value of the register is saved.
Reception/transmission is paused.
Error flags are all cleared, and reception data register (RDR) becomes "00H".
Writing "0" is no effect.
Reading value returns always "0".
[bit1] SCKE: Serial clock output enable
SCKE
Serial clock output enable
0
External clock input [Initial value]
1
Internal clock output
This bit controls I/O of serial clock pin (SCK).
When this bit is "0", SCK pin operates as general-purpose port/serial clock input pin. When this is "1",
SCK pin becomes a serial clock output pin.
Note:
When SCK pin is used as serial clock input (SCKE=0), set the port to input. When used as serial clock
output, it is required to set the SCKE bit and the port function register (PFR) corresponding to SCK pin.
For details of port function register setting, refer to "CHAPTER 6 I/O PORT".
Select the external clock with external clock select bit (EXT=1).
378
CHAPTER 12 LIN-UART
[bit0] SOE: Serial-data output enable bit
SOE
Serial data output
0
SOT output disabled [Initial value]
1
SOT output enable
This bit enables serial output.
When this bit is "1", serial data output is enabled.
Note:
When SOT pin is used as serial output, it is required setting of SOE bit and corresponding port
function register (PFR). For details of port function register setting, refer to "CHAPTER 6 I/O PORT".
379
CHAPTER 12 LIN-UART
12.3.3
Serial Status Register (SSR)
Serial status register (SSR) checks the transmission/reception state and presence or
absence of error. This register also controls transmission or reception interrupt.
■ Serial Status Register (SSR)
Figure 12.3-4 Bit Configuration of Serial Status Register (SSR)
SSR
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
PE
R
ORE
R
FRE
R
RDRF
R
TDRE
R
BDS
R/W
RIE
R/W
TIE
R/W
00001000B
R/W: Readable/Writable
R:
Read only
[bit15] PE: Parity error flag bit
PE
Parity error
0
No parity error [Initial value]
1
Parity error occurred during reception
If parity error occurs during reception, this bit is set to "1". If "1" is written to CRE bit of serial control
register (SCR), this bit is cleared.
When this bit and RIE bit are "1", reception interrupt request is outputted.
When the flag is set, the data in the receive data register (RDR) is invalid.
[bit14] ORE: Overrun error flag bit
ORE
Overrun error
0
No overrun error [Initial value]
1
Overrun error occurred during reception
When overrun occurs during reception, this bit is set to "1". When "1" is written to CRE bit of serial
control register (SCR), this bit is cleared.
When this bit and RIE bit are "1", reception interrupt request is outputted.
When the flag is set, the data in the receive data register (RDR) is invalid.
380
CHAPTER 12 LIN-UART
[bit13] FRE: Framing error flag bit
FRE
Framing error
0
No framing error [Initial value]
1
Framing error occurred during reception
When framing error occurs during reception, this bit is set to "1". When "1" is written to CRE bit of serial
control register (SCR), this bit is cleared.
When this bit and RIE bit are "1", reception interrupt request is outputted.
When the flag is set, the data in the receive data register (RDR) is invalid.
[bit12] RDRF: Receive data full flag bit
RDRF
Reception data register full
0
No data in reception data register [Initial value]
1
Data in reception data register
This flag indicates the status of the reception data register (RDR).
When reception data is stored in RDR, this bit is set to "1". Only RDR reading clears to "0".
When this bit and RIE bit are "1", reception interrupt request is outputted.
[bit11] TDRE: Transmission data empty flag bit
TDRE
Transmission data register empty
0
Data in transmission data register
1
No data in transmission data register [Initial value]
This flag indicates the status of the transmission data register (TDR).
When transmission data is written to TDR, this bit is cleared to "0". When data is stored to transmission
shift register and transmission starts, this bit is set to "1".
When this bit and TIE bit are "1", transmission interrupt request is outputted.
[bit10] BDS: Transfer direction selection bit
BDS
Bit direction setting
0
Transmission/reception is LSB first [Initial value]
1
Transmission/reception is MSB first
This bit selects whether to transfer the serial transfer data from LSB first (BDS=0) or MSB first
(BDS=1).
This bit is fixed to "0" in mode 3 (LIN mode).
381
CHAPTER 12 LIN-UART
Note:
Because the high-order and low-order sides of the serial data are switched when the serial data
register is written to or read, the data will become invalid if the bit is rewritten after data is written to
the RDR register.
[bit9] RIE: Reception interrupt request enable bit
RIE
Reception interrupt request enable
0
Reception interrupt disable [Initial value]
1
Reception interrupt enable
This bit controls reception interrupt request to CPU.
After this bit is set, when reception data flag bit (RDRF) is "1" or error flag (PE, ORE, FRE) is set,
reception interrupt request is transmitted.
[bit8] TIE: Transmission interrupt request enable bit
TIE
Transmission interrupt request enable
0
Disable transmission interrupts [Initial value]
1
Transmission interrupt enable
This bit controls transmission interrupt request to CPU.
When this bit is set and TDRE bit becomes "1", transmission interrupt request is transmitted.
382
CHAPTER 12 LIN-UART
12.3.4
Reception/Transmission Data Register (RDR/TDR)
Reception data register (RDR) and transmission data register (TDR) retains the reception
data and transmission data respectively. RDR and TDR are assigned in the same address.
■ Reception/Transmission Data Register (RDR/TDR)
Figure 12.3-5 Reception/Transmission Data Register
RDR / TDR
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D7
R/W
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
R/W
00000000B
R/W: Readable/Writable
[bit7 to bit0] Data Register bits
Access
Data Register
Read
Read from reception data register
Write
Write to transmission data register
● Reception
RDR is the register that contains reception data. The serial data signal transmitted from the SIN pin is
converted in the shift register and stored in this register. When the data length is 7 bits, the MSB (D7) contains
"0". When reception is completed, the data is stored in this register and the reception data full flag bit (RDRF
bit in SSR) is set to "1". If a reception interrupt request is enabled at this time, a reception interrupt occurs.
Read RDR when the RDRF bit of the serial status register (SSR) is "1". The RDRF bit is cleared to "0"
automatically when RDR is read. Also the reception interrupt is cleared if it is enabled and no reception
error has occurred.
● Transmission
When data to be transmitted is written to the transmission data register in transmission enable state, it is
transferred to the transmission shift register, then converted to serial data, and transmitted from the serial
data output pin (SOT). If the data length is 7 bits, the MSB (D7) is not set.
When transmission data is written to this register, the transmission data empty flag bit (TDRE bit in SSR) is
cleared to "0". When transfer to the transmission shift register is completed, the TDRE bit is set to "1".
When the TDRE bit is "1", the next part of transmission data can be written to. If transmission interrupt
requests have been enabled, a transmission interrupt occurs. Write the next part of transmission data when a
transmission interrupt occurs or the TDRE bit is "1".
383
CHAPTER 12 LIN-UART
Note:
TDR is write only and RDR is read only. These registers are assigned in the same address, the
reading value is different from the writing value. So, do not access in read-modify-write instruction.
384
CHAPTER 12 LIN-UART
12.3.5
Extended Status/Control Register (ESCR)
Extended status/control register can set the LIN function. This register can also set the
direct access to SIN and SOT pins and UART synchronous clock mode.
■ Extended Status/Control Register (ESCR)
Figure 12.3-6 Bit Configuration of Extended Status/Control Register (ESCR)
ESCR
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
LBIE
R/W
LBD
R/W
LBL1
R/W
LBL0
R/W
SOPE
R/W
SIOP
R/W
CCO
R/W
SCES
R/W
00000100B
R/W: Readable/Writable
[bit15] LBIE: LIN-Break detection interrupt enable bit
LBIE
LIN-Break detection interrupt enable
0
LIN-Break interrupt disabled [Initial value]
1
LIN-Break interruption enable
When LIN-Break is detected, this bit enables the generated interruption.
[bit14] LBD: LIN-Break detection flag bit
LIN-Break detection
LBD
Write
Read
0
Clear of LIN-Break detection flag
No detection of LIN-Break [Initial value]
1
No effect
LIN-Break has been detected.
This bit will be set to "1" if LIN-Break is detected. Write "0" to clear this flag bit if LIN-Break detection
interrupt is enabled, the interrupt is also cleared.
Read-modify-write instruction always returns "1", but LIN-Break detection is meaningless in this case.
385
CHAPTER 12 LIN-UART
[bit13, bit12] LBL1, LBL0: LIN-Break length select bits
LBL0
LBL1
LIN-Break Length
0
0
LIN-Break length is 13 bits. [Initial value]
1
0
LIN-Break length is 14 bits.
0
1
LIN-Break length is 15 bits.
1
1
LIN-Break length is 16 bits.
These bits define serial bit length of LIN-Break generated by UART. LIN-Break reception is always
fixed to 11 bits.
[bit11] SOPE: Serial output pin direct access enable bit
SOPE
Serial output pin direct access
0
Serial output pin direct access disabled [Initial value]
1
Serial output pin direct access enabled
When this bit is set to "1", direct writing to SOT pin is enabled.
For details, refer to Table 12.3-1.
[bit10] SIOP: Serial I/O pin direct access enable bit
Serial input/output pin access
SIOP
Write (when SOPE is "1")
0
SOT is "0" output.
1
SOT is "1" output. [Initial value]
Read
The value of SIN is read.
In a normal reading instruction, this bit returns the value of SIN pin. Writing sets the value of SOT pin. In
a read-modify-write instruction, this bit returns the value of SOT.
For details, refer to Table 12.3-1.
Table 12.3-1 Functions of SOPE and SIOP
SOPE
SIOP
Writing into SIOP
0
R/W
No effect to SOT pin
Writing value is retained.
The value of SIN is read.
1
R/W
Writing value is outputted to SOT pin.
The value of SIN is read.
1
RMW*
The value of SOT pin is read and written.
*: The abbreviation of Read-Modify Write
386
Reading from SIOP
CHAPTER 12 LIN-UART
Note:
The setting value of this bit is enabled only when the TXE bit in the serial control register (SCR) is
set to "0".
[bit9] CCO: Continuous clock output enable bit
CCO
Continuous clock output (mode 2)
0
Continuous clock output disabled [Initial value]
1
Continuous clock output enabled
When UART operates in master mode 2 (synchronous mode) and SCK pin is set as output, consecutive
serial clock output in SCK is enabled.
[bit8] SCES: Serial clock edge select bit
SCES
Serial clock edge select
0
Sampling at rising edge of clock (normal) [Initial value]
1
Sampling at falling edge of clock (inversion clock)
This bit inverts the internal serial clock in mode 2 (synchronous mode). When UART operates in mode 2
master (synchronous mode) and SCK pin is set as output, output clock is also inverted.
In mode 2 slave, sampling edge changes from rising edge to falling edge.
387
CHAPTER 12 LIN-UART
12.3.6
Extended Communication Control Register (ECCR)
Extended communication control register (ECCR) enables setting of bus idle detection
interrupt and synchronous clock, and generating LIN-Break.
■ Extended Communication Control Register (ECCR)
Figure 12.3-7 Bit Configuration of Extended Communication Control Register (ECCR)
ECCR
R/W:
R:
W:
X:
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
LBR
W
MS
R/W
SCDE
R/W
SSM
R/W
BIE
R/W
RBI
R
TBI
R
000000XXB
Readable/Writable
Read only
Write only
Undefined
[bit7] Reserved: Reserved bit
Reserved bit. Be sure to write "0".
[bit6] LBR: LIN-Break set bit
LIN-Break setting
LBR
Write
0
No effect [Initial value]
1
LIN-Break generated
Read
Reading value is always "0".
When the operation mode is mode 0 or 3, if "1" is written to this bit, the length of LIN-Break specified by
the LBL1 and LBL0 of the ESCR is generated.
[bit5] MS: Master/slave mode select bit
MS
Master/slave function in mode 2
0
Master mode (serial clock generation) [Initial value]
1
Slave mode (external serial clock reception)
This bit sets UART in synchronous mode 2 as master or slave. When setting as master, UART generates
a synchronous clock. When setting as slave mode, it receives an external serial clock.
Note:
When setting as slave mode, set the clock source to 1 to 1 external clock input as the external clock.
(SCKE=0, EXT=1, OTO=1 in SMR)
388
CHAPTER 12 LIN-UART
[bit4] SCDE: Serial clock delay enable bit
SCDE
Serial clock delay enable in mode 2
0
Clock delay disabled [Initial value]
1
Clock delay enabled
When UART operates in mode 2 if this bit is set, the serial output clock delays one machine cycle.
[bit3] SSM: Start/stop bit mode enable
SSM
Start-stop synchronization in mode 2
0
Start/stop bit mode disabled in mode 2 [Initial value]
1
Start/stop bit mode enabled in mode 2
When UART operates in mode 2, this bit adds start bit and stop bit for synchronization. In other mode
(mode 0, 1, and 3), this bit is fixed to "0".
[bit2] BIE: Bus Idle Interrupt enable
BIE
Bus idle interrupt enable
0
Bus idle interrupt disable [Initial value]
1
Bus idle interrupt enable
When neither reception nor transmission is executed (RBI=1,TBI=1), this bit enables reception interrupt.
In mode 2, when SSM bit is "0", do not use this bit.
[bit1] RBI: Receive bus idle flag bit
RBI
Receive bus idle
0
Reception operation
1
During stop of reception
When there is no reception at the SIN pin, this bit is set to "1".
In mode 2, when SSM bit is "0", do not use this bit.
[bit0] TBI: Transmit bus idle flag bit
TBI
Transmit bus idle
0
Transmission Operation
1
During stop of transmission
When there is no transmission at the SOT pin, this bit is set to "1".
In mode 2, when SSM bit is "0", do not use this bit.
389
CHAPTER 12 LIN-UART
Note:
When the UART operation mode is set to mode 2, if the SSM bit is "0", do not use BIE, RBI, and TBI
bits.
390
CHAPTER 12 LIN-UART
12.3.7
Baud Rate/Reload Counter Register (BGR)
Baud rate/reload counter register (BGR) sets division ratio of serial clock. Correct value
of transmission reload counter is also read.
■ Baud Rate/Reload Counter Register (BGR)
Figure 12.3-8 Baud Rate/Reload Counter Register (BGR)
BGR1
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
-
B14
R/W
B13
R/W
B12
R/W
B11
R/W
B10
R/W
B09
R/W
B08
R/W
00000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
B07
R/W
B06
R/W
B05
R/W
B04
R/W
B03
R/W
B02
R/W
B01
R/W
B00
R/W
00000000B
BGR0
R/W: Readable/Writable
[bit15] Reserved: Reserved bit
Reserved bit. Read value is always "0".
[bit14 to bit8] BGR1: Baud rate generator register 1
BGR1
Baud rate generator register 1
Write
Write the bit14 to bit8 of reload value to counter
Read
Read the count bit14 to bit8
[bit7 to bit0] BGR0: Baud rate generator register 0
BGR0
Baud rate generator register 0
Write
Write bit7 to bit0 of reload value to counter
Read
Read count bit7 to bit0
■ Baud Rate/Reload Counter Register
Baud Rate/reload counter register (BGR) sets the division ratio of serial clock.
The register enables to read/write in byte access or halfword access.
391
CHAPTER 12 LIN-UART
12.4
UART Interrupt
UART has reception interrupt and transmission interrupt. Interrupt request is generated
in the following cases.
• Storing reception data to reception data register (RDR) or generating reception error
• Transmitting transmission data from transmission data register (TDR) to transmission
shift register
• LIN-Break detection
• Bus idle (without transmission/reception operation)
■ UART Interrupt
Table 12.4-1 shows interrupt control bits and interrupt causes.
Table 12.4-1 Interrupt Control Bit and Interrupt Causes of UART
Reception/
Interrupt
Flag
transmission/ request flag
register
ICU
bit
0
1
2
3
RDRF
SSR
❍
❍
❍
❍ written to RDR
ORE
SSR
❍
❍
❍
❍ Overrun error
FRE
SSR
❍
❍
▲
❍ Framing error
PE
SSR
❍
X
▲
X
LBD
ESCR
❍
X
X
❍ detected
TBI & RBI
ESCR
❍
❍
▲
❍
TDRE
SSR
❍
❍
❍
❍ register empty
ICP
ICS
❍
X
X
❍ LIN-Sync-Field
ICP
ICS
❍
X
X
❍ LIN-Sync-Field
Reception
Transmission
Operation mode
Interrupt cause
Interrupt
cause
enable bit
Receive data is
Receive data is
read
SSR: RIE
Parity error
LIN-Sync-Break
Bus idle
Transmission
1st falling edge of
How to clear the
interrupt request
"1" is written to
the receive error
clear bit
(SSR: CRE)
ESCR: LBIE
"1" is written to
ESCR: LBD
ECCR: BIE
Reception data/
transmission data
SSR: TIE
Write
transmission data
ICS: ICP
Disable ICP
temporary
ICS: ICP
Disable ICP
temporary
ICU
❍: Used
▲: Only available if ECCR/SSM=1
X: Undefined
392
5th falling edge of
CHAPTER 12 LIN-UART
■ Reception Interrupt
If one of the following is generated in reception mode, the flag bit corresponding to serial status register
(SSR) is set to "1".
• Completion of data reception: RDRF
Reception data is transmitted from serial input shift register to reception data register (RDR) and read is
enabled.
• Overrun error: ORE
RDRF=1 and RDR is not read from CPU.
• Framing error: FRE
When stop bit is received, "0" is received.
• Parity error: PE
Wrong parity bit is detected.
If the reception interrupt is enabled (RIE in SSR=1) and at least one of the above flags is set to "1", the
reception interrupt is generated.
When reception data register (RDR) is read, RDRF flag is cleared to "0" automatically. Only this method
clears RDRF flag.
When "1" is written to reception error flag clear bit (CRE) of serial control register (SCR), all error flags
are cleared to "0".
Note:
CRE bit is write only. When writing "1", "1" is retained for 1 machine cycle.
■ Transmission Interrupt
If transmission data is transferred from the transmission data register (TDR) to the transfer shift register
(occurs when the shift register is empty, and the transmission data exists), the transmission data register
empty flag bit (TDRE) of the serial status register (SSR) is set to "1". In this case, an interrupt request is
generated if the transmission interrupt enable (TIE) bit of the SSR was set before.
Note:
Initial value of TDRE is "1". Therefore, when TIE flag is set to "1", transmission interrupt is generated
immediately. TDRE flag is reset by writing to transmission data register (TDR) only.
■ LIN-Synch-Break Interrupt
LIN-Synch-Break interrupt functions if UART operates in mode 0 or 3 as LIN slave.
If the serial input bus goes "0" (dominant) for more than 11-bit time, LIN-Break detection flag bit (LBD) of
the extended status/control register (ESCR) is set to "1". In this case, the reception error flags are set to "1"
after 9-bit time. Therefore, be sure to set the RIE or RXE flag to 0 if only LIN-Sync-Break detection is
desired. Otherwise, the reception error interrupt is generated, and then wait LBD bit to 1 in the interrupt
processing routine. The interrupt and LBD flag are cleared if "1" is written to the LBD flag. Thus, CPU
detects LIN-Sync-Break surely for the procedure of adjustment for serial clock to the following LIN
master.
393
CHAPTER 12 LIN-UART
■ LIN-Synch-Field Edge Detection Interrupt
LIN-Synch-Field edge detection interrupt functions if UART operates in mode 0 or mode 3 as LIN slave.
The falling edge of the reception bus after LIN -Break detection is indicated by UART. The interrupt signal
connected to ICU is set to "1" simultaneously. This signal is reset at the fifth falling edge of LIN-SyncField. In both cases, if the detection of both edges and ICU interrupt are enabled, ICU generates an
interrupt. The difference between the counter values detected in ICU is 8 times of the serial clock. By using
this result, the baud rate for dedicated reload counter can be calculated. There is no need to restart the
reload counter because it is automatically reset if the falling edge of the start bit is detected.
■ Bus Idle Interrupt
When there is no reception operation on the SIN pin, the RBI flag bit of the ECCR is set to "1". Similarly,
when there is no transmission operation on the SOT pin, the TBI flag bit is set to "1". When the bus idle
enable bit (BIE) of the ECCR is set if both bus idle flags (TBI and RBI) are "1", the interrupt is occurred.
Note:
When the SOPE bit is "1" and "0" is written to the SIOP bit, the TBI flag becomes "0" even though
the bus operation is not performed. TBI bit and RBI bit cannot use when the SSM bit of the ECCR
register is "0" in synchronous mode 2.
Figure 12.4-1 shows generating of bus idle interrupt.
Figure 12.4-1 Generating of Bus Idle Interrupt
Transmission
data
Reception
data
TBI
RBI
Reception
IRQ
: Start bit
394
: Stop bit
: Data bit
CHAPTER 12 LIN-UART
12.4.1
Generation of Reception Interrupt and Flag Set Timing
This section explains reception interrupt factors, reception completion (RDRF bit of
SSR) and generation of reception error (PE, ORE and FRE bits of SSR).
■ Generation of Reception Interrupt and Flag Set Timing
If the reception interrupt enable flag bit (RIE) of the serial status register (SSR) is set to "1" when the data
reception is completed (RDRF=1), an interrupt is occurred. This interrupt is generated when the stop bit is
detected in mode 0 to mode 2 (when SSM is "1"), and 3, or when last data bit is read in mode 2 (when SSM
is "0").
Note:
If the reception error occurs, the content of the reception data register is invalid even in one of the
modes.
Figure 12.4-2 Reception Operation and Flag Set Timing
Receive data
(mode 0/3)
ST
D0
D1
D2
D5
D6
D7/
P
SP
ST
Receive data
(mode 1)
ST
D0
D1
D2
D6
D7
AD
SP
ST
D0
D1
D2
D4
D5
D6
D7
D0
Receive data
(mode 2)
PE*1, FRE
RDRF
ORE*2
(if RDRF= 1)
*1: The PE flag will always remain “0” in mode 1 or 3.
*2: ORE only occurs, if the reception data is read
by the CPU (RDRF = 1) and another frame is read.
ST: Start Bit
SP: Stop Bit
reception interrupt occurs
AD: Mode 1 (multi processor) address/data selection bit
Note:
Figure 12.4-2 does not show all possible reception options in mode o and 3. Here it is: "7p1" and
"8N1" (p="E"[even], or "0"[odd]).
395
CHAPTER 12 LIN-UART
Figure 12.4-3 ORE Setting Timing
Receive
data
RDRF
ORE
396
CHAPTER 12 LIN-UART
12.4.2
Transmission Interrupt Generation and Flag Timing
Transmission interrupt is generated when next transmission data is ready to be written
to the transmission data register (TDR).
■ Transmission Interrupt Generation and Flag Timing
Transmission interrupt is generated when the transmission data is ready to be written to the TDR register. If
the transmission interrupt enable bit (TIE) of the serial status register (SSR) is set to 1 and the transmission
interrupt is enabled, the transmission interrupt is generated when the TDR register is empty.
The transmission register empty flag bit (TDRE) of the SSR register indicates that the TDR is empty. The
TDRE bit is read only. The flag is cleared only by writing a data to the TDR register.
UART transmission operation and flag set timing is shown in Figure 12.4-4.
Figure 12.4-4 Transmission Operation and Flag Set Timing
transmission interrupt occurs
transmission interrupt occurs
Mode 0,1 or 3:
write to TDR
TDRE
serial output
P
P
ST D0 D1 D2 D3 D4 D5 D6 D7
SP ST D0 D1 D2 D3 D4 D5 D6 D7 SP
AD
AD
transmission interrupt occurs
transmission interrupt occurs
Mode 2 (SSM = 0):
write to TDR
TDRE
serial output
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4
ST: Start bit D0 ... D7: data bits
P: Parity
AD: Address/data selection bit (mode1)
SP: Stop bit
Note:
Figure 12.4-4 does not show all possible transmission options in mode 0.
Here is: "8p1"(p="E"[even] or "O"[odd]). In mode 3 and mode 2,when SSM bit is "0", the parity is not
provided.
397
CHAPTER 12 LIN-UART
■ Transmission Interrupt Request Generation Timing
When transmission interrupt is enabled (TIE bit of SSR is "1".) if TDRE flag becomes "1", transmission
interrupt request is generated.
Note:
The initial value of TDRE is "1". Therefore, when transmission interrupt is enabled (TIE=1),
transmission completion interrupt is set immediately. TDRE is read only. TDRE flag is cleared by
writing to transmission data register (TDR) only. Note the timing which enables transmission
interrupt.
398
CHAPTER 12 LIN-UART
12.5
UART Baud Rate
One of the following can be selected as UART serial clock:
• Dedicated baud rate generator (reload counter)
• External clock (clock input from SCK pin)
• Using the external clock for baud rate generator (reload counter)
■ UART Baud Rate Select
Figure 12.5-1 shows baud rate select circuit. The baud rate is selectable from three following description.
● Using of dedicated baud rate generator (reload counter)
UART has an independent reload counter each for transmission/reception serial clock. Baud rate is set by
15-bit reload value of baud rate generator register (BGR).
Reload counter is divided the machine clock by the setting value of baud rate generator register.
● Using an external clock (1 to 1 mode)
Clock input from UART clock input pin (SCK) is used as direct baud rate.
● Using the external clock for dedicated baud rate generator
External clock can be connected to reload counter in internal device. In this mode, external clock is used
instead of internal machine clock.
399
CHAPTER 12 LIN-UART
Figure 12.5-1 Baud Rate Select Circuit (Reload Counter)
REST
Start bit falling
edge detected
Reload Value: v
Rxc = 0?
set
Reception
15-bit Reload Counter Reload
Rxc = v/2?
0
FF
reset
1
EXT
Reload Value: v
Txc = 0?
CLK
SCK
(external
clock
input)
0
set
Transmission
15-bit Reload Counter Reload
1
Count Value: Txc
Txc = v/2?
0
FF
reset
400
OTO
1
Transmission
Clock
Internal data bus
EXT
REST
OTO
Reception
Clock
SMR
register
BGR14
BGR13
BGR12
BGR11
BGR10
BGR09
BGR08
BGR1
register
BGR07
BGR06
BGR05
BGR04
BGR03
BGR02
BGR01
BGR00
BGR0
register
CHAPTER 12 LIN-UART
12.5.1
Setting the Baud Rate
This section shows setting method of baud rate and calculating result of serial clock
frequency.
■ Baud Rate Calculation
15-bit reload counter is set by baud rate generator register (BGR).
The following formula is used for the calculation of baud rate.
v = [φ/b]-1,
In this case, "φ" and "b" shows machine clock frequency and baud rate respectively.
● Example of Calculation
When the machine clock is 16MHz and the desired baud rate is 19200bps, the reload value "v" can be
calculated as follows:
v = [16×106 / 19200]-1 = 832
The exact baud rate should be recalculated below:
bexact = φ / (v + 1) = 16×106 / 833 = 19207.6831 bps
Note:
Setting a reload value of "0" stops the reload counter. Therefore, a minimum dividing frequency ratio
is equal to 2 dividing frequency.
401
CHAPTER 12 LIN-UART
■ Baud Rate Setting Example of Each Machine Clock Frequency
Table 12.5-1 shows a setting example of the machine clock frequency and baud rate.
Table 12.5-1 Baud Rate Setting Example of Each Machine Clock Frequency
Baud
rate
8MHz
16MHz
20MHz
24MHz
32MHz
value
dev.
value
dev.
value
dev.
value
dev.
value
dev.
4M
-
-
-
-
4
0
5
0
7
0
2M
-
-
7
0
9
0
11
0
15
0
1M
7
0
15
0
19
0
23
0
31
0
500000
15
0
31
0
39
0
47
0
63
0
460800
-
-
-
-
-
-
51
-0.16
68
-0.64
250000
31
0
63
0
79
0
95
0
127
0
230400
-
-
-
-
-
-
103
-0.16
138
0.08
153600
51
-0.16
103
-0.16
129
-0.16
155
-0.16
207
-0.16
125000
63
0
127
0
159
0
191
0
255
0
115200
68
-0.64
138
0.08
173
0.22
207
-0.16
277
0.08
76800
103
-0.16
207
-0.16
259
-0.16
311
-0.16
416
0.08
57600
138
0.08
277
0.08
346
-0.06
416
0.08
555
0.08
38400
207
-0.16
416
0.08
520
0.03
624
0
832
-0.04
28800
277
0.08
554
-0.01
693
-0.06
832
-0.03
1110
-0.01
19200
416
0.08
832
-0.03
1041
0.03
1249
0
1666
0.02
10417
767
0
1535
0
1919
0
2303
0
3071
0
9600
832
-0.04
1666
0.02
2083
0.03
2499
0
3332
-0.01
7200
1110
-0.01
2221
-0.01
2777
0.01
3332
-0.01
4443
-0.01
4800
1666
0.02
3332
-0.01
4166
0.01
4999
0
6666
0
2400
3332
-0.01
6666
0
8332
0
9999
0
13332
0
1200
6666
0
13332
0
16666
0
19999
0
26666
0
600
13332
0
26666
0
-
-
-
-
-
-
300
26666
0
-
-
-
-
-
-
-
-
Note:
Deviations are given in %.
The maximum synchronous baud rate is 5-division of machine clock.
402
CHAPTER 12 LIN-UART
■ Using an External Clock
If the EXT bit of the SMR is set, the external pin SCK is selected as a clock. The external clock signal is
handled in the same way as internal MCU clock. e.g. crystal oscillator of 1.8432 MHz is connected to the
SCK pin, and the reload counter is used to select all the baud rate in PC-16550-UART.
If "1 to 1" external clock input mode (OTO bit of SMR) is selected, the SCK signal is directly connected to
the UART serial clock input. This is required to be operated as slave device in UART synchronous mode 2.
Note:
In either case, the clock signal is synchronized with MCU clock in UART. This means that indivisible
clock ratio will be unstable signal.
■ Counting Example
Figure 12.5-2 shows the operating example of transmission/reception reload counter. In this case, the reload
value is 832.
Figure 12.5-2 Counting Example of the Reload Counters
Transmission/
Reception Clock
Reload
Count
001
000
832
831
830
829
828
827
412
411
410
Reload Count value
Transmission/
Reception Clock
Reload
Count
417
416
415
414
413
Note
The falling edge of a serial clock signal is always after |(v + 1) / 2| .
403
CHAPTER 12 LIN-UART
12.5.2
Restart of the Reload Counter
Reload counter enables to restart by the following causes.
• Transmission/reception reload counter
• MCU reset
• UART software clear (UPCL bit of SMR)
• UART software restart (REST bit of SMR)
• Only reception reload counter
• Falling edge of start bit in asynchronous mode
■ Software Restart
When REST bit of a serial mode register (SMR) is set, the both of transmission and reception reload counters
is restarted in the next clock cycle. This function is for using the transmission reload counter as a timer.
Figure 12.5-3 shows the using of this function. In this case, the reload value is set to 100.
Figure 12.5-3 Example of Reload Counter Restart
MCU
Clock
Reload Counter
Clock Outputs
REST
Reload
Value
37
36 35 100 99
98
97
96
95
94
93
92
91
90
89 88
87
Read
BGR0/BGR1
Data
Bus
90
: don’t care
In this example, MCU clock cycle number (cyc) after REST becomes as following.
cyc = v – c + 1 = 100 – 90 + 1 = 11
In this case, "v" and "c" means the reload value and read counter value respectively.
Note:
If UART is reset by UPCL bit of SMR, reload counter is restarted.
404
CHAPTER 12 LIN-UART
■ Automatic Restart
When the falling edge of start bit is detected in asynchronous UART mode, reception reload counter is
restarted. This is for synchronization of serial input shift register and input serial data.
405
CHAPTER 12 LIN-UART
12.6
Operation of UART
UART operates as normal bidirectional serial communication in operation mode 0. In
mode 2 and 3, operate bidirectional communication as master or slave. In mode 1,
operate multiprocessor communication as master or slave.
■ Operation of UART
● Operating mode
UART has four operation modes of 0 to 3. Table 12.6-1 shows the operation mode which is selectable
depending on connection method in CPU and data transmission.
Table 12.6-1 UART Operation Mode
Data length
Operation mode
0
Normal mode
1
Multiprocessor mode
2
Normal mode
3
LIN mode
Parity
disabled
Parity
enabled
7 or 8
7 or 8 + 1 *2
8
8
-
synchronization
Length of stop
bit
Data
direction *1
Asynchronous
1 or 2
L/M
Asynchronous
1 or 2
L/M
Synchronous
0, 1 or 2
L/M
Asynchronous
1
L
*1: means the transfer data format (LSB first, MSB first)
*2: ”+1”means the indicator bit of the address/data section in the multiprocessor mode, instead of party bits.
Note:
Mode 1 operation is supported both for master or slave operation of UART in a master-slave
connection system. In Mode 3, the UART function is locked to 8NI-Format, LSB first.
If the mode is changed, UART cuts off all possible transmission or reception and starts next action.
406
CHAPTER 12 LIN-UART
■ Inter-CPU Connect
External clock "1 to 1" connection (normal mode) and master-slave connection (multiprocessor mode) can
be selected. For either connection method, the data length, whether to enable parity, and the
synchronization method must be common to all CPUs.
Select the operating mode as follows.
• In "1 to 1" connection method, two CPUs are set to operation mode 0 for asynchronous transfer mode or
to operation mode 2 for synchronous transfer mode. In synchronous mode 2, be sure to set CPU for the
master and the other for the slave.
• Select operation mode 1 for the master-slave connection method and use it either for the master or slave
system.
■ Synchronization Method
In asynchronous operation mode, UART reception clock is synchronized with falling edge of reception
start bit automatically.
In synchronous operation mode the synchronization is performed either by the clock signal of the master
device or by UART itself operation as master.
■ Signal Mode
UART handles the data as non-return to zero format.
■ Operation Enable Bit
UART uses transmission enable bit (TXE bit of SCR) and reception enable bit (RXE bit of SCR) to control
transmission and reception. When operation is disabled, they are each stopped as following.
• If reception operation is disabled during reception (data is inputted to the reception shift register), finish
frame reception and read the received data of the reception data register (RDR), and then stop the
reception operation.
• If the transmission operation is disabled during transmission (data is outputted from the transmission
shift register), wait until there is no data in the transmission data register (TDR) before stopping the
transmission operation.
407
CHAPTER 12 LIN-UART
12.6.1
Operation in the Asynchronous Mode
(Operation Mode 0 and Mode 1)
When UART is used in operating mode 0 (normal mode) or operating mode 1
(multiprocessor mode), asynchronous transfer mode is selected.
■ Transfer Data Format
The data transfer in the asynchronous operation mode begins with the start bit (low-level) and ends with the
stop bit (minimum one bit, high-level). The direction of the bit stream (LSB or MSB first) is set by the
BDS bit of the serial status register (SSR). The parity bit (if enabled) is always placed between the last data
bit and the stop bit.
In operation mode 0, the length of the data frame is 7 or 8 bits including the address/data delimiter bit
instead of parity bit. Stop bit is selectable from 1-bit or 2-bit.
The formula for bit length of transmission frame is as follows.
bit length = 1 + d + p + s
(d = Data bit [7 or 8], p = Parity [0 or 1], s = Stop bit [1 or 2])
Figure 12.6-1 Transfer Data Format (Operation Mmodes 0 and 1)
*1
Operation mode 0
ST
D0
D1
D2
D3
D4
D5
D6
D7/P
Operation mode 1
ST
D0
D1
D2
D3
D4
D5
D6
D7
*2
SP
AD
SP
SP
*1 : D7 (bit 7) if parity is not provided and data length is 8 bits
P (parity) if parity is provided and data length is 7 bits
*2 : only if SBL-Bit of SCR is set to "1"
ST: Start Bit
SP: Stop Bit
AD: Address/data selection bit in mode 1 (multiprocessor mode)
Note:
If BDS bit of the serial status register (SSR) is set to "1" (MSB first), the bit stream processes as: D7,
D6, ..., D1, D0, (P).
During reception both stop bits are detected, if 2 bits are selected. But the reception data full flag (RDRF)
will go "1" at the first stop bit. The bus idle flag (RBI bit of ECCR) goes "1" after the second stop bit if no
further start bit is detected (The second stop bit means "bus activity").
408
CHAPTER 12 LIN-UART
■ Transmission Operation
If the transmission data register empty flag (TDRE) of the serial status register (SSR) is set to "1", data is
enabled to write to the transmission data register (TDR). When data is written to TDR, TDRE flag becomes
"0". If the transmission operation is enabled by the TXE bit of serial control register (SCR), data is written
to transmission shift register and transmission is started from start bit in the next serial clock cycle.
Therefore, TDRE flag becomes "1" and can write the next data to TDR.
When transmission interrupt is enabled (TIE=1), interrupt is generated by TDRE flag. Initial value of
TDRE flag is "1" and when TIE bit is set to "1", interrupt is generated immediately.
When the bit length is set to 7 bits (CL=0), the unused bit of the TDR is always the MSB, independently
from the bit direction setting in the BDS bit (LSB or MSB first).
■ Reception Operation
When reception operation is enabled by RXE flag bit of SCR, reception operation is executed. If start bit is
detected, data frame is received depending on the format specified by SCR. When an error is generated, the
corresponding error flag (PE, ORE, FRE) is set. After reception of data frame, data is transmitted from
serial shift register to reception data register (RDR), reception data register full flag (RDRF) bit of SSR is
set. Be sure to read RDR from CPU to clear RDRF flag. When reception interrupt is enabled (RIE=1),
interrupt is generated by RDRF.
When the bit length is set to 7 bits (CL=0), the unused bit of the RDR is always the MSB, independently
from the bit direction setting in the BDS bit (LSB or MSB first).
Note:
Only when the RDRF flag is set and no errors have occurred the reception data register (RDR)
contains valid data.
Set the reception enable flag (RXE) to "1" while the reception bus level is "H".
■ Stop Bit
1 or 2 stop-bit can be selected at the transmission. When 2 bits are set at the reception, both 2 bits are
detected. This is because reception bus idle (RBI) flag is set appropriately after second stop bit.
■ Error Detection
In mode 0, parity, overrun, and framing errors can be detected.
In mode 1, overrun and framing errors are detected. In this mode, parity is not existed.
■ Parity
In mode 0 (and mode 2, when the SSM bit of the ECCR is set), the UART executes to calculate (at
transmission), detect, and check (at reception) the parity by the parity enable (PEN) bit of the serial control
register (SCR).
Odd parity or even parity is set by P bit of SCR.
409
CHAPTER 12 LIN-UART
12.6.2
Operation in the Synchronous Mode (Operation Mode 2)
In UART operating mode 2 (normal mode), clock synchronous transfer is used.
■ Transfer Data Format
In synchronous mode, 8-bit data is transferred without start/stop bit if the SSM bit of the extended
communication control register (ECCR) is "0". Data format of mode 2 depends on a clock signal.
Figure 12.6-2 shows the data format at transmission of synchronous operation mode.
Figure 12.6-2 Transfer Data Format (operation Mode 2)
Reception or transfer data
(ECCR:SSM=0, SCR:PEN=0)
D0
D1
D2
D3
D4
D5
D6
D7
Reception or transfer data
(ECCR:SSM=1, SCR:PEN=0)
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
SP *
Reception or transfer data
(ECCR:SSM=1, SCR:PEN=1)
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
SP *
* : only if SBL-Bit of SCR is set to "1"
ST: Start Bit
SP: Stop Bit
P: Parity Bit
■ Clock Inversion and Start/Stop Bit in Mode 2
When SCES bit of extended status/control register (ESCR) is set, serial clock is inverted. Therefore, data is
captured in falling edge of reception serial clock in slave mode. When SCES bit is set in master mode,
mark level of clock signal is "0". When SSM bit of extended communication control register (ECCR) is set,
start bit and stop bit are given in data format as asynchronous mode.
Figure 12.6-3 Transfer Data Format at Clock Inversion
mark level
reception or transmission clock
(SCES = 0, CCO = 0):
reception or transmission clock
(SCES = 1, CCO = 0):
data (SSM = 1)
(here: no parity, 1 stop bit)
mark level
ST
SP
data frame
410
CHAPTER 12 LIN-UART
■ Clock Supply
In clock synchronous mode (normal mode), the number of transmission bit and reception bit must be the
same as the clock cycle. When the start-stop synchronization communication is set, the number of the clock
cycles matches with that of adding start/stop bit. If the internal clock is selected (dedicated reload timer),
the data received in the clock synchronous is generated automatically when the data is transmitted.
If the external clock is selected, the data is stored in the transmission data register and the clock cycle per
bit to be transmitted is supplied from outside generated. When the SCES is "0", the mark level ("H") is
maintained period before transmission starts and after transmission completes.
The transmission clock signal is delayed 1 machine cycle by setting the SCDE bit of the ECCR so that the
transmission data is valid and stable at any falling edge of the clock. (it is required when the reception
device captures the data at the rising or falling edge of the clock.) This function stops when the CCO is set.
Figure 12.6-4 Delay Transmission Clock Signal (SCDE=1)
Transmission data
writing
Reception data sample edge (SCES = 0)
Mark level
Transmitting or
receiving clock
(normal)
Mark level
Transmitting clock
(SCDE = 1)
Mark level
Transmission and
reception data
0
1
1
0
LSB
1
0
0
1
MSB
Data
When serial clock edge select (SCES) bit of ESCR is set, UART clock is inverted and reception data is
captured in falling edge of clock. In this case, be sure to set as valid serial data at falling edge of clock.
In master mode, CCO bit of extended status/control register (ESCR) is set, and serial clock is sequentially
outputted from SCK pin. In this mode, the start bit and stop bit must be used to indicate the start and end of
the data frame in reception side. Figure 12.6-5 shows above descriptions.
Figure 12.6-5 Continuous Clock Output in Mode 2
reception or transmission clock
(SCES = 0, CCO = 1):
reception or transmission clock
(SCES = 0, CCO = 1):
data (SSM = 1)
(here: no parity, 1 stop bit)
ST
SP
data frame
■ Error Detection
When not using start/stop bit (SSM=0 of ECCR), only overrun error is detected.
411
CHAPTER 12 LIN-UART
■ Communication
For initialization of synchronous communication mode, set as follows.
• Baud rate/generator register (BGR)
Setting of reload value to dedicated baud rate/reload counter
• Serial mode register (SMR)
MD1, MD0: "10B" (mode 2)
SCKE:
"1" (using of dedicated baud rate reload counter)
"0" (external clock input)
• Serial control register (SCR)
RXE, TXE: Set the flag bit to "1".
SBL, AD:
No stop bit. No address/data delimiter. The value is invalid.
CL:
Fixed to 8-bit automatically. The value is invalid.
CRE:
"1" (Error flag is cleared to initialize and transmission/reception are stopped.)
SSM=0:
No parity. Setting value of PEN and P are invalid.
SSM=1:
Setting of PEN and P are valid.
• Serial status register (SSR)
BDS:
"0" (LSB first), "1" (MSB first)
RIE:
"1" (interrupt enabled), "0" (interrupt disabled)
TIE:
"1" (interrupt enabled), "0" (interrupt disabled)
• Extended communication control register (ECCR)
SSM:
"0" (without start/stop, normal)
"1" (with start/stop, special)
MS:
"0" (master mode, UART generates serial clock.)
"1" (slave mode, UART receives serial clock from external.)
Write the data to transmission data register (TDR) to start the communication. For reception only, stop
output in serial output enable (SOE) bit of SMR and then write the dummy data to TDR.
Note:
As with the asynchronous mode, continuous clock, start/stop bit, and bidirectional communication
can be used.
412
CHAPTER 12 LIN-UART
12.6.3
Operating in LIN Function (Operation Mode 3)
UART is usable as LIN master device or LIN slave device. LIN function is assigned
mode 3. When UART is set to mode 3, data format is 8N1 and LSB first.
■ UART as LIN Master
In LIN master mode, the master determines the baud rate of the whole bus, therefore slave devices are
synchronized to the master. Therefore, the specified baud rate is remained in master operation after
initialization.
Writing "1" into the LBR bit of the Extended Communication Control Register (ECCR) generates a 13 to
16 bit time "L" level on the SOT pin, which is LIN-Synch-Break and the start of a LIN message. Thereby
the TDRE flag of the Serial Status Register (SSR) goes "0" and is reset to "1" after the break, and generates
a transmission interrupt to the CPU (if TIE bit of SSR is "1").
The length of Synch-Break to be sent can be determined by the LBL1/LBL0 bits of the ESCR as follows:
Table 12.6-2 LIN-Break Length
LBL1
LBL0
Length of Break
0
0
13 Bit times
0
1
14 Bit times
1
0
15 Bit times
1
1
16 Bit times
The Synch-Field can be sent as byte data of 55H after the LIN-Break. To prevent a transmission interrupt,
the 55H can be written to the TDR just after writing the "1" to the LBR bit, although the TDRE flag is "0".
The transmission shift register waits until the LIN-Break has finished and shifts the TDR value out
afterwards. In this case, no interrupt is generated after the LIN-Break and before the start bit.
413
CHAPTER 12 LIN-UART
■ UART as LIN Slave
UART synchronizes with baud rate of master in LIN slave mode. When the reception is disabled (RXE=0)
and LIN-Break interrupt is enabled (LBIE=1), UART generates the reception interrupt if Synch-Break of
LIN master is detected and indicates it with the LBD flag of the ESCR. Writing "0" to this bit clears the
interrupt.
Next, the baud rate of LIN master is analyzed. The first falling edge of Synch-Field is detected in UART.
UART transmits to the input capture (ICU) via the internal signal, and a signal to ICU is reset at the fifth
falling edge. Therefore, it is necessary to set ICU as LIN input capture and to enable the interrupt of ICU.
The time that a signal to ICU is "1" is the correct baud rate of the LIN master divided by 8.
The value of baud rate setting is the following.
• Without timer overflow: BGR value = (b-a)/8
• With timer overflow : BGR value = (max + b – a) / 8
where max is the maximum value of timer.
where a is the value of ICU counter register after first interrupt
where b is the value of ICU counter register after second interrupt
414
CHAPTER 12 LIN-UART
■ Interrupt and Flag Upon Detection of LIN-Synch-Break
When LIN-Synch-Break is detected in slave mode, LIN-Break detection (LBD) flag of ESCR is set to "1".
If LIN-Break interrupt enable (LBIE) bit is set, this is an interrupt cause.
Figure 12.6-6 LIN-Synch-Break Detection and Flag Set Timing
Serial clock
cycle#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Serial
clock
Serial
input
(LIN bus)
FRE
(RXE=1)
LBD
(RXE=0)
Reception interrupt occurs, if RXE=1
Reception interrupt occurs, if RXE=0
Figure 12.6-6 shows LIN-Synch-Break detection and flag set timing.
If the reception interrupt is enabled (RIE=1) at the reception enable state (RXE=1), the reception data
framing error (FRE) flag bit of the SSR will cause a reception interrupt 2-bit time ("8N1") earlier than the
LIN-Break interrupt. So it is recommended to set RXE bit to "0" if LIN-Break is used.
LBD can be used in operating mode 0 and operating mode 3.
Figure 12.6-7 UART Operation in LIN Slave Mode
Serial
clock
Serial
Input
(LIN bus)
LBR cleared
by CPU
LBD
Internal
ICU
input
Synch break (e.g. 14 Tbit)
Synch field
415
CHAPTER 12 LIN-UART
■ LIN Bus Timing
Figure 12.6-8 LIN Bus Timing and UART Signal
old serial clock
no clock used
(calibration frame)
new (calibrated) serial clock
ICU count
LIN bus
(SIN)
RXE
LBD
(IRQ0)
LBIE
Internal
Signal to
ICU
IRQ from
ICU
RDRF
(IRQ0)
RIE
Read
RDR
by CPU
Reception Interrupt enable
LIN break begins
LIN break detected and Interrupt
IRQ cleared by CPU (LBD -> 0)
IRQ from ICU
IRQ cleared: Begin of Input Capture
IRQ from ICU
IRQ cleared: Calculate & set new baud rate
LBIE disable
Reception enable
Edge of Start bit of Identifier byte
Byte read in RDR
RDR read by CPU
416
CHAPTER 12 LIN-UART
12.6.4
Direct Access to Serial Pins
UART can access the value of transmission pin (SOT) and reception pin (SIN) directly.
■ UART Pin Direct Access
The UART provides the ability for the software to access directly to the value of serial input or output pin.
The software can always monitor the incoming serial data by reading the SIOP bit of the ESCR. If setting
the Serial Output Pin direct access Enable (SOPE) bit of the ESCR, the software can force the SOT pin to
output value. Note that this access is only possible, if the transmission shift is empty (i.e. no transmission
activity).
In LIN mode this function is used for reading back the own transmission data and is used for error handling
if something is physically wrong with the single-wire LIN-bus.
Note:
SIOP holds the last written value. Write the described value to the SIOP pin before enabling the
output pin access to prevent undesired edge output.
During a Read-Modify-Write access, the SIOP bit returns the value of SOT pin. In a normal read
instruction, the value of SIN pin is returned.
417
CHAPTER 12 LIN-UART
12.6.5
Bidirectional Communication Function (Normal Mode)
Normal serial bidirectional communication is enabled in operation mode 0 and mode 2.
Select operation mode 0 and mode 2 for asynchronous communication and
synchronous communication respectively.
■ Bidirectional Communication Function
Figure 12.6-9 shows the setting of UART in normal mode (operation mode 0 and 2).
Figure 12.6-9 Setting of UART in Operation Mode 0 and 2
bit15 bit14 bit13 bit12 bit11 bit10 bit9
SCR, SMR
PEN
P
SBL
CL
AD
bit8
bit7
bit6
Mode 0
0
0
0
Mode 2
0
1
0
SSR,
TDR/RDR
bit5
bit4
bit3
bit2
bit1
bit0
CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE
PEN ORE FRE TDRE RDRF TDRE RIE
TIE
0
0
0
0
0
0
1
Set transfer data (during writing)
Retain reception data (during reading)
Mode 0
Mode 2
ESCR, ECCR LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES
Mode 0
Mode 2
: Bit used
: Bit not used
1 : Set "1"
0 : Set "0"
: Bit used if SSM = 1 (Synchronous start-/stop-bit mode)
: Bit automatically set to correct value
418
LBR
MS SCDE SSM
BIE
RBI
TBI
CHAPTER 12 LIN-UART
■ Inter-CPU Connect
Figure 12.6-10 shows connection between 2 CPUs in UART mode 2.
Figure 12.6-10 Connection Example of UART Operation Mode 2 Bidirectional Communication
SOT
SOT
SIN
SIN
SCK
CPU-1 (Master)
Output
Input
SCK
CPU-2 (Slave)
419
CHAPTER 12 LIN-UART
12.6.6
Master-Slave Communication Function (Multiprocessor
Mode)
In master/slave mode, either system of master/slave enables UART communication with
plural CPUs.
■ Master-Slave Communication Function
Figure 12.6-11 shows the setting of UART in multiprocessor mode (operation mode 1).
Figure 12.6-11 Setting of UART in Operation Mode 1
bit15 bit14 bit13 bit12 bit11 bit10 bit9
SCR, SMR
PEN
P
SBL
CL
AD
Mode 1
SSR,
TDR/RDR
bit8
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE
0
PE
bit7
ORE FRE TDRE RDRF TDRE RIE
0
TIE
1
0
0
0
0
1
Set transfer data (during writing)
Retain reception data (during reading)
Mode 1
ESCR, ECCR LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES
Mode 1
: Bit used
: Bit not used
1 : Set "1"
0 : Set "0"
: Bit automatically set to correct value
420
LBR
MS SCDE SSM
BIE
RBI
TBI
CHAPTER 12 LIN-UART
■ Inter-CPU Connect
Figure 12.6-12 shows communication system which consists of the master CPU connected with two
communication lines and plural slave CPUs. UART can be used for the master or slave CPU.
Figure 12.6-12 Connection Example of UART Master-Slave Communication
SOT
SIN
Master CPU
SOT
SIN
SOT
Slave CPU #0
SIN
Slave CPU #1
■ Function
Please set the operating mode and the data transfer mode for the master-slave communication as shown in
Table 12.6-3.
Table 12.6-3 Setting of Master-Slave Communication
Operation Mode
Master
CPU
Address
transmission/
reception
Data
transmission/
reception
Mode 1
(AD bit
issue)
Slave
CPU
Mode 1
(AD bit
reception)
Data
Parity
Synchronization
method
Stop bit
Bit
direction
None
Asynchronous
1 bit or
2 bits
LSB or
MSB first
AD=1+
7-bit or
8-bit address
AD=0+
7- bit or
8-bit data
■ Communication Procedure
When master CPU transmits the address data, communication is started. AD bit of address data is set to
"1", and CPU for communication is selected. Each slave CPU confirms the address data. When address
data shows the address assigned in slave CPU, the slave CPU communicates with master CPU (normal
mode).
Figure 12.6-13 shows a flowchart of master-slave communication (multiprocessor mode).
421
CHAPTER 12 LIN-UART
Figure 12.6-13 Master-slave Communication Flowchart
(Master CPU)
(Slave CPU)
Start
Start
Set operation mode 1
Set operation mode 1
Set SIN pin as the
serial data input pin.
Set SOT pin as the
serial data output pin.
Set SIN pin as the
serial data input pin.
Set SOT pin as the
serial data output pin.
Set 7 or 8 data bits.
Set 1 or 2 stop bits.
Set 7 or 8 data bits.
Set 1 or 2 stop bits.
Set “1” in AD bit
Set TXE = RXE = 1.
Set TXE = RXE = 1.
Receive Byte
Send Slave Address
Is
AD bit = 1 ?
waiting
NO
YES
Bus-idle
Interrupt
Does
Slave Address
match ?
Set “0” in AD bit
NO
YES
Communication with
slave CPU
Is
communication
complete?
Communication with
master CPU
NO
YES
Communicate
with another
slave CPU?
YES
NO
YES
Set TXE = RXE = 0
End
422
Is
communication
complete?
NO
CHAPTER 12 LIN-UART
12.6.7
LIN Communication Function
In either system of LIN master or LIN slave, the UART communication with LIN device is
enabled.
■ LIN-Master-Slave Communication Function
Figure 12.6-14 shows the setting of UART in LIN communication mode (operating mode 3).
Figure 12.6-14 Setting of UART in Operation Mode 3 (LIN)
bit15 bit14 bit13 bit12 bit11 bit10 bit9
SCR, SMR
PEN
P
SBL
CL
AD
Mode 3
SSR,
TDR/RDR
bit8
0
PE
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE
ORE FRE TDRE RDRF TDRE RIE
1
TIE
1
0
0
0
0
1
Set transfer data (during writing)
Retain reception data (during reading)
Mode 3
ESCR, ECCR LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES
Mode 3
LBR
MS SCDE SSM
BIE
RBI
TBI
0
: Bit used
: Bit not used
1 : Set "1"
0 : Set "0"
: Bit automatically set to correct value
423
CHAPTER 12 LIN-UART
■ Connection of LIN Device
Figure 12.6-15shows connecting of LIN master device and LIN slave device.
UART is settable as LIN master or LIN slave.
Figure 12.6-15 Connecting Example of LIN Bus System
SOT
SOT
LIN bus
SIN
LIN-Master
424
SIN
Single-WireTransceiver
Single-WireTransceiver
LIN-Slave
CHAPTER 12 LIN-UART
12.6.8
LIN Communication Mode (Operation Mode 3)
UART Sample Flowchart
This section shows an example of UART flowchart in LIN communication mode.
■ UART as Master Device
Figure 12.6-16 UART Flowchart in LIN Master Mode
START
Initialization:
Set Operation mode 3
(8N1 data format)
TIE = 0, RIE = 0
Send
Message?
NO
YES
Send Synch Break:
write “1” to ECCR:
LBR, TIE = 1;
Send Sleep Mode
TDR = 80H
TIE = 0
Send Synch Field:
TDR = 55H
Wake up
from CPU?
YES
NO
Send Sleep
Mode?
Send Wake up signal
RIE = 0
TIE = 1
TDR = 80H
RIE = 1
YES
NO
Send Identify Field:
TDR = Id
Write to
slave?
NO
TIE = 0
RIE = 1
Read data from slave
RIE = 0
NO
YES
00H, 80H or C0H
received?
TIE = 1
Write data to slave
TIE = 0
YES
RIE = 0
Errors
occurred?
NO
YES
Error Handler
425
CHAPTER 12 LIN-UART
■ UART as Slave Device
Figure 12.6-17 UART Flowchart in LIN Slave Mode
START
A
B
Initialization:
Set Operation mode 3
(8N1 data format)
C
Error
occurred?
Slave
address
matched?
E
C
RIE = 0; LBIE = 1;
RXE = 0
Wait for
slave
operation
Transmission
request from
master?
LBD = 1
LIN break interrupt
Wait for message from
LIN master
Write "0" to ESCR.LBD
Disable interrupt
Enable ICU interrupt
Wait for
slave
operation
ICUInterrupt
Receive data
+ check sum
80H
received?
(sleep
mode)
S
(To the next page)
TIE = 0
B
Read ICU data
Clear ICU interrupt flag
RIE = 0
TIE = 1
Calculate
checksum
Transmit data
C
Transmission
request from
master?
Wait for
slave
operation
C
ICUInterrupt
Read ICU data
Calculate new baud rate
Clear ICU interrupt flag
Clear interrupt
Wait for
slave
operation
Bus-idle
Interrupt
E
Error handler
C
Receive ID
RIE = 1; RXE = 1
A
(Continued)
426
CHAPTER 12 LIN-UART
(Continued)
S
Wake up
from CPU?
NO
Transmit wakeup code
RIE = 0
TIE = 1
TDR = 80H
YES
RIE = 1
NO
Receive
00H, 80H or
C0H?
TIE = 0
YES
RIE = 0
C
427
CHAPTER 12 LIN-UART
12.7
Precautions when Using UART
This section shows the precautions when using UART.
■ Operation Setting
UART serial control register (SCR) has TXE (transmission) and RXE (reception) operating enable bits.
Because the initial value of these bits is in the state of stop, set before transmission start in transmission/
reception operation. To disable setting bits can stop transmission.
The single bus system as ISO9141 (LIN bus system) is single direction communication, so do not set these
two bits simultaneously. The data transmitted by UART also receives UART itself because the reception is
executed automatically.
■ Communication Mode Setting
Set the communication mode while the system is not operating. When the operation mode is changed
during transmission/reception, transmission/reception is stopped and the data is lost.
■ Transmission Interrupt Enabling Timing
Initial value of transmission data empty flag bit (TDRE bit of SSR) is "1" (in the state of transmission data
writing enable without transmission data). When transmission interrupt request is enabled (TIE bit of SSR
is "1"), it is generated immediately. Set TIE flag to "1" after writing of transmission data to TDR register
not to generate this interrupt.
■ Using LIN in Operation Mode 3
LIN function is enabled to use in mode 0 (transmission and reception break), but when operation mode is
set in mode 3, data format of UART is set to LIN format (8N1 and LSB first) automatically. For applying
to LIN bus protocol of UART, set the operating mode to mode 3. Break transmission time is changeable,
but 11 serial bit times are required at least.
■ Changing Operation Setting
When changing the operation setting of UART, be sure to reset UART. Special care has to be taken
whether the start/stop bit is enabled in synchronous mode 2.
When setting the serial mode register (SMR), resetting of UART and the UPCL bit cannot be performed
simultaneously. In this case, UART may not operate correctly. Set UPCL bit after setting SMR bit.
■ Setting of LIN Slave
When UART is initialized as LIN slave, be sure to set baud rate before receiving the first LIN synchronous
break. This is because the LIN synchronous break of minimum 13-bit time is detected correctly.
428
CHAPTER 12 LIN-UART
■ Software Compatible
Although this UART is similar to other UART in other microcontrollers it is not software compatible to
them. The programming models may be the same, but the structure of the registers differ. Furthermore, the
setting of the baud rate is now determined by a reload value instead of selecting a predefined value.
■ Bus Idle Function
The Bus Idle Function cannot be used in synchronous mode 2.
■ AD Bit of Serial Control Register (SCR)
When using AD bit (address/data bit in multiprocessor mode) of serial control register (SCR), note the
following.
This bit is both a control bit and a flag bit, because writing to it sets the AD bit for transmission, whereas
reading from it returns the last received AD bit. Internally, the received and the transmitted data are stored
in different registers, but in Read-Modify-Write instruction, the received data is read, modified and then
written back for transmission. This can lead to a wrong value in the AD bit, when one of the other bits in
the same register is accessed by an instruction of this kind.
Therefore, this bit should be written by the last register access before transmission. Alternatively using byte
access and writing the correct values for all bits at once avoids this problem.
Furthermore, the AD bit is not buffered like the transmission data register.
Update of the bit during transmission will change the AD bit of the currently transmitted data.
429
CHAPTER 12 LIN-UART
430
CHAPTER 13
I2C INTERFACE
This chapter describes the outline of the I2C interface,
the configuration and functions of registers, and I2C
interface operation.
13.1 Outline of I2C Interface
13.2 I2C Interface Register
13.3 Operation Explanation of I2C Interface
13.4 Operation Flowcharts
431
CHAPTER 13 I2C INTERFACE
13.1
Outline of I2C Interface
The I2C interface is a serial I/O port that supports internal IC BUS and operates as the
master/slave devices on I2C bus.
■ Features
The I2C interface has the following features:
• Master or slave sending and receiving
• Arbitration function
• Clock synchronization function
• Slave address/general call address detection function
• Transfer direction detection function
• Function that generates and detects a repeated START condition
• Bus error detection function
• 10-bit and 7-bit slave addresses
• Slave address reception acknowledge control in master mode
• Composite slave addresses supported
• Interrupt enabled for a transmission or bus error
• Standard mode (maximum of 100 kbps) and high-speed mode (maximum of 400 kbps) available
432
CHAPTER 13 I2C INTERFACE
■ I2C Interface Registers
The following describes the configuration and functions of registers used by the I2C interface.
• Bus control register (IBCR)
IBCR0 to IBCR2
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
BER
R/W
BEIE
R/W
SCC
R/W
MSS
R/W
ACK
R/W
GCAA
R/W
INTE
R/W
INT
R/W
00000000B
R/W: Readable/Writable
• Bus status register (IBSR)
IBSR0 to IBSR2
R:
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
BB
R
RSC
R
AL
R
LRB
R
TRX
R
AAS
R
GCA
R
ADT
R
00000000B
Read only
• 10-bit slave address register (ITBA)
ITBAH0 to ITBAH2
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
-
-
-
-
-
-
TA9
R/W
TA8
R/W
------00B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
TA7
R/W
TA6
R/W
TA5
R/W
TA4
R/W
TA3
R/W
TA2
R/W
TA1
R/W
TA0
R/W
00000000B
ITBAL0 to ITBAL2
R/W: Readable/Writable
• 10-bit slave address mask register (ITMK)
ITMKH0 to ITMKH2
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
ENTB
R/W
RAL
R
-
-
-
-
TM9
R/W
TM8
R/W
00----11B
ITMKL0 to ITMKL2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
TM7
R/W
TM6
R/W
TM5
R/W
TM4
R/W
TM3
R/W
TM2
R/W
TM1
R/W
TM0
R/W
11111111B
R/W: Readable/Writable
R:
Read only
433
CHAPTER 13 I2C INTERFACE
• 7-bit slave address register (ISBA)
ISBA0 to ISBA2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
SA6
R/W
SA5
R/W
SA4
R/W
SA3
R/W
SA2
R/W
SA1
R/W
SA0
R/W
-0000000B
R/W: Readable/Writable
• 7-bit slave address mask register (ISMK)
ISMK0 to ISMK2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ENSB
R/W
SM6
R/W
SM5
R/W
SM4
R/W
SM3
R/W
SM2
R/W
SM1
R/W
SM0
R/W
01111111B
R/W: Readable/Writable
• Data register (IDAR)
IDAR0 to IDAR2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D7
R/W
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
R/W
00000000B
R/W: Readable/Writable
• Clock control register (ICCR)
ICCR0 to ICCR2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
NSF
R/W
EN
R/W
CS4
R/W
CS3
R/W
CS2
R/W
CS1
R/W
CS0
R/W
-0011111B
R/W: Readable/Writable
434
CHAPTER 13 I2C INTERFACE
■ Block Diagram of I2C Interface
Figure 13.1-1 is a block diagram of the I2C interface.
Figure 13.1-1 Block Diagram of I2C Interface
ICCR
EN
2
I C operation enable
CLKP
Clock enable
ICCR
CS4
CS3
CS2
CS1
CS0
IBSR
BB
RSC
Clock division 2
2345
32
Shift clock
generation
Clock selection 2 (1/12)
Shift clock edge change
timing
Bus busy
Repeat start
Last Bit
LRB
TRX
Send/
receive
Start/Stop condition
detection
Error
First byte
ADT
AL
R-bus
Sync
Arbitration lost detection
IBCR
SCL
BER
BEIE
IBCR
SCC
MSS
ACK
GCAA
IRQ
Interrupt request
INTE
INT
SDA
End
Start
Master
ACK
permission
GC-ACK
permission
Start/Stop condition
generation
IDAR
IBSR
AAS
Slave
Global call
GCA
Slave Address
Compare
ISML
FNSB
ITMK
ENTB RAL
ITBA
ITMK
ISBA
ISMK
435
CHAPTER 13 I2C INTERFACE
13.2
I2C Interface Register
The structure and functions of registers used in the I2C interface are described.
■ I2C Interface Registers
The I2C interface has the following 8 registers:
• Bus status register (IBSR0 to IBSR2)
• Bus control register (IBCR0 to IBCR2)
• Clock control register (ICCR0 to ICCR2)
• 10-bit slave address register (ITBAH0 to ITBAH2, ITBAL0 to ITBAL2)
• 10-bit slave address mask register (ITMKH0 to ITMKH2, ITMKL0 to ITMKL2)
• 7-bit slave address register (ISBA0 to ISBA2)
• 7-bit slave address mask register (ISMK0 to ISMK2)
• Data register (IDAR0 to IDAR2)
436
CHAPTER 13 I2C INTERFACE
13.2.1
Bus Status Register (IBSR0 to IBSR2)
The bus status register (IBSR0 to IBSR2) has the following functions.
• Bus busy detected
• Repeated start condition detected
• Arbitration lost detected
• Acknowledge detected
• Data transfer direction indicated
• Slave addressing detected
• General call address detected
• Address data transfer detected
■ Bus Status Register (IBSR0 to IBSR2)
The following shows the register configuration of the bus status register (IBSR).
IBSR0 to IBSR2
R:
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
BB
R
RSC
R
AL
R
LRB
R
TRX
R
AAS
R
GCA
R
ADT
R
00000000B
Read only
This register is read-only for all bits. All bits of this register is controlled by hardware automatically. All
bits are cleared when I2C interface operation is stopped (ICCR EN = 0).
[bit7] BB: Bus busy bit
It is a bit which the state of the I2C bus is shown.
Value
Description
0
STOP condition detected [Initial value]
1
START condition detected (bus used)
[bit6] RSC: Repeated start condition bit
This bit is the repeated START condition detection bit.
Value
Description
0
Repeated START condition not detected [Initial value]
1
Repeated START condition detected
This bit is cleared when the slave address transfer ends (ADT=0) or when the STOP condition is
detected.
437
CHAPTER 13 I2C INTERFACE
[bit5] AL: Arbitration lost detection bit
It is an arbitration lost detection bit.
Value
Description
0
Arbitration lost not detected [Initial value]
1
Arbitration lost detected during master transmission
Write "0" to the INT bit or "1" to the MSS bit of the IBCR register to clear this bit.
Arbitration lost is detected if:
• The data transmission does not match the data on the SDA line at the rising edge of SCL.
• A repeated START condition is generated in the first bit of the data by another master.
• The I2C interface cannot generate a START or STOP condition because the SCL line is driven to "L"
by another slave device.
[bit4] LRB: Acknowledge storing bit
This bit is an acknowledge storage bit that stores an acknowledge from the receiving device.
Value
Description
0
Slave acknowledge detected [Initial value]
1
Slave acknowledge not detected
This bit is rewritten if an acknowledge is detected (reception 9 bits).
This bit is cleared if a START or STOP condition is detected.
[bit3] TRX: Transferring data bit
This bit indicates the transmission status during a data transfer.
Value
Description
0
Data transmission stopped [Initial value]
1
Data transmission in progress
This bit is set to "1" if: A START condition occurs in master mode.
- Transfer of the first byte ends during read access (transmission) in slave mode.
- Data is being sent in master mode.
This bit is set to "0" if: The bus is idle (IBCR BB=0).
- An arbitration loss occurs.
- "1" is written to the SCC bit in the master interrupt status (MSS=1, INT=1).
- The MSS bit is cleared in the master interrupt status (MSS=1, INT=1).
- No acknowledge occurred for the last transfer in slave.
- Data is received in slave mode.
- Data is received from a slave in master mode.
438
CHAPTER 13 I2C INTERFACE
[bit2] AAS: Slave addressing detection bit
This bit is the slave addressing detection bit.
Value
Description
0
The interface is not specified as a slave. [Initial value]
1
The interface is specified as a slave.
This bit is cleared when a (repeated) START or STOP condition is detected.
This bit is set when a 7-bit or 10-bit slave address is detected.
[bit1] GCA: General call address detection bit
This bit is the general call address (00H) detection bit.
Value
Description
0
General call address is not detected. [Initial value]
1
General call address is detected.
This bit is cleared when a (repeated) START or STOP condition is detected.
[bit0] ADT: Address data transfer bit
This bit is the slave address reception detection bit.
Value
Description
0
Received data is not a slave address (or the bus is idle). [Initial value]
1
Received data is a slave address.
This bit is set to "1" if a START condition is detected. It is cleared after the second byte if the header
section of a slave address is detected during 10-bit write access. Otherwise, it is cleared after the first
byte.
"After the first or second byte" means the following:
• Writing "0" to the MSS bit during master interrupt (MSS=1, INT=1: IBCR)
• Writing "1" to the SCC bit during master interrupt (MSS=1, INT=1: IBCR)
• Clearing the INT bit
• Beginning of all transfer bytes master or slave that is not used for the transfer destination.
439
CHAPTER 13 I2C INTERFACE
13.2.2
Bus Control Register (IBCR0 to IBCR2)
The bus control register (IBCR0 to IBCR2) has the following functions.
• Interrupt enable flag
• Interrupt generation flag
• Bus error detection flag
• Repeated start condition generation
• Master/slave mode selection
• General call acknowledge generation enable
• Data byte acknowledge generation enable
■ Bus Control Register (IBCR0 to IBCR2)
The following shows the register configuration of the bus control register (IBCR).
IBCR0 to IBCR2
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
BER
R/W
BEIE
R/W
SCC
R/W
MSS
R/W
ACK
R/W
GCAA
R/W
INTE
R/W
INT
R/W
00000000B
R/W: Readable/Writable
Perform write access to the bus control register (IBCR) when the INT bit is "1" or when the transfer is
started. When the ACK bit or GCAA bit is changed, the bus error is detected. Therefore, do not perform
write access to the register during transfer operation. Bits other than BER and BEIE are cleared if the I2C
interface is stopped (ICCR EN=0).
[bit15] BER: Bus error flag
This bit is the bus error interrupt request flag bit. For a read by a read modify instruction, "1" is always
read.
During writing
Value
Description
0
Clears the bus error interrupt request flag.
1
Has no meaning.
During reading
Value
Description
0
Bus error not detected [Initial value]
1
Error condition detected
If this bit is set, the EN bit of the ICCR register is cleared, the I2C interface is stopped, and data transfer
is halted. All bits of the IBSR and IBCR registers except BER and BEIE are cleared. Clear this bit before
the I2C interface is enabled (EN = 1) again.
440
CHAPTER 13 I2C INTERFACE
This bit is set to "1" if:
1. An illegal START or STOP condition at a specific location is detected (while a slave address or data is
being transferred). *
2. The header section of a slave address is received during a 10-bit read access before 10-bit write access
with the first byte is performed. *
3. A START condition is detected during transfer in master mode.
*: When the I2C interface is enabled during transfer, this detection flag is set after the first STOP condition
is received to prevent an incorrect bus error report from being issued.
[bit14] BEIE: Bus error interrupt enable bit
This bit is the bus error interrupt enable bit.
Value
Description
0
Bus error interrupt disabled [Initial value]
1
Bus error interrupt enabled
An interrupt occurs if this bit is set to "1" and the BER bit is set to "1".
[bit13] SCC: Start condition continue bit
This bit is the repeated START condition generation bit.
At write
Value
Description
0
Has no meaning.
1
Generates a repeated START condition in master transfer.
The read value of this bit is always "0".
If "1" is written to this bit in master mode (MSS = 1, INT = 1), a repeated START condition is generated
and the INT bit is automatically cleared.
[bit12] MSS: Master/slave selection bit
This bit is the master or slave selection bit.
Value
Description
0
Selects slave mode. [Initial value]
1
Selects master mode. Generates a START condition to enable the value of the IDAR
register to be sent as a slave address.
• This bit is cleared when arbitration lost occurs during master transmission, causing slave mode to
start.
• Write "0" to this bit during setting a master interrupt flag (MSS=1, INT=1) to automatically clear the
INT bit. Then, generate a STOP condition to end the transfer.
Note: The MSS bit functions as a direct reset. To detect a STOP condition, check the BB bit of the
IBSR register.
441
CHAPTER 13 I2C INTERFACE
• If "1" is written to this bit while the bus is idle (MSS = 0, BB = 0), a START condition is generated
and the value of IDAR is sent.
• If "1" is written to this bit while the bus is busy (BB = 1, TRX = 0, MSS = 0), the I2C interface starts
transmission when the bus becomes idle. If the I2C interface is specified as the address for a slave that
is accompanied by a write access during this time, the bus becomes idle after the transfer ends. If the
interface is transmitting as a slave (IBCR AAS = 1, TRX = 1) during this time, no data is sent even if
the bus has become idle. It is important to check whether the I2C interface is specified as a slave
(IBSR AAS = 1), and whether data transmission has ended normally (IBCR MSS = 1) at the next
interrupt or otherwise data transmission has failed with an error (IBSR AL = 1).
[bit11] ACK: Acknowledge bit
This bit generates an acknowledge according to the setting of the data receive enable bit.
Value
Description
0
Acknowledge not generated when data is received [Initial value]
1
Acknowledge generated when data is received
• This bit is disabled when a slave address is received in slave mode. When the I2C interface detects a
7-bit or 10-bit slave address specification, an acknowledge is returned if the corresponding enable bits
(ENTB ITMK, ENSB ISMK) are set.
• Write to this bit while an interrupt flag is set (INT = 1), the bus is idle (IBSR BB = 0), or the I2C
interface is stopped (ICCR EN = 0).
[bit10] GCAA: General call address acknowledge bit
This bit is an acknowledge enable bit used when a general call address is received.
Value
Description
0
Acknowledge not generated when general call address is detected [Initial value]
1
Acknowledge generated when general call address is detected
Write to this bit while an interrupt flag is set (INT = 1), the bus is idle (IBSR BB = 0), or the I2C
interface is stopped (ICCR EN = 0).
• At reception of the general call address, when both this bit and ACK bit are set to "1", acknowledge
response is enabled.
• At transmission of the general call address, when this bit is set to "1", acknowledge response is
enabled.
• The output of the acknowledge bit is allowed at the data reception in the slave reception (including the
arbitration lost occurs after the general call address is transmitted in the master) when both the ACK
bit and this bit are "1".
• Do not change the set value of this bit when the GCA bit of the bus status register (IBSR) is "1".
442
CHAPTER 13 I2C INTERFACE
[bit9] INTE: Interruption enable bit
This bit is the interrupt enable bit.
Value
Description
0
Interrupt disabled [Initial value]
1
Interruption enabled
When this bit is "1" and the INT bit is "1", the interrupt is generated.
[bit8] INT: Interrupt request flag
This bit is the transfer end interrupt request flag bit. For a read by a read modify instruction, "1" is read.
At write
Value
Description
0
Clears the transfer end interrupt request flag.[Initial value]
1
Has no meaning.
During reading
Value
Description
0
Transfer not ended, not the transfer target, or bus is idle. [Initial value]
1
This is set when 1 byte of data including the ACK bit has already been transferred and if
the following condition is applied.
• It is a bus master.
• The interface was specified as a slave address.
• The general call address was received.
• The arbitration lost happened.
If the interface is specified as a slave address, this bit is set at the end of slave address
reception that includes an acknowledge.
If this bit is set to "1", the SCL line is maintained at the "L" level. Write "0" to this bit to clear it, release
the SCL line, and transfer the next byte. A repeated START or STOP condition is generated.
This bit is cleared when the SCC bit or the MSS bit is set to "1".
443
CHAPTER 13 I2C INTERFACE
Notes:
Contention of SCC, MSS, and INT bits
If data is simultaneously written to the SCC, MSS, and INT bits, contention occurs between the nextbyte transfer, repeated START condition generation, and STOP condition generation. If this situation
occurs, the priorities are as follows:
• Next-byte transfer and STOP condition generation
When the INT bit is set to "0" and the MSS bit is set to "0", writing of the MSS bit has precedence
and a STOP condition is generated.
• Next-byte transfer and repeated START condition generation
When the INT bit is set to "0" and the SCC bit is set to "1", writing of the SCC bit has precedence,
repeated START condition is generated, and the value of IDAR is transmitted.
• Repeated START condition generation and STOP condition generation
When the SCC bit is set to "1" and the MSS bit is set to "0" at the same time, clearing of the MSS
bit has precedence. A STOP condition is generated and the I2C interface enters slave mode.
When an instruction which generates a START condition is executed (set "1" to MSS bit in IBCR) at
timing shown in Figure 13.2-1 and Figure 13.2-2, arbitration lost detection (AL bit in IBCR=1)
prevents an interrupt (INT bit in IBCR=1) from being generated.
● Condition 1 in which an interrupt upon detection of "arbitration lost" does not occur
When an instruction which generates a START condition is executed (set "1" to MSS bit in IBCR
register) with no START condition detected (BB bit in IBSR=0) and with the SDA or SCL pin at the
"L" level.
Figure 13.2-1 Diagram of Timing at which an Interrupt Upon Detection of "Arbitration Lost" does not Occur
SCL pin or SDA pin is at Low level
SC pin
"L"
SDA pin
"L"
1
2
I C operation enable state (ENbit=1)
Master mode setting (MSSbit=1)
Arbitration lost detection (AL bit=1)
444
Bus busy (BB bit)
0
Interrupt (INT bit)
0
CHAPTER 13 I2C INTERFACE
● Condition 2 in which an interrupt upon detection of "arbitration lost" does not occur
When an instruction which generates a START condition by enabling I2C operation (EN bit in
ICCR=1) is executed (set "1" to MSS bit in IBCR register) with the I2C bus occupied by another
master.
This is because, as shown in Figure 13.2-2, when the other master on the I2C bus starts
communication with I2C disabled (EN bit in ICCR=0), the I2C bus enters the occupied state with no
START condition detected (BB bit in IBSR=0).
Figure 13.2-2 Diagram of Timing at which an Interrupt Upon Detection of "Arbitration Lost"
does not Occur
The INT bit interrupt does not
occur in the ninth clock cycle.
Start Condition
Stop Condition
SCL pin
SDA pin
SLAVE
ADDRESS
ACK
DAT
ACK
ENbit
MSSbit
ALbit
BBbit
INTbit
0
0
If a symptom as described above can occur, follow the procedure below for software processing.
1. Execute the instruction that generates a START condition (set the MSS bit in IBCR register to "1")
2. Use, for example, the timer function to wait for the time for three-bit data transmission at the I2C
transfer frequency set in the ICCR register.*
Example:
Time for three-bit data transmission at an I2C transfer frequency of 100 kHz = {1/(100 × 103)} ×
30=30µs
*: When the arbitration lost is detected, the MSS bit is set and then the AL bit is set to "1" without
fail after the time for three-bit data transmission at the I2C transfer frequency.
3. Check the AL and BB bits in the IBSR register and, if the AL and BB bits are "1" and "0",
respectively, set the EN bit in the ICCR register to "0" to initialize I2C.
When the AL and BB bits are not so, perform normal processing.
445
CHAPTER 13 I2C INTERFACE
A sample flow is given below.
Master mode setting
Set the MSS bit in the bus control register (IBCR) to "1".
Wait for the time for three - bit data transmission at the I2C
transfer frequency set in the clock control register (ICCR).
NO
BB bit = 0 and AL bit = 1?
YES
Set the EN bit to initialize I2C
to normal process
● Example of occurrence for an interrupt upon detection of "arbitration lost"
When an instruction which generates a START condition is executed (setting the MSS bit in IBCR
register to "1") with "bus busy" detected (BB bit=1 in IBSR) and arbitration is lost, the INT bit is set to
"1" and interrupt occurs upon detection of "AL bit=1".
Figure 13.2-3 Diagram of Timing at which an Interrupt Upon Detection of "Arbitration Lost" Occurs
Interrupt at 9th clock
Start Condition
SCL pin
SDA pin
SLAVE
ADDRESS
ACK
DAT
EN bit
MSS bit
Clear AL bit by software
AL bit
BB bit
Open SCL by clearing INT bit by software
INT bit
446
CHAPTER 13 I2C INTERFACE
13.2.3
Clock Control Register (ICCR0 to ICCR2)
The clock control register (ICCR0 to ICCR2) supports the following functions.
• Noise filter enable
• I2C interface operation enable
• Serial clock frequency setting
■ Clock Control Register (ICCR0 to ICCR2)
The following shows the register configuration of the clock control register (ICCR).
ICCR0 to ICCR2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
NSF
R/W
EN
R/W
CS4
R/W
CS3
R/W
CS2
R/W
CS1
R/W
CS0
R/W
-0011111B
R/W: Readable/Writable
[bit15] Reserved: Reserved bit
The read value is always 0.
[bit14] NSF: Noise filter enable bit
This bit enables the noise filter located in SDA and SCL pins. This noise filter can control spike that
generates to this input (CLKP1 to 1.5 cycles). Set this bit to "1" when the transmission/reception is used
at speed of 100Kbps or more.
[bit13] EN: Operation enable bit
It is the I2C interface operation permission bit.
Value
Description
0
Disabled operations [Initial value]
1
Enable operations
[bit12 to bit8] CS4 to CS0: Clock period select bits
These bits set the serial clock frequency.
These bits can be written only when the I2C interface is disabled (EN = 0) or the EN bit is cleared.
The frequency fsck in the shift clock is set as shown in the next formula.
fsck =
φ
n × 12+16
n > 0 φ:machine clock (=CLKP)
447
CHAPTER 13 I2C INTERFACE
Register setting
n
CS4
CS3
CS2
CS1
CS0
1
0
0
0
0
1
2
0
0
0
1
0
3
0
0
0
1
1
•••
•••
•••
•••
•••
•••
31
1
1
1
1
1
CS4 to CS0=00000B is a set interdiction.
448
CHAPTER 13 I2C INTERFACE
13.2.4
10-bit Slave Address Register (ITBAH0 to ITBAH2,
ITBAL0 to ITBAL2)
The 10-bit slave address register (ITBAH0 to ITBAH2, ITBAL0 to ITBAL2) indicates the
10-bit slave address.
■ 10-bit Slave Address Register (ITBAH0 to ITBAH2, ITBAL0 to ITBAL2)
The following shows the register configuration of the 10-bit slave address register (ITBA).
ITBAH0 to ITBAH2
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
-
-
-
-
-
-
TA9
TA8
------00B
-
-
-
-
-
-
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
TA7
R/W
TA6
R/W
TA5
R/W
TA4
R/W
TA3
R/W
TA2
R/W
TA1
R/W
TA0
R/W
00000000B
ITBAL0 to ITBAL2
R/W: Readable/Writable
Writing to this register should be executed during operation of I2C interface is stopped. (ICCR EN=0)
[bit15 to bit10] Reserved: Reserved bits
Set to "0" at reading.
[bit9 to bit0] TA9 to TA0: 10-bit slave address bit (A9 to A0)
When 10-bit address is valid (ENTB=1: ITMK), and the slave address is received in the slave mode,
compare the received address with ITBA.
Acknowledge is transmitted to the master after address header of 10-bit write access is received.
Received data of the first and second bytes and the TBAL register are compared. When a match is
detected, an acknowledge signal transmits to the master device and the AAS bit is set.
I2C interface responds to the reception of address header for 10-bit read access after repetition START
condition.
All bits of the slave address are masked by setting of ITMK. The reception slave address is written to the
ITBA register. This register is effective only when "1" is set to ASS (IBSR register).
449
CHAPTER 13 I2C INTERFACE
13.2.5
10-bit Slave Address Mask Register
(ITMKH0 to ITMKH2, ITMKL0 to ITMKL2)
The 10-bit slave address mask register (ITMKH0 to ITMKH2, ITMKL0 to ITMKL2) has the
10-bit slave address mask and 10-bit slave address enable bit.
■ 10-bit Slave Address Mask Register (ITMKH0 to ITMKH2, ITMKL0 to ITMKL2)
The following shows the register configuration of the 10-bit slave address mask register (ITMKH0 to
ITMKH2, ITMKL0 to ITMKL2).
ITMKH0 to ITMKH2
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
ENTB
R/W
RAL
R
-
-
-
-
TM9
R/W
TM8
R/W
00----11B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
TM7
R/W
TM6
R/W
TM5
R/W
TM4
R/W
TM3
R/W
TM2
R/W
TM1
R/W
TM0
R/W
11111111B
ITMKL0 to ITMKL2
R/W: Readable/Writable
R:
Read only
[bit15] ENTB: 10-bit slave address enable bit
This bit is the 10-bit slave address enable bit.
Value
Description
0
10-bit slave address disabled [Initial value]
1
10-bit slave address enabled
Write to this bit while the I2C interface is stopped (ICCR EN = 0).
[bit14] RAL: Reception slave address length bit
This bit indicates the slave address length.
Value
Description
0
7-bit slave address [Initial value]
1
10-bit slave address
If the 10-bit and 7-bit slave address enable bits are both enabled (ENTB =1 and ENSB = 1), this bit can
be used to determine whether the transfer length of a 10-bit or 7-bit slave address becomes valid.
This bit is valid when the AAS bit (IBSR) is set to "1".
This bit is cleared when the interface is disabled (ICCR EN = 0).
This bit is read-only.
450
CHAPTER 13 I2C INTERFACE
[bit13 to bit10] Reserved: Reserved bits
These bits are reserved. The values read from these bits are always "1".
[bit9 to bit0] TM9 to TM0: 10-bit slave address mask bits
These bits mask the bits of the 10-bit slave address register (ITBA). Write to this register when the I2C
interface is disabled (ICCR EN = 0).
Value
Description
0
These bits are not used for comparison of slave addresses
1
These bits are used for comparison of slave addresses [Initial value]
Setting these bits enables transmission of an acknowledge to a compound 10-bit slave address. When
using this register for comparison of 10-bit slave addresses, set these bits to "1". The received slave
address is written to ITBA. When ASS = 1 (IBSR), the specified slave address can be determined by
reading the ITBA register.
Each of TM9 to TM0 bits of ITMK corresponds to one bit of the ITBA address. If the each value of the
TM9 to TM0 bits is 1, the ITBA address becomes valid; if it is 0, the ITBA address becomes invalid.
Example: ITBA address is 0010010111B and ITMK address is 1111111100B:
The slave address is in the space from 0010010100B to 0010010111B.
451
CHAPTER 13 I2C INTERFACE
13.2.6
7-bit Slave Address Register (ISBA0 to ISBA2)
The 7-bit slave address register (ISBA0 to ISBA2) indicates the 7-bit slave address.
■ 7-bit Slave Address Register (ISBA0 to ISBA2)
The following shows the register configuration of the 7-bit slave address register (ISBA0 to ISBA2).
ISBA0 to ISBA2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
SA6
R/W
SA5
R/W
SA4
R/W
SA3
R/W
SA2
R/W
SA1
R/W
SA0
R/W
-0000000B
R/W: Readable/Writable
Writing to this register should be executed during operation of I2C interface is stopped (ICCR EN=0).
[bit7] Reserved: Reserved bit
The read value is "0".
[bit6 to bit0] SA6 to SA0: Slave address bits
If a 7-bit slave address is enabled (ISMK ENSB = 1) when slave address data is received in slave mode,
these bits of ISBA and the received slave address data are compared. If a slave address match is
detected, an acknowledge is sent to the master and the AAS bit is set.
The I2C interface returns an acknowledge in response to reception of the address header of a 7-bit read
access after a repeated START condition is generated.
All bits of a slave address are masked using the setting of the ISMK. The received slave address data is
written to the ISBA register. This register is enabled only when AAS (IBSR register) is set to "1".
The I2C interface does not compare ISBA and the received slave address when a 10-bit slave address is
specified or a general call is received.
452
CHAPTER 13 I2C INTERFACE
13.2.7
7-bit Slave Address Mask Register (ISMK0 to ISMK2)
The 7-bit slave address mask register (ISMK0 to ISMK2) has the 7-bit slave address
mask and 7-bit slave address enable bit.
■ 7-bit Slave Address Mask Register (ISMK0 to ISMK2)
The following shows the register configuration of the 7-bit slave address mask register (ISMK0 to ISMK2).
ISMK0 to ISMK2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ENSB
R/W
SM6
R/W
SM5
R/W
SM4
R/W
SM3
R/W
SM2
R/W
SM1
R/W
SM0
R/W
01111111B
R/W: Readable/Writable
Write to this register while operation of I2C interface is stopped (ICCR EN=0).
[bit15] ENSB: 7-bit slave address enable bit
This bit is the 7-bit slave address enable bit.
Value
Description
0
7-bit slave address disabled [Initial value]
1
7-bit slave address enabled
[bit14 to bit8] SM6 to SM0: 7-bit slave address mask bits
These bits mask the bits of the 7-bit slave address register (ISBA).
Value
Description
0
These bits are not used for comparison of slave addresses
1
These bits are used for comparison of slave addresses [Initial value]
Setting these bits enables transmission of an acknowledge to a compound 7-bit slave address. When
using this register for comparison of a 7-bit slave address, set these bits to "1". The received slave
address is written to ISBA. When ASS = 1 (IBSR), the specified slave address can be determined by
reading the ISBA register.
After the I2C interface is enabled, the slave address (ISBA) is rewritten by reception operation. When
SMK is rewritten, SMK must be set again to provide the expected operation.
Each of the SM6 to 0 bits of ISMK corresponds to one bit of the ISBA address. If the each value of the
SM6 to 0 bits is "1", the ISBA address becomes valid; if it is "0", the ISBA address becomes invalid.
Example: If ISBA address is 0010111B and ISMK address is 1111100B, the slave address is in the
space from 0010100B to 0010111B.
453
CHAPTER 13 I2C INTERFACE
13.2.8
Data Register (IDAR0 to IDAR2)
This section describes the configuration and functions of the data register (IDAR0 to
IDAR2).
■ Data Register (IDAR0 to IDAR2)
The following shows the register configuration of the data register (IDAR0 to IDAR2).
IDAR0 to IDAR2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00000000B
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/Writable
[bit7 to bit0] D7 to D0: Data bits
Bits D7 to D0 are a data register used for the serial transfer and transferred from MSB.
The writing side of this register has a double buffer. While the bus is busy (BB = 1), write data is loaded
into the register for serial transfer. When the INT bit (IBCR) is cleared or the bus is idle (IBSR BB = 0),
transfer data is loaded into the internal transfer register.
Since data is directly read from the register for serial transfer during reading, receive data in this register
is valid only while the INT bit (IBCR) is set.
454
CHAPTER 13 I2C INTERFACE
13.3
Operation Explanation of I2C Interface
The I2C bus consists of two bidirectional bus lines used for transfer: one serial data line
(SDA) and one serial clock line (SCL). The I2C interface, which has 2 open drain inputoutput pins (SDA and SCL) to them, allows wired logic.
■ START Condition
Write "1" to the MSS bit while the bus is open (BB=0, MSS=0) to place the I2C interface in master mode
and to generate a START condition. The interface sends the value of the IDAR register as a slave address.
Write "1" to the SCC bit while the interrupt flag is set in bus master mode (IBCR MSS =1, INT = 1) to
generate a repeated START condition.
Write "1" to the MSS bit while the bus is busy (IBSR BB = 1, TRX = 0, IBCR MSS = 0 or INT = 0) to
release the bus and start transmission.
If a write (reception) access is performed in slave mode, the interface starts transmission after transmission
is completed and the bus is released. If the interface is sending data, it does not start transmission even
though the bus has been released.
The interface must be checked for the following:
• Whether the interface is specified as a slave (IBCR MSS=0, IBSR AAS=1)
• Whether data byte transmission is normal (IBSR AL=1) when the next interrupt is received
■ STOP Condition
Write "0" to the MSS bit in master mode (IBCR MSS = 1, INT = 1) to generate a STOP condition and to
place the interface in slave mode. Writing "0" to the MSS bit in any other state is ignored.
After the MSS bit is cleared, the interface attempts to generate a STOP condition. However, a STOP
condition will not be generated if the SCL line is driven to "L". An interrupt is generated after the next byte
is transferred.
Note:
After "0" is written to the MSS bit, it takes time until a STOP condition is generated. If the I2C
interface is disabled (IDAR DBL = 1 or ICCR EN = 0) before the START condition is generated, the
operation stops immediately and an incorrect clock is generated on the SCL line. Disable the I2C
interface (IDAR DBL = 1 or ICCR EN = 0) after checking that a START condition has been
generated (IBSR BB = 0).
455
CHAPTER 13 I2C INTERFACE
■ Slave Address Detection
In slave mode, BB=1 is set after a START condition is generated. The transmission data from the master is
stored in the IDAR register.
[When a 7-bit slave address is enabled] (ISMK ENSB=1)
After 8-bit data is received, the IDAR and ISBA register values are compared. At this time, the values are
compared with the values of the bits masked with the ISMK register.
If the comparison result is a match, the AAS bit is set to "1" and an acknowledge is sent to the master.
The value of bit0 of the received data (bit0 of the IDAR register after reception) is then inverted and
stored in the TRX bit.
[When a 10-bit slave address is enabled] (ITMK ENTB=1)
If the header section of a 10-bit address (11110, TA1, TA0, write) is detected, an acknowledge is sent to
the master and the value of bit0 of received data is inverted and stored in the TRX bit. No interrupt
occurs at this time.
Then, the next data to be transferred and the low-order data of the ITBA register are compared. They are
compared with the values of the bits masked with the ISMK register.
If the result is a match, the AAS bit is set to "1", an acknowledge is sent to the master, and an interrupt
occurs.
If the address has been specified as a slave and a repeated START condition is detected, the AAS bit is
set to "1" and an interrupt occurs after the header section of a 10-bit address (11110, TA1, TA0, read) is
received.
The interface has a 10-bit slave address register (ITBA) and a 7-bit slave address register (ISBA). If both
registers are enabled (ISMK ENSB = 1, ITMK ENTB = 1), an acknowledge can be sent for the 10-bit
and 7-bit addresses.
The receive slave address length in slave mode (AAS = 1) is determined by the RAL bit of the ITMK
register. In master mode, disabling both registers (ISMK ENSB = 0, ITMK ENTB = 0) can prevent a
slave address from being generated for the I2C interface.
All slave addresses can be masked by setting the ITMK and ISMK registers.
■ Slave Address Mask
The slave address mask registers (ITMK and ISMK) can mask each bit of the slave address registers. A bit
set to "1" in the mask register is address-compared while a bit set to "0" is ignored. In slave mode (IBSR
AAS = 1), a receive slave address can be read from the ITBA register (for a 10-bit address) or the ISBA
register (for a 7-bit address).
If the bit mask is cleared, the interface can be used as the bus monitor because it is always accessed as a
slave.
Note:
This feature does not become a real bus monitor because it returns an acknowledge when a slave
address is received even though no other slave device is available.
456
CHAPTER 13 I2C INTERFACE
■ Slave Addressing
In master mode, BB = 1 and TRX = 1 are set after a START condition is generated and the IDAR register
contents are outputted starting with the MSB. After sending the address data, receives the
acknowledgement from the slave, reverses bit0 (bit0 of IDAR register that is already sent) of the sending
data, and then stores it into TRX bit. This operation is executed in a repeat START condition as well.
Two bytes are sent for a 10-bit slave address during write access. The first byte consists of the header
section (11110A9A80) that indicates a 10-bit sequence, and the second byte sends the low-order 8 bits of
the slave address (A7 to A0).
The 10-bit slave device in the read access state sends the above bytes and generates a repeated START
condition as well as the header section (11110A9A81) that indicates a read access.
Write
START condition: A6 A5 A4 A3 A2 A1 A0 0
Read
START condition: A6 A5 A4 A3 A2 A1 A0 1
Write
START condition: 1 1 1 1 0 A9 A8 0-A7 A6 A5 A4 A3 A2 A1
A0
Read
START condition: 1 1 1 1 0 A9 A8 0-A7 A6 A5 A4 A3 A2 A1
A0
Repeated START condition: -1 1 1 1 0 A9 A8 1
7-bit slave access
10-bit slave access
■ Arbitration
If other master are sending the data simultaneously in the master sending mode, the arbitration will occur.
If data sent by the local device is "1" and the data on the SDA line is the "L" level, the local device assumes
arbitration to have been lost and sets AL=1.
AL = 1 is set if the interface detects an unnecessary START condition in the first bit of the data or neither a
START condition nor a STOP condition can be generated.
If the arbitration lost is detected, MSS = 0 and TRX = 0 are set and the device enters slave receive mode
and returns an acknowledge when it receives the device's own slave address.
■ Acknowledge
The receiver sends the acknowledge to the sender. The ACK bit (IBCR) can specify whether an
acknowledge is sent when data is received.
Even if an acknowledge is not returned from the master during data transmission in slave mode (read
access from other master devices), the TRX bit is set to "0" and the device enters receive mode. This allows
the master to generate a STOP condition when the slave releases the SCL line.
In master mode, an acknowledge can be checked by reading the LRB bit (IBSR).
If the arbitration lost occurred after the general call address is transmitted when the acknowledge is
responded at the data (including data that is generated) reception, both ACK bit and GCAA bit are set to
"1". Otherwise, the acknowledge is not responded.
457
CHAPTER 13 I2C INTERFACE
■ Bus Error
If the following conditions exist, it will be considered as bus error, and the I2C interface will be in the
stopped state.
• A violation of the bus protocol on the I2C bus during data transfer (including the ACK bit) is detected.
• A stop condition in master mode is detected.
• A violation of the bus protocol on the I2C bus while the bus is idle is detected.
■ Communication Error That Causes No Error
If an incorrect clock is generated on the SCL line due to noise or some other reason during transmission in
master mode, the transmission bit counter of the I2C interface may run quickly, causing the slave to hang
up while the "L" level appears on the SDA line in the ACK cycle. An error (AL = 1, BER = 1) does not
occur for such an incorrect clock.
If this situation occurs, perform the following error processing:
1. Determine that when MSS = 1, TRX = 1, INT = 1, and LRB = 1, there is a communication error.
2. Set EN to "0", and then set EN to "1" to cause SCL to generate one clock on a pseudo basis.
This action causes the slave to release the bus.
The period from when EN is set to "0" until EN is set to "1" must be long enough for the slave to
recognize it as a clock (about as long as the "H" period of a transmission clock).
3. Since IBSR and IBCR are cleared when EN is set to "0", perform retransmission processing from the
START condition. At this time, a STOP condition cannot be generated even if BSS is set to "0".
Insert an interval equal to or longer than n × 7 × tCCP between the point where EN is set to "1" and the
point where MSS is set to "1" (START condition).
Example:
High-speed mode: 6 × 7 × 40 =: 1.680 µs
Standard mode: 27 × 7 × 40 =: 7.560 µs
(When CLKP=25MHz)
Note:
When BER is set, it is not cleared even if EN is set to "0". Clear BER, and then retransmit it.
458
CHAPTER 13 I2C INTERFACE
■ The Others
1. After the arbitration lost occurs, check whether or not the local device is addressed using software.
When the arbitration lost occurs, the device becomes a slave in terms of hardware. However, after onebyte transfer is completed, both the clock and data lines are pulled to "L". Thus, if the device is not
addressed, immediately open the clock and data lines. If the device is addressed, open the clock and data
lines after preparing for slave transmission or reception. (All of these things must be processed using
software.)
2. Since the I2C bus has only one interrupt, an interrupt source is generated when one-byte transfer is
completed or when an interrupt condition is met.
Since multiple interrupt conditions must be checked using one interrupt, each of the flags must be
checked by the interrupt routine. Multiple conditions of interrupts on completion of one-byte transfer is
as follows.
- When it is a bus master
- When it is a slave that the address is done
- When receiving the general call address
- Arbitration lost occurs.
3. When the arbitration lost is detected, an interrupt source is generated, not immediately but after one-byte
transfer is completed.
When the arbitration lost is detected, the device automatically becomes a slave. However, in slave
mode, a total of nine clocks must be outputted before an interrupt source can be generated. Thus, since
an interrupt source is not immediately generated, no processing can be performed after the arbitration
lost occurs.
459
CHAPTER 13 I2C INTERFACE
13.4
Operation Flowcharts
This section provides operation flowcharts using slave address/data transfer, and
reception data as examples.
■ Example of Slave Address and Data Transfer
Figure 13.4-1 shows an example of slave address and data transfer.
Figure 13.4-1 Example of Slave Address and Data Transfer
7-bit slave addressing
Transfer data
Start
Start
BER bit clear (set)
Slave address in
write access
Interface enable EN=1
IDAR =S.address<<1+R W
MSS=1
IDAR = Byte data
INT=0
INT=0
NO
NO
INT=1?
INT=1?
YES
YES
YES
YES
BER=1?
Bus error
BER=1?
NO
YES
AL=1?
NO
Restart and
transfer due to
YES Restart and
AL=1?
check of ASS
NO
ACK=?
(LRB=0?)
NO
NO
YES
Preparing for
data transfer
Transfer completed
- The slave does not generate
ACK, or the master cannot
receive ACK.
- Set EN to 0 at first, and
resend data.
460
transfer due to
check of AAS
ACK=?
(LRB=0?)
NO
YES
Transfer
of last byte
YES
NO
Transfer completed
- Generate a repeated START
condition or STOP condition.
- Check that a STOP condition
has been generated (BB=0),
and set EN to 0.
Transfer completed
Transmission:
- The slave does not generate
ACK,or the master cannot
receive ACK.
- Set EN to 0 for retransmission.
Reception:
Generate a repeated START
condition or STOP condition
without acknowledge.
CHAPTER 13 I2C INTERFACE
■ Example of Receive Data
Figure 13.4-2 shows an example of receive data.
Figure 13.4-2 Example of Receive Data
Start
Slave address in read access
Clear the ACK bit if data
is the last read data from
slave
INT=0
NO
INT=1?
YES
YES
BER=1?
Bus error
Restart
NO
NO
Transfer
of last
byte
YES
Transfer completed
Generates repeated
START condition or STOP
condition.
461
CHAPTER 13 I2C INTERFACE
■ Interrupt Processing
Figure 13.4-3 shows interrupt processing.
Figure 13.4-3 Interrupt Processing
START
NO
INT=1?
Receive
interrupt from
another module
YES
YES
Bus error
Restart
BER=1?
NO
GCA=1?
YES
NO
NO
Failure of
transfer Retry
AAS=1?
General call detected in
slave mode
YES
YES
YES
Arbitration lost
Retransfer
AL=1?
AL=1?
NO
YES No ACK from slave.
NO
Generate STOP
condition or repeated
START condition.
LRB=1?
YES
ADT=1
Start to transfer new
data upon next
interrupt.
If required,change
ACK bit.
NO
YES
NO
TRX=1?
TRX=1?
YES
NO
NO
Read received data
from IDAR.
If required, change
ACK bit.
Write next
send data
to IDAR.
Read received data
from IDAR.
If required, change
ACK bit.
Clear INT bit.
End of ISR
462
Write next send
data to IDAR.
Or clear MSS bit.
CHAPTER 14
16-BIT RELOAD TIMER
This chapter explains register configuration/ function
and timer operation of 16-bit reload timer.
14.1 Overview of the 16-bit Reload Timer
14.2 Registers of the 16-bit Reload Timer
14.3 Operation of 16-bit Reload Timer
463
CHAPTER 14 16-BIT RELOAD TIMER
14.1
Overview of the 16-bit Reload Timer
The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, an
internal count, a prescaler for creating clock, and a control register.
■ Overview of the 16-bit Reload Timer
The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, an internal count, a
prescaler for creating clock, and a control register.
The clock source can be selected from three internal clocks (machine clock divided by 2, 8, and 32) and an
external event.
■ Block Diagram of 16-bit Reload Timer
Figure 14.1-1 is a block diagram of the 16-bit reload timer.
Figure 14.1-1 Block Diagram of the 16-bit Reload Timer
16-bit reload register
(TMRLR)
Reload
R-bus
16-bit down counter (TMR)
UF
OUT
CTL
Count
enable
Clock
selector
CSL1
CSL0
EXCK
Prescaler
φ
464
RELD
OUTL
INTE
UF
CNTE
TRG
Prescaler
clear
IRQ
External timer
output
IN CTL
CSL1
CSL0
TOE0 to
TOE3
External
trigger select
Bit in PFR
External trigger input
CHAPTER 14 16-BIT RELOAD TIMER
14.2
Registers of the 16-bit Reload Timer
This section describes the configuration and functions of the registers used by the 16bit reload timer.
■ 16-bit Reload Timer Registers
Figure 14.2-1 16-bit Reload Timer Registers
TMCSR high byte
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
-
-
-
-
CSL1
R/W
CSL0
R/W
MOD1
R/W
MOD0
R/W
----0000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
MOD0
R/W
R
OUTL
R/W
RELD
R/W
INTE
R/W
UF
R/W
CNTE
R/W
TRG
R/W
00000000B
bit0
Initial value
TMCSR low byte
TMR
bit15
XXXXH
R
TMRLR
bit15
bit0
Initial value
XXXXH
W
R/W:
R:
W:
X:
Readable/Writable
Read only
Write only
Undefined
465
CHAPTER 14 16-BIT RELOAD TIMER
14.2.1
Control Status Registers (TMCSR)
The control status register (TMCSR) controls the operating modes and interrupts of the
16-bit reload timer.
■ Bit Configuration of the Control Status Register (TMCSR)
TMCSR high byte
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
-
-
-
-
CSL1
R/W
CSL0
R/W
MOD1
R/W
MOD0
R/W
----0000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
MOD0
R/W
R
OUTL
R/W
RELD
R/W
INTE
R/W
UF
R/W
CNTE
R/W
TRG
R/W
00000000B
TMCSR low byte
R/W: Readable/Writable
R:
Read only
[bit15 to bit12] Reserved: Reserved bits
Reserved bits
Reading value is always "0000B".
[bit11, bit10] CSL1, CSL0: Count source select bits
These bits are the count source select bits. Count sources can be selected from the internal clock or the
external event. The count sources that can be selected using these bits is shows in the following.
Count source
(φ : Machine clock)
φ=32MHz
φ=16MHz
φ/21 [initial value]
62.5ns
125ns
Internal clock
φ/23
250ns
500ns
0
Internal clock
φ/25
1.0µs
2.0µs
1
External event
-
-
CSL1
CSL0
0
0
Internal clock
0
1
1
1
Countable edges used when external event is set as the count source are set by the MOD1 and MOD0
bits.
The minimum pulse width required for an external clock is 2 × T (T: Machine clock cycle).
466
CHAPTER 14 16-BIT RELOAD TIMER
[bit9 to bit7] MOD2, MOD1, MOD0: Mode bits
These bits set the operating modes. These functions are switched by the count source ("internal clock" or
"external clock").
Internal clock mode
: setting reload trigger
External clock mode
: setting count enable edge
The MOD2 bit has to be set to "0".
[Reload trigger setting at selecting internal clock]
When internal clock is selected as count source, the contents of reload register are loaded after inputted
valid edge by setting MOD2 to MOD0 bits, and count function keeps operating.
MOD2
MOD1
MOD0
Valid edge
0
0
0
Software trigger [initial value]
0
0
1
External trigger (rising edge)
0
1
0
External trigger (falling edge)
0
1
1
External trigger (both edges)
1
X
X
Setting disabled
[Valid edge setting at selecting external clock]
When external clock event is selected as count source, the event is counted after inputted valid edge by
setting MOD2 to MOD0 bits.
MOD2
MOD1
MOD0
Valid edge
X
0
0
- [initial value]
X
0
1
External trigger (rising edge)
X
1
0
External trigger (falling edge)
X
1
1
External trigger (both edges)
Reload of external event is generated by underflow and software trigger.
[bit6] Reserved: Reserved bit
Reserved bit
Reading value is always "0".
[bit5] OUTL: Output level
This bit sets the external timer output level. The output level is reversed depending on whether this bit is
"0" or "1".
467
CHAPTER 14 16-BIT RELOAD TIMER
[bit4] RELD: Reload enable bit
This bit is the reload enable bit. If it is set to "1", reload mode is entered. As soon as the counter value
underflows from "0000H" to "FFFFH", the contents of the reload register are loaded into the counter and
the count operation is continued.
If this bit is set to "0", one-shot mode is entered, and the count operation is stopped when the counter
value underflows from "0000H" to "FFFFH".
PFRxy
OUTL
RELD
Output waveform
0
X
X
Output disabled [initial state]
1
0
0
Rectangular wave of "H" during counting
1
0
1
Rectangular wave of "L" during counting
1
1
0
Toggle output of "L" at count start
1
1
1
Toggle output of "H" at count start
PFRxy means the PFR register value of corresponding pin.
[bit3] INTE: Interrupt enable bit
This bit is the interrupt request enable bit. If the INTE bit is set to "1", an interrupt request is generated
when the UF bit is set to "1". If it is set to "0", no interrupt request is generated.
[bit2] UF: Underflow interrupt flag
This bit is the timer interrupt request flag. This bit is set to "1" when the counter value underflows from
"0000H" to "FFFFH". Write "0" to this bit to clear it.
Writing "1" to this bit is meaningless.
When this bit is read by a read-modify-write instruction, "1" is always read.
[bit1] CNTE: Count enable bit
This bit is the count enable bit of the timer. Write "1" to this bit to enter the start trigger wait state. Write
"0" to this bit to stop the count operation.
[bit0] TRG: Trigger bit
This bit is the software trigger bit. Write "1" to this bit to generate a software trigger, load the contents of
the reload register into the counter, and start the count operation.
Writing "0" to this bit is meaningless. The read value is always "0".
The trigger input to this register is valid only if CNTE=1. No operation occurs if CNTE=0.
Note:
Rewrite the bit other than UF, CNTE, and TRG bits if CNTE=0.
468
CHAPTER 14 16-BIT RELOAD TIMER
14.2.2
16-bit Timer Register (TMR)
The 16-bit timer register (TMR) is a register to which the count value of the 16-bit timer
can be read.
■ Bit Configuration of the 16-bit Timer Register (TMR)
TMR
bit15
bit0
Initial value
XXXXH
R
R:
X:
Read only
Undefined
This register can read the count value of 16-bit timer. The initial value is undefined. Be sure to read this
register using a 16-bit data transfer instruction.
469
CHAPTER 14 16-BIT RELOAD TIMER
14.2.3
16-bit Reload Register (TMRLR)
The 16-bit reload register (TMRLR) holds the initial value of a counter.
■ Bit Configuration of the 16-bit Reload Register (TMRLR)
TMRLR
bit15
bit0
Initial value
XXXXH
W
W:
X:
Write only
Undefined
This register is the register for holding the initial value of a counter. The initial value is undefined. Be sure
to read this register using a 16-bit data transfer instruction.
470
CHAPTER 14 16-BIT RELOAD TIMER
14.3
Operation of 16-bit Reload Timer
This section describes the following operations of the 16-bit reload timer:
• Internal clock operation
• Underflow operation
• Output pin function
■ Internal Clock Operation
If the timer operates with a divide-by clock of the internal clock, one of the clocks created by dividing the
machine clock by 2, 8, or 32 can be selected as the count source.
To start the count operation as soon as counting is enabled, write "1" to the CNTE and TRG bits of the
control status register.
Trigger input occurring due to the TRG bit is always valid regardless of the operating mode while the timer
is running (CNTE=1).
Time as long as T (T: peripheral clock machine cycle) is required after the counter start trigger is inputted
and before the data of the reload register is actually loaded into the counter.
Figure 14.3-1 Startup and Operations of the Counter
Count clock
Counter
Reload data
-1
-1
-1
Data load
CNTE bit
TRG bit
T
471
CHAPTER 14 16-BIT RELOAD TIMER
■ Underflow Operation
An underflow is an event in which the counter value changes from "0000H" to "FFFFH". Thus, an
underflow occurs at the count of [Reload register setting value + 1].
If the RELD bit of the control register is set to "1" when an underflow occurs, the contents of the reload
register are loaded into the counter and the count operation is continued. If the RELD bit is set to "0", the
counter stops at "FFFFH".
Figure 14.3-2 Underflow Operation
[RELD=1]
Count clock
Counter
0000H
Reload data
0000H
FFFFH
Data load
Underflow set
[RELD=0]
Count clock
Counter
Underflow set
472
-1
-1
-1
CHAPTER 14 16-BIT RELOAD TIMER
■ Output Pin Function
The TOT output pin provides a toggle output that is inverted by an underflow in reload mode and a pulse
output that indicates that counting is in progress in one-shot mode. The output polarity can be set using the
OUTL bit of the register. If OUTL=0, toggle output is "0" for the initial value and the one-shot pulse output
is "1" while the count operation is in progress. If OUTL=1, the output waveform is reversed.
Figure 14.3-3 Output Pin Function [RELD=1, OUTL=0]
Count start
Underflow
TOT0 to TOT3
Inverted at OUTL=1
General-purpose port
CNTE
Start trigger
Figure 14.3-4 Output Pin Function [RELD=0, OUTL=0]
Count start
Underflow
TOT0 to TOT3
Inverted at
OUTL=1
General-purpose port
CNTE
Start trigger
Start trigger waiting state
473
CHAPTER 14 16-BIT RELOAD TIMER
■ Operating Status of Counter
The counter state is determined by the CNTE bit of the control register and the WAIT signal, which is an
internal signal. The states that can be set include the stop state, when CNTE=0 and WAIT=1 (STOP state);
the startup trigger wait state, when CNTE=1 and WAIT=1 (WAIT state); and the operation state, when
CNTE=1 and WAIT=0 (RUN state).
Figure 14.3-5 Counter Status Transfer
State transmitted by hardware
Reset
State transmitted by register access
STOP CNTE=0,WAIT=1
Counter : Holds the value
when it stops; undefined
just after reset
CNTE=1
TRG=0
WAIT CNTE=1,WAIT=1
Counter : Holds the value
when it stops; undefined
just after reset and until
data is loaded
TRG=1
CNTE=1
TRG=1
RUN CNTE=1,WAIT=0
Counter: operation
RELD, UF
TRG=1
LOAD CNTE=1,WAIT=0
Loads contents of reload
register into counter
RELD,UF
Load completed
■ Note
• The internal prescaler is enabled if a trigger (software or external trigger) is applied while bit1 (timer
enable: CNTE) of the control status register is set to "1".
• If the device attempts to set and clear the interrupt request flag at the same time, the flag is set and the
clear operation becomes ineffective.
• If the device attempts to write to the 16-bit timer reload register and reload the data into the 16-bit timer
reload register at the same time, old data is loaded into the counter. New data is loaded into the counter
only in the next reload timing.
• If the device attempts to load and count the 16-bit timer register at the same time, the load (reload)
operation takes precedence.
474
CHAPTER 15
16-BIT FREE-RUN TIMER
This chapter describes the functions and operation of
the 16-bit free-run timer.
15.1 Overview of 16-bit Free-run Timer
15.2 16-bit Free-run Timer Registers
15.3 Operation of 16-bit Free-run Timer
15.4 Notes on Using the 16-bit Free-run Timer
475
CHAPTER 15 16-BIT FREE-RUN TIMER
15.1
Overview of 16-bit Free-run Timer
The 16-bit free-run timer consists of a 16-bit timer (up counter) and control circuit. The
16-bit free-run timer can be used with combination of the input capture and the output
compare.
■ Overview of 16-bit Free-run Timer
The 16-bit free-run timer consists of a 16-bit up counter and control status register. The count value from
the 16-bit free-run timer is used as the base time for the output compare and input capture.
• The count clock can be selected from four different clocks.
• An interrupt can be generated when a counter overflow occurs.
• A mode setting is available that initializes the counter when a match with the value in compare register
(in the output compare unit) occurs.
■ Block Diagram of 16-bit Free-run Timer
Figure 15.1-1 Block Diagram of 16-bit Free-run Timer
Interrupt
IVF
IVFE
STOP MODE
CLR
CLK1
CLK0
R-bus
ECLK
Divide freq.
φ
FRCK
Clock selector
16-bit free-run timer
(TCDT)
Clock
To internal circuit
Comparator
476
(T15 to T00)
CHAPTER 15 16-BIT FREE-RUN TIMER
15.2
16-bit Free-run Timer Registers
This section explains the 16-bit free-run timer registers.
■ 16-bit Free-run Timer Registers
TCDT high byte
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00000000B
T15
T14
T13
T12
T11
T10
T09
T08
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
T07
R/W
T06
R/W
T05
R/W
T04
R/W
T03
R/W
T02
R/W
T01
R/W
T00
R/W
00000000B
TCDT low byte
TCCS
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ECLK
IVF
IVFE
STOP
MODE
CLR
CLK1
CLK0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/Writable
477
CHAPTER 15 16-BIT FREE-RUN TIMER
15.2.1
Timer Data Register (TCDT)
The timer data register (TCDT) is used to read the count value of the 16-bit free-run
timer.
■ Timer Data Register (TCDT)
TCDT high byte
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
T15
R/W
T14
R/W
T13
R/W
T12
R/W
T11
R/W
T10
R/W
T09
R/W
T08
R/W
00000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
T07
R/W
T06
R/W
T05
R/W
T04
R/W
T03
R/W
T02
R/W
T01
R/W
T00
R/W
00000000B
TCDT low byte
R/W: Readable/Writable
The counter value of the timer data register is initialized to" 0000H" by a reset. Write to this register to set
the timer value.
Note that this register must be written to while the 16-bit free-run timer is stopped (STOP in TCCS
register=1).
The 16-bit free-run timer is initialized as the following factor:
• Initialization by a reset
• Initialization by writing "1" to CLR bit of the timer control status register
• Initialization due to match of the compare clear register value in the output compare and the timer
counter value (Mode setting is required).
Note:
Access to this register must be halfword (16-bit) access.
478
CHAPTER 15 16-BIT FREE-RUN TIMER
15.2.2
Timer Control Status Register (TCCS)
The timer control status register (TCCS) is used to control the count value of the 16-bit
free-run timer.
■ Timer Control Status Register (TCCS)
TCCS
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ECLK
R/W
IVF
R/W
IVFE
R/W
STOP
R/W
MODE
R/W
CLR
R/W
CLK1
R/W
CLK0
R/W
00000000B
R/W: Readable/Writable
[bit7] ECKL: Clock select bit
This bit selects either the internal or external clock as count clock source for the 16-bit free-run timer.
Select the clock source while output compare and input capture are stopped.
ECLK
Clock selection
0
Selects the internal clock source (CLKP) [Initial value]
1
Selects the external pin (FRCK).
Note:
If the internal clock is selected, set the count clock in bits 1 and 0 (CLK1 and CLK0) of TCCS
register. This count clock is handled as the base clock. If a clock is inputted from FRCK, set the
corresponding DDR bit to 0 (input port).
The minimum pulse width required for the external clock is 2 × T (T: Peripheral clock cycle).
If the external clock is specified and output compare is used, a compare match or interrupt occurs at
the next clock cycle. For a compare match to be outputted and an interrupt to occur, at least one
clock cycle must be inputted after the compare match.
[bit6] IVF: Interrupt request flag
IVF is the interrupt request flag of the 16-bit free-run timer.
When the 16-bit free-run timer overflows or when, as a result of the mode setting, a match with compare
register, this bit is set to "1".
An interrupt occurs when the interrupt request enable bit (IVFE) is set.
Write "0" to this bit to clear it. A read-modify-write instruction always reads "1" from this bit.
While the IVF bit is initialized to "0" at a reset, the free-run timer remains operating. The IVF bit is
therefore set to "1" after the overflow generation period has passed.
479
CHAPTER 15 16-BIT FREE-RUN TIMER
IVF
Interrupt request flag
0
No interrupt request [Initial value]
1
Interrupt request
[bit5] IVFE: Interruption enable bit
IVFE is the interrupt enable bit of the 16-bit free-run timer.
When this bit is set to "1" and the IVF bit is set to "1", an interrupt occurs.
IVFE
Interruption permission
0
Interrupt disabled [initial value]
1
Interruption enabled
[bit4] STOP: STOP bit
The STOP bit is used to stop counting by the 16-bit free-run timer.
STOP
Count operation
0
Count enabled (operation) [Initial value]
1
Count disabled (stop)
Note:
When the 16-bit free-run timer stops, the output compare operation also stops.
[bit3] MODE: Mode setting bit
The MODE bit is used to set the initialization conditions of the 16-bit free-run timer.
When this bit is set to "0", the counter value can be initialized by a reset and the CLR bit (bit2).
When this bit is set to "1", the counter value can be initialized as the result of a match with the value of
compare register in the output compare unit as well as by a reset and the CLR bit (bit2).
MODE
480
Timer initialization condition
0
Reset, clear bit [Initial value]
1
Reset, clear bit, compare register
CHAPTER 15 16-BIT FREE-RUN TIMER
[bit2] CLR: Timer clear bit
This bit is used to initialize the value of the operating 16-bit free-run timer to "0000H".
When "1" is written to this bit, the timer value is initialized to "0000H".
"1" is always read from this bit.
Note:
The initialization of the counter takes place at count value change points. After "1" is written to the
CLR bit, the counter clear request is canceled when "0" is written before the counter is cleared.
To initialize the counter value while the timer is stopped, write "0000H" to the data register.
[bit1, bit0] CLK1, CLK0: Count clock selection bits
These bits are used to select the count clock of the 16-bit free-run timer.
Immediately after a value is written to these bits, the count clock is updated. Therefore, be sure to stop
the output compare and input capture operation before changing a value to these bits.
CLK1
CLK0
Count Clock(φ)
φ=32MHz
φ=16MHz
0
0
φ/22
125ns
250ns
0
1
φ/24
500ns
1.0µs
1
0
φ/25
1.0µs
2.0µs
1
1
φ/26
2.0µs
4.0µs
φ: Machine clock (CLKP) frequency
481
CHAPTER 15 16-BIT FREE-RUN TIMER
15.3
Operation of 16-bit Free-run Timer
The 16-bit free-run timer starts counting at the counter value of "0000H" when a reset
has been released. This counter value is a reference time for the 16-bit output compare
and 16-bit input capture.
■ Explanation of Operation of 16-bit Free-run Timer
The counter value is cleared by the following condition.
• An overflow occurs
• A compare match with the compare clear register (output compare register) value (A mode setting is
required).
• "1" is written to the CLR bit of the TCCS register during operation.
• "0000H" is written to the TCDT register while the timer is stopped.
• A reset occurs.
An interrupt can occur when an overflow occurs because a compare match with the compare clear register
value occurs (A mode setting is required for a compare match interrupt).
Figure 15.3-1 Clearing of Counter by an Overflow
Counter Value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Reset
Interrupt
482
Time
CHAPTER 15 16-BIT FREE-RUN TIMER
Figure 15.3-2 Clearing of Counter by a Compare Match with the Compare Clear Register Value
Counter Value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
BFFFH
Compare register
Interrupt
■ Clear Timing of the 16-bit Free-run Timer
The counter can be cleared by a reset, software, or a match with the compare clear register.
A reset and software clear the counter as soon as the clear occurs. A match with the compare clear register,
however, clears the counter in synchronization with the count timing.
Figure 15.3-3 Clear Timing of the 16-bit Free-run Timer
φ
Compare clear
register value
N
Counter clear
Counter value
N
0000H
■ Count Timing of the 16-bit Free-run Timer
The 16-bit free-run timer counts up according to an input clock (internal or external clock). When an
external clock is selected, the clock’s falling edge is synchronized with the system clock, then the falling
edge of the internal count clock is counted.
Figure 15.3-4 Count Timing of Free-run Timer
φ
External clock input
Internal clock input
Counter value
N
N+1
483
CHAPTER 15 16-BIT FREE-RUN TIMER
15.4
Notes on Using the 16-bit Free-run Timer
This section contains notes on using the 16-bit free-run timer.
■ Notes on Using the 16-bit Free-run Timer
• If the interrupt request flag set timing and clear timing occur simultaneously, the flag setting operation
overrides the flag clearing operation.
• When bit2 (counter initialize bit: CLR) in the control status register is set to "1", it holds the value until
the internal counter clear timing and clears itself at that timing. If the clear timing and writing "1" occur
simultaneously, the write operation overrides the clear operation and the CLR bit remains "1" until next
clear timing.
• The counter clear operation is valid only while the internal counter is operating (with the internal
prescaler also operating). To clear the counter being stopped, set the timer count data register to
"0000H".
484
CHAPTER 16
INPUT CAPTURE
This chapter describes the function and operation of the
input capture.
16.1 Overview of the Input Capture
16.2 Input Capture Registers
16.3 Operation of Input Capture
485
CHAPTER 16 INPUT CAPTURE
16.1
Overview of the Input Capture
The input capture unit detects rising edges, falling edges, or both edges of the external
input signal and saves the value of the 16-bit free-run timer at that time to a register.
The unit can also generate an interrupt when an edge is detected.
The input capture consists of an input capture data register and control register.
■ Overview of Input Capture
Each input capture has its own external input pin.
• The valid edge of the external input can be selected from three types:
- Rising edge
- Falling edge
- Both edges
• The input capture can generate an interrupt when an active edge of external input is detected.
■ Block Diagram of Input Capture
16bit Timer Count Value (T15 to T00)
IN0
Input Pin
Edge
Detection
R-bus
Capture Data Register
ch.0
EG11
EG10
EG01
EG00
16-bit Timer Count Value (T15 to T00)
Capture Data Register
ch.1
ICP1
IN1
Input Pin
Edge
Detection
ICP0
ICE1
ICE0
Interrupt
Interrupt
486
CHAPTER 16 INPUT CAPTURE
16.2
Input Capture Registers
The input capture unit has the following two registers:
• Input capture register (IPCP0, IPCP1)
• Input capture control register (ICS01)
This section describes these registers in detail.
■ List of Register of Input Capture
IPCP high byte
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
CP15
CP14
CP13
CP12
CP11
CP10
CP09
CP08
XXXXXXXXB
R
R
R
R
R
R
R
R
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
CP07
R
CP06
R
CP05
R
CP04
R
CP03
R
CP02
R
CP01
R
CP00
R
XXXXXXXXB
IPCP low byte
ICS
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ICP1
R/W
ICP0
R/W
ICE1
R/W
ICE0
R/W
EG11
R/W
EG10
R/W
EG01
R/W
EG00
R/W
00000000B
R/W: Readable/Writable
R:
Read only
X:
Undefined
487
CHAPTER 16 INPUT CAPTURE
16.2.1
Input Capture Register (IPCP)
The input capture register (IPCP) retains the 16-bit free-run timer value when the device
detects the valid edge of a waveform input from the corresponding external pin.
■ Bit Configuration of Input Capture Register (IPCP)
IPCP high byte
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
CP15
R
CP14
R
CP13
R
CP12
R
CP11
R
CP10
R
CP09
R
CP08
R
XXXXXXXXB
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
CP07
R
CP06
R
CP05
R
CP04
R
CP03
R
CP02
R
CP01
R
CP00
R
XXXXXXXXB
IPCP low byte
R:
X:
Read only
Undefined
The input capture register retains the 16-bit free-run timer value when the device detects the valid edge of a
waveform input from the corresponding external pin. The value of this register is undefined after a reset.
Access this register using 16-bit or 32-bit data. Writing to this register is not permitted.
488
CHAPTER 16 INPUT CAPTURE
16.2.2
Input Capture Control Register (ICS)
Input capture control register (ICS) is used to control interrupt and edge detection of
input capture.
■ Bit Configuration of Input Capture Control Register (ICS)
ICS
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ICP1
R/W
ICP0
R/W
ICE1
R/W
ICE0
R/W
EG11
R/W
EG10
R/W
EG01
R/W
EG00
R/W
00000000B
R/W: Readable/Writable
[bit7, bit6] ICP1, ICP0: Interrupt flag
These bits are input capture interrupt flags. When a valid edge from the external input pin is detected,
these bits are set to "1". If the interrupt enable bits (ICE1 and ICE0) are also set, the detection of a valid
edge causes an interrupt to be generated. Write "0" to these bits to clear them. Writing "1" is
meaningless. A read-modify-write instruction always reads "1" from these bits.
ICP0/ICP1
Interrupt flag
0
There is no valid edge detection [Initial value]
1
There is valid edge detection
[bit5, bit4] ICE1, ICE0: Interruption enable bits
These bits are the input capture interrupt enable bits. If they are set to "1" and the interrupt flags (ICP1,
and ICP0) are also set to "1", an input capture interrupt occurs.
ICE0/ICE1
Enable the interrupt
0
Interrupt disabled [Initial value]
1
Interruption enable
[bit3 to bit0] EG11, EG10, EG01, EG00: Edge selection bits
These bits are used to select a valid edge polarity for external input. They also enable an input capture
operation.
EGn1
EGn0
Edge detection polarity
0
0
There is no edge detection (stopped state) [Initial value]
0
1
Rising edge detection ↑
1
0
Falling edge detection ↓
1
1
Both-edge detection ↑ &↓
The number n in EGn1/EGn0 corresponds to the input capture channel number.
489
CHAPTER 16 INPUT CAPTURE
16.3
Operation of Input Capture
When the 16-bit input capture unit detects the specified valid edge, it can read the value
of the 16-bit free-run timer into the capture register and generate an interrupt.
■ 16-bit Input Capture Operation
Figure 16.3-1 Example of Timing For Input Capture Reading
Counter Value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
IN0
IN1
IN2
Data Register 0
3FFFH
Undefine
Data Register 1
Data Register 2
BFFFH
Undefine
BFFFH
Undefine
7FFFH
Capture 0 Interrupt
Capture 1 Interrupt
Capture 2 Interrupt
It is re-generated the interruption by a valid edge.
Capture 0 : Rising edge
Capture 1 : Falling edge
Capture 2 : Both edges
Interrupt clear by software
■ Input Timing of 16-bit Input Capture
φ
Counter Value
Input Capture Input
N
N+1
Valid edge
Capture Signal
Capture Register value
Interrupt
490
N+1
CHAPTER 17
OUTPUT COMPARE
This chapter explains functions and operation of the
output compare.
17.1 Overview of the Output Compare
17.2 Registers of the Output Compare
17.3 Output Compare Operation
491
CHAPTER 17 OUTPUT COMPARE
17.1
Overview of the Output Compare
Output compare module is configured with a bit compare register, a compare output
latch, and a control register.
■ Features of the Output Compare
• The compare registers operate independently. Each compare register has its own output pin and interrupt
flag.
• The compare registers can be used together to control an output pin. The output pin can invert by using
the compare registers.
• The initial value of each output pin can be specified.
• An interrupt is generated when a compare match occurs.
■ Block Diagram of the Output Compare
OTD1 OTD0
R-bus
Compare
Register
Compare
Circuit
Compare
Register
CMOD
Compare
Circuit
Compare
Output Latch
PORT0
Output
Compare
Output Latch
PORT1
Output
CST1 CST0
ICP1
16-bit Free-run Timer
ICP0
ICE1
ICE0
Interrupt Output
Interrupt Output
492
CHAPTER 17 OUTPUT COMPARE
17.2
Registers of the Output Compare
The output compare has a compare register and a control register.
■ Registers of the Output Compare
OCCP high byte
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
XXXXXXXXB
C15
C14
C13
C12
C11
C10
C09
C08
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
C07
R/W
C06
R/W
C05
R/W
C04
R/W
C03
R/W
C02
R/W
C01
R/W
C00
R/W
XXXXXXXXB
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
-
-
-
CMOD
-
-
OTD1
OTD0
11101100B
-
-
-
R/W
-
-
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ICP1
R/W
ICP0
R/W
ICE1
R/W
ICE0
R/W
-
-
CST1
R/W
CST0
R/W
00001100B
OCCP low byte
OCS high byte
OCS low byte
R/W: Readable/Writable
X:
Undefined
493
CHAPTER 17 OUTPUT COMPARE
17.2.1
Compare Register (OCCP)
This section explains the details of the compare register (OCCP).
■ Bit Configuration of the Compare Register (OCCP)
OCCP high byte
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
XXXXXXXXB
C15
C14
C13
C12
C11
C10
C09
C08
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
C07
R/W
C06
R/W
C05
R/W
C04
R/W
C03
R/W
C02
R/W
C01
R/W
C00
R/W
XXXXXXXXB
OCCP low byte
R/W: Readable/Writable
X:
Undefined
■ Functions of the Compare Registers (OCCP)
The compare registers are 16-bit compare registers that are compared with the 16-bit free-run timer. The
initial value of this register is undefined, so set the compare value and then enable the activation.
Access the compare registers using 16-bit or 32-bit data. When the register value and the 16-bit free-run
timer value match, a compare signal is generated and the output compare interrupt flag is set.
When the corresponding bit of the port function register (PFR) is set and output is enabled, the output level
corresponding to the compare register is reversed.
494
CHAPTER 17 OUTPUT COMPARE
17.2.2
Control Register (OCS)
This section describes the control registers (OCS) in detail.
■ Bit Configuration of the Control Register
OCS high byte
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
11101100B
-
-
-
CMOD
-
-
OTD1
OTD0
-
-
-
R/W
-
-
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ICP1
R/W
ICP0
R/W
ICE1
R/W
ICE0
R/W
-
-
CST1
R/W
CST0
R/W
00001100B
OCS low byte
R/W: Readable/Writable
[bit15 to bit13] Reserved: Reserved bits
Reserved bits. In a read operation, "111B" is always read from these bits.
[bit12] CMOD: Mode bit
Switches the mode for reversing the pin output level for a compare match if output pin is enabled.
• If CMOD=0 (initial value), the output level of the pin corresponding to the compare register is
reversed.
-OC0: Reverses the level at a match with the compare register 0.
-OC1: Reverses the level at a match with the compare register 1.
• If CMOD=1
-OC0: Reverses the level at a match with the compare register 0.
-OC1: When the compare registers 0 and 1 match, the level is reversed.
[bit11, bit10] Reserved: Reserved bits
Reserved bits. In a read operation, "11B" is always read from these bits.
[bit9, bit8] OTD1, OTD0: Compare pin output level change bits
Use these bits to change the pin output level when output pin of output compare register is enabled.
Specify to these bits after stopping the compare operation. In a read operation, the output compare pin
output value is read from these bits.
OTD1, OTD0
Compare pin output level
0
Sets the compare pin output to "0". [Initial value]
1
Sets the compare pin output to "1".
495
CHAPTER 17 OUTPUT COMPARE
[bit7, bit6] ICP1, ICP0: Interrupt flag bits
These bits are interrupt flags for an output compare operation. They are set to "1" if the compare registers
and the 16-bit free-run timer value match. When the interrupt request bits (ICE1, ICE0) are enabled and
these bits are set to "1", an output compare interrupt occurs. Write "0" to these bits to clear them. Writing
"1" is meaningless. A read modify write instruction always reads "1" from these bits.
ICP1, ICP0
Interrupt flag
0
No output compare match [Initial value]
1
Output compare match
If an external clock is specified for the free-run timer, a compare match or interrupt occurs at the next
clock. For a compare match to be outputted and an interrupt to occur, at least one clock must be inputted
to the external clock of the free-run timer after the compare match.
[bit5, bit4] ICE1, ICE0: Interruption enable bits
These bits enable an output compare interrupt. When they are set to "1" and the interrupt flags (ICP0 and
ICP1) are set to "1", an output compare interrupt occurs.
ICE1, ICE0
Interruption permission
0
Output compare interrupt disabled [Initial value]
1
Output compare interrupt enabled
[bit3, bit2] Reserved: Reserved bits
Reserved bits. In a read operation, "11B" is always read from these bits.
[bit1, bit0] CST1, CST0: Match operation enable bits
These bits enable a match operation with the 16-bit free-run timer. Before enabling the compare
operation, be sure to set the compare register value and the output control register value.
CST1, CST0
Enabling match operations
0
Compare operation disabled [Initial value]
1
Compare operation enabled
The output compare is synchronized to the 16 - bit free - run timer. Therefore, if the 16 - bit free - run
timer stops, compare operation also stops.
496
CHAPTER 17 OUTPUT COMPARE
17.3
Output Compare Operation
The 16-bit output compare operation compares the specified compare register value
and the 16-bit free-run timer value. If a match occurs, the interrupt flag is set and the
output level is reversed.
■ Operation of 16 - Bit Output Compare
• The compare operation can be executed for each channel independently (at CMOD=0).
Figure 17.3-1 Example of the Output Waveform When Using Compare Register 0 and 1
(The Initial Value of the Output is "0")
Counter Value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare Register 0
BFFFH
Compare Register 1
7FFFH
OP0 Output
OP1 Output
Compare 0 Interrupt
Compare 1 Interrupt
497
CHAPTER 17 OUTPUT COMPARE
• The output level can be changed if two compare register pairs are used (at CMOD=1).
Figure 17.3-2 Example of the Output Waveform When Using Compare Register 0 and 1
(The Initial Value of the Output is "0")
Counter Value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare Register 0
BFFFH
Compare Register 1
7FFFH
OP0 Output
OP1 Output
Compare 0 Interrupt
Compare 1 Interrupt
498
CHAPTER 17 OUTPUT COMPARE
■ Operation Timing of 16-bit Output Compare
The output level can be changed if two compare register pairs are used (at CMOD=1).
When the values of the free-run timer and the specified compare register match, the output compare
generates a compare match signal to reverse the output and generate an interrupt. Reversal of output due to
a compare match occurs in synchronization with the count timing of the counter.
● Compare register write timing
The compare register does not compare the counter value when it is rewritten.
N
Counter Value
N+1
N+2
N+3
Match signal dose not occur.
N+1
N
Compare Clear Register 0
Compare Register 0 Write
L
Compare Clear Register 1
N+3
Compare Register 1 Write
Compare 0 stop
Compare 1 stop
● Compare match, interrupt timing
φ
Counter Clock
Counter Value
Compare register
N
N+1
N+3
N+2
N
Compare Match
Pin Output
Interrupt
● Pin output timing
Counter Value
Compare Register
N
N+1
N+1
N+1
N
Compare Match
Pin Output
499
CHAPTER 17 OUTPUT COMPARE
500
CHAPTER 18
PPG TIMER
This chapter describes the PPG timer.
18.1 Overview
18.2 Block Diagram
18.3 PPG Register
18.4 Operation Explanation
501
CHAPTER 18 PPG TIMER
18.1
Overview
PPG, the 8-bit reload timer module, performs the PPG output by the pulse output
control according to timer operation.
On a hardware level, the PPG timer consists of an 8-bit down counter, an 8-bit reload
register, a control register, an external pulse output, and an interrupt output.
■ Functions of the PPG
● 8-bit PPG output independent operation mode
Independent PPG output operation is enabled.
● 16-bit PPG output operation mode
16-bit PPG output operation is enabled.
● 8+8-bit PPG output operation mode
Channel (2n+1) output is used as channel (2n) clock input, enabling the 8-bit PPG output operation of an
arbitrary cycle.
● 16+16-bit PPG output operation mode
The 16-bit prescaler output of channel (4n+3) + channel (4n+2) is used as the 16-bit PPG clock input of
channel (4n+1) + channel (4n).
● PPG output operation
Outputs a pulse waveform with arbitrary period and duty ratio.
Can also be used in conjunction with an external circuit to form a D/A converter.
● Output inverted function
The PPG output value can be inverted.
Note:
The D/A converter has been provided only for MB91V280.
502
CHAPTER 18 PPG TIMER
18.2
Block Diagram
This section shows the block diagram of PPG.
■ Block Diagram of the 8-bit PPG (ch.0 and ch.2)
Figure 18.2-1 Block Diagram of the 8-bit PPG (ch.0 and ch.2)
Borrow of ch. (n+1)
64-division of machine clock
To port
16-division of machine clock
4-division of machine clock
Machine clock
PPG
Output latch
Inversion
Clear
PEN(n+1)
Count clock select
S
R
PCNT (Down counter)
Q
IRQn
Reload
"H"/"L"select
"H"/"L"select
PIEn
PRLLn
PRLHn
PUFn
Data bus in "L" side
Data bus in "H" side
PPGCn TRG
n = 0, 2
Operation mode
(control)
503
CHAPTER 18 PPG TIMER
■ Block Diagram of the 8-bit PPG (ch.1)
Figure 18.2-2 Block Diagram of the 8-bit PPG (ch.1)
Borrow of ch. (n+1)
64-division of machine clock
To port
16-division of machine clock
4-division of machine clock
Machine clock
PPG
Output latch
Inversion
Clear
PENn
S
Count clock select
R
Q
IRQn
PCNT (Down counter)
Reload
Borrow of
ch.(n-1)
"H"/"L"select
"H"/"L"select
PUFn
PRLLn
PIEn
PRLHn
Data bus in "L" side
Data bus in "H" side
n=1
PPGCn TRG
Operation mode
(control)
504
CHAPTER 18 PPG TIMER
■ Block Diagram of the 8-bit PPG (ch.3)
Figure 18.2-3 Block Diagram of the 8-bit PPG (ch.3)
To port
64-division of machine clock
16-division of machine clock
4-division of machine clock
Machine clock
PPG
Output latch
Inversion
Clear
PENn
S
Count clock select
R
Q
PCNT (Down counter)
Reload
Borrow of
ch.(n-1)
"H"/"L"select
"H"/"L" selector
PUFn
PRLLn
PIEn
PRLHn
Data bus in "L" side
Data bus in "H" side
n=3
PPGCn TRG
Operation mode
(control)
505
CHAPTER 18 PPG TIMER
18.3
PPG Register
This section explains the details of the PPG register.
■ List of PPG Registers
PPGC
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PIE
R/W
PUF
R/W
INTM
R/W
PCS1
R/W
PCS0
R/W
MD1
R/W
MD0
R/W
-
0000000XB
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
D15
D14
D13
D12
D11
D10
D9
D8
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D7
R/W
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
R/W
XXXXXXXXB
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
PEN15
R/W
PEN14
R/W
PEN13
R/W
PEN12
R/W
PEN11
R/W
PEN10
R/W
PEN09
R/W
PEN08
R/W
00000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PEN07
R/W
PEN06
R/W
PEN05
R/W
PEN04
R/W
PEN03
R/W
PEN02
R/W
PEN01
R/W
PEN00
R/W
00000000B
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
REV15
R/W
REV14
R/W
REV13
R/W
REV12
R/W
REV11
R/W
REV10
R/W
REV09
R/W
REV08
R/W
00000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
REV07
R/W
REV06
R/W
REV05
R/W
REV04
R/W
REV03
R/W
REV02
R/W
REV01
R/W
REV00
R/W
00000000B
PRLH
PRLL
TRG1
TRG0
REVC1
REVC0
R/W: Readable/Writable
X:
Undefined
506
CHAPTER 18 PPG TIMER
18.3.1
PPG Operation Mode Control Register (PPGC)
PPG operation mode control register (PPGC) is the register that controls PPG interrupt,
operation clock, and operation mode.
■ PPG Operation Mode Control Register (PPGC)
PPGC
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PIE
R/W
PUF
R/W
INTM
R/W
PCS1
R/W
PCS0
R/W
MD1
R/W
MD0
R/W
-
0000000XB
R/W: Readable/Writable
X:
Undefined
[bit7] PIE: PPG interrupt enable bit
This bit controls a PPG interrupt enable as described below.
PIE
PPG interrupt enable
0
Interrupt disabled [initial value]
1
Interruption enabled
- If this bit is set to "1", an interrupt request is generated when the PUF is set to "1".
- If this bit is set to "0", no interrupt request is generated.
- Initialized to "0" by reset.
- The read and write are possible.
[bit6] PUF: PPG counter underflow bit
This bit controls PPG counter underflow bits as described below.
PUF
PPG counter underflow
0
PPG counter underflow has not been detected. [initial value]
1
PPG counter underflow has been detected.
- In 8-bit PPG 2 channels mode and 8-bit prescaler + 8-bit PPG mode, this bit is set to "1" if an
underflow occurs because the count value for ch.0 changes from 00H to FFH.
- In 16-bit PPG 1 channel mode, this bit is set to "1" if an underflow occurs because the count value for
ch.1/ch.0 changes from 0000H to FFFFH.
- Writing "0" clears the bit to "0".
- Writing "1" to this bit is meaningless.
- When this bit is read to a read modify write instruction, "1" is always read.
- Initialized to "0" by reset.
- The read and write are possible.
507
CHAPTER 18 PPG TIMER
[bit5] INTM: Interrupt mode bit
This bit can limit the PUF bit detection at an underflow only from PRLH.
INTM
Interrupt mode
0
At underflow, PUF is set to "1".
[initial value]
1
PUF is set to "1" at an underflow only from PRLH.
- Initialized to "0" by reset.
- The read and write are possible.
- If this bit is set to "1", an interrupt is enabled at one cycle output of PPG waveform.
- Do not rewrite this bit when the interrupt is allowed.
[bit4, bit3] PCS1/PCS0: Count clock select bit
These bits are used to select the down counter operating clock as shown below.
PCS1
PCS0
Count clock
0
0
Machine clock [initial value]
0
1
Machine clock/4
1
0
Machine clock/16
1
1
Machine clock/64
- Initialized to "00B" by reset.
- The read and write are possible.
[bit2, bit1] MD1/MD0: Operation mode select bit
MD1
MD0
Operating mode
0
0
8-bit PPG 2 channels [initial value]
0
1
8-bit prescaler + 8-bit PPG mode
1
0
16-bit PPG mode
1
1
16-bit prescaler + 16-bit PPG mode
- Initialized to "00B" by reset.
- The read and write are possible.
- These bits exist only in even-numbered channels.
[bit0] Reserved: Reserved bit
Reserved bit. Write "0". (Writing "1" is disabled.)
The read value is undefined.
508
CHAPTER 18 PPG TIMER
18.3.2
Reload Registers (PRLL/PRLH)
Reload registers (PRLL/PRLH) are the registers to hold the reload value of PPG.
■ Reload Registers (PRLL/PRLH)
PRLH
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
D15
R/W
D14
R/W
D13
R/W
D12
R/W
D11
R/W
D10
R/W
D9
R/W
D8
R/W
XXXXXXXXB
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PRLL
R/W: Readable/Writable
X:
Undefined
These registers hold reload values for a down counter PCNT. Each register has own role as shown below.
Register name
Function
PRLL
Reload value in "L" side is held.
PRLH
Reload value in "H" side is held.
Any register can read and write.
Note:
To use in the 8-bit prescaler + 8-bit PPG mode and 16-bit prescaler + 16-bit PPG mode, if the
different values are set to the PRLL and PRLH in prescaler side, the PPG waveform may differ from
cycle to cycle. It is recommended that the PRLL and PRLH in prescaler side be set to the same
value.
509
CHAPTER 18 PPG TIMER
18.3.3
PPG Starting Register (TRG)
PPG starting register (TRG) is a register to enable the PPG operation.
■ PPG Starting Register (TRG)
TRG1
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
PEN15
R/W
PEN14
R/W
PEN13
R/W
PEN12
R/W
PEN11
R/W
PEN10
R/W
PEN09
R/W
PEN08
R/W
00000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PEN07
PEN06
PEN05
PEN04
PEN03
PEN02
PEN01
PEN00
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TRG0
R/W: Readable/Writable
[bit15 to bit0] PEN15 to PEN00: PPG operation enable bit
These bits are used to select the PPG operation start and the operation mode as shown below.
PEN
Operating state
0
Operation stop ("L" level output retained) [initial value]
1
PPG operating enabled
- Initialized to "0" by reset.
- The read and write are possible.
- To use in the 16-bit PPG mode, it must be the same setting for the corresponding PEN bit of both
even-numbered and odd-numbered. Be sure to enable/disable the even-numbered and odd-numbered
simultaneously at register setting.
510
CHAPTER 18 PPG TIMER
18.3.4
Output Inverted Register (REVC)
Output inverted register (REVC) is a register to invert the PPG output value.
■ Output Inverted Register (REVC)
REVC1
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
REV15
R/W
REV14
R/W
REV13
R/W
REV12
R/W
REV11
R/W
REV10
R/W
REV09
R/W
REV08
R/W
00000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
REV07
REV06
REV05
REV04
REV03
REV02
REV01
REV00
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
REVC0
R/W: Readable/Writable
[bit15 to bit0] REV15 to REV00: Output inverted bit
The PPG output values including the initial values are inverted.
REV
Output level
0
Normal [Initial value]
1
Inversion
- Initialized to "0" by reset.
- The read and write are possible.
- Since these bits invert the PPG outputs, they also invert the initial levels.
- The relationship between "L" and "H" of the reload register is also inverted.
- To use in the 16-bit PPG mode, the same waveform is generated from either PPG (m) or PPG (m+1)
pin, so the inverted output is obtained if REVxx of used pin is set. In addition, the same value can be
set for both outputs.
511
CHAPTER 18 PPG TIMER
18.4
Operation Explanation
The PPG contains 8-bit length PPG units. By combining the operation, four operation
modes can be performed: independent mode, 8-bit prescaler + 8-bit PPG mode, 16-bit
PPG1 channel mode, and 16-bit prescaler + 16-bit PPG mode.
■ PPG Operation
Each of 8-bit length PPG units has two 8-bit-length reload registers for the L and H sides (PRLL, PRLH).
The value written to this register is reloaded into "L" and "H" sides of 8-bit down counter (PCNT)
alternately, counted down based on the count clock, and inverted a pin output (PPG) at reloading when a
counter borrow occurs. This operation makes the pin output (PPG) to pulse output with "L" width and "H"
width corresponding to the value of reload register.
Operation is started/restarted by the written register bit.
The relationship between the reload operation and the pulse output is shown below.
Reload operation
Pin output change
PRLH → PCNT
PPGn [0 → 1]
PRLL → PCNT
PPGn [1 → 0]
n: PPG channel number
Also, when bit7: PIE of the PPGC register is "1", the interrupt request is outputted due to a borrow if the
counter changes from 00H to FFH (in 16-bit PPG mode, borrow from 0000H to FFFFH).
■ Operating Mode
This block has four operation modes: independent mode, 8-bit prescaler +8-bit PPG mode, 16-bit PPG1
channel mode, and 16-bit prescaler + 16-bit PPG mode.
• In the independent mode, a channel can operate as 8-bit PPG independently. PPG output of ch.n is
connected to PPGn pin.
• The 8-bit prescaler +8-bit PPG mode is an operation mode that can output the 8-bit PPG waveform of
any cycle when 1 channel is operated as the 8-bit prescaler and counting is performed with its borrow
output. For example, prescaler output of ch.1 is connected to PPG1 pin, and PPG output of ch.0 is
connected to PPG0 pin.
• The 16-bit PPG1 channel mode is an operation mode that operates as 16-bit PPG when 2 channels are
combined. For example, 16-bit PPG output is connected to both PPG0 pin and PPG1 pin when ch.0 and
ch.1 are combined.
512
CHAPTER 18 PPG TIMER
■ PPG Output Operation
PPG starts counting when the bits of each channel on the TRG register (PPG activation register) are set to
"1". After operation starts, the count operation is stopped when each channel bit of TRG register is set to
"0". After having stopped, the pulse output holds "L" level.
Do not set the PPG channel as the operating state, with the prescaler channel as the stopped state, in the 8bit prescaler + 8-bit PPG mode and the 16-bit prescaler + 16-bit PPG mode.
In 16-bit PPG mode, control simultaneous start/stop for PEN of TRG register for each channel,
respectively.
PPG output operation is explained below.
In PPG operation, the pulse wave with any frequency/duty ratio (the ratio between "H" level period and "L"
level period in pulse wave) is outputted continuously. After the PPG starts to output the pulse wave, it does
not stop until the operation stop is set.
PENn
Operation is
started by
PENn
(from L side)
Output pin
PPG
T x (L+1)
T x (H+1)
Start
n=0 to 3
L: The value of PRLL
H: The value of PRLH
T: Machine clock
(φ,φ/4,φ/16)
or
Input from timer base counter
(depending on clock select of PPGC)
PPG output operation output waveform
■ Relation Between Reload Value and Pulse Width
The pulse width to be outputted is the value that multiplies the cycle of the count clock by the value in the
reload register plus 1. Note that the pulse width will be one cycle of the count clock when the reload
register value is set to "00H" at operating the 8-bit PPG and when the reload register value is set to "0000H"
at operating the 16-bit PPG. Also, note that the pulse width will be 256 cycles of the count clock when the
reload register value is set to "FFH" at operating the 8-bit PPG and 65536 cycles of the count clock when
the value is set to "FFFFH "at operating the 16-bit PPG.
The equations for calculating the pulse width are shown below:
L : PRLL value
Pl = T × (L+1)
H : PRLH value
Ph = T × (H+1)
T : Input clock cycle
Ph : "H" pulse width
Pl : "L" pulse width
513
CHAPTER 18 PPG TIMER
■ Count Clock Selection
The count clock for the operation of this block uses the peripheral clock and can select from 4 types of
count clock input.
The count clock operates as shown below.
PPGC register
Count clock operation
PCS1
PCS0
0
0
1 count per peripheral clock
0
1
1 count per 4 cycles of peripheral clock
1
0
1 count per 16 cycles of peripheral clock
1
1
1 count per 64 cycles of peripheral clock
However, the value of bit4, bit3: PCS1, PCS0 in the PPGC register of PPG other than first PPG is invalid in
the 8-bit prescaler + 8-bit PPG mode and 16-bit PPG mode, 16-bit prescaler + 16-bit PPG mode.
Note that the first count cycle may become out of synchronization if the PPG side is started, in the 8-bit
prescaler + 8-bit PPG mode and the 16-bit prescaler + 16-bit PPG mode, and when the prescaler side is in
the operating state and the PPG side is in stop state.
■ Pulse Pin Output Control
The pulse output generated by operating this module can be outputted from external pins PPGn.
In 16-bit PPG mode, PPG (m) and PPG (m+1) is outputted the same waveform, so the same output can be
obtained even though either of external pin output is enabled.
In the 8-bit prescaler + 8-bit PPG mode and the 16-bit prescaler + 16-bit PPG mode, the 8-bit prescaler
toggle waveform is outputted on the prescaler side, and the 8-bit PPG waveform is outputted on the PPG
side. The following shows an example of the output waveform in this mode.
Ph
Pl
PPG1
PPG0
Ph
514
Pl0
CHAPTER 18 PPG TIMER
■ Interrupt
The interrupt of this module becomes active when a reload value is counted out and a borrow occurs.
However, when the INTM bit is set to "1", it becomes active only when an underflow (borrow) from PRLH
occurs. That is, the interrupt occurs when "H" width pulse ends.
Each interrupt request is executed due to a borrow of each counter in the 8-bit PPG mode and 8-bit
prescaler + 8-bit PPG mode, but PUF (m) and PUF (m+1) are set simultaneously due to a borrow of 16-bit
counter in the 16-bit PPG mode and 16-bit prescaler + 16-bit PPG mode. For this reason, it is
recommended that either PIE (m) or PIE (m + 1) is enabled in order to unify the interrupt sources. It is also
recommended that PUF(m) and PUF(m+1) are performed simultaneously in clearing interrupt factor.
■ Initial Value of Each Hardware
Each hardware of this block is initialized by a reset as shown below.
<Register>
PPGC
→ 0000000xB
<Pulse output>
PPG
→ "L"
<Interrupt request>
IRQ
→ "L"
Any hardware other than those above is not initialized.
■ Combination of PPG
ch.0: PPGC
ch.2: PPGC
ch.0
ch.1
ch.2
ch.3
0
8-bit PPG
8-bit PPG
8-bit PPG
8-bit PPG
0
1
8-bit PPG
8-bit PPG
8-bit PPG
8-bit prescaler
0
1
0
8-bit PPG
8-bit PPG
0
0
1
1
0
1
0
0
8-bit PPG
8-bit prescaler
8-bit PPG
8-bit PPG
0
1
0
1
8-bit PPG
8-bit prescaler
8-bit PPG
8-bit prescaler
0
1
1
0
8-bit PPG
8-bit prescaler
0
1
1
1
1
0
0
0
16-bit PPG
8-bit PPG
8-bit PPG
1
0
0
1
16-bit PPG
8-bit PPG
8-bit prescaler
1
0
1
0
16-bit PPG
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
MD1
MD0
MD1
MD0
0
0
0
0
0
0
16-bit PPG
Setting disabled
16-bit PPG
Setting disabled
16-bit PPG
Setting disabled
16-bit PPG
16-bit prescaler
515
CHAPTER 18 PPG TIMER
■ Duty Modification
Note that the duty is changed from next cycle to be changed when the duty setting is changed with PPG
output operated.
1. Overview of the PPG timer operation
The 8/16-bit PPG timer reloads the value set in the "L" width setting register (PRLL) and "H" width setting
register (PRLH) to the down counter alternately per underflow of the down counter.
PPGn
PPG output latch
8-bit or 16-bit down counter
Underflow
H/L selector
PUF
Interrupt
PIE
PRLLn
PRLHn
Bus
Timer function of PPG timer has following functions.
- When PWM timer mode : Cycle = "L" width setting register + "H" width setting register
- When reload timer mode : Setting time = "L" width setting register = "H" width setting register
2. Notes on executing PWM timer mode
If the PWM is controlled using the PPG timer, the interrupt can be generated each underflow of the
counter. Thus, the value of the "L" width/"H" width setting registers corresponding to object of update per
this interrupt is updated, enabling the duty control. However, if the time set in "L" width/"H" width is short,
the time from an interrupt to next interrupt is short, next interrupt occurs while the register is updated
within the interrupt processing, and the phenomenon which the interrupt is ignored occurs at the clear
timing of interrupt flag. Thus, it is required to set the time which this interrupt is not ignored or to perform
the software processing in consideration of the interrupt even if the interrupt is ignored.
The following diagram shows the update timing and output timing.
Interrupt ignore generated
”H1”
”L1”
”L2”
”H2”
”L3”
”H3”
”L4” ”H4”
”L5”
PPG
L2
renewal
Startup
H2
renewal
L3/H3 renewal
Interrupt
Interrupt
L4
Interrupt
H4 renewal
L5
Interrupt
H5/L6
renewal
Interrupt
Note : The interrupt is ignored if the L width/H width setting time is short.
Software consideration is necessary as the update timing.
Idea 1) Set a time which the interrupt must not be ignored.
Idea 2) Program to deal even if the interrupt omission is generated.
516
CHAPTER 18 PPG TIMER
3. Interrupt processing time
The following shows the processing time required for the interrupt processing indicated in step 2.
Moreover, since the time is described in the number of required cycle at the minimum time, please examine
the setting time that can afford for the following time.
(1) Time until starting the interrupt processing
- About 6 cycles
(2) Processing at entry of interrupt function
STM(R0 to R7)
STM(R8 to R15)
ST MDH,@-R15
ST MDL,@-R15
ST RP,@-R15
ENTER
; Maximum 9 cycles
; Maximum 9 cycles
; 1 cycle
; 1 cycle
; 1 cycle
; 2 cycles
(3) Setting to flag clear and reload register
LDI:20 #PPGCn,R0
BANDH #B,@R0
LDI:20 #0x0XXXX,R0
LDI:20 #PRLn,R12
STH R0,@R12
; 2 cycles
; 3 cycles
; 2 cycles
; 2 cycles
; 1 cycle
Program in the interrupt processing.
Cycle calculation of the actual program
contents is required.
Total: 65 cycles + α
(Instruction at interrupt execution)
(4) Processing at interrupt function exit
LEAVE
LD @R15+,RP
LD @R15+,MDL
LD @R15+,MDH
LDM1(R8 to R15)
LDM0(R0 to R7)
RETI
; 1 cycle
; 1 cycle
; 1 cycle
; 1 cycle
; 9 cycles
; 9 cycles
; 9 cycles
The processing by multiple interrupts is not considered for this time. Thus, when multiple interrupts are
used, higher interrupt processing time than the PPG timer interrupt must be added.
The example of the duty ratio is shown when taking this time into consideration.
Condition) Cycle: 5000 cycles, no multiple interrupts, minimum setting time = 250 cycles
PPG
4750 cycles
250
250
4750 cycles
Duty ratio: =4750:250 to 250:4750=5% to 95%
If the cycle is long, a large number can be set to the duty ratio, but if it is short, small number is set to the
duty ratio as well.
517
CHAPTER 18 PPG TIMER
4. Processing method of considering interruption disregard
Main
PPG interrupt
Flag=1
Flag judgement
Flag=0
Update "L" width
setting register
Update "H" width
setting register
Clear interrupt flag
Clear interrupt flag
PPGx=0
PPGx=1
Pin judgement
PPGx=1
Flag inversion
process
"H" width setting register
renewal
RETI
1) PPG timer interrupt occurs.
2) Check the "L" width/"H" width decision flag.
3) Update the "L" width setting register if flag=0/
update the "H" width setting register if flag=1 .
4) Clear interrupt flag.
5) Decide the PPG output pin state after the interrupt
flag is cleared.
6) If the PPG pin state is positive, execute the flag inversion processing,
and if it is negative, update each setting register.
7) Return main by RETI.
518
Pin judgement
PPGx=0
"L" width setting register
renewal
Program for
interrupt ignore
CHAPTER 19
UP/DOWN COUNTER
This chapter describes the function and operation of
8/16-bit up/down counter.
19.1 Overview of Up/Down Counter
19.2 Register of Up/Down Counter
19.3 Operation of Up/Down Counters
519
CHAPTER 19 UP/DOWN COUNTER
19.1
Overview of Up/Down Counter
The 8/16-bit up/down counter is the up/down counter/timer which consists of three
event input pins, 16-bit up/down counters, 16-bit reload/compare registers, and their
control circuits.
The operating mode can switch two channels of 8-bit counter or one channel of 16-bit
by setting.
■ Features of Up/Down Counter
• With the 16-bit count register, counting can be performed in a range between 0D to 65535D.
• The following four count modes can be selected for the count clock:
- Timer mode
- Up/down counter mode
- Phase difference count mode (multiply-by-2)
- Phase difference count mode (multiply-by-4)
• In timer mode, the count clock can be selected from two internal clocks and input from an internal
circuit.
Count clocks available for selection (for operation at 32MHz)
- 62.5ns (16MHz: divide-by-2)
- 250ns (4MHz: divide-by-8)
• The detection edge of the external pin input signal can be selected in up and in down counting mode.
- Detection falling edge
- Detection rising edge
- Detection both rising and falling edges
- Edge detection disabled
• The phase difference counting mode is suitable for counting for an encoder, such as for a motor. Using
one of A phase output, B phase output, and Z phase output for the encoder as input allows to count
rotation angle and number of rotations easily and with high precision.
• Two different functions can be selected for the ZIN pin (this applies for all modes).
- Counter clear function
- Gate function
• The compare function and reload function are available. These functions can be used separately or
combined. By combining these functions, counting up or down can be performed with an arbitrary
width.
- Compare function (compare interrupt request output)
- Compare function (compare interrupt request output and counter clearing)
- Reload function (underflow interrupt request output and reloading)
- Compare and reload function (compare interrupt request output, counter clearing, underflow interrupt
request output, and reloading)
- Compare and reload disabled
520
CHAPTER 19 UP/DOWN COUNTER
• With the count direction flag, the counting direction immediately before the current count can be
identified.
• The generation of interrupts when a compare match occurs, at reload (underflow), at overflow, or when
the counting direction changes, can be controlled individually.
■ Block Diagram of Up/Down Counter
Figure 19.1-1 Block Diagram of Up/Down Counter
8/16-bit up/down counter/timer (ch0)
Data bus
CGE1 CGE0 CGSC
ZIN0
8-bit
RCR0
(reload/compare register 0)
CTUT
Reload
control
UCRE
RLDE
Edge level detection
To ch.1
M16E
Carry
Counter
clear
UDCC
CES1 CES0
8-bit
UDCR0
(up/down count register 0)
CMS1 CMS0
CMPF
UDFF
AIN0
Up/down
count clock
selection
Count
clock
CSTR
OVFF
UDIE
BIN0
UDF1
UDF0 CDCF
Prescaler
CITE
CLKS
CFIE
Interrupt output
521
CHAPTER 19 UP/DOWN COUNTER
8/16-bit up/down counter/timer (ch1)
Data bus
8-bit
RCR1
(reload/compare register 1)
CGE1 CGE0 CGSC
ZIN1
CTUT
Reload
control
UCRE
RLDE
Edge/level detection
Counter
clear
UDCC
CES1
8-bit
UDCR1
(up/down count register 1)
CES0
CMS1 CMS0
Carry
AIN1
Up/down
count clock
selection
CMPF
M16E
Count
clock
UDFF
CSTR
OVFF
UDIE
BIN1
UDF1
UDF0 CDCF
Prescaler
CITE
CLKS
CFIE
Interrupt output
522
CHAPTER 19 UP/DOWN COUNTER
19.2
Register of Up/Down Counter
The up/down counter has up/down count register (UDCR), reload compare register
(RCR), count status register (CSR), and counter control register (CCR).
This section explains these registers.
■ List of Registers of Up/Down Counter
UDCR1
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
D15
R
D14
R
D13
R
D12
R
D11
R
D10
R
D09
R
D08
R
00000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D07
R
D06
R
D05
R
D04
R
D03
R
D02
R
D01
R
D00
R
00000000B
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
D15
W
D14
W
D13
W
D12
W
D11
W
D10
W
D09
W
D08
W
00000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D07
W
D06
W
D05
W
D04
W
D03
W
D02
W
D01
W
D00
W
00000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
CSTR
R/W
CITE
R/W
UDIE
R/W
CMPF
R/W
OVFF
R/W
UDFF
R/W
UDF1
R
UDF0
R
00000000B
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
M16E
DCCF
CFIE
CLKS
CMS1
CMS0
CES1
CES0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
CTUT
R/W
UCRE
R/W
RLDE
R/W
UDCC
R/W
CGSC
R/W
CGE1
R
CGE0
R
UDCR0
RCR1
RCR0
CSR
CCRH
CCRL
R/W
Initial value
00000000B
R/W: Readable/Writable
R:
Read only
W: Write only
523
CHAPTER 19 UP/DOWN COUNTER
19.2.1
Up/Down Count Register (UDCR)
Up/down count register (UDCR) is 8-bit count register. Up/down counting is performed
by an input from the internal circuit, an internal prescaler, or an input of AIN pin and BIN
pin. Also, in 16-bit count mode, this register operates as 16-bit count register.
■ Up/Down Count Register (UDCR)
UDCR1
Address
000172H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
D15
D14
D13
D12
D11
D10
D09
D08
00000000B
R
R
R
R
R
R
R
R
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D07
D06
D05
D04
D03
D02
D01
D00
00000000B
R
R
R
R
R
R
R
R
UDCR0
Address
000173H
R:
Read only
Values cannot be written to this register directly. To write a value to this register, the RCR must be used.
First write the value to write to this register to the RCR, then set the CTUT bit of the CCRL register to "1".
The value will then be transferred from the RCR to this register (in a reload-operation by software).
In 16-bit mode, perform a 16-bit read operation for this register once.
524
CHAPTER 19 UP/DOWN COUNTER
19.2.2
Reload Compare Register (RCR)
Reload compare register (RCR) is 8-bit reload/compare register. The reload value and
the compare value is set by this register. The reload value and the compare value is the
same and up/down count is enabled in 00H to the value of this register (16-bit operation
mode: 0000H to the value of this register) by activating the function of reload and
compare.
■ Reload Compare Register (RCR)
RCR1
Address
000170H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
D15
D14
D13
D12
D11
D10
D09
D08
00000000B
W
W
W
W
W
W
W
W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D07
D06
D05
D04
D03
D02
D01
D00
00000000B
W
W
W
W
W
W
W
W
RCR0
Address
000171H
W:
Write only
This register is enabled to write only and disabled to read. By setting the CTUT bit of the CCR register to
"1" while counting is stopped, the value of this register can be transferred to the UDCR.
(reloaded by software)
In 16-bit mode (when M16E = 1), write a 16-bit value to this register once.
525
CHAPTER 19 UP/DOWN COUNTER
19.2.3
Counter Status Register (CSR)
Counter status register (CSR) can check the state of up/down counter and control the
interrupt.
■ Bit Configuration of Counter Status Register (CSR)
CSR
Address
CSR0: 000177H
CSR1: 00017BH
CSR2: 000187H
CSR3: 00018BH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
CSTR
R/W
CITE
R/W
UDIE
R/W
CMPF
R/W
OVFF
R/W
UDFF
R/W
UDF1
R
UDF0
R
00000000B
R/W: Readable/Writable
R:
Read only
[bit7] CSTR: Count start bit
This bit controls start and stop of UDCR counting operation.
CSTR
Count activation
0
Stops the counting operation [initial value].
1
Starts the counting operation.
[bit6] CITE: Compare interrupt enable bit
This bit controls whether to enable or disable interrupt output to the CPU when a compare detection flag
(CMPF) is set (during a compare operation).
CITE
Compare interrupt enable
0
Disables compare interrupt [initial value].
1
Enables compare interrupt.
[bit5] UDIE: Overflow/underflow interrupt enable bit
This bit controls whether to enable or disable interrupt output to the CPU when OVFF/UDFF is set (when
overflow or underflow occurs).
UDIE
526
Overflow/underflow interrupt enable
0
Disables overflow/underflow interrupt [initial value].
1
Enables overflow/underflow interrupt.
CHAPTER 19 UP/DOWN COUNTER
[bit4] CMPF: Compare detection flag
This flag indicates that the comparison result of the UDCR value and RCR value is that the values are
equal.
In write operations, the flag can only be set to "0", not to "1".
CMPF
Meaning of compare detection flag
0
Comparison result does not match [initial value].
1
Comparison result matches.
[bit3] OVFF: Overflow detection flag
This flag indicates the occurrence of an overflow.
In write operations, this flag can only be set to "0", not to "1".
OVFF
Meaning of overflow detection flag
0
No overflow [initial value]
1
Overflow
[bit2] UDFF: Underflow detection flag
This flag indicates the occurrence of an underflow.
In write operations, this flag can only be set to "0", not to "1".
UDFF
Meaning of underflow detection flag
0
No underflow [initial value]
1
Underflow
[bit1, bit0] UDF1, UDF0: Up/down flag
These bits indicate the type of a counting operation (up or down) immediately preceding the current
operation.
Only reading is allowed. No writing is allowed.
UDF1
UDF0
Up/down flag
0
0
No input [initial value]
0
1
Down count
1
0
Up count
1
1
Both up and down counting were performed simultaneously.
527
CHAPTER 19 UP/DOWN COUNTER
19.2.4
Counter Control Register (CCR)
Counter control register (CCR) is the register which controls the operation mode of up/
down counter. The function of bit15 (M16E) is different in odd channel and even
channel.
■ Bit Configuration of Counter Control Register (CCR)
CCRH
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
CSR0: 000174H
CSR0: 000178H
M16E
R/W
DCCF
R/W
CFIE
R/W
CLKS
R/W
CMS1
R/W
CMS0
R/W
CES1
R/W
CES0
R/W
00000000B
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CSR0: 000175H
CSR0: 000179H
Reserved
CTUT
R/W
UCRE
R/W
RLDE
R/W
UDCC
R/W
CGSC
R/W
CGE1
R
CGE0
R
CCRL
R/W
R/W: Readable/Writable
R:
Read only
Initial value
00000000B
[bit15] M16E: 16-bit mode permission setting bit
8 bits × 2 channels/16 bits × 1 channel operation mode selection (switching) bit
M16E
16-bit mode enable setting
0
8 bits × 2 channels operation mode [initial value]
1
16 bits × 1 channel operation mode
Note:
M16E bit only exists in even channel. Be sure to set "0" in odd channel.
[bit14] CDCF: Count direction change flag
This flag sets when the count direction is changed. When the count direction is changed up to down or
down to up during counting, "1" is set to this bit.
0: Writing "0" clears the setting.
1: Writing "1" is ignored. The value of this bit is not changed.
CDCF
Direction change detection
0
Direction has not been changed [initial value].
1
Direction has been changed once or more.
The count direction is set to down when the counter is reset. Therefore, CDCF is set to "1" when up
counting is performed immediately after a reset.
528
CHAPTER 19 UP/DOWN COUNTER
[bit13] CFIE: Count direction change interrupt enable bit
This bit controls the interrupt output for the CPU when CDCF is set. An interrupt occurs if the count
direction is changed at least once during counting.
CFIE
Direction change interrupt enable
0
Disables direction change interrupt [initial value].
1
Enables direction change interrupt.
[bit12] CLKS: Internal prescaler selection bit
When timer mode is selected, this bit selects the frequency of the internal prescaler.
This bit is effective only in timer mode and only for down counting.
CLKS
Internal prescaler
0
Two machine cycles [initial value]
1
Eight machine cycles
[bit11, bit10] CMS1, CMS0: Counting mode selection bit
This bit selects counting mode.
CMS1
CMS0
Counting mode
0
0
Timer mode (down count) [initial value]
0
1
Up or down counting mode
1
0
Phase difference counting mode, 2 multiplication
1
1
Phase difference counting mode, 4 multiplication
[bit9, bit8] CES1, CES0: Count clock edge selection bit
In up/down counting mode, these bits select the input of internal circuit or the detection edge of external
pins AIN and BIN.
This setting is invalid in modes other than up or down counting mode.
CES1
CES0
Selection edge
0
0
Disables edge detection [initial value].
0
1
Detects falling edge.
1
0
Detects rising edge.
1
1
Detects rising and falling edges.
[bit7] Reserved: Reserved bit
This bit is reserved. Be sure to set this bit to "0".
529
CHAPTER 19 UP/DOWN COUNTER
[bit6] CTUT: Counter write bit
This bit transfers data from RCR to UDCR.
When this bit is set to "1", data is transferred from RCR to UDCR.
Writing "0" to this bit has no effect. The read value is always "0".
Do not set this bit to "1" during counting (when the CSTR bit of the CSR is "1").
[bit5] UCRE: UDCR clear enable bit
This bit controls the compare operation that clears UDCR.
UDCR clear functions other than clearing due to comparing (such as due to the ZIN pin), are not
affected.
UCRE
Counter clear by compare
0
Disables counter clear [initial value].
1
Enables counter clear.
[bit4] RLDE: Reload enable bit
This bit controls the start of the reload function. When the reload function is started, if UDCR leads the
underflow, this bit transfers the value of RCR to UDCR.
RLDE
Reload function
0
Disables the reload function [initial value].
1
Enables the reload function.
[bit3] UDCC: UDCR clear bit
This bit clears the UDCR. When this bit is set to "0", the UDCR is cleared to "0000H".
Writing "1" to this bit has no effect. The read value is always "1".
[bit2] CGSC: Counter clear/gate selection bit
This bit selects the function of the external pin ZIN.
CGSC
ZIN pin function
0
Counter clear function [initial value]
1
Gate function
[bit1, bit0] CGE1, CGE0: Counter clear/gate edge selection bit
These bits select the detection edge/level of the external pin ZIN.
530
CGE1
CGE0
When counter clear function is selected
When gate function is selected
0
0
Disables edge detection [initial value].
Disables level detection [initial
value] (count disable)
0
1
Falling edge
"L" level
1
0
Rising edge
"H" level
1
1
Setting disabled
Setting disabled
CHAPTER 19 UP/DOWN COUNTER
19.3
Operation of Up/Down Counters
This section describes the up/down counter operation.
■ Selecting Counting Mode
This counters/timers have four counting modes. The CMS1 and CMS0 bits of the CCR register are used to
select the counting modes.
CMS1
CMS0
Counting mode
0
0
Timer mode (down count) [initial value]
0
1
Up/down counting mode
1
0
Phase difference counting mode, 2 multiplication
1
1
Phase difference counting mode, 4 multiplication
● Timer mode [down count]
In timer mode, the output of the internal prescaler is used for counting down. For the internal prescaler,
either two machine cycles or eight machine cycles can be selected with the CLKS bit of the CCRH register.
● Up/down counting mode
In up/down counting mode, counting up/down is performed by counting the input through external pins
AIN and BIN. The input through the AIN pin controls counting up and the input through the BIN pin
controls counting down.
The inputs through the AIN pin and BIN pin are subject to edge-detected. The edge detection can be
selected by the CES1 and CES0 bits of the CCRH register.
CES1
CES0
Selection edge
0
0
Disables the edge detection. [initial value]
0
1
Detects falling edge.
1
0
Detects rising edge.
1
1
Detects both falling and rising edges.
● Phase difference counting mode (two multiplication/four multiplication)
In phase difference counting mode, to count the phase difference between phase A and phase B of the
output signal for the encoder, detect the input level of the BIN pin at input edge detection of the AIN pin.
For the phase difference between AIN pin input and BIN pin input in two multiplication or four
multiplication mode, count up if the AIN is faster, and count down if the BIN is faster.
In two multiplication mode, counting is performed by detecting the value of the AIN pin in the period
531
CHAPTER 19 UP/DOWN COUNTER
between the rising and falling edges of the BIN pin. In this case, counting is performed as follows:
Edge of the BIN pin
Level of the AIN pin
Count
Rising ↑
"H" level
Count up
Rising ↑
"L" level
Count down
Falling ↓
"H" level
Count down
Falling ↓
"L" level
Count up
Figure 19.3-1 Overview of the Phase Difference Counting Mode (Two Multiplication) Operation
AIN pin
BIN pin
+1
1
Count value 0
+1
2
+1
3
+1
4
+1
5
-1
4
+1
5
-1
4
-1
3
-1
2
-1
1
-1
0
In four-multiplication mode, counting is performed by detecting the value of the AIN pin at the timing
between the rising and falling edges of the BIN pin and detecting the value of the BIN pin at the timing
between the rising and falling edges of the AIN pin. In this case, counting is performed as follows:
Edge input
Edge
Level input
Level
Count
"H" level
Count up
"L" level
Count down
"H" level
Count down
Falling ↓
"L" level
Count up
Rising ↑
"H" level
Count down
"L" level
Count up
"H" level
Count up
"L" level
Count down
Rising ↑
BIN
AIN
Rising ↑
AIN
Falling ↓
Rising ↑
BIN
Falling ↓
Falling ↓
Figure 19.3-2 Overview of the Phase Difference Counting Mode (Four Multiplication) Operation
AIN pin
BIN pin
Count value 0
+1 +1 +1 +1 +1+1 + 1+1 +1+1
1 2 3 4 5 6 7 8 9 10
-1
9
+1
10
-1
9
-1 -1 -1 -1 -1 -1 -1 -1
8 7 6 5 4 3 2 1
For counting the encoder output, by inputting the A phase to the AIN pin, the B phase to the BIN pin, and
the Z phase to the ZIN pin, a highly precise count of the rotation angle and number of rotations can be
obtained and the rotation direction can be detected as well.
When this counting mode is selected, the detection edge selection with the CES1 and CES0 bits is invalid.
532
CHAPTER 19 UP/DOWN COUNTER
■ Reload/Compare Function
This counters have reload and compare clear functions, which can be combined for processing.
The examples of setting are shown in following.
RLDE
UCRE
Reload/Compare function
0
0
Disables clearing by reload/compare [initial value].
0
1
Enables clearing by compare.
1
0
Reload is enabled.
1
1
Enables clearing by reload/compare.
● Reload function
When the reload function is started, the value of the RCR is transferred to the UDCR with the timing of the
down count clock after an underflow. In this case, when UDFF bit is set, an interrupt request is generated.
In a mode in which down counting is not performed, starting this function is invalid.
Figure 19.3-3 Overview of the Operation of the Reload Function
(0FFFFH)
FFH
RCR
Reload interrupt
generated
Reload interrupt
generated
00H
Underflow
Underflow
● Compare clear function
When the compare clear function is enabled, the compare function can be used in all modes other than
timer mode. When the compare function is started, if the value of RCR and the value of UDCR match,
CMPF bit is set and an interrupt request is generated. When the compare clear function is started, the
UDCR is cleared with the timing of the next up count clock. (The UDCR is not cleared when counting
down is performed.)
In a mode in which up counting is not performed, starting this function is invalid.
533
CHAPTER 19 UP/DOWN COUNTER
Figure 19.3-4 Overview of the Compare Function Operation
(0FFFFH)
FFH
RCR
Compare match
Compare match
00H
Counter clear,
interrupt generated
534
Counter clear,
interrupt generated
CHAPTER 19 UP/DOWN COUNTER
■ Synchronous Start of Reload/Compare Function
When the reload/compare function is started, counting up or down can be performed with an arbitrary
width.
The reload function is started at an underflow and transfers the value of the RCR to the UDCR. When the
values of RCR and UDCR match, the compare function clears the UDCR. By using these functions,
counting up or down is performed for values between "0000H" and the value of the RCR.
Figure 19.3-5 Overview of the Operation When the Reload and Compare Functions are Started at the Same Time
FFH
RCR
Compare match Compare match Reload
Reload
Reload
Compare match
00H
Counter clear
Counter clear
Underflow
Underflow
Counter clear
Underflow
An interrupt to the CPU can be generated at a compare match or at reload (underflow). These interrupt
outputs can be enabled separately.
The timing for clearing the UDCR is different during counting and when counting is stopped.
Reloading (writing "1" to the CTUT bit) by software is not allowed during counting.
• During counting, if an event for clearing occurs, all the events are synchronized with the count clock.
UDCR
Clear event
0065H
0066H
0000H
0001H
Synchronized to this clock
Count clock
Reference:
During counting, reloading due to an underflow is performed in synchronization with all count clocks.
535
CHAPTER 19 UP/DOWN COUNTER
• When an event for clearing occurs during counting, if counting is stopped in count clock
synchronization wait state (state of waiting for the count input for synchronization), the clear operations
are performed when counting is stopped.
UDCR
0065H
0066H
0000H
Clear event
Count clock
Diable (count disabled)
Count enable
Enable (count enabled)
• If the events for reloading and clearing occur during counting, reload and clear are performed when the
event occurs.
UDCR
0065H
0080H
Load/
clear event
Clear by compare is performed when the values of the UDCR and the RCR match and while counting up. If
down counting is performed or counting is stopped, the clear operation is not performed even when the
values of the UDCR and the RCR match.
As for the timing of clearing and reloading, the clear operation follows the above timing for all events other
than reset input, and reloading also uses the above timing for all events.
When the events for clearing and reloading occur at the same time, the clear event takes priority.
■ Writing Data to UDCR
Data cannot be written to the UDCR directly from the data bus. To write arbitrary value to the UDCR,
follow the procedure below.
1. Write the data that is to be written to the UDCR first to the RCR (Note that this means that the original
data in the RCR will be lost).
2. By setting the CTUT bit of the CCR to "1", data is transferred from the RCR to the UDCR.
Perform the above operation while counting is stopped (when the CSTR bit of the CSR is "0").
Reference:
If "1" is written to the CTUT bit by mistake during counting, the value of the RCR is transferred to the
UDCR at the timing for a write.
Besides the above procedure, the following procedure can also be applied to clear the counter.
• Clearing by reset input.
• Clearing by edge input through the ZIN pin.
• Clearing by writing "0" to UDCC bit of the CCR.
• Clearing by compare.
The above can be performed regardless of whether counting is performed or stopped.
536
CHAPTER 19 UP/DOWN COUNTER
■ Count Clear/Gate Function
The ZIN pin can be used after selecting the count clear function or gate function based on the CGSC bit of
the CCR register.
When the count clear function is started, the ZIN pin clears the counter. The CGE1 and CGE0 bits of the
CCRL register can control which edge input of the ZIN pin to use for counting.
When the gate function is started, the ZIN pin enables or disables counting. The CGE1 and CGE0 bits of
the CCR register can control which level input of the ZIN pin enables counting.
This function is effective for all modes.
CGSC
ZIN pin function
0
Counter clear function [initial value]
1
Gate function
CGE1
CGE0
When counter clear function is used
When gate function is used
0
0
Disables edge detection. [initial value]
Disables level detection. [initial value]
(count disable)
0
1
Falling edge
"L" level
1
0
Rising edge
"H" level
1
1
Setting disabled
Setting disabled
■ Count Direction Flag
The count direction flag (UDF1 and UDF0) indicates at the time of up/down counting whether the counting
operation preceding the current operation was counting up or down. Based on the count clock signal from
the input of the AIN and BIN pins, this value of this flag changes for each count. Current rotation direction,
such as control of motor, can be determined by referring this flag.
UDF1
UDF0
Count direction
0
0
Without input [initial value]
0
1
Down count
1
0
Up count
1
1
Up/down occurs simultaneously (no counting operation is performed).
537
CHAPTER 19 UP/DOWN COUNTER
■ Count Direction Change Flag
The CDCF is set when the counting direction changes between up and down. Simultaneously to setting this
flag, an interrupt request to the CPU can be generated. By referring the interrupt and count direction flag,
the direction to which counting is changed can be determined.
However, note that when the period of direction change is short and multiple direction changes are
performed in succession, the direction that the flag indicates after the direction change may return to the
original direction so that it appears as if the counting direction has not changed at all in between.
CDCF
Count direction change detection
0
No direction change [initial value]
1
Counting direction has changed (at least once).
■ Compare Detection Flag
The CMPF is set when the values of UDCR and RCR match during counting. This flag is set for a match
during counting up or down, match by occurrence of a reloading event, as well as when the values already
match when counting started.
■ Operations for 8 Bits × 2 Channels and 16 Bits × 1 Channel
This module can be used as an 8-bit up/down counter for two channels or a 16-bit up/down counter for one
channel. Setting the M16E bit of the CCR register to 0 sets 8 bit mode for two channels. Setting the bit to
"1" sets 16 bit mode for one channel.
For operation in 16 bit mode for one channel, the registers CSR0, CCRL0, CCRH0 are valid and the CSR1,
CCRL1, and CCRH1 registers are invalid. In addition, the AIN0, BIN0, ZIN0 pins are enabled as input
pins, while the AIN1, BIN1, and ZIN1 pins are disabled.
538
CHAPTER 19 UP/DOWN COUNTER
■ Interrupt Generation Timing
Interrupt flag
Flag setting interrupt
Reload
Clear
CDCF
(Count direction change
flag)
An interrupt is generated
simultaneously with setting
of the flag when counting
starts immediately after the
counting direction is
changed.
CMPF
(Compare detection flag)
An interrupt is generated
simultaneously with setting
of the flag when the values
of RCR and UDCR match
when up or down counting,
or reload counting is
initiated.
UDCR is cleared at
the timing of the
first up count after
RCR and UDCR
match. (UDCR is
not cleared for
down counting).
OVFF
(Overflow detection flag)
An interrupt is generated
simultaneously with setting
of the flag at the timing of
the first up count after the
count reaches "FFFFH".
UDCR is cleared at
the timing of the
first count after the
count reaches
"FFFFH".
UDFF
(Underflow detection flag)
An interrupt is generated
simultaneously with setting
of the flag at the timing of
the first down count after
the count reaches "0000H".
The value of RCR is
transferred to
UDCR at the timing
of the first count
after the count
reaches "0000H".
• When interrupt is generated, count is stopped until clearing interrupt flag.
• Because the value of RCR is used for both the reload and compare values, the compare flag is set
always when reloading is performed.
• If the clear function is enabled, clearing occurs when up counting is performed after the values of RCR
and UDCR match during down counting.
■ Note
The count direction is set to down when the count is reset. Therefore, at the first up count after resetting,
CDCR is set to "1" to indicate that the counting direction has been changed.
After the up/down count register (UDCR) reaches the maximum count that the register can hold, counting
continues without a carry-over. It therefore appears that counting is continuing with the up-down count
register cleared.
The minimum pulse width at the AIN, BIN, and ZIN pins is 2 × T (T stands for the peripheral clock
machine cycle).
539
CHAPTER 19 UP/DOWN COUNTER
540
CHAPTER 20
CLOCK MONITOR
This chapter explains the functions and operation of
clock monitor.
20.1 Overview of Clock Monitor
20.2 Clock Output Enable Register
541
CHAPTER 20 CLOCK MONITOR
20.1
Overview of Clock Monitor
When the output enable bit of the clock output enable register is set to " 1 ", the clock is
outputted from the clock monitor terminal (CKOT). The frequency of the clock to be
outputted is set by the output frequency selection bit of the clock output enable
register.
■ Output Frequency of Clock Monitor
The frequency of the clock to be outputted using the clock monitor function is shown in Table 20.1-1.
Table 20.1-1 Output Frequency for Clock Monitor Function
φ=32MHz
φ=16MHz
φ=8MHz
FRQ2 to
FRQ0
Clock
output
frequency
Cycle
Frequency
Cycle
Frequency
Cycle
Frequency
000B
φ/21
62.5ns
16MHz
125ns
8MHz
250ns
4MHz
001B
φ/22
125ns
8MHz
250ns
4MHz
500ns
2MHz
010B
φ/23
250ns
4MHz
500ns
2MHz
1.0µs
1MHz
011B
φ/24
500ns
2MHz
1.0µs
1MHz
2.0µs
500kHz
100B
φ/25
1.0µs
1MHz
2.0µs
500kHz
4.0µs
250kHz
101B
φ/26
2.0µs
500kHz
4.0µs
250kHz
8.0µs
125kHz
110B
φ/27
4.0µs
250kHz
8.0µs
125kHz
16.0µs
62.5kHz
111B
φ/28
8.0µs
125kHz
16.0µs
62.5kHz
32.0µs
31.3kHz
φ: Machine clock (CLKP) frequency
542
CHAPTER 20 CLOCK MONITOR
■ Block Diagram of Clock Monitor
Internal data bus
Figure 20.1-1 Clock Monitor Block Diagram
φ
Count
clock
selector
Prescaler
Pin
CKOT
Output enable
3
Clock output enable
register (CMCLKR)
−
−
−
−
CKEN FRQ2 FRQ1 FRQ0
− : Undefined bit
φ : Machine clock frequency
543
CHAPTER 20 CLOCK MONITOR
20.2
Clock Output Enable Register
Clock output enable register sets the clock output.
■ Bit Configuration of Clock Output Enable Register
CMCLKR
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
CKEN
R/W
FRQ2
R/W
FRQ1
R/W
RQ0
R/W
----0000B
R/W: Readable/Writable
[bit7 to bit4] Reserved: Reserved bits
Reserved bits.
Reading is always "1111B".
Writing to these bits is invalid.
[bit3] CKEN: Output enable bit
Output of the clock monitor terminal (CKOT) is enabled.
CKEN
Clock output enable
0
Clock output disabled [initial value]
1
Clock output enabled
[bit2 to bit0] FRQ2 to FRQ0: Output frequency select bits
Frequency of the clock to be outputted is set.
The division rate for the machine clock (CLKP) can be selected and set from 8 types.
544
FRQ2
FRQ1
FRQ0
Divide ratio
0
0
0
2-frequency division [initial value]
0
0
1
4-frequency division
0
1
0
8-frequency division
0
1
1
16-frequency division
1
0
0
32-frequency division
1
0
1
64-frequency division
1
1
0
128-frequency division
1
1
1
256-frequency division
CHAPTER 21
REAL TIME CLOCK
This chapter describes the register structure and
functions of the Real Time Clock (hereafter, referred to
as RTC) and describes the operation of RTC module.
The RTC consists of the timer control register, subsecond register, second/minute/hour registers, 1/2 clock
divider, 21-bit prescaler and second/minute/hour
counters. The RTC operates as the real-world time timer
and provides the real-world time information.
Also, this chapter explains the sub clock calibration unit
supplied to the RTC module. When the main clock is
selected as a clock which supplies to the RTC module,
set the main clock frequency to 4MHz.
21.1 Configuration of Registers
21.2 Block Diagram
21.3 Details of Registers
21.4 Clock Calibration Unit
21.5 Register of Clock Calibration Unit
21.6 Using of Clock Calibration Unit
545
CHAPTER 21 REAL TIME CLOCK
21.1
Configuration of Registers
This section shows register configuration of real time clock.
■ Register List of Real Time Clock
WTCRH
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
INTE3
INT3
INTE2
INT2
INTE1
INT1
INTE0
INT0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
R/W
R/W
R/W
-
RUN
R/W
UPDT
R/W
-
ST
R/W
000-00-0B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
D20
D19
D18
D17
D16
---XXXXXB
-
-
-
R/W
R/W
R/W
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
D15
R/W
D14
R/W
D13
R/W
D12
R/W
D11
R/W
D10
R/W
D9
R/W
D8
R/W
XXXXXXXXB
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D7
R/W
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
R/W
XXXXXXXXB
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
R/W
R/W
R/W
H4
R/W
H3
R/W
H2
R/W
H1
R/W
H0
R/W
---XXXXXB
WTCRL
WTBR2
WTBR1
WTBR0
WTHR
R/W: Readable/Writable
X:
Undefined
(Continued)
546
CHAPTER 21 REAL TIME CLOCK
(Continued)
WTMR
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
M5
R/W
M4
R/W
M3
R/W
M2
R/W
M1
R/W
M0
R/W
--XXXXXXB
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
-
-
S5
R/W
S4
R/W
S3
R/W
S2
R/W
S1
R/W
S0
R/W
--XXXXXXB
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
-
-
WTCK
R/W
DBL
R/W
------00B
WTSR
WTDBL
R/W: Readable/Writable
X:
Undefined
547
CHAPTER 21 REAL TIME CLOCK
21.2
Block Diagram
This section shows the block diagram of a real time clock.
■ Block Diagram
Oscillation
clock
21-bit
prescaler
1/2-clock
divider
WOT
CO
EN
Sub-second
register
UPDT
ST
Second counter
CI
EN
LOAD
6-bit
INTE0
INT0
INTE1
Minute counter
Time counter
6-bit
Second/minute/register
INT1
INTE2
INT2
5-bit
INTE3
INT3
IRQ
548
CHAPTER 21 REAL TIME CLOCK
21.3
Details of Registers
This section explains details of register configuration for real time clock.
■ Timer Control Register (WTCR)
WTCRH
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
INTE3
R/W
INT3
R/W
INTE2
R/W
INT2
R/W
INTE1
R/W
INT1
R/W
INTE0
R/W
INT0
R/W
00000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
RUN
UPDT
-
ST
000-00-0B
-
-
-
-
R/W
R/W
-
R/W
WTCRL
R/W: Readable/Writable
[bit15 to bit8] INT3 to INT0, INTE3 to INTE0: Interrupt flag and interrupt enable bit
INT0 to INT3 are the interrupt flags. They are set when the second counter, minute counter and hour
counter overflow respectively. If an INT bit is set while the corresponding INTE bit is "1", the flags
generate an interrupt signal. These flags are intended to generate an interrupt signal every second/minute/
hour/day. Writing "0" to the INT bits clears the flags and writing "1" does not have any effect, Any readmodify-write instruction performed on the INT bit results reading "1".
Interrupt
Source
Interrupt enable bit
Interrupt flag
Second interrupt
Prescaler overflow
INTE0
INT0
Minute interrupt
Second counter overflow
INTE1
INT1
Hour interrupt
Minute counter overflow
INTE2
INT2
Day interrupt
Hour counter overflow
INTE3
INT3
[bit7 to bit5] Reserved: Reserved bits
Be sure to set these bits to "000B".
[bit3] RUN: Flag
Read is only possible. If the reading value is "1", this shows RTC module is operating.
[bit2] UPDT: Update bit
The UPDT bit is prepared for modifying the second/minute/hour counter values.
To modify the counter values, write the modified data in the second/minute/hour registers. Then, set the
UPDT bit to "1". The register values are loaded to the counter at the next CO signal (write) from the 21bit prescaler. The UPDT bit is reset by the hardware when the counter values are updated. However, if
the set operation by software and the reset operation by hardware occur at the same time, the UPDT bit
will not be reset. This will only work, if the peripheral clock (CLKP) has a higher frequency than the
RTC clock (oscillation clock).
Writing "0" to the UPDT bit has no effect. Read modify write instruction performed on UPDT bit results
reading "0".
549
CHAPTER 21 REAL TIME CLOCK
[bit0] ST: Start bit
When the ST bit is set to "1", the watch timer loads second/minute/hour values from the registers and
starts its operation. When it is reset to "0", all the counters and the prescalers are reset to "0" and halt.
This bit can also be used for updating the counter values. Set ST bit to "0", wait for RUN bit to go to "0",
update the counter values and set ST bit to "1".
550
CHAPTER 21 REAL TIME CLOCK
■ Sub Second Registers
WTBR2
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
Initial value
-
-
-
D20
R/W
D19
R/W
D18
R/W
D17
R/W
D16
R/W
---XXXXXB
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
D15
R/W
D14
R/W
D13
R/W
D12
R/W
D11
R/W
D10
R/W
D9
R/W
D8
R/W
XXXXXXXXB
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D7
R/W
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
R/W
XXXXXXXXB
WTBR1
WTBR0
R/W: Readable/Writable
X:
Undefined
[bit20 to bit0] D20 to D0
The sub-second register stores the reload value for the 21-bit prescaler. This value is reloaded after the
reload counter reaches "0". Note that when modifying all the three bytes, make sure the reload operation
will not be performed in between the write instructions. Otherwise, the 21-bit prescaler loads the
combined value of new data and old data bytes. It is recommended that the sub-second register are
updated while the ST bit is "0". While the sub-second registers are set to "0", the 21-bit prescaler does
not operate at all.
The combination of these two prescalers is allowed to provide a clock signal of exact one second.
The example of the setting value for the sub second register is shown below.
Input clock frequency
WTBR setting value
(decimal)
WTBR setting value
(hexadecimal)
4MHz
1999999
1E847F
100kHz
49999
00C34F
32kHz
15999
003E7F
Note:
The sub second register is 21-bit and the upper limit of the frequency which generates a second is
4.19MHz. When the main clock is selected as a clock which supplies to the RTC module, set the
main clock frequency to 4MHz.
551
CHAPTER 21 REAL TIME CLOCK
■ Second/Minute/Hour Registers
WTHR
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
R/W
R/W
-
H4
R/W
H3
R/W
H2
R/W
H1
R/W
H0
R/W
XXXXXXXXB
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
M5
R/W
M4
R/W
M3
R/W
M2
R/W
M1
R/W
M0
R/W
--XXXXXXB
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
-
-
S5
R/W
S4
R/W
S3
R/W
S2
R/W
S1
R/W
S0
R/W
--XXXXXXB
WTMR
WTSR
R/W: Readable/Writable
X:
Undefined
The second/minute/hour registers stores the time information. It is a binary representation of the second,
minute and hour.
Reading these registers simply returns the counter values. These registers are combined with write value
however, the written data is loaded in the counters after the UPDT bit is set to "1".
Since there are three byte-registers, make sure the output values are consistent. i.e. Output value of "1 hour,
59 minutes, 59 seconds" could be "0 hour 59 minutes, 59 seconds" or "2 hours, 59 minutes, 59 seconds".
If reading is done at the moment of the counter overflow it is possible to read wrong values. So reading
should be either triggered by an interrupt of the RTC module or the following procedure should be
followed:
• Clearing of RTC interrupt flag (INT)
• Register reading
• If time overflow occurs during reading when the flag is set after reading, it is read again.
552
CHAPTER 21 REAL TIME CLOCK
■ Clock Disabling Registers
WTDBL
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
-
-
WTCK
R/W
DBL
R/W
------00B
R/W: Readable/Writable
X:
Undefined
[bit1] WTCK: Clock selecting
This bit can select the input clock of the sub second register. The initial value of this bit is "0", and 4MHz
oscillation (main oscillation) is selected as the clock source. When setting this bit to "1", 32kHz
oscillation (sub oscillation) is selected as the clock source.
This bit can be read and written.
Note:
For the product that 32kHz oscillation is not supported, be sure to set the WTCK bit to "0".
When the main clock frequency is faster than 4MHz, set "1" and select the sub clock.
[bit0] DBL: Clock disabled
When setting this bit to "1", clock of RTC module is disabled. For normal operation, set this bit to "0".
This bit is initialized to "0". Read and write are enabled.
553
CHAPTER 21 REAL TIME CLOCK
21.4
Clock Calibration Unit
By using the sub clock calibration unit, a sub oscillation clock supplied to the RTC
module can be calibrated based on a main oscillation Clock.
■ Clock Calibration Unit
By using the clock calibration unit, the signal generated by a sub oscillation can be measured by a main
oscillation with software.
For process by software and usage of this unit, the accuracy of a sub oscillation can be improved to that of
a main oscillation. The measurement result from the clock calibration unit can be processed by software
and obtained the required setting to the RTC module.
This unit has a timer operates in sub clock and in main, and the value of main timer is stored in the register
when the sub timer triggers the main timer. The value stored in the register is processed with software, and
the required setting to the RTC module can be calculated.
■ Measurement Processing Timing
Figure 21.4-1 Measurement Processing Timing
32 kHz
STRT(CLKP)
STRTS(32 kHz)
RUN(32 kHz)
RUNS(4 MHz)
CUTD
32 kHz counter (16-bit)
4 MHz counter (24-bit)
CUTD-1
Old CUTR
2
1
0
CUTD
New CUTR
READY (32 kHz)
READY PUSE (CLKP)
INT (CLKP)
■ Clock
The clock calibration unit operates using three clocks: main clock OSC4, sub clock OSC32, peripheral
clock CLKP. Each clock area is synchronized with the synchronization circuit.
These clocks must satisfy the following:
• Clock ratio
TOSC32 > 2 × TOSC4 + 3 × TCLKP
TOSC4 < 1/2 × TOSC32 – 3/2 × TCLKP
TCLKP < 1/3 × TOSC32 – 2/3 × TOSC4
554
CHAPTER 21 REAL TIME CLOCK
21.5
Register of Clock Calibration Unit
This section lists the register of the clock calibration unit and explains the function of
registers in detail.
■ Register List of Clock Calibration Unit
CUCR
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
R
R
R
STRT
R/W
R
R/W
INT
R/W
INTEN
R/W
00000000B
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
TDD15
R/W
TDD14
R/W
TDD13
R/W
TDD12
R/W
TDD11
R/W
TDD10
R/W
TDD9
R/W
TDD9
R/W
10000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
TDD7
R/W
TDD6
R/W
TDD5
R/W
TDD4
R/W
TDD3
R/W
TDD2
R/W
TDD1
R/W
TDD0
R/W
00000000B
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
R
R
R
R
R
R
R
R
00000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
TDR23
R
TDR22
R
TDR21
R
TDR20
R
TDR19
R
TDR18
R
TDR17
R
TDR16
R
00000000B
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
TDR15
TDR14
TDR13
TDR12
TDR11
TDR10
TDR9
TDR8
00000000B
R
R
R
R
R
R
R
R
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
TDR7
R
TDR6
R
TDR5
R
TDR4
R
TDR3
R
TDR2
R
TDR1
R
TDR0
R
00000000B
CUTDH
CUTDL
CUTR1H
CUTR1L
CUTR2H
CUTR2L
R/W: Readable/Writable
R:
Read only
555
CHAPTER 21 REAL TIME CLOCK
21.5.1
Calibration Unit Control Register (CUCR)
The calibration unit control register (CUCR) has following functions:
• Start/stop of calibration measurement
• Interrupt enable/disable
• Display the end of calibration measurement
■ Calibration Unit Control Register (CUCR)
CUCR
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
R
R
R
STRT
R/W
R
R/W
INT
R/W
INTEN
R/W
00000000B
R/W: Readable/Writable
R:
Read only
[bit7 to bit5] Reserved: Reserved bits
Reserved bit
Reading value is always "0".
[bit4] STRT: Calibration starting bit
0
Calibration stop, calibration unit stop [initial value]
1
Calibration start
When the STRT bit is set to "1" by software, the calibration is started. Sub timer starts counting down
from the value set in sub timer data register, and main timer starts counting up from "0".
When sub timer reaches "0", this bit is reset to "0" automatically.
When "0" is written to this bit by software during calibration processing, the calibration stops
immediately. If writing "0" by software and resetting "0" by hardware occur at the same time, the
hardware is preferred. That is, the calibration is completed, and the INT bit which indicates the
completion is set to "1". Writing "1" to this bit during calibration has no effect on operation.
[bit3] Reserved: Reserved bit
Reserved bit
Reading value is always "0".
[bit2] Reserved: Reserved bit
Reserved bit
Be sure to set this bit to "0".
556
CHAPTER 21 REAL TIME CLOCK
[bit1] INT: Interrupt flag bit
0
During calibration or calibration unit stop [initial value]
1
Calibration completed
This bit indicates the end of calibration. After the calibration starts, if sub timer reaches 0, main timer
data register stores the last value of main timer, and the INT bit is set to "1".
When read-modify-write instruction is executed for this bit, "1" is read. The INT bit is cleared by writing
"0". Writing "1" is invalid.
Because the interrupt flag (INT) is not reset with hardware, when new calibration is started, reset with
software.
[bit0] INTEN: Interrupt enable bit
0
Interrupt disabled [initial value]
1
Interruption enabled
This bit is an interrupt enable bit. If this bit is set to "1" when the INT bit of bit1 is set due to the
completion of calibration, the calibration unit sends the interrupt signal to the CPU. The INT bit is
automatically set when the calibration is completed even though the interrupt is disabled (INTEN=0)
regardless of the setting value for the INTEN bit.
This bit can be read and written.
557
CHAPTER 21 REAL TIME CLOCK
21.5.2
Sub Timer Data Register (CUTD)
Sub timer data register (CUTD) retains the value which determines the calibration
period (sub reload value).
■ Sub Timer Data Register (CUTD)
CUTDH
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
TDD15
R/W
TDD14
R/W
TDD13
R/W
TDD12
R/W
TDD11
R/W
TDD10
R/W
TDD9
R/W
TDD9
R/W
10000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
TDD7
R/W
TDD6
R/W
TDD5
R/W
TDD4
R/W
TDD3
R/W
TDD2
R/W
TDD1
R/W
TDD0
R/W
00000000B
CUTDL
R/W: Readable/Writable
The initial value of sub timer data register is "8000H", and it corresponds to the measurement time of one
second at 32.768kHz.
Write to this register while the calibration stops (STRT=0).
Sub timer data register stores the value specified to the calibration time. When the calibration is started, the
set valve is loaded to sub timer, and counting down is performed until the timer reaches "0".
When "0000H" is set to sub timer data register, underflow occurs, and the measurement value is (FFFFH+1)
× TOSC32.
To set the measurement time to one second, specify the set value to "8000H". Table 21.5-1 shows the ideal
value of measurement result (for OSC4=4.00MHz).
Table 21.5-1 Ideal Measurement Result
558
Calibration time
CUTD value
CUTR value
2.00 s
0000H
7A1200H
1.75 s
E000H
6ACFC0H
1.50 s
C000H
5B8D80H
1.25 s
A000H
4C4B40H
1.00 s
8000H
3D0900H
0.75 s
6000H
2DC6C0H
0.50 s
4000H
1E8480H
0.25 s
2000H
0F4240H
CHAPTER 21 REAL TIME CLOCK
The processing time from writing "1" to the STRT bit to resetting of the STRT bit by hardware due to the
completion of calibration is longer than actual correcting time. This is because the calibration unit uses
multiple clocks and for its synchronization.
• Processing time < (CUTD + 3) × TOSC32
• Correcting time = CUTD × TOSC32
559
CHAPTER 21 REAL TIME CLOCK
21.5.3
Main Timer Data Register (CUTR)
Timer data register (CUTR) retains the value of calibrating result (4MHz counter).
■ Main Timer Data Register (CUTR)
Completion of calibration is shown by INT bit and STRT bit of CUCR register.
When the INT bit is "1" and the STRT bit is "0" by the completion of calibration, the CUTR value is
enabled.
Reference:
The CUTR register value is continued to update during the calibration (STRT=1), and the reading
value of the register sets the data at calibration as well.
CUTR1H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
R
R
R
R
R
R
R
R
00000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
TDR23
R
TDR22
R
TDR21
R
TDR20
R
TDR19
R
TDR18
R
TDR17
R
TDR16
R
00000000B
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
TDR15
R
TDR14
R
TDR13
R
TDR12
R
TDR11
R
TDR10
R
TDR9
R
TDR8
R
00000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
TDR7
R
TDR6
R
TDR5
R
TDR4
R
TDR3
R
TDR2
R
TDR1
R
TDR0
R
00000000B
CUTR1L
CUTR2H
CUTR2L
R:
Read only
4MHz timer data register stores the calibration result. When the calibration is started, 4MHz timer starts
counting up from 0. When 32kHz timer reaches 0, 4MHz timer stops counting, and the register retains the
calibration result until next calibration is triggered by software (STRT=1).
560
CHAPTER 21 REAL TIME CLOCK
21.6
Using of Clock Calibration Unit
This section explains the accuracy of calibration and measurement time.
■ Setting of Sub Timer Data Register
Setting of sub timer data register can be calculated in the following method.
Suppose that the main oscillation frequency is 4MHz and the sub oscillation frequency is 32.768kHz.
If the calibration time is one second, set "8000H"(=32768D) to sub timer data register. This indicates 32768
cycles of 32.768kHz oscillation clock.
By setting this, the value of approximately "3D0900H" is stored to main timer data register as the
calibration result. This indicates 4000000 cycles of main oscillation.
■ Accuracy of Calibration
The calibration accuracy depends on the input clock frequency and calibration time of main timer.
Maximum error of main timer is ±1. The calibration accuracy is calculated in the following method when
the input clock frequency is main and calibration time is one second.
0.25µs (input clock cycle) /1s (correcting time) = 0.25ppm
561
CHAPTER 21 REAL TIME CLOCK
562
CHAPTER 22
A/D CONVERTER
This chapter explains the overview of the A/D converter,
the configuration/function of the register, and its
operation.
22.1 Overview of A/D Converter
22.2 Block Diagram of the A/D Converter
22.3 Registers of A/D Converter
22.4 Operation of A/D Converter
563
CHAPTER 22 A/D CONVERTER
22.1
Overview of A/D Converter
The A/D converter converts an analog input voltage to a digital value. This section
explains the overview of the A/D converter.
■ A/D Converter
The A/D converter has the following features:
• Conversion time: Minimum of 3.0 µs per channel
• The adoption of the sequential comparison conversion method with sample & hold circuit
• 10-bit resolution (Switchable between 8 bits and 10 bits)
• Selection of analog input from 24 channels by software
• Conversion Mode
- Single conversion mode: Converts one channel.
- Scan conversion mode: Continuously converts multiple channels. Up to 24 channels can be
programmed.
- Continuous conversion mode: Repetitiously converts a specified channel.
- Stop conversion mode: Converts a specified channel, pauses, and stands by until the next activation
occurs (the conversion start can be synchronized).
• Interrupt request
- At the A/D conversion end, the interrupt request of A/D conversion end can be generated for CPU
• Selectable start cause
- Start cause is selected from software, external trigger (falling edge), or timer (rising edge).
■ Input Impedance
The sampling circuit of the A/D converter is shown in the following equivalent circuit.
Figure 22.1-1 Input Impedance
Rin
13.6kΩ(AVCC ≥ 4.0V)
2.52kΩ(AVCC ≥ 4.5V)
Rext
Analog
signal
ANx
Analog Switch
Cin:max 10.7pF
ADC
Don't set Rext over maximum sampling time (Tsamp).
Rext = Tsamp/(7*Cin) - Rin
564
CHAPTER 22 A/D CONVERTER
22.2
Block Diagram of the A/D Converter
Figure 22.2-1 shows a block diagram of the A/D converter.
■ Block Diagram of the A/D Converter
Figure 22.2-1 Block Diagram of the A/D Converter
AN0
AN1
AN2
AN3
MPX
AVCC
AVSS
D/A converter
AN4
AN5
AN6
AN7
AN8
Comparator
Internal data bus
Sample & hold circuit
Decoder
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
Sequential
comparison register
Input circuit
AN9
AN10
AVRH/L
Data register
A/D control register 0
A/D control register 1
ADCS0/
ADCS1
Operation
clock
ATG pin
16-bit
reload timer
CLKP
Prescaler
565
CHAPTER 22 A/D CONVERTER
22.3
Registers of A/D Converter
This section explains the configuration and function of the register used by the A/D
converter.
■ Registers of A/D Converter
The A/D converter has the following six types of registers.
• Analog input enable register (ADER)
• Control Status Registers (ADCS)
• Data Register (ADCR)
• Conversion time setting register (ADCT)
• Start channel setting register (ADSC)
• End channel setting register (ADEC)
■ Register List
ADERH low byte
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ADE23
R/W
ADE22
R/W
ADE21
R/W
ADE20
R/W
ADE19
R/W
ADE18
R/W
ADE17
R/W
ADE16
R/W
00000000B
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
ADE15
R/W
ADE14
R/W
ADE13
R/W
ADE12
R/W
ADE11
R/W
ADE10
R/W
ADE9
R/W
ADE8
R/W
00000000B
ADERL high byte
ADERL low byte
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ADE7
R/W
ADE6
R/W
ADE5
R/W
ADE4
R/W
ADE3
R/W
ADE2
R/W
ADE1
R/W
ADE0
R/W
00000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
BUSY
R/W
INT
R/W
INTE
R/W
PAUS
R/W
STS1
R/W
STS0
R/W
STRT
R/W
reserved
R/W
00000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
MD1
MD0
S10
ACH4
ACH3
ACH2
ACH1
ACH0
00000000B
R/W
R/W
R/W
R
R
R
R
R
ADCS1
ADCS0
R/W: Readable/Writable
R:
Read only
(Continued)
566
CHAPTER 22 A/D CONVERTER
(Continued)
ADCR1
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
-
-
-
-
-
-
D9
R
D9
R
------XXB
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D7
R
D6
R
D5
R
D4
R
D3
R
D2
R
D1
R
D0
R
XXXXXXXXB
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
CT5
R/W
CT4
R/W
CT3
R/W
CT2
R/W
CT1
R/W
CT0
R/W
ST9
R/W
ST9
R/W
00010000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ST7
R/W
ST6
R/W
ST5
R/W
ST4
R/W
ST3
R/W
ST2
R/W
ST1
R/W
ST0
R/W
00101100B
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
-
-
-
ANS4
R/W
ANS3
R/W
ANS2
R/W
ANS1
R/W
ANS0
R/W
---00000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
ANE4
R/W
ANE3
R/W
ANE2
R/W
ANE1
R/W
ANE0
R/W
---00000B
ADCR0
ADCT1
ADCT0
ADSCH
ADECH
R/W: Readable/Writable
R:
Read only
X:
Undefined
567
CHAPTER 22 A/D CONVERTER
22.3.1
Analog Input Enable Register (ADER)
"1" is always written to the ADER bit corresponding to the pin used to the analog input.
■ A/D Enable Register (ADER)
ADERH low byte
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ADE23
ADE22
ADE21
ADE20
ADE19
ADE18
ADE17
ADE16
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
ADE15
R/W
ADE14
R/W
ADE13
R/W
ADE12
R/W
ADE11
R/W
ADE10
R/W
ADE9
R/W
ADE8
R/W
00000000B
ADERL high byte
ADERL low byte
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable/Writable
[ADE23 to ADE0] A/D input enable
ADE
Function
0
General-purpose port [initial value]
1
Analog input
These bits are initialized to "000000H" at reset.
"1" is always written to the analog input enable register of a start channel and an end channel.
568
CHAPTER 22 A/D CONVERTER
22.3.2
A/D Control Status Register (ADCS)
The A/D control status register (ADCS) controls the A/D converter and indicates the A/D
converter status. Do not update the ADCS register during conversion.
■ A/D Control Status Register 1 (ADCS1)
ADCS1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
BUSY
R/W
INT
R/W
INTE
R/W
PAUS
R/W
STS1
R/W
STS0
R/W
STRT
R/W
reserved
R/W
00000000B
R/W: Readable/Writable
[bit7] BUSY (busy flag and stop)
BUSY
Function
Read
This bit is used to indicate A/D converter operation.
This bit is set when A/D conversion starts and cleared when A/D conversion of last
channel ends.
Write
Setting this bit to "0" during A/D operation is forcibly cleared.
This bit is used to forcibly stop operation in continuous during stop conversion
modes.
The bit for indicating A/D operation cannot be set to "1".
RMW instructions always read "1".
In single mode, the bit is cleared after the A/D conversion termination of the last set channel.
In continuous and stop modes, the bit is not cleared before it is set to "0" to stop operation.
This bit is initialized to "0" at reset.
Note:
Do not execute the forced stop and the software activation simultaneously
(BUSY = 0 and STRT = 1).
569
CHAPTER 22 A/D CONVERTER
[bit6] INT (interrupt)
It is set when conversion data is written to the ADCR.
When INTE (bit5) is "1", setting the INT bit will generate an interrupt request.
Writing "0" to this bit clears it.
This bit is initialized to "0" at reset.
When using the DMA, this bit is cleared at end of the DMA transfer.
Note:
Write INT bit to "0" to clear it while the A/D converter is stopped.
[bit5] INTE (interrupt enable)
This bit is used to enable or disable interrupts at the end of conversion.
INTE
Function
0
Interrupt disabled (initial value)
1
Interruption enabled
This bit is initialized to "0" at reset.
[bit4] PAUS (A/D converter pause)
This bit is set when A/D conversion stops temporarily.
Because there is only one register to store the A/D conversion results, the conversion results must be
transferred by the DMA when continuous conversion, otherwise the previous data item will be
overwritten.
To protect the previous data item. the next conversion data item is not stored until the data register
contents are transferred by the DMA. A/D conversion is suspended during this time.
A/D conversion restarts when DMA transfer ends.
This bit is valid only when the DMA is used.
- This bit can be cleared by writing "0" to it.
(This bit is not cleared at the end of the DMA transfer)
- However, this bit cannot be cleared at the DMA transfer wait state.
- See "22.4 Operation of A/D Converter" for the converted data protection function.
- This bit is initialized to "0" at reset.
570
CHAPTER 22 A/D CONVERTER
[bit3, bit2] STS1, STS0 (Start source select)
These bits are initialized to "00B"at reset.
The A/D start source is selected by setting of these bits.
STS1
STS0
Function
0
0
Software activation [initial value]
0
1
External pin trigger activation or software activation
1
0
16-bit reload timer activation or software activation
1
1
External pin trigger activation, 16-bit reload timer activation, or software
activation
For modes that enable multiple start sources, the A/D converter is activated by the first of these sources.
Because these bits are rewritten when the start source changes, exercise caution when changing the start
source during A/D converter operation.
- For the external pin trigger, the falling edge is detected. If the external trigger input level is the "L"
level, the A/D converter can be activated when this bit is rewritten to set external pin trigger
activation.
- Selecting the timer selects the 16-bit reload timer 2.
[bit1] STRT (Start)
Setting this bit to "1" activates the A/D converter (software activation).
To restart the A/D converter, set this bit to "1" again.
This bit is initialized to "0" at reset.
In continuous mode and stop mode, the operating function cannot be restarted. Check the BUSY bit
before writing "1" to this bit. (Activate after clearing the BUSY bit.)
Do not execute the forced stop and the software activation simultaneously (BUSY=0 and STRT=1).
[bit0] Reserved bit
"0" is always set to this bit.
571
CHAPTER 22 A/D CONVERTER
■ A/D Control Status Register 0 (ADCS0)
ADCS0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
MD1
R/W
MD0
R/W
S10
R/W
ACH4
R
ACH3
R
ACH2
R
ACH1
R
ACH0
R
00000000B
R/W: Readable/Writable
R:
Read only
[bit7, bit6] MD1, MD0 (A/D converter mode set)
These bits are used to set the operation mode.
These bits are initialized to "00B" at reset.
MD1
MD0
Operating mode
0
0
Single mode. Restarts are disabled during operation. [initial value]
0
1
Single mode. Restarts are disabled during operation.
1
0
Continuous mode. Restarts are disabled during operation.
1
1
Stop mode. Restarts are disabled during operation.
• Single mode:
A/D conversion is continuously performed for the channels set by ANS4 to ANS0 up to the channels
set by ANE4 to ANE0, and the conversion stops when the conversion of all channel ends.
• Continuous mode:
A/D conversion is performed repeatedly and continuously for the channels set by ANS4 to ANS0 up
to the channels set by ANE4 to ANE0.
• Stop mode:
A/D conversion is performed for the channels set by ANS4 to ANS0 up to the channels set by ANE4
to ANE0, but operation stops temporarily for each channel. The A/D conversion is restarted by the
start source generation.
• When A/D conversion is activated in continuous and stop mode, the conversion operation continues
until being stopped by the BUSY bit forcibly.
• To stop the conversion operation forcibly, set the BUSY bit to "0".
• The A/D conversion is performed from the channels set by ANS4 to ANS0 at the activation after
forced stop.
• A/D conversion cannot be restarted in single, continuous, or stop mode when the timer, external
trigger, or a software interrupt have been selected for activating the A/D converter.
Note:
If the A/D conversion mode selection bit (MD1, MD0) is set to "00B", a restart can be performed
during A/D conversion.
Only the software activation (STS1, STS0=00B) can be set in this mode. Follow the procedure below
to restart A/D conversion:
(1) Clear the INT bit to "0".
(2) Write "1" to the STRT bit and "0" to the INT bit simultaneously.
572
CHAPTER 22 A/D CONVERTER
[bit5] S10
This bit specifies the resolution of the conversion. When setting this bit to "0", the 10-bit A/D conversion
is performed. Otherwise, the 8-bit A/D conversion is performed, and its result is stored in the ADCR0.
This bit is initialized to "0" at reset.
[bit4 to bit0] ACH4 to ACH0 (Analog convert select channel)
These bits indicate the channel while the A/D conversion is in progress.
These bits are initialized to ''00000B" at reset.
ACH4
ACH3
ACH2
ACH1
ACH0
Channel
0
0
0
0
0
AN0
0
0
0
0
1
AN1
0
0
0
1
0
AN2
0
0
0
1
1
AN3
0
0
1
0
0
AN4
0
0
1
0
1
AN5
0
0
1
1
0
AN6
0
0
1
1
1
AN7
0
1
0
0
0
AN8
0
1
0
0
1
AN9
0
1
0
1
0
AN10
0
1
0
1
1
AN11
0
1
1
0
0
AN12
0
1
1
0
1
AN13
0
1
1
1
0
AN14
0
1
1
1
1
AN15
1
0
0
0
0
AN16
1
0
0
0
1
AN17
1
0
0
1
0
AN18
1
0
0
1
1
AN19
1
0
1
0
0
AN20
1
0
1
0
1
AN21
1
0
1
1
0
AN22
1
0
1
1
1
AN23
573
CHAPTER 22 A/D CONVERTER
ACH
Function
Read
During the A/D conversion (BUSY bit=1), current conversion channel is indicated by
these bits.
When stopped by forced stop (BUSY bit=0), the channel that the conversion is
stopped is indicated.
Write
Writing to these bits are invalid.
Note:
Writing to the register other than the set value described in the table is disabled.
574
CHAPTER 22 A/D CONVERTER
22.3.3
Data Register (ADCR1, ADCR0)
The data register (ADCR0, ADCR1) is used to store digital value generated as a result of
conversion. The ADCR0 stores the lower 8 bits, and ADCR1 stores the most significant
2 bits of the conversion result. These register values are rewritten every time
conversion ends. Last converted value is stored in these registers normally.
■ Data Register (ADCR1, ADCR0)
ADCR1
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
-
-
-
-
-
-
D9
D9
000000XXB
-
-
-
-
-
-
R
R
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D7
R
D6
R
D5
R
D4
R
D3
R
D2
R
D1
R
D0
R
XXXXXXXXB
ADCR0
R:
X:
Read only
Undefined
"000000B" is always read from bits 15 to 10 of the ADCR1.
These bits can use the converted data protection function. See "22.4 Operation of A/D Converter".
575
CHAPTER 22 A/D CONVERTER
22.3.4
Conversion Time Setting Register (ADCT)
The A/D conversion time setting register (ADCT) controls the sampling time and
comparison time of the analog input. The A/D conversion time is set by setting of the
ADCT register.
Do not rewrite the ADCT register during A/D conversion.
■ Conversion Time Setting Register
ADCT1
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00010000B
CT5
CT4
CT3
CT2
CT1
CT0
ST9
ST9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
ST7
R/W
ST6
R/W
ST5
R/W
ST4
R/W
ST3
R/W
ST2
R/W
ST1
R/W
ST0
R/W
00101100B
ADCT0
R/W: Readable/Writable
[bit15 to bit10] CT5 to CT0 (A/D comparison time set)
Setting these bits specifies the clock division value of the comparison operation time.
When set the CT5 to CT0 to "000001B", it becomes no division = CLKP.
Do not set the CT5 to CT0 to "000000B".
These bits are initialized to "000100B" at reset.
Comparison operation time (Compare Time) =
CT set value × CLKP cycle × 10 + (4 × CLKP cycle)
Note:
Set the comparison operation time not exceeding 500µs. The minimum time for comparison is 1.375µs.
[bit9 to bit0] ST9 to ST0 (A/D input sampling time set)
Setting these bits specifies the sampling time of the analog input.
These bits are initialized to "0000101100B" at reset.
Sampling time (Sampling Time) = ST set value × CLKP cycle
The required sampling time and ST set value are calculated in the following formula.
Required sampling time (Tsamp) = (Rext + Rin) × Cin × 7
ST9 to ST0 set values = required sampling time (Tsamp) / CLKP cycle
Set the ST set values so that A/D sampling time is greater than the required sampling time.
576
CHAPTER 22 A/D CONVERTER
Example:
CLKP=32MHz, AVCC ≥ 4.5V, Rext = 200kΩ
Tsamp = (200 × 103 + 2.52 × 103) × 10.7 × 10-12 × 7 = 15.17µs
Set ST = 15.17-6 / 31.25-9 = 485.44 → 486 ("0111100110B") or higher.
Note:
When AVCC is less than 4.5V, set the sampling time at least 1.2µs.
The required sampling time is determined by the Rext so the Rext should be determined by taking
the conversion time into consideration.
■ Recommended Set Value
It is recommended to set the following value to reach appropriate conversion time.
(AVCC ≥ 4.5V, Rext ≤15kΩ)
CLKP (MHz)
Comparison
operation time
(CT5 to CT0)
Sampling time
(ST9 to ST0)
ADCT
set value
Conversion time (µs)
16
000010B
0000010110B
0816H
1.375 + 1.500 = 2.875
24
000011B
0000100001B
0C21H
1.375 + 1.417 = 2.792
32
000100B
0000101100B
102CH
1.375 + 1.375 = 2.750
577
CHAPTER 22 A/D CONVERTER
22.3.5
Start Channel Setting Register (ADSCH)
End Channel Setting Register (ADECH)
The start/end channel setting registers (ADSCH/ADECH) set the start channel and end
channel of the A/D conversion.
Do not rewrite the ADSCH and ADECH registers during A/D conversion.
■ Start Channel Setting Register (ADSCH)
End Channel Setting Register (ADECH)
ADSCH
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
-
-
-
ANS4
ANS3
ANS2
ANS1
ANS0
---00000B
-
-
-
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
ANE4
R/W
ANE3
R/W
ANE2
R/W
ANE1
R/W
ANE0
R/W
---00000B
ADECH
R/W: Readable/Writable
These bits set the start channel and end channel of the A/D conversion.
When the same channels are written to the ANS4 to ANS0 and ANE4 to ANE0, the conversion is
performed for one channel (single channel conversion).
When setting the continuous mode or stop mode, return to the start channels set by the ANS4 to ANS0 after
the conversion of the channels set by these bits ends.
When the set channel is ANS > ANE, the conversion starts from ANS. If the conversion is performed up to
23 channels, it returns to 0 channel and performs up to ANE.
These bits are initialized 0 channel to ANS = 00000B and ANE=00000B at reset.
For example, the channel setting is ANS=6 channels and ANE=3 channels in single mode, the conversion
is performed in the following order:
6 channels →7 channels →8 channels →…→22 channels →23 channels →0 channel →1 channel→
2 channels →3 channels
578
CHAPTER 22 A/D CONVERTER
[bit12 to bit8] ANS4 to ANS0 (A/D start channel set)
[bit4 to bit0] ANE4 to ANE0 (A/D end channel set)
ANS4
ANE4
ANS3
ANE3
ANS2
ANE2
ANS1
ANE1
ANS0
ANE0
0
0
0
0
0
AN0
0
0
0
0
1
AN1
0
0
0
1
0
AN2
0
0
0
1
1
AN3
0
0
1
0
0
AN4
0
0
1
0
1
AN5
0
0
1
1
0
AN6
0
0
1
1
1
AN7
0
1
0
0
0
AN8
0
1
0
0
1
AN9
0
1
0
1
0
AN10
0
1
0
1
1
AN11
0
1
1
0
0
AN12
0
1
1
0
1
AN13
0
1
1
1
0
AN14
0
1
1
1
1
AN15
1
0
0
0
0
AN16
1
0
0
0
1
AN17
1
0
0
1
0
AN18
1
0
0
1
1
AN19
1
0
1
0
0
AN20
1
0
1
0
1
AN21
1
0
1
1
0
AN22
1
0
1
1
1
AN23
1
1
0
0
0
Setting disabled
1
1
0
0
1
Setting disabled
1
1
0
1
0
Setting disabled
1
1
0
1
1
Setting disabled
1
1
1
0
0
Setting disabled
1
1
1
0
1
Setting disabled
1
1
1
1
0
Setting disabled
1
1
1
1
1
Setting disabled
Start/End Channel
579
CHAPTER 22 A/D CONVERTER
22.4
Operation of A/D Converter
The A/D converter operates using the successive comparison method and can select a
10-bit or 8-bit resolution. This section describes the operation modes of the A/D
converter.
■ Analog to Digital Conversion Data
The conversion data register (ADCR0 and ADCR1) is rewritten each time the conversion is completed
because this A/D converter has only one register for storing conversion result (16-bit).
Therefore, it is recommended to convert by transferring the conversion data to memory using DMA since
the A/D converter is not applied to the continuous conversion processing by itself.
■ Single Mode
This mode sequentially converts the analog input specified by the ANS and ANE bits and A/D stops
operation after performing conversion up to the end channel specified by the ANE bit. The conversion
operation for either of channels occurs when the start and end channels are the same (ANS=ANE).
Example
• ANS=00000B, ANE=00011B
Beginning →AN0 →AN1 →AN2 →AN3 →End
• ANS=00010B, ANE=00010B
Beginning →AN2 →End
■ Continuous Mode
This mode sequentially converts the analog input defined by the ANS and ANE bits, returns to the analog
input of ANS after performing the conversion up to the end channel defined by the ANE bit, and continues
the conversion operation. The conversion operation for either of channels is continued if the start and end
channels are the same (ANS=ANE).
Example
• ANS=00000B, ANE=00011B
Beginning →AN0 →AN1 →AN2 →AN3 →AN0 →AN1 (Repeated)
• ANS=00010B, ANE=00010B
Beginning →AN2 →AN2 →AN2 (Repeated)
Continuous conversion mode continues to repeatedly perform conversion until 0 is written to the BUSY bit.
(Write "0" to the BUSY bit →terminate forcibly.) Be careful when you forcibly terminate the operation
because the conversion in progress is stopped before it is completed. (If operation is forcibly terminated,
the conversion register holds the previous data that has been converted.)
580
CHAPTER 22 A/D CONVERTER
■ Stop Mode
This mode sequentially converts the analog input specified by the ANS and ANE bits and temporarily stops
operation each time conversion has been performed for one channel. To clear the temporary stop, start A/D
conversion again.
This mode returns to the analog input of ANS after performing conversion up to the end channel specified
by the ANE bit and then continues the A/D conversion operation.
The conversion operation for either of channels is performed if the start and end channels are the same
(ANS=ANE).
Example
• ANS=00000B, ANE=00011B
Beginning→AN0→Stop→Start →AN1 →Stop→Start →AN2 →Stop→Start→AN3 →Stop→
Start →AN0 →Stop→Start →AN1 (Repeated)
• ANS=00010B, ANE=00010B
Beginning →AN2 →Stop→Start →AN2 →Stop→Start →AN2 (Repeated)
Only start sources specified by STS1 and STS0 are used at this time.
Use this mode to synchronize the beginning of conversion.
Note:
If the A/D conversion mode selection bit (MD1, MD0) is set to "00B", a restart can be performed
during A/D conversion. Only the software activation (STS1, STS0=00B) can be set in this mode.
Follow the procedure below to restart A/D conversion:
(1) Clear the INT bit to "0".
(2) Write "1" to the STRT bit and "0" to the INT bit simultaneously.
581
CHAPTER 22 A/D CONVERTER
582
CHAPTER 23
D/A CONVERTER
This chapter describes the overview of the D/A
converter, the configuration and functions of registers,
and the D/A converter operation.
Note: MB91V280 Only
23.1 Overview of D/A Converter
23.2 Registers of D/A Converter
23.3 Operation of the D/A Converter
583
CHAPTER 23 D/A CONVERTER
23.1
Overview of D/A Converter
This section shows the functions and the block diagram of D/A converter.
■ Functions of D/A Converter
This module is D/A converter which is R-2R type with 10-bit resolution.
D/A converter has two channels.
Output control can be individually executed in two channels by using D/A control register.
■ Block Diagram of the D/A Converter
Figure 23.1-1 shows the block diagram of D/A converter.
Figure 23.1-1 Block Diagram of the D/A Converter
R-bus
DA DA DA DA DA DA DA DA DA DA
19 18 17 16 15 14 13 12 11 10
DA DA DA DA DA DA DA DA DA DA
09 08 07 06 05 04 03 02 01 00
DAVC
DAVC
DA19
DA18
DA17
DA10
DA09
2R R
2R R
2R R
2R R
DAE1
Standby control
DA output
ch.1
584
DA08
DA18
DA00
2R R
2R R
2R R
2R R
DAE0
Standby control
DA output
ch.0
CHAPTER 23 D/A CONVERTER
23.2
Registers of D/A Converter
This section explains the registers used in D/A converter.
■ List of D/A Converter Registers
Figure 23.2-1 shows the list of D/A converter registers.
Figure 23.2-1 List of D/A Converter Registers
DACR
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
-
MODE
R/W
DAE1
R/W
DAE0
R/W
-----000B
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
DA09
R/W
DA08
R/W
------XXB
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
DA07
R/W
DA06
R/W
DA05
R/W
DA04
R/W
DA03
R/W
DA02
R/W
DA00
R/W
DA00
R/W
XXXXXXXXB
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
DA19
R/W
DA18
R/W
-------XXB
DADR0
DADR0
DADR1
DADR1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
DA17
DA16
DA15
DA14
DA13
DA12
DA11
DA10
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
-
-
-
DBL
-------0B
-
-
-
-
-
-
-
R/W
DADBL
R/W: Readable/Writable
X:
Undefined
585
CHAPTER 23 D/A CONVERTER
■ D/A Control Register (DACR)
Figure 23.2-2 shows the bit configuration of D/A control register (DACR).
Figure 23.2-2 Bit Configuration of D/A Control Register (DACR)
DACR
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
-
MODE
R/W
DAE1
R/W
DAE0
R/W
-----000B
R/W: Readable/Writable
X:
Undefined
[bit2] MODE
This bit is used for mode control of D/A converter.
When writing "1" to this bit, D/A converter performs in 8-bit resolution. When writing "0", D/A
converter performs in 10-bit resolution.
This bit is initialized to "0" at a reset. This is enabled to read and write.
[bit1, bit0] DAE1, DAE0
These bits are used to enable or disable D/A converter output. DAE1 bit controls ch.1 output and DAE0
bit controls ch.0 output.
When writing "1" to these bits, D/A output is enabled. When writing "0", D/A output is disabled.
These bits are initialized to "0" at a reset. They are enabled to read and write.
586
CHAPTER 23 D/A CONVERTER
■ D/A Data Register (DADR0, DADR1)
Figure 23.2-3 shows the bit configuration of D/A data registers (DADR0, DADR1).
Figure 23.2-3 Bit Configuration of D/A Data Registers (DADR0,DADR1)
DADR0
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
DA09
R/W
DA08
R/W
------XXB
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
DA07
R/W
DA06
R/W
DA05
R/W
DA04
R/W
DA03
R/W
DA02
R/W
DA00
R/W
DA00
R/W
XXXXXXXXB
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
DA19
R/W
DA18
R/W
-------XXB
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
DA17
R/W
DA16
R/W
DA15
R/W
DA14
R/W
DA13
R/W
DA12
R/W
DA11
R/W
DA10
R/W
XXXXXXXXB
DADR0
DADR1
DADR1
R/W: Readable/Writable
X:
Undefined
[bit9 to bit0] DADR0 registers DA09 to DA00
These bits are used to set the output voltage of D/A converter channel 0.
They are not initialized at a reset. They are enabled to read and write.
[bit9 to bit0] DADR1 registers DA19 to DA10
These bits are used to set the output voltage of D/A converter channel 1.
They are not initialized at a reset. They are enabled to read and write.
When reading these registers in 8-bit resolution mode, the values written as DAx7 to DAx0 are displayed
as DAx9 to DAx2.
587
CHAPTER 23 D/A CONVERTER
■ D/A Clock Control Register (DADBL)
Figure 23.2-4 shows the bit configuration of D/A clock control register (DADBL).
Figure 23.2-4 Bit Configuration of D/A Clock Control Register (DADBL)
DADBL
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
-
-
-
-
-
-
-
DBL
R/W
-------0B
R/W: Readable/Writable
[bit0] DBL
This bit is used for clock control of D/A converter module.
When writing "1" to this bit, clock of D/A converter module is disabled. When setting to "0", clock is
supplied to D/A converter module.
This is initialized to "0" at a reset. This is enabled to read and write.
588
CHAPTER 23 D/A CONVERTER
23.3
Operation of the D/A Converter
This section explains operation overview of D/A converter.
■ Operation Overview of D/A Converter
D/A output is started when D/A output value is written in the D/A data register (DADR) and "1" is set to
corresponding D/A output channel enable bit in the D/A control register (DACR).
If D/A output is disabled, analog switches inserted into the output of each D/A converter channel in series
are turned off. Moreover, the D/A converter is cleared to "0" internally, and path of direct current is cut off.
This is also adapted to stop mode.
■ Theoretical Expressions for D/A Converter Output Voltage
Table 23.3-1 and Table 23.3-2 show the theoretical value of D/A converter output voltage.
The D/A converter output voltage ranges from 0 V to 255/256 × DVR in 8-bit mode and from 0 V to 1023/
1024 × DVR in 10-bit mode. The range of output voltage can be changed by external adjustment of the
DVR voltage.
The D/A converter output contains no internal buffer amplifier. Analog switch (100Ω) is inserted into
output in series, so there is enough setting time when external output load is added.
Table 23.3-1 Theoretical Expressions for D/A Converter Output Voltage in 8-bit Resolution
Setting value of DA07 to DA00
(DA17 to DA10)
Theoretical value of output voltage
00H
DVRL + 0 × 1LSB
01H
DVRL + 1 × 1LSB
02H
DVRL + 2 × 1LSB
...
...
FDH
DVRL + 253 × 1LSB
FEH
DVRL + 254 × 1LSB
FFH
DVRL + 255 × 1LSB
Note: 1LSB=(DVRH - DVRL)/256
589
CHAPTER 23 D/A CONVERTER
Table 23.3-2 Theoretical Expressions for D/A Converter Output Voltage in 10-bit
Resolution
Setting value of DA07 to DA00
(DA17 to DA10)
Theoretical value of output voltage
000H
DVRL + 0 × 1LSB
001H
DVRL + 1 × 1LSB
002H
DVRL + 2 × 1LSB
...
...
3FDH
DVRL + 1021 × 1LSB
3FEH
DVRL + 1022 × 1LSB
3FFH
DVRL + 1023 × 1LSB
Note: 1LSB=(DVRH - DVRL)/1024
590
CHAPTER 24
CLOCK MODULATOR
This chapter describes the register configuration,
function and operation of the clock modulator.
24.1 Overview of Clock Modulator
24.2 Registers of Clock Modulator
591
CHAPTER 24 CLOCK MODULATOR
24.1
Overview of Clock Modulator
This section explains the overview of clock modulator.
■ Overview of Clock Modulator
The clock modulator is intended for the reduction of electromagnetic interference (EMI), by spreading the
spectrum of the clock signal over a wide range of frequencies.
592
CHAPTER 24 CLOCK MODULATOR
24.2
Registers of Clock Modulator
This section explains the register configuration and functions used for clock modulator.
■ Overview of Clock Modulator Register
Clock modulator has the following registers:
• Clock modulator parameter register (CMPR)
• Clock modulator control register (CMCR)
■ Register List
CMPR high byte
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
R
R
MP13
R/W
MP12
R/W
MP11
R/W
MP10
R/W
MP9
R/W
MP8
R/W
00001000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
MP7
R/W
MP6
R/W
MP5
R/W
MP4
R/W
MP3
R/W
MP2
R/W
MP1
R/W
MP0
R/W
11111101B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PHSEL
R/W
R
R/W
R/W
R
RUN
R
EN
R/W
PDX
R/W
00010000B
CMPR low byte
CMCR
R/W: Readable/Writable
R:
Read only
593
CHAPTER 24 CLOCK MODULATOR
24.2.1
Clock Modulator Parameter Register (CMPR)
Clock modulation parameter register (CMPR) is determined the modulation rate in
frequency modulation mode.
■ Clock Modulation Parameter Register (CMPR)
CMPR high byte
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
R
R
MP13
R/W
MP12
R/W
MP11
R/W
MP10
R/W
MP9
R/W
MP8
R/W
00001000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
MP7
R/W
MP6
R/W
MP5
R/W
MP4
R/W
MP3
R/W
MP2
R/W
MP1
R/W
MP0
R/W
11111101B
CMPR low byte
R/W: Readable/Writable
R:
Read only
• Modulation parameter determines the modulation rate and maximum/minimum frequency
modulation clock.
of the
• Setting of modulation parameter is changed by PLL clock frequency. Setting of PLL clock frequency is
consistent in that of parameter.
• Modulation parameter is enabled in frequency modulation mode.
• Change the modulation parameter when modulator is stopped and RUN bit of CMCR is "0".
[bit15, bit14] Reserved
Reserved bits: Reading value is always "00".
[bit13 to bit0] MP13 to MP0: Modulation parameter
The following modulation parameter is settable by PLL frequency.
594
F0:
Non-modulation input clock frequency (PLL clock frequency)
T0:
Non-modulation input clock cycle (PLL clock cycle)
Resolution:
Frequency resolution of modulation clock (1 to 7)
Fmax:
Maximum frequency generated in modulation clock
Fmin:
Minimum frequency generated in modulation clock
CHAPTER 24 CLOCK MODULATOR
24.2.2
Clock Modulator Control Register (CMCR)
The clock modulator control register (CMCR) has functions of modulator power down
mode setting, modulator operation and stop, phase modulation and frequency
modulation mode selection and modulator state display.
■ Clock Modulator Control Register (CMCR)
CMCR
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PHSEL
R/W
R
R/W
R/W
R
RUN
R
EN
R/W
PDX
R/W
00010000B
R/W: Readable/Writable
R:
Read only
Clock modulator has two operation modes.
• Phase modulation
• Frequency modulation
[bit7] PHSEL: Phase modulation mode select bit
PHSEL
Phase modulation mode select
0
Frequency modulation mode [initial value]
1
Phase modulation mode
Be sure to change PHSEL during clock modulation stop (when EN bit is "0"). If changing during clock
modulation operation, it may cause malfunction.
[bit6 to bit3] Reserved
Reserved bits
Be sure to set "0010B".
[bit2] RUN: Modulator status bit
RUN
Modulator status
0
CPU operates in non-modulation clock. [initial value]
1
CPU operates in modulation clock.
• This bit shows the state of modulator output clock in frequency modulation mode (PHSEL=0). When
output clock frequency is modulated, this bit is set to "1". When it is not modulated, this bit is set to
"0".
• This bit is always "0" in phase modulation mode.
595
CHAPTER 24 CLOCK MODULATOR
Oscillation frequency (F0)
Correcting time
4MHz
64.00 µs
5MHz
51.20 µs
6MHz
42.67 µs
Correcting time = 256/F0
• At normal operation, do not change to non-modulation clock which correction completes.
• To switch the synchronization of EN signal and that to non-modulation clock, the minimum time of
9 × T0 (input clock cycle) is passed before this bit changes to "0". The clock is switched to nonmodulation clock after the modulator operation is stopped.
• This bit is read only. Write is invalid.
[bit1] EN: Clock modulation operation enable bit
EN
Clock modulation operation enable
0
Clock modulation operation stopped [initial value]
1
Clock modulation operation enabled
• When this bit is set to "1", modulator is enabled to operate.
• Enable the modulation operation after PLL supply stabilization clock (after PLL lock time passed).
• PLL clock frequency used in frequency modulation mode is 15 MHz to 25 MHz.
• Be sure to stop modulator before changing of PLL clock frequency and PLL stop.
• The EN bit is set to "1" and the modulator is corrected after setting in the frequency modulation mode.
The clock outputted at this time is non-modulation clock. Therefore, time of several µs is required
when the output clock switches to the modulation clock until the RUN bit is set to "1". This
correction time depends on the frequency of the external oscillator.
[bit0] PDX: Power down mode bit
PDX
Power down mode
0
Power down mode [initial value]
1
Normal operating mode
• This bit is power down mode bit of frequency modulation.
• Before starting modulation operation, set this bit to "1" and switch from power down mode to normal
operation mode. At this time, waiting time of 6 µs is required as starting time.
• Before switching to power down mode, be sure to stop modulator.
596
CHAPTER 25
CLOCK SUPERVISOR
This chapter explains clock supervisor's function.
25.1 Overview of Clock Supervisor
25.2 Clock Supervisor Control Register (CSVCR)
25.3 Clock Supervisor Operation
597
CHAPTER 25 CLOCK SUPERVISOR
25.1
Overview of Clock Supervisor
This section explains clock supervisor's function overview.
■ Overview of Clock Supervisor
The clock supervisor provides the following functions.
• If the leading edge of the main oscillation clock is not detected in 4 cycles of the built-in CR oscillation
clock, the clock supervisor will detect an oscillation problem. Any longer main oscillation cycle than
this period (TRC(TYP) ≤TMAIN/4) will be considered as an oscillation problem. When the MCU operates
on the sub clock, this period represents 32 cycles of the CR oscillation clock.
• The main oscillation, the sub oscillation, and the CR oscillation can individually stop oscillating.
• When any problem is detected in the sub clock at main oscillation operation, the execution of MCU
initialization depends on the set value of the control bit.
• Both the main and sub oscillation supervision functions are automatically activated or deactivated by the
oscillation control signal from MCU.
• Upon suspension of external oscillation in STOP mode, built-in CR oscillation will automatically halt.
When MCU is returned from the STOP mode, the oscillation is restarted.
598
CHAPTER 25 CLOCK SUPERVISOR
25.2
Clock Supervisor Control Register (CSVCR)
The clock supervisor control register (CSVCR) sets the clock supervisor's operation
mode.
■ Clock Supervisor Control Register (CSVCR)
CSVCR
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
R/W
MM
R
SM
R
RCE
R/W
MSVE
R/W
SSVE
R/W
SRST
R/W
R/W
0001XX00B
R/W: Readable/Writable
R:
Read only
X:
Undefined
[bit7] Reserved
Reserved bit.
Be sure to set this bit to "0".
[bit6] MM: Main oscillation miss detection flag
MM
The main oscillation miss detection
0
No miss detection of the main oscillation [initial value]
1
Miss detection of the main oscillation
When the main oscillation supervision function detects a main oscillation problem due to the failure of
the crystal oscillator, this bit will be set at "1". "0" means a normal operating.
Only this bit is for read, and write is invalid. The reset input (INITX=0) from an external terminal
initializes this bit. Reset factors within the MCU (software reset, watchdog reset) will not cause the
initialization.
[bit5] SM: Sub oscillation miss detection flag
SM
Sub oscillation miss detection
0
No miss detection of sub oscillation [initial value]
1
Miss detection of sub oscillation
When the sub oscillation supervision function detects a sub oscillation problem due to the failure of the
crystal oscillator, this bit will be set at "1". "0" means a normal operating.
This bit is only for read, and write is invalid. The reset input (INITX=0) from an external terminal
initializes this bit. Reset factors within the MCU (software reset, watchdog reset) will not cause the
initialization.
599
CHAPTER 25 CLOCK SUPERVISOR
[bit4] RCE: CR oscillation enable bit
RCE
CR oscillation enable
0
Built-in CR oscillation stop
1
Built-in CR oscillation operating [initial value]
Built-in CR oscillation operates when this bit is set to "1". Be sure to set this bit to "1" when either of
main or sub oscillation supervision is active.
First halt the main and sub supervision function and then ensure that both the MM and SM bits are "0"
before setting this bit to "0".
The reset input (INITX=0) from an external terminal initializes this bit to "1". Reset factors within the
MCU (software reset, watchdog reset) will not cause the initialization.
[bit3] MSVE: Main oscillation supervisor enable bit
MSVE
Main oscillation supervisor operating
0
Main oscillation supervisor stop
1
Main oscillation supervisor operating
Setting this bit to "1" enables the supervision function of the main oscillation clock. Ensure that the RCE
bit is "1" before enabling the supervision function by writing "1". When the RCE bit is "0", set the RCE
bit to "1" leaving the MSVE bit as "0", and then set the MSVE bit to "1" after a lapse of oscillation start
time (10 µs or longer) for built-in CR oscillation.
Note:
MSVE bit cannot be initialized by any reset factor. Whether the main oscillation supervision function
is used or not, be sure to set it to "1" (enabled) or "0" (disabled).
[bit2] SSVE: Sub oscillation supervisor enable bit
SSVE
Sub oscillation supervisor operating
0
Sub oscillation supervisor stop
1
Sub oscillation supervisor operating
Setting this bit to "1" enables the supervision function of the sub oscillation clock. Ensure that the RCE
bit is "1" before enabling the supervision function by writing "1". When the RCE bit is "0", set the RCE
bit to "1" leaving the SSVE bit as "0", and then set the SSVE bit to "1" after a lapse of oscillation start
time (10 µs or longer) for built-in CR oscillation.
Note:
SSVE bit cannot be initialized by any reset factor. Whether the sub oscillation supervision function is
used or not, be sure to set it to "1" (enabled) or "0" (disabled).
600
CHAPTER 25 CLOCK SUPERVISOR
[bit1] SRST: Sub clock mode reset bit
Reserved bit.
Be sure to set this bit to "0".
[bit0] Reserved
Reserved bit.
Be sure to set this bit to "0".
601
CHAPTER 25 CLOCK SUPERVISOR
25.3
Clock Supervisor Operation
This section explains the operation of clock supervisor.
■ Operation in Initial State
• Built-in CR oscillation is operating.
• If the MSVE bit is "1" after a lapse of stability latency time for main oscillation, the main oscillation
supervision function will be enabled. When any oscillation problem is detected before a lapse of
oscillation stability latency time, the function will be enabled after the latency time is secured by the CR
oscillation clock. When the oscillator has any problem at power-on, issue of the reset signal will
continue to keep the device in reset status.
• If the SSVE bit is "1" after a lapse of stability latency time by the built-in CR oscillation clock, the sub
oscillation supervision function will be enabled.
■ CR Oscillation and Operation Stop of Clock Supervisor Function
• When the RCE bit (bit4 of CSVCR) is set to "0", built-in CR oscillation stops oscillating. Never halt CR
oscillation while either of the main or sub oscillation supervision function is active. First halt the
oscillation supervision function and then ensure that both the MM and SM bits are "0" before stopping
CR oscillation. Please do not stop the CR oscillation when either of bits is set to "1".
• The main oscillation supervisor function stops when the MSVE bit (bit3 of CSVCR) is set to "0".
• The sub oscillation supervisor function stops when the SSVE bit (bit2 of CSVCR) is set to "0".
■ CR Oscillation and Reactivation of Clock Supervisor Function
• If the RCE bit (bit4 of CSVCR1) is set to "1" while CR oscillation is halted, oscillation operation will
resume. Please secure the oscillation stability waiting time after it reactivates with software.
• If the MSVE bit (bit3 of CSVCR1) is set to "1" while the main oscillation supervision function is halted,
this function will be enabled. A lapse of the oscillation stability latency time (10 µs) or longer from the
beginning of CR oscillation operation is required before this bit is set to "1".
• If the MSVE bit (bit2 of CSVCR1) is set to "1" while the sub oscillation supervision function is halted,
this function will be enabled. A lapse of the oscillation stability latency time (10 µs) or longer from the
beginning of CR oscillation operation is required before this bit is set to "1".
■ Sub Clock Mode
In sub clock mode, the main oscillation supervision function is inactive while the set value for the MSVE
bit (bit3 of CSVCR1) will be retained. On this account, the supervision function will be enabled after a
lapse of latency time for main oscillation stability following the transition to main clock mode.
■ STOP Mode
In STOP mode, CR oscillation operation and the main and sub oscillation supervision function
automatically halt. The operation enable bits (RCE, MSVE, SSVE) corresponding to the CSVCR retain
their set value, and therefore the device will resume operation after recovery from STOP mode.
In this case, after it returns from the STOP mode, the CR oscillation immediately restarts operating.
The main oscillation supervision function will resume operation after a lapse of latency time for main
oscillation stability. If main oscillation is halted after recovery from STOP mode, replacement by the CR
oscillation clock will take place.
The sub oscillation supervision function will resume operation after a lapse of latency time secured by the
CR oscillation clock.
When the bits corresponding to CR oscillation operation and oscillation supervision functions are set to "0",
it will remain inactive even after recovery from STOP mode.
602
CHAPTER 25 CLOCK SUPERVISOR
■ Confirmation of Clock Supervisor Reset
Read the INIT bit of the reset factor register (RSRR) and the CSVCR's MM and SM bits through software
to determine that the reset factor of the MCU is due to clock supervisor reset. The value and the reset factor
of each flag are indicated in Table 25.3-1.
Table 25.3-1 Reset Factor
Register
RSRR
CSVCR
HWDCS
Address
000480H
0004ADH
0005FDH
Bit
INIT
MM
SM
CPUF
Bit position
bit7
bit6
bit5
bit0
1
1
X
0
Main oscillation stop
1
X
1
0
Sub oscillation stop
1
0
0
1
Hardware watchdog
1
0
0
0
External INIT input
Reset Factor*
*: For hardware watchdog reset and other reset factors, see the corresponding chapters.
603
CHAPTER 25 CLOCK SUPERVISOR
604
CHAPTER 26
FLASH MEMORY
This chapter provides an outline of flash memory and
explains its register configuration, register functions,
and operations.
26.1 Outline of Flash Memory
26.2 Flash Memory Registers
26.3 Explanation of Flash Memory Operation
26.4 Automatic Algorithm of Flash Memory
26.5 Writing to and Erasing from Flash Memory
26.6 Wild Register
26.7 Notes on Flash Memory Programming
605
CHAPTER 26 FLASH MEMORY
26.1
Outline of Flash Memory
This series contains 512KB (MB91F273(S)/MB91F278(S)) flash memory.
The internal flash memory operates on a single power supply voltage of 3.3V. The
internal flash memory can be erased by sector, batch-erased (all sectors erased), and
written in halfword (16 bits) units via the FR-CPU.
■ Outline of Flash Memory
The flash memory employed is an internal flash memory that operates on 3.3V. The flash memory
employed here is the same as the Fujitsu flash memory MBM29LV400C (except for the capacity and sector
configuration) and supports writing using a device-external ROM writer. Along with this manual, refer to
the MBM29LV400C Data Sheet.
When this memory is used as FR-CPU internal ROM, it becomes possible to read instructions and data in
word units (32 bits), in addition to features equivalent to the features of the MBM29LV400C. This enables
high-speed device operation.
This product supports the following features by combining a built-in flash memory and FR-CPU interface
circuits:
• Features for use as CPU memory, for storing programs and data
(hereafter referred to as CPU mode)
- Accessibility through 32-bit bus when used as ROM
- Allowing read, write, and erase (automatic program algorithm*) by the CPU
• Features of a single flash memory product equivalent to MBM29LV400C
(hereafter referred to as FLASH mode)
- Allowing read, write, and erase (automatic program algorithm*) by a ROM writer
This section explains usage of the flash memory accessed from the FR-CPU.
For information on using the flash memory accessed from a ROM writer, see the instruction manual
provided with the ROM writer.
Reference:
*: Automatic program algorithm (Embedded AlgorithmTM)
Embedded AlgorithmTM is a trademark of Advanced Micro Devices, Inc.
606
CHAPTER 26 FLASH MEMORY
■ Block Diagram of Flash Memory
Figure 26.1-1 shows a block diagram of the flash memory.
Figure 26.1-1 Block Diagram of Flash Memory
RDY/BUSYX
Detection of rising edge
Generation of
control signal
RESETX
BYEX
OEX
FLASH memory
WEX
RDY
Bus control signal
CEX
WE
FA18 to FA0
DI15 to
DI0
Address buffer
DO15 to
DO0
Data buffer
FD31 to
FD0
FA18 to
FA0
FR F-bus (instruction/data)
■ Memory Map of Flash Memory
The flash memory employs different address mapping depending on whether accessed in flash memory
mode or CPU mode.
Figure 26.1-2 shows the mapping for access in flash memory mode and CPU mode.
Figure 26.1-2 Memory Mapping of Flash Memory (MB91F273(S)/MB91F278(S))
FLASH memory mode
CPU mode
0000_0000H
0008_0000H
I/O, etc.
0008_0000H
32-bit
8-bit / 16-bit
512K bytes
FLASH
0010_0000H
512K bytes
FLASH
000F_FFFFH
FFFF_FFFFH
607
CHAPTER 26 FLASH MEMORY
■ Sector Address Table of Flash Memory
● Sector map of flash memory (512KB)
• Read/write mode in halfword, read mode in byte
15
0
FLASH
mode
CPU mode
15
0
FLASH
mode
CPU mode
Sector 6
16KB
BFFFFH
BC000H
FFFFCH
F8000H
Sector 13
16KB
FFFFFH
FC000H
FFFFEH
F8002H
Sector 5
8KB
BBFFFH
BA000H
F7FFCH
F4000H
Sector 12
8KB
FBFFFH
FA000H
F7FFEH
F4002H
Sector 4
8KB
B9FFFH
B8000H
F3FFCH
F0000H
Sector 11
8KB
F9FFFH
F8000H
F3FFEH
F0002H
Sector 3
32KB
B7FFFH
B0000H
EFFFCH
E0000H
Sector 10
32KB
F7FFFH
F0000H
EFFFEH
E0002H
Sector 2
64KB
AFFFFH
A0000H
DFFFCH
C0000H
Sector 9
64KB
EFFFFH
E0000H
DFFFEH
C0002H
Sector 1
64KB
9FFFFH
90000H
BFFFCH
A0000H
Sector 8
64KB
DFFFFH
D0000H
BFFFEH
A0002H
Sector 0
64KB
8FFFFH
80000H
9FFFCH
80000H
Sector 7
64KB
CFFFFH
C0000H
9FFFEH
80002H
• Read mode in word (32 bits)
31
608
16
15
0
CPU mode
Sector 6
16KB
Sector 13
16KB
FFFFFH
F8000H
Sector 5
8KB
Sector 12
8KB
F7FFFH
F4000H
Sector 4
8KB
Sector 11
8KB
F3FFFH
F0000H
Sector 3
32KB
Sector 10
32KB
EFFFFH
E0000H
Sector 2
64KB
Sector 9
64KB
DFFFFH
C0000H
Sector 1
64KB
Sector 8
64KB
BFFFFH
A0000H
Sector 0
64KB
Sector 7
64KB
9FFFFH
80000H
CHAPTER 26 FLASH MEMORY
26.2
Flash Memory Registers
This section explains the configuration and functions of the registers used by the flash
memory.
■ List of Flash Memory Registers
The flash memory has the following two registers.
• FLCR: Flash Control/Status Register (CPU mode)
• FLWC: Flash Memory Wait Register
FLCR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
007000H
R/W
R/W
R/W
R
RDY
R
R/W
WE
R/W
R/W
01X0X000B
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
007004H
R
R/W
FAC1
R/W
FAC0
R/W
R/W
WTC2
R/W
WTC1
R/W
WTC0
R/W
00000011B
FLWC
R/W: Readable/Writable
R:
Read only
X:
Undefined
609
CHAPTER 26 FLASH MEMORY
26.2.1
FLASH Control/Status Registers (FLCR)
The flash control/status register (FLCR) indicates the operation status of the flash
memory.
The FLCR register controls writing to the flash memory. The FLCR register can be
accessed only in CPU mode. Do not use read modify write instruction to access this
register.
■ Bit Configuration of Flash Control/Status Register (FLCR)
The following shows the bit configuration of FLCR.
FLCR
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
007000H
R/W
R/W
R/W
R
RDY
R
R/W
WE
R/W
R/W
01X0X000B
R/W: Readable/Writable
R:
Read only
X:
Undefined
[bit7 to bit5] Reserved: Reserved bit
Reserved bits.
Be sure to set these bits to "011B".
[bit4] Reserved: Reserved bit
Reserved bit.
The bit is initialized to "0" at a reset.
[bit3] RDY: Ready
This bit indicates the operation status of the automatic algorithm (write/erase).
When this bit is set to "0", writing or erasure is in progress with the automatic algorithm and no Write
and Erase command can be accepted. Moreover, data cannot be read from any address in flash memory.
The read data indicates the flash memory status as listed in the table below.
RDY
Function
0
While writing or erasing is in process, flash memory is not ready to accept a new
Write/Erase command, and no data can be read from a flash memory address.
1
Flash memory is ready to accept a new Write/Erase command and data can be read
from a flash memory address.
• This bit is not initialized during a reset. (The value of this bit depends on the flash memory status).
• Only read operation is possible, but write operation does not affect this bit.
[bit2] Reserved: Reserved bit
Reserved bit.
Be sure to set this bit to "0".
610
CHAPTER 26 FLASH MEMORY
[bit1] WE: Write Enable
This bit controls the writing of data and commands to flash memory in CPU mode.
When this bit is set to "0", writing data and commands to flash memory is disabled.
When WE=1, writing data and commands to flash memory is enabled and automatic algorithm can be
started.
If this bit is rewritten, confirm that the RDY bit has stopped the automatic algorithm (write/erase). When
the RDY bit is set to "0", the value of this bit cannot be changed.
Writing is enabled regardless of this bit in flash memory mode.
WE
Function
0
Writing to flash memory is disabled. [initial value]
1
Writing to flash memory is enabled.
• This bit is initialized to "0" during reset.
• Read and write operations are enabled.
[bit0] Reserved: Reserved bit
Reserved bit.
Be sure to set this bit to "0".
611
CHAPTER 26 FLASH MEMORY
26.2.2
Wait Register (FLWC)
The wait register (FLWC) controls the wait status of the flash memory in CPU mode.
■ Bit Configuration of Wait Register (FLWC)
The following shows the bit configuration of flash memory wait register (FLWC).
FLWC
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
007004H
R
R/W
FAC1
R/W
FAC0
R/W
R/W
WTC2
R/W
WTC1
R/W
WTC0
R/W
00000011B
R/W: Readable/Writable
R:
Read only
[bit7, bit6] Reserved: Reserved bits
Reserved bits.
Be sure to set these bits to "00B".
[bit5, bit4] FAC1 and FAC0: Access control bits
These bits set to control the internal pulse generation of the flash control. These bits set ATDIN/EQIN
pulse width.
FAC1
FAC0
0
0
0.5 clock
1.0 clock
0
1
1.0 clock
1.5 clock
1
0
1.5 clocks
2.0 clocks
1
1
2.0 clocks
2.5 clocks
[bit3] Reserved: Reserved bit
Reserved bit.
Be sure to set this bit to "0".
612
ATDIN
EQIN
[Initial value]
CHAPTER 26 FLASH MEMORY
[bit2 to bit0] WTC2, WTC1, and WTC0: wait cycle bits
WTC2
WTC1
WTC0
Wait cycle
Read
Programming
0
0
0
-
Setting disabled
Setting disabled
0
0
1
1
to 32MHz is enable.
Setting disabled
0
1
0
2
to 32MHz is enable.
Setting disabled
0
1
1
3
to 32MHz is enable.
to 32MHz is enable. [Initial value]
1
0
0
4
Setting disabled
Setting disabled
1
0
1
5
Setting disabled
Setting disabled
1
1
0
6
Setting disabled
Setting disabled
1
1
1
7
Setting disabled
Setting disabled
• Be initialized to " 011B" when resetting.
• Set within the cycle specified by FAC1 and FAC0 bits.
• The initial value is set for write access. At reading (WE bit in FLCR is "0"), the high-speed setting can
be performed (WTC[2:0]=001B or 010B).
613
CHAPTER 26 FLASH MEMORY
26.3
Explanation of Flash Memory Operation
This section explains operation of the flash memory.
■ Flash Memory Access Modes
The following two types of access mode are available for the FR-CPU:
• ROM mode:
One word (32 bits) can be read but not written in a single cycle.
• Programming mode:
Access to data with a length defined in words (32 bits) is prohibited but writing data with a length
defined in half-words (16 bits) is enabled.
■ FR-CPU ROM Mode (32 Bits, Read Only)
In this mode, the flash memory serves as FR-CPU internal ROM. This mode enables to read one word (32
bits) in one cycle but does not enable to write to the flash memory or to start the automatic algorithm.
• Mode specification
- When specifying this mode, set the "WE" bit of the flash control/status register to "0".
- This mode is always set after a reset occurs at CPU run time.
- This mode can be set only when the CPU is running.
• Detailed operation
In this mode, one word (32 bits) can be read from the flash memory area in one cycle.
• Restrictions
- Address assignment and endians in this mode differ from those for writing with the ROM writer.
- In this mode, commands and data cannot be written to the flash memory together.
■ FR-CPU Programming Mode (16 Bits, Read/Write)
This mode enables data to be written and erased. As one word (32 bits) cannot be accessed in one cycle,
program execution in flash memory is disabled in this mode.
• Mode specification
- When specifying this mode, set the "WE" bit of the flash control/status register to "1".
- After a reset occurs at CPU run time, the "WE" bit indicates "0". When setting this mode, set the
"WE" bit to "1". If the "WE" bit is set again to "0" through a writing operation or because of a reset,
the device enters ROM mode.
- When the "RDY" bit of the flash control/status register is "0", the "WE" bit cannot be rewritten.
When rewriting the "WE" bit, ensure that the "RDY" bit is set to "1".
• Detailed operation
- One half-word (16 bits) can be read from the flash memory area in one cycle.
- The automatic algorithm can be started by writing a command to flash memory. When the automatic
algorithm starts, data can be written to or erased from flash memory. For details on the automatic
algorithm, see "26.4 Automatic Algorithm of Flash Memory".
• Restrictions
- Address assignment and endians in this mode differ from those for writing with the ROM writer.
- This mode inhibits reading data in words (32 bits).
614
CHAPTER 26 FLASH MEMORY
■ Automatic Algorithm Execution Status
When the automatic algorithm is started in CPU programming mode, the operation status of the automatic
algorithm can be checked using the internal ready/busy signal (RDY/BUSYX). The level of this signal can
be read as the RDY bit in the flash control/status register.
When the RDY bit is set to "0", data is being written or erased with the automatic algorithm, and no write
or erase command can be accepted. Moreover, data cannot be read from any address in flash memory.
Data read with the RDY bit set to "0" is a hardware sequence flag to indicate flash memory status.
615
CHAPTER 26 FLASH MEMORY
26.4
Automatic Algorithm of Flash Memory
This section describes the command sequence of the flash memory automatic
algorithm, the method used to check the operation status of the automatic algorithm,
and writing to and erasing from flash memory.
■ Overview of Flash Memory Automatic Algorithm
The flash memory automatic algorithm can be started using a Read/Reset, Write, Chip Erase, or Sector
Erase command. The Sector Erase command can stop and restart the automatic algorithm.
616
CHAPTER 26 FLASH MEMORY
26.4.1
Command Sequence
This section explains the command sequence for starting the automatic algorithm.
■ Command Sequence of Automatic Algorithm
At the start of the automatic algorithm, one to six half-words (16 bits) are written to flash memory
continuously. This data is called the command.
If the address and data to be written are invalid or are written in an incorrect sequence, the flash memory is
reset to read mode.
Table 26.4-1 lists commands that can be used to write data to or erase data from flash memory.
When writing data using FR-CPU, write data with half-words (16 bits). (The table lists the addresses in
CPU mode.)
Table 26.4-1 Command Sequence Table
Command
sequence
Bus
write
cycle
First bus write
cycle
Second bus write
cycle
Third bus write
cycle
Fourth bus write
cycle
Fifth bus write
cycle
Sixth bus write
cycle
FMA
DIN
DMA
DIN
FMA
DIN
FMA
DIN
FMA
DIN
FMA
DIN
Read/ Reset
1
XXXXH
F0H
--
--
--
--
--
--
--
--
--
--
Read/ Reset
4
D5557H
AAH
CAAABH
55H
D5557H
F0H
RA
RD
--
--
--
--
Write
4
D5557H
AAH
CAAABH
55H
D5557H
A0H
PA
PD
--
--
--
--
Chip Erase
6
D5557H
AAH
CAAABH
55H
D5557H
80H
D5557H
AAH
CAAABH
55H
D5557H
10H
Sector Erase
6
D5557H
AAH
CAAABH
55H
D5557H
80H
D5557H
AAH
CAAABH
55H
SA
30H
Sector Erase Suspend
Input of address "FXXXXXH" and data (XXB0H) suspends the sector erase operation.
Sector erase resume
Input of address "FXXXXXH" and data (XX30H) resumes the suspended sector erase operation.
RA: Read address
PA: Writing address
SA: Sector address
RD: Read data
■ Read/Reset Command
Set flash memory into Read/Reset mode. The flash memory remains in reading state until another
command is entered. When the power is turned on, flash memory is automatically set to the read or reset
mode. In this case, data can be read without a command of the automatic algorithm.
Upon returning to read mode after the time limit is exceeded, note that a Read/Reset command sequence
can be issued. Data is read from the flash memory in the next read cycle.
617
CHAPTER 26 FLASH MEMORY
■ Program (Write)
In CPU programming mode, data is basically written in half-word units. The write operation is performed
in four cycles of bus operation. The command sequence has two "unlock" cycles, which are followed by a
write Setup command and a write data cycle. Writing to memory starts in the last write cycle.
After an automatic write algorithm command sequence was executed, it becomes unnecessary to control the
flash memory externally.
The flash memory itself internally generates write pulses to check the margin of the cells to which data is
written. The data polling function compares bit7 of the original data with bit7 of the written data, and if
these bits are the same, the automatic write operation ends (see "■ Hardware sequence flag" in "26.4.2
Check the Execution State of Automatic Algorithm"). The automatic write operation then returns to the
read mode and accepts no more write addresses. After that, the flash memory requests the next valid
address. In this manner, the data polling function indicates a write operation in memory.
During a write operation, all commands written to the flash memory are ignored. If a hardware reset starts
during write operation, the data at the address for writing may become invalid.
Writing operations can be performed in any address sequence and outside of sector boundaries. However,
write operations cannot change a data item "0" to "1". If a "0" is overwritten with a "1", the data polling
algorithm either determines that the elements are defective, or that "1" seems to have been written. In the
latter case, however, the respective data item is read as "0" in reset or read mode. A data item "0" can be
changed to "1" only after an erase operation.
■ Chip Erase
The Chip Erase command sequence ("erase all sectors simultaneously") is executed in six access cycles.
First, two "unlock" cycles are executed, then a "Setup" command is written. After two more "unlock"
cycles, the Chip Erase command is entered.
During the Chip Erase command sequence, the user does not need to write to the flash memory before the
erase operation. When the automatic erase algorithm is executed, the flash memory checks cell states by
writing a pattern of zeros before automatically erasing the contents of all cells (preprogram). In this
operation, the flash memory does not need to be controlled externally.
The automatic erase operation starts with the write operation of the command sequence and ends when bit7
is set to "1", where the flash memory returns to the read mode. The chip erase time can be expressed as
follows: time for sector erase × number of all sectors + time for writing to the chip (preprogram).
618
CHAPTER 26 FLASH MEMORY
■ Sector Erasing
The Sector Erase command sequence is executed in six access cycles. First, two "unlock" cycles are
executed, then a "setup" command is written.
After two more "unlock" cycles, the Sector Erase command is entered in the sixth cycle for starting the
sector erase operation.
The next Sector Erase command can be accepted within a time-out period of 50µs after the last Sector
Erase command is written.
As already mentioned, multiple Sector Erase commands can be accepted concurrently during the six bus
cycles of the writing operation. During the command sequence, Sector Erase commands (30H) for sectors
whose contents are to be erased simultaneously are written consecutively to the addresses for these sectors.
The sector erase operation itself starts from the end of the time-out period of 50µs after the last Sector
Erase command is written. When the contents of multiple sectors are erased simultaneously, the subsequent
Sector Erase commands must be input within the 50µs time-out period to ensure that they are accepted. For
checking whether the succeeding Sector Erase command is valid, read bit3 (see "■ Hardware sequence
flag" in "26.4.2 Check the Execution State of Automatic Algorithm").
During the time-out period, any command other than Sector Erase and Temporarily Stop Erase is reset at
read time, and the preceding command sequence is ignored. In the case of the Temporary Stop Erase
command, the contents of the sector are erased again and the erase operation is completed.
Any combination and number of sector addresses can be entered in the sector erase buffers.
The user does not need to write to the flash memory before the sector erase operation. The flash memory
writes to all cells in a sector whose data is automatically erased (preprogram). When the contents of a
sector are erased, the other sectors remain intact. In these operations, the flash memory does not need to be
controlled externally.
The automatic sector erase operation starts from the end of the 50µs time-out period after the last Sector
Erase command is written. When bit7 is set to "1", the automatic sector erase operation ends and flash
memory returns to the read mode. At this time, other commands are ignored.
The data polling function is enabled for any sector address in which data has been erased. The time
required for erasing the data of multiple sectors can be expressed as follows: time for sector erase + time
for sector write (preprogram) × number of erased sectors.
619
CHAPTER 26 FLASH MEMORY
■ Temporarily Stop Erase
The Temporarily Stop Erase command temporarily stops the automatic algorithm in the flash memory
when the user is erasing the data of a sector, thereby making it possible to write data to and read data from
the other sectors. This command is valid only during the sector erase operation and ignored during chip
erase and write operations.
The Temporarily Stop Erase command (B0H) is effective only during sector erasure operation that includes
the sector erase time-out period after a Sector Erase command (30H) is issued. When this command is
entered within the time-out period, waiting for time-out ends and the erase operation is suspended. The
erase operation is restarted when a Restart Erase command was written. Temporarily Stop Erase and
Restart Erase commands can be entered with any address.
When a Temporarily Stop Erase command is entered during sector erase operation, the flash memory needs
a maximum of 20µs to stop the erase operation. When the flash memory enters temporary erase stop mode,
a Ready or Busy signal and bit7 output "1", and bit6 stops to toggle. For checking whether the erase
operation has stopped, enter the address of the sector whose data is being erased and read the values of bit6
and bit7. At this time, another Temporarily Stop Erase command entry is ignored.
When the erase operation stops, the flash memory enters the temporary erase stop and read mode. Data
reading is enabled in this mode for sectors that are not subject to temporary erase stop. Other than that,
there is no difference from the standard read operation. In this mode, bit2 toggles for consecutive reading
operations from sectors subject to temporary erase stop.
After the temporary erase stop and read mode is entered, the user can write to flash memory by writing a
Write command sequence. The write mode in this case is the temporary erase stop and write mode. In this
mode, data write operations become valid for sectors that are not subject to temporary erase stop. Other
than that, there is no difference from the standard byte writing operation. In this mode, bit2 toggles for
consecutive reading operations from sectors that are subject to temporary erase stop. The temporary erase
stop bit (bit6) can be used to detect this operation.
Note that bit6 can be read from any address, but bit7 must be read from write addresses.
To restart the sector erase operation, a Restart Erase command (30H) must be entered. Another Restart
Erase command entry is ignored in this case. On the other hand, a Temporarily Stop Erase command can be
entered after flash memory restarts the erase operation.
620
CHAPTER 26 FLASH MEMORY
26.4.2
Check the Execution State of Automatic Algorithm
The flash memory is provided with hardware to indicate the internal operation status of
the flash memory and the completion of write/erase operations in the automatic
algorithm.
The following two hardware sequence flags for the automatic algorithm can be used to
check the operation status of the flash memory:
■ Ready/Busy Signal (RDY/BUSYX)
The flash memory uses the Ready/Busy signal in addition to the hardware sequence flag to indicate
whether the internal automatic algorithm is running.
The Ready/Busy signal is transmitted to the flash memory interface circuit, where it can be read via the
"RDY" bit of the flash memory status register.
When the read value of the "RDY" bit is "0", the flash memory is executing a write or erase operation,
where new Write and Erase commands are not accepted. When the read value of the "RDY" bit is "1", the
flash memory is in read/write or erase operation wait state.
■ Hardware Sequence Flag
The following shows the structure of the hardware sequence flag.
bit15
During half-word read
87
(Undefined)
0
Hardware sequence flag
bit7
During byte read
(from odd address only)
(In half-word and byte
access)
0
Hardware sequence flag
DPOLL
TOGGLE TLOVER Undefined SETIMER TOGGL2 Undefined Undefined
Note:
Reading in units of words is disabled. Always use FR-CPU programming mode.
For obtaining the hardware sequence flag as data, read an arbitrary address (an odd address in byte access)
from the flash memory when the automatic algorithm is executed. The data contains five validity bits which
indicate the status of the automatic algorithm.
The hardware sequence flag becomes invalid in FR-CPU ROM mode. Always use it in FR-CPU
programming mode and read only in half-words or bytes.
621
CHAPTER 26 FLASH MEMORY
Table 26.4-2 shows the status of the hardware sequence flag.
Table 26.4-2 Status of the Hardware Sequence Flag
State
DPOLL
TOGGLE
TLOVER
SETIMR
TOGGL2
Reverse data
Toggle
0
0
1
0
Toggle
0
1
Toggle
Temporary
erase stop
and read
(from sectors
in temporary
erase stop)
1
1
0
0
Toggle*1
Temporary
erase stop
and read
(from sectors
not in
temporary
erase stop)
Data
Data
Data
Data
Data
Temporary
erase stop
and write (to
sectors in
temporary
erase stop)
Reverse data
Toggle *2
1
0
1 *3
Automatic erase operation
Reverse data
Toggle
1
0
1
Temporary erase stop mode
0
Toggle
1
1
*4
Write operation in temporary
erase stop status
0
Toggle
1
1
*4
Automatic programming
operation
Automatic erase operation
Executing
Temporary
erase stop
mode
Time limit
exceeded
*1: TOGGL2 toggles continuous read operations from sectors in temporary erase stop status.
*2: TOGGLE toggles continuous read operations from any address.
*3: During temporary erase stop status and write operations, TOGGL2 indicates "1" while reading the
address for write operation. However, TOGGL2 toggles continuous read operations from sectors in
temporary erase stop status.
*4: TOGGL2 toggles continuous read operations for sectors under write/erase operation, but does not toggle
read operations for other sectors while TLOVER indicates "1", meaning that the time limit is exceeded.
Each bit listed in the table has the following meaning:
622
[bit7] :DPOLL
: Data polling
[bit6] :TOGGLE
: Toggle bit
[bit5] :TLOVER
: Time limit exceeded
[bit3] :SETIMR
: Sector erase timer
[bit2] :TOGGL2
: Toggle bit 2
CHAPTER 26 FLASH MEMORY
Each bit is briefly described below:
[bit7] DPOLL: Data polling flag
The data polling flag (DPOLL) indicates whether the automatic algorithm is being executed or has been
terminated by using the data polling function.
• Automatic write operation status
When read access is performed while the automatic write algorithm is being executed, the flash
memory outputs the inversion of bit7 of the last data written regardless of the address indicated by
the address signal.
When read access is performed at the end of the automatic write algorithm, the flash memory outputs
bit7 of the read value to the address indicated by the address signal.
• Chip/sector erase operation status
When read access is performed while the erase/sector erase algorithm is being executed for a sector
erase, the flash memory outputs "0" from the sector currently being erased. For a chip erase, the flash
memory outputs "0" regardless of the address indicated by the address signal. In the same way, "1" is
output when it ends.
• Temporary sector erase stop status
When read access is performed during temporary sector erase stop status, the flash memory outputs
"1" when the address indicated by the address signal is included in the sector in erase status.
If the address is not included in the sector in erase status, the flash memory outputs bit7 of the read
value to the address. For checking whether a sector is in temporary sector erase stop status and which
sector is in erase status, read this bit and the toggle bit flag.
Note:
Read access to a specified address is ignored while the automatic algorithm is active. Values can be
output to other bits after data polling flag operation terminates in data read operation.
Therefore, when data is to be read after terminating the automatic algorithm, confirm that data
polling is terminated in the current read access.
[bit6] TOGGLE: Toggle bit flag
Like the data polling flag, the toggle bit flag (DQ6) is a flag that indicates by the toggle bit function that
the automatic algorithm execution is proceeding or ended.
• Write or chip/sector erase operation status
When continuous read operations are performed while the automatic write algorithm or chip/sector
erase algorithm is being executed, the flash memory outputs "1" and "0" by turns toggle results to
bit6 regardless of the address indicated by the address signal.
When continuous read operations are performed at the end of the automatic write algorithm or chip/
sector erase algorithm, the flash memory stops bit6 from toggling and outputs bit6 (DATA: 6) of the
read value from the address indicated by the address signal.
• Temporary sector erase stop status
When a read operation is performed during a temporary sector erase stop operation, the flash
memory outputs "1" if the address indicated by the address signal is included in the sector in erase
state.
If the address is not included in the sector in erase state, the flash memory outputs the data of bit6 of
the read value at the address indicated by the address signal.
623
CHAPTER 26 FLASH MEMORY
Reference:
If a write target sector is protected from rewriting during a write operation, the toggle bit tries to
toggle for about 2µs and stops toggling without changing data. If all selected sectors are protected
from rewriting during erase operation, the toggle bit tries to toggle for about 100µs and the system
returns to read/reset status without changing data.
[bit5] TLOVER: Time limit over flag
This flag is used to report that a time (number of internal pulses) specified internally with flash memory
is exceeded while the automatic algorithm is being executed.
• Write or chip/sector erase operation status
When read access is performed within a specified time (necessary for write or erase) after activating
the automatic write or chip/sector erase algorithm, the flash memory outputs "0". If read access is
performed beyond the specified time, the flash memory outputs "1".
Because these output operations are not affected by whether the automatic algorithm is being
executed or terminated, these operations can be used to check whether write or erase operation is
successful. If the flash memory outputs "1" while the automatic algorithm is being executed with the
data polling function or toggle bit function, consider the write operation to be unsuccessful.
For example, when "1" is written to a flash memory address where "0" is written, failure occurs.
Flash memory is locked and the automatic algorithm is not terminated. There is unusually what
terminates normally like "1" having been written. Thus, valid data is not outputted from the data
polling flag. The toggle bit flag does not stop toggling, the time limit is exceeded, and "1" is
outputted to the TLOVER flag. This status indicates that the flash memory was not used correctly,
not that it was defective. Be sure to execute the reset command if this state appears.
624
CHAPTER 26 FLASH MEMORY
[bit3] SETIMR: Sector erase timer flag
This flag is used to report that sector erasure is being awaited after starting a Sector Erase command.
• Sector erase operation status
When read access is performed within a sector erase wait period after starting a Sector Erase
command, the flash memory outputs "0" regardless of the address indicated by the address signal of
the target sector. If read access is performed beyond the wait period, the flash memory outputs "1"
regardless of the address.
When "1" is set in this flag while the data polling or toggle bit function indicates that the erase
algorithm is being executed, an internally controlled erase operation has started. Any subsequent
commands are ignored except for the write command or erase suspend command for the sector erase
code until erasing finishes.
When this flag is "0", the flash memory accepts another sector erase code entry. In this case, it is
recommended to check the status of this flag by software before writing the succeeding sector erase
code. If this flag is "1" at the second time of status check, the additional sector erase code may not
be accepted.
• Sector erase operation status
When a read operation is performed during a temporary sector erase stop operation, the flash
memory outputs "1" if the address indicated by the address signal is included in the sector that is
subject to the erase operation. If the address is not included in the sector that is subject to the erase
operation, the flash memory outputs the data of bit3 of the read value at the address indicated by the
address signal.
[bit2] TOGGL2: Toggle bit flag 2
Together with toggle bit6, this toggle bit is used with the toggle bit function to report whether the flash
memory is under automatic erase operation or in temporary erase stop status.
• Write or chip/sector erase operation status
This bit toggles the same way as bit2.
• Temporary sector erase stop operation status
When continuous read access is performed from a sector in temporary erase stop status while the
flash memory is in temporary erase stop status and read mode, bit2 toggles.
When continuous read access is performed from a sector not subject to a temporary erase stop
operation while the flash memory is in temporary erase stop status and write mode, bit2 becomes "1".
Unlike bit2, bit6 only toggles in normal write and erase operations, or in temporary erase stop status
and write operation.
Reference:
For example, bit2 and bit6 are used together to detect a temporary erase stop and read mode (bit2
toggles but bit6 does not). Bit2 is also used to detect sectors that are subject to erase operations. If
data is read from a sector that is subject to an erase operation for the flash memory, bit2 toggles.
625
CHAPTER 26 FLASH MEMORY
26.5
Writing to and Erasing from Flash Memory
This section explains how to issue a command to start the automatic algorithm for a
read/reset, write, chip erase, sector erase, temporary sector erase stop, or sector erase
restart operation in flash memory.
■ Writing/Erase
The automatic algorithm can be executed for the following operations in flash memory by executing bus
write cycles for the corresponding command sequence:
• Read/Reset
• Data Writing
• Chip Erase
• Sector Erase
• Temporary Sector Erase Stop
• Sector Erase Restart
The write cycles for each bus must always be executed continuously.
Termination of the automatic algorithm can be checked with the data polling function. Flash memory is set
again into read/reset status after the automatic algorithm terminates normally.
626
CHAPTER 26 FLASH MEMORY
26.5.1
Read/Reset Status
This section explains how to issue Read/Reset commands to set flash memory into
Read/Reset status.
■ Read/Reset Status
The Read/Reset operation becomes possible by continuously sending Read/Reset commands (listed in the
command sequence table) to target sectors in flash memory.
A bus operation is performed one or three times with a Read/Reset command sequence. There is no
essential difference between these two sequences. The read/reset status is the initial status of flash memory,
and when the power supply is turned on, or when the command is normally terminated, the flash memory is
always set to the read/reset status. The read/reset status indicates a waiting status for input from other
commands to be entered.
Under the read/reset status, data can be read using standard read access. The data can be program - accessed
from the CPU same as the mask ROM. The Read/Reset command is not necessary for reading data in
normal read access. This command should be mainly used for initializing the automatic algorithm if the
command has not terminated normally for any reason.
627
CHAPTER 26 FLASH MEMORY
26.5.2
Data Writing
This section explains how to issue a Write command to write data to flash memory.
■ Data Writing
The automatic data write algorithm can be started by continuously sending write commands (listed in the
command sequence table) to target sectors in flash memory.
The automatic algorithm and automatic writing start when writing data to the target address terminates in
the fourth cycle.
■ How to Specify the Address
Only an even-numbered address is acceptable for the write address specified in the data write cycle. If an
odd-numbered address is specified, data cannot be written correctly. In other words, data must be written to
even-numbered addresses in units of half-words.
Data can be written by freely specifying the order of addresses where data is to be written. Moreover, data
can be written beyond sector boundaries. Note that items of data can only be written with each write
command in units of half-words.
■ Notes on Data Programming
Data "0" cannot be returned to data "1" by writing.
If data "1" is overwritten, the data polling algorithm or toggle operation does not terminate, and the flash
memory device is considered defective. An error is assumed with the time limit over flag if the specified
write time is exceeded, or if only data "1" is apparently written, although data "0" is read in read/reset
status. However, if data is read from the flash memory in the read/reset status, data remains "0". Data
"0"can be changed to "1" only by deletion.
All commands are ignored while automatic writing is being performed. When hardware reset is activated
during writing, care must be taken as the data of the address to which writing is carried out is not protected.
■ Write Procedure of Flash Memory
Figure 26.5-1 shows an example of the write procedure.
The status of the automatic algorithm in flash memory can be checked using the hardware sequence flag.
Data polling flag (DPOLL) is used to confirm an end of writing.
Data for the flag check is read from the address where the last data was written.
As the data polling flag (DPOLL) is changed along with the timing limit over flag (TLOVER), you need to
recheck the data polling flag bit (DPOLL) even if the timing limit over flag (TLOVER) is " 1 ".
Likewise, as the toggle bit flag (TOGGLE) terminates the toggle operation just when the timing limit over
flag (TLOVER) changes into "1", you need to recheck the toggle bit flag (TOGGLE).
628
CHAPTER 26 FLASH MEMORY
Figure 26.5-1 Example of Write Procedure (in Flash Memory)
Writing start
Enable writing to FLASH memory
with WE (bit 5) in FLCR.
Write command sequence
D5557H
CAAABH
D5557H
Write address
AAH
55H
A0H
Write data
Read internal address.
Data polling
(DPOLL)
Next address
Data
Data
0
Time limit
(TLOVER)
1
Read internal address.
Data
Data polling
(DPOLL)
Data
Write error
Last address
NO
YES
Disable writing to FLASH memory
with WE (bit 5) in FLCR.
Check hardware
sequence flag
Writing completion
629
CHAPTER 26 FLASH MEMORY
26.5.3
Data Erase (Chip Erase)
This section explains how to issue Chip Erase commands to erase all items of data in
flash memory.
■ Data Erase (Chip Erase)
All items of data can be erased from flash memory by continuously sending Chip Erase commands (listed
in the command sequence table) to target sectors in flash memory.
The chip erase command is executed by executing the bus operation six times.
The operation starts when the sixth write cycle is completed. The user need not write any value to flash
memory before the chip erase operation. During automatic algorithm execution, flash memory verifies by
writing "0" before all cells are erased automatically.
630
CHAPTER 26 FLASH MEMORY
26.5.4
Data Erase (Sector Erase)
This section explains how to issue Sector Erase commands to erase specified sectors
in flash memory. Erasing in sector units is enabled and multiple sectors can be
specified at the same time.
Specified sectors can be erased from flash memory by continuously sending Sector
Erase commands (listed in the command sequence table) to target sectors in flash
memory.
■ Method of Specifying a Sector
The sector erase command is executed in six bus operations. A 50µs sector erase wait period starts when a
sector erase code (30H) is written to an even-numbered address accessible in the target sector in the sixth
cycle. To erase another sector, an erase code (30H) must be written in the same cycle the same way.
■ Note on Specifying a Number of Sectors
A sector erase operation starts when the 50µs sector erase wait period terminates after the final sector erase
code is written. In other words, in order to delete a number of sectors simultaneously, the next deletion
sector address and deletion code (6th cycle of the command sequence) needs to be input within 50µs, and
may not be accepted after that period.
The sector erase timer (hardware sequence flag: SETIMR) can be used to check the validity of a written
sector erase code. The address at which the sector erase command is read should indicate the target sector.
■ Procedure for Deleting a Sector
The hardware sequence flag can be used to check the status of the automatic algorithm in flash memory.
Figure 26.5-2 shows an example of the sector erase procedure.
In this example, the toggle bit flag (TOGGLE) is used to check that erase ends.
Note that data for the flag check is read from the sector to be erased.
The toggle bit flag (TOGGLE) stops toggling simultaneously when the value of the time limit over flag
(TLOVER) changes to "1". Therefore, TOGGLE must be rechecked even though TLOVER is set to "1".
Likewise, as the data polling flag (DPOLL) changes at the moment at which the timing limit over flag
(TLOVER) changes, you need to recheck the data polling flag (DPOLL).
631
CHAPTER 26 FLASH MEMORY
Figure 26.5-2 Example of the Sector Erase Procedure
Erase start
Is value of
sector erase
timer 1 or 0?
Enable erasure in FLASH memory
with WE (bit 5) in FLCR.
1
0
Erase command sequence
AAH
D5557H
CAAABH
55H
D5557H
80H
D5557H
AAH
CAAABH
55H
Enter code (30H) to sector to be erased.
YES
Is there another
sector to be erased?
NO
Internal address read
Internal address read 1
Next sector
Internal address read 2
Toggle bit
(TOGGLE)
data1 = data2 ?
YES
NO
Check with hardware
sequence flag
0
Time limit
(TLOVER)
1
Internal address read 1
Internal address read 2
NO
Toggle bit
(TOGGLE)
data1 = data2 ?
YES
Erase completion
If final sector
erased ?
YES
Disable erasure in FLASH memory
with WE (bit 5) in FLCR.
Erase completion
632
NO
CHAPTER 26 FLASH MEMORY
26.5.5
Temporary Sector Erase Stop
This section explains how to issue Temporary Sector Erase Stop commands to
temporarily stop a sector erase operation in flash memory. Data can be read from the
sector not being erased.
■ Temporary Sector Erase Stop
A sector erase operation in flash memory can be stopped temporarily by continuously sending Temporary
Sector Erase Stop commands (listed in Table 26.4-1) to the target sector in flash memory.
Data can be read from a sector not being erased by using the Temporary Sector Erase Stop command to
temporarily stop the erasure. Data can only be read from the sector; data cannot be written there. This
command is only valid during sector deletion including the waiting time for erasing and is ignored during
chip erasing and during writing.
If the Temporary Sector Erase Stop command is entered during a sector erase wait period, sector erase wait
is finished and the erase operation is stopped, changing to an erase - terminated condition. When a
temporary erase stop command is inputted during the sector erase operation after the sector erase wait
period, the temporary erase stop state is set after a maximum of 20µs. The temporary sector erase stop
command should be used 20µs or more after the sector erase command or the sector erase restart command
has been issued.
633
CHAPTER 26 FLASH MEMORY
26.5.6
Sector Erase Restart
This section explains how to issue Sector Erase Restart commands to restart a
temporarily stopped sector erase operation in the flash memory.
■ Sector Erase Restart
A temporarily stopped sector erase operation can be restarted by continuously sending Sector Erase Restart
commands (listed in Table 26.4-1) to the target sector in the flash memory.
The Sector Erase Restart command is Temporary Sector Erase Stop command. Restart operation starts
when an erase restart code (30H) is written. The address where the erase restart code is written should
indicate an address in the flash memory.
Further, issuing the sector erase restart command is ignored while erasing a sector.
634
CHAPTER 26 FLASH MEMORY
26.6
Wild Register
The wild register function replaces data in internal ROM with arbitrary data.
The combination of address and data to be replaced is referred to as a channel. This
series supports the data replacement of two channels. Replaced data is set in words
(4 bytes).
For details of this function, please contact their FUJITSU representatives.
635
CHAPTER 26 FLASH MEMORY
26.7
Notes on Flash Memory Programming
Notes on programming to flash memory are given below.
■ Notes on Flash Memory Programming
When the flash memory is rewritten using program, note the following content:
• If a reset occurs during rewriting the flash memory, the contents written at a reset are not guaranteed.
• Do not execute program in the flash memory during the flash memory write mode (WE in FLCR
register=1). Under the same condition, do not generate the interrupt when the interrupt vector table is set
in the flash memory. In either case, program is not correctly executed without obtaining the correct
value from the flash memory.
• Termination of writing to the flash memory is checked using both RDY flag and TOGGLE flag.
If the flash memory is defective, program goes into an endless loop only when these two flags are
referred because the RDY flag to indicate the end of write operation is not set.
• Do not transit to the sub-run mode and low-power consumption mode during the flash memory write
mode (WE in FLCR register=1).
636
CHAPTER 27
HARDWARE WATCHDOG
TIMER
This chapter explains the functions of hardware
watchdog timer.
27.1 Overview of Hardware Watchdog Timer
27.2 Configuration of Hardware Watchdog Timer
27.3 Hardware Watchdog Timer Registers
27.4 Function of Hardware Watchdog Timer
27.5 Precautions
637
CHAPTER 27 HARDWARE WATCHDOG TIMER
27.1
Overview of Hardware Watchdog Timer
Hardware watchdog timer issues the reset signal (setting initialization reset) when
internal counter is not cleared for a specified period.
■ Hardware Watchdog Timer
Hardware watchdog timer is a module for CPU operation monitoring. This timer immediately starts countup after setting initialization reset (INIT). This timer must periodically be cleared within a specified period
to continue the program execution. When the counter is not cleared over a specified period, such as
entering to infinite loop, the reset signal is issued. The width of this reset signal is 63 cycles of system base
clock.
Note:
When CPU transfers to the mode which stops operations (standby mode) as follows, the operation of
this module is also stopped.
• SLEEP mode
: CPU stop, peripheral circuit operation
• STOP mode
: CPU and peripheral circuit are stopped.
• RTC mode
: CPU and peripheral circuits except for RTC module are stopped.
Oscillator operation
If one of the following conditions is met, hardware watchdog timer is cleared.
• "0" writing to the CL bit of the HWDCS register
• Reset
• Oscillation stops
• Transfer to SLEEP, STOP or RTC mode
638
CHAPTER 27 HARDWARE WATCHDOG TIMER
27.2
Configuration of Hardware Watchdog Timer
Hardware watchdog timer consists of the following two circuits.
• Watchdog timer
• Hardware watchdog timer control register
■ Block Diagram of Hardware Watchdog Timer
Figure 27.2-1 Block Diagram of Hardware Watchdog Timer
CR clock
Counter
Reset signal
FF
Clear
RESV0 RESV0 RESV0 RESV1
CL
RESV0 RESV0 CPUF
Internal Bus
● Watchdog timer
Timer for monitoring CPU operation. Clear it periodically after reset releasing.
● Hardware watchdog timer control register
This register has a reset flag and a clear bit of timer.
● Reset issue
If the timer is not cleared over a specified period, the hardware watchdog timer module issues the cause of
setting initialization reset (INIT). The width of internal reset signal is 63 cycles of system base clock. For
details of reset sequence, refer to device status.
639
CHAPTER 27 HARDWARE WATCHDOG TIMER
27.3
Hardware Watchdog Timer Registers
Hardware watchdog timer control register has a reset flag and a watchdog timer clear
bit.
■ Hardware Watchdog Timer Control Register
HWDCS
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
RESV0
R/W
RESV0
R/W
RESV0
R/W
RESV1
R/W
CL
W
RESV0
R/W
RESV0
R/W
CPUF
R/W
00011000B
R/W: Readable/Writable
W: Write only
[bit7 to bit5] RESV0: Reserved bits
Reserved bits.
Be sure to set these bits to "000B".
[bit4] RESV1: Reserved bit
Reserved bit.
Be sure to set this bit to "1".
[bit3] CL: Timer clear bit
Watchdog timer clear bit.
Writing "0" to this bit clears the watchdog timer.
Reading value is always "1". Writing "1" is invalid.
[bit2, bit1] RESV0: Reserved bits
Reserved bits.
Be sure to set these bits to "00B".
[bit0] CPUF: CPU reset flag
When overflow is generated in watchdog timer, this bit is set to "1".
Writing "0" clears this bit. Writing "1" is invalid.
External reset input (INIT) and clock supervisor reset initialize this bit, but internal reset (software reset,
etc.) does not initialize it.
640
CHAPTER 27 HARDWARE WATCHDOG TIMER
27.4
Function of Hardware Watchdog Timer
If the watchdog timer is not cleared over a specified period, the setting initialization
reset (INIT) is issued. In this case, the register value of CPU is not guaranteed.
■ Function of Hardware Watchdog Timer
After a reset is released, the hardware watchdog timer immediately starts counting up without waiting the
stabilization time. If the timer is not cleared for a specified time, the setting initialization reset (INIT) is
issued.
■ Cycle of Hardware Watchdog Timer
Bit length of hardware watchdog timer is 16-bit. CR oscillator is used as a clock of a timer, so the cycle has
disparity.
CR oscillation cycle (µs)
Watchdog cycle (ms)
Min
Typ
Max
8.7
10
11.8
569.88
655.36
771.01
641
CHAPTER 27 HARDWARE WATCHDOG TIMER
27.5
Precautions
This section explains the precautions of hardware watchdog timer.
■ Precautions of Hardware Watchdog Timer
● Stop disabled in software
Watchdog timer immediately starts operation after releasing reset. The counting cannot be stopped by
software.
● Reset control
Clear of timer is required to control hardware watchdog reset. When "0" is written to CL bit of hardware
watchdog timer control register, the timer is once cleared and reset issue is controlled.
● Stop and clear of the timer
In the mode which CPU is not operating (SLEEP mode, STOP mode, and RTC mode), the timer is cleared
before transferring such mode and count is stopped.
● Operation during DMA transfer
Writing "0" to the CL bit is disabled during DMA transferring of D-bus module. Therefore, in the case that
DMA transfer time is longer than watchdog cycle, reset is issued. For details of watchdog cycle, refer to
"27.4 Function of Hardware Watchdog Timer".
642
APPENDIX
The appendixes describe the I/O map, interrupt vectors,
and pin states in each CPU state.
APPENDIX A I/O Map
APPENDIX B Interrupt Vector
APPENDIX C Pin States in Each CPU State
APPENDIX D Programming Example of Serial Programming
(Asynchronous)
APPENDIX E Programming Example of Serial Programming
(Synchronous)
643
APPENDIX A I/O Map
APPENDIX A I/O Map
Table A-1 shows the correspondence between the memory space area and the
peripheral resource registers.
■ I/O Map
[Reading the table]
Register
Address
+0
+1
+2
000000H PDR0 [R/W]B PDR1 [R/W]B PDR2 [R/W]B
XXXXXXXX
XXXXXXXX
XXXXXXXX
Block
+3
PDR3 [R/W]B T-unit port
XXXXXXXX data register
Read/write attribute, access unit
(B: byte, H: Halfword,W: Word)
Register initial value after reset
Register name (column 1 of the register is at address 4n,
column 2 is at address 4n + 1...)
Leftmost register address (For word-length access, column 1 of the
register becomes the MSB of the data.)
Note:
The initial values of bits in a register are indicated as follows:
1: Initial value "1"
0: Initial value "0"
X: Initial value "X"
-: A physical register does not exist at the location.
"Reserved" addresses are access-barred.
644
APPENDIX A I/O Map
■ Correspondence Between the Memory Space Area and Peripheral Resource Registers
Table A-1 I/O Map (1 / 16)
Address
000000H
000004H
000008H
00000CH
000010H
000014H
to
00003CH
000040H
000044H
000048H
Register
+0
+1
+2
+3
PDR0 [R/W] B,H
XXXXXXXX
PDR4 [R/W] B,H
XXXXXXXX
PDR8 [R/W] B,H
XXXXXXXX
PDRC [R/W] B,H
XXXXXXXX
PDRG [R/W] B,H
XXXXXXXX
PDR1 [R/W] B,H
XXXXXXXX
PDR5 [R/W] B,H
XXXXXXXX
PDR9 [R/W] B,H
XXXXXXXX
PDRD [R/W] B,H
XXXXXXXX
PDR2 [R/W] B,H
XXXXXXXX
PDR6 [R/W] B,H
XXXXXXXX
PDRA [R/W] B,H
------XX
PDRE [R/W] B,H
XXXXXXXX
PDR3 [R/W] B,H
XXXXXXXX
PDR7 [R/W] B,H
XXXXXXXX
PDRB [R/W] B,H
--XXXXXX
PDRF [R/W] B,H
XXXXXXXX
--
--
--
--
--
--
--
EIRR0 [R/W]
ENIR [R/W]
00000000
00000000
DICR [R/W]
HRCL [R,R/W]
-------0
0--11111
TMRLR0 [W]
XXXXXXXX XXXXXXXX
00004CH
--
000050H
TMRLR1 [W]
XXXXXXXX XXXXXXXX
000054H
--
000058H
TMRLR2 [W]
XXXXXXXX XXXXXXXX
00005CH
000060H
000064H
000068H
00006CH
000070H
000074H
000078H
to
0000ACH
--
--
SCR0 [R,R/W]
00000000
ESCR0 [R/W]
00000100
SCR5 [R,R/W]
00000000
ESCR5 [R/W]
00000100
SCR6 [R,R/W]
00000000
ESCR6 [R/W]
00000100
SMR0 [W,R/W]
00000000
ECCR0 [R,W,R/W]
000000XX
SMR5 [W,R/W]
00000000
ECCR5 [R,W,R/W]
000000XX
SMR6 [W,R/W]
00000000
ECCR6 [R,W,R/W]
000000XX
--
--
ELVR0 [R/W]
00000000 00000000
--
Port Data Registers
(PDRB to PDRG are
for MB91V280.)
Reserved
Ext. INT0 to INT7
--
TMR0 [R]
XXXXXXXX XXXXXXXX
TMCSR0 [R,RW]
00000000 00000000
TMR1 [R]
XXXXXXXX XXXXXXXX
TMCSR1 [R,RW]
00000000 00000000
TMR2 [R]
XXXXXXXX XXXXXXXX
TMCSR2 [R,RW]
00000000 00000000
SSR0 [R,R/W]
RDR0/TRD0 [R/W]
00001000
00000000
BGR10 [R/W]
BGR00 [R/W]
00000000
00000000
SSR5 [R,R/W]
RDR5/TRD5 [R/W]
00001000
00000000
BGR15 [R/W]
BGR05 [R/W]
00000000
00000000
SSR6 [R,R/W]
RDR6/TRD6 [R/W]
00001000
00000000
BGR16 [R/W]
BGR06 [R/W]
00000000
00000000
--
Block
--
DLY / I-Unit
Reload Timer 0
Reload Timer 1
Reload Timer 2
LIN-UART0
LIN-UART5
LIN-UART6
Reserved
645
APPENDIX A I/O Map
Table A-1 I/O Map (2 / 16)
Address
0000B0H
0000B4H
0000B8H
0000BCH
0000C0H
0000C4H
0000C8H
0000CCH
0000D0H
0000D4H
0000D8H
0000DCH
0000E0H
0000E4H
0000E8H
0000ECH
0000F0H
0000F4H
0000F8H
0000FCH
Register
+0
+1
SCR1 [R,R/W]
SMR1 [W,R/W]
00000000
00000000
ESCR1 [R/W]
ECCR1 [R,W,R/W]
00000100
000000XX
SCR2 [R,R/W]
SMR2 [W,R/W]
00000000
00000000
ESCR2 [R/W]
ECCR2 [R,W,R/W]
00000100
000000XX
SCR3 [R,R/W]
SMR3 [W,R/W]
00000000
00000000
ESCR3 [R/W]
ECCR3 [R,W,R/W]
00000100
000000XX
SCR4 [R,R/W]
SMR4 [W,R/W]
00000000
00000000
ESCR4 [R/W]
ECCR4 [R,W,R/W]
00000100
000000XX
EIRR1 [R/W]
ENIR1 [R/W]
00000000
00000000
TCDT0 [R/W] H
00000000 00000000
TCDT1 [R/W] H
00000000 00000000
TCDT2 [R/W] H
00000000 00000000
TCDT3 [R/W] H
00000000 00000000
IPCP1 [R]
XXXXXXXX XXXXXXXX
--
--
IPCP3 [R]
XXXXXXXX XXXXXXXX
--
--
IPCP5 [R]
XXXXXXXX XXXXXXXX
--
--
IPCP7 [R]
XXXXXXXX XXXXXXXX
000100H
--
--
000104H
--
--
000108H
00010CH
000110H
646
OCCP1 [R/W]
XXXXXXXX XXXXXXXX
OCCP3 [R/W]
XXXXXXXX XXXXXXXX
OCS23 [R/W]
11101100 00001100
+2
+3
Block
SSR1 [R,R/W]
RDR1/TRD1 [R/W]
00001000
00000000
LIN-UART1
BGR11 [R/W]
BGR01 [R/W]
00000000
00000000
SSR2 [R,R/W]
RDR2/TRD2 [R/W]
00001000
00000000
LIN-UART2
BGR12 [R/W]
BGR02 [R/W]
00000000
00000000
SSR3 [R,R/W]
RDR3/TRD3 [R/W]
00001000
00000000
LIN-UART3
BGR13 [R/W]
BGR03 [R/W]
00000000
00000000
SSR4 [R,R/W]
RDR4/TRD4 [R/W]
00001000
00000000
LIN-UART4
BGR14 [R/W]
BGR04 [R/W]
00000000
00000000
ELVR1 [R/W]
Ext. INT8 to INT15
00000000 00000000
TCCS0 [R/W] B
-Free-Run Timer 0
00000000
TCCS1 [R/W] B
-Free-Run Timer 1
00000000
TCCS2 [R/W] B
-Free-Run Timer 2
00000000
TCCS3 [R/W] B
-Free-Run Timer 3
00000000
IPCP0 [R]
XXXXXXXX XXXXXXXX
Input Capture Unit
0,1
ICS01 [R/W]
-00000000
IPCP2 [R]
XXXXXXXX XXXXXXXX
Input Capture Unit
2,3
ICS23 [R/W]
-00000000
IPCP4 [R]
XXXXXXXX XXXXXXXX
Input Capture Unit
4,5
ICS45 [R/W]
-00000000
IPCP6 [R]
XXXXXXXX XXXXXXXX
Input Capture Unit
6,7
ICS67 [R/W]
-00000000
--Reserved
OCCP0 [R/W]
OCU1/OCU0
XXXXXXXX XXXXXXXX
OCCP2 [R/W]
OCU3/OCU2
XXXXXXXX XXXXXXXX
OCS01 [R/W]
OCU3 to OCU0 Ctrl.
11101100 00001100
APPENDIX A I/O Map
Table A-1 I/O Map (3 / 16)
Address
000114H
000118H
000110hH
000120H
to
00012CH
000130H
000134H
000138H
00013CH
000140H
000144H
000148H
00014CH
000150H
000154H
000158H
00015CH
000160H
000164H
to
00016CH
000170H
000174H
000178H
00017CH
Register
+0
+1
OCCP5 [R/W]
XXXXXXXX XXXXXXXX
OCCP7 [R/W]
XXXXXXXX XXXXXXXX
OCS67 [R/W]
11101100 00001100
--
--
+2
+3
OCCP4 [R/W]
XXXXXXXX XXXXXXXX
OCCP6 [R/W]
XXXXXXXX XXXXXXXX
OCS45 [R/W]
11101100 00001100
--
--
EIRR2 [R/W]
00000000
EIRR3 [R/W]
00000000
EIRR4 [R/W]
00000000
ENIR2 [R/W]
00000000
ENIR3 [R/W]
00000000
ENIR4 [R/W]
00000000
DACR [R/W]
------000
DADR1 [R/W]
------00 00000000
WTDBL [R/W] B
-------00
ELVR2 [R/W]
00000000 00000000
ELVR3 [R/W]
00000000 00000000
ELVR4 [R/W]
00000000 00000000
DADR0 [R/W]
------00 00000000
DADBL [R/W]
--------0
WTCR [R/W] B,H
00000000 000-00-X
WTBR [R/W] B
----XXXXX XXXXXXXX XXXXXXXX
WTHR [R/W] B,H WTMR [R/W] B,H
WTSR [R/W] B
-XXXXXXXX
XXXXXXXX
--XXXXXXXX
ADERH [R/W]
ADERL [R/W]
00000000 00000000
00000000 00000000
ADCS1 [R/W]
ADCS0 [R,R/W]
ADCR1 [R]
ADCR0 [R]
00000000
00000000
------XX
XXXXXXXX
ADCT1 [R/W]
ADCT0 [R/W]
ADSCH [R/W]
ADECH [R/W]
00010000
00101100
---00000
---00000
CUCR [R/W] B,H,W
CUTD [R/W] B,H,W
-------- ---0--00
10000000 00000000
CUTR1 [R] B,H,W
CUTR2 [R] B,H,W
-------- 00000000
00000000 00000000
--
--
UDRC1 [W] B,H
UDRC0 [W] B,H
00000000
00000000
UDCCH0 [R/W] B,H UDCCL0 [R/W] B,H
00000000
-0000000
UDCCH1 [R/W] B,H UDCCL1 [R/W] B,H
-0000000
-0000000
--
--
Block
OCU5/OCU4
OCU7/OCU6
OCU7 to OCU4 Ctrl.
Reserved
Ext. INT16 to INT23
(MB91V280 only)
Ext. INT24 to INT31
(MB91V280 only)
Ext. INT32 to INT39
(MB91V280 only)
DAC
(MB91V280 only)
Real Time Clock
ADC
Clock Calibration
(MB91V280 and
products without
suffix "S")
--
--
Reserved
UDCR1 [R] B,H
00000000
UDCR0 [R] B,H
00000000
UDCS0 [R/W] B
00000000
UDCS1 [R/W] B
00000000
Up/Down Counter 0/
Up/Down Counter 1
--
Reserved
----
647
APPENDIX A I/O Map
Table A-1 I/O Map (4 / 16)
Address
000180H
000184H
000188H
00018CH
000190H
000194H
000198H
00019CH
0001A0H
0001A4H
0001A8H
Register
+0
+1
UDRC3 [W] B,H
UDRC2 [W] B,H
00000000
00000000
UDCCH2 [R/W] B,H UDCCL2 [R/W] B,H
00000000
-0000000
UDCCH3 [R/W] B,H UDCCL3 [R/W] B,H
-0000000
-0000000
--
--
AD2ERH [R/W]
00000000 00000000
AD2CS1 [R/W]
AD2CS0 [R,R/W]
00000000
00000000
AD2CT1 [R/W]
AD2CT0 [R/W]
00010000
00101100
--
--
CMPR [R/W] B,H
--000010 11111101
CMT1 [R/W] B,H,W
00000000 10000000
CANPRE [R,R/W]
-00000000
Block
+2
+3
UDCR3 [R] B,H
00000000
UDCR2 [R] B,H
00000000
UDCS2 [R/W] B
00000000
UDCS2 [R/W] B
00000000
Up/Down Counter 2/
Up/Down Counter 3
--
Reserved
----
AD2ERL [R/W]
00000000 00000000
AD2CR1 [R]
AD2CR0 [R]
------XX
XXXXXXXX
AD2SCH [R/W]
AD2ECH [R/W]
---00000
---00000
--
--
CMCR [R/W] B,H
-0010000
CMT2 [R/W] B,H,W
00000000 00000000
EISSR [R/W] B,H
00000000 00000000
ADC2
(MB91V280 only)
Reserved
--
Clock Modulator
CAN Clock Presc /
Ext. Int. Source Sel.
0001ACH
--
--
--
--
Reserved
0001B0H
PRLL0 [R/W] B,H,W
XXXXXXXX
PRLL2 [R/W] B,H,W
XXXXXXXX
PPGC1 [R/W] B,H,W
0000000X
PRLH1 [R/W] B,H,W
XXXXXXXX
PRLH3 [R/W] B,H,W
XXXXXXXX
PPGC2 [R/W] B,H,W
0000000X
PRLL1 [R/W] B,H,W
XXXXXXXX
PRLL3 [R/W] B,H,W
XXXXXXXX
PPGC3 [R/W] B,H,W
0000000X
PPG0 to PPG3
0001B8H
PRLH0 [R/W] B,H,W
XXXXXXXX
PRLH2 [R/W] B,H,W
XXXXXXXX
PPGC0 [R/W] B,H,W
0000000X
0001BCH
--
--
--
--
Reserved
0001C0H
PRLL4 [R/W] B,H,W
XXXXXXXX
PRLL6 [R/W] B,H,W
XXXXXXXX
PPGC5 [R/W] B,H,W
0000000X
PRLH5 [R/W] B,H,W
XXXXXXXX
PRLH7 [R/W] B,H,W
XXXXXXXX
PPGC6 [R/W] B,H,W
0000000X
PRLL5 [R/W] B,H,W
XXXXXXXX
PRLL7 [R/W] B,H,W
XXXXXXXX
PPGC7 [R/W] B,H,W
0000000X
PPG4 to PPG7
0001C8H
PRLH4 [R/W] B,H,W
XXXXXXXX
PRLH6 [R/W] B,H,W
XXXXXXXX
PPGC4 [R/W] B,H,W
0000000X
0001CCH
--
--
--
--
Reserved
0001B4H
0001C4H
0001D0H
0001D4H
0001D8H
0001DCH
648
PRLH8 [R/W] B,H,W PRLL8 [R/W] B,H,W PRLH9 [R/W] B,H,W PRLL9 [R/W] B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PRLHA [R/W] B,H,W PRLLA [R/W] B,H,W PRLHB [R/W] B,H,W PRLLB [R/W] B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PPGC8 [R/W] B,H,W PPGC9 [R/W] B,H,W PPGCA [R/W] B,H,W PPGCB [R/W] B,H,W
0000000X
0000000X
0000000X
0000000X
--
--
--
--
PPG8 to PPGB
Reserved
APPENDIX A I/O Map
Table A-1 I/O Map (5 / 16)
Address
0001E0H
0001E4H
0001E8H
0001ECH
0001F0H
0001F4H
0001F8H
0001FCH
Register
+0
--
--
PPGTRG [R/W] B,H,W
00000000 00000000
PPGSWAP [R/W] B
-00000000
CMCLKR [R/W] B
-----0000
--
+3
--
--
--
PPGREVC [R/W] B,H,W
00000000 00000000
000208H
00020CH
000210H
000214H
000218H
00021CH
000220H
000224H
--
--
--
--
PPGC to PPGF
Reserved
PPG0 to PPGF
Enable / Reverse
PPG0 to PPGF
Output Swap
--
--
--
Clock Monitor
--
--
Reserved
--
DMAC
--
DMACR [R/W]
0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX
000240H
Block
--
DMACA0 [R/W]
00000000 00000000 00000000 00000000
DMACB0 [R/W]
00000000 00000000 00000000 00000000
DMACA1 [R/W]
00000000 00000000 00000000 00000000
DMACB1 [R/W]
00000000 00000000 00000000 00000000
DMACA2 [R/W]
00000000 00000000 00000000 00000000
DMACB2 [R/W]
00000000 00000000 00000000 00000000
DMACA3 [R/W]
00000000 00000000 00000000 00000000
DMACB3 [R/W]
00000000 00000000 00000000 00000000
DMACA4 [R/W]
00000000 00000000 00000000 00000000
DMACB4 [R/W]
00000000 00000000 00000000 00000000
000204H
000244H
to
0003ECH
+2
PRLHC [R/W] B,H,W PRLLC [R/W] B,H,W PRLHD [R/W] B,H,W PRLLD [R/W] B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PRLHE [R/W] B,H,W PRLLE [R/W] B,H,W PRLHF [R/W] B,H,W PRLLF [R/W] B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PPGCC [R/W] B,H,W PPGCD [R/W] B,H,W PPGCE [R/W] B,H,W PPGCF [R/W] B,H,W
0000000X
0000000X
0000000X
0000000X
000200H
000228H
to
00023CH
+1
--
Reserved
DMAC
--
Reserved
649
APPENDIX A I/O Map
Table A-1 I/O Map (6 / 16)
Address
0003F0H
0003F4H
0003F8H
0003FCH
000400H
000404H
000408H
00040CH
000410H
000414H
to
00041C0H
000420H
000424H
000428H
00042CH
000430H
000434H
to
00043CH
650
Register
+0
+1
+2
+3
Block
BSD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Bit Search
BSDC [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDR0 [R/W] B,H
DDR1 [R/W] B,H
DDR2 [R/W] B,H
DDR3 [R/W] B,H
00000000
00000000
00000000
00000000
DDR4 [R/W] B,H
DDR5 [R/W] B,H
DDR6 [R/W] B,H
DDR7 [R/W] B,H
Data Direction
00000000
00000000
00000000
00000000
Registers
DDR8 [R/W] B,H
DDR9 [R/W] B,H
DDRA [R/W] B,H DDRB [R/W] B,H
00000000
00000000
------00
--000000
DDRC [R/W] B,H DDRD [R/W] B,H DDRE [R/W] B,H
DDRF [R/W] B,H (DDRB to DDRG are
only for MB91V280.)
00000000
00000000
00000000
00000000
DDRG [R/W] B,H
---00000000
--
--
--
--
PFR0 [R/W] B,H
--00-00PFR4 [R/W] B,H
000000-PFR8 [R/W] B,H
00-00-0PFRC [R/W] B,H
00000000
PFRG [R/W] B,H
00000000
PFR1 [R/W] B,H
00-00--PFR5 [R/W] B,H
-----00PFR9 [R/W] B,H
00000000
PFRD [R/W] B,H
00000000
PFR2 [R/W] B,H
00000000
PFR6 [R/W] B,H
00000000
PFRA [R/W] B,H
------00
PFRE [R/W] B,H
00000000
PFR3 [R/W] B,H
00000-00
PFR7 [R/W] B,H
00-----PFRB [R/W] B,H
--000000
PFRF [R/W] B,H
00000000
--
--
--
--
--
--
--
Reserved
Port Function
Registers
(PFRB to PFRG are
only for MB91V280.)
Reserved
APPENDIX A I/O Map
Table A-1 I/O Map (7 / 16)
Address
Register
Block
+0
+1
+2
+3
ICR00 [R,R/W]
---11111
ICR04 [R,R/W]
---11111
ICR08 [R,R/W]
---11111
ICR12 [R,R/W]
---11111
ICR16 [R,R/W]
---11111
ICR20 [R,R/W]
---11111
ICR24 [R,R/W]
---11111
ICR28 [R,R/W]
---11111
ICR32 [R,R/W]
---11111
ICR36 [R,R/W]
---11111
ICR40 [R,R/W]
---11111
ICR44 [R,R/W]
---11111
ICR01 [R,R/W]
---11111
ICR05 [R,R/W]
---11111
ICR09 [R,R/W]
---11111
ICR13 [R,R/W]
---11111
ICR17 [R,R/W]
---11111
ICR21 [R,R/W]
---11111
ICR25 [R,R/W]
---11111
ICR29 [R,R/W]
---11111
ICR33 [R,R/W]
---11111
ICR37 [R,R/W]
---11111
ICR41 [R,R/W]
---11111
ICR45 [R,R/W]
---11111
ICR02 [R,R/W]
---11111
ICR06 [R,R/W]
---11111
ICR10 [R,R/W]
---11111
ICR14 [R,R/W]
---11111
ICR18 [R,R/W]
---11111
ICR22 [R,R/W]
---11111
ICR26 [R,R/W]
---11111
ICR30 [R,R/W]
---11111
ICR34 [R,R/W]
---11111
ICR38 [R,R/W]
---11111
ICR42 [R,R/W]
---11111
ICR46 [R,R/W]
---11111
ICR03 [R,R/W]
---11111
ICR07 [R,R/W]
---11111
ICR11 [R,R/W]
---11111
ICR15 [R,R/W]
---11111
ICR19 [R,R/W]
---11111
ICR23 [R,R/W]
---11111
ICR27 [R,R/W]
---11111
ICR31 [R,R/W]
---11111
ICR35 [R,R/W]
---11111
ICR39 [R,R/W]
---11111
ICR43 [R,R/W]
---11111
ICR47 [R,R/W]
---11111
Interrupt Control Unit
--
--
--
--
Reserved
000484H
RSRR [R,R/W]
10000000
CLKR [R/W]
00000000
STCR [R/W]
00110011
WPR [W]
XXXXXXXX
CTBR [W]
XXXXXXXX
DIVR1 [R/W]
00000000
000488H
--
--
TBCR [R/W]
00XXXX00
DIVR0 [R/W]
00000011
OSCCR [R/W]
XXXXXXX0
00048CH
--
--
--
--
Reserved
000490H
OSCR [W,R/W]
00000000
--
--
--
Oscillation
stabilization waiter
000494H
to
0004A8H
--
--
--
--
Reserved
0004ACH
--
CSVCR [R/W]
0001XX00
--
--
Clock supervisor
0004B0H
to
0004FCH
--
--
--
--
Reserved
000440H
000444H
000448H
00044CH
000450H
000454H
000458hH
00045CH
000460H
000464H
000468H
00046CH
000470H
to
00047CH
000480H
Clock Control Unit
--
651
APPENDIX A I/O Map
Table A-1 I/O Map (8 / 16)
Address
Register
Block
+0
+1
+2
+3
PPER0 [R/W] B,H
00000000
PPER4 [R/W] B,H
00000000
PPER8 [R/W] B,H
00000000
PPERC [R/W] B,H
00000000
PPERG [R/W] B,H
00000000
PPER1 [R/W] B,H
00000000
PPER5 [R/W] B,H
00000000
PPER9 [R/W] B,H
00000000
PPERD [R/W] B,H
00000000
PPER2 [R/W] B,H
00000000
PPER6 [R/W] B,H
00000000
PPERA [R/W] B,H
------00
PPERE [R/W] B,H
00000000
PPER3 [R/W] B,H
00000000
PPER7 [R/W] B,H
00000000
PPERB [R/W] B,H
--000000
PPERF [R/W] B,H
00000000
--
--
--
--
--
--
--
PPCR0 [R/W] B,H
11111111
PPCR4 [R/W] B,H
----1111
PPCR8 [R/W] B,H
11111111
PPCRC [R/W] B,H
11111111
PPCRG [R/W] B,H
11111111
PPCR1 [R/W] B,H
11111111
PPCR5 [R/W] B,H
--111111
PPCR9 [R/W] B,H
11111111
PPCRD [R/W] B,H
11111111
PPCR2 [R/W] B,H
11111111
PPCR6 [R/W] B,H
11111111
PPCRA [R/W] B,H
------11
PPCRE [R/W] B,H
11111111
PPCR3 [R/W] B,H
11111111
PPCR7 [R/W] B,H
00000000
PPCRB [R/W] B,H
--111111
PPCRF [R/W] B,H
11111111
--
--
--
--
--
--
--
PILR0 [R/W] B,H
00000000
PILR4 [R/W] B,H
00000000
PILR8 [R/W] B,H
00000000
PILRC [R/W] B,H
00000000
PILRG [R/W]
00000000
PILR1 [R/W] B,H
00000000
PILR5 [R/W] B,H
00000000
PILR9 [R/W] B,H
00000000
PILRD [R/W] B,H
00000000
PILR2 [R/W] B,H
00000000
PILR6 [R/W] B,H
00000000
PILRA [R/W] B,H
------00
PILRE [R/W] B,H
00000000
--
--
--
--
--
--
--
Reserved
000564H
IBCR0 [R/W]
00000000
ITMKH0 [R/W,R]
00----11
I2C0
--
ITBAH0 [R/W]
------00
ISMK0 [R/W]
01111111
ICCR0 [R/W]
-0011111
ITBAL0 [R/W]
00000000
ISBA0 [R/W]
-0000000
000568H
IBSR0 [R]
00000000
ITMKL0 [R/W]
11111111
IDAR0 [R/W]
00000000
00056CH
--
--
--
--
000500H
000504H
000508H
00050CH
000510H
000514H
to
00051CH
000520H
000524H
000528H
00052CH
000530H
000534H
to
00053CH
000540H
000544H
000548H
00054CH
000550H
000554H
to
00055CH
000560H
652
Port Pull-up/down
Enable Registers
(PPERB to PPERG
are only for
MB91V280.)
Reserved
Port Pull-up/down
Control Registers
(PPCRB to PPCRG
are only for
MB91V280.)
Reserved
PILR3 [R/W] B,H
00000000
PILR7 [R/W] B,H
Port Input Level
00000000
select Registers
PILRB [R/W] B,H
--000000
(PILRB to PILRG are
PILRF [R/W] B,H
only for MB91V280.)
00000000
-Reserved
APPENDIX A I/O Map
Table A-1 I/O Map (9 / 16)
Address
Register
Block
+0
+1
+2
+3
000574H
IBCR1 [R/W]
00000000
ITMKH1 [R/W,R]
00----11
--
ITBAH1 [R/W]
------00
ISMK1 [R/W]
01111111
ICCR1 [R/W]
-0011111
ITBAL1 [R/W]
00000000
ISBA1 [R/W]
-0000000
000578H
IBSR1 [R]
00000000
ITMKL1 [R/W]
11111111
IDAR1 [R/W]
00000000
00057CH
--
--
--
--
Reserved
000584H
IBCR2 [R/W]
00000000
ITMKH2 [R/W,R]
00----11
I2C2
--
ITBAH2 [R/W]
------00
ISMK2 [R/W]
01111111
ICCR2 [R/W]
00011111
ITBAL2 [R/W]
00000000
ISBA2 [R/W]
-0000000
000588H
IBSR2 [R]
00000000
ITMKL2 [R/W]
11111111
IDAR2 [R/W]
00000000
00058CH
--
--
--
--
Reserved
000590H
to
0005F8H
--
--
--
--
Reserved
0005FCH
--
Hardware Watchdog
000570H
000580H
000600H
000604H
000608H
00060CH
000610H
000614H
to
00061CH
000620hH
000624H
000628H
00062CH
000630H
000634H
to
00063CH
--
--
HWDCS [R/W] B, H
00011000
EPFR1 [R/W] B,H
------0EPFR5 [R/W] B,H
00000000
EPFR9 [R/W] B,H
----0000
EPFRD [R/W] B,H
00000000
--
--
EPFR2 [R/W] B,H
00000000
EPFR6 [R/W] B,H
00000000
EPFRA [R/W] B,H
------00
EPFRE [R/W] B,H
00000000
EPFR3 [R/W] B,H
00000000
EPFR7 [R/W] B,H
00000000
EPFRB [R/W] B,H
--000000
EPFRF [R/W] B,H
00000000
--
--
--
--
--
--
--
PIDR0 [R/W] B,H
XXXXXXXX
PIDR4 [R/W] B,H
XXXXXXXX
PIDR8 [R/W] B,H
XXXXXXXX
PIDRC [R/W] B,H
XXXXXXXX
PIDRG [R/W] B,H
XXXXXXXX
PIDR1 [R/W] B,H
XXXXXXXX
PIDR5 [R/W] B,H
XXXXXXXX
PIDR9 [R/W] B,H
XXXXXXXX
PIDRD [R/W] B,H
XXXXXXXX
PIDR2 [R/W] B,H
XXXXXXXX
PIDR6 [R/W] B,H
XXXXXXXX
PIDRA [R/W] B,H
------XX
PIDRE [R/W] B,H
XXXXXXXX
--
--
--
--
--
--
--
EPFR0 [R/W] B,H
00000000
EPFR4 [R/W] B,H
----00-EPFR8 [R/W] B,H
----0-0EPFRC [R/W] B,H
00000000
EPFRG [R/W] B,H
00000000
I2C1
Extra Port Function
Register
(EPFRB to EPFRG
are only for
MB91V280.)
Reserved
PIDR3 [R/W] B,H
XXXXXXXX
PIDR7 [R/W] B,H Port Input Direct data
XXXXXXXX
Register
PIDRB [R/W] B,H
--XXXXXXXX
(PIDRB to PIDRG
are only for
PIDRF [R/W] B,H
MB91V280.)
XXXXXXXX
Reserved
653
APPENDIX A I/O Map
Table A-1 I/O Map (10 / 16)
Address
000640H
000644H
000648H
00064CH
000650H
to
00065CH
000660H
000664H
Register
+0
+1
+2
ASR0 [R/W]
00000000 00000000
ASR1 [R/W]
XXXXXXXX XXXXXXXX
ASR2 [R/W]
XXXXXXXX XXXXXXXX
ASR3 [R/W]
XXXXXXXX XXXXXXXX
--
+3
Block
ACR0 [R/W]
00110*00 00000000
ACR1 [R/W]
XXXX0X00 00X0XXXX
ACR2 [R/W]
XXXX0X00 00X0XXXX
ACR3 [R/W]
01XX0X00 00X0XXXX
--
--
AWR0 [R/W]
01110000 01011011
AWR2 [R/W]
0XXX0000 XX0X1XXX
--
T-Unit
AWR1 [R/W]
XXXX0000 XX0X1XXX
AWR3 [R/W]
0XXX0000 0X0X1XXX
000668H
to
00067FH
--
--
--
--
000680H
CSER [R/W]
----0001
--
--
--
000684H
to
0007F8H
--
--
--
--
Reserved
0007FCH
--
MODR [W]
XXXXXXXX
--
--
Mode Register
000800H
to
000FFCH
--
--
--
--
Reserved
001000H
--
001004H
--
001008H
--
00100CH
--
001010H
--
001014H
--
001018H
--
00101CH
--
001020H
--
001024H
--
654
DMASA0 [R/W]
----0000 00000000 00000000
DMADA0 [R/W]
----0000 00000000 00000000
DMASA1 [R/W]
----0000 00000000 00000000
DMADA1 [R/W]
----0000 00000000 00000000
DMASA2 [R/W]
----0000 00000000 00000000
DMADA2 [R/W]
----0000 00000000 00000000
DMASA3 [R/W]
----0000 00000000 00000000
DMADA3 [R/W]
----0000 00000000 00000000
DMASA4 [R/W]
00000000 00000000 00000000
DMADA4 [R/W]
00000000 00000000 00000000
DMAC
APPENDIX A I/O Map
Table A-1 I/O Map (11 / 16)
Address
00102BH
to
006FFCH
007000H
0007004H
0007008H
to
01FFFCH
Register
+0
+1
+2
+3
--
--
--
--
--
--
--
--
--
--
--
--
--
FLCR [R/W]
0110X000
FLWC [R/W]
00000011
--
Block
Reserved
FLASH I/F
Reserved
655
APPENDIX A I/O Map
Table A-1 I/O Map (12 / 16)
Address
020000H
020004H
020008H
02000CH
020010H
020014H
020018H
02001CH
020020H
020024H
020030H
to
020034H
020038H
to
02003CH
020040H
020044H
020048H
02004CH
020050H
020054H
020060H
to
020064H
020068H
to
02006CH
020080H
020090H
656
Register
+0
+1
CTRLR0 [R,R/W]
00000000 00000001
ERRCNT0 [R]
00000000 00000000
INTR0 [R]
00000000 00000000
BRPER0 [R,R/W]
00000000 00000000
IF1CREQ0 [R,R/W]
00000000 00000001
IF1MSK20 [R,R/W]
11111111 11111111
IF1ARB20 [R/W]
00000000 00000000
IF1MCTR0 [R,R/W]
00000000 00000000
IF1DTA10 [R/W]
XXXXXXXX XXXXXXXX
IF1DTB10 [R/W]
XXXXXXXX XXXXXXXX
+2
+3
Block
STATR0 [R,R/W]
00000000 00000000
BTR0 [R,R/W]
00100011 00000001
TESTR0 [R,R/W]
00000000 00000000
-IF1CMSK0 [R,R/W]
00000000 00000000
IF1MSK10 [R,R/W]
11111111 11111111
IF1ARB10 [R/W]
00000000 00000000
-IF1DTA20 [R/W]
XXXXXXXX XXXXXXXX
IF1DTB20 [R/W]
XXXXXXXX XXXXXXXX
Reserved (IF1 data mirror, little endian byte ordering)
--
--
IF2CREQ0 [R,R/W]
00000000 00000001
IF2MSK20 [R,R/W]
11111111 11111111
IF2ARB20 [R/W]
00000000 00000000
IF2MCTR0 [R,R/W]
00000000 00000000
IF2DTA10 [R/W]
XXXXXXXX XXXXXXXX
IF2DTB10 [R/W]
XXXXXXXX XXXXXXXX
--
--
IF2CMSK0 [R,R/W]
00000000 00000000
IF2MSK10 [R,R/W]
11111111 11111111
IF2ARB10 [R/W]
00000000 00000000
-IF2DTA20 [R/W]
XXXXXXXX XXXXXXXX
IF2DTB20 [R/W]
XXXXXXXX XXXXXXXX
Reserved (IF2 data mirror, little endian byte ordering)
--
-TREQR20 [R]
00000000 00000000
NEWDT20 [R]
00000000 00000000
--
-TREQR10 [R]
00000000 00000000
NEWDT10 [R]
00000000 00000000
CAN0
APPENDIX A I/O Map
Table A-1 I/O Map (13 / 16)
Address
Register
+0
0200B0H
020100H
020104H
020108H
02010CH
020110H
020114H
020118H
02011CH
020120H
020124H
020130H
to
020134H
020138H
to
02013CH
020140H
020144H
020148H
02014CH
020150H
020154H
020160H
to
020164H
+2
INTPND20 [R]
00000000 00000000
MSGVAL20 [R]
00000000 00000000
0200A0H
0200B4H
to
0200FCH
+1
--
+3
INTPND10 [R]
00000000 00000000
MSGVAL10 [R]
00000000 00000000
--
CTRLR1 [R,R/W]
00000000 00000001
ERRCNT1 [R]
00000000 00000000
INTR1 [R]
00000000 00000000
BRPER1 [R,R/W]
00000000 00000000
IF1CREQ1 [R,R/W]
00000000 00000001
IF1MSK21 [R,R/W]
11111111 11111111
IF1ARB21 [R/W]
00000000 00000000
IF1MCTR1 [R,R/W]
00000000 00000000
IF1DTA11 [R/W]
XXXXXXXX XXXXXXXX
IF1DTB11 [R/W]
XXXXXXXX XXXXXXXX
--
CAN0
--
--
IF2CREQ1 [R,R/W]
00000000 00000001
IF2MSK21 [R,R/W]
11111111 11111111
IF2ARB21 [R/W]
00000000 00000000
IF2MCTR1 [R,R/W]
00000000 00000000
IF2DTA11 [R/W]
XXXXXXXX XXXXXXXX
IF2DTB11 [R/W]
XXXXXXXX XXXXXXXX
Reserved
STATR1 [R,R/W]
00000000 00000000
BTR1 [R,R/W]
00100011 00000001
TESTR1 [R,R/W]
00000000 00000000
-IF1CMSK1 [R,R/W]
00000000 00000000
IF1MSK11 [R,R/W]
11111111 11111111
IF1ARB11 [R/W]
00000000 00000000
-IF1DTA21 [R/W]
XXXXXXXX XXXXXXXX
IF1DTB21 [R/W]
XXXXXXXX XXXXXXXX
Reserved (IF1 data mirror, little endian byte ordering)
--
Block
--
CAN1
(MB91V280 only)
--
IF2CMSK1 [R,R/W]
00000000 00000000
IF2MSK11 [R,R/W]
11111111 11111111
IF2ARB11 [R/W]
00000000 00000000
-IF2DTA21 [R/W]
XXXXXXXX XXXXXXXX
IF2DTB21 [R/W]
XXXXXXXX XXXXXXXX
Reserved (IF2 data mirror, little endian byte ordering)
657
APPENDIX A I/O Map
Table A-1 I/O Map (14 / 16)
Address
020168H
to
02016CH
020180H
020190H
0201A0H
0201B0H
658
Register
+0
+1
+2
+3
--
--
--
--
TREQR21 [R]
00000000 00000000
NEWDT21 [R]
00000000 00000000
INTPND21 [R]
00000000 00000000
MSGVAL21 [R]
00000000 00000000
TREQR11 [R]
00000000 00000000
NEWDT11 [R]
00000000 00000000
INTPND11 [R]
00000000 00000000
MSGVAL11 [R]
00000000 00000000
Block
CAN1
(MB91V280 only)
APPENDIX A I/O Map
Table A-1 I/O Map (15 / 16)
Address
020200H
020204H
020208H
02020CH
020210H
020214H
020218H
02021CH
020220H
020224H
020230H
to
020234H
020238H
to
02023CH
020240H
020244H
020248H
02024CH
020250H
020254H
020260H
to
020264H
020268H
to
02026CH
020280H
020290H
Register
+0
+1
CTRLR2 [R,R/W]
00000000 00000001
ERRCNT2 [R]
00000000 00000000
INTR2 [R]
00000000 00000000
BRPER2 [R,R/W]
00000000 00000000
IF1CREQ2 [R,R/W]
00000000 00000001
IF1MSK22 [R,R/W]
11111111 11111111
IF1ARB22 [R/W]
00000000 00000000
IF1MCTR2 [R,R/W]
00000000 00000000
IF1DTA12 [R/W]
XXXXXXXX XXXXXXXX
IF1DTB12 [R/W]
XXXXXXXX XXXXXXXX
+2
+3
Block
STATR2 [R,R/W]
00000000 00000000
BTR2 [R,R/W]
00100011 00000001
TESTR2 [R,R/W]
00000000 00000000
-IF1CMSK2 [R,R/W]
00000000 00000000
IF1MSK12 [R,R/W]
11111111 11111111
IF1ARB12 [R/W]
00000000 00000000
-IF1DTA22 [R/W]
XXXXXXXX XXXXXXXX
IF1DTB22 [R/W]
XXXXXXXX XXXXXXXX
Reserved (IF1 data mirror, little endian byte ordering)
CAN2
--
--
IF2CREQ2 [R,R/W]
00000000 00000001
IF2MSK22 [R,R/W]
11111111 11111111
IF2ARB22 [R/W]
00000000 00000000
IF2MCTR2 [R,R/W]
00000000 00000000
IF2DTA12 [R/W]
XXXXXXXX XXXXXXXX
IF2DTB12 [R/W]
XXXXXXXX XXXXXXXX
--
--
(MB91V280 only)
IF2CMSK2 [R,R/W]
00000000 00000000
IF2MSK12 [R,R/W]
11111111 11111111
IF2ARB12 [R/W]
00000000 00000000
-IF2DTA22 [R/W]
XXXXXXXX XXXXXXXX
IF2DTB22 [R/W]
XXXXXXXX XXXXXXXX
Reserved (IF2 data mirror, little endian byte ordering)
--
-TREQR22 [R]
00000000 00000000
NEWDT22 [R]
00000000 00000000
--
-TREQR12 [R]
00000000 00000000
NEWDT12 [R]
00000000 00000000
659
APPENDIX A I/O Map
Table A-1 I/O Map (16 / 16)
Address
0202A0H
0202B0H
034000H
to
03FFFCH
03A000H
to
03FFFCH
080000H
to
0FFFFCH
660
Register
+0
+1
+2
INTPND22 [R]
00000000 00000000
MSGVAL22 [R]
00000000 00000000
+3
INTPND12 [R]
00000000 00000000
MSGVA12 [R]
00000000 00000000
Block
CAN2
(MB91V280 only)
-
F-bus RAM
(MB91V280)
-
F-bus RAM
(MB91F273(S)
MB91F278(S))
-
FLASH MEMORY
(MB91F273(S)
MB91F278(S))
APPENDIX B Interrupt Vector
APPENDIX B Interrupt Vector
Table B-1 "Interrupt vector table" shows the interrupt vector table.
The interrupt vector table gives the interrupt sources and interrupt vector/interrupt
control register allocations.
■ Interrupt Vector
Table B-1 Interrupt Vector Table (1 / 3)
Interrupt cause
Interrupt
number
Decimal
Reset
Mode vector
System reservation
System reservation
System reservation
System reservation
System reservation
Coprocessor absent trap
Coprocessor error trap
INTE instruction
System reservation
System reservation
Step trace trap
NMI demand (tool)
Undefined instruction exception
NMI demand
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
External interrupt 7
Reload timer 0
Reload timer 1
Reload timer 2
LIN-UART0 reception
LIN-UART0 transmission
LIN-UART1 reception
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Interrupt level
HexaRegisters
decimal
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
---------------15(FH) fixed
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
Interrupt vector
DMA
Address
Offset
TBR default
address
RN
Stop
----------------440H
441H
442H
443H
444H
445H
446H
447H
448H
449H
44AH
44BH
44CH
44DH
3FCH
3F8H
3F4H
3F0H
3ECH
3E8H
3E4H
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
3C0H
3BCH
3B8H
3B4H
3B0H
3ACH
3A8H
3A4H
3A0H
39CH
398H
394H
390H
38CH
388H
000FFFFCH
000FFFF8H
000FFFF4H
000FFFF0H
000FFFECH
000FFFE8H
000FFFE4H
000FFFE0H
000FFFDCH
000FFFD8H
000FFFD4CH
000FFFD0H
000FFFCCH
000FFFC8H
000FFFC4H
000FFFC0H
000FFFBCH
000FFFB8H
000FFFB4H
000FFFB0H
000FFFACH
000FFFA8H
000FFFA4H
000FFFA0H
000FFF9CH
000FFF98H
000FFF94H
000FFF90H
000FFF8CH
000FFF88H
----------------6
7
------8
9
10
0
3
1
---------------------------Stop
-Stop
661
APPENDIX B Interrupt Vector
Table B-1 Interrupt Vector Table (2 / 3)
Interrupt cause
Interrupt
number
Decimal
Interrupt level
HexaRegisters
decimal
Interrupt vector
DMA
Address
Offset
TBR default
address
RN
Stop
LIN-UART1 transmission
LIN-UART2 reception
LIN-UART2 transmission
CAN0
CAN1/ICU6/ICU7
CAN2
LIN-UART3/UART5 reception
LIN-UART3/UART5
transmission
LIN-UART4/UART6 reception
LIN-UART4/UART6
transmission
30
31
32
33
34
35
36
1E
1F
20
21
22
23
24
ICR14
ICR15
ICR16
ICR17
ICR18
ICR19
ICR20
44EH
44FH
450H
451H
452H
453H
454H
384H
380H
37CH
378H
374H
370H
36CH
000FFF84H
000FFF80H
000FFF7CH
000FFF78H
000FFF74H
000FFF70H
000FFF6CH
4
2
5
-----
-Stop
------
37
25
ICR21
455H
368H
000FFF68H
--
--
38
26
ICR22
456H
364H
000FFF64H
--
--
39
27
ICR23
457H
360H
000FFF60H
--
--
I2C0
40
28
ICR24
458H
35CH
000FFF5CH
--
--
I2C1/UDC2
41
29
ICR25
459H
358H
000FFF58H
--
--
I2C2
A/D converter
RTC
UDC1
Main oscillation stabilization wait
timer
TBT overflow
PPG0/PPG1/PPG4/PPG5
PPG2/PPG3/PPG6/PPG7
PPG8/PPG9/PPGC/PPGD
PPGA/PPGB/PPGE/PPGF
FRT0/FRT1
FRT2/FRT3
ICU0/ICU1/ICU2/ICU3
ICU4/ICU5
OCU0/OCU1/OCU2/OCU3
UDC3
OCU4/OCU5/OCU6/OCU7
UDC0
External interrupt 8 to11
External interrupt 12 to 39
ROM collection interrupt
DMA
Delayed interrupt
System reservation (REALOS)
System reservation (REALOS)
System reservation
42
2A
ICR26
45AH
354H
000FFF54H
--
--
43
44
45
2B
2C
2D
ICR27
ICR28
ICR29
45BH
45CH
45DH
350H
34CH
348H
000FFF50H
000FFF4CH
000FFF48H
14
---
----
46
2E
ICR30
45EH
344H
000FFF44H
--
--
47
48
49
50
51
52
53
54
55
2F
30
31
32
33
34
35
36
37
ICR31
ICR32
ICR33
ICR34
ICR35
ICR36
ICR37
ICR38
ICR39
45F
460H
461H
462H
463H
464H
465H
466H
467H
340H
33CH
338H
334H
330H
32CH
328H
324H
320H
000FFF40H
000FFF3CH
000FFF38H
000FFF34H
000FFF30H
000FFF2CH
000FFF28H
000FFF24H
000FFF20H
----------
----------
56
38
ICR40
468H
31CH
000FFF1CH
--
--
57
58
59
60
61
62
63
64
65
66
39
3A
3B
3C
3D
3E
3F
40
41
42
ICR41
ICR42
ICR43
ICR44
ICR45
ICR46
ICR47
----
469H
46AH
46BH
46CH
46DH
46EH
46FH
318H
314H
310H
30CH
308H
304H
300H
2FCH
2F8H
2F4H
000FFF18H
000FFF14H
000FFF10H
000FFF0CH
000FFF08H
000FFF04H
000FFF00H
000FFEFCH
000FFEF8H
000FFEF4H
-----------
-----------
662
----
APPENDIX B Interrupt Vector
Table B-1 Interrupt Vector Table (3 / 3)
Interrupt cause
Interrupt
number
Decimal
Interrupt level
HexaRegisters
decimal
Interrupt vector
Address
Offset
TBR default
address
2F0H
2ECH
2E8H
2E4H
2E0H
2DCH
2D8H
2D4H
2D0H
2CCH
2C8H
2C4H
2C0H
2BCH
to
000H
000FFEF0H
000FFEECH
000FFEE8H
000FFEE4H
000FFEE0H
000FFEDCH
000FFED8H
000FFED4H
000FFED0H
000FFECCH
000FFEC8H
000FFEC4H
000FFEC0H
000FFEBCH
to
000FFC00H
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
67
68
69
70
71
72
73
74
75
76
77
78
79
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
--------------
--------------
Used in INT instruction
80
to
255
50
to
FF
--
--
DMA
RN
Stop
--------------
--------------
--
--
Note: CAN1, CAN2, and external interrupt 16 to 39 are available only on MB91V280.
663
APPENDIX C Pin States in Each CPU State
APPENDIX C Pin States in Each CPU State
"Table C-1 Explanation of Terms Used in the Pin State Lists" explains the terms used in
the pin state lists. "Table C-2 Pin state at single-chip mode" and "Table C-3 Pin state at
external bus mode" list the pin states in each CPU state.
■ Explanation of Terms Used in the Pin State Lists
"Table C-1 Explanation of Terms Used in the Pin State Lists" explains the terms used for pin states.
Table C-1 Explanation of Terms Used in the Pin State Lists
Term
Input enabled
The input function can be used.
Input cut off
External input is blocked by the input gate immediately after the pin and L is
propagated internally.
Hi-Z output
The pin-driving transistor is set to the drive-disabled state and the pin is set to high
impedance.
Output storage
The output state immediately before this mode is set continues as the output state.
That is, if an output internal peripheral is operating, output is performed based on
the internal peripheral. If output using a port is being performed, that type of
output is maintained.
Retention of the
immediately prior
state
664
Description
For output, the output state immediately before this mode is set continues as the
output state. For input, the previous input state is maintained.
APPENDIX C Pin States in Each CPU State
■ Pin States in Each CPU State
● Single-chip mode
Table C-2 Pin State at Single-chip Mode (1 / 6)
At initialization
Port
name
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
Specified
Internal ROM mode vector
function name Function
(MD2 to MD0=000B)
name
INITX
RST
INT8/
SIN5
INT9/
SOT5
INT10/
SCK5
INT11/
SIN6
INT12/
SOT6
INT13/
SCK6
INT14
INT15
TIN1
TOT1
SIN3/
INT11R
SOT3
SCK3
SIN4
SOT4
SCK4
PPG9
PPGB
PPGD
PPGF
IN0
IN1
IN2
IN3
IN4
IN5
RX2/
INT10R
TX2
OUT4
OUT5
OUT6
OUT7
Sleep mode,
sub sleep
mode
In stop mode,
RTC mode
Remark
HIZ=0
HIZ=1
P00
P01
P02
P03
P04
Retention of
Hi-Z output/ Hi-Z output/ the
input enabled input enabled immediately
prior state
Retention of
the
immediately
prior state
Hi-Z output/
input cut off
Retention of
Hi-Z output/ Hi-Z output/ the
input enabled input enabled immediately
prior state
Retention of
the
immediately
prior state
Hi-Z output/
input cut off
Retention of
Hi-Z output/ Hi-Z output/ the
input enabled input enabled immediately
prior state
Retention of
the
immediately
prior state
Hi-Z output/
input cut off
Retention of
Hi-Z output/ Hi-Z output/ the
input enabled input enabled immediately
prior state
Retention of
the
immediately
prior state
Hi-Z output/
input cut off
*1
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
*1
*1
665
APPENDIX C Pin States in Each CPU State
Table C-2 Pin State at Single-chip Mode (2 / 6)
At initialization
Port
name
Specified
Internal ROM mode vector
function name Function
(MD2 to MD0=000B)
name
INITX
RST
P40
P40
P41
P41
P42
P43
P44
P45
P46
P47
P50
P51
P52
P53
P54
P55
P56
P57
666
RX1/
INT9R
IN7/
TX1
SDA0/
FRCK0
SCL0/
FRCK1/
AIN2
SDA1/
BIN2
SCL1/
ZIN2
AN8/
SIN2
AN9/
SOT2
AN10/
SCK2
AN11/
BIN1
AN12/
AIN1
AN13/
ZIN1
AN14/
DAO0
AN15/
DAO1
Sleep mode,
sub sleep
mode
Retention of
Hi-Z output/ Hi-Z output/ the
input enabled input enabled immediately
prior state
In stop mode,
RTC mode
Remark
HIZ=0
Retention of
the
immediately
prior state
HIZ=1
Hi-Z output/
input cut off
*1
P42
P43
P44
P45
Retention of
Hi-Z output/ Hi-Z output/ the
input enabled input enabled immediately
prior state
Retention of
the
immediately
prior state
Hi-Z output/
input cut off
Retention of
Hi-Z output/ Hi-Z output/ the
input enabled input enabled immediately
prior state
Retention of
the
immediately
prior state
Hi-Z output/
input cut off
P46
P47
P50
P51
P52
P53
P54
P55
P56
P57
APPENDIX C Pin States in Each CPU State
Table C-2 Pin State at Single-chip Mode (3 / 6)
At initialization
Port
name
P60
P61
P62
P63
P64
P65
P66
P67
P70
P71
P72
P73
P74
P75
P76
P77
Specified
Internal ROM mode vector
function name Function
(MD2 to MD0=000B)
name
INITX
RST
AN0/
PPG0
AN1/
PPG2
AN2/
PPG4
AN3/
PPG6
AN4/
PPG8
AN5/
PPGA
AN6/
PPGC
AN7/
PPGE
AN16/
INT0
AN17/
INT1
AN18/
INT2
AN19/
INT3
AN20/
INT4
AN21/
INT5
AN22/
INT6/
SDA2
AN23/
INT7/
SCL2
Sleep mode,
sub sleep
mode
In stop mode,
RTC mode
Remark
HIZ=0
HIZ=1
P60
P61
P62
P63
P64
Retention of
Hi-Z output/ Hi-Z output/ the
input enabled input enabled immediately
prior state
Retention of
the
immediately
prior state
Hi-Z output/
input cut off
Retention of
Hi-Z output/ Hi-Z output/ the
input enabled input enabled immediately
prior state
Retention of
the
immediately
prior state
Hi-Z output/
input cut off
*1
Retention of
Hi-Z output/ Hi-Z output/ the
input enabled input enabled immediately
prior state
Retention of
the
immediately
prior state
Hi-Z output/
input cut off
*1
P65
P66
P67
P70
P71
P72
P73
P74
P75
P76
P77
667
APPENDIX C Pin States in Each CPU State
Table C-2 Pin State at Single-chip Mode (4 / 6)
At initialization
Port
name
P80
P81
P82
P83
P84
P85
P86
P87
P90
P91
P92
P93
P94
P95
P96
P97
PA0
Specified
Internal ROM mode vector
function name Function
(MD2 to MD0=000B)
name
INITX
RST
TIN0/
ADTG/
INT12R
TOT0/
CKOT/
INT13R
SIN0/
TIN2/
INT14R
SOT0/
TOT2
SCK0/
INT15R
SIN1
SOT1
SCK1
PPG1
PPG3/
AIN3
PPG5/
BIN3
PPG7/
BIN3
OUT0/
AIN0
OUT1/
BIN0
OUT2/
ZIN0
OUT3
RX0/
INT8R
Remark
HIZ=0
HIZ=1
P80
P81
P82
P83
*1
Retention of
Hi-Z output/ Hi-Z output/ the
input enabled input enabled immediately
prior state
Retention of
the
immediately
prior state
Hi-Z output/
input cut off
P84
*1
P85
P86
P87
P90
P91
P92
P93
P94
Retention of
Hi-Z output/ Hi-Z output/ the
input enabled input enabled immediately
prior state
Retention of
the
immediately
prior state
Retention of
Hi-Z output/ Hi-Z output/ the
input enabled input enabled immediately
prior state
Retention of
Hi-Z output/ Hi-Z output/ the
input enabled input enabled immediately
prior state
Retention of
the
immediately
prior state
Retention of
the
immediately
prior state
Hi-Z output/
input cut off
P95
P96
P97
PA0
PA1
TX0
PA1
PB0
INT8 to INT2/
SIN5 to SIN2
PB0
668
Sleep mode,
sub sleep
mode
In stop mode,
RTC mode
Hi-Z output/
input cut off
Hi-Z output/
input cut off
*1
*2
APPENDIX C Pin States in Each CPU State
Table C-2 Pin State at Single-chip Mode (5 / 6)
At initialization
Port
name
PB1
PB2
PB3
PB4
PB5
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
Specified
Internal ROM mode vector
function name Function
(MD2 to MD0=000B)
name
INITX
RST
INT9 to INT2/
SOT5 to SOT2
INT10 to INT2/
SCK5 to SCK2
INT11 to INT2/
SIN6 to SIN2
INT12 to INT2/
SOT6 to SOT2
INT13 to INT2/
SCK6 to SCK2
OUT4 to OUT2/
INT0R
OUT5 to OUT2/
INT1R
SIN3 to SIN2/
INT2R
SOT3 to SOT2/
INT3R
SCK3 to SCK2/
INT4R
SIN4 to SIN2/
INT5R
SOT4 to SOT2/
INT6R
SCK4 to SCK2/
INT7R
PPG9 to PPG2/
INT16
PPGB to PPG2/
INT17
PPGD to PPG2/
INT18
PPGF to PPG2/
INT19
IN0 to IN2/
INT20
IN1 to IN2/
INT21
IN2 to IN2/
INT22
IN3 to IN2/
INT23
Sleep mode,
sub sleep
mode
In stop mode,
RTC mode
Remark
HIZ=0
HIZ=1
PB1
PB2
PB3
PB4
Retention of
Hi-Z output/ Hi-Z output/ the
input enabled input enabled immediately
prior state
Retention of
the
immediately
prior state
Hi-Z output/
input cut off
*2
Retention of
Hi-Z output/ Hi-Z output/ the
input enabled input enabled immediately
prior state
Retention of
the
immediately
prior state
Hi-Z output/
input cut off
*1
Retention of
Hi-Z output/ Hi-Z output/ the
input enabled input enabled immediately
prior state
Retention of
the
immediately
prior state
Hi-Z output/
input cut off
*1
Retention of
Hi-Z output/ Hi-Z output/ the
input enabled input enabled immediately
prior state
Retention of
the
immediately
prior state
Hi-Z output/
input cut off
*1
PB5
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
669
APPENDIX C Pin States in Each CPU State
Table C-2 Pin State at Single-chip Mode (6 / 6)
At initialization
Port
name
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
Specified
Internal ROM mode vector
function name Function
(MD2 to MD0=000B)
name
INITX
RST
INT24
INT25
INT26
INT27
INT28
INT29
INT30
INT31
INT32
INT33
INT34
INT35
INT36
INT37
INT38
INT39
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
Sleep mode,
sub sleep
mode
In stop mode,
RTC mode
Remark
HIZ=0
HIZ=1
Retention of
Hi-Z output/ Hi-Z output/ the
input enabled input enabled immediately
prior state
Retention of
the
immediately
prior state
Hi-Z output/
input cut off
*1
Retention of
Hi-Z output/ Hi-Z output/ the
input enabled input enabled immediately
prior state
Retention of
the
immediately
prior state
Hi-Z output/
input cut off
*1
Retention of
Hi-Z output/ Hi-Z output/ the
input enabled input enabled immediately
prior state
Retention of
the
immediately
prior state
Hi-Z output/
input cut off
*1
*1:When the corresponding external interrupt is enabled by ENIR and selected as the external
interrupt input pin by EISSR, it is allowed input and can be used for the return from STOP state.
*2:When the corresponding external interrupt is enabled by ENIR and selected as the external
interrupt input pin by EPFR, it is allowed input and can be used for the return from STOP state.
● External bus Modes
- At the setting initialization (INITX) state, the external bus interface pin is output state. While INIT
pin is "L", these pins are Hi-Z state. While INIT pin is "H", the value shown in Table C-3 is
outputted.
- Port 2, 3, 9, E, and F can disable the external bus interface output by setting EPFR. Table C-3
indicates as follows;
B:External bus interface function state (EPFR=0)
P:General-purpose port or peripheral function state (EPFR=1)
670
APPENDIX C Pin States in Each CPU State
Table C-3 Pin State at External Bus Mode (1 / 9)
In stop mode,
RTC mode
At initialize/reset
Port
Specified
name function name
Initial value
Function External ROM Internal ROM
name mode vector mode vector
(MD2 to
(MD2 to
MD0=001B) MD0=000B)
P00
AD00/
INT8/
SIN5
AD00
P01
AD01/
INT9/
SOT5
AD01
P02
AD02/
INT10/
SCK5
AD02
P03
AD03/
INT11/
SIN6
Sleep
sub sleep
Remark
HIZ=0
HIZ=1
Address output
(MPX)
AD03 Hi-Z output/
input enabled
P04
AD04/
INT12/
SOT6
AD04
P05
AD05/
INT13/
SCK6
AD05
P06
AD06/
INT14
AD06
P07
AD07/
INT15
AD07
P10
AD08/
TIN1
AD08
P11
AD09/
TOT1
AD09
P12
AD10/
SIN3/
INT11R
AD10
P13
AD11/
SOT3
AD11
P14
AD12/
SCK3
AD12
Hi-Z output/
input enabled Hi-Z output/
input enabled
(data)
Same as at
left
Hi-Z output/
input cut off
*1
Same as at
left
Hi-Z output/
input cut off
*1
Address output
(MPX)
Hi-Z output/
input enabled
Hi-Z output/
input enabled Hi-Z output/
input enabled
(data)
671
APPENDIX C Pin States in Each CPU State
Table C-3 Pin State at External Bus Mode (2 / 9)
In stop mode,
RTC mode
At initialize/reset
Port
Specified
name function name
Initial value
Function External ROM Internal ROM
name mode vector mode vector
(MD2 to
(MD2 to
MD0=001B) MD0=000B)
P15
AD13/
SIN4
AD13
P16
AD14/
SOT4
AD14
P17
AD15/
SCK4
AD15
P20
A16/
PPG9
A16
P21
A17/
PPGB
A17
P22
A18/
PPGD
A18
A19/
PPGF
A19
P23
Sleep
sub sleep
Remark
HIZ=0
HIZ=1
Address output
(MPX)
Hi-Z output/
input enabled
Same as at
left
Hi-Z output/
input cut off
Hi-Z output/
Same as at
P:
input enabled
left
Retention of the
immediately
prior state
Hi-Z output/
input cut off
Hi-Z output/
input enabled Hi-Z output/
input enabled
(data)
B:
Address output
P24
A20/
IN0
A20
P25
A21/
IN1
A21
P26
A22/
IN2
A22
P27
A23/
IN3
A23
P30
AS/
IN4
AS
P31
RD/
IN5
FFH
output
*2
*2
RD
P32
WR0/
RX2/
INT10R
WR0
P33
WR1/
TX2
WR1
P34
672
OUT4
Retention of the
Same as at
immediately
left
prior state
"H" output
P34
Hi-Z output/
input enabled
Hi-Z output/
input cut off
*1
*2
*2
Hi-Z output/
input enabled
Retention of
Retention of the
the
immediately
immediately
prior state
prior state
APPENDIX C Pin States in Each CPU State
Table C-3 Pin State at External Bus Mode (3 / 9)
In stop mode,
RTC mode
At initialize/reset
Port
Specified
name function name
P35
Initial value
Function External ROM Internal ROM
name mode vector mode vector
(MD2 to
(MD2 to
MD0=001B) MD0=000B)
Remark
HIZ=0
HIZ=1
Retention of
Retention of the
the
immediately
immediately
prior state
prior state
Hi-Z output/
input enabled
OUT5
Sleep
sub sleep
*2
B:
Hi-Z output
P36
RDY/
OUT6
RDY
Hi-Z output/
input enabled
Same as at
P:
left
Retention of the
Hi-Z output/
immediately
input enabled
prior state
B:
Clock output
P37
SYSCLK/
OUT7
P37
P40
P40
P41
P41
P42
RX1/
INT9R
P42
P43
IN7/
TX1
P43
P44
SDA0/
FRCK0
P44
P45
SCL0 AIN2/
FRCK1
P45
P46
SDA1/
BIN2
P46
P47
SCL1/
ZIN2
P47
Clock output
Hi-Z output/
input cut off
B:
"H" output
P:
P:
Retention of
Retention of the
the
immediately
immediately
prior state
prior state
*2
Same as single-chip mode
673
APPENDIX C Pin States in Each CPU State
Table C-3 Pin State at External Bus Mode (4 / 9)
In stop mode,
RTC mode
At initialize/reset
Port
Specified
name function name
Initial value
Function External ROM Internal ROM
name mode vector mode vector
(MD2 to
(MD2 to
MD0=001B) MD0=000B)
P50
AN8/
SIN2
P50
P51
AN9/
SOT2
P51
P52
AN10/
SCK2
P52
P53
AN11/
BIN1
P53
P54
AN12/
AIN1
P54
P55
AN13/
ZIN1
P55
P56
AN14/
DAO0
P56
P57
AN15/
DAO1
P57
P60
AN0/
PPG0
P60
P61
AN1/
PPG2
P61
P62
AN2/
PPG4
P62
P63
AN3/
PPG6
P63
P64
AN4/
PPG8
P64
P65
AN5/
PPGA
P65
P66
AN6/
PPGC
P66
P67
AN7/
PPGE
P67
Same as single-chip mode
Same as single-chip mode
Same as single-chip mode
Same as single-chip mode
674
Sleep
sub sleep
Remark
HIZ=0
HIZ=1
APPENDIX C Pin States in Each CPU State
Table C-3 Pin State at External Bus Mode (5 / 9)
In stop mode,
RTC mode
At initialize/reset
Port
Specified
name function name
Initial value
Function External ROM Internal ROM
name mode vector mode vector
(MD2 to
(MD2 to
MD0=001B) MD0=000B)
P70
AN16/
INT0
P70
P71
AN17/
INT1
P71
P72
AN18/
INT2
P72
P73
AN19/
INT3
P73
P74
AN20/
INT4
P74
P75
AN21/
INT5
P75
P76
AN22/
INT6/
SDA2
P76
P77
AN23/
INT7/
SCL2
P77
P80
TIN0/
ADTG/
INT12R
P80
P81
TOT0/
CKOT/
INT13R
P81
P82
SIN0/
TIN2/
INT14R
P82
P83
SOT0/
TOT2
P83
P84
SCK0/
INT15R
P84
P85
SIN1
P85
P86
SOT1
P86
P87
SCK1
P87
Sleep
sub sleep
Remark
HIZ=0
HIZ=1
Same as single-chip mode
Same as single-chip mode
Same as single-chip mode
675
APPENDIX C Pin States in Each CPU State
Table C-3 Pin State at External Bus Mode (6 / 9)
In stop mode,
RTC mode
At initialize/reset
Port
Specified
name function name
Initial value
Function External ROM Internal ROM
name mode vector mode vector
(MD2 to
(MD2 to
MD0=001B) MD0=000B)
P90*3
CS0/
PPG1
CS0
P91*3
CS1/
PPG3/
AIN3
CS1
*3
P92
CS2/
PPG5/
BIN3
CS2
P93*3
CS3/
PPG7/
BIN3
CS3
P94*3
OUT0/
AIN0
P94
P95*3
OUT1/
BIN0
P95
P96*3
OUT2/
ZIN0
P96
P97*3
OUT3
P97
PA0*3
RX0/
INT8R
PA0
TX0
PA1
INT8 to INT2/
SIN5 to SIN2
PB0
INT9 to INT2/
PB1*3 SOT5 to SOT2
PB1
INT10 to INT2/
PB2*3 SCK5 to SCK2
PB2
INT11 to INT2/
SIN6 to SIN2
PB3
INT12 to INT2/
PB4*3 SOT6 to SOT2
PB4
INT13 to INT2/
PB5*3 SCK6 to SCK2
PB5
PA1
*3
PB0*3
PB3
676
Remark
HIZ=0
HIZ=1
B:
"H" output
"H" output
Hi-Z output/
Same as at
P:
input enabled
left
Retention of the
immediately
prior state
Same as single-chip mode
Same as single-chip mode
Same as single-chip mode
*3
Sleep
sub sleep
Hi-Z output/
input cut off
*2
APPENDIX C Pin States in Each CPU State
Table C-3 Pin State at External Bus Mode (7 / 9)
In stop mode,
RTC mode
At initialize/reset
Port
Specified
name function name
Initial value
Function External ROM Internal ROM
name mode vector mode vector
(MD2 to
(MD2 to
MD0=001B) MD0=000B)
PC0*3
OUT4 to
OUT2/
INT0R
PC0
PC1*3
OUT5 to
OUT2/
INT1R
PC1
PC2*3
SIN3 to SIN2/
INT2R
PC2
PC3*3
SOT3 to SOT2/
INT3R
PC3
PC4*3
SCK3 to SCK2/
INT4R
PC4
PC5*3
SIN4 to SIN2/
INT5R
PC5
PC6*3
SOT4 to SOT2/
INT6R
PC6
PC7*3
SCK4 to SCK2/
INT7R
PC7
PD0*3
PPG9 to PPG2/
INT16
PD0
PD1*3
PPGB to PPG2/
INT17
PD1
PD2*3
PPGD to PPG2/
INT18
PD2
PD3*3
PPGF to PPG2/
INT19
PD3
PD4*3
IN0 to IN2/
INT20
PD4
PD5*3
IN1 to IN2/
INT21
PD5
PD6*3
IN2 to IN2/
INT22
PD6
PD7*3
IN3 to IN2/
INT23
PD7
Sleep
sub sleep
Remark
HIZ=0
HIZ=1
Same as single-chip mode
Same as single-chip mode
Same as single-chip mode
Same as single-chip mode
677
APPENDIX C Pin States in Each CPU State
Table C-3 Pin State at External Bus Mode (8 / 9)
In stop mode,
RTC mode
At initialize/reset
Port
Specified
name function name
Initial value
Function External ROM Internal ROM
name mode vector mode vector
(MD2 to
(MD2 to
MD0=001B) MD0=000B)
PE0*3
A00/
INT24
A00
PE1*3
A01/
INT25
A01
PE2*3
A02/
INT26
A02
PE3*3
A03/
INT27
A03
Remark
HIZ=0
HIZ=1
B:
Address output
"H" output
PE4*3
A04/
INT28
A04
PE5*3
A05/
INT29
A05
PE6*3
A06/
INT30
A06
PE7*3
A07/
INT31
A07
PF0*3
A08/
INT32
A08
PF1*3
A09/
INT33
A09
PF2*3
A10/
INT34
A10
PF3*3
A11/
INT35
A11
Hi-Z output/
Same as at
P:
input enabled
left
Retention of the
immediately
prior state
Hi-Z output/
input cut off
*1
*2
Hi-Z output/
input cut off
*1
*2
B:
Address output
"H" output
PF4*3
A12/
INT36
A12
PF5*3
A13/
INT37
A13
PF6*3
A14/
INT38
A14
PF7*3
A15/
INT39
A15
678
Sleep
sub sleep
Hi-Z output/
Same as at
P:
input enabled
left
Retention of the
immediately
prior state
APPENDIX C Pin States in Each CPU State
Table C-3 Pin State at External Bus Mode (9 / 9)
In stop mode,
RTC mode
At initialize/reset
Port
Specified
name function name
Initial value
Function External ROM Internal ROM
name mode vector mode vector
(MD2 to
(MD2 to
MD0=001B) MD0=000B)
PG0*3
AN24
PG0
PG1*3
AN25
PG1
PG2*3
AN26
PG2
PG3*3
AN27
PG3
PG4*3
AN28
PG4
PG5*3
AN29
PG5
PG6*3
AN30
PG6
PG7*3
AN31
PG7
Sleep
sub sleep
Remark
HIZ=0
HIZ=1
Same as single-chip mode
*1:When the corresponding external interrupt is enabled by ENIR and selected as the external interrupt input pin by
EISSR, it is allowed input and can be used for the return from STOP state.
*2:At power on or from rising edge of INIT pin, pin state is Hi-Z output while INIT pin is "L".
*3:MB91V280 only
679
APPENDIX D Programming Example of Serial Programming (Asynchronous)
APPENDIX D Programming Example of Serial Programming
(Asynchronous)
This section explains the serial programming (asynchronous) to FLASH memory.
■ The Basic Component
Figure D-1 Configuration Figure of Serial Programming (Asynchronous)
WINDOWS
RS232C driver
User system
RS232C
Communication by UART
MB91F27x
FLASH memory of the microcontroller that is built in FLASH installed in the user system can be rewritten
using RS232C from personal computer. Also, it is the condition that the RS232C driver is set in the user
system and can communicate with UART of the microcontroller.
680
APPENDIX D Programming Example of Serial Programming (Asynchronous)
■ Connection Example of On-board Write by Programmer
Figure D-2 Connection Example of On-board Write by Programmer
User system
10kΩ
MB91F27x
1
When serial rewriting 1
MD2
0
10kΩ
When serial rewriting 0
1
MD1
0
10kΩ
1
When serial rewriting 0
MD0
0
1
0
When serial rewriting 0
1
User circuit
0
When serial rewriting 0
P10
P11
User circuit
X0
4MHz
X1
RS232C
driver
INIT
SIN
SOT
Communication by UART
RS232C
Set MD2, MD1, MD0, P10, and P11 pins on the user system because they cannot be controlled from PC
side. Also, during serial writing, after MD2, MD1, MD0, P10, and P11 pins are set, the pins are set to serial
write mode by changing INIT from "0" to "1" and serial write is allowed from PC.
After serial rewrite is completed, MD2, MD1, and MD0 pins are switched to normal mode and P10 and
P11 pins are switched to user circuit side, and the user program is executed by changing INITX from "0" to
"1".
681
APPENDIX D Programming Example of Serial Programming (Asynchronous)
■ Pins Used for On-board Rewrite by Programmer
Table D-1 Using Pins for Writing On-board
Pin
Function
Supplementary Information
MD2, MD1,
MD0
Mode Pin
Control at FLASH writing.
Specify to FLASH write mode by setting MD2=1, MD1=0, and MD0=0.
P10, P11
Programming program
activation pin
Set P10=0 and P11=0 at FLASH writing mode.
INIT
External reset input pin
Release the reset after setting MD2, MD1, MD0, P10, and P11 pins to FLASH
write mode.
SIN1 (P85)
Serial data input pin
Serial data input pin for UART1.
SOT1 (P86)
Serial data output pin
Serial data output pin for UART1.
X0, X1
Oscillation pins
In programming mode, the CPU internal operation clock is one multiplication
of the PLL clock. Therefore, the oscillation clock frequency becomes the
internal operation clock.
VCC
Power supply voltage
Use this under the recommended operating conditions.
VSS
GND
Use this under the recommended operating conditions.
■ Timing Chart of Each Pin
Each pin of the microcontroller should be inputted at the timing as shown in Figure D-3 based on an input
of INIT pin.
Figure D-3 Timing Chart of Each Pin
H
INIT
5t cp
L
MD0
H
tcp
L
MD1
H
tcp
L
MD2
H
tcp
L
P10,11
H
t cp
tcp × 250
L
SIN
H
tcp × 3500(min)
Data
L
Minimum value of set up time and hold time for each signal due to rising of INIT and P10 and P11 pins
indicate programming program activation pin, and SIN shows serial data input pin.
682
APPENDIX E Programming Example of Serial Programming (Synchronous)
APPENDIX E
Programming Example of Serial Programming
(Synchronous)
This section explains the serial programming (synchronous) to FLASH memory.
■ The Basic Component
The AF210 flash microcontroller programmer made by Yokogawa Digital Computer Corporation is used
for Fujitsu standard serial on-board programming.
Either the program that can operate in the single-chip mode or that can operate in the internal ROM
external bus mode can be selected for writing.
Figure E-1 Basic Configuration of Synchronous Serial Programming
Host interface cable (AZ201)
General-purpose common cable
(AZ210)
AF210
RS232C
Flash microcontroller
programmer
CLK synchronous
MB91F27x
serial
User system
+
Memory card
Operation is enabled in stand alone.
Note:
Contact Yokogawa Digital Computer Corporation for details of the functions of and operational
procedures related to the AF210 flash microcontroller programmer, general-purpose common
connecting cable (AZ210) and applicable connectors.
683
APPENDIX E Programming Example of Serial Programming (Synchronous)
■ Pins Used for Fujitsu Standard Serial On-board Programming
Table E-1 Serial On-board Program Using Pin
Pin
Function
Supplementary Information
MD2, MD1,
MD0
Mode Pin
Controlled from FLASH microcontroller programmer to programming mode.
FLASH serial programming mode: MD2,MD1,MD0=1,0,0
Reference: Single-chip mode: MD2,MD1,MD0=0,0,0
P10, P11
Programming program
activation pin
Set to P10=0 and P11=1 at FLASH writing mode.
INIT
External reset input pin
Release the reset after setting MD2, MD1, MD0, P10, and P11 pins to FLASH
write mode.
SIN1 (P85)
Serial data input pin
Serial data input pin for UART1.
SOT1 (P86)
Serial data output pin
Serial data output pin for UART1.
SCK1 (P87)
Serial clock input pin
Serial clock input pin for UART1.
X0, X1
Oscillation pins
In programming mode, the CPU internal operation clock is one multiplication
of the PLL clock. Therefore, the oscillation clock frequency becomes the
internal operation clock.
VCC
Power supply voltage
Use this under the recommended operating conditions.
VSS
GND
Use this under the recommended operating conditions.
To use the P10, P11, SIN1, SOT1, and SCK1 pins within the user system as well, the control circuit in the
"Figure E-2 Control circuit of serial programming pins" is required. (The user circuit can be cut off during
serial writing using the /TICS signal of the flash microcontroller programmer. Please refer to the
connection example.)
Figure E-2 Control Circuit of Serial Programming Pins
AF210
MB91F27X
writing control pin
writing control pin
10kΩ
AF210
/TICS pin
User
684
APPENDIX E Programming Example of Serial Programming (Synchronous)
■ Example of Connecting Serial Writing
Example of connecting serial writing is shown below.
● Serial writing connection example (when user power is used)
"Figure E-3 Serial writing connection example (when user power is used)" shows an example of connecting
serial writing when the user power is used.
Also, the values "1" and "0" are inputted to the mode pins MD2 and MD0 from TAUX3 and TMODE of
the flash microcontroller programmer (AF210).
(Serial rewrite mode: MD2,MD1,MD0=100B)
Figure E-3 Serial Writing Connection Example (When User Power is Used)
User system
AF210
Flash microcontroller
Connector
programmer
DX10-28S
TAUX3
10kΩ
MB91F27x
(19)
MD2
MD1
10kΩ
TMODE
MD0
(12)
10kΩ
X0
4MHz
X1
TAUX
(23)
P10
10kΩ
/TICS
(10)
User
/TRES
10kΩ
(5)
INIT
10kΩ
P11
User
TTXD
(13)
SIN1
TRXD
(27)
SOT1
TCK
(6)
SCK1
TVcc
GND
(2)
(7,8,
14,15,
21,22,
1,28)
3,4,9,11,16,17,18,
20,24,25,26 pins
are OPEN
DX10-28S: Write angle type
VCC
User power
supply
14 pin
VSS
1 pin
DX10-28S
28 pin
15 pin
Connector (manufactured by Hirose) pin layout
•
To use the P10, P11, SIN1, SOT1, and SCK1 pins within the user system as well, the control circuit in the "Figure E-2 Control circuit of serial programming pins" is required. (The user circuit
can be cut off during serial writing using the /TICS signal of the flash microcontroller programmer.)
• Connect the AF210 while the user power is off.
685
APPENDIX E Programming Example of Serial Programming (Synchronous)
● Example of connecting serial writing (Power supplied from flash microcontroller programmer)
"Figure E-4 Example of connecting serial writing (power supplied from programmer)" shows an example
of connecting serial writing when the power is used from the flash microcontroller programmer (AF210).
Also, the values "1" and "0" are inputted to the mode pins MD2 and MD0 from TAUX3 and TMODE of
the flash microcontroller programmer (AF210).
(Serial rewrite mode: MD2,MD1,MD0=100B)
Figure E-4 Example of Connecting Serial Writing (Power Supplied from Programmer)
User system
AF210
Flash microcontroller
Connector
programmer
DX10-28S
10kΩ
MB91F27x
MD2
MD1
(19)
TAUX3
10kΩ
TMODE
(12)
MD0
10kΩ
X0
4MHz
X1
(23)
TAUX
P10
10kΩ
(10)
/TICS
User
10kΩ
/TRES
INIT
(5)
10kΩ
P11
User
TTXD
(13)
SIN1
TRXD
(27)
SOT1
TCK
(6)
SCK1
Vcc
(3)
VCC
GND
(7,8,
14,15,
21,22,
1,28)
Power supply regulator
AZ264
14 pin
2,4,9,11,16,17,18,
20,24,25,26
pins are OPEN
DX10-28S: Write angle type
•
User power supply
VSS
1 pin
DX10-28S
28 pin
15 pin
Connector (manufactured by Hirose) pin layout
To use the P10, P11, SIN1, SOT1, and SCK1 pins within the user system as well, the control circuit in the "Figure E-2 Control circuit of serial programming pins" is required. (The user circuit
can be cut off during serial writing using the /TICS signal of the flash microcontroller programmer.)
• Connect the AF210 while the user power is off.
• When programming power is supplied from the AF210, be careful not to short-circuit the user
power.
686
APPENDIX E Programming Example of Serial Programming (Synchronous)
● Example of minimum connection to flash microcontroller programmer (when using user power)
"Figure E-5 Example of minimum connection for serial writing (when user power is used)" shows an
example of minimum connection to the flash microcontroller programmer (AF210) when the user power is
used. At FLASH memory programming, the MD2, MD1, MD0, P10, and P11 and the flash microcontroller
programmer need not be connected if the pins are set as described below.
(Serial rewrite mode: MD2,MD1,MD0=100B)
Figure E-5 Example of Minimum Connection for Serial Writing (When User Power is Used)
AF210
Flash microcontroller
programmer
User system
MB91F27x
10kΩ
When serial writing 1
MD2
When serial writing 0
10kΩ
10kΩ
MD1
10kΩ
10kΩ
MD0
When serial writing 0
10kΩ
X0
4MHz
X1
P10
When serial writing 0
10kΩ
10kΩ
User circuit
P11
When serial writing 1
User circuit
Connector
DX10-28S
10kΩ
INIT
/TRES
(5)
TTXD
(13)
SIN1
TRXD
(27)
SOT1
TCK
TVcc
GND
(6)
SCK1
(2)
VCC
(7,8,
14,15,
21,22,
1,28)
User power
supply
14 pin
3,4,9,10,11,12,16,17,
18,19,20,23,24,25,26
pins are OPEN
1 pin
DX10-28S
28 pin
DX10-28S: Write angle type
VSS
15 pin
Connector (manufactured by Hirose) pin layout
•
To use the SIN1, SOT1, and SCK1 pins within the user system as well, the control circuit in the
"Figure E-2 Control circuit of serial programming pins" is required. (The user circuit can be cut
off during serial writing using the /TICS signal of the flash microcontroller programmer.)
• Connect the AF210 while the user power is off.
687
APPENDIX E Programming Example of Serial Programming (Synchronous)
● Example of minimum connection to flash microcontroller programmer (power supplied from
programmer)
"Figure E-6 Example of minimum connection for serial writing (power supplied from programmer)" shows
an example of minimum connection when the power is supplied from the flash microcontroller programmer
(AF210). At FLASH memory programming, the MD2, MD1, MD0, P10, and P11 and the flash
microcontroller programmer need not be connected if the pins are set as described below.
(Serial rewrite mode: MD2,MD1,MD0=100B)
Figure E-6 Example of Minimum Connection for Serial Writing (Power Supplied from Programmer)
AF210
Flash microcontroller
programmer
User system
10kΩ
When serial writing 1
MB91F27x
MD2
When serial
writing 0
10kΩ
10kΩ
MD1
10kΩ
10kΩ
MD0
When serial writing 0
10kΩ
X0
4MHz
X1
P10
10kΩ
10kΩ
When serial
writing 0
User circuit
P11
When serial writing 1
User circuit
Connector
DX10-28S
/TRES
TTXD
TRXD
TCK
(5)
(13)
(27)
(6)
Vcc
(3)
GND
(7,8,
14,15,
21,22,
1,28)
Power supply regulator
AZ264
2,4,9,10,11,12,
16,17,18,19,20,
23,24,25,26 pins
are OPEN
DX10-28S: Write angle type
•
10kΩ
INIT
SIN1
SOT1
SCK1
VCC
User power
supply
14 pin
VSS
1 pin
DX10-28S
28 pin
15 pin
Connector (manufactured by Hirose) pin layout
To use the SIN1, SOT1, and SCK1 pins within the user system as well, the control circuit in the
"Figure E-2 Control circuit of serial programming pins" is required. (The user circuit can be cut
off during serial writing using the /TICS signal of the flash microcontroller programmer.)
• Connect the AF210 while the user power is off.
• When programming power is supplied from the AF210, be careful not to short-circuit the user
power.
688
APPENDIX E Programming Example of Serial Programming (Synchronous)
■ System Configuration for the AF210 Flash Microcontroller Programmer
Body
Model
Function
AF220
/AC4P
Ethernet interface model/100V to 220V power adapter
AF210
/AC4P
Standard model/100 V to 220 V power adapter
AF120
/AC4P
Single key Ethernet interface model/100V to 220V power adapter
AF110
/AC4P
Single key model/100 V to 220 V power adapter
AZ221
PC/AT RS232C cable for programmer
AZ210
Standard target probe (a) length: 1 m
FF003
Fujitsu FR flash microcontroller control module
AZ290
Remote controller
/P2
2MB PC Card (Option)
FLASH memory capacitance up to 128KB
/P4
4MB PC Card (Option)
FLASH memory capacitance up to 512KB
Inquiry: Yokogawa Digital Computer Corporation
Tel.: 81-42-333-6224
■ Oscillation Clock Frequency
The oscillation clock that can be used at FLASH memory programming is 4.0MHz.
■ Other Notes
The port state at FLASH memory programming via serial writer is the same as the reset state except the pin
used for programming.
689
APPENDIX E Programming Example of Serial Programming (Synchronous)
690
INDEX
INDEX
The index follows on the next page.
This is listed in alphabetic order.
691
INDEX
INDEX
Numerics
0 Detection
0 Detection ..................................................... 246
0 Detection Data Register
0 Detection Data Register (BSD0) .................... 244
1 Detection
1 Detection ..................................................... 246
1 Detection Data Register
1 Detection Data Register (BSD1) .................... 244
10-bit Slave Address Mask Register
10-bit Slave Address Mask Register
(ITMKH0 to ITMKH2,
ITMKL0 to ITMKL2)......................... 450
10-bit Slave Address Register
10-bit Slave Address Register
(ITBAH0 to ITBAH2,
ITBAL0 to ITBAL2) .......................... 449
16 - Bit Output Compare
Operation of 16 - Bit Output Compare............... 497
16-bit Free-run Timer
16-bit Free-run Timer Registers ........................ 477
Block Diagram of 16-bit Free-run Timer ........... 476
Clear Timing of the 16-bit Free-run Timer......... 483
Count Timing of the 16-bit Free-run Timer ........ 483
Explanation of Operation of 16-bit Free-run
Timer ................................................ 482
Notes on Using the 16-bit Free-run Timer.......... 484
Overview of 16-bit Free-run Timer ................... 476
16-bit Input Capture
16-bit Input Capture Operation ......................... 490
Input Timing of 16-bit Input Capture................. 490
16-bit Output Compare
Operation Timing of 16-bit Output
Compare............................................ 499
16-bit Reload Register
Bit Configuration of the 16-bit Reload Register
(TMRLR) .......................................... 470
16-bit Reload Timer
16-bit Reload Timer Registers .......................... 465
Block Diagram of 16-bit Reload Timer.............. 464
Overview of the 16-bit Reload Timer ................ 464
16-bit Timer Register
Bit Configuration of the 16-bit Timer Register
(TMR)............................................... 469
692
2-Cycle Transfer
2-Cycle Transfer (The Timing is the Same as for
Internal RAM -->External I/O, RAM,
External I/O, RAM -->Internal RAM.)
(TYP3 to TYP0=0000B,
AWR=0008H).....................................178
2-Cycle Transfer (External -->I/O)
(TYP3 to TYP0=0000B,
AWR=0008H).....................................179
2-Cycle Transfer (I/O -->External)
(TYP3 to TYP0=0000B,
AWR=0008H).....................................180
Burst 2-Cycle Transfer .....................................272
Flow of Data During 2-Cycle Transfer ...............291
Step/Block Transfer 2-Cycle Transfer ................273
7-bit Slave Address Mask Register
7-bit Slave Address Mask Register
(ISMK0 to ISMK2) .............................453
7-bit Slave Address Register
7-bit Slave Address Register
(ISBA0 to ISBA2) ..............................452
8-bit PPG
Block Diagram of the 8-bit PPG
(ch.0 and ch.2) ....................................503
Block Diagram of the 8-bit PPG (ch.1)...............504
Block Diagram of the 8-bit PPG (ch.3)...............505
INDEX
A
A/D Control Status Register
A/D Control Status Register 0 (ADCS0) ............572
A/D Control Status Register 1 (ADCS1) ............569
A/D Converter
A/D Converter .................................................564
A/D Converter: 24 Channels
(in MB91V280, support +8 Channels as
Independent Module) ..............................4
Block Diagram of the A/D Converter .................565
Registers of A/D Converter ...............................566
A/D Enable Register
A/D Enable Register (ADER) ...........................568
Acceptance Filter
Acceptance Filter of Reception Message ............346
Access Mode
Access Mode .....................................................76
Accuracy
Accuracy of Calibration....................................561
Acknowledge
Acknowledge...................................................457
ACR
Register Configuration of ACR0 to ACR3
(Area Configuration Register) ..............143
AD Bit
AD Bit of Serial Control Register (SCR) ............429
ADCR
Data Register (ADCR1, ADCR0) ......................575
ADCS
A/D Control Status Register 0 (ADCS0) ............572
A/D Control Status Register 1 (ADCS1) ............569
Address Error
Occurrence of an Address Error.........................284
Address Register
Address Register Specifications.........................275
Address/Data Multiplex Access
Normal Access or a Address/Data Multiplex Access
Operation ...........................................150
Addressing
Direct Addressing ..............................................42
Direct Addressing Area ......................................36
Slave Addressing .............................................457
ADECH
End Channel Setting Register (ADECH) ............578
ADER
A/D Enable Register (ADER) ...........................568
ADSCH
Start Channel Setting Register (ADSCH) ...........578
AF210 Flash Microcontroller Programmer
System Configuration for the AF210 Flash
Microcontroller Programmer ................689
All Channels
Disabling All Channels.....................................283
Enabling Operations for All Channels................ 279
Setting of Temporary Stopping by Writing to the
Control Register
(Set Independently for Each Channel or All
Channels Simultaneously) ................... 282
All-Channel Control Register
Bit Function of All-Channel Control Register
(DMACR).......................................... 266
Analog to Digital Conversion Data
Analog to Digital Conversion Data.................... 580
Arbitration
Arbitration ...................................................... 457
Architecture
Configuration of the Internal Architecture............ 39
Features of the Internal Architecture.................... 38
Overview of the Internal Architecture.................. 37
Area Configuration Register
Register Configuration of ACR0 to ACR3
(Area Configuration Register).............. 143
Area Select Register
Register Configuration of ASR0 toASR3
(Area Select Register) ......................... 142
Area Wait Register
Register Configuration of AWR0 to AWR3
(Area Wait Register) ........................... 148
Arithmetic Operation
Arithmetic Operation ......................................... 41
ASR
Example of Setting ASR and ASZ1, ASZ0 ........ 154
Register Configuration of ASR0 toASR3
(Area Select Register) ......................... 142
ASZ
Example of Setting ASR and ASZ1, ASZ0 ........ 154
Automatic Algorithm
Automatic Algorithm Execution Status .............. 615
Command Sequence of Automatic
Algorithm .......................................... 617
Overview of Flash Memory Automatic
Algorithm .......................................... 616
Automatic Restart
Automatic Restart ............................................ 405
Auto-Wait Timing
Auto-Wait Timing
(TYP3 to TYP0=0000B,
AWR=2008H) .................................... 171
AWR
2-Cycle Transfer (External -->I/O)
(TYP3 to TYP0=0000B,
AWR=0008H) .................................... 179
2-Cycle Transfer (I/O -->External)
(TYP3 to TYP0=0000B,
AWR=0008H) .................................... 180
693
INDEX
Auto-Wait Timing
(TYP3 to TYP0=0000B,
AWR=2008H) .................................... 171
Basic Timing (For Successive Accesses)
(TYP3 to TYP0=0000B,
AWR=0008H) .................................... 167
CS Delay Setting
(TYP3 to TYP0=0000B,
AWR=000CH) ................................... 173
External Wait Timing
(TYP3 to TYP0=0001B,
AWR=2008H) .................................... 172
Read -->Write Timing
(TYP3 to TYP0=0000B,
AWR=0048H) .................................... 169
Register Configuration of AWR0 to AWR3
(Area Wait Register)........................... 148
Setting of CS-->RD/WR Setup
(TYP3 to TYP0=0101B,
AWR=100BH) ................................... 177
With External Wait
(TYP3 to TYP0=0101B,
AWR=1008H) .................................... 176
Without External Wait
(TYP3 to TYP0=0100B,
AWR=0008H) .................................... 175
Write -->Write Timing
(TYP3 to TYP0=0000B,
AWR=0018H) .................................... 170
WRn + Byte Control Type
(TYP3 to TYP0=0010B,
AWR=0008H) .................................... 168
B
Base Clock Division Setting Register
Base Clock Division Setting Register 0
(DIVR0) ............................................ 101
Base Clock Division Setting Register 1
(DIVR1) ............................................ 103
Basic Component
The Basic Component.............................. 680, 683
Basic Mode
Basic Mode..................................................... 358
Basic Programming
Basic Programming Model................................. 43
Baud Rate
Baud Rate Calculation ..................................... 401
Baud Rate Setting Example of Each Machine Clock
Frequency.......................................... 402
UART Baud Rate Select .................................. 399
Baud Rate/Reload Counter Register
Baud Rate/Reload Counter Register .................. 391
Baud Rate/Reload Counter Register (BGR) ....... 391
BGR
Baud Rate/Reload Counter Register (BGR) ....... 391
694
Bidirectional Communication
Bidirectional Communication Function ..............418
Bit Operation
Logical Operation and Bit Operation ...................42
Bit Ordering
Bit Ordering ......................................................52
Bit Search Module
Bit Search Module(Using REALOS) .....................3
Block Diagram of the Bit Search Module ...........243
Block Diagram
Basic Block Diagram of the I/O Port..................184
Block Diagram ........................................360, 548
Block Diagram of 16-bit Free-run Timer ............476
Block Diagram of 16-bit Reload Timer ..............464
Block Diagram of Clock Generation
Controller.............................................88
Block Diagram of Clock Monitor ......................543
Block Diagram of DMA Controller
(DMAC) ............................................252
Block Diagram of External Bus Interface ...........139
Block Diagram of External Reset Pin.................132
Block Diagram of Flash Memory ......................607
Block Diagram of Hardware Watchdog
Timer.................................................639
Block Diagram of I2C Interface.........................435
Block Diagram of Input Capture Unit ................486
Block Diagram of Main Clock Oscillation
Stabilization Wait Timer......................118
Block Diagram of the 8-bit PPG
(ch.0 and ch.2) ....................................503
Block Diagram of the 8-bit PPG (ch.1)...............504
Block Diagram of the 8-bit PPG (ch.3)...............505
Block Diagram of the A/D Converter.................565
Block Diagram of the Bit Search Module ...........243
Block Diagram of the D/A Converter.................584
Block Diagram of the External Interrupt.............228
Block Diagram of the Interrupt Controller ..........216
Block Diagram of the MB91270 Series ..................7
Block Diagram of the Output Compare Unit .......492
Block Diagram of Up/Down Counter .................521
Block Diagram of the Delayed Interrupt
Module ..............................................239
CAN Block Diagram ........................................295
UART Block Diagram..............................367, 368
Block Size
Block Size.......................................................274
Block Transfer
Block Transfer.................................................273
Operation Flowchart for Block Transfer .............289
Branch Instruction
Overview of Branch Instruction...........................55
BSD0
0 Detection Data Register (BSD0) .....................244
BSD1
1 Detection Data Register (BSD1) .....................244
INDEX
BSDC
Change Point Detection Data Register
(BSDC)..............................................245
BSRR
Detection Result Register (BSRR) .....................245
Built-in Memory
Built-in Memory ..................................................3
Burst 2-Cycle Transfer
Burst 2-Cycle Transfer .....................................272
Burst Transfer
Operation Flowchart for Burst Transfer..............290
Bus Access
External Bus Access.........................................159
Bus Control Register
Bus Control Register (IBCR0 to IBCR2) ............440
Bus Converter
32-bit/16-bit Bus Converter.................................40
Harvard/Princeton Bus Converter ........................40
Bus Error
Bus Error ........................................................458
Bus Idle
Bus Idle Function.............................................429
Bus Idle Interrupt .............................................394
Bus Interface
External Bus Interface ..........................................2
Bus Mode
Bus Mode..........................................................76
Bus Mode 0 (Single-chip Mode)..........................77
Bus Mode 1
(Internal ROM External Bus Mode) ........77
Bus Mode 2
(External ROM External Bus Mode) .......77
Bus Status Register
Bus Status Register (IBSR0 to IBSR2) ...............437
Bus Width
Data Bus Width ...............................................159
Byte Access
Byte Access.....................................................165
Byte Ordering
Byte Ordering ....................................................52
C
Calibration
Accuracy of Calibration....................................561
Calibration Unit Control Register
Calibration Unit Control Register (CUCR) .........556
CAN
CAN Block Diagram ........................................295
CAN Clock Prescaler Setting ............................362
Features of CAN ..............................................294
CAN Controller
CAN Controller ...............................................295
CAN Controller: Maximum 3 Channels .................3
CAN_TX Pin
Software Control of CAN_TX Pin..................... 358
CCR
Bit Configuration of Counter Control Register
(CCR)................................................ 528
CCR (Condition Code Register) .......................... 46
Change Point Detection
Change Point Detection.................................... 247
Change Point Detection Data Register
Change Point Detection Data Register
(BSDC) ............................................. 245
Channel Group
Channel Group ................................................ 288
Chip Erase
Chip Erase ...................................................... 618
Data Erase (Chip Erase) ................................... 630
Chip Select Enable Register
Register Configuration of CSER
(Chip Select Enable Register) .............. 153
CLKB
CPU Clock (CLKB)........................................... 85
CLKP
Peripheral Clock (CLKP) ................................... 85
CLKR
Clock Source Control Register (CLKR) ............... 97
CLKT
External Bus Clock (CLKT) ............................... 86
Clock
Baud Rate Setting Example of Each Machine Clock
Frequency .......................................... 402
CAN Clock Prescaler Setting ............................ 362
Clock.............................................................. 554
Clock Inversion and Start/Stop Bit
in Mode 2 .......................................... 410
Clock Supply .................................................. 411
Clock Switch Procedure ................................... 361
Count Clock Selection...................................... 514
CPU Clock (CLKB)........................................... 85
External Bus Clock (CLKT) ............................... 86
Generation of Internal Operating Clock ............... 81
Internal Clock Operation .................................. 471
Note on PLL Clock Mode Operation ................... 33
Note on Using External Clock............................. 33
Operations of Clock Supply Function ................ 122
Oscillation Clock Frequency............................. 689
Peripheral Clock (CLKP) ................................... 85
Precautions of Non-use of Sub Clock .................. 33
Register List of Real Time Clock ...................... 546
Selection of Source Clock .................................. 81
Using an External Clock................................... 403
Waiting Time to the Main Clock
from Sub Clock .................................... 84
Clock Calibration Unit
Clock Calibration Unit ..................................... 554
Register List of Clock Calibration Unit .............. 555
695
INDEX
Clock Control Register
Clock Control Register (ICCR0 to ICCR2) ........ 447
Clock Disabling Registers
Clock Disabling Registers ................................ 553
Clock Generation Controller
Block Diagram of Clock Generation
Controller ............................................ 88
Clock Inversion
Clock Inversion and Start/Stop Bit
in Mode 2 .......................................... 410
Clock Modulation Parameter Register
Clock Modulation Parameter Register
(CMPR) ............................................ 594
Clock Modulator
Overview of Clock Modulator .......................... 592
Overview of Clock Modulator Register ............. 593
Clock Modulator Control Register
Clock Modulator Control Register
(CMCR) ............................................ 595
Clock Monitor
Block Diagram of Clock Monitor...................... 543
Output Frequency of Clock Monitor.................. 542
Clock Output Enable Register
Bit Configuration of Clock Output Enable
Register ............................................. 544
Clock Prescaler Register
Clock Prescaler Register .................................. 299
Clock Source Control Register
Clock Source Control Register (CLKR)............... 97
Clock Supervisor
Confirmation of Clock Supervisor Reset............ 603
CR Oscillation and Operation Stop of Clock
Supervisor Function............................ 602
CR Oscillation and Reactivation of Clock Supervisor
Function ............................................ 602
Overview of Clock Supervisor.......................... 598
Clock Supervisor Control Register
Clock Supervisor Control Register
(CSVCR)........................................... 599
Clock Supply
Clock Supply .................................................. 411
Operations of Clock Supply Function................ 122
Clock Switch
Clock Switch Procedure................................... 361
CMCR
Clock Modulator Control Register
(CMCR) ............................................ 595
CMPR
Clock Modulation Parameter Register
(CMPR) ............................................ 594
Communication
Bidirectional Communication Function ............. 418
Communication............................................... 412
696
Communication Error That Causes
No Error.............................................458
Communication Mode Setting ...........................428
Communication Procedure................................421
LIN-Master-Slave Communication
Function.............................................423
Master-Slave Communication Function .............420
Communication Error
Communication Error That Causes
No Error.............................................458
Compare Detection Flag
Compare Detection Flag ...................................538
Compare Function
Reload/Compare Function ................................533
Synchronous Start of Reload/Compare
Function.............................................535
Compare Register
Functions of the Compare Registers
(OCCP)..............................................494
Bit Configuration of the Compare Register
(OCCP)..............................................494
Compatible
Software Compatible........................................429
Condition Code Register
CCR (Condition Code Register) ..........................46
Connection Example
Connection Example of On-board Write by
Programmer .......................................681
Continuous Mode
Continuous Mode.............................................580
Control Register
Bit Configuration of the Control Register ...........495
Control Status Register
Bit Configuration of the Control Status Register
(TMCSR) ...........................................466
Control/Status Register
Bit Function of Control/Status Register B
(DMACB0 to DMACB4).....................258
Conversion
Analog to Digital Conversion Data ....................580
Conversion Time Setting Register
Conversion Time Setting Register .....................576
Converter
32-bit/16-bit Bus Converter ................................40
Harvard/Princeton Bus Converter ........................40
Coprocessor
Coprocessor Error Trap ......................................75
No-coprocessor Trap ..........................................75
Coprocessor Error Trap
Coprocessor Error Trap ......................................75
Count Clear
Count Clear/Gate Function ...............................537
Count Clock
Count Clock Selection......................................514
INDEX
Count Direction Change Flag
Count Direction Change Flag ............................538
Count Direction Flag
Count Direction Flag ........................................537
Counter Control Register
Bit Configuration of Counter Control Register
(CCR) ................................................528
Counter Status Register
Bit Configuration of Counter Status Register
(CSR) ................................................526
Counting Mode
Selecting Counting Mode..................................531
CPU
CPU..................................................................40
CPU Interface..................................................295
FR-CPU Programming Mode
(16 Bits, Read/Write) ..........................614
FR-CPU ROM Mode (32 Bits, Read Only).........614
Inter-CPU Connect...........................407, 419, 421
Pin States in Each CPU State ............................665
CPU Clock
CPU Clock (CLKB) ...........................................85
CPU State
Pin States in Each CPU State ............................665
CR Oscillation
CR Oscillation and Operation Stop of Clock
Supervisor Function ............................602
CR Oscillation and Reactivation of Clock Supervisor
Function.............................................602
Crystal Oscillator Circuit
Crystal Oscillator Circuit ....................................32
CS -->RD/WR Setup
CS -->RD/WR Setup and RD/WR -->CS Hold Setting
(TYP3 to TYP0=0000B,
AWR=000BH) ....................................174
CS Delay Setting
CS Delay Setting
(TYP3 to TYP0=0000B,
AWR=000CH) ....................................173
CS-->RD/WR Setup
Setting of CS-->RD/WR Setup
(TYP3 to TYP0=0101B,
AWR=100BH) ....................................177
CSER
Register Configuration of CSER
(Chip Select Enable Register)...............153
CSR
Bit Configuration of Counter Status Register
(CSR) ................................................526
CSVCR
Clock Supervisor Control Register
(CSVCR) ...........................................599
CTBR
Time-base Counter Clear Register (CTBR)...........96
CUCR
Calibration Unit Control Register (CUCR)......... 556
CUTD
Sub Timer Data Register (CUTD) ..................... 558
CUTR
Main Timer Data Register (CUTR) ................... 560
D
D/A Clock Control Register
D/A Clock Control Register (DADBL) .............. 588
D/A Control Register
D/A Control Register (DACR) .......................... 586
D/A Converter
Block Diagram of the D/A Converter ................ 584
D/A Converter:2 Channels
(MB91V280 Only).................................. 4
List of D/A Converter Registers ........................ 585
Theoretical Expressions for D/A Converter Output
Voltage.............................................. 589
D/A Data Register
D/A Data Register (DADR0, DADR1) .............. 587
DACR
D/A Control Register (DACR) .......................... 586
DADBL
D/A Clock Control Register (DADBL) .............. 588
DADR
D/A Data Register (DADR0, DADR1) .............. 587
Data Bus
Data Bus Width ............................................... 159
Data Direction Register
Data Direction Register (DDR) ......................... 187
Data Erase
Data Erase (Chip Erase) ................................... 630
Data Format
Data Format .................................................... 158
Transfer Data format................................ 408, 410
Data Frame
Data Frame Reception...................................... 346
Data Register
Data Register (ADCR1, ADCR0)...................... 575
Data Register (IDAR0 to IDAR2) ..................... 454
Reception/Transmission Data Register
(RDR/TDR) ....................................... 383
DDR
Data Direction Register (DDR) ......................... 187
Delay Slot
Explanation of Operation with Delay Slot ............ 56
Explanation of Operation without Delay Slot........ 58
Instruction of Operation without Delay Slot ......... 58
Instructions of Operation with Delay Slot ............ 56
Limitation of Operation with Delay Slot .............. 57
Delayed Interrupt Module
Overview of the Delayed Interrupt Module ........ 238
697
INDEX
Register List of the Delayed Interrupt
Module.............................................. 239
Delayed Interrupt Module Registers
DICR (Delayed Interrupt Module Registers) ...... 240
Detection
0 Detection ..................................................... 246
1 Detection ..................................................... 246
Change Point Detection ................................... 247
Error Detection ....................................... 409, 411
LIN-Synch-Field Edge Detection Interrupt ........ 394
Slave Address Detection .................................. 456
Interrupt and Flag Upon Detection
of LIN-Synch-Break ........................... 415
Detection Result Register
Detection Result Register (BSRR) .................... 245
Device State Control
Overview of Device State Control..................... 109
Device States
Device States .................................................. 110
DICR
DICR (Delayed Interrupt Module Registers) ...... 240
DLYI Bit of DICR........................................... 241
Different Blocks
Explanation of the Different Blocks .................. 369
Digital
Analog to Digital Conversion Data ................... 580
Direct Access
UART Pin Direct Access ................................. 417
Direct Addressing
Direct Addressing.............................................. 42
Direct Addressing Area...................................... 36
Divergence
Divergence ....................................................... 41
Divide-by Rate
Setting of Divide-by Rate................................... 87
Dividing Frequency Ratio
Initialization of Dividing Frequency Ratio
Setting................................................. 87
DIVR
Base Clock Division Setting Register 0
(DIVR0) ............................................ 101
Base Clock Division Setting Register 1
(DIVR1) ............................................ 103
DLYI Bit
DLYI Bit of DICR........................................... 241
DMA
Note of DMA Transfer in Sleep Mode............... 286
Overriding DMA............................................. 278
Timing for Clearing an Interrupt by DMA ......... 281
DMA Controller
Block Diagram of DMA Controller
(DMAC)............................................ 252
DMA Controller (DMAC) Registers ................. 251
DMAC (DMA Controller).................................... 3
698
DMA Transfer
DMA Transfer and Interrupts ............................278
DMAC
Block Diagram of DMA Controller
(DMAC) ............................................252
DMA Controller (DMAC) Registers ..................251
DMAC (DMA Controller) ....................................3
DMAC Interrupt Control ..................................285
Hardware Configuration of DMAC....................250
Main Functions of DMAC ................................250
OVERVIEW of DMAC....................................268
Principal Operations of DMAC .........................269
DMACA
Bit Function of DMACA0 to DMACA4.............254
DMACB
Bit Function of Control/Status Register B
(DMACB0 to DMACB4).....................258
DMACR
Bit Function of All-Channel Control Register
(DMACR) ..........................................266
DMASA
Bit Function of Transfer Source/Transfer Destination
Address Setting Registers
(DMASA0 to DMASA4/
DMADA0 to DMADA4) .....................264
Duty Modification
Duty Modification............................................516
E
Each Channel
Setting of Temporary Stopping by Writing to the
Control Register
(Set Independently for Each Channel or All
Channels Simultaneously)....................282
ECCR
Extended Communication Control Register
(ECCR)..............................................388
Edge Detection
LIN-Synch-Field Edge Detection Interrupt .........394
EIRR
External Interrupt Factor Register (EIRR) ..........231
EISSR
External Interrupt Input Pin Select Register
(EISSR) .............................................204
EIT
EIT Causes........................................................59
EIT Vector Table ...............................................67
Features of EIT ..................................................59
Priority of EIT Factor To Be Accepted.................70
Return from EIT ................................................59
EIT Factor
Priority of EIT Factor To Be Accepted.................70
INDEX
ELVR
Bit Configuration of the External Interrupt Request
Level Setting Register (ELVR).............232
End Channel Setting Register
End Channel Setting Register (ADECH) ............578
Endian
Overview of Endian .........................................156
ENIR
Bit Configuration of the Interrupt Enable Register
(ENIR)...............................................230
Erase
Chip Erase.......................................................618
Data Erase (Chip Erase)....................................630
Sector Erase Restart .........................................634
Temporarily Stop Erase ....................................620
Temporary Sector Erase Stop ............................633
Writing/Erase ..................................................626
Erasing
Sector Erasing .................................................619
Error
Communication Error That Causes
No Error.............................................458
Coprocessor Error Trap ......................................75
Error Detection ........................................409, 411
Occurrence of an Address Error.........................284
Bus Error ........................................................458
ESCR
Extended Status/Control Register (ESCR) ..........385
Extended Communication Control Register
Extended Communication Control Register
(ECCR)..............................................388
Extended Status/Control Register
Extended Status/Control Register (ESCR) ..........385
External Bus
Bus Mode 1
(Internal ROM External Bus Mode) ........77
Bus Mode 2
(External ROM External Bus Mode) .......77
External Bus Setting...........................................33
External Bus Access
External Bus Access.........................................159
External Bus Clock
External Bus Clock (CLKT)................................86
External Bus Interface
External Bus Interface ..........................................2
Block Diagram of External Bus interface ...........139
Features of External Bus interface .....................138
Procedure for External Bus interface..................181
Register List of External Bus interface ...............140
Register Types of External Bus interface ............141
External Clock
Note on Using External Clock .............................33
Using an External Clock ...................................403
External Devices
Example of Connection
with External Devices ......................... 162
External I/O
2-Cycle Transfer (The Timing is the Same as for
Internal RAM -->External I/O, RAM,
External I/O, RAM -->Internal RAM.)
(TYP3 to TYP0=0000B,
AWR=0008H) .................................... 178
External Interrupt
Block Diagram of the External Interrupt ............ 228
External Interrupt Registers ...................... 228, 229
External Interrupt Request Level ....................... 234
Notes If Restoring from STOP Status Performed
Using an External Interrupt.................. 235
Operation of an External Interrupt ..................... 233
Operation Procedure of External Interrupt.......... 233
External Interrupt Factor Register
External Interrupt Factor Register (EIRR) .......... 231
External Interrupt Input Pin Select Register
External Interrupt Input Pin Select Register
(EISSR) ............................................. 204
External Interrupt Request Level Setting Register
Bit Configuration of the External Interrupt Request
Level Setting Register (ELVR) ............ 232
External ROM External Bus Mode
Bus Mode 2
(External ROM External Bus Mode)....... 77
External Wait Timing
External Wait Timing
(TYP3 to TYP0=0001B,
AWR=2008H) .................................... 172
F
FIFO Buffer
Message Reception with FIFO Buffer................ 349
Reading from FIFO Buffer ............................... 350
Filter
Acceptance Filter of Reception Message............ 346
Flag
Compare Detection Flag................................... 538
Count Direction Change Flag............................ 538
Count Direction Flag........................................ 537
Generation of Reception Interrupt and Flag Set
Timing............................................... 395
Hardware Sequence Flag .................................. 621
I Flag................................................................ 61
Transmission Interrupt Generation and Flag
Timing............................................... 397
Interrupt and Flag Upon Detection
of LIN-Synch-Break ........................... 415
Flash Control/Status Register
Bit Configuration of Flash Control/Status Register
(FLCR).............................................. 610
699
INDEX
Flash Memory
Block Diagram of Flash Memory...................... 607
Flash Memory Access Modes ........................... 614
List of Flash Memory Registers ........................ 609
Memory Map of Flash Memory ........................ 607
Notes on Flash Memory Programming .............. 636
Outline of Flash Memory ................................. 606
Overview of Flash Memory Automatic
Algorithm .......................................... 616
Sector Address Table of Flash Memory ............. 608
Write Procedure of Flash Memory .................... 628
Flash Microcontroller
System Configuration for the AF210 Flash
Microcontroller Programmer ............... 689
FLCR
Bit Configuration of Flash Control/Status Register
(FLCR) ............................................. 610
FLWC
Bit Configuration of Wait Register (FLWC) ...... 612
FR
Feature of FR CPU .............................................. 2
FR-CPU Programming Mode
(16 Bits, Read/Write).......................... 614
FR-CPU ROM Mode (32 Bits, Read Only) ........ 614
FR-CPU Programming Mode
FR-CPU Programming Mode
(16 Bits, Read/Write).......................... 614
FR-CPU ROM Mode
FR-CPU ROM Mode (32 Bits, Read Only) ........ 614
Free-run Timer
16-bit Free-run Timer Registers ........................ 477
Block Diagram of 16-bit Free-run Timer ........... 476
Clear Timing of the 16-bit Free-run Timer......... 483
Count Timing of the 16-bit Free-run Timer ........ 483
Explanation of Operation of 16-bit Free-run
Timer ................................................ 482
Notes on Using the 16-bit Free-run Timer.......... 484
Overview of 16-bit Free-run Timer ................... 476
Fujitsu Standard
Pins Used for Fujitsu Standard Serial On-board
Programming ..................................... 684
Function
Reload/Compare Function................................ 533
Synchronous Start of Reload/Compare
Function ............................................ 535
G
Gate
Count Clear/Gate Function ............................... 537
General-purpose Register
General-purpose Register ................................... 44
700
H
Halfword Access
Halfword Access..............................................164
Hardware
Hardware Configuration of the Interrupt
Controller...........................................214
Hardware Sequence Flag ..................................621
Initial Value of Each Hardware .........................515
Hardware Watchdog
Hardware Watchdog.............................................4
Hardware Watchdog Timer
Block Diagram of Hardware Watchdog
Timer.................................................639
Hardware Watchdog Timer ...............................638
Cycle of Hardware Watchdog Timer..................641
Function of Hardware Watchdog Timer .............641
Precautions of Hardware Watchdog Timer .........642
Hardware Watchdog Timer Control Register
Hardware Watchdog Timer Control
Register .............................................640
Harvard
Harvard/Princeton Bus Converter ........................40
Hold Request Cancel Request
Hold Request Cancellation Request
(Hold Request Cancel Request) ............223
Hold Request Cancellation Request
Hold Request Cancellation Request
(Hold Request Cancel Request) ............223
Hold Request Cancellation Request Function
Example of Using the Hold Request Cancellation
Request Function (HRCR) ...................225
Hold Request Cancellation Request Level Setting
Register
Bit Configuration of the Hold Request Cancellation
Request Level Setting Register
(HRCL) .............................................219
Hold Suppress Level Interrupt
NMI/Hold Suppress Level Interrupt
Processing ..........................................282
HRCL
Bit Configuration of the Hold Request Cancellation
Request Level Setting Register
(HRCL) .............................................219
HRCR
Example of Using the Hold Request Cancellation
Request Function (HRCR) ...................225
I
I Flag
I Flag ................................................................61
INDEX
I/O
2-Cycle Transfer (External -->I/O)
(TYP3 to TYP0=0000B,
AWR=0008H).....................................179
I/O Cell
I/O Cell List ......................................................25
I/O Circuit
I/O Circuit Type.................................................26
I/O Map
I/O Map ..........................................................644
I/O Pin
I/O Pin Number .................................................24
I/O Pins...........................................................140
I/O Port
Basic Block Diagram of the I/O Port..................184
I/O Port...............................................................4
I2C Interface
Block Diagram of I2C Interface .........................435
I2C Interface (Supported for 400Kbps):
3 Channels .............................................4
I2C Interface Registers..............................433, 436
IBCR
Bus Control Register (IBCR0 to IBCR2) ............440
IBSR
Bus Status Register (IBSR0 to IBSR2) ...............437
ICCR
Clock Control Register (ICCR0 to ICCR2) .........447
ICR
Bit Configuration of Interrupt Control Register
(ICR) ...................................................62
Bit Configuration of the Interrupt Control Register
(ICR) .................................................218
Mapping of Interrupt Control Register (ICR) ........63
ICS
Bit Configuration of Input Capture Control Register
(ICS)..................................................489
IDAR
Data Register (IDAR0 to IDAR2)......................454
Idle
Bus Idle Function.............................................429
Bus Idle Interrupt .............................................394
ILM
ILM ............................................................49, 61
Impedance
Input Impedance ..............................................564
INIT
Return by INIT Pin ..........................................129
Setting Initialization Reset (INIT)......................130
Initial State
Operation in Initial State...................................602
Initial Value
Initial Value of Each Hardware .........................515
Initialization
Initialization of Dividing Frequency Ratio
Setting ................................................. 87
Operation Initialization Reset (RST).................. 131
Setting Initialization Reset (INIT) ..................... 130
Wait Time after Setting Initialization................... 84
Input Capture
16-bit Input Capture Operation ......................... 490
Block Diagram of Input Capture Unit ................ 486
Input Timing of 16-bit Input Capture ................. 490
List of Register of Input Capture ....................... 487
Overview of Input Capture ............................... 486
Input Capture Control Register
Bit Configuration of Input Capture Control Register
(ICS) ................................................. 489
Input Capture Register
Bit Configuration of Input Capture Register
(IPCP) ............................................... 488
Input Data Direct Read Register
Input Data Direct Read Register (PIDR) ............ 211
Input Impedance
Input Impedance .............................................. 564
Input Voltage
Pin Input Voltage............................................... 25
Instruction
Instruction of Operation without Delay Slot ......... 58
Instructions of Operation with Delay Slot ............ 56
Operation of INT Instruction .............................. 73
Operation of INTE Instruction ............................ 73
Operation of RETI Instruction ............................ 75
Operation of Undefined Instruction Exception...... 74
Overview of Branch Instruction .......................... 55
Overview of Other Instructions ........................... 42
INT Instruction
Operation of INT Instruction .............................. 73
INTE Instruction
Operation of INTE Instruction ............................ 73
Inter-CPU Connect
Inter-CPU Connect .......................... 407, 419, 421
Interface
Control Signal of Ordinary Bus Interface ........... 157
Control Signal of Time Division I/O
Interface ............................................ 157
CPU Interface ................................................. 295
I2C Interface (Supported for 400Kbps):
3 Channels ............................................. 4
Internal Architecture
Features of the Internal Architecture.................... 38
Overview of the Internal Architecture.................. 37
Internal Clock Operation
Internal Clock Operation .................................. 471
Internal Operating Clock
Generation of Internal Operating Clock ............... 81
701
INDEX
Internal Peripheral Request
Internal Peripheral Request .............................. 271
Internal RAM
2-Cycle Transfer (The Timing is the Same as for
Internal RAM -->External I/O, RAM,
External I/O, RAM -->Internal RAM.)
(TYP3 to TYP0=0000B,
AWR=0008H) .................................... 178
Internal ROM External Bus Mode
Bus Mode 1
(Internal ROM External Bus Mode) ....... 77
Interrupt
Bus Idle Interrupt ............................................ 394
DMA Transfer and Interrupts ........................... 278
DMAC Interrupt Control.................................. 285
Generation of Reception Interrupt and Flag Set
Timing .............................................. 395
Interrupt ......................................................... 515
Interrupt and Flag Upon Detection
of LIN-Synch-Break ........................... 415
Interrupt Generation Timing ............................. 539
Interrupt Levels................................................. 60
Interrupt Number............................................. 241
Interrupt Processing......................................... 462
Interrupt Stack .................................................. 65
Level Mask for Interrupt and NMI ...................... 61
LIN-Synch-Break Interrupt .............................. 393
LIN-Synch-Field Edge Detection Interrupt ........ 394
Main Clock Oscillation Stabilization Wait Timer
Interrupt ............................................ 121
Notes If Restoring from STOP Status Performed
Using an External Interrupt ................. 235
Reception Interrupt.......................................... 393
Timing for Clearing an Interrupt by DMA ......... 281
Transmission Interrupt ..................................... 393
Transmission Interrupt Enabling Timing............ 428
Transmission Interrupt Generation and Flag
Timing .............................................. 397
Transmission Interrupt Request Generation
Timing .............................................. 398
UART Interrupt............................................... 392
Interrupt Control Register
Bit Configuration of Interrupt Control Register
(ICR) .................................................. 62
Bit Configuration of the Interrupt Control Register
(ICR) ................................................ 218
Mapping of Interrupt Control Register (ICR) ....... 63
Interrupt Controller
Block Diagram of the Interrupt Controller ......... 216
Hardware Configuration of the Interrupt
Controller .......................................... 214
Interrupt Controller Registers ................... 215, 217
Interrupt Controller: Maximum 40 Channels .......... 4
Major Functions of the Interrupt Controller........ 214
702
Interrupt Enable Register
Bit Configuration of the Interrupt Enable Register
(ENIR)...............................................230
Interrupt Vector
Interrupt Vector ...............................................661
Interval Timer
Operations of the Interval Timer Functions.........121
Interval Timer/Counter
Other Interval Timer/Counter................................4
IPCP
Bit Configuration of Input Capture Register
(IPCP) ...............................................488
ISBA
7-bit Slave Address Register
(ISBA0 to ISBA2) ..............................452
ISMK
7-bit Slave Address Mask Register
(ISMK0 to ISMK2) .............................453
ITBAH
10-bit Slave Address Register
(ITBAH0 to ITBAH2,
ITBAL0 to ITBAL2) ...........................449
ITBAL
10-bit Slave Address Register
(ITBAH0 to ITBAH2,
ITBAL0 to ITBAL2) ...........................449
ITMKH
10-bit Slave Address Mask Register
(ITMKH0 to ITMKH2,
ITMKL0 to ITMKL2) .........................450
ITMKL
10-bit Slave Address Mask Register
(ITMKH0 to ITMKH2,
ITMKL0 to ITMKL2) .........................450
L
Latch Up
Preventing a Latch Up ........................................32
Level Mask
Level Mask for Interrupt and NMI.......................61
LIN
Connection of LIN Device ................................424
Interrupt and Flag Upon Detection
of LIN-Synch-Break............................415
LIN Bus Timing ..............................................416
LIN-Synch-Break Interrupt ...............................393
LIN-Synch-Field Edge Detection Interrupt .........394
UART as LIN Master .......................................413
UART as LIN Slave .........................................414
UART which Supports for LIN :
Maximum 7 Channels .............................3
Using LIN in Operation Mode 3 ........................428
LIN Device
Connection of LIN Device ................................424
INDEX
LIN Master
UART as LIN Master .......................................413
LIN Slave
Setting of LIN Slave.........................................428
UART as LIN Slave .........................................414
LIN-Master-Slave Communication
LIN-Master-Slave Communication
Function.............................................423
LIN-Synch-Break
Interrupt and Flag Upon Detection
of LIN-Synch-Break............................415
LIN-Synch-Break Interrupt ...............................393
LIN-Synch-Field Edge Detection
LIN-Synch-Field Edge Detection Interrupt .........394
Load
Load and Store...................................................41
Logical Operation
Logical Operation and Bit Operation....................42
Loop Back
Loop Back Combined with Silent Mode .............357
Loop Back Mode .............................................356
LQFP 100-pin
LQFP 100-pin..................................................8, 9
M
Machine Clock Frequency
Baud Rate Setting Example of Each Machine Clock
Frequency ..........................................402
Main Clock
Block Diagram of Main Clock Oscillation
Stabilization Wait Timer......................118
Interval Time of Main Clock Oscillation Stabilization
Wait Timer .........................................117
Main Clock Oscillation Stabilization Wait Timer
Interrupt .............................................121
Operation of the Main Clock Oscillation Stabilization
Wait Timer .........................................122
Precautions on Using the Main Clock Oscillation
Stabilization Wait Timer......................123
Waiting Time to the Main Clock
from Sub Clock.....................................84
Main Clock Oscillation Stabilization Wait Timer
Block Diagram of Main Clock Oscillation
Stabilization Wait Timer......................118
Interval Time of Main Clock Oscillation Stabilization
Wait Timer .........................................117
Main Clock Oscillation Stabilization Wait Timer
Interrupt .............................................121
Operation of the Main Clock Oscillation Stabilization
Wait Timer .........................................122
Precautions on Using the Main Clock Oscillation
Stabilization Wait Timer......................123
Main Clock Oscillation Stabilization Wait Timer
Control Register
Main Clock Oscillation Stabilization Wait Timer
Control Register ................................. 119
Main Timer Data Register
Main Timer Data Register (CUTR) ................... 560
Mask
Slave Address Mask......................................... 456
Master
UART as LIN Master....................................... 413
UART as Master Device .................................. 425
Master-Slave Communication
Master-Slave Communication Function ............. 420
MB91270
Block Diagram of the MB91270 Series.................. 7
Memory Map of MB91270 Series ....................... 10
MB91V280
A/D Converter: 24 Channels
(in MB91V280, support +8 Channels as
Independent Module) .............................. 4
MD
About Mode Pin (MD0 to MD2) ......................... 33
Measurement
Measurement Processing Timing....................... 554
Memory
Built-in Memory.................................................. 3
Memory Map
Memory Map .............................................. 36, 54
Memory Map of Flash Memory ........................ 607
Memory Map of MB91270 Series ....................... 10
Memory Space
Correspondence Between the Memory Space Area and
Peripheral Resource Registers .............. 645
Message
Acceptance Filter of Reception Message............ 346
Message Handler
Message Handler ............................................. 295
Message Handler Register
Message Handler Register ........................ 300, 331
Message Handler Register List.......................... 299
Message Interface Register
Message Interface Register ............................... 300
Message Interface Register List ........................ 297
Message Object
Message Object ............................................... 342
Configuration of Message Object ...................... 326
Functions of Message Object ............................ 326
Setting of Reception Message Object................. 347
Setting of Transmission Message Object............ 345
Update of Transmission Message Object............ 345
Message RAM
Message RAM ................................................ 295
Data Sending and Receiving
with Message RAM ............................ 343
703
INDEX
Message Reception
Message Reception Process.............................. 348
Message Reception with FIFO Buffer ............... 349
Message Transmission
Message Transmission ..................................... 344
Mode
Access Mode .................................................... 76
Basic Mode..................................................... 358
Bus Mode ......................................................... 76
Bus Mode 0 (Single-chip Mode) ......................... 77
Bus Mode 1
(Internal ROM External Bus Mode) ....... 77
Bus Mode 2
(External ROM External Bus Mode) ...... 77
Clock Inversion and Start/Stop Bit
in Mode 2 .......................................... 410
Communication Mode Setting .......................... 428
Continuous Mode ............................................ 580
Flash Memory Access Modes ........................... 614
FR-CPU Programming Mode
(16 Bits, Read/Write).......................... 614
FR-CPU ROM Mode (32 Bits, Read Only) ........ 614
Loop Back Combined with Silent Mode ............ 357
Loop Back Mode............................................. 356
Mode Pin.................................................. 78, 133
Note of DMA Transfer in Sleep Mode............... 286
Note on PLL Clock Mode Operation ................... 33
Operating Mode .............................................. 512
Overview of Operating Mode ............................. 76
Return from Standby Mode (Sleep/Stop) ........... 224
Selecting Counting Mode................................. 531
Silent Mode .................................................... 355
Single Mode ................................................... 407
Sleep Mode..................................................... 113
STOP Mode.................................................... 602
Stop Mode .............................................. 114, 581
Sub Clock Mode ............................................. 602
Test Mode Setting ........................................... 355
Transfer Mode ................................................ 269
UART Operation Modes .................................. 365
Using LIN in Operation Mode 3 ....................... 428
Wait Time after Returning from Stop Mode......... 84
Mode Data
State of Pins after Mode Data Read ................... 136
Mode Pin
About Mode Pin (MD0 to MD2)......................... 33
Mode Register
Mode Register (MODR) .................................... 79
MODR
Mode Register (MODR) .................................... 79
Multiplication and Division Register
Multiplication and Division Register
(Multiply & Divide Register)................. 51
704
Multiply & Divide Register
Multiplication and Division Register
(Multiply & Divide Register) .................51
Multiply-by Rate
PLL Multiply-by Rate ........................................83
Wait Time after Changing the PLL Multiply-by
Rate .....................................................84
N
NC
About the Processing of the NC and the OPEN
Pins .....................................................33
NMI
Level Mask for Interrupt and NMI.......................61
NMI (Non Maskable Interrupt)..........................223
NMI/Hold Suppress Level Interrupt
Processing ..........................................282
Operation of User Interrupt/NMI .........................72
No-coprocessor Trap
No-coprocessor Trap ..........................................75
Non Maskable Interrupt
NMI (Non Maskable Interrupt)..........................223
Normal Access
Normal Access or a Address/Data Multiplex Access
Operation ...........................................150
O
OCCP
Bit Configuration of the Compare Register
(OCCP)..............................................494
Functions of the Compare Registers
(OCCP)..............................................494
On-board Rewrite
Pins Used for On-board Rewrite by
Programmer .......................................682
On-board Write
Connection Example of On-board Write by
Programmer .......................................681
OPEN Pins
About the Processing of the NC and the OPEN
Pins .....................................................33
Operating Mode
Operating Mode...............................................512
Overview of Operating Mode..............................76
Operating State
Operating State ................................................111
Operating Status
Operating Status of Counter ..............................474
Operation Enable Bit
Operation Enable Bit ........................................407
Operation Initialization
Operation Initialization Reset (RST) ..................131
INDEX
Operation Mode
Using LIN in Operation Mode 3 ........................428
Ordering
Bit Ordering ......................................................52
Byte Ordering ....................................................52
Ordinary Bus Interface
Control Signal of Ordinary Bus Interface ...........157
OSCCR
Oscillation Control Register (OSCCR) ...............105
Oscillation
CR Oscillation and Operation Stop of Clock
Supervisor Function ............................602
CR Oscillation and Reactivation of Clock Supervisor
Function.............................................602
Source Oscillation Input at Power-on ...................33
Oscillation Clock
Oscillation Clock Frequency .............................689
Oscillation Control Register
Oscillation Control Register (OSCCR) ...............105
Oscillation Stabilization Wait Time
Oscillation Stabilization Wait Time
at Power-on ........................................129
Oscillation Stabilization Wait Timer
Block Diagram of Main Clock Oscillation
Stabilization Wait Timer......................118
Interval Time of Main Clock Oscillation Stabilization
Wait Timer .........................................117
Main Clock Oscillation Stabilization Wait Timer
Interrupt .............................................121
Operation of the Main Clock Oscillation Stabilization
Wait Timer .........................................122
Precautions on Using the Main Clock Oscillation
Stabilization Wait Timer......................123
Oscillator Circuit
Crystal Oscillator Circuit ....................................32
Output Compare
Block Diagram of the Output Compare Unit .......492
Features of the Output Compare Unit .................492
Operation of 16 - Bit Output Compare ...............497
Operation Timing of 16-bit Output
Compare ............................................499
Output Inverted Register
Output Inverted Register (REVC) ......................511
Output Pin
Output Pin Function .........................................473
Overall Control Registers
List of Overall Control Registers .......................296
Overall Control Registers..........................300, 301
P
Parity
Parity ..............................................................409
PC
PC (Program Counter) ........................................49
PDR
Port Data Register (PDR) ................................. 186
Peripheral Clock
Peripheral Clock (CLKP) ................................... 85
Peripheral Resource Registers
Correspondence Between the Memory Space Area and
Peripheral Resource Registers .............. 645
PIDR
Input Data Direct Read Register (PIDR) ............ 211
Pin Input Level
Pin Input Level................................................ 206
Selection of Pin Input Level.............................. 206
Pin Number
I/O Pin Number ................................................. 24
Pin State
Explanation of Terms Used in the Pin State Lists 664
Pin States
Pin States in Each CPU State ............................ 665
PLL
PLL Multiply-by Rate ........................................ 83
PLL Operation Enable........................................ 82
Wait Time after Changing the PLL Multiply-by
Rate..................................................... 84
Wait Time after Enabling a PLL ......................... 84
PLL Clock Mode
Note on PLL Clock Mode Operation ................... 33
Port
General Specification of Ports........................... 185
Port 0
Port 0 ............................................................. 188
Port 1
Port 1 ............................................................. 189
Port 2
Port 2 ............................................................. 190
Port 3
Port 3 ............................................................. 191
Port 4
Port 4 ............................................................. 193
Port 5
Port 5 ............................................................. 194
Port 6
Port 6 ............................................................. 195
Port 7
Port 7 ............................................................. 196
Port 8
Port 8 ............................................................. 197
Port 9
Port 9 ............................................................. 198
Port A
Port A............................................................. 199
Port B
Port B (Only for MB91V280) ........................... 200
705
INDEX
Port C
Port C (Only for MB91V280)........................... 201
Port D
Port D (Only for MB91V280)........................... 202
Port Data Register
Port Data Register (PDR) ................................. 186
Port E
Port E (Only for MB91V280) ........................... 203
Port F
Port F (Only for MB91V280) ........................... 203
Port G
Port G (Only for MB91V280)........................... 203
Port Pull-up and Pull-down Control Register
Port Pull-up and Pull-down Control Register...... 210
Port Pull-up and Pull-down Enable Register
Port Pull-up and Pull-down Enable Register....... 208
Power Pins
Power Pins........................................................ 32
Power-on
At Power-on ..................................................... 33
Oscillation Stabilization Wait Time
at Power-on ....................................... 129
Source Oscillation Input at Power-on .................. 33
Wait Time after Power-on .................................. 84
PPG
Block Diagram of the 8-bit PPG
(ch.0 and ch.2) ................................... 503
Block Diagram of the 8-bit PPG (ch.1) .............. 504
Block Diagram of the 8-bit PPG (ch.3) .............. 505
Functions of the PPG ....................................... 502
List of PPG Registers....................................... 506
PPG Operation ................................................ 512
PPG Output Operation ..................................... 513
PPG Operation Mode Control Register
PPG Operation Mode Control Register
(PPGC) ............................................. 507
PPG Starting Register
PPG Starting Register (TRG)............................ 510
PPGC
PPG Operation Mode Control Register
(PPGC) ............................................. 507
Prescaler
CAN Clock Prescaler Setting............................ 362
Prescaler Register
Prescaler Register............................................ 300
Princeton
Harvard/Princeton Bus Converter ....................... 40
Priority
Priority Among Channels................................. 287
Priority Decision ............................................. 220
Priority of EIT Factor To Be Accepted ................ 70
Reception Priority ........................................... 346
Transmission Priority....................................... 344
706
PRLH
Reload Registers (PRLL/PRLH)........................509
PRLL
Reload Registers (PRLL/PRLH)........................509
Program
Program(Write) ...............................................618
Program Counter
PC (Program Counter) ........................................49
Program Status
PS (Program Status) ...........................................45
Programmer
Connection Example of On-board Write by
Programmer .......................................681
Pins Used for On-board Rewrite by
Programmer .......................................682
Programming
Basic Programming Model .................................43
FR-CPU Programming Mode
(16 Bits, Read/Write) ..........................614
Notes on Data Programming .............................628
Notes on Flash Memory Programming ...............636
PS
PS (Program Status) ...........................................45
Pull-down Control
Pull-up and Pull-down Control ..........................208
Pull-up and Pull-down Control
Pull-up and Pull-down Control ..........................208
Pull-up Control
Pull-up Control ..................................................33
Pulse
Pulse Pin Output Control ..................................514
Pulse Width
Relation Between Reload Value
and Pulse Width..................................513
R
RAM
2-Cycle Transfer (The Timing is the Same as for
Internal RAM -->External I/O, RAM,
External I/O, RAM -->Internal RAM.)
(TYP3 to TYP0=0000B,
AWR=0008H).....................................178
Data Sending and Receiving
with Message RAM ............................343
Message RAM.................................................295
RCR
Reload Compare Register (RCR).......................525
RD/WR -->CS Hold Setting
CS -->RD/WR Setup and RD/WR -->CS Hold Setting
(TYP3 to TYP0=0000B,
AWR=000BH) ....................................174
RDR
Reception/Transmission Data Register
(RDR/TDR) .......................................383
INDEX
RDY/BUSYX
Ready/Busy Signal (RDY/BUSYX)...................621
Read -->Write Timing
Read -->Write Timing
(TYP3 to TYP0=0000B,
AWR=0048H).....................................169
Ready/Busy Signal
Ready/Busy Signal (RDY/BUSYX)...................621
Real Time Clock
Register List of Real Time Clock.......................546
Receive
Example of Receive Data..................................461
Reception
Data Frame Reception ......................................346
Generation of Reception Interrupt and Flag Set
Timing ...............................................395
Reception Interrupt ..........................................393
Reception Operation.........................................409
Reception Priority ............................................346
Reception/Transmission Data Register
(RDR/TDR)........................................383
Setting of Reception Message Object .................347
Reception Message
Acceptance Filter of Reception Message ............346
Recommended Set Value
Recommended Set Value ..................................577
Register
Register Configuration .............................310, 311
Register Function.............................................340
Reload
Reload/Compare Function ................................533
Synchronous Start of Reload/Compare
Function.............................................535
Reload Compare Register
Reload Compare Register (RCR) .......................525
Reload Operation
Reload Operation .............................................274
Transfer Count Register
and Reload Operation ..........................277
Reload Registers
Reload Registers (PRLL/PRLH)........................509
Reload Timer
16-bit Reload Timer Registers ...........................465
Block Diagram of 16-bit Reload Timer ..............464
Overview of the 16-bit Reload Timer .................464
Reload Value
Relation Between Reload Value
and Pulse Width..................................513
Remote Frame
Remote Frame .................................................347
Reset
Block Diagram of External Reset Pin .................132
Confirmation of Clock Supervisor Reset ............603
Correspondence of Reset Factor Bit
and Reset Factor ................................. 135
Operation Initialization Reset (RST).................. 131
Pin Status During Reset.................................... 136
Read/Reset Command ...................................... 617
Read/Reset Status ............................................ 627
Reset .............................................................. 134
Reset Factor .................................................... 126
Reset Timing of External Pin ............................ 132
Setting Initialization Reset (INIT) ..................... 130
Reset Factor
Correspondence of Reset Factor Bit
and Reset Factor ................................. 135
Reset Factor Bit
Correspondence of Reset Factor Bit
and Reset Factor ................................. 135
Notes on Reset Factor Bit ................................. 135
Reset Source Register/Watchdog Timer Control
Register
Reset Source Register/Watchdog Timer Control
Register (RSRR)................................... 89
Restart
Automatic Restart ............................................ 405
Sector Erase Restart ......................................... 634
Software Restart .............................................. 404
RETI Instruction
Operation of RETI Instruction ............................ 75
Return Pointer
RP (Return Pointer) ........................................... 50
REVC
Output Inverted Register (REVC) ..................... 511
ROM
FR-CPU ROM Mode (32 Bits, Read Only) ........ 614
RP
RP (Return Pointer) ........................................... 50
RSRR
Reset Source Register/Watchdog Timer Control
Register (RSRR)................................... 89
RST
Operation Initialization Reset (RST).................. 131
S
Save/Restore Processing
Save/Restore Processing................................... 248
SCR
AD Bit of Serial Control Register (SCR)............ 429
SCR (System Condition Code Register)............... 48
Serial Control Register (SCR) ........................... 374
Second/Minute/Hour Registers
Second/Minute/Hour Registers ......................... 552
Sector
Method of Specifying a Sector .......................... 631
Note on Specifying a Number of Sectors............ 631
Procedure for Deleting a Sector......................... 631
707
INDEX
Sector Address Table of Flash Memory ............. 608
Sector Erase Restart......................................... 634
Temporary Sector Erase Stop ........................... 633
Sector Erase Restart
Sector Erase Restart......................................... 634
Sector Erasing
Sector Erasing................................................. 619
Serial Control Register
AD Bit of Serial Control Register (SCR) ........... 429
Serial Control Register (SCR)........................... 374
Serial Mode Register
Serial Mode Register (SMR) ............................ 377
Serial On-board Programming
Pins Used for Fujitsu Standard Serial On-board
Programming ..................................... 684
Serial Status Register
Serial Status Register (SSR) ............................. 380
Serial Writing
Example of Connecting Serial Writing .............. 685
Setting Initialization
Setting Initialization Reset (INIT) ..................... 130
Silent Mode
Silent Mode .................................................... 355
Loop Back Combined with Silent mode............. 357
Single Mode
Single Mode ........................................... 407, 580
Single-chip Mode
Bus Mode 0 (Single-chip Mode) ......................... 77
Slave
Example of Slave Address and Data Transfer..... 460
Setting of LIN Slave ........................................ 428
Slave Address Detection .................................. 456
Slave Address Mask ........................................ 456
Slave Addressing............................................. 457
UART as LIN Slave ........................................ 414
UART as Slave Device .................................... 426
Slave Address
Example of Slave Address and Data Transfer..... 460
Slave Address Detection .................................. 456
Slave Address Mask ........................................ 456
Slave Address Mask Register
10-bit Slave Address Mask Register
(ITMKH0 to ITMKH2,
ITMKL0 to ITMKL2)......................... 450
7-bit Slave Address Mask Register
(ISMK0 to ISMK2) ............................ 453
Slave Address Register
10-bit Slave Address Register
(ITBAH0 to ITBAH2,
ITBAL0 to ITBAL2) .......................... 449
7-bit Slave Address Register
(ISBA0 to ISBA2).............................. 452
Slave Addressing
Slave Addressing............................................. 457
708
Slave Device
UART as Slave Device.....................................426
Sleep
Return from Standby Mode (Sleep/Stop) ............224
Sleep Mode
Sleep Mode .....................................................113
Note of DMA Transfer in Sleep Mode ...............286
SMR
Serial Mode Register (SMR) .............................377
Software Compatible
Software Compatible........................................429
Software Control
Software Control of CAN_TX Pin .....................358
Software Request
Software Request .............................................271
Software Restart
Software Restart ..............................................404
Source Clock
Selection of Source Clock...................................81
Source Oscillation
Source Oscillation Input at Power-on ...................33
SSP
SSP (System Stack Pointer) ..........................50, 64
SSR
Serial Status Register (SSR)..............................380
Standby
Synchronous Standby Operations ......................116
Standby Control Register
Standby Control Register (STCR)........................91
Standby Mode
Return from Standby Mode (Sleep/Stop) ............224
Start Channel Setting Register
Start Channel Setting Register (ADSCH) ...........578
START Condition
START Condition............................................455
Start/Stop Bit
Clock Inversion and Start/Stop Bit
in Mode 2...........................................410
STCR
Standby Control Register (STCR)........................91
Step Trace Trap
Operation of Step Trace Trap ..............................74
Step Transfer
Step Transfer ...................................................273
Step/Block Transfer
Step/Block Transfer 2-Cycle Transfer ................273
Stop
Notes If Restoring from STOP Status Performed
Using an External Interrupt ..................235
Recovery Operations from STOP Status.............236
Return from Standby Mode (Sleep/Stop) ............224
Stop Bit...........................................................409
INDEX
STOP Condition
STOP Condition ..............................................455
Stop Mode
STOP Mode ....................................................602
Stop Mode...............................................114, 581
Wait Time after Returning from Stop Mode..........84
Stop Requests
Transfer Stop Requests
from Peripheral Circuits.......................284
Store
Load and Store...................................................41
Sub Clock
Precautions of Non-use of Sub Clock ...................33
Waiting Time to the Main Clock
from Sub Clock.....................................84
Sub Clock Mode
Sub Clock Mode ..............................................602
Sub Second Registers
Sub Second Registers .......................................551
Sub Timer Data Register
Sub Timer Data Register (CUTD)......................558
Successive
Basic Timing (For Successive Accesses)
(TYP3 to TYP0=0000B,
AWR=0008H).....................................167
Synch
Interrupt and Flag Upon Detection
of LIN-Synch-Break............................415
LIN-Synch-Break Interrupt ...............................393
LIN-Synch-Field Edge Detection Interrupt .........394
Synchronization
Synchronization Method ...................................407
Synchronization Method
Synchronization Method ...................................407
Synchronous
Synchronous Standby Operations ......................116
Synchronous Start
Synchronous Start of Reload/Compare
Function.............................................535
System Condition Code Register
SCR (System Condition Code Register) ...............48
System Stack Pointer
SSP (System Stack Pointer) ..........................50, 64
T
Table Base Register
TBR (Table Base Register) ...........................49, 66
TBCR
Time-base Counter Control Register (TBCR) .......94
TBR
TBR (Table Base Register) ...........................49, 66
TCCS
Timer Control Status Register (TCCS) ...............479
TCDT
Timer Data Register (TCDT) ............................ 478
TDR
Reception/Transmission Data Register
(RDR/TDR) ....................................... 383
Temporarily Stop Erase
Temporarily Stop Erase.................................... 620
Temporary Sector Erase Stop
Temporary Sector Erase Stop............................ 633
Temporary Stop
Starting from a Temporary Stop ........................ 279
Temporary Stopping
Setting of Temporary Stopping by Writing to the
Control Register
(Set Independently for Each Channel or All
Channels Simultaneously) ................... 282
Test Mode
Test Mode Setting............................................ 355
Theoretical Expressions
Theoretical Expressions for D/A Converter Output
Voltage.............................................. 589
Time Division I/O Interface
Control Signal of Time Division I/O
Interface ............................................ 157
Time-base Counter
Time-base Counter .......................................... 106
Time-base Counter Clear Register
Time-base Counter Clear Register (CTBR) .......... 96
Time-base Counter Control Register
Time-base Counter Control Register (TBCR) ....... 94
Timer Control Register
Timer Control Register (WTCR) ....................... 549
Timer Control Status Register
Timer Control Status Register (TCCS)............... 479
Timer Data Register
Timer Data Register (TCDT) ............................ 478
Timing Chart
Timing Chart of Each Pin ................................. 682
TMCSR
Bit Configuration of the Control Status Register
(TMCSR)........................................... 466
TMR
Bit Configuration of the 16-bit Timer Register
(TMR) ............................................... 469
TMRLR
Bit Configuration of the 16-bit Reload Register
(TMRLR) .......................................... 470
Trace
Operation of Step Trace Trap.............................. 74
Transfer
Block Transfer ................................................ 273
Burst 2-Cycle Transfer ..................................... 272
DMA Transfer and Interrupts............................ 278
709
INDEX
Example of Slave Address and Data Transfer..... 460
Flow of Data During 2-Cycle Transfer .............. 291
Note of DMA Transfer in Sleep Mode............... 286
Number of Transfers and Ending Transfer ......... 270
Operation Flowchart for Block Transfer ............ 289
Operation Flowchart for Burst Transfer ............. 290
Selection of the Transfer Sequence ................... 272
Starting Transfer ............................................. 279
Step Transfer .................................................. 273
Step/Block Transfer 2-Cycle Transfer ............... 273
The End of Transfer......................................... 283
Transfer Address ............................................. 270
Transfer Data Format............................... 408, 410
Transfer Mode ................................................ 269
Transfer Request Acceptance and Transfer ........ 280
Transfer Stop Requests
from Peripheral Circuits ...................... 284
Transfer Type ................................................. 269
Transfer Address
Transfer Address ............................................. 270
Transfer Count
Transfer Count Register
and Reload Operation ......................... 277
Transfer Mode
Transfer Mode ................................................ 269
Transfer Source/Transfer Destination Address
Setting Registers
Bit Function of Transfer Source/Transfer Destination
Address Setting Registers
(DMASA0 to DMASA4/
DMADA0 to DMADA4) .................... 264
Transfer Stop Requests
Transfer Stop Requests
from Peripheral Circuits ...................... 284
Transfer Type
Transfer Type ................................................. 269
Transmission
Message Transmission ..................................... 344
Setting of Transmission Message Object ........... 345
Transmission Interrupt ..................................... 393
Transmission Interrupt Enabling Timing............ 428
Transmission Interrupt Generation and Flag
Timing .............................................. 397
Transmission Interrupt Request Generation
Timing .............................................. 398
Transmission Operation ................................... 409
Transmission Priority....................................... 344
Update of Transmission Message Object ........... 345
Transmission Data Register
Reception/Transmission Data Register
(RDR/TDR) ....................................... 383
Trap
Coprocessor Error Trap...................................... 75
No-coprocessor Trap ......................................... 75
Operation of Step Trace Trap ............................. 74
710
TRG
PPG Starting Register (TRG) ............................510
TYP
2-Cycle Transfer (External -->I/O)
(TYP3 to TYP0=0000B,
AWR=0008H).....................................179
2-Cycle Transfer (I/O -->External)
(TYP3 to TYP0=0000B,
AWR=0008H).....................................180
Auto-Wait Timing
(TYP3 to TYP0=0000B,
AWR=2008H).....................................171
Basic Timing (For Successive Accesses)
(TYP3 to TYP0=0000B,
AWR=0008H).....................................167
CS Delay Setting
(TYP3 to TYP0=0000B,
AWR=000CH) ....................................173
External Wait Timing TYP3 to TYP0=0001B,
AWR=2008H).....................................172
Read -->Write Timing
(TYP3 to TYP0=0000B,
AWR=0048H).....................................169
Setting of CS-->RD/WR Setup
(TYP3 to TYP0=0101B,
AWR=100BH) ....................................177
With External Wait
(TYP3 to TYP0=0101B,
AWR=1008H).....................................176
Without External Wait
(TYP3 to TYP0=0100B,
AWR=0008H).....................................175
Write -->Write Timing
(TYP3 to TYP0=0000B,
AWR=0018H).....................................170
WRn + Byte Control Type
(TYP3 to TYP0=0010B,
AWR=0008H).....................................168
U
UART
Operation of UART .........................................406
Register of UART............................................372
UART as LIN Master .......................................413
UART as LIN Slave .........................................414
UART as Master Device...................................425
UART as Slave Device.....................................426
UART Baud Rate Select ...................................399
UART Block Diagram..............................367, 368
UART Interrupt ...............................................392
UART Operation Modes...................................365
UART Pin Direct Access ..................................417
UART which Supports for LIN :
Maximum 7 Channels .............................3
UDCR
Up/Down Count Register (UDCR) ....................524
INDEX
Writing Data to UDCR .....................................536
Undefined Instruction
Operation of Undefined Instruction Exception ......74
Underflow
Underflow Operation........................................472
Unused Input Pin
About the Processing of an Unused Input Pin .......32
Up/Down Count Register
Up/Down Count Register (UDCR) ....................524
Up/Down Counter
Block Diagram of Up/Down Counter .................521
Features of Up/Down Counter ...........................520
List of Registers of Up/Down Counter ...............523
User Interrupt
Operation of User Interrupt/NMI .........................72
User Stack Pointer
USP (User Stack Pointer)....................................50
USP
USP (User Stack Pointer)....................................50
Write -->Write Timing
Write -->Write Timing
(TYP3 to TYP0=0000B,
AWR=0018H) .................................... 170
WRn
WRn + Byte Control Type
(TYP3 to TYP0=0010B,
AWR=0008H) .................................... 168
WTCR
Timer Control Register (WTCR) ....................... 549
V
Vector Table
EIT Vector Table ...............................................67
W
Wait Register
Bit Configuration of Wait Register (FLWC) .......612
Wait Time
Wait Time after Changing the PLL Multiply-by
Rate .....................................................84
Wait Time after Enabling a PLL..........................84
Wait Time after Power-on...................................84
Wait Time after Returning from Stop Mode..........84
Wait Time after Setting Initialization ...................84
Watchdog
Hardware Watchdog.............................................4
Watchdog Reset Postpone Register
Watchdog Reset Postpone Register (WPR).........100
With External Wait
With External Wait
(TYP3 to TYP0=0101B,
AWR=1008H).....................................176
Without External Wait
Without External Wait
(TYP3 to TYP0=0100B,
AWR=0008H).....................................175
Word Access
Word Access ...................................................163
Word Alignment
Word Alignment ................................................53
WPR
Watchdog Reset Postpone Register (WPR).........100
711
INDEX
712
CM71-10128-2E
FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL
FR60Lite
32-BIT MICROCONTROLLER
MB91270 Series
HARDWARE MANUAL
March 2007 the second edition
Published
FUJITSU LIMITED
Edited
Business Promotion Dept.
Electronic Devices
Similar pages