September 2003 Revision 1.0 PC87427 ServerI/O with SensorPathTM Health Monitoring General Description The National Semiconductor PC87427 is targeted for a wide range of servers, workstations and high-end desktops that use the Low Pin Count (LPC) bus for the host interface and an SMBus® interface for either a Baseboard Management Controller (BMC) or mini-BMC (mBMC), both of which are optional. For LPC and SMBus access, the PC87427 features a fast X-Bus, over which boot flash and I/O devices can be accessed. The PC87427 supports X-Bus address line forcing (to 0 or 1) to create memory windows for BIOS data storage. When VSB exists, the BMC or mBMC can access the PC87427 and its fast X-Bus via SMBus. The SMBus also controls serial port float, RTC access, and serial port interconnection (snoop and take-over modes). In addition, the PC87427 provides routing of up to two selected LPC I/O port transactions to the GPIO Extension Port. The PC87427 provides a VSB-powered high-frequency clock for on-chip peripherals; it also provides a configurable highfrequency clock for other VSB-powered platform components. The PC87427 supports SensorPath health monitor interface to LMPCxx sensors, fan monitoring and control, and a chassis intrusion detector. The System Wake-Up Control (SWC) module supports flexible wake-up and power-off request mechanisms for all platforms (i.e., with or without BMC/mBMC). The PC87427 supports both I/O and memory mapping of module registers and enables building legacy-free systems. The PC87427 also incorporates a Floppy Disk Controller (FDC), two serial ports (UARTs), a Keyboard and Mouse Controller (KBC), General-Purpose Input/Output (GPIO), GPIO extension for additional off-chip GPIO ports, and an interrupt serializer for parallel IRQs. Outstanding Features ■ Legacy-reduced Advanced I/O, optimized for high-end platforms. Legacy modules: FDC, two Serial Ports (UARTs) and a Keyboard and Mouse Controller (KBC). ■ SensorPath system health support for LMXX sensors, fan monitor/control, and chassis intrusion detection, for all platforms (i.e., with or without a BMC or mBMC). ■ 8/16-bit fast X-Bus extension for boot flash, memory and I/O. ■ I/O-mapped and memory-mapped registers. ■ VSB-powered SMBus access to modules and fast X-Bus. ■ Two sets of BIOS code and data support, for main and back-up BIOS. ■ Extremely low current consumption in Battery Backup mode. ■ Serial Interface for manageability (Serial Interface M). Two-to-one multiplexing of Serial Ports 1 and 2. ■ 52 GPIO ports with a variety of wake-up events, plus GPIO extension for additional off-chip GPIO ports. ■ Watchdog for autonomous system recovery for BIOS Boot process and for operating system use. ■ 128-pin PQFP package. Block Diagram Serial Serial Serial Interface 1 Interface 2 Interface M ServerI/O Clock VDD Floppy Disk Interface KBC Ports Fan Fan Serial LPC PWM Tach IRQ Interface Clock Serial Data Route Matrix Serial Port 1 Serial Port 2 FDC Keyboard & Mouse Controller Fan Monitor and Control LPC Bus Interface SMBus Slave Interface Internal Clocks VBAT VSB PS/2 Interfaces System Wake-Up Control RTC Clock Health Monitor Watchdog Generator and Control Wake-Up Power SCI & Chassis 32.768 Low-F High-F Events Control SMI Intrusion KHz Clock Clock SensorPath Interface WDO GPIO GPIO Ports Extension X-Bus Extension I/O Port XIRQ X-Bus Ports Extension Interface National Semiconductor and TRI-STATE are registered trademarks of National Semiconductor Corporation. SensorPath is a trademark of National Semiconductor Corporation. All other brand or product names are trademarks or registered trademarks of their respective holders. © 2003 National Semiconductor Corporation www.national.com PC87427 ServerI/O with SensorPath™ Health Monitoring PRELIMINARY PC87427 Features System Health Support ■ ■ ■ — Multiplexed address-data lines: ❏ Four direct address lines SensorPath interface to sensors optimizes digital/analog partitioning — Simplifies board design and routing — Supports distributed sensors and centralized control — Off-loads SMBus, faster boot time ❏ Fan Monitor and Control (FMC) — Four PWM-based fan controls — Eight 16-bit resolution tachometer inputs — Software or local temperature feedback control ■ Chassis intrusion detection LPC Bus Interface — Based on Intel’s LPC Interface Specification Revision 1.0, September 29, 1997 — Synchronous cycles using up to 33 MHz bus clock — 8-bit I/O and 8-bit Memory read and write cycles — Up to four 8-bit DMA channels — Serial IRQ — Supports bootable memory — Supports LPC and FWH boot transactions — Supports registers memory and I/O mapping ■ SMBus Interface — Compliant with SMBus Specification Revision 2.0, August 3, 2000 — Enables a system controller to access the internal functions and the fast X-Bus extension — Proprietary commands for read/write byte from/to: ❏ Internal register ❏ X-Bus I/O device ❏ X-Bus memory device Programmable through the LPC bus ❏ VBAT backed-up ■ — Optional internal pull-up on the two SMBus pins Fast X-Bus Extension — Supports I/O and memory read/write operations — 8- or 16-bit data bus, 28-bit addressing — Accessible from both LPC bus and SMBus — VSB powered ■ — Boot configuration selected by straps — Programmable protection control for access from the LPC bus — Supports three XIRQ external interrupts www.national.com ❏ Four user-defined I/O zones Configuration Control — Compliant with PC01 Specification Revision 1.0, 1999-2000 — Compliant with Hardware Design Guide Version 3.0 for Microsoft Windows 2000 Server, June 30 2000 — Plug and Play (PnP) Configuration register structure — Base Address strap, to setup the address of the Index-Data register pair — Flexible resource allocation for all logical devices: ❏ Relocatable base address ❏ 15 IRQ routing options to serial IRQ ❏ Up to four optional 8-bit DMA channels Legacy Modules — Supports SMBALERT — Concurrent access with the LPC bus — VSB powered ■ Two user-defined memory zones (up to 32 Mbytes total) — SMBus control over pin multiplexing, module disable and output TRI-STATE® for all Legacy modules — Slave address: ❏ One of two values selected by strap ❏ ❏ — Address line forcing (to 0 or 1) for access to two BIOS code and data sets — Optional indirect addressing of memory — XRD-XEN or XWR-XR/W mode support — Supports both slow and fast devices — For faster transactions in 16-bit data bus, strobe signals for address latches change automatically only when the address is changed Bus Interfaces ■ Partial non-multiplexed option — Four chip-select outputs, each supporting multiple zones: ❏ Two BIOS memory zones (up to 32 Mbytes total) 2 Serial Ports 1 and 2 — Software compatible with the 16550A and the 16450 — Supports shadow register for write-only bit monitoring — UART data rates up to 1.5 Mbaud — Three sets of Serial Interface pins ❏ Serial Interface 1 ❏ Snoop or Take-over connection of Serial Interface M ❏ Two-to-one multiplexing of Serial Ports 1 and 2 to Serial Interface 2 Floppy Disk Controller (FDC) — Programmable write protect — Supports FM and MFM modes — Supports Enhanced mode command for three-mode Floppy Disk Drive (FDD) — Perpendicular recording drive support for 2.88 MB — Burst and Non-Burst modes — Full support for IBM Tape Drive Register (TDR) implementation of AT and PS/2 drive types Revision 1.0 (Continued) — Separated SMBus access to RTC RAM and RTC Control D register — Battery level measurement — 16-byte FIFO — Error-free handling of data overrun and underrun — Software compatible with the PC8477, which contains a superset of the FDC functions in the µDP8473, NEC µPD765A/B and N82077 — High-performance digital separator — Supports standard 5.25" and 3.5" FDDs — Supports one FDD — Supports fast tape drives (2 Mbps) and standard tape drives (1 Mbps, 500 Kbps and 250 Kbps) ■ Power Management ■ Supports ACPI Specification Revision 2.0b, July 27, 2000 ■ System Wake-Up Control (SWC) — Wake-up request on detection of: ❏ Preprogrammed Keyboard or Mouse sequence Keyboard and Mouse Controller (KBC) — 8-bit microcontroller, software compatible with 8042AH and PC87911 — Standard interface (60h, 64h, IRQ1 and IRQ12) — Supports two external swapable PS/2 interfaces for keyboard and mouse — Five programmable, dedicated, quasi-bidirectional I/O lines (Fast GA20/P21, KBRST/P20, P12, P16, P17) 52 General-Purpose I/O (GPIO) Ports — Individually assigned to either LPC or SMBus control — 45 ports individually configured as input or output — 7 output ports — Programmable features for each output pin: ❏ Drive type (open-drain, push-pull or TRI-STATE) ❏ — Programmable option for internal pull-up resistor on each input pin — Lock option for the configuration and data of each output pin — 16 GPIO ports generate IRQ/SIOSMI/SIOSCI for wake-up events, with individual: ❏ Enable control Polarity and edge/level selection ❏ Debounce mechanism — Low-cost external GPIO port extension via a serial bus — I/O ports transactions routing to the GPIO port extension Real-Time Clock — DS1287, MC146818 and PC87911 compatible — Battery-backed 242-byte CMOS RAM, in two banks (accessed through 70-71h and 72-73h) — Selective lock mechanisms for the RTC RAM — Y2K-compliant calendar, including century and automatic leap-year adjustment — Time of day in seconds, minutes and hours, which allows a 12-hour or 24-hour format with optional adjustment for daylight saving time Revision 1.0 ❏ General-Purpose Input Events from up to 16 GPIO pins ❏ IRQs of internal logical devices ❏ Power-off, 4-second override ❏ Power Button output ■ Power Supply On/Off control — Supports Legacy- and ACPI-compatible Power Button — Direct power supply control in response to wake-up events — Programmable Crowbar time-out for “On” request — On/Off control via software emulation — Power-fail recovery ■ Enhanced Power Management (PM), including: — Special configuration registers for power down — Reduced current leakage from pins — Low-power CMOS technology — Capability for disabling all modules ■ Keyboard Events — Wake-up on any key — Supports programmable 8-byte sequence “password” for Power Management — Simultaneous recognition of three programmable keys (sequences): “Power”, “Sleep” and “Resume” ■ Power Active Timers — Two power-on, elapsed-time counters for the main (VDD) and standby (VSB) power supplies — VSB powered ■ Predetermined RTC date and time alarm — Sleep Button support TRI-STATE on VDD-fall detection for pins driving VDD-supplied devices ❏ External modem ring from RI1 or RI2 on serial ports ❏ — Optional routing of power-up request to SERIRQ, SIOSMI, SIOSCI, PWBTOUT and ONCTL — Routing control per input/output event combination — Outputs enable/disable per event and system state combination (ACPI Sx states) — Implements bank “b” of the ACPI registers — Suspend modes via software emulation (control) — Battery-backed event-logic configuration — Power Button support, featuring: ❏ On/Off control General-Purpose I/O Module ■ ❏ — 32-bit counters, clocked by a 1-second clock — VBAT backed-up counters 3 www.national.com PC87427 Features PC87427 Features ■ (Continued) — On-chip high-frequency clock generator: ❏ Based on the 32.768 KHz clock Watchdog — Compliant with Watchdog Timer Hardware Requirements for Microsoft Windows .NET Server, April 2002 — Autonomous system reset and programmable address line forcing on expiration of watchdog timer — Generates a 100 ms pulse at WDO pin ❏ ❏ Clocking, Supply and Package Information ■ ■ Strap Input Controlled Operating Modes — Base Address (BADDR) for the PnP Index-Data register pair — Input clock presence (CKIN48) select — X-Bus configuration (XCNF2-0) select — SMBus slave address (SMBSA) select — High frequency clock selection (HFCKS) Testability — XOR tree structure ❏ Includes all the device pins (except the supply pins, oscillator pins and CHASSIS pin) ❏ Protection — All pins are 5V tolerant and back-drive protected (except the LPC bus pins) — Separate battery pin that includes an internal UL protection resistor — GPIO multiplexing configuration lock ■ Power Supply — 3.3V supply operation — Separate pins for main (VDD) and standby (VSB) power supplies — Backup battery input for RTC, SWC and Power Active timers — Separate pin for core voltage filtering (VCORF) Selected at power-up by strap input (TEST) — Reduced standby power consumption — Very low power consumption for RTC and timers (0.9 µA typical) from backup battery Clocks — LPC clock input (up to 33 MHz) — ServerI/O modules clock: 48 MHz input or internal clock multiplier — 32.768 KHz crystal — On-chip low-frequency clock generator: ❏ 32.768 KHz for RTC, System Wake-Up Control (SWC), Power Active timers and the high-frequency clock generator ❏ Very low power consumption ❏ VBAT powered www.national.com HFCKOUT - configurable up to 48 MHz. The default frequency 6, 10, 24 or 40 MHz, configurable by strap. ■ — TRI-STATE device pins, selected at power-up by strap input (TRIS) ■ VSB powered — Clock outputs: ❏ LFCKOUT - 32.768 KHz or 1 Hz ■ 4 Package — 128-pin PQFP Revision 1.0 1.1 CONNECTION DIAGRAM 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 STEP/GPIO33 WDATA/GPIO32 WGATE/GPIO31 TRK0/GPIO30 WP RDATA HDSEL DSKCHG CLKIN XA9/GPO63/CKIN48 GPO60/WDO XSTB2/FANOUT1 BIOS_SEL/CTEST GPIOE45/LED2 XA8/LED1 GPIOE43/PWBTOUT XA7/GPO61/SMBSA SMBCLK SMBDAT LFCKOUT/GPO62/MSEN0 32KX2 VSS 32KX1_32KCLKIN VBAT VSB ONCTL Signal/Pin Connection and Description PC87427 1.0 65 66 67 RI2 102 34 33 32 PC87427-xxx/VLA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GPIOE44/SIOSCI XA6/SIOSMI/GPIO27 FANIN6/PWBTIN/XIRQ2 GPIOE42/SLBTIN/XIRQ1/SMBALERT XSTB0/XCNF0 XSTB1/FANOUT2 GPIOE47/SLPS5 XA4_XD0/GPIO37 XA5_XD1/GPIO36 XA6_XD2/GPIO35 XA7_XD3/GPIO34 XA8_XD4/GPIO33 XA9_XD5/GPIO32 XA10_XD6/GPIO31 XA11_XD7/GPIO30 XCS0 GPIOE41/XA4/THRMTRIP2 GPIOE40/XA5/THRMTRIP1 GPIOE46/SLPS3 XA0_XA20/GPIO25 XA1/GPO24 XA2/GPIO23 XA3/GPIO22 XWR_XRW/GPIO21 XRD_XEN/GPIO20 GPIO07/HFCKOUT VSB VSS XIRQ0/GPIO06 FANIN7/XRDY GPIOE17/XA12_XD8/FANOUT2 GPIOE16/XA13_XD9/FANOUT1 GPIOE15/XA14_XD10 GPIOE14/XA15_XD11 GPIOE13/XA16_XD12 GPIOE12/XA17_XD13 GPIOE11/XA18_XD14 GPIOE10/XA19_XD15 DSR2/GPIOE15 SIN2/GPIOE14 RTS2/GPIOE13 SOUT2/GPIOE12 CTS2/GPIOE11 DTR2_BOUT2/XCNF1 DCD2/GPIOE10 LAD3 LAD2 LAD1 LAD0 LCLK VSS VDD LFRAME LDRQ SERIRQ LRESET P12 KBRST GA20 GPIO00/CLKRUN GPIO01/KBCLK GPIO02/KBDAT GPIO03/MCLK GPIO04/MDAT XOR_OUT/DTR1_BOUT1/BADDR RI1 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 38 37 36 35 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 DIR FANIN0/P17 DR0/FANOUT3 VSS VDD VCORF MTR0/GPIO37 INDEX/GPIO36 DRATE0/GPIO35 DENSEL/GPIO34 FANIN4/P16 FANIN3 FANIN2 FANOUT0 GPIO57/GPEXD GPIO56/GPEXC GPEXC2/FANIN1 LMPCIF/GPIO05/XA10 FANIN5/GPIO26/XA11/VRMTHRM CHASSIS GPIO50/DCDM/XCS3 GPIO51/DSRM/XCS2 GPIO52/CTSM/XCS1 HFCKS/DTRM_BOUTM GPO55/SOUTM/TEST GPIO54/SINM GPO53/RTSM/XCNF2 VSB VSS DCD1 DSR1 SIN1 RTS1/TRIS SOUT1 CTS1 Plastic Quad Flatpack (PQFP), JEDEC Order Number PC87427-xxx/VLA See NS Package Number VLA128A xxx = Three-character identifier for National data, keyboard ROM and/or customer identification code. Revision 1.0 5 www.national.com PC87427 1.0 Signal/Pin Connection and Description 1.2 (Continued) BUFFER TYPES AND SIGNAL/PIN DIRECTORY The signal DC characteristics of the pins described in Section 1.4 are denoted by buffer type symbols, which are defined in Table 1. The pin multiplexing information refers to two different types of multiplexing: • Multiplexed, denoted by a slash (/) between pins in the diagram in Section 1.1. Pins are shared between two different functions. Each function is associated with different board connectivity. Normally, the function selection is determined by the board design and cannot be changed dynamically. The multiplexing options must be configured by the BIOS on power-up to comply with the board implementation. • Multiple Mode, denoted by an underscore (_) between pins in the diagram in Section 1.1. Pins have two or more modes of operation within the same function. These modes are associated with the same external (board) connectivity. Mode selection can be controlled by the device driver through the registers of the functional block and does not require a special BIOS setup upon power-up. These pins are not considered multiplexed pins from the ServerI/O configuration perspective. The mode selection method (registers and bits), as well as the signal specification in each mode, are described within the functional description of the relevant functional block. Table 1. Buffer Types Symbol www.national.com Description INCS Input, CMOS compatible, with Schmitt Trigger INOSC Input, from crystal oscillator (not characterized) INPCI Input, PCI 3.3V INSM Input, SMBus compatible INT Input, TTL compatible INTS Input, TTL compatible, with Schmitt Trigger INULR Input, power, resistor protected (not characterized) Op/n Output, push-pull output buffer capable of sourcing p mA and sinking n mA ODn Output, open-drain output buffer capable of sinking n mA OOSC Output, to crystal oscillator (not characterized) OPCI Output, PCI 3.3V ODPCI Output, open-drain, PCI 3.3V PWR Power pin GND Ground pin 6 Revision 1.0 1.3 PC87427 1.0 Signal/Pin Connection and Description (Continued) PIN MULTIPLEXING The table below shows only multiplexed pins, their associated functional blocks and the configuration bits for the selection of the multiplexed options used in the PC87427. Table 2. Pin Multiplexing Configuration Pin Functional Block Signal Functional Block Signal 1 GPIOE10 XA19_XD15 2 GPIOE11 XA18_XD14 3 GPIOE12 XA17_XD13 4 GPIOE13 XA16_XD12 5 GPIO GPIOE14 XA15_XD11 6 GPIOE15 7 GPIOE16 XA13_XD9 8 GPIOE17 XA12_XD8 Functional Block Signal Functional Block Signal SIOCFC.XDATA16 SIOCFC.XDATA16 SIOCFC.XDATA16 X-Bus 9 XA14_XD10 FMC XRDY 10 GPIO06 13 GPIO07 14 GPIO20 XRD_XEN 15 GPIO21 XWR_XRW 16 GPIO22 17 GPIO23 XA2 18 GPO24 XA1 19 GPIO25 XA0_XA20 20 GPIOE46 Clocks FANOUT1 SIOCFC.XDATA16 & SIOCFB.FANOUT1 FANOUT2 SIOCFC.XDATA16 & SIOCFB.FANOUT2 FANIN7 SIOCF4.XRDYMUX XIRQ0 SIOCF5.XIRQ0MUX HFCKOUT SIOCF4.HFCKMUX XA3 X-Bus 21 Configuration Select SWC SIOCF4.NOXBUS SLPS3 GPIOE40 XA5 22 GPIOE41 XA4 24 GPIO30 25 GPIO31 26 GPIO32 27 GPIO33 XA8_XD4 28 GPIO34 XA7_XD3 29 GPIO35 XA6_XD2 30 GPIO36 XA5_XD1 31 GPIO37 XA4_XD0 32 GPIOE47 SWC 33 XSTB1 34 XSTB0 GPIO SIOCF3.EXTSTMUX THRMTRIP1 SIOCF4.NOADDIR & SIOCFB.TRIP1 THRMTRIP2 SIOCF4.NOADDIR & SIOCFB.TRIP2 HMC XA11_XD7 XA10_XD6 X-Bus XA9_XD5 SIOCF4.NOXBUS SLPS5 SIOCF3.EXTSTMUX FMC FANOUT2 SIOCF5.XSTB1MUX Straps XCNF0 XIRQ1 GPIO GPIOE42 SLBTIN 36 XIRQ2 FMC FANIN6 PWBTIN SIOCF3.PWBTIMUX & SIOCFB.FANIN6MUX 37 XA6 SIOSMI SIOCF3.SMIMUX & SIOCF4.NOADDIR SIOSCI SIOCF3.SCIMUX 35 X-Bus GPIO27 SWC GPIO 38 Revision 1.0 GPIOE44 7 SMBus SMBALERT SIOCF3.SLBTIMUX & SIOCFC.XIRQ1MUX www.national.com PC87427 1.0 Signal/Pin Connection and Description (Continued) Table 2. Pin Multiplexing Configuration (Continued) Pin Functional Block Signal Functional Block 45 GPO62 Clocks 48 GPIO GPO61 X-Bus 49 GPIOE43 50 X-Bus XA8 51 GPIO GPIOE45 SWC Signal Functional Block Signal LFCKOUT FDC MSEN0 XA7 Straps SMBSA Functional Block Signal Configuration Select SIOCF4.LFCKMUX SIOCF4.NOADDIR PWBTOUT SIOCF3.PWBTOMUX LED1 SIOCF4.NOADDIR LED2 SIOCF3.LED2MUX 52 X-Bus BIOS_SEL Straps CTEST 53 X-Bus XSTB2 FMC FANOUT1 SIOCF5.XSTB2MUX 54 GPO60 Watchdog WDO SIOCF2.WDOMUX 55 GPO63 X-Bus XA9 61 GPIO30 62 GPIO31 GPIO GPIO CKIN48 SIOCF4.NOADDIR TRK0 WGATE FDC SIOCFC.GP3AMUX 63 GPIO32 WDATA 64 GPIO33 STEP 66 Straps P17 SIOCF2.P17MUX 67 FANOUT3 FANIN0 KBC DR0 SIOCFB.FANOUT3 71 GPIO37 MTR0 FMC 72 GPIO36 FDC INDEX GPIO SIOCFC.GP3AMUX 73 GPIO35 DRATE0 74 GPIO34 DENSEL 75 FMC FANIN4 79 GPIO57 KBC P16 SIOCF2.P16MUX GPEXD GPIO SIOCFC.GPEXMUX 80 GPIO56 81 FMC FANIN1 82 XA10 83 GPIO GPEXC SIOCFB.FANIN1MUX & SIOCFD.GPEXC2MUX GPEXC2 LMPCIF GPIO05 XA11 VRMTHRM GPIO26 85 X-Bus XCS3 DCDM 86 XCS2 87 XCS1 88 HFCKS HMC Serial Interface M SIOCF4.NOADDIR & SIOCFD.LMPCIF FMC FANIN5 SIOCF4.NOADDIR & SIOCFB.FANIN5 GPIO50 SIOCFC.SIMMUX & SIOCF5.XCS3MUX DSRM GPIO51 SIOCFC.SIMMUX & SIOCF5.XCS2MUX CTSM GPIO52 SIOCFC.SIMMUX & SIOCF5.XCS1MUX GPIO DTRM_BOUTM Straps 89 TEST SOUTM 90 91 Straps SINM XCNF2 97 Serial RTS1 Interface 1 GPIO54 RTSM Straps 100 Serial Interface 1 DTR1_BOUT1 Straps www.national.com GPO55 GPIO SIOCFC.SIMMUX GPO53 TRIS BADDR Testability XOR_OUT 8 For XOR_OUT selection Revision 1.0 PC87427 1.0 Signal/Pin Connection and Description (Continued) Table 2. Pin Multiplexing Configuration (Continued) Functional Block Pin Functional Block Signal Signal Functional Block Signal Functional Block Configuration Select Signal 103 GPIOE15 DSR2 104 GPIOE14 SIN2 105 GPIO GPIOE13 RTS2 106 GPIOE12 107 GPIOE11 CTS2 108 Straps XCNF1 DTR2_BOUT2 109 GPIOE10 DCD2 SIOCFC.GP1AMUX 124 GPIO00 CLKRUN SIOCF2.CLKRNMUX 125 GPIO01 126 GPIO02 127 GPIO03 MCLK 128 GPIO04 MDAT SIOCFC.GP1AMUX Serial Interface 2 SOUT2 LPC SIOCFC.GP1AMUX KBCLK KBDAT KBC 1.4 SIOCF2.NOKBC DETAILED SIGNAL/PIN DESCRIPTIONS This section describes all PC87427 signals. 1.4.1 LPC Interface Signal Pin(s) I/O Buffer Type Power Well Description LAD3-01 110-113 I/O INPCI/OPCI VDD LPC Address-Data. Multiplexed command, address bidirectional data, and cycle status. LCLK1 114 I INPCI VDD LPC Clock. Derived from the PCI clock (up to 33 MHz). LFRAME1 117 I INPCI VDD LPC Frame. Low pulse indicates the beginning of a new LPC cycle or termination of a broken cycle. LDRQ1 118 O OPCI VDD LPC DMA Request. Encoded DMA request for LPC Interface. LRESET1 120 I INPCI VDD LPC Reset. Derived from the PCI system reset. SERIRQ1 119 I/O INPCI/OPCI VDD Serial IRQ. The interrupt requests are serialized over a single pin, where each IRQ level is delivered during a designated time slot. CLKRUN1 124 I/O INPCI/ODPCI VDD Clock Run. Indicates that LCLK is going to be stopped and requests full-speed LCLK (same behavior as PCI CLKRUN). 1. This pin is neither 5-Volt tolerant nor back-drive protected. 1.4.2 SMBus (SMB) Interface Signal Pin(s) I/O Buffer Type Power Well Description SMBCLK 47 I/O INSM/OD6 VSB SMBus Clock. An internal pull-up for this pin is optional. SMBDAT 46 I/O INSM/OD6 VSB SMBus Serial Data. An internal pull-up for this pin is optional. SMBALERT 35 O OD6 VSB SMBus Alert. SMBus Interrupt line. An internal pull-up for this pin is optional Revision 1.0 9 www.national.com PC87427 1.0 Signal/Pin Connection and Description 1.4.3 (Continued) X-Bus Extension Signal XRD_XEN Pin(s) I/O Buffer Type Power Well Description 14 O O6/12 VSB Read. Active (low) level indicates a read cycle on the X-Bus. Enable. Active (high) level indicates valid data on the X-Bus. XWR_XRW 15 O O14/14 VSB Write. Active (low) level indicates a write cycle on the X-Bus. Read/Write. A high level indicates a read cycle on the X-Bus; a low level indicates a write cycle on the X-Bus. XA19_XD15 1-8, -XA12_XD8 I/O INTS/O4/8 VSB Multiplexed Data/Address Bus Lines. The XA11-4 address lines are multiplexed with the 8-bit data lines XD7-XD0. If the 16-bit data bus is selected, the XA19-12 address lines are multiplexed with data lines XD15-XD8. O O3/6 VSB Non-Multiplexed Address Bus Lines. The XA0 address line pin is the XA20 address line for XCSn configured to 16-bit data bus. XA11_XD7 24-31 -XA4_XD0 XA11-1, 83, 82, 55, 50, 48, 37, 21, 22, 16-18, XA0_XA20 19 XSTB2-0 53, 33-34 O O3/6 VSB Address Strobes. Controls the strobe of up to three external latches for the multiplexed address lines. XCS3-0 85-87, 23 O O14/14 VSB Chip Selects. Controls the selection of up to four devices residing on the X-Bus. XRDY 9 I INTS VSB I/O Ready. Instructs the PC87427 to extend the access cycle. XIRQ2-0 36-35, 10 I INTS VSB X-Bus Interrupt. Converted into serial interrupt by the Interrupt Serializer. The system configuration includes the interrupt number associated with this signal. BIOS_SEL 52 O O3/6 VSB BIOS Select. BIOS image selections. 1.4.4 Serial Port Interfaces (SI1, SI2 and SIM) Signal Pin(s) I/O Buffer Type Power Well CTS1 99 CTS2 CTSM 107 87 DCD1 94 DCD2 109 DCDM 85 O1 O14/14 VSB DSR1 95 I INTS VDD DSR2 DSRM 103 86 www.national.com I INTS VDD Description Clear to Send. When low, indicates that the modem or other data transfer device is ready to exchange data. VSB I INTS VDD Data Carrier Detected. When low, indicates that the data transfer device, e.g., modem, has detected the data carrier. VSB Data Set Ready. When low, indicates that the data transfer device, e.g., modem, is ready to establish a communications link. VSB 10 Revision 1.0 Signal Pin(s) DTR1_ BOUT1 100 DTR2_ BOUT2 108 DTRM_ BOUTM 88 RI1 101 RI2 102 RTS1 97 RTS2 RTSM 105 91 SIN1 96 SIN2 SINM 104 90 SOUT1 98 SOUT2 SOUTM 106 89 I/O Buffer Type Power Well O O4/8 VDD INTS VDD O3/6 VDD Request to Send. When low, indicates to the modem or other data transfer device that the corresponding UART is ready to exchange data. A system reset sets these signals to inactive high, and loopback operation holds them inactive. VSB I INTS VDD Serial Input. Receives composite serial data from the communications link (peripheral device, modem or other data transfer device). VSB O O3/6 Description Ring Indicator. When low, indicates that a telephone ring signal was received by the modem. These pins are monitored during VDD power-off for wake-up event detection. VSB O (Continued) Data Terminal Ready. When low, indicates to the data transfer device, e.g., modem, that the UART is ready to establish a communications link. After a system reset, these pins provide the DTR function and set these signals to inactive high. Loopback operation holds them inactive. Baud Output. Provides the associated serial channel baud rate generator output signal if Test mode is selected, i.e., bit 7 of EXCR1 register is set. VSB I PC87427 1.0 Signal/Pin Connection and Description VDD Serial Output. Sends composite serial data to the communications link (peripheral device, modem or other data transfer device). These signals are set active high after a system reset. VSB 1. DCDM is an output signal due to its role in an exchange connection with an external BMC. 1.4.5 Fan Monitor & Control (FMC) Signal Pin(s) FANIN0-7 66, 77, 75, 36, FANOUT0 78 FANOUT1 7 81, 76, 83, 9 I/O Buffer Type Power Well Description I INTS VDD Fan Inputs. Used to feed the fan’s tachometer pulse to the Fan Speed Monitor. O OD12,O6/12 VDD Fan Outputs. Pulse Width Modulation (PWM) signals, used to control the speed of cooling fans by controlling the voltage supplied to the fans motors. 53 FANOUT2 8 33 FANOUT3 Revision 1.0 67 11 www.national.com PC87427 1.0 Signal/Pin Connection and Description 1.4.6 (Continued) Health Monitoring & Control (HMC) Signal Pin(s) I/O Buffer Type Power Well LMPCIF 82 I/O INSM/OD6 VSB LMPC Sensor Interface. Bidirectional, SensortPath proprietary interface signal to LMPC sensor device(s). An internal pull-up for this pin is optional. THRMTRIP1-2 21, 22 I INTS VDD Thermal Trip Inputs. Indicates that a thermal trip from a CPU occurred. VRMTHRM 83 I INTS VDD VRM Thermal Warning. Thermal warning from a VRM of a CPU. 1.4.7 Description Keyboard and Mouse Controller (KBC) Signal Pin(s) I/O Buffer Type Power Well Description KBCLK 125 I/O INTS/OD14 VDD Keyboard Clock. Keyboard clock signal. An external pull-up resistor is required for PS/2 compliance. This pin is monitored during VDD power-off for wake-up event detection. KBDAT 126 I/O INTS/OD14 VDD Keyboard Data. Keyboard data signal. An external pull-up resistor is required for PS/2 compliance. This pin is monitored during VDD power-off for wake-up event detection. MCLK 127 I/O INTS/OD14 VDD Mouse Clock. Mouse clock signal. An external pull-up resistor is required for PS/2 compliance. This pin is monitored during VDD power-off for wake-up event detection. MDAT 128 I/O INTS/OD14 VDD Mouse Data. Mouse data signal. An external pull-up resistor is required for PS/2 compliance. This pin is monitored during VDD power-off for wake-up event detection. KBRST 122 I/O INT/OD8, VDD KBD Reset. Keyboard reset (P20) quasi-bidirectional signal. VDD Gate A20. KBC gate A20 (P21) quasi-bidirectional signal. VDD I/O Port. KBC quasi-bidirectional signal for general-purpose input and output (controlled by KBC firmware). VDD I/O Port. KBC quasi-bidirectional signal for general-purpose input and output (controlled by KBC firmware). O4/8 GA20 123 I/O INT/OD8, O4/8 P12 121 I/O INT/OD8, O4/8 P16, P17 75, 66 I/O INT/OD8, O4/8 www.national.com 12 Revision 1.0 1.4.8 PC87427 1.0 Signal/Pin Connection and Description (Continued) General-Purpose I/O (GPIO) Signal Pin(s) I/O Buffer Type Power Well GPIO00 124 I/O INPCI/OPCI VSB GPIO01-04 125-128 I/O INTS/O14/14 VSB GPIO05 82 I/O INTS/O3/6 VSB GPIO06 10 I/O INTS/O3/6 VSB GPIO07 13 I/O INTS/O14/14 VSB INTS/O3/6 1, 3-6 GPIOE10, GPIOE12-15 109, 106-103 I/O INTS/O14/14 2 GPIOE11 I/O INTS/O3/6 INTS/O3/6 107 INTS/O3/6 VSB Description General-Purpose I/O Ports. Each pin is configured independently as input or I/O with or without static pull-up and with either open-drain or push-pull output type. The GPIOEnn pins have event detection capability. VSB VSB GPIOE16-17 7-8 I/O GPIO20 14 I/O INTS/O6/12 VSB GPIO21 15 I/O INTS/O14/14 VSB GPIO22-23 16-17 I/O INTS/O3/6 VSB GPO24 18 O O3/6 VSB GPIO25-27 19, 83, 37 I/O INTS/O3/6 VSB 31,29-25 INTS/O4/8 VSB INTS/O6/12 VDD INTS/O4/8 VSB 72, 61 INTS/O3/6 VDD GPIOE40-44 21-22, I/O 35, 49, 38 INTS/O3/6 VSB GPIOE45 51 INTS/O14/14 VSB GPIOE46-47 20, 32 INTS/O3/6 VSB GPIO50-52 85-87 I/O INTS/O14/14 VSB GPO53 91 O O3/6 VSB General-Purpose Output Port. GPIO54 90 I/O INTS/O3/6 VSB General-Purpose I/O Port. The pin is configured independently as input or I/O with or without static pull-up and with either open-drain or push-pull output type. GPO55 89 O O3/6 VSB General-Purpose Output Port. I/O INTS/O14/14 VSB General-Purpose I/O Ports. Each pin is configured independently as input or I/O with or without static pull-up and with either open-drain or push-pull output type. The GPIOEnn pins have event detection capability. GPIO37,35-31 71, 7374, 64-62 I/O 30, 24 GPIO36,30 GPIO56-57 Revision 1.0 I/O 80-79 I/O I/O General-Purpose Output Port. General-Purpose I/O Ports. Each pin is configured independently as input or I/O with or without static pull-up and with either open-drain or push-pull output type. The GPIOEnn pins have event detection capability. 13 www.national.com PC87427 1.0 Signal/Pin Connection and Description Signal Pin(s) I/O Buffer Type Power Well (Continued) Description GPO60-63 54,48, 45,55 O O3/6 VSB General-Purpose Output Ports. GPEXD 79 I/O INTS/O14/14 VSB General-Purpose I/O Extension Data. GPEXC 80 O O14/14 VSB General-Purpose I/O Extension Clock. GPEXC2 81 O O14/14 VSB General-Purpose I/O Extension Clock 2. 1.4.9 Floppy Disk Controller (FDC) Signal Pin(s) I/O Buffer Type Power Well Description DENSEL 74 O OD12,O6/12 VDD Density Select. Indicates that either a high FDC density data rate (500 Kbps, 1 Mbps or 2 Mbps) or a low density data rate (250 or 300 Kbps) is selected. DIR 65 O OD12,O6/12 VDD Direction. Determines the direction of the Floppy Disk Drive (FDD) head movement (active = step in; inactive = step out) during a seek operation. DR0 67 O OD12,O6/12 VDD Drive Select. Controlled by bit 0 of the Digital Output Register (DOR). DRATE0 73 O OD12,O6/12 VDD Data Rate. Reflects the value of bit 0 of the Configuration Control Register (CCR) or the Data Rate Select Register (DSR), whichever was written to last. DSKCHG 57 I INTS VDD Disk Change. Indicates if the drive door was opened. HDSEL 58 O OD12,O6/12 VDD Head Select. Determines which side of the FDD is accessed. Active low selects side 1; inactive selects side 0. INDEX 72 I INTS VDD Index. Indicates the beginning of an FDD track. MSEN0 45 I INTS VDD Automatic Media Sense. Identifies the media type of the floppy disk in drives 1 and 0 (if the drives support this protocol). MTR0 71 O OD12,O6/12 VDD Motor Select. Motor enable lines for drives 0. RDATA 59 I INTS VDD Read Data. Raw serial input data stream read from the FDD. STEP 64 O OD12,O6/12 VDD Step. Sends pulses to the disk drive at a software programmable rate to move the head during a seek operation. TRK0 61 I INTS VDD Track 0. Indicates to the controller that the head of the selected floppy disk drive is at track 0. WDATA 63 O OD12,O6/12 VDD Write Data. Carries out the pre-compensated serial data that is written to the FDD. Pre-compensation is software selectable. WGATE 62 O OD12,O6/12 VDD Write Gate. Enables the write circuitry of the selected FDD. WP 60 I INTS VDD Write Protected. Indicates that the disk in the selected drive is write protected. www.national.com 14 Revision 1.0 PC87427 1.0 Signal/Pin Connection and Description (Continued) 1.4.10 System Wake-Up Control (SWC) Signal Pin(s) I/O Buffer Type Power Well Description GPIOE17-16 8-7 I INTS VSB GPIOE11-10 2-1 I INTS VSB 21-22, 35, GPIOE40-47 49, 38, 51, 20, 32 I INTS VSB RI1 RI2 101 102 I INTS VSB Ring Indicator Wake-up. When low, generates a wake-up event or an interrupt, indicating that a telephone ring signal was received by the modem. When RI functionality is not required, an internal pull-up resistor allows this pin to be left floating. KBCLK 125 I INTS VSB Keyboard Clock Wake-up. Generates a wake-up event or an interrupt, indicating a change in the keyboard clock signal. KBDAT 126 I INTS VSB Keyboard Data Wake-up. Generates a wake-up event or an interrupt, indicating a change in the keyboard data signal. MCLK 127 I INTS VSB Mouse Clock Wake-up. Generates a wake-up event or an interrupt, indicating a change in the mouse clock signal. MDAT 128 I INTS VSB Mouse Data Wake-up. Generates a wake-up event or an interrupt, indicating a change in the mouse data signal. PWBTIN 36 I INTS VSB Power Button In. Active (low) level indicates a user request to turn the power on or off. This pin has debounce protection. PWBTOUT 49 O OD6 VSB Power Button Out. Output for the chip-set Power Button input. SLBTIN 35 I INTS VSB Sleep Button In. Active (low) level indicates a user request to enter or exit Sleep mode. This pin has debounce protection. SLPS3, SLPS5 20 32 I INTS VSB Sleep State 3 to 5. Active (low) level indicates the system is in one of the sleep states S3, S4 or S5. These signals are generated by an external ACPI controller. Pins SLPS3 SLPS5 Functionality 1 1 Working state (S0) or sleep states S1 or S2 0 1 Sleep state S3 0 0 Sleep states S4 or S5 1 0 Illegal combination SIOSCI 38 O OD6 VSB System Control Interrupt. Active (low) level indicates that a wake-up event occurred, causing the system to exit its current sleep state. SIOSMI 37 O OD6 VSB System Management Interrupt. Active (low) level indicates that an SMI occurred. ONCTL 39 O OD6 VSB Power Supply On/Off Control. Active level (low) indicates that the power should be turned on. An external pull-up resistor is required LED1, LED2 50, 51 O O14/14 VSB LED Drives. These outputs can be connected directly to LED devices. They can be configured, with programmable blink rate for all LEDs, as one dual-colored LED or two singlecolored LEDs. CHASSIS I INCS VPP1 Chassis Intrusion Input. Any change of this pin sets the intrusion detection. For correct operation, this pin must be tied to VSS when it is not used. GPIOE15-10 103-107, 109 84 Wake-up Inputs. Generate a wake-up event or an interrupt. These pins have programmable debounce protection. 1. Internal VPP is based on VSB and VBAT. Revision 1.0 15 www.national.com PC87427 1.0 Signal/Pin Connection and Description (Continued) 1.4.11 Watchdog Signal Pin(s) I/O Buffer Type Power Well WDO 54 O O3/6 Description VSB Watchdog Out. An active pulse (low) of a fixed width; it is generated when a watchdog time-out occurs. 1.4.12 Clocks Signal Pin(s) I/O Buffer Type Power Well Description 32KX1_32KCLKIN1 42 I INOSC VPP 32.768 KHz Crystal Input. Input from external crystal oscillator circuitry. 32.768 KHz Clock Oscillator Input. Input from external clock oscillator device.2 32KX23 44 O OOSC VPP 32.768 KHz Crystal Oscillator Output. Output to external crystal oscillator circuitry. LFCKOUT 45 O O3/6 VSB Low Frequency Clock Output. The Real-Time Clock frequency (32.768 KHz), or a 1 Hz clock output. CLKIN 56 I INTS VSB4 Clock Input. 48 MHz for the Legacy functions, or no input clock. HFCKOUT 13 O O14/14 VSB High Frequency Clock Output. Clock output for system use. 1. This pin is not 5-volt tolerant. 2. If the input clock is in TRI-STATE while VSB is off, it is recommended to connect an external 10 KΩ pull-down resistor to this pin. 3. This pin is neither 5-volt tolerant nor back-drive protected. 4. The CLKIN signal source can be VDD powered. 1.4.13 Configuration Straps Note: All external pull-down resistors must be connected to VSS. Signal Pin(s) I/O Buffer Type Power Well Description BADDR 100 I INTS VDD Base Address. Sampled at VDD Power-Up reset to determine the base address of the configuration Index-Data register pair, as follows: No pull-down resistor: 2Eh-2Fh 10 KΩ1 external pull-down resistor: 4Eh-4Fh TRIS 97 I INTS VDD TRI-STATE Device. Sampled at VDD Power-Up reset to force the device to float all its output and I/O pins, as follows: No pull-down resistor: Pins active 10 KΩ1 external pull-down resistor: Pins floating CKIN48 55 I INTS VSB CLKIN 48 MHz. Sampled at VSB Power-Up reset to determine the presence of the 48 MHz input clock at the CLKIN pin, as follows: No pull-down resistor: No clock 10 KΩ external pull-down resistor: 48 MHz clock www.national.com 16 Revision 1.0 Signal Pin(s) PC87427 1.0 Signal/Pin Connection and Description (Continued) I/O Buffer Type Power Well Description HFCKS 88 I INTS VSB High Frequency Clock Selection. Sampled at VSB Power-Up reset to determine the high frequency clock selection, as follows: For CKIN48=0: No pull-down resistor: 40 MHz 10 KΩ1 external pull-down resistor: 10 MHz For CKIN48=1: No pull-down resistor: 24 MHz 10 KΩ1 external pull-down resistor: 6 MHz XCNF2-0 91, 108, 34 I INTS VSB X-Bus Default Configuration. Sampled at VSB Power-Up reset to set the configuration of the X-Bus transactions. Pins 2 1 0 Functionality 1 1 1 0 0 0 0 1 0 0 1 1 0 0 x: 1: 0: 1: 0: 1: 0: No BIOS 16-bit data BIOS, XSTB0 only 16-bit data BIOS, XSTB0 and XSTB1 8-bit data BIOS, XA11-4 multiplexed, XRDY disabled 8-bit data BIOS, XA11-4 multiplexed, XRDY enabled 8-bit data BIOS, XA11-4 direct, XRDY disabled 8-bit data BIOS, XA11-4 direct, XRDY enabled Pulled to 1 by internal resistor or set to 0 by external 10 KΩ1 pulldown resistor. SMBSA 48 I INTS VSB SMBus Slave Address. Sampled at VSB Power-Up reset to determine the slave address of the device on SMBus, as follows No pull-down resistor: D8h, D9h 10 KΩ external pull-down resistor: 60h, 61h TEST 89 I INTS VDD XOR Tree Test Mode. Sampled at VDD Power-Up reset to force the device pins into a XOR tree configuration. No pull-down resistor (default): Normal device operation 10 KΩ1 external pull-down resistor: Pins configured as XOR tree. When TEST is set to 0 (by an external pull-down resistor), TRIS must be 1 (left unconnected). CTEST 52 I INTS VSB Complementary Test Mode. Sampled at VSB Power-Up reset to set the device to Test Mode No pull-down resistor: Normal Operation mode 10 KΩ external pull-down resistor: Test Mode 1. Because the strap function is multiplexed with the Serial Port pins, a CMOS transceiver device is recommended for Serial Port functionality; in this case, the value of the external pull-down resistor is 10 KΩ. If, however, a TTL transceiver device is used, the value of the external pull-down resistor must be 470Ω, and since the Serial Port pins are not able to drive this load, the external pull-down resistor must be disconnected tIPLV after VDD power-up (see “Reset Timing” on page 27). 1.4.14 Testability Signal XOR_OUT Revision 1.0 Pin(s) I/O Buffer Type Power Well 100 O O4/8 VDD Description XOR Tree Output. All the device pins (except power pins) are internally connected in a XOR tree structure. 17 www.national.com PC87427 1.0 Signal/Pin Connection and Description (Continued) 1.4.15 Power and Ground Signal Pin(s) I/O Buffer Type Description VSS 11, 43, 68, 93, 115 I GND Ground. Serves for both on-chip logic, output drivers and back-up battery circuit. VDD 69, 116 I PWR Digital 3.3V Power Supply. Serves as power supply for the legacy peripherals and the LPC Interface. VSB 12, 40, 92 I PWR Standby Digital 3.3V Power Supply. Used for the SMBus and X-Bus interfaces, the GPIO ports and the clock generator. When active, it also powers the RTC and the SWC. VCORF 70 I/O PWR On-Chip Core Power Converter Filter. Used by the on-chip core power converter which powers the core logic of all the device modules. An external 1µF ceramic filter capacitor must be connected between this pin and VSS. VBAT 41 I INULR Battery Power Supply. When VSB is off, this supply provides battery back-up to the SWC registers, the RTC and the 32 KHz crystal oscillator. The pin is connected to the internal logic through a series resistor for UL-compliant protection. 1.5 INTERNAL PULL-UP AND PULL-DOWN RESISTORS The signals listed in Table 3 have internal pull-up (PU) and/or pull-down (PD) resistors. The internal resistors are optional for those signals indicated as “Programmable”. See Section 2.3 on page 25 for the values of each resistor type. Table 3. Internal Pull-Up and Pull-Down Resistors Signal Pin(s) Power Well Type Comments Keyboard and Mouse Controller (KBC) P12, P16, P17 VDD 121, 75, 66 PU30 SMBus (SMB) Interface SMBCLK 47 VSB PU30 Programmable1 SMBDAT 46 VSB PU30 Programmable1 SMBALERT 35 VSB PU30 Programmable1 Health Monitoring and Control (HMC) LMPCIF 82 VSB PU1K25 THRMTRIP1, THRMTRIP2 21, 22 VDD PU30 VRMTHRM 83 VDD PU30 Programmable2 System Wake-Up Control (SWC) PWBTIN 36 VSB PU30 SLBTIN 35 VSB PU30 PWBTOUT 49 VSB PU30 SIOSMI 37 VSB PU30 SIOSCI 38 VSB PU30 www.national.com 18 Note 3 Revision 1.0 PC87427 1.0 Signal/Pin Connection and Description (Continued) Table 3. Internal Pull-Up and Pull-Down Resistors (Continued) Signal Pin(s) Power Well Type Comments RI1 101 VSB PU90 Pin can be left Not Connected RI2 102 VSB PU90 Pin can be left Not Connected General-Purpose Input/Output (GPIO) Ports GPIO00-04, 06-07 124-128, 10, 13 GPIO05 82 VSB or VDD PU30 Programmable VSB PU1K25 Programmable VSB PU30 Programmable 1-6 GPIOE10-15 109, 107-103 GPIOE16-17 7, 8 VSB PU30 Programmable GPIO20-27 14-19, 83, 37 VSB PU30 Programmable GPIO30-37 61-64, 74, 73-71 VSB PU30 Programmable GPIOE40-47 21-22, 35, 49, 38, 51, 20, 32 VSB PU30 Programmable GPIO50-57 85-87, 91-89, 80-79 VSB PU30 Programmable4 GPO60-63 54, 48, 45, 55 VSB PU30 Programmable Strap Configuration BADDR 100 VDD PU30 Strap5 TRIS 97 VDD PU30 Strap5 CKIN48 55 VSB PU30 Strap6 91, 108, 34 VSB PU30 Strap6 48 VSB PU30 Strap6 HFCKS 88 VSB PU30 Strap6 TEST 89 VDD PU30 Strap5 CTEST 52 VSB PU30 Strap6 XCNF2-0 SMBSA 1. Default at reset: disabled. 2. Default at reset: enabled. 3. Disabled when VDD is off. 4. Disabled during VSB Power-Up reset. 5. Active only during VDD Power-Up reset. 6. Active only during VSB Power-Up reset. Revision 1.0 19 www.national.com PC87427 2.0 Device Characteristics 2.1 GENERAL DC ELECTRICAL CHARACTERISTICS 2.1.1 Recommended Operating Conditions Symbol Min Typ Max Unit VDD Supply Voltage 3.0 3.3 3.6 V VSB Standby Voltage 3.0 3.3 3.6 V VBAT Battery Backup Supply Voltage 2.4 3.0 3.6 V +70 °C TA 2.1.2 Parameter Operating Temperature 0 Absolute Maximum Ratings Absolute maximum ratings are values beyond which damage to the device may occur. Unless otherwise specified, all voltages are relative to ground. Symbol VSUP VI VO TSTG Parameter Conditions Min Max Unit −0.5 +4.1 V All other pins −0.5 5.5 V LCLK, LAD3-0, LFRAME, LRESET, SERIRQ, CLKRUN, 32KX1_32KCLKIN −0.5 VDD + 0.5 V All other pins −0.5 5.5 V LAD3-0, LDRQ, SERIRQ, CLKRUN, 32KX2 −0.5 VDD + 0.5 V −65 +165 °C 1 W +260 °C Supply Voltage1 Input Voltage Output Voltage Storage Temperature PD Power Dissipation TL Lead Temperature Soldering (10 s) ESD Tolerance CZAP = 100 pF RZAP = 1.5 MCRS Battery Maximum Safe Reverse Current 2000 V 2.274 mA KΩ2 VSB = 3.63V RUL3=1.6KΩ 1. VSUP is VDD, VSB or VBAT. 2. Value based on test complying with RAI-5-048-RA human body model ESD testing. 3. Minimum value of internal protection resistor. 4. For batteries with lower MCRS it is necessary to connect a series resistor between the battery and VBAT pin, with resistance: R=(3.63V/MCRS)-1.6 KΩ. www.national.com 20 Revision 1.0 2.1.3 PC87427 2.0 Device Characteristics (Continued) Capacitance Symbol Min2 Parameter Typ1 Max2 Unit 4 5 pF 8 12 pF CIN Input Pin Capacitance CIN1 Clock Input Capacitance3 CIO I/O Pin Capacitance 8 10 pF CO Output Pin Capacitance 6 8 pF 5 1. TA = 25°C, f = 1 MHz. 2. Not tested. Guaranteed by characterization. 3. LCLK, CLKIN. 2.1.4 Power Consumption under Recommended Operating Conditions Conditions1 Typ Max Unit VDD Average Main Supply Current VIL = 0.5V, VIH = 2.4V No Load 14 20 mA VDD Quiescent Main Supply Current in VIL = VSS, VIH = VDD No Load 0.5 0.8 mA VSB Average Main Supply Current VIL = 0.5V, VIH = 2.4V No Load 21 30 mA VSB Quiescent Main Supply Current in VIL = VSS, VIH = VSB No Load 5 8 mA VDD, VSB = 0V, VBAT = 3V 0.9 1.5 µA Symbol IDD IDDLP Parameter Low Power Mode2 ISB ISBLP Low Power Mode2 IBAT VBAT Battery Supply Current 1. All parameters specified for 0° C ≤ TA ≤ 70° C; VDD and VSB = 3.3V ±10%, unless otherwise specified. 2. All the modules disabled; clock outputs disabled; no LPC or SMBus activity. 2.1.5 Voltage Thresholds Symbol Parameter1 Min2 Typ Max2 Unit VDDON VDD Detected as Power-on 2.3 2.6 2.9 V VDDOFF VDD Detected as Power-off 2.2 2.5 2.8 V VDDHY VDD Hysteresis (VDDON − VDDOFF) 50 VSBON VSB Detected as Power-on 2.3 2.6 2.9 V VSBOFF VSB Detected as Power-off 2.2 2.5 2.8 V VSBHY VSB Hysteresis (VSBON − VSBOFF) 50 VBATDTC Battery Detected 1.0 1.2 V VLOWBAT Low Battery Voltage 1.3 1.9 V mV mV 1. All parameters specified for 0° C ≤ TA ≤ 70° C. 2. Not tested. Guaranteed by characterization. Revision 1.0 21 www.national.com PC87427 2.0 Device Characteristics 2.2 (Continued) DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES The following tables summarize the DC characteristics of all device pins described in Section 1.2 on page 6. The characteristics describe the general I/O buffer types defined in Table 1 on page 6. For exceptions, refer to Section 2.2.10 on page 24. The DC characteristics of the LPC Interface meet the PCI Local Bus Specification (Rev 2.2 December 18, 1998) for 3.3V DC signaling. The DC characteristics of the SMBus Interface meet the SMBus (Rev 1.1 Dec. 11, 1998) and SMBus (Rev. 2.0 Aug. 2000) specifications for on-board devices. 2.2.1 Input, CMOS Compatible with Schmitt Trigger Symbol: INCS Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 0.75 VSUP1 5.52 V VIL Input Low Voltage −0.51 1.1 V VHY Input Hysteresis 5003 IIL Input Leakage Current mV ±14 0 < VIN < VSUP µA 1. VSUP is VDD, VSB or VPP according to the input power well. 2. Not tested. Guaranteed by design. 3. Not tested. Guaranteed by characterization. 4. Maximum 10 µA for all pins together. Not tested. Guaranteed by characterization. 2.2.2 Input, PCI 3.3V Symbol: INPCI Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 0.5 VDD VDD + 0.51 V VIL Input Low Voltage −0.51 0.3 VDD V lIL2 Input Leakage Current ±13 µA 0 < VIN < VDD 1. Not tested. Guaranteed by design. 2. Input leakage current includes the output leakage of the bidirectional buffers with TRI-STATE outputs. 3. Maximum 10 µA for all pins together. Not tested. Guaranteed by characterization. 2.2.3 Input, SMBus Compatible Symbol: INSM Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 1.4 5.51 V VIL Input Low Voltage −0.51 0.8 V IIL2 Input Leakage Current ±13 µA 0 < VIN < VSB 1. Not tested. Guaranteed by design. 2. Input leakage current includes the output leakage of the bidirectional buffers with TRI-STATE outputs. 3. Maximum 10 µA for all pins together. Not tested. Guaranteed by characterization. www.national.com 22 Revision 1.0 2.2.4 PC87427 2.0 Device Characteristics (Continued) Input, TTL Compatible Symbol: INT Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 2.0 5.51 V VIL Input Low Voltage −0.51 0.8 V IIL2 Input Leakage Current ±14 µA 0 < VIN < VSUP3 1. Not tested. Guaranteed by design. 2. Input leakage current includes the output leakage of the bidirectional buffers with TRI-STATE outputs. 3. VSUP is VDD, VSB or VPP according to the input power well. 4. Maximum 10 µA for all pins together. Not tested. Guaranteed by characterization. 2.2.5 Input, TTL Compatible with Schmitt Trigger Symbol: INTS Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 2.0 5.51 V VIL Input Low Voltage −0.51 0.8 V VHY Input Hysteresis 2502 IIL3 Input Leakage Current mV ±15 0 < VIN < VSUP4 µA 1. Not tested. Guaranteed by design. 2. Not tested. Guaranteed by characterization. 3. Input leakage current includes the output leakage of the bidirectional buffers with TRI-STATE outputs. 4. VSUP is VDD, VSB or VPP according to the input power well. 5. Maximum 10 µA for all pins together. Not tested. Guaranteed by characterization. 2.2.6 Output, TTL Compatible Push-Pull Buffer Symbol: Op/n Output, TTL Compatible, rail-to-rail Push-Pull buffer that is capable of sourcing p mA and sinking n mA Symbol VOH VOL Parameter Output High Voltage Output Low Voltage Conditions Min Max Unit IOH = −p mA 2.4 V IOH = −50 µA VSUP − 0.21 V IOL = n mA 0.4 V IOL = 50 µA 0.2 V 1. VSUP is VDD, VSB or VPP according to the output power well. Revision 1.0 23 www.national.com PC87427 2.0 Device Characteristics 2.2.7 (Continued) Output, Open-Drain Buffer Symbol: ODn Output, TTL Compatible Open-Drain output buffer capable of sinking n mA. Output from these signals is open-drain and is never forced high. Symbol Parameter VOL 2.2.8 Conditions Output Low Voltage Min Max Unit IOL = n mA 0.4 V IOL = 50 µA 0.2 V Max Unit Output, PCI 3.3V Symbol: OPCI Symbol Parameter Conditions Min 0.9 VDD VOH Output High Voltage lout = −500 µA VOL Output Low Voltage lout =1500 µA 2.2.9 V 0.1 VDD V Max Unit 0.1 VDD V Output, Open-Drain, PCI 3.3V Symbol: ODPCI Symbol VOL 2.2.10 Parameter Conditions lout =1500 µA Output Low Voltage Min Exceptions 1. All pins are 5-Volt tolerant except for the pins with PCI (INPCI, OPCI) buffer types. 2. All pins are back-drive protected except for the pins with PCI (INPCI, OPCI) and oscillator (OOSC) buffer types. 3. The following pins have an internal static pull-up resistor (when enabled) and therefore may have leakage current to VSUP (when VIN = 0): P12, P16, P17, SMBCLK, SMBDAT, SMBALERT, PWBTIN, SLBTIN, PWBTOUT, SIOSMI, SIOSCI GPIO00-07, GPIOE10-17, GPIO20-27, GPIO30-37, GPIOE40-47, GPO50-57 and GPIO60-63. 4. The following strap pins have an internal static pull-up resistor enabled during Power-Up reset and therefore may have leakage current to VSS (when VIN = VSUP): BADDR, TRIS, CKIN48, XCNF2-0, SMBSA, HFCKS, CTEST and TEST. 5. IOH is valid for a GPIO pin only when it is not configured as open-drain. 2.2.11 Terminology Back-Drive Protection. A pin that is back-drive protected does not sink current into the supply when an input voltage higher than the supply, but below the pin’s maximum input voltage, is applied to the pin. This is true even when the supply is inactive. Note that active pull-up resistors and active output buffers are typically not back-drive protected. 5-Volt Tolerance. An input signal that is 5V tolerant can operate with input voltage of up to 5V even though the supply to the device is only 3.3V. The actual maximum input voltage allowed to be supplied to the pin is indicated by the maximum high voltage allowed for the input buffer. Note that some pins have multiple buffers, not all of which are 5V tolerant. In such cases, there is a note that indicates at what conditions a 5V input may be applied to the pin; if there is no note, the low maximum voltage among the buffers is the maximum voltage allowed for the pin. www.national.com 24 Revision 1.0 2.3 PC87427 2.0 Device Characteristics (Continued) INTERNAL RESISTORS DC Test Conditions Pull-Down Resistor Test Circuit Pull-Up Resistor Test Circuit VSUP VSUP Device Under Test Device Under Test IPU RPU VSUP Pin IPD Pin A A VPIN RPD V V VPIN Figure 1. Internal Resistor Test Conditions, TA = 0 °C to 70 °C, VSUP = 3.3V VSUP Device Under Test VSUP VPIN > VIH Device Under Test IPU RPU Pin VSUP VPIN < VIL 10µA RPU IPU Pin A VPIN V A 10µA VPIN V 10 KΩ Figure 2. Internal Pull-Up Resistor for Straps, TA = 0 °C to 70 °C, VSUP = 3.3V Notes for Figures 1 and 2: 1. VSUP is VDD or VSB according to the pin power well. 1. The equivalent resistance of the pull-up resistor is calculated by RPU = (VSUP − VPIN) / IPU. 2. The equivalent resistance of the pull-down resistor is calculated by RPD = VPIN / IPD. 2.3.1 Pull-Up and Pull-Down Resistors Symbol: PUnn, PDnn Symbol Parameter RPU Pull-up equivalent resistance RPD Pull-down equivalent resistance Conditions1 Min2 Typical Max2 Unit VPIN = 0V nn−30% nn nn+30% KΩ VPIN = VSUP nn−30% nn nn+30% KΩ nn−50% KΩ VPIN = 0.17 VSUP3 VPIN = 0.8 VSUP3 nn−48% KΩ 1. TA = 0 °C to 70 °C, VSUP = 3.3V. 2. Not tested. Guaranteed by characterization. 3. For strap pins only. Revision 1.0 25 www.national.com PC87427 2.0 Device Characteristics 2.4 (Continued) PACKAGE THERMAL INFORMATION Thermal resistance (degrees C/W) ThetaJC and ThetaJA values for the PC87427 package are as follows: Table 4. Theta (Θ) J Values Package Type [email protected] lfpm [email protected] lfpm [email protected] lfpm 128 PQFP 47 35.8 31.1 ThetaJC 14.9 Note: Airflow for ThetaJA values is measured in linear feet per minute (lfpm). 2.5 2.5.1 AC ELECTRICAL CHARACTERISTICS AC Test Conditions Load Circuit VSUP AC Testing Input, Output Waveform S1 2.4 0.1 µf 0.4 2.0 0.8 Test Points 2.0 0.8 RL Input Device Under Test Output CL Figure 3. AC Test Conditions, TA = 0°C to 70°C, VSUP = 3.3V ±10% Notes: 1. VSUP is VDD, VSB or VPP according to the pin power well. 1. CL = 50 pF for all output pins except the following pin groups: CL = 100 pF for Serial Port 1, 2 and M (see Section 1.4.4 on page 10) and Floppy Disk Controller (see Section 1.4.9) pins; CL = 40 pF for HFCKOUT pin; CL = 400 pF for SMBus pins (see Section 1.4.2 on page 9); These values include both jig and oscilloscope capacitance. 2. S1 = Open for push-pull output pins. S1 = VSUP for high impedance to active low and active low to high impedance transition measurements. S1 = GND for high impedance to active high and active high to high impedance transition measurements. RL = 1.0 KΩ for all the pins. 3. For the FDC open-drain interface pins, S1 = VDD and RL = 150 Ω. www.national.com 26 Revision 1.0 2.5.2 PC87427 2.0 Device Characteristics (Continued) Reset Timing VSB Power-Up Reset Symbol Figure Description tLRST 5 Minimum LRESET active time 4 Reference Conditions Internal Power-Up Reset Time tIRST VSB power-up to end of LRESET VSB power-up to end of internal reset Ended by 32 KHz Clock Domain Min1 10 ms t32KW + 17 * t32KOSC Ended by LRESET 5 Max1 t32KVAL2 + 17 * t32KOSC tLRST tEPLV 4, 5 External strap pull-down resistors, valid time Before end of internal reset tIRST tIPLV 4, 5 Internal strap pull-up resistors, valid time3 Before end of internal reset tIRST 1. Not tested. Guaranteed by design. 2. t32KW + t32KVAL from VBAT power-up to 32 KHz domain toggling if VSB and VBAT are powered-up together; see “Low Frequency Clock Timing” on page 31. 3. Active only during VSB Power-Up reset. VSB (Power) VSBONmin t32KOSC t32KW + t32KVAL 32 KHz Domain (Internal) tIRST VSB Power-Up Reset (Internal) LRESET tIPLV Internal Straps (Pull-Up) tEPLV External Straps (Pull-Down) Figure 4. Internal VSB Power-Up Reset - Ended by 32 KHz Clock Domain Revision 1.0 27 www.national.com PC87427 2.0 Device Characteristics (Continued) VSBONmin VSB (Power) tK32OSC t32KW + t32KVAL 32 KHz Domain (Internal) tIRST VSB Power-Up Reset (Internal) tLRST LRESET tIPLV Internal Straps (Pull-Up) tEPLV External Straps (Pull-Down) Figure 5. Internal VSB Power-Up Reset - Ended by LRESET VDD Power-Up Reset Description Reference Conditions Min1 Symbol Figure tLRST 6 Minimum LRESET active time tIRST 6 Internal Power-Up reset time VDD power-up to end of internal reset tIPLV 6 Internal strap pull-up resistors, valid time2 Before end of internal reset tIRST tEPLV 6 External strap pull-down resistors, valid time Before end of internal reset tIRST VDD power-up to end of LRESET Max1 10ms tLRST 1. Not tested. Guaranteed by design. 2. Active only during VDD Power-Up reset. VDD (Power) VDDONmin VDD Power-Up Reset (Internal) tIRST tLRST LRESET tIPLV Internal Straps (Pull-Up) tEPLV External Straps (Pull-Down) Figure 6. Internal VDD Power-Up Reset www.national.com 28 Revision 1.0 PC87427 2.0 Device Characteristics (Continued) Hardware Reset Symbol Figure tWRST 7 Description Reference Conditions LRESET pulse width Min Max 100 ns Internal Clock tWRST LRESET Figure 7. Hardware Reset Revision 1.0 29 www.national.com PC87427 2.0 Device Characteristics 2.5.3 (Continued) Clock Timing High Frequency Clock Timing CLKIN (48 MHz) Symbol Figure Clock Input Parameters Reference Conditions Min tCH 8 Clock High Pulse Width1 8 tCL 8 Clock Low Pulse Width1 8 tCP 8 Clock Period1 (50%-50%) FCK − Clock Frequency 8 tCR 8 tCF Typ Max ns ns 20.2 20.83 FCKTYP − 3% Clock Fall Time1 (80%-20%) 9 Clock Wake-Up Time tCINVAL 9 Clock Valid Time1 After VSB > VSBON Clock start toggling to clock within specification 21.5 ns 48 + 3% MHz F (FCKTYP) CKTYP Clock Rise Time1 (20%-80%) tCINW Units 2.22 ns 2.22 ns 33 ms System dependent 1. Not tested. Guaranteed by design. 2. Recommended value HFCKOUT (48 MHz) Symbol Figure HFCKOUT (40 MHz) Clock Output Parameter Min Typ Max Min Typ Max Units tCH 8 Clock High Pulse Width1,2 8.2 10.3 ns tCL 8 Clock Low Pulse Width1,2 8.2 10.3 ns tCP 8 Clock Period3 (50%-50%) tCR tCF 8 8 t48TYP − 4− 32KTOL 50ppm 20.83 (t48TYP) t40TYP − t48TYP + 32KTOL4 + 50ppm 4− 32KTOL 150ppm 25 (t40TYP) ns t40TYP + 32KTOL4 + 150ppm Clock Rise Time CL = 15 pF (20%-80%) CL = 40 pF 2.5 2.5 ns 5 5 ns Clock Fall Time2 CL = 15 pF (80%-20%) CL = 40 pF 2.5 2.5 ns 5 5 ns 2 1. CL = 15 pF. 2. Not tested. Guaranteed by characterization. 3. Not tested. Guaranteed by design. 4. 32KTOL = tolerance of t32KCLKIN parameter; see Low Frequency Clock Timing. tCP tCH CLKIN HFCKOUT x= I , for In O, for Out VxH VxH VxH VxL VxL VxL tCL tCF tCR Figure 8. Clock Waveform Timing www.national.com 30 Revision 1.0 VDD (Power) PC87427 2.0 Device Characteristics (Continued) VDDONmin tCP (CLKIN) tCINVAL tCINW CLKIN (48 MHz) Figure 9. CLKIN Timing Low Frequency Clock Timing Symbol Figure Description Reference Conditions Min Typ Max Units 30.5145 (t32TYP − 100ppm) 30.517578 (t32TYP) 30.5206 (t32TYP + 100ppm) µs Clock Input Timing t32KCLKIN – Required clock period for 32KCLKIN1 From RE to RE of 32KCLKIN. Clock Output Timing µs t32KOSC 10 Clock period of the internal From RE to RE of LFCKOUT. oscillator2 t32KW+ t32KVAL 10 32K oscillator wake-up time3 After VBAT > VLOWBAT 1 sec t32KD 11 Internally generated After VSB > VSBON 40/48 MHz clock delay time3 33 ms 30.517578 (t32TYP) 1. Recommended for RTC timekeeping accuracy and for HFCKOUT, LFCKOUT frequency accuracy. 2. Determined by the values of the external crystal circuit components. 3. Not tested. Guaranteed by characterization. VBAT t32KW t32KOSC t32KVAL 32KX1/32KCLKIN 0V 32KX2 0V 32KHz Domain (Internal) Figure 10. Low Frequency Clock Waveforms Revision 1.0 31 www.national.com PC87427 2.0 Device Characteristics (Continued) VBAT 0V VSB t32KD Internally Generated 40/48 MHz Clock CKVALID (internal) Figure 11. Internal Clock Waveforms 2.5.4 LPC Interface Timing The AC characteristics of the LPC Interface meet the PCI Local Bus Specification (Rev 2.2 December 18, 1998) for 3.3V DC signaling. LCLK and LRESET Symbol Parameter Min Max Units tCYC1 LCLK Cycle Time 30 ns tHIGH LCLK High Time2 11 ns tLOW LCLK Low Time2 11 ns - LCLK Slew Rate2,3 1 - LRESET Slew Rate2,4 50 4 V/ns mV/ns 1. The PCI may have any clock frequency between nominal DC and 33 MHz. Device operational parameters at frequencies under 16 MHz are guaranteed by design rather than by testing. The clock frequency may be changed at any time during the operation of the system as long as the clock edges remain “clean” (monotonic) and the minimum cycle high and low times are not violated. The clock may only be stopped in a low state. 2. Not tested. Guaranteed by characterization. 3. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock wavering (0.2 VDD to 0.6 VDD) as shown below. 4. The minimum LRESET slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system noise cannot make an otherwise monotonic signal appear to bounce in the switching range. VDD = 3.3V ±10% tHIGH tLOW 0.6 VDD 0.5 VDD 0.4 VDD p-to-p (minimum) 0.4 VDD 0.3 VDD 0.2 VDD tCYC www.national.com 32 Revision 1.0 PC87427 2.0 Device Characteristics (Continued) SERIRQ and LPC Signals Symbol Figure Description tVAL Output Output Valid Delay tON Output tOFF Output tSU tHL Reference Conditions Min Max Unit After RE CLK 2 11 ns Float to Active Delay After RE CLK 21 Active to Float Delay After RE CLK Input Input Setup Time Before RE CLK 7 ns Input Input Hold Time After RE CLK 0 ns ns 281 ns 1. Not tested. Guaranteed by characterization. Outputs VDD = 3.3V ±10% LCLK 0.4 VDD 0.4 VDD tVAL tVAL LAD3-LAD0, LDRQ, SERIRQ 0.615 VDD 0.285 VDD tON LAD3-LAD0, Leakage Only SERIRQ VDD = 3.3V ±10% LCLK tOFF Output Enabled Inputs 0.4 VDD tSU LAD3-LAD0, LFRAME LRESET, SERIRQ Revision 1.0 Leakage Only tHL 0.4 VDD 33 www.national.com PC87427 2.0 Device Characteristics 2.5.5 (Continued) X-Bus Extension Timing Symbol Figure Description Reference Conditions tVAL Outputs Output Valid Delay After RE Internal Clock tVAL_CS Outputs Output Valid Delay for XCS3-0, XWR_XRW After RE Internal Clock tVAL_XD Outputs tON Min Max Unit CL = 50 pF 221 ns CL = 20 pF 121 ns CL = 20 pF 171 ns CL = 50 pF 201 ns Output Valid Delay for XA19_XD15-XA4_XD0 After RE Internal Clock Outputs Float to Active Delay After RE Internal Clock 02 ns tOH Outputs Output Hold time After RE Internal Clock 02 ns tOFF Outputs Active to Float Delay After RE Internal Clock tSU Inputs Input Setup Time Before RE Internal Clock 51 ns tHL Inputs Input Hold Time After RE Internal Clock 01 ns tCSDV tSP4D Mode 0, Speed Read from External Grades 3, 4, Chip Select active to Data Valid Device Read Transaction Mode 0, Speed Chip Select active to Grade 4, Write XWR_XRW active delay Transaction CL = 50 pF 301 ns CL = 20 pF 73 ns CL = 50 pF 70 ns 0.5 ns Write to External Device CL = 20 pF − 0.51 1. Not tested. Guaranteed by characterization. 2. Not tested. Guaranteed by design. Outputs Internal Clock (for reference only; not available off chip) tVAL tOH tON XA11-0, XRD_XEN, XSTB2-0, BIOS_SEL tOFF tVAL_CS tOH tON XCS3-0, XWR_XRW tOFF tVAL_XD tOH tON XA19_XD15-XA4_XD0 tOFF www.national.com 34 Revision 1.0 PC87427 2.0 Device Characteristics (Continued) Inputs Internal Clock (for reference only: not available off chip) tSU XD15-0 XRDY, XIRQ tHL Input Valid Mode 0, Speed Grades 3, 4, Read Transaction XCS3-0 tCSDV Data Valid XD15-0 Mode 0, Speed Grade 4, Write Transaction XCS3-0 XWR_XRW tSP4D Revision 1.0 35 www.national.com PC87427 2.0 Device Characteristics 2.5.6 (Continued) SMBus Timing Type of Requirement1 Symbol Figure Description tSMBR 12 Rise time (SMBCLK and SMBDAT) tSMBF 12 Fall time (SMBCLK and SMBDAT) Min Max Unit Input2 10003 ns Input 3003 ns Output2 2504 ns tSMBCKL 12 Clock low period (SMBCLK) Input 4.7 µs tSMBCKH 12 Clock high period (SMBCLK) Input 4 µs tSMBCY 13 Clock cycle (SMBCLK) Input 10 µs tSMBDS 13 Data setup time (before clock rising edge) Input 250 ns 250 ns Input 0 ns Output2 300 ns Output tSMBDH 13 Data hold time (after clock falling edge) 2 tSMBPS 14 Stop condition setup time (clock before data) Input 4 µs tSMBSH 14 Start condition hold time (clock after data) Input 4 µs tSMBBUF 14 Bus free time between Stop and Start conditions (SMBDAT) Input 4.7 µs tSMBRS 15 Restart condition setup time (clock before data) Input 4.7 µs tSMBRH 15 Restart condition hold time (clock after data) Input 4 µs tSMBLEX - Cumulative clock low extend time from Start to Stop (SMBCLK) Output tSMBTO - Clock low time-out (SMBCLK) Input ms 253 ms 253,5 Output ms 353,6 1. An “Input” type is a value the PC87427 expects from the system; an “Output” type is a value the PC87427 provides to the system. 2. Test conditions: RL = 1 KΩ to VSB = 3.3V, CL = 400 pF to GND. 3. Not tested. Guaranteed by design. 4. Not tested. Guaranteed by characterization. 5. The PC87427 detects a time-out condition if SMBCLK is held low for more than tSMBTO. 6. Upon detection of a time-out condition, the PC87427 resets the SMBus Interface no later than tSMBTO. tSMBCKH 3.0V 2.5V 2.5V 0.4V 0.4V tSMBR 0.4V tSMBCKL 0.4V tSMBF Figure 12. SMBus Signals (SMBCLK and SMBDAT) Rising Time and Falling Time www.national.com 36 Revision 1.0 PC87427 2.0 Device Characteristics (Continued) SMBDAT tSMBDH tSMBDS SMBCLK tSMBCY Figure 13. SMBus Data Bit Timing Start Condition Stop Condition SMBDAT tSMBDS SMBCLK tSMBPS tBUF tSMBSH Figure 14. SMBus Start and Stop Condition Timing Restart Condition SMBDAT SMBCLK tSMBDS tSMBRS tSMBRH Figure 15. SMBus Restart Condition TIming Revision 1.0 37 www.national.com PC87427 2.0 Device Characteristics 2.5.7 (Continued) GPE Timing Symbol Figure tVAL Outputs tSU tHL Description Reference Conditions Min CL = 20 pF Max Unit 41 ns Output Valid Delay After clock falling edge Inputs Input Setup Time Before clock rising edge 121 ns Inputs Input Hold Time After clock rising edge 01 ns 1. Not tested. Guaranteed by characterization. GPEXC/C2 tSU tHL Input Valid GPEXD GPEXC/C2 tVAL Output Valid GPEXD www.national.com 38 Revision 1.0 2.5.8 PC87427 2.0 Device Characteristics (Continued) FDC Timing FDC Write Data Timing Symbol Parameter Min Max Unit tHDH HDSEL Hold from WGATE Inactive1 100 µs tHDS HDSEL Setup to WGATE Active1 100 µs tWDW Write Data Pulse Width1 See tDRP, tICP and tWDW values in table below 1. Not tested. Guaranteed by design. HDSEL WGATE tHDS tHDH tWDW WDATA tDRP tICP tWDW Values Data Rate tDRP tICP tICP Nominal tWDW tWDW Minimum Unit 1 Mbps 1000 6 x tCP1 125 2 x tICP 250 ns 500 Kbps 2000 6 x tCP1 125 2 x tICP 250 ns 300 Kbps 3333 10 x tCP1 208 2 x tICP 375 ns 250 Kbps 4000 12 x tCP1 250 2 x tICP 500 ns 1. tCP is the clock period defined for CLKIN in Clock Timing on page 30. FDC Drive Control Timing Symbol Parameter Min Max Unit 6 µs Index Pulse Width 100 ns tSTD DIR Hold from STEP Inactive tSTR ms tSTP STEP Active High Pulse Width1 8 µs tSTR STEP Rate Time1 0.5 ms tDST DIR Setup to STEP Active1 tIW 1. Not tested. Guaranteed by design. Revision 1.0 39 www.national.com PC87427 2.0 Device Characteristics (Continued) DIR tSTD tDST STEP tSTP tSTR INDEX tIW FDC Read Data Timing Symbol tRDW Parameter Min Read Data Pulse Width Max Unit 50 ns Conditions Min Max Unit Transmitter tBTN − 252 tBTN + 252 ns Receiver tBTN − 2%2 tBTN + 2%2 ns tRDW RDATA 2.5.9 Serial Interfaces 1, 2 and M Timing Serial Port Data Timing Symbol tBT Parameter Single Bit Time in Serial Interface1 1. Not tested. Guaranteed by design. 2. tBTN is the nominal bit time in the Serial Interface; it is determined by the setting of the Baud Generator Divisor registers. SIN SOUT www.national.com tBT 40 Revision 1.0 PC87427 2.0 Device Characteristics (Continued) Modem Control Timing Symbol Parameter Min Max Unit tL RI Low Time1,2 10 ns tH RI High Time1,2 10 ns tSIM Delay to Set IRQ from Modem Input 40 ns 1. Not tested. Guaranteed by characterization 2. This value also applies to RI2,1 wake-up detection in the SWC module. CTS, DSR, DCD tSIM tSIM INTERRUPT (Read MSR) (Read MSR) tSIM tL tH RI 2.5.10 SWC Timing Wake-Up Inputs at VSB Power Switching Symbol Figure Description Reference Conditions tEWIV 16 External Wake-up inputs not At VSB power on, after the 32 KHz Domain is toggling valid1 tPBOP 17 PWBTOUT pulse time1 Resume by SLPS3, SLPS5 after Power Fail Min Max 24576 * t32KOSC2 32768 * t32KOSC 100 ms3 100.03 ms 1. Not tested. Guaranteed by design. 2. t32KOSC is the cycle time of the 32 KHz clock domain (see “Low Frequency Clock Timing” on page 31) 3. Except when generated by PWBTIN pulse. Revision 1.0 41 www.national.com PC87427 2.0 Device Characteristics VSB (Power) (Continued) VSBOFF VSBON tIRST VSB Power-Up Reset (Internal) t32KW + t32KVAL 32 KHz Clock (internal) tEWIV GPIOE10-17, GPIOE40-47 RI1, RI2 PWBTIN, SLBTIN XIRQ2-0 KBCLK, MCLK KBDAT, MDAT SLPS3, SLPS5 Figure 16. Inputs at VSB Power Switching (No VBAT) VSB (Power) VSBOFF VSBON tIRST VSB Power-Up Reset (Internal) t32KW + t32KVAL 32 KHz Clock (internal) tEWIV SLPS3, SLPS5 ONCTL TRI-STATE tPBOP PWBTOUT TRI-STATE Figure 17. Resume by SLPS3, SLPS5, After Power Fail (No VBAT) www.national.com 42 Revision 1.0 PC87427 2.0 Device Characteristics (Continued) Wake-Up Inputs at VDD Power Switching Symbol Figure tEWIV 18 Description External Wake-up inputs valid1 Reference Conditions After VDD power On2 Min Max 24576 * t32KOSC3 32768 * t32KOSC 1. Not tested. Guaranteed by design. 2. The 32 KHz clock domain is assumed to be toggling at VDD power stable. 3. t32KOSC is the cycle time of the 32 KHz clock domain (see “Low Frequency Clock Timing” on page 31) VDDON VDDOFF VDD (Power) tEWIV GPIOE10-17, GPIOE40-47 (VDDLOAD=1) Figure 18. Wake-Up Inputs at VDD Power Switching Power Button Override Symbol Figure Description tPBOV 19 Power Button Override1 tOVEX 19 tPBID 19 Reference Conditions Min Max After PWBTIN active 3.89 s 3.92 s Power Button Override Extension1 After the end of tPBOV 0.2 s 0.24 s PWBTIN disable time1 After a Power-Off event 1s 1.25 s 1. Not tested. Guaranteed by design. tPBOV tOVEX tPBID PWBTIN PWBTOUT ONCTL Figure 19. Power Button Override Timing Revision 1.0 43 www.national.com PC87427 2.0 Device Characteristics (Continued) Crowbar Symbol Figure tCBTO 20, 21 tCBPBO tPBID Description Reference Conditions Min Max Crowbar Timeout1 After ONCTL active, or VDD power fall 0.5 s2 20 s2 20, 21 Crowbar generated, PWBTOUT pulse time1 After completion of Crowbar Timeout 4s 4.25 s 20, 21 PWBTIN disable time1 After a Power-Off event 1s 1.25 s 1. Not tested. Guaranteed by design. 2. Set by CRBAR_TOUT. tPBID PWBTIN tCBPBO PWBTOUT ONCTL tCBTO VDD (Power) Figure 20. Power-On Crowbar Timing tPBID PWBTIN tCBPBO PWBTOUT ONCTL tCBTO VDD (Power) Figure 21. Power-Fall Crowbar Timing www.national.com 44 Revision 1.0 PC87427 2.0 Device Characteristics (Continued) System Watchdog Power-Off / ETC Symbol Figure Description tPBO 22 PWBTOUT pulse time1 tPBID 22 PWBTIN disable time1 Reference Conditions After a Power-Off event Min Max 4s 4.25 s 1s 1.25 s tPBID PWBTIN tPBO PWBTOUT ONCTL VDD (Power) Figure 22. Watchdog Power-Off / ETC Timing Revision 1.0 45 www.national.com PC87427 ServerI/O with SensorPath™ Health Monitoring Physical Dimensions All dimensions are in millimeters Plastic Quad Flatpack (PQFP), JEDEC Order Number PC87427-xxx/VLA NS Package Number VLA128A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Email: [email protected] 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 87 90 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 Email: [email protected] www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.