Datasheet

UNISONIC TECHNOLOGIES CO., LTD
U74HCT165
CMOS IC
8-BIT PARALLEL-LOAD SHIFT
REGISTER

DESCRIPTION
The U74HCT165 is an 8-bit parallel-load shift register that,
when clocked, shifts the data toward a serial (QH) output.
Parallel-in access to each stage is provided by eight individual
direct data (A-H) inputs these are enabled by a low level at
SOP-16
shift/load (SH/ LD ) input. The U74HCT165 also features a
clock-inhibit (CLK INH) function and a complementary serial ( QH )
output.
Clocking is accomplished by a low-to-high transition of the
clock (CLK) input while SH/ LD is held high and CLK INH is held
low. The functions of CLK and CLK INH are interchangeable.
Since a low CLK and a low-to-high transition of CLK INH also
accomplish clocking, CLK INH should be changed to the high
level only while CLK is high. Parallel loading is inhibited when
SH/ LD is held high. While SH/ LD is low, the parallel inputs to
the register are enabled independently of the levels of the CLK,
CLK INH, or serial (SER) inputs.
The inputs are compatible with TTL,NMOS and CMOS output
voltage levels.

FEATURES
* Complementary Outputs
* Direct Overriding Load (Data) Inputs
* Gated Clock Inputs
* Parallel-to-Serial Data Conversion
* Compatible with TTL, NMOS, CMOS output voltage levels

ORDERING INFORMATION
Ordering Number
U74HCT165G-S16-R
U74HCT165G-S16-R

Package
SOP-16
(1) Packing Type
(1) R: Tape Reel
(2) Package Type
(2) S16: SOP-16
(3) Green Package
(3) G: Halogen Free and Lead Free
Packing
Tape Reel
MARKING
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U74HCT165
CMOS IC

PIN CONFIGURATION

FUNCTION TABLE
Operating Modes
Parallel Load
Serial Shift
Hold “Do Nothing”
Inputs
Qn Registers
Outputs
SH/ LD
CLK/INH
CLK
SER
A to H
Q0
Q1 to Q6
QH
QH
L
L
X
X
X
X
X
X
L
H
L
H
L to L
H to H
L
H
H
L
H
L
↑
I
X
L
q0 to q 5
q6
q6
H
L
↑
h
X
H
q0 to q 5
q6
q6
H
↑
L
I
X
L
q0 to q 5
q6
q6
H
↑
L
h
X
H
q0 to q 5
q6
q6
H
H
X
X
X
Q0
q1 to q6
q7
q7
H
X
H
X
X
Q0
q1 to q6
q7
q7
Notes: H=HIGH Voltage Level;
h= HIGH Voltage Level one set-up time prior to the LOW-to-HIGH clock transition;
L=LOW Voltage Level;
l= LOW Voltage Level one set-up time prior to the LOW-to-HIGH clock transition;
q=state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X=don’t care;
↑= LOW-to-HIGH clock transition.
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U74HCT165

LOGIC SYMBOL

LOGIC DIAGRAM (positive logic)
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CMOS IC
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U74HCT165

CMOS IC
TYPICAL SHIFT, LOAD, AND INHIBIT SEQUENCE
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U74HCT165

CMOS IC
ABSOLUTE MAXIMUM RATING
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage
VCC
-0.5 ~ 7
V
VCC or GND Current
ICC
±50
mA
Output Current
IOUT
±25
mA
Input Clamp Current
IIK
±20
mA
Output Clamp Current
IOK
±20
mA
Storage Temperature
TSTG
-65 ~ + 150
°C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.

RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
VCC
Supply Voltage
High-level Input Voltage
VIH
Low-level Input Voltage
VIL
Input Voltage
Output Voltage
Input Transition (Rise and Fall) Time
Operating Free-air Temperature

VIN
VOUT
tt
TA
VCC=4.5V
VCC=5.5V
VCC=4.5V
VCC=5.5V
MIN
4.5
2
2
0
0
VCC=4.5V
-40
TYP MAX UNIT
5
5.5
V
V
V
0.8
V
0.8
V
VCC
V
VCC
V
500
ns
+125 °C
THERMAL DATA
PARAMETER
Junction to Ambient

TEST CONDITIONS
SYMBOL
θJA
RATINGS
73
UNIT
°C/W
ELECTRICAL CHARACTERISTICS (TA =25°C , unless otherwise specified)
PARAMETER
SYMBOL
Output Voltage High-Level
VOH
Output Voltage Low-Level
VOL
Input Leakage Current
Quiescent Supply Current
II(LEAK)
ICC
Additional supply current
Input Capacitance
△ICC
TEST CONDITIONS
VCC=4.5V, IOH=-20μA
VCC=4.5V, IOH=-4mA
VCC=4.5V, IOH=20μA
VCC=4.5V, IOL=4mA
VCC=5.5V, VIN= VCC or GND
VCC=5.5V, VIN=VCC or GND
TYP MAX UNIT
4.5
V
4.32
V
0
0.1
V
0.15 0.26
V
±100 nA
8
μA
VI=VCC-2.1V,other inputs at VCC or
GND,VCC=4.5V to 5.5V, DS, Dn inputs
35
126
uA
VI=VCC-2.1V, other inputs at VCC or GND,
VCC=4.5V to 5.5V,
CLK, CLKINH, SH / LD inputs
65
234
uA
CI
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MIN
4.4
3.98
3.5
pF
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
CMOS IC
TIMING REQUIREMENTS (TA =25°C , unless otherwise specified)
PARAMETER
SYMBOL
Clock frequency
Pulse duration
Setup time
Hold time

fCLOCK
CLK high input
tW
SH/ LD low input
DS before CLK,CLK INH
CLK INH to CLK, CLK to CLK INH
tSU
Dn to SH/ LD
DS to CLK,CLK INH
CLK to CLK INH,CLK INH to CLK
th
MIN
26
16
TYP MAX UNIT
44
MHz
48
MHz
6
ns
VCC=4.5V
20
9
ns
VCC=4.5V
VCC=4.5V
20
20
2
7
ns
ns
VCC=4.5V
20
10
VCC=4.5V
VCC=4.5V
7
0
ns
ns
ns
SWITCHING CHARACTERISTICS (tr = tf = 6ns, CL=50pF, TA =25°C, unless otherwise specified)
PARAMETER
SYMBOL
Propagation delay FROM SH/ LD to QH or QH
Propagation delay FROM CLK, CLK, INH to QH or
tPD
QH
Propagation delay FROM D7 to QH or QH
FROM QH or QH

TEST CONDITIONS
VCC=4.5V
VCC=5V, CL=15pF
VCC=4.5
tt
Condition
VCC=4.5V
VCC=5V, CL=15pF
MIN
VCC=4.5V
TYP MAX UNIT
20
40
ns
17
Ns
17
40
Ns
VCC=5V, CL=15pF
14
VCC=4.5V
VCC=5V, CL=15pF
14
11
35
Ns
ns
VCC=4.5V
7
15
ns
Ns
OPERATING CHARACTERISTICS (TA =25°C , unless otherwise specified)
PARAMETER
Power Dissipation Capacitance
SYMBOL
TEST CONDITIONS
CPD
No load
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MIN
TYP MAX UNIT
35
pF
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U74HCT165

CMOS IC
TEST CIRCUIT AND WAVEFORMS
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U74HCT165

CMOS IC
TEST CIRCUIT AND WAVEFORMS (Cont.)
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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