Data Sheet

NE57810TK
Advanced DDR memory termination power with external
reference voltage in
Rev. 5 — 9 January 2013
Product data sheet
1. Introduction
The NE57810TK is designed to provide power for termination of a Double Data Rate
(DDR) SDRAM memory bus. It significantly reduces parts count, board space, and overall
system cost compared to previous solutions.
2. General description
The NE57810TK DDR termination regulator maintains an output voltage (DDR reference
bus voltage) that is half the RAM supply voltage. It is capable of providing up to  3.5 A for
sustained periods. Overcurrent limiting protects the NE57810TK from inrush currents at
start-up. Overtemperature shutdown protects the device in extreme temperature
situations.
The package is thermally robust for flexibility of thermal design. The NE57810TK is a
linear regulator so no external inductors or switching FETs are necessary. Fast response
to load changes reduces the need for output capacitors.
3. Features and benefits









Fast transient response time
Overtemperature protection
Overcurrent protection
Commercial (0 C to +70 C) temperature range
Reduced need for external components (switching FETs, inductors, decoupling
capacitors)
Internal divider maintains termination voltage at half the memory supply voltage
Reference out for other memory and control components
Optional external voltage reference in for flexible application
Compatible with DDR-I (VDD = 2.5 V) or DDR-II (VDD = 1.8 V) SDRAM systems
4. Applications






Desktop microcomputer systems
Workstations
Servers
Game machines
Set top boxes
Embedded systems
NE57810TK
NXP Semiconductors
Advanced DDR memory termination power with external reference
voltage in
 Digital video recorders
5. Ordering information
Table 1.
Ordering information
Type number
NE57810TK
Package
Name
Description
Version
HVSON10
plastic thermal enhanced very thin small outline package; no leads;
10 terminals; body 10  10 mm  0.85 mm
SOT1325-1
6. Functional diagram
DIMM0
DIMM1
ExtRefIn
(optional)
RefOut
0.1 μF
Control
and address
VTT
NE57810TK
Data
MEMORY
CONTROLLER
100 μF
TERMINATOR
POWER
RS
27 Ω (typical)
RT
27 Ω (typical)
014aaa407
Fig 1.
Simplified system diagram
NE57810TK
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 January 2013
© NXP B.V. 2013. All rights reserved.
2 of 18
NE57810TK
NXP Semiconductors
Advanced DDR memory termination power with external reference
voltage in
7. Pinning information
7.1 Pinning
WHUPLQDO
LQGH[DUHD
977
*1'
9''
*1'
966
*1'
([W5HIOQ
*1'
5HI2XW
*1'
1(7.
DDD
7UDQVSDUHQWWRSYLHZ
Fig 2.
NE57810TK pinning diagram
7.2 Pin description
Table 2.
Pin
Description
VTT
1
regulated termination voltage
VDD
2
power supply
VSS
3
circuit ground[1]
ExtRefIn
4
external reference voltage in
RefOut
5
reference voltage out
GND
6
ground
GND
7
ground
GND
8
ground
GND
9
ground
GND
10
ground
[1]
NE57810TK
Product data sheet
Pin description
Symbol
The thermal pad on the rear of the device (shown by dotted outline) is connected electrically to VSS
internally and provides enhancement to thermal conductivity. It should not be used as the primary
connection to ground as device specifications indicate the use of the VSS pin for this purpose.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 January 2013
© NXP B.V. 2013. All rights reserved.
3 of 18
NE57810TK
NXP Semiconductors
Advanced DDR memory termination power with external reference
voltage in
8. Application design-in information
The NE57810TK can be used in a variety of DDR memory configurations. Its small
footprint, fast transient response and reduced need for large bulk output capacitance,
makes it highly adaptable. Some of examples methods of use are described in the
following sections.
8.1 Normal operating mode (VTT = VDDR/2)
The most common implementation of a DDR terminator regulator using the NE57810TK is
shown in Figure 3. The NE57810TK has an internal resistor divider between the VDD (pin
2) and VSS (pin 3) pins which maintains the output voltage, VTT, at VDD/2.
Typically, the VDD voltage is the DDR RAM supply voltage, which can range from
1.8 V to 2.5 V. The center node of this resistor divider is connected to ExtRefIn (pin 4).
This node acts as the reference for the VTT output voltage and the buffered RefOut signal
(pin 5).
If the ExtRefIn pin is not connected to other voltage sources, two small bypass capacitors
(0.01 F) should be placed between the ExtRefIn pin and the VSS and VDD pins to improve
the terminator’s noise performance. These two capacitors improve enable the terminator
to better track any variations in the memory VDD voltage. This method can be seen in
Figure 3.
+VDD
2
1
VDD
0.01μF
+VTT
NE57810TK
CIN
4
RefOut
ExtRefIn
5
COUT
(LF)
0.01μF
COUT
(HF)
VSS
3
GND
GND
VREF
Fig 3.
014aaa409
Normal operating method (VTT = VDD/2)
There are two components to the memory signal load: a high frequency component
caused by the 266 MHz plus speed of the address, data and control buses, and a low
frequency component caused by the time-average skew of all of the bus states away from
an equal number of 1s and 0s. Electrolytic and tantalum capacitors show inductance at
the high frequencies, so two types of capacitors are required for output filtering.
A very good, low ESR bulk electrolytic capacitor of no less than 470 F should be placed
next to the terminator which, in turn, should be placed as close as possible to the memory
array. Multiple high frequency ceramic filter capacitors are also needed for high speed
transient filtering and output stability. These capacitors may be from VTT to VSS (shown in
the diagrams) or one half from VTT to VDD and the other half from VTT to VSS so the output
will better track any variations in the VDD voltage.
NE57810TK
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 January 2013
© NXP B.V. 2013. All rights reserved.
4 of 18
NE57810TK
NXP Semiconductors
Advanced DDR memory termination power with external reference
voltage in
For different memory sizes, the values of the recommended output filter capacitances will
change. For a 256 MB memory space, for example, approximately 100 F of ceramic
surface mount chip capacitors should be evenly distributed across the physical memory
layout. Depending upon the PCB noise environment, this can be 10 pieces of 10 F,
20 pieces of 5 F, and so on.
8.2 Externally programmed VTT output voltage
The NE57810TK enables use of an external reference voltage to set its VTT output
voltage. This pin (ExtRefIn pin 4) is used for applications where the VTT voltage is not VDD
divided by 2. This allows VTT voltage and current to be drawn from a power supply bus
that is not the DDR RAM supply voltage. This has some advantages when you are
attempting to better match the power being drawn from the outputs emerging from the
main system power supply. This can be seen in Figure 4.
The internal reference voltage is set by two matched 100 k resistors connected in a
resistor divider between the VDD and VSS pins of the NE57810TK
VREF
External Reference In
+VDD
VDD
+VTT
VTT
NE57810TK
RefOut
ExtRefIn
COUT
(LF)
CIN
COUT
(HF)
VSS
GND
GND
014aaa419
Fig 4.
Externally programmed VTT
8.3 Cascading the NE57810TK
For high-performance computer systems, sometimes memory banks are driven
180 degrees out of phase with one another in such a way that the apparent access time is
halved (even and odd memory addresses). To do this, NXP recommends that two
NE57810TKs are used, one to terminate each memory bank.
Cascading NE57810TK terminators offers two advantages, it improves the system noise
performance by bringing the memory SIMMs closer to the terminator, and it distributes
any heat generated by the terminator system. By using the RefOut pin from one
NE57810TK to the ExtRefIn pin for the other NE57810TK(s) used in the system, one can
always guarantee that the VTT voltages are identical.
Because of the very tight output voltage regulation of the NE57810TK, the VTT outputs
should never be wired together. This is because the terminators would ‘fight’ one another
if their output were different by only a few millivolts. This method can be used in either the
normal operating mode and the externally programmed operating mode. This method of
use can be seen in Figure 5.
NE57810TK
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 January 2013
© NXP B.V. 2013. All rights reserved.
5 of 18
NE57810TK
NXP Semiconductors
Advanced DDR memory termination power with external reference
voltage in
VREF
+VDD
Master
VDD
+VTT1
VTT
NE57810TK
RefOut
ExtRefIn
COUT
(LF)
CIN
COUT
(HF)
VSS
GND
GND
(HF)
VDD
VTT
Slave
+VTT
NE57810TK
RefOut
ExtRefIn
COUT
(LF)
CIN
COUT
(HF)
VSS
To other
NE5781s
GND
014aaa420
Fig 5.
Cascading terminator systems for complex memory systems
9. Technical description
The NE57810TK supplies power to the DDR memory bus termination resistors at
nominally half the voltage supplied to the memory ICs or DIMMs. DDR memory output
drivers source and sink current into and out of their outputs.
A typical DDR memory system is seen in Figure 1. Each input/output pin on the bus has a
series 20  resistor connected to it. The bus is terminated to the DDR terminator through
a 27  to 50  resistance. The memory system then requires current from the VTT
terminator bus only when the instantaneous values of the aggregate bus state are not
equal amounts of 1s and 0s.
When memory bus speeds are in the 200 MHz to 300 MHz region, the period of any single
bus state is extremely small. This permits the DDR bus termination regulator to be a linear
power operational amplifier that can source and sink current instantly to the DDR bus from
the VDD supply voltage.
Figure 7 models the VTT loading condition of each bus line equivalent circuit during
operation and with terminating resistors.
NE57810TK
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 January 2013
© NXP B.V. 2013. All rights reserved.
6 of 18
NE57810TK
NXP Semiconductors
Advanced DDR memory termination power with external reference
voltage in
VDD
VDD
VDD
VDD
100 kΩ
OVERCURRENT
OVERTEMPERATURE
ExtRefIn
VTT
RefOut
100 kΩ
a. '0' data
b. '1' data
VSS
014aaa424
Fig 6.
VTT loading conditions
Fig 7.
014aaa410
Block diagram
This yields the worst case current loading Equation 1:
N DDR V DD
I O(max) = --------------------------2  RT + RS 
(1)
Where:
• NDDR is the total number of terminated control, address and data lines within the DDR memory
system. (typically 192).
• RT is the value of the terminating resistors.
• RS is the value of the series resistors from the active output driver.
Hence the worst case current loading condition, where there are either all 1s or all 0s for
an instant, and RT is 27  and RS is 20 , produces an instantaneous output current of
either +3.5 A or 3.5 A.
10. Thermal design
Designing the proper thermal system for the NE57810TK is important for its reliable
operation. The NE57810TK will be operating at an average power level less than the
maximum rating of the part. In a typical DDR terminator system the average power
dissipation is between 0.8 W and 1.5 W.
The termination power will vary as the average number of 1s and 0s changes during
normal operation of the DDR memory. The load current will assume a new value for each
bus cycle at a 266 MHz rate, and will increase and decrease as the statistical average of
bus states change.
The terminator heat sink must be designed to accommodate the average power as a
steady state condition and be able to withstand momentary periods of increased
dissipation, typically 2 seconds to 5 seconds duration. For the typical NE57810TK
application, the power dissipated by the terminator can be calculated by Equation 2:
P D = I DD  V TT W
NE57810TK
Product data sheet
(2)
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 January 2013
© NXP B.V. 2013. All rights reserved.
7 of 18
NE57810TK
NXP Semiconductors
Advanced DDR memory termination power with external reference
voltage in
The thermal resistance of a surface mount package is given as Rth(j-a), the thermal
resistance from the junction to air. JESD51-7 specifies a 4-layer multilayer PCB
(2 oz/1 oz/1 oz/2 oz copper) that is 4 inches on each side.
This is probably the best (or lowest) thermal resistance you will see in any application.
Most applications cannot afford the PCB area to create this situation, but the thermal
performance of a multilayer PCB will still provide a significant heatsinking effect. The
actual thermal resistance will be higher than the 18.7 C/W given for the 4-layer JEDEC
PCB.
Figure 8 shows the thermal resistance you can expect for heatsinking PCB areas less
than the JEDEC specification. The graph is for a 2 oz single-sided PCB with a square area
of the side dimension as given on the X-axis. If you use a double-sided PCB with some
plated-through holes to help transfer heat to the bottom side, the thermal resistance only
improves by about 3 C/W to 4 C/W.
40.0
10
0.25 s
30.0
0.5 s
Thermal
resistance 20.0
(°C/W)
DC
IDD (A) 1
10.0
0.0
0
20
40
60
80
Length of side of 2 oz. copper area (mm)
0.1
100
1
2
014aaa425
Fig 8.
PCB heat sink area versus thermal resistance
Fig 9.
3
4
VDD (V)
5
6
7 8 9 10
014aaa426
Safe operating area for the NE57810TK
After the power is estimated, the minimum PCB area can be determined by calculating the
worst case thermal resistance and, based on Figure 8, determine the PCB area. This is
done by Equation 3:
T j – T amb
R qJA(min) = ---------------------PD
(3)
Where:
• Tj is the maximum desired junction temperature.
• Tamb is the highest expected local ambient temperature.
• PD is the estimated average power
The junction temperature should be kept well away from the overtemperature cut-off
threshold temperature (+150 C) in normal operation. Using the above power dissipation,
the highest ambient temperature and a junction temperature of +125 C, calculate the
maximum thermal resistance using Equation 4, (1.5 W is used only as an example).
125C – 70C
R th((j-a)(min)) = ----------------------------------- = 36.6C/W
1.5W
NE57810TK
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 January 2013
(4)
© NXP B.V. 2013. All rights reserved.
8 of 18
NE57810TK
NXP Semiconductors
Advanced DDR memory termination power with external reference
voltage in
Looking at Figure 8, you see that this power dissipation requires a minimum PCB island
area of 225 mm2 (15 mm on each side). This is the smallest area you could use at this
power dissipation. Of course, increasing this area will allow the NE57810TK to operate at
cooler temperatures, thus enhancing its long-term reliability.
11. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDD
supply voltage
VDD to VSS voltage
0.3
+3.6
V
Tamb
ambient temperature
0
+70
C
Tstg
storage temperature
40
+165
C
Tj
junction temperature
-
160
C
PD
power dissipation
-
3.3
W
[1]
[1]
Tested on a minimum footprint on a four-layer PCB per JEDEC specification JESD51-7
12. Thermal characteristics
Table 4.
Thermal characteristics
Symbol
Parameter
Rth(j-a)
thermal resistance from junction
to ambient
Conditions
Typ
Unit
18.7
K/W
13. Characteristics
Table 5.
Characteristics
Tamb = 0C to +70 C, VDD = 2.5 V; ITT = –3.5 A to +3.5 A, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VTT
output voltage
ExtRefIn not connected
-
VDD/2
-
V
15
-
+15
mV
1.6
-
3.6
V
[1]
VACC
output voltage accuracy
VDD
supply voltage
IQ
supply current
ITT = 0 A
-
14
30
mA
ITT
output current
2.5 V  VDD  3.6 V
3.5
-
+3.5
A
VDD = 1.6 V
2.5
-
+2.5
A
-
6
-
mV
VTT
load regulation
ITT =  1.0 A
CLOAD
load capacitance
stable operation
ITT =  3.5 A
[2]
18
-
+18
mV
-
100
-
F
0.8
-
VDD  0.8
V
35
50
-
k
15
-
+15
mV
6
-
+6
mV
External reference in
VTT
output voltage swing
Rin(ExtRefIn) input impedance
output voltage accuracy
ITT = 0 A
line regulation
ExtRefIn = 1.25 V;
VDD = 2.25 – 3.6 V
NE57810TK
Product data sheet
[3]
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 January 2013
© NXP B.V. 2013. All rights reserved.
9 of 18
NE57810TK
NXP Semiconductors
Advanced DDR memory termination power with external reference
voltage in
Table 5.
Characteristics …continued
Tamb = 0C to +70 C, VDD = 2.5 V; ITT = –3.5 A to +3.5 A, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
15
ExtRefIn
+15
mV
2.2
3
-
mA
0.1
-
-
F
Reference out
RefOut
voltage reference out
IrefOut
reference out current max
CLOAD
load capacitance
IrefOut = 0 A;
source or sink
stable operation
[4]
Power stage
IIlim
current limit
3.6
4.5
6.5
A
Tlim
temperature shutdown
-
150
-
C
temperature shutdown
hysteresis
-
20
-
C
[1]
VACC = VTT  VDD/2.
[2]
Ceramic capacitors only. Low ESR electrolytic capacitors are not necessary.
[3]
Voltage accuracy refers to voltage at ExtRefIn pin.
[4]
RefOut voltage referenced to 0.5 VDD if ExtRefIn is not connected.
NE57810TK
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 January 2013
© NXP B.V. 2013. All rights reserved.
10 of 18
NE57810TK
NXP Semiconductors
Advanced DDR memory termination power with external reference
voltage in
14. Typical performance curves
Figure 10 through Figure 14 show the typical performance curves for the NE57810TK.
+5 mV
VTT
0.5 mV
2
−3 A
1
ITT
+3 A
CH3
CH1 200 mV Ch2 200 mV
25.0 mV Ch4 10.0 mV M10.0 μs
M50.0 μs Ch2 −100 mV
014aaa427
Fig 10. VTT transient response
(output filter 50 F ceramic)
014aaa428
Fig 11. VDD to VTT response
(output filter 50 F ceramic)
VTT
VTT
−35 A
ITT
VREF Input
+35 A
CH1
500 mv Ch2
500 mV
M10.0 μs
014aaa421
Fig 12. VREF to VTT transient response
(output filter 820 F + 50 F ceramic)
NE57810TK
Product data sheet
CH3 25.0 mV Ch4 10.0 mV M10.0 μs
014aaa422
Fig 13. VREF to VTT transient response
(output filter 50 F ceramic)
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 January 2013
© NXP B.V. 2013. All rights reserved.
11 of 18
NE57810TK
NXP Semiconductors
Advanced DDR memory termination power with external reference
voltage in
1.300
Normal operating region
1.280
1.260
Volts
1.240
Output sink
Output source
1.220
1.200
−6
−4
−2
0
Amps
2
4
6
014aaa429
Fig 14. Typical VTT versus output current (VDD = 2.5 V at 25 C)
NE57810TK
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 January 2013
© NXP B.V. 2013. All rights reserved.
12 of 18
NE57810TK
NXP Semiconductors
Advanced DDR memory termination power with external reference
voltage in
15. Test information
Figure 15, Figure 16 and Figure 17 show the diagrams for the NE57810TK test circuits.
2
VDD
NE57810TK
VIN
820 μF
Oscon
4
R (Load)
1
VTT
ExtRefIn
VSS
0.01 μF
(5 ea)
10 μF
Ceramic
3
820 μF
Oscon
V
Light load
014aaa411
Heavy load
Fig 15. Load transient test (+3 A to –3 A)
2
VDD
NE57810TK
4
VIN
VTT
ExtRefIn
R (Load)
1
(5 ea)
10 μF
Ceramic
VSS
3
820 μF
Oscon
V
Light load
Heavy load
014aaa412
Fig 16. ExtRefIn to VTT transient test
VIN
0.4 V
2
VDD
NE57810TK
VIN
4
2.5 V
0.01 μF
VTT
ExtRefIn
1
VSS
V
3
014aaa423
Fig 17. VDD to VTT transient test
NE57810TK
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 January 2013
© NXP B.V. 2013. All rights reserved.
13 of 18
NE57810TK
NXP Semiconductors
Advanced DDR memory termination power with external reference
voltage in
16. Package outline
KQB*X
>->Z>
-[?\
\
*-
\]Z*/*/*69#--
`
!"#$
b
-
/
b
-
/
^
]
`
_
#
Z Z
>
*
:
>
*
#-
-
=-->?-
@
,
--
]
-/ 6** *6*# *69*
- *69# *6*" *6;*
- *69* *6** *6:*
*6"
=@
>
=@
>
*6 :6# *6 #6:#
*6* :6* *6* #6:*
&6& :6*# &6& #6##
^
6;
:69
6##
6#*
6<#
*6
_
Z
*6*# *6*#
Z
*6
B
6J
-
*6*;#---/--
6
!"#$
!"#$'
"$*!$*"
"$*!$"*
%$""&
Fig 18. Package outline SOT1325-1 (HVSON10)
NE57810TK
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 January 2013
© NXP B.V. 2013. All rights reserved.
14 of 18
NE57810TK
NXP Semiconductors
Advanced DDR memory termination power with external reference
voltage in
17. Revision history
Table 6.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
NE57810TK v.5
20130109
Product data sheet
-
NE57810 v.4
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Package changed from SOT756 to SOT1325-1.
Section 7 “Pinning information” has been updated.
Table 1 “Ordering information” has been updated
Figure 18 “Package outline SOT1325-1 (HVSON10)” has been updated.
NE57810 v.4
20081124
Product data sheet
-
NE57810 v.3
NE57810 v.3
20080702
Product data sheet
-
NE57810 v.2
NE57810 v.2
20030912
Product data sheet
-
NE57810 v.1
NE57810 v.1
20020716
Product data sheet
-
-
NE57810TK
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 January 2013
© NXP B.V. 2013. All rights reserved.
15 of 18
NE57810TK
NXP Semiconductors
Advanced DDR memory termination power with external reference
voltage in
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
NE57810TK
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 January 2013
© NXP B.V. 2013. All rights reserved.
16 of 18
NE57810TK
NXP Semiconductors
Advanced DDR memory termination power with external reference
voltage in
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
NE57810TK
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 January 2013
© NXP B.V. 2013. All rights reserved.
17 of 18
NE57810TK
NXP Semiconductors
Advanced DDR memory termination power with external reference
voltage in
20. Contents
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.2
8.3
9
10
11
12
13
14
15
16
17
18
18.1
18.2
18.3
18.4
19
20
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Application design-in information . . . . . . . . . . 4
Normal operating mode (VTT = VDDR/2) . . . . . . 4
Externally programmed VTT output voltage . . . 5
Cascading the NE57810TK . . . . . . . . . . . . . . . 5
Technical description . . . . . . . . . . . . . . . . . . . . 6
Thermal design . . . . . . . . . . . . . . . . . . . . . . . . . 7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal characteristics . . . . . . . . . . . . . . . . . . 9
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical performance curves . . . . . . . . . . . . . . 11
Test information . . . . . . . . . . . . . . . . . . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 9 January 2013
Document identifier: NE57810TK
Similar pages