Data Sheet

INTEGRATED CIRCUITS
DATA SHEET
UDA1341TS
Economy audio CODEC for
MiniDisc (MD) home stereo and
portable applications
Product specification
Supersedes data of 2001 Jun 29
2002 May 16
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
CONTENTS
1
FEATURES
1.1
1.2
1.3
1.4
General
Multiple format data interface
DAC digital sound processing
Advanced audio configuration
2
GENERAL DESCRIPTION
3
ORDERING INFORMATION
4
QUICK REFERENCE DATA
5
BLOCK DIAGRAM
6
PINNING
7
FUNCTIONAL DESCRIPTION
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
System clock
Pin compatibility
Analog front end
Programmable Gain Amplifier (PGA)
Analog-to-Digital Converter (ADC)
Digital Automatic Gain Control (AGC)
AGC status detection
Digital mixer
Decimation filter (ADC)
Overload detection (ADC)
Mute (ADC)
Interpolation filter (DAC)
Peak detector
Quick mute
Noise shaper (DAC)
Filter Stream Digital-to-Analog Converter
(FSDAC)
Multiple format input/output interface
L3-interface
Address mode
Data transfer mode
Programming the sound processing and other
features
STATUS control
DATA0 direct control
DATA0 extended programming registers
DATA1 control
7.17
7.18
7.19
7.20
7.21
7.21.1
7.21.2
7.21.3
7.21.4
2002 May 16
8
LIMITING VALUES
9
THERMAL CHARACTERISTICS
10
DC CHARACTERISTICS
11
AC CHARACTERISTICS (ANALOG)
12
AC CHARACTERISTICS (DIGITAL)
13
APPLICATION INFORMATION
14
PACKAGE OUTLINE
15
SOLDERING
15.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
15.2
15.3
15.4
15.5
2
UDA1341TS
16
DATA SHEET STATUS
17
DISCLAIMERS
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
1
1.1
UDA1341TS
FEATURES
General
• Low power consumption
• 3.0 V power supply
• 256fs, 384fs or 512fs system clock frequencies (fsys)
• Small package size (SSOP28)
• Partially pin compatible with UDA1340M and
UDA1344TS
• Optional differential input configuration for enhanced
ADC sound quality
• Fully integrated analog front end including digital AGC
• Stereo line output (under microcontroller volume
control)
• ADC plus integrated high-pass filter to cancel DC offset
• ADC supports 2 V (RMS value) input signals
• Digital peak level detection
• Overload detector for easy record level control
• High linearity, dynamic range and low distortion.
• Separate power control for ADC and DAC
• No analog post filter required for DAC
2
• Easy application
The UDA1341TS is a single-chip stereo Analog-to-Digital
Converter (ADC) and Digital-to-Analog Converter (DAC)
with signal processing features employing bitstream
conversion techniques. Its fully integrated analog front
end, including Programmable Gain Amplifier (PGA) and a
digital Automatic Gain Control (AGC). Digital Sound
Processing (DSP) featuring makes the device an excellent
choice for primary home stereo MiniDisc applications, but
by virtue of its low power and low voltage characteristics it
is also suitable for portable applications such as MD/CD
boomboxes, notebook PCs and digital video cameras.
• Functions controllable via L3-interface.
1.2
Multiple format data interface
• I2S-bus, MSB-justified and LSB-justified format
compatible
• Three combinational data formats with MSB data output
and LSB 16, 18 or 20 bits data input
• 1fs input and output format data rate.
1.3
DAC digital sound processing
The UDA1341TS is similar to the UDA1340M and the
UDA1344TS but adds features such as digital mixing of
two input signals and one channel with a PGA and a digital
AGC.
• Digital dB-linear volume control (low microcontroller
load)
• Digital tone control, bass boost and treble
• Digital de-emphasis for 32, 44.1 or 48 kHz audio sample
frequencies (fs)
The UDA1341TS supports the I2S-bus data format with
word lengths of up to 20 bits, the MSB-justified data format
with word lengths of up to 20 bits, the LSB-justified serial
data format with word lengths of 16, 18 and 20 bits and
three combinations of MSB data output combined with
LSB 16, 18 and 20 bits data input. The UDA1341TS has
DSP features in playback mode like de-emphasis, volume,
bass boost, treble and soft mute, which can be controlled
via the L3-interface with a microcontroller.
• Soft mute.
1.4
Advanced audio configuration
• DAC and ADC polarity control
• Two channel stereo single-ended input configuration
• Microphone input with on-board PGA
3
GENERAL DESCRIPTION
ORDERING INFORMATION
TYPE
NUMBER
UDA1341TS
2002 May 16
PACKAGE
NAME
DESCRIPTION
VERSION
SSOP28
plastic shrink small outline package; 28 leads; body width 5.3 mm
SOT341-1
3
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
4
UDA1341TS
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDA(ADC)
ADC analog supply voltage
2.4
3.0
3.6
V
VDDA(DAC)
DAC analog supply voltage
2.4
3.0
3.6
V
VDDD
digital supply voltage
2.4
3.0
3.6
V
IDDA(ADC)
ADC analog supply current
operation mode
−
12.5
−
mA
ADC power-down
−
6.0
−
mA
IDDA(DAC)
DAC analog supply current
operation mode
−
7.0
−
mA
DAC power-down
−
50
−
μA
operation mode
−
7.0
−
mA
−20
−
+85
°C
−
1.0
−
V
0 dB
−
−85
−80
dB
−60 dB; A-weighted
−
−37
−33
dB
0 dB
−
−90
−85
dB
−60 dB; A-weighted
−
−40
−36
dB
stand-alone mode
−
97
−
dB
double differential mode
−
100
−
dB
−
100
−
dB
0 dB
−
−85
−
dB
−60 dB; A-weighted
−
−37
−
dB
Vi = 0 V; A-weighted
−
95
−
dB
IDDD
digital supply current
Tamb
operating ambient temperature
Analog-to-digital converter
Vi(rms)
input voltage (RMS value)
(THD + N)/S total harmonic distortion-plus-noise
to signal ratio
notes 1 and 2
stand-alone mode
double differential mode
S/N
αcs
signal-to-noise ratio
Vi = 0 V; A-weighted
channel separation
Programmable gain amplifier
(THD + N)/S total harmonic distortion-plus-noise
to signal ratio
S/N
signal-to-noise ratio
1 kHz; fs = 44.1 kHz
Digital-to-analog converter
Vo(rms)
output voltage (RMS value)
supply voltage = 3 V; note 3
−
900
−
mV
(THD+N)/S
total harmonic distortion-plus-noise
to signal ratio
0 dB
−
−91
−86
dB
−60 dB; A-weighted
−
−40
−
dB
S/N
signal-to-noise ratio
code = 0; A-weighted
−
100
−
dB
αcs
channel separation
−
100
−
dB
Notes
1. The ADC inputs can be used in a 2 V (RMS value) input signal configuration when a resistor of 12 kΩ is used in series
with the inputs and 1 or 2 V (RMS value) input signal operation can be selected via the Input Gain Switch (IGS).
2. The ADC input signal scales inversely proportional with the power supply voltage.
3. The DAC output voltage scales linear with the DAC analog supply voltage.
2002 May 16
4
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
5
UDA1341TS
BLOCK DIAGRAM
VDDA(ADC)
handbook, full pagewidth
VSSA(ADC)
3
VINL2
VDDD
1
10
VADCN
7
11
5
6
8
PGA
2
ADC2
0 dB/6 dB
SWITCH
4
0 dB/6 dB
SWITCH
ADC1
VINR1
ADC1
22
UDA1341TS
VINR2
PGA
ADC2
VINL1
VADCP
VSSD
DIGITAL AGC
AGCSTAT
DIGITAL MIXER
9
DECIMATION FILTER
DATAO
BCK
WS
DATAI
18
13
16
DIGITAL INTERFACE
17
L3-BUS
INTERFACE
15
19
12
DSP FEATURES
QMUTE
23
INTERPOLATION FILTER
20
28
21
DAC
VOUTL
L3CLOCK
L3DATA
SYSCLK
TEST1
TEST2
DAC
26
24
VOUTR
27
25
VDDA(DAC)
VSSA(DAC)
Fig.1 Block diagram.
2002 May 16
L3MODE
PEAK
DETECTOR
NOISE SHAPER
Vref
14
OVERFL
5
MGR427
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
6
PINNING
SYMBOL
UDA1341TS
SYMBOL
PIN
DESCRIPTION
PIN
DESCRIPTION
L3DATA
15
L3-bus data input and output
VSSA(ADC)
1
ADC analog ground
BCK
16
bit clock input
VINL1
2
ADC1 input left
WS
17
word select input
VDDA(ADC)
3
ADC analog supply voltage
DATAO
18
data output
VINR1
4
ADC1 input right
DATAI
19
data input
VADCN
5
ADC negative reference voltage
TEST1
20
test control 1 (pull-down)
VINL2
6
ADC2 input left
TEST2
21
test control 2 (pull-down)
VADCP
7
ADC positive reference voltage
AGCSTAT
22
AGC status
VINR2
8
ADC2 input right
QMUTE
23
quick mute input
OVERFL
9
decimation filter overflow output
VOUTR
24
DAC output right
VDDD
10
digital supply voltage
VDDA(DAC)
25
DAC analog supply voltage
VSSD
11
digital ground
VOUTL
26
DAC output left
SYSCLK
12
system clock 256fs, 384fs or 512fs
VSSA(DAC)
27
DAC analog ground
L3MODE
13
L3-bus mode input
Vref
28
ADC and DAC reference voltage
L3CLOCK
14
L3-bus clock input
handbook, halfpage
handbook, halfpage
27 VSSA(DAC)
VINL1 2
VDDA(ADC) 3
27 VSSA(DAC)
VINL1 2
VDDA(ADC) 3
26 VOUTL
25 VDDA(DAC)
VINR1 4
28 Vref
VSSA(ADC) 1
28 Vref
VSSA(ADC) 1
26 VOUTL
25 VDDA(DAC)
VINR1 4
VADCN 5
24 VOUTR
VADCN 5
24 VOUTR
VINL2 6
23 QMUTE
VINL2 6
23 QMUTE
VADCP 7
VADCP 7
22 AGCSTAT
22 AGCSTAT
UDA1341TS
UDA1341TS
VINR2 8
21 TEST2
VINR2 8
21 TEST2
OVERFL 9
20 TEST1
OVERFL 9
20 TEST1
VDDD 10
19 DATAI
VDDD 10
19 DATAI
VSSD 11
18 DATAO
VSSD 11
18 DATAO
SYSCLK 12
17 WS
SYSCLK 12
17 WS
L3MODE 13
16 BCK
L3MODE 13
16 BCK
15 L3DATA
L3CLOCK 14
15 L3DATA
L3CLOCK 14
MGR429
MGR428
Marked pins are compatible with UDA1340M
Fig.2 Pin configuration.
2002 May 16
Fig.3 Compatible pins with UDA1340M.
6
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
7
FUNCTIONAL DESCRIPTION
7.1
7.5
7.6
Pin compatibility
Analog front end
The analog front end of the UDA1341TS consists of two
stereo ADCs with a Programmable Gain Amplifier (PGA) in
channel 2. The PGA is intended to pre-amplify a
microphone signal applied to the input channel 2.
7.7
7.8
INPUT
GAIN
SWITCH
Present
0 dB
2 V (RMS value) input signal;
note 1
Present
6 dB
1 V (RMS value) input signal
Absent
0 dB
1 V (RMS value) input signal
Absent
6 dB
0.5 V (RMS value) input signal
• ADC1 only mode (for line input); input channel 2 is off
• ADC2 only mode, including PGA and digital AGC (for
microphone input); input channel 1 is off
MAXIMUM INPUT VOLTAGE
• ADC1 + ADC2 mixer mode, including PGA and AGC
• ADC1 and ADC2 double differential mode (improved
ADC performance).
Important: In order to prevent crosstalk between the line
inputs no signal should be applied to the microphone input
in the double differential mode.
In all modes (except the double differential mode) a
reference voltage is always present at the input of the
ADC. However, in the double differential mode there is no
reference voltage present at the microphone input.
Note
1. If there is no need for 2 V (RMS value) input signal
support, the external resistor should not be used.
7.4
In the mixer mode, the output signals of both ADCs in
channel 1 and channel 2 (after the digital AGC) can be
mixed with coefficients that can be set via the L3-interface.
The range of the mixer coefficients is from 0 to −∞ dB in
1.5 dB steps.
Programmable Gain Amplifier (PGA)
The PGA can be set via the L3-interface at the gain
settings: −3, 0, 3, 9, 15, 21 or 27 dB.
2002 May 16
Digital mixer
The two stereo ADCs (including the AGC) can be used in
four modes:
Application modes using input gain stage
RESISTOR
(12 kΩ)
AGC status detection
The AGCSTAT signal from the digital AGC is HIGH when
the gain level of the AGC is below 8 dB. This signal can be
used to give the PGA a new gain setting via the
L3-interface and to power e.g. a LED.
Input channel 1 has a selectable 0 or 6 dB gain stage, to
be controlled via the L3-interface. In this way, input signals
of 1 V (RMS value) or 2 V (RMS value) e.g. from a
CD source can be supported using an external resistor of
12 kΩ in series with the input channel 1. The application
modes are given in Table 1.
Table 1
Digital Automatic Gain Control (AGC)
Input channel 2 has a digital AGC to compress the
dynamic range when a microphone signal is applied to
input channel 2. The digital AGC can be switched on and
off via the L3-interface. In the on state the AGC
compresses the dynamic range of the input signal of input
channel 2. Via the L3-interface the user can set the
parameters of the AGC: attack time, decay time and output
level. When the AGC is set off via the L3-interface, the gain
of input channel 2 can be set manually. In this case the
gain of the PGA and digital AGC are combined. The range
of the gain of the input channel 2 is from −3 to +60.5 dB in
steps of 0.5 dB.
The UDA1341TS is partially pin compatible with the
UDA1340M and UDA1344TS, making an upgrade of a
printed-circuit board from UDA1340M to UDA1341TS
easier. The pins that are compatible with the UDA1340M
are marked in Fig.3.
7.3
Analog-to-Digital Converter (ADC)
The stereo ADC of the UDA1341TS consists of two
3rd-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The over-sampling ratio is 128.
System clock
The UDA1341TS accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock. The system frequency is
selectable. The options are 256fs, 384fs or 512fs.
The system clock must be locked in frequency to the digital
interface signals.
7.2
UDA1341TS
7
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
7.9
7.12
Decimation filter (ADC)
The decimation from 128fs is performed in two stages.
Table 3
CONDITIONS
Interpolation filter characteristics
ITEM
Decimation filter characteristics
ITEM
Interpolation filter (DAC)
The digital filter interpolates from 1fs to 128fs by means of
a cascade of a recursive filter and a Finite Impulse
Response (FIR) filter.
sin x
The first stage realizes 3rd order ------------ characteristic,
x
decimating by 16. The second stage consists of
3 half-band filters, each decimating by a factor of 2.
Table 2
UDA1341TS
VALUE
(dB)
CONDITIONS
VALUE
(dB)
Passband ripple
0 to 0.45fs
±0.03
Stop band
>0.55fs
−50
Dynamic range
0 to 0.45fs
108
Passband ripple
0 to 0.45fs
±0.05
Stop band
>0.55fs
−60
Dynamic range
0 to 0.45fs
108
7.13
Overall gain
input channel 1;
0 dB input
−1.16
In the playback path a peak level detector is build in.
The position of the peak detection can be set via the
L3-interface to either before or after the sound features.
The peak level detector is implemented as a peak-hold
detector, which means that the highest sound level is hold
until the peak level is read out via the L3-interface. After
read-out the peak level registers are reset.
7.10
Overload detection (ADC)
This name is convenient but a little inaccurate. In practice
the output is used to indicate whenever that output data, in
either the left or right channel, is bigger than −1 dB (actual
figure is −1.16 dB) of the maximum possible digital swing.
If this condition is detected the OVERFL output is forced
HIGH for at least 512fs cycles (11.6 ms at fs = 44.1 kHz).
This time-out is reset for each infringement.
7.11
7.14
Quick mute
A hard mute can be activated via the static pin QMUTE.
When QMUTE is set HIGH, the output signal is instantly
muted to zero. Setting QMUTE to LOW, the mute is
instantly de-activated.
Mute (ADC)
On recovery from power-down or switching on of the
system clock, the serial data output on pin DATAO is held
at LOW level until valid data is available from the
decimation filter. This time depends on whether the
DC-cancellation filter is selected:
7.15
Noise shaper (DAC)
The 3rd-order noise shaper operates at 128fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique allows for high
signal-to-noise ratios. The noise shaper output is
converted into an analog signal using a filter stream
digital-to-analog converter.
• DC cancel off:
1024
t = ------------- ; t = 23.2 ms at fs = 44.1 kHz
fs
• DC cancel on:
12288
t = ---------------- ; t = 279 ms at fs = 44.1 kHz.
fs
2002 May 16
Peak detector
8
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
7.16
Filter Stream Digital-to-Analog Converter
(FSDAC)
7.17
UDA1341TS
Multiple format input/output interface
The UDA1341TS supports the following data formats:
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at virtual
ground of the output operational amplifier. In this way very
high signal-to-noise performance and low clock jitter
sensitivity is achieved. A post filter is not needed due to the
inherent filter function of the DAC. On-board amplifiers
convert the FSDAC output current to an output voltage
signal capable of driving a line output.
• I2S-bus with word length up to 20 bits
• MSB-justified serial format with word length up to 20 bits
• LSB-justified serial format with word length of
16, 18 or 20 bits
• MSB data output with LSB 16, 18 or 20 bits input.
Left and right data-channel words are time multiplexed.
The formats are illustrated in Fig.4.
The UDA1341TS allows for double speed data monitoring
purposes. In this case the sound features bass boost,
treble and de-emphasis cannot be used. However, volume
control and soft-mute can still be controlled. The double
speed monitoring option can be set via the L3-interface.
The bit clock frequency must be 64 times word select
frequency or less, so fBCK ≤ 64 × fWS.
2002 May 16
9
RIGHT
>=8
3
1
2
3
BCK
DATA
MSB
B2
LSB MSB
>=8
B2
LSB MSB
INPUT FORMAT I2S-BUS
LEFT
WS
1
2
RIGHT
>=8
3
1
2
LSB MSB
B2
>=8
3
BCK
DATA
MSB
B2
LSB MSB
B2
MSB-JUSTIFIED FORMAT
WS
RIGHT
LEFT
16
15
2
1
16
B15 LSB
MSB
15
2
1
BCK
10
MSB
DATA
B2
B2
B15 LSB
LSB-JUSTIFIED FORMAT 16 BITS
WS
RIGHT
LEFT
18
NXP Semiconductors
2
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
1
handbook, full pagewidth
2002 May 16
LEFT
WS
17
16
15
2
1
18
B17
LSB
MSB
17
16
15
2
1
B17
LSB
2
1
BCK
DATA
MSB
B2
B3
B4
B2
B3
B4
LSB-JUSTIFIED FORMAT 18 BITS
WS
LEFT
20
19
18
RIGHT
17
16
15
20
B19
LSB
MSB
19
18
17
16
15
BCK
DATA
MSB
B2
B3
B4
B5
B6
B2
B3
B4
B5
B6
B19
LSB
MGG841
LSB-JUSTIFIED FORMAT 20 BITS
Fig.4 Serial interface formats.
Product specification
1
UDA1341TS
2
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
7.18
L3-interface
UDA1341TS
The address mode is required to select a device
communicating via the L3-bus and to define the
destination registers for the data transfer mode.
The UDA1341TS has a microcontroller input mode. In the
microcontroller mode, all the digital sound processing
features and the system controlling features can be
controlled by the microcontroller.
Data transfer can be in both directions: input to the
UDA1341TS to program its sound processing and system
controlling features and output from the UDA1341TS to
provide the peak level value.
The controllable features are:
• Reset
• System clock frequency
7.19
• Power control
The address mode is used to select a device for
subsequent data transfer and to define the destination
registers. The address mode is characterized by L3MODE
being LOW and a burst of 8 pulses on L3CLOCK,
accompanied by 8 data bits. The fundamental timing is
shown in Fig.5.
• DAC gain switch
• ADC input gain switch
• ADC/DAC polarity control
• Double speed playback
• De-emphasis
Address mode
Data bits 7 to 2 represent a 6-bit device address, with bit 7
being the MSB and bit 2 the LSB. The address of the
UDA1341TS is 000101.
• Volume
• Mode switch
Data bits 0 to 1 indicate the type of the subsequent data
transfer as shown in Table 4.
• Bass boost
• Treble
In the event that the UDA1341TS receives a different
address, it will deselect its microcontroller interface logic.
• Mute
• MIC sensitivity control
• AGC control
7.20
• Input amplifier gain control
Data transfer mode
The selection activated in the address mode remains
active during subsequent data transfers, until the
UDA1341TS receives a new address command.
• Digital mixer control
• Peak detection position.
The fundamental timing of data transfers is essentially the
same as the timing in the address mode and is given in
Fig.6.
Via the L3-interface the peak level value of the signal in the
DAC path can be read out from the UDA1341TS to the
microcontroller.
• L3MODE: microcontroller interface mode line
Note that ‘L3DATA write’ denotes data transfer from the
microcontroller to the UDA1341TS and ‘L3DATA peak
read’ denotes data transfer in the opposite direction.
The maximum input clock and data rate is 64fs.
All transfers are byte-wise, i.e. they are based on groups
of 8 bits. Data will be stored in the UDA1341TS after the
eighth bit of a byte has been received.
• L3CLOCK: microcontroller interface clock line.
A multibyte transfer is illustrated in Fig.7.
The exchange of data and control information between the
microcontroller and the UDA1341TS is accomplished
through a serial hardware L3-interface comprising the
following pins:
• L3DATA: microcontroller interface data line
Information transfer through the microcontroller bus is
organized in accordance with the so called ‘L3’ format, in
which two different modes of operation can be
distinguished: address mode and data transfer mode.
2002 May 16
11
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Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
Table 4
Selection of data transfer
BIT 1 BIT 0
0
UDA1341TS
0
MODE
DATA0
TRANSFER
direct addressing registers: volume, bass boost, treble, peak detection position,
de-emphasis, mute and mode
extended addressing registers: digital mixer control, AGC control, MIC sensitivity control,
input gain, AGC time constant and AGC output level
0
1
DATA1
1
0
STATUS reset, system clock frequency, data input format, DC-filter, input gain switch, output gain
switch, polarity control, double speed and power control
peak level value read-out (information from UDA1341TS to microcontroller)
1
1
not used
handbook, full pagewidth
L3MODE
tsu(L3)A
th(L3)A
tCLK(L3)L
tsu(L3)A
tCLK(L3)H
th(L3)A
L3CLOCK
Tcy(CLK)(L3)
tsu(L3)DA
L3DATA
th(L3)DA
BIT 0
BIT 7
MGR431
Fig.5 Timing address mode.
2002 May 16
12
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
UDA1341TS
tstp(L3)
handbook, full pagewidth
tstp(L3)
L3MODE
tCLK(L3)L
th(L3)D
Tcy(CLK)L3
tCLK(L3)H
tsu(L3)D
L3CLOCK
th(L3)DA
L3DATA
write
tsu(L3)DA
th(L3)DA
BIT 7
BIT 0
L3DATA
read
PL0
PL1
PL2
PL3
PL4
PL5
MGR430
Fig.6 Timing for data transfer mode.
tstp(L3)
handbook, full pagewidth
L3MODE
L3CLOCK
L3DATA
address
data byte #1
data byte #2
Fig.7 Multibyte transfer.
2002 May 16
13
address
MGR432
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
7.21
• DATA0
Programming the sound processing and other
features
There are two addressing modes: direct addressing
mode and extended addressing mode.
The sound processing and other feature values are stored
in independent registers.
Direct addressing mode is using the 2 MSB bits of the
data byte. Via this addressing mode the features
volume, bass boost, treble, peak position, de-emphasis,
mute, and mode can be controlled directly.
The first selection of the registers is achieved by the choice
of data type that is transferred. This is performed in the
address mode using bit 0 and bit 1 (see Table 4).
The second selection is performed by the 2 or 3 MSBs of
the data byte (bits 7 and 6 or bits 7, 6 and 5).
The other bits in the data byte (bits 5 to 0 or bits 4 to 0)
represent the value that is placed in the selected registers.
Extended addressing mode is provided for controlling
the features digital mixer, AGC control, MIC sensitivity,
input gain, AGC time constants, and AGC output level.
An extended address can be set via the EA registers
(3 bits). The data in the extended registers can be set by
writing data to the ED registers (5 bits).
For the UDA1341TS the following modes can be selected:
• STATUS
• DATA1
In this mode the features reset, system clock frequency,
data input format, DC-filter, input gain switch, output
gain switch, polarity control, double speed and power
control can be controlled.
Table 5
UDA1341TS
In this mode the detected peak level value can be read
out.
Default settings
SYMBOL
FEATURE
SETTING OR VALUE
Status
OGS
Output gain switch
0 dB
IGS
Input gain switch
0 dB
PAD
Polarity of ADC
non-inverting
PDA
Polarity of DAC
non-inverting
DS
Double speed
single speed
PC
Power control ADC and DAC
on
Direct control
VC
Volume control
0 dB
BB
Bass boost
0 dB
TR
Treble
0 dB
PP
Peak detection position
after the tone features
DE
De-emphasis
no de-emphasis
MT
Mute
no mute
M
Mode switch
flat
Extended programming
−6 dB
MA
Mixer gain channel 1
MB
Mixer gain channel 2
−6 dB
MS
MIC sensitivity
0 dB
MM
Mixer mode switch
double differential
AG
AGC control
disable AGC
AT
AGC attack and decay time
11 ms and100 ms
AL
AGC output level
−9 dB FS
2002 May 16
14
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
7.21.1
Table 6
UDA1341TS
STATUS CONTROL
Data transfer of type ‘STATUS’
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0
RST
SC1
SC0
IF2
IF1
IF0
DC
REGISTER SELECTED
RST = reset
SC = system clock frequency (2 bits)
IF = data input format (3 bits)
DC = DC-filter
1
OGS
IGS
PAD
PDA
DS
PC1
PC0
OGS = output gain (6 dB) switch
IGS = input gain (6 dB) switch
PAD = polarity of ADC
PDA = polarity of DAC
DS = double speed
PC = power control (2 bits)
7.21.1.1
Reset
7.21.1.4
A 1-bit value to initialize the L3-registers with the default
settings except system clock frequency.
Data input format
A 3-bit value to select the data input format.
Table 10 Data input format settings
Table 7
Reset settings
RST
IF2 IF1 IF0
FUNCTION
FUNCTION
0
0
0
I2S-bus
0
no reset
0
0
1
LSB-justified 16 bits
1
reset
0
1
0
LSB-justified 18 bits
0
1
1
LSB-justified 20 bits
1
0
0
MSB-justified
1
0
1
LSB-justified 16 bits input and
MSB-justified output
1
1
0
LSB-justified 18 bits input and
MSB-justified output
1
1
1
LSB-justified 20 bits input and
MSB-justified output
7.21.1.2
System clock frequency
A 2-bit value to select the used external clock frequency.
Table 8
System clock settings
SC1 SC0
FUNCTION
0
0
512fs
0
1
384fs
1
0
256fs
1
1
not used
7.21.1.3
DC-filter
A 1-bit value to enable the digital DC-filter.
Table 9
DC-filtering settings
DC
FUNCTION
0
no DC-filtering
1
DC-filtering
2002 May 16
15
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
7.21.1.5
Output gain switch
UDA1341TS
7.21.1.9
Double speed
A 1-bit value to control the DAC output gain switch.
The default setting is given in Table 5.
A 1-bit value to enable the double speed playback.
The default setting is given in Table 5.
Table 11 Gain switch of DAC settings
Table 15 Double speed settings
OGS
GAIN OF DAC
DS
0
0 dB
0
single speed playback
1
6 dB
1
double speed playback
7.21.1.6
Input gain switch
FUNCTION
7.21.1.10 Power control
A 1-bit value to control the ADC input gain switch.
The default setting is given in Table 5.
A 2-bit value to disable the ADC and/or DAC to reduce
power consumption. The default setting is given in Table 5.
Table 12 Gain switch of ADC settings
Table 16 Power control settings
IGS
FUNCTION
GAIN OF ADC
0
0 dB
1
6 dB
7.21.1.7
PC1
Polarity of ADC
A 1-bit value to control the ADC polarity. The default
setting is given in Table 5.
Table 13 Polarity control of ADC settings
PAD
POLARITY OF ADC
0
non-inverting
1
inverting
7.21.1.8
Polarity of DAC
A 1-bit value to control the DAC polarity. The default
setting is given in Table 5.
Table 14 Polarity control of DAC settings
PDA
POLARITY OF DAC
0
non-inverting
1
inverting
2002 May 16
16
PC0
ADC
DAC
off
off
0
0
0
1
off
on
1
0
on
off
1
1
on
on
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
7.21.2
UDA1341TS
DATA0 DIRECT CONTROL
Table 17 Data transfer of type ‘DATA0’
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
REGISTER SELECTED
0
0
VC5
VC4
VC3
VC2
VC1
VC0
VC = volume control (6 bits)
0
1
BB3
BB2
BB1
BB0
TR1
TR0
BB = bass boost (4 bits)
TR = treble (2 bits)
1
0
PP
DE1
DE0
MT
M1
M0
PP = peak detection position
DE = de-emphasis (2 bits)
MT = mute
M = mode switch (2 bits)
1
1
0
0
0
EA2
EA1
EA0
EA = extended address (3 bits)
1
1
1
ED4
ED3
ED2
ED1
ED0
ED = extended data (5 bits)
7.21.2.1
Volume control
7.21.2.2
Bass boost
A 6-bit value to program the left and right channel volume
attenuation. The range is from 0 to −∞ dB in steps of 1 dB.
The default setting is given in Table 5.
A 4-bit value to program the bass boost settings. The used
set depends on the mode bits. The default setting is given
in Table 5.
Table 18 Volume settings
Table 19 Bass boost settings
BASS BOOST
VC5
VC4
VC3
VC2
VC1
VC0
VOLUME
(dB)
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
−1
0
0
0
0
0
0
0
1
1
−2
0
0
:
:
:
:
:
:
:
0
1
1
1
0
1
1
−58
0
1
1
1
1
0
0
−59
1
1
1
1
0
1
−60
1
1
1
1
1
0
−∞
1
1
1
1
1
1
−∞
2002 May 16
BB3 BB2 BB1 BB0
17
FLAT
(dB)
MIN.
(dB)
MAX.
(dB)
0
0
0
0
1
0
2
2
1
0
0
4
4
0
1
1
0
6
6
1
0
0
0
8
8
0
1
0
1
0
10
10
0
1
1
0
0
12
12
0
1
1
1
0
14
14
1
0
0
0
0
16
16
1
0
0
1
0
18
18
1
0
1
0
0
18
20
1
0
1
1
0
18
22
1
1
0
0
0
18
24
1
1
0
1
0
18
24
1
1
1
0
0
18
24
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
7.21.2.3
Treble
UDA1341TS
7.21.2.6
A 2-bit value to program the treble setting. The used set
depends on the mode bits. The default setting is given in
Table 5.
Mute
A 1-bit value to enable the digital mute. The default setting
is given in Table 5.
Table 23 Mute settings
Table 20 Treble settings
MT
TREBLE
FUNCTION
0
no mute
1
mute
TR1
TR0
FLAT
(dB)
MIN.
(dB)
MAX.
(dB)
0
0
0
0
0
7.21.2.7
0
1
0
2
2
1
0
0
4
4
1
1
0
6
6
A 2-bit value to program the mode of the sound processing
filters of bass boost and treble. The default setting is given
in Table 5.
7.21.2.4
Table 24 Mode filter switch settings
Peak detection position
A 1-bit value to control the position of the peak level
detector in the signal processing path. The default setting
is given in Table 5.
Table 21 Peak detection position settings
PP
FUNCTION
0
before tone features
1
after tone features
7.21.2.5
De-emphasis
A 2-bit value to enable the digital de-emphasis filter.
The default setting is given in Table 5.
Table 22 De-emphasis settings
DE1
DE0
0
0
no de-emphasis
0
1
de-emphasis: 32 kHz
1
0
de-emphasis: 44.1 kHz
1
1
de-emphasis: 48 kHz
2002 May 16
Mode
FUNCTION
18
M1
M0
FUNCTION
0
0
flat
0
1
minimum
1
0
minimum
1
1
maximum
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
7.21.3
UDA1341TS
DATA0 EXTENDED PROGRAMMING REGISTERS
Table 25 Extended control registers
EA2
EA1
EA0
ED4
ED3
ED2
ED1
ED0
REGISTER SELECTED
0
0
0
MA4 MA3 MA2 MA1 MA0 MA = mixer gain channel 1 (5 bits)
0
0
1
MB4 MB3 MB2 MB1 MB0 MB = mixer gain channel 2 (5 bits)
0
1
0
MS2 MS1 MS0 MM1 MM0 MS = MIC sensitivity (3 bits)
1
0
0
MM = mixer mode (2 bits)
AG
0
0
IG1
IG0
AG = AGC control
IG = input amplifier gain channel 2 (2 bits)
1
0
1
IG6
IG5
IG4
IG3
IG2
IG = input amplifier gain channel 2 (5 bits)
1
1
0
AT2
AT1
AT0
AL1
AL0 AT = AGC time constant (3 bits)
AL = AGC output level (2 bits)
Programming via extended addressing is done by first
sending a DATA0 data byte EA (3 bits) which specifies the
addresses of the extended register followed by a DATA0
data byte which specifies the contents of the extended
data register (5 bits). The EA extended addresses and
names of the extended data registers are given in
Table 25.
7.21.3.1
7.21.3.2
A 3-bit value to program eight gain settings of the
microphone amplifier. These settings are valid only when
AGC control is enabled and not in the double differential
mode. The default setting is given in Table 5.
Table 27 MIC sensitivity settings
Mixer gain control
MS2 MS1 MS0
Two 5-bit values to program the channel 1 (MA) and
channel 2 (MB) coefficients in the mixer mode. The range
is from 0 to −∞ dB in steps of 1.5 dB. The default settings
are given in Table 5.
Table 26 Mixer gain control channel 1 and channel 2
settings
MA4 MA3 MA2 MA1 MA0
MB4 MB3 MB2 MB1 MB0
MIXER GAIN
(dB)
0
0
0
0
0
0
0
0
0
0
1
−1.5
0
0
0
1
0
−3.0
:
:
:
:
:
:
1
1
1
0
1
−43.5
1
1
1
1
0
−45.0
1
1
1
1
1
−∞
2002 May 16
MIC sensitivity
19
MIC AMPLIFIER GAIN
(dB)
−3
0
0
0
0
0
1
0
0
1
0
+3
0
1
1
+9
1
0
0
+15
1
0
1
+21
1
1
0
+27
1
1
1
not used
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
7.21.3.3
Mixer mode
UDA1341TS
7.21.3.6
Input channel 2 amplifier gain
A 2-bit value to program the mode of the digital mixer.
There are four modes: double differential, input channel 1
select, input channel 2 select and digital mixer mode.
The default setting is given in Table 5.
A 7-bit value to program the input channel 2 amplifier gain.
The range is from −3 to +60.5 dB in steps of 0.5 dB. These
settings are only valid when AGC control is disabled and
not valid in the double differential mode.
Table 28 Mixer mode switch settings
Table 31 Input channel 2 amplifier gain settings
MM1 MM0
FUNCTION
0
0
double differential mode
0
1
input channel 1 select (input channel 2 off)
1
0
input channel 2 select (input channel 1 off)
1
1
digital mixer mode
(input 1 × MA + input 2 × MB)
7.21.3.4
IG6 IG5 IG4 IG3 IG2 IG1 IG0
AGC control
A 1-bit value to enable the AGC input. The default setting
is given in Table 5.
Table 29 AGC control settings
INPUT
CHANNEL 2
AMPLIFIER
GAIN
(dB)
0
0
0
0
0
0
0
−3.0
0
0
0
0
0
0
1
−2.5
0
0
0
0
0
1
0
−2.0
0
0
0
0
0
1
1
−1.5
0
0
0
0
1
0
0
−1.0
0
0
0
0
1
0
1
−0.5
0
0
0
0
1
1
0
0.0
AG
FUNCTION
:
:
:
:
:
:
:
:
0
disable AGC: manual gain setting through
IG (7 bits)
1
1
1
1
1
0
1
59.5
1
1
1
1
1
1
0
60.0
enable AGC: gain control with manual MIC
sensitivity setting
1
1
1
1
1
1
1
60.5
1
7.21.3.7
7.21.3.5
AGC output level
AGC time constant
A 2-bit value to program the AGC output level. The default
setting is given in Table 5.
A 3-bit value to program the attack and the decay
parameters of the digital AGC. The default setting is given
in Table 5.
Table 30 AGC output level settings
Table 32 AGC time constant settings
AT2
AT1
AT0
ATTACK TIME
(ms)
DECAY TIME
(ms)
−9.0
0
0
0
11
100
1
−11.5
0
0
1
16
100
0
−15.0
0
1
0
11
200
1
−17.5
0
1
1
16
200
1
0
0
21
200
1
0
1
11
400
1
1
0
16
400
1
1
1
21
400
AL1
AL0
0
0
0
1
1
2002 May 16
OUTPUT LEVEL
(dB FS)
20
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
7.21.4
UDA1341TS
DATA1 CONTROL
Table 33 Data transfer of type ‘DATA1’
BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PL5
PL4
7.21.4.1
PL3
PL2
PL1
PL0
READ-OUT DATA
peak level value (6 bits)
Peak level value
A 6-bit value to indicate the peak level value of the playback data. The largest value of the left and right channel data in
the playback signal path is held since the last read-out of the microcontroller.
Table 34 Peak level read-out data
PEAK
VALUE(1)
(dB)
PL5
PL4
PL3
PL2
PL1
PL0
0
0
0
0
0
0
−∞
0
0
0
0
0
1
n.a.
0
0
0
0
1
0
n.a.
0
0
0
0
1
1
−90.31
0
0
0
1
0
0
n.a.
0
0
0
1
0
1
n.a.
0
0
0
1
1
0
n.a.
0
0
0
1
1
1
−84.29
:
:
:
:
:
:
:
0
1
0
0
1
1
note 2
0
1
0
1
0
0
note 3
:
:
:
:
:
:
:
1
1
1
1
0
1
−2.87
1
1
1
1
1
0
−1.48
1
1
1
1
1
1
0.00
Notes
1. Peak value (dB) = (Peak level − 63.5) × 5 × log 2.
11 × log 2
2. For peak data >010011, the error in the peak value is < -------------------------4
3. For peak data <010100, the error is larger due to limited bit length.
2002 May 16
21
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
UDA1341TS
8 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); VDDD = VDDA = 3 V; all voltages measured with
respect to ground; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDD
supply voltage
−
5.0
V
Txtal(max)
maximum crystal temperature
−
150
°C
Tstg
storage temperature
−65
+125
°C
Tamb
operating ambient temperature
−20
+85
°C
Ves
electrostatic handling
note 1
note 2
−2000
+2000
V
note 3
−250
+250
V
Ilu(prot)
latch-up protection current
Tamb = 125 °C; VDD = 3.6 V
−
200
mA
Isc(DAC)
DAC short-circuit current:
Tamb = 0 °C; VDD = 3.0 V;
note 4
−
482
mA
−
346
mA
output short-circuited to VSSA(DAC)
output short-circuited to VDDA(DAC)
Notes
1. All VDD and VSS connections must be made to the same power supply.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor.
3. Equivalent to discharging a 200 pF capacitor via a 2.5 μH series inductor.
4. DAC operation cannot be guaranteed after a short-circuit has occurred.
9
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
VALUE
UNIT
90
K/W
in free air
10 DC CHARACTERISTICS
VDDD = VDDA = 3 V; Tamb = 25 °C; RL = 5 kΩ; all voltages measured with respect to ground (pins 1, 11 and 27); unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDA(ADC) ADC analog supply voltage
note 1
2.4
3.0
3.6
V
VDDA(DAC) DAC analog supply voltage
note 1
2.4
3.0
3.6
V
note 1
2.4
3.0
3.6
V
VDDD
digital supply voltage
IDDA(ADC)
ADC analog supply current
IDDA(DAC)
DAC analog supply current
IDDD
digital supply current
2002 May 16
operation mode
−
12.5
−
mA
ADC power-down
−
6.0
−
mA
operation mode
−
7.0
−
mA
DAC power-down
−
50
−
μA
operation mode
−
7.0
−
mA
DAC power-down
−
4.0
−
mA
ADC power-down
−
3.0
−
mA
22
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
SYMBOL
PARAMETER
UDA1341TS
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital input pins
VIH
HIGH-level input voltage
0.8VDDD
−
VDDD + 0.5 V
VIL
LOW-level input voltage
−0.5
−
0.2VDDD
V
|ILI|
input leakage current
−
−
10
μA
Ci
input capacitance
−
−
10
pF
Digital output pins
VOH
HIGH-level output voltage
IOH = −2 mA
0.85VDDD −
−
V
VOL
LOW-level output voltage
IOL = 2 mA
−
0.4
V
−
Analog-to-digital converter
VADCP
positive reference voltage
−
VDDA
−
V
VADCN
negative reference voltage
0.0
0.0
0.0
V
Ro(ref)
Vref reference output resistance
pin 28
−
24
−
kΩ
Ri
input resistance
measured at 1 kHz
stand-alone mode
−
12.5
−
kΩ
double differential mode
−
6.25
−
kΩ
−
20
−
pF
microphone mode
−
12.5
−
kΩ
double differential mode
−
>1
−
MΩ
−
0.13
3.0
Ω
(THD + N)/S < 0.1%
−
0.22
−
mA
3
−
−
kΩ
note 2
−
−
50
pF
with respect to VSSA
0.45VDDA 0.5VDDA
0.55VDDA
V
Ci
input capacitance
Programmable gain amplifier (input channel 2)
Ri
input resistance
Digital-to-analog converter
Ro
output resistance
Io(max)
maximum output current
RL
load resistance
CL
load capacitance
Reference voltage
Vref
reference voltage
Notes
1. All power supply pins (VDD and VSS) must be connected to the same external power supply unit.
2. When higher capacitive loads (above 50 pF) must be driven then a resistor of 100 Ω must be connected in series
with the DAC output in order to prevent oscillations in the output operational amplifier.
2002 May 16
23
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
UDA1341TS
11 AC CHARACTERISTICS (ANALOG)
VDDD = VDDA = 3 V; fi = 1 kHz; fs = 44.1 kHz; Tamb = 25 °C; RL = 5 kΩ; all voltages measured with respect to ground
(pins 1, 11 and 27); unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Analog-to-digital converter
Vi(rms)
input voltage (RMS value)
ΔVi
unbalance between
channels
(THD + N)/S
total harmonic
distortion-plus-noise to
signal ratio
−
1.0
−
V
−
0.1
−
dB
0 dB
−
−85
−80
dB
−60 dB; A-weighted
−
−37
−33
dB
0 dB
−
−90
−85
dB
−60 dB; A-weighted
−
−40
−36
dB
stand-alone mode
−
97
−
dB
double differential mode
notes 1 and 2
stand-alone mode
double differential mode
S/N
signal-to-noise ratio
Vi = 0 V; A-weighted
−
100
−
dB
αcs
channel separation
−
100
−
dB
PSRR
power supply rejection ratio fripple = 1 kHz;
Vripple(p-p) = 30 mV
−
30
−
dB
Manual gain mode (AGC disabled)
Gmin
minimum gain
−
−3
−
dB
Gmax
maximum gain
−
60.5
−
dB
Gstep
digital gain step
−
0.5
−
dB
−3 dB setting
−
1414
−
mV
0 dB setting
−
1000
−
mV
Programmable gain amplifier
Vi(rms)
(THD + N)/S
2002 May 16
input voltage (RMS value)
total harmonic
distortion-plus-noise to
signal ratio
at full-scale
3 dB setting
−
708
−
mV
9 dB setting
−
355
−
mV
15 dB setting
−
178
−
mV
21 dB setting
−
89
−
mV
27 dB setting
−
44
−
mV
−3 dB setting
−
−75
−
dB
0 dB setting
−
−85
−
dB
3 dB setting
−
−85
−
dB
9 dB setting
−
−85
−
dB
15 dB setting
−
−80
−
dB
21 dB setting
−
−75
−
dB
27 dB setting
−
−75
−
dB
at 0 dB
24
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
SYMBOL
(THD + N)/S
PARAMETER
total harmonic
distortion-plus-noise to
signal ratio
UDA1341TS
CONDITIONS
MIN.
TYP.
MAX.
UNIT
at −60 dB; A-weighted
−3 dB setting
−
tbf
−
dB
0 dB setting
−
−37
−
dB
3 dB setting
−
tbf
−
dB
9 dB setting
−
tbf
−
dB
15 dB setting
−
tbf
−
dB
27 dB setting
−
tbf
−
dB
Digital-to-analog converter
Vo(rms)
output voltage (RMS value) note 3
−
900
−
mV
ΔVo
unbalance between
channels
−
0.1
−
dB
(THD + N)/S
total harmonic
distortion-plus-noise to
signal ratio
0 dB
−
−91
−86
dB
−60 dB; A-weighted
−
−40
−
dB
S/N
signal-to-noise ratio
code = 0; A-weighted
−
100
−
dB
αcs
channel separation
−
100
−
dB
PSRR
power supply rejection ratio fripple = 1 kHz;
Vripple(p-p) = 100 mV
−
50
−
dB
Notes
1. The ADC inputs can be used in a 2 V (RMS value) input signal configuration when a resistor of 12 kΩ is used in series
with the inputs and 1 or 2 V (RMS value) input signal operation can be selected via the Input Gain Switch (IGS).
2. The ADC input signal scales inversely proportional with the power supply voltage.
3. The DAC output voltage scales linear with the DAC analog supply voltage.
2002 May 16
25
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
UDA1341TS
12 AC CHARACTERISTICS (DIGITAL)
VDDD = VDDA = 2.7 to 3.6 V; Tamb = −20 to +85 °C; all voltages measured with respect to ground (pins 1, 11 and 27);
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System clock timing (see Fig.8)
Tsys
clock cycle time
fsys = 256fs
78
88
131
ns
fsys = 384fs
52
59
87
ns
fsys = 512fs
39
44
66
ns
tCWL
LOW-level pulse width
fsys < 19.2 MHz
0.30Tsys
−
0.70Tsys
ns
fsys ≥ 19.2 MHz
0.40Tsys
−
0.60Tsys
ns
tCWH
HIGH-level pulse width
fsys < 19.2 MHz
0.30Tsys
−
0.70Tsys
ns
fsys ≥ 19.2 MHz
0.40Tsys
−
0.60Tsys
ns
Serial input/output data timing (see Fig.9)
Tcy
bit clock cycle time
300
−
−
ns
tBCK(H)
bit clock HIGH time
100
−
−
ns
tBCK(L)
bit clock LOW time
100
−
−
ns
tr
rise time
−
−
20
ns
tf
fall time
−
−
20
ns
ts;DATI
data input set-up time
20
−
−
ns
th;DATI
data input hold time
0
−
−
ns
td;DATO(BCK)
data output delay time
(from BCK falling edge)
−
−
80
ns
td;DATO(WS)
data output delay time
(from WS edge)
−
−
80
ns
th;DATO
data output hold time
0
−
−
ns
ts;WS
word select set-up time
20
−
−
ns
th;WS
word select hold time
10
−
−
ns
MSB-justified format
Microcontroller L3-interface timing (see Figs 5 and 6)
Tcy(CLK)(L3)
L3CLOCK
500
−
−
ns
tCLK(L3)H
L3CLOCK HIGH time
250
−
−
ns
tCLK(L3)L
L3CLOCK LOW time
250
−
−
ns
tsu(L3)A
L3MODE set-up time
addressing mode
190
−
−
ns
th(L3)A
L3MODE hold time
addressing mode
190
−
−
ns
tsu(L3)D
L3MODE set-up time
data transfer mode
190
−
−
ns
th(L3)D
L3MODE hold time
data transfer mode
190
−
−
ns
tsu(L3)DA
L3DATA set-up time
data transfer and
addressing mode
190
−
−
ns
th(L3)DA
L3DATA hold time
data transfer and
addressing mode
30
−
−
ns
tstp(L3)
L3MODE halt time
190
−
−
ns
2002 May 16
26
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
UDA1341TS
tCWH
handbook, full pagewidth
tCWL
MGL443
Tsys
Fig.8 System clock timing.
handbook, full pagewidth
WS
tr
tBCK(H)
th;WS
tf
td(DATO)(BCK)
ts;WS
BCK
tBCK(L)
td(DATO)(WS)
th;DATO
Tcy
DATAO
ts;DATI
th;DATI
DATAI
MGG840
Fig.9 Serial interface timing.
2002 May 16
27
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
UDA1341TS
13 APPLICATION INFORMATION
handbook, full pagewidth L1
+3 V
BLM32A07
VDDA
VDDA
R21
1Ω
L2
VDDD
BLM32A07
C12
100 μF
(16 V)
ground
C2
C11
100 μF
(16 V)
VDDD
100 μF
(16 V)
100 μF
(16 V)
C21
C25
C29
100 nF
(63 V)
100 nF
(63 V)
100 nF
(63 V)
VSSD
VSSA(ADC) VDDA(ADC)
R30
system
clock
SYSCLK
47 Ω
DATAO
BCK
WS
DATAI
OVERFL
overflow
flag
1
R28
1Ω
C9
3
VADCN
VADCP
5
7
11
VDDD
10
12
18
28
16
C22
100 nF
(63 V)
17
19
VINL1
left
line input
C4
C6
MIC input
2
24
VINL2
C7
47 μF
(16 V)
VOUTR
C8
47 μF
(16 V)
6
VINR2 8
23
L3MODE
L3CLOCK
L3DATA
22
13
14
21
15
20
25
27
VSSA(DAC)
VDDA(DAC)
C27
100 nF
(63 V)
C10
100 μF
(16 V)
R29
1Ω
VDDA
Fig.10 Application diagram.
2002 May 16
left
output
UDA1341TS
47 μF
(16 V)
right
R23
100 Ω
R22
10 kΩ
VINR1 4
47 μF
(16 V)
left
C5
VOUTL
47 μF
(16 V)
47 μF
(16 V)
right
C3
47 μF
(16 V)
9
26
C1
Vref
28
MGR433
QMUTE
AGCSTAT
TEST2
TEST1
R26
100 Ω
R27
10 kΩ
right
output
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
UDA1341TS
14 PACKAGE OUTLINE
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
D
SOT341-1
E
A
X
c
HE
y
v M A
Z
28
15
Q
A2
pin 1 index
A
(A 3)
A1
θ
Lp
L
1
14
w M
bp
e
detail X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
10.4
10.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
1.1
0.7
8
o
0
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
OUTLINE
VERSION
SOT341-1
2002 May 16
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-150
29
o
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
15 SOLDERING
15.1
Introduction to soldering surface mount
packages
• For packages with leads on two sides and a pitch (e):
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
15.2
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
15.3
15.4
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
2002 May 16
UDA1341TS
30
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
15.5
UDA1341TS
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
not suitable
suitable(3)
HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
not
PLCC(4), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
REFLOW(2)
suitable
suitable
suitable
not
recommended(4)(5)
suitable
not
recommended(6)
suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your NXP Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 May 16
31
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
UDA1341TS
16 DATA SHEET STATUS
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary data sheet
Qualification
This document contains data from the preliminary specification.
Product data sheet
Production
This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
17 DISCLAIMERS
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at
the customer’s own risk.
Limited warranty and liability ⎯ Information in this
document is believed to be accurate and reliable.
However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
information.
Applications ⎯ Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
In no event shall NXP Semiconductors be liable for any
indirect, incidental, punitive, special or consequential
damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the
removal or replacement of any products or rework
charges) whether or not such damages are based on tort
(including negligence), warranty, breach of contract or any
other legal theory.
Customers are responsible for the design and operation of
their applications and products using NXP
Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole
responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as
for the planned application and use of customer’s third
party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks
associated with their applications and products.
Notwithstanding any damages that customer might incur
for any reason whatsoever, NXP Semiconductors’
aggregate and cumulative liability towards customer for
the products described herein shall be limited in
accordance with the Terms and conditions of commercial
sale of NXP Semiconductors.
NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and
products using NXP Semiconductors products in order to
avoid a default of the applications and the products or of
the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.
Right to make changes ⎯ NXP Semiconductors
reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
Suitability for use ⎯ NXP Semiconductors products are
not designed, authorized or warranted to be suitable for
use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
2002 May 16
32
NXP Semiconductors
Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
Limiting values ⎯ Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
Quick reference data ⎯ The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
Non-automotive qualified products ⎯ Unless this data
sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
product is not suitable for automotive use. It is neither
qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts
no liability for inclusion and/or use of non-automotive
qualified products in automotive equipment or
applications.
Terms and conditions of commercial sale ⎯ NXP
Semiconductors products are sold subject to the general
terms and conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an
individual agreement is concluded only the terms and
conditions of the respective agreement shall apply. NXP
Semiconductors hereby expressly objects to applying the
customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
In the event that customer uses the product for design-in
and use in automotive applications to automotive
specifications and standards, customer (a) shall use the
product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and
specifications, and (b) whenever customer uses the
product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at
customer’s own risk, and (c) customer fully indemnifies
NXP Semiconductors for any liability, damages or failed
product claims resulting from customer design and use of
the product for automotive applications beyond NXP
Semiconductors’ standard warranty and NXP
Semiconductors’ product specifications.
No offer to sell or license ⎯ Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control ⎯ This document as well as the item(s)
described herein may be subject to export control
regulations. Export might require a prior authorization from
national authorities.
2002 May 16
UDA1341TS
33
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: [email protected]
© NXP B.V. 2010
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753505/04/pp34
Date of release: 2002 May 16
Document order number:
9397 750 09805
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