DS9232A 03

RT9232A
Programmable Frequency Synchronous Buck PWM Controller
General Description
The RT9232A is a single-phase synchronous buck PWM
DC-DC converter controller designed to drive two N-Channel
MOSFET. It provides a highly accurate, programmable
output voltage precisely regulated to low voltage
requirement with an internal 0.8V ± 1% reference.
The RT9232A uses an external compensated, single
feedback loop voltage mode PWM control for fast transient
response. An oscillator with Programmable frequency
(50kHz to 800kHz) reduces the external inductor and
capacitor component size for saving PCB board area.
The RT9232A provides fast transient response to satisfy
high current output applications (up to 25A) while
minimizing external components. It is suitable for highperformance graphic processors, DDR and VTT power.
The RT9232A integrates complete protect functions such
as Soft Start, Output Enable, UVLO(under-voltage lockout)
into a small 14-pin package.
Ordering Information
RT9232A
Package Type
S : SOP-14
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :
`
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
Features
Single IC Supply Voltage : 12V
Single phase DC/DC Buck Converter with
` High Output Current (up to 25A )
` Low Output Voltage (down to 0.8V )
` High Input Voltage (up to 12V )
Operate from 12V, 5V or 3.3V Input
0.8V ± 1% Internal Reference
Adaptive Non-Overlapping Gate Drivers
Integrated High-Current, HV Gate Drivers
External Programmable Soft Start
External Programmable Frequency
(Range : 50kHz to 800kHz, 200kHz Free Run )
Integrated Output Short Circuit Protection
On/Off Control by Enable Pin
Drives Two N-MOSFET
Full 0 to 100% Duty Cycle
Fast Transient Response
Voltage Mode PWM Control with External
Feedback Loop Compensation
RoHS Compliant and 100% Lead (Pb)-Free
Applications
System (Graphic, MB) with 12V Power.
Graphic Cards (AGP 8X, 4X, PCI Express*16):
– High-Current for High-Performance Graphic Processors
(GPU, VPU)
– Middle Current for High-Performance Graphic Memory
Power (DDR, DDR II)
– Low Current with Sink Capacity for High-Performance
Graphic Memory Power (DDR/VTT)
3.3V to 12V Input DC-DC Regulators
Low Voltage Distributed Power Supplies
Pin Configurations
(TOP VIEW)
RT
SENSE
SS
COMP
FB
EN
GND
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
PVCC
LGATE
PGND
BOOT
UGATE
PHASE
SOP-14
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1
RT9232A
Typical Application Circuit
VIN
3.3V - 12V
L1
1uH
CE0
+
470uF
VCC
C2 0.22uF
CSS
1
9
SS
PHASE
RT
6 EN
7 GND
LGATE
4 COMP
PGND
FB
8
R5
0
C6
10uF
CE1
1000uF
CE2
1000uF
Q1
IPD09N03LA
L2
2.2uH
C4
0.1uF
R6
0
12
11
C5
0.1uF
C3 1nF
2
Q2
R7
2.2
CE3
+
R3
10k
10
+
VCC
SENSE
PVCC
UGATE
0.1uF 3
R2
51k
BOOT
+
13
VCC
+
14
+
R1
C1
2.2
0.22uF
R4
3.01k
D1
1N4148
CE4
VOUT
C8
C9
C10
C7
1nF
IPD06N03LA
5
2200uF 510uF 22uF
10uF 0.1uF
RT9232A
R9
1k
C11 33pF
C12
10nF
R8
15k
R10
562
C13
10nF
R11
1k
Functional Pin Description
No
Pin Name
Pin Function
1
RT
Oscillator Frequency Setting
2
SENSE
Sense VIN Power Condition
3
SS
Soft Start Time Interval Setting
4
COMP
Feedback Compensation
5
FB
Voltage Feedback
6
EN
Chip Enable (Active High)
7
GND
IC Signal Reference Ground
8
PHASE
Return Path for Upper MOSFET
9
UGATE
Upper MOSFET Gate Drive
10
BOOT
Input Supply for Upper Gate Drive
11
PGND
Power Ground
12
LGATE
Lower MOSFET Gate Drive
13
PVCC
Input Supply for Lower Gate Drive
14
VCC
Internal IC Supply (12V Bias)
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DS9232A-03 April 2011
RT9232A
Function Block Diagram
VCC
EN
VIN
Power-On
POR
Reset (POR)
SENSE
1.5V
Soft Start
and
Fault Logic
SS
0.6V
+
-
UV
INHIBIT
0.8V
-
POR
10uA
FB
+
+
+
-
+
- EA
+
Reference
PWM
Driver Logic
BOOT
UGATE
PHASE
PVCC
LGATE
COMP
PGND
Oscillator
GND
RT
Operation
Startup
RT9232A initializes automatically after receiving both VCC and VIN power. Special power-on sequence is not necessary.
The Power-On Reset (POR) function continually monitors input supply voltages and enable voltage. POR function
monitors IC power via VCC pin and external MOSFET power via SENSE pin. Voltage on SENSE pin is a fixed voltage
drop less than VIN. When voltages on VCC, SENSE, and EN pins exceed their thresholds, POR function initializes softstart operation. POR inhibits driver operation while EN pin pulls low. Transitioning EN pin high after input supply voltages
ready initializes soft-start operation.
Soft-Start
After POR function releases soft-start operation, an internal 10uA current source charges an external capacitor on SS
pin (Css) to 5V. Soft-start function clamps both COMP & FB pins to SS pin voltage & a fixed voltage drop less than SS
pin voltage respectively. Thus upper MOSFET turns on at a limited duty and output current overshoot can be reduced.
This method provides a rapid and controlled output voltage rise.
Under Voltage Protection
The under voltage protection function protects the converter from an shorted output by detecting the voltage on FB pin
to monitor the output voltage. The UVP function cycles soft-start function in a hiccup mode. When output voltage lower
than 75% of designated voltage, UVP function initializes soft-start cycles. The soft-start function discharges Css with
10uA current sink and disable PWM operation. Then soft-start function recharges Css and PWM operation resumes.
The soft-start hiccup restarts after SS voltage fully charges to 4V if the output short event still remains. The converter is
shutdown permanently after 3 times hiccup and only restarting supply voltages can enable the converter.
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RT9232A
Absolute Maximum Ratings
(Note 1)
Supply Input Voltage, VCC, PVCC ------------------------------------------------------------------------PHASE to GND
DC ----------------------------------------------------------------------------------------------------------------< 200ns ---------------------------------------------------------------------------------------------------------BOOT to PHASE ---------------------------------------------------------------------------------------------BOOT to GND
DC ----------------------------------------------------------------------------------------------------------------< 200ns ---------------------------------------------------------------------------------------------------------SS, FB, COMP, RT -------------------------------------------------------------------------------------------Input, Output or I/O Voltage --------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
SOP-14, θJA ---------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Mode) ---------------------------------------------------------------------------------MM (Machine Mode) -----------------------------------------------------------------------------------------
Recommended Operating Conditions
15V
−5V to 15V
−10V to 30V
15V
−0.3V to VCC+15V
−0.3V to 42V
6V
GND−0.3V to VCC+ 0.3V
100°C/W
260°C
150°C
−65°C to 150°C
2kV
200V
(Note 4)
Supply Input Voltage, VCC ---------------------------------------------------------------------------------Supply Voltage to Drain of Upper MOSFETs, VIN -----------------------------------------------------Ambient Temperature Range -------------------------------------------------------------------------------Junction Temperature Range --------------------------------------------------------------------------------
12V ±10%
3.3V, 5V to 12V ±10%
0°C to 70°C
0°C to 125°C
Electrical Characteristics
(VCC = 12V, TA = 25°C, Unless otherwise specified.)
Parameter
Symbol
Test Conditions
Min
Typ.
Max
Unit
ICC
EN=VC C, UGATE, LGATE open
--
3
--
mA
VCC _ON
V SENSE = 4.5V
8.4
--
10
V
V SENSE = 4.5V
0.4
0.7
--
V
--
1.5
2
V
VCC Supply Current
Nominal Supply Current
Power-On Reset (POR)
V CC Rising Threshold
Power On Reset Hysteresis
SENSE Rising Threshold for start up VSENSE_ON
Enable Input Threshold (ON)
VEN_ON
V SENSE = 4.5V
--
--
2
V
Enable Input Threshold (OFF)
VEN,_OFF
V SENSE = 4.5V
0.8
--
--
V
170
200
230
kHz
20
%
Oscillator
Free Running Frequency
RT9232A
fOSC
Variation
Ramp Amplitude
6k < (RT to GND) < 200k
Δ VOSC
−20
--
2
--
VP-P
0.792
0.8
0.808
V
Reference
Error Amplifier Reference Voltage
VREF
To be continued
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DS9232A-03 April 2011
RT9232A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
--
88
--
dB
--
15
--
MHz
--
6
--
V/μs
7
10
--
μA
Error Amplifier
DC gain
Gain-Bandwidth product
GBW
Slew Rate
SR
COMP=10pF
Soft Start
External SS Source Current
ISS
PWM Controller Gate Driver
Upper Drive Source
RUG_SC
V BOOT-PH ASE = 12V
V BOOT-UGATE = 1V
--
3.3
--
Ω
Upper Drive Sink
RUG_SK
V BOOT-PH ASE = 12V
V UGATE-PHASE = 1V
--
3.7
--
Ω
Lower Drive Source
RLG_SC
V PVCC – LGATE = 1V
--
2.5
--
Ω
Lower Drive Sink
RLG_SK
V LGATE – PGND = 1V
--
2.1
--
Ω
Upper Drive Source
IUG_SC
V BOOT-UGATE = 12V
--
1.7
--
A
Upper Drive Sink
IUG_SK
V UGATE-PHASE = 12V
--
1.2
--
A
Lower Drive Source
ILG_SC
V PVCC – LGATE = 12V
--
2.6
--
A
Lower Drive Sink
ILG_SK
V LGATE – PGND = 12V
--
2.4
--
A
0.5
0.6
0.7
V
--
30
--
μs
Driving Capability
Protection
Under-Voltage Protection
FB Falling
Under-Voltage Protection Delay
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
DS9232A-03 April 2011
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RT9232A
Typical Operating Characteristics
Efficient vs. Output Current
RRT vs. Oscillator Frequency
100
1000
Pull high to VCC
VIN = 3.3V
VIN = 5V
VIN = 12V
80
100
(kΩ)
RRT (k
)
Efficient (%)
90
70
10
Pull down to GND
60
50
1
0
5
10
15
20
25
30
0
100
200
300
400
500
600
Output Current (A)
Frequency (kHz)
Dead Time
Dead Time
800
Loading = 0A
Loading = 0A
UGATE
UGATE
(5V/Div)
700
PHASE
PHASE
VGS
VGS
(5V/Div)
LGATE
LGATE
Time (25ns/Div)
Time (25ns/Div)
UVP
Bootstrap Wave Form
VCC = EN (2V/Div)
SS (5V/Div)
V OUT
(500mV/Div)
LGATE
(5V/Div)
PHASE
(5V/Div)
UGATE
(5V/Div)
FB (500mV/Div)
UGATE (10V/Div)
Time (20ms/Div)
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Time (1us/Div)
DS9232A-03 April 2011
RT9232A
Power On
Power On
EN (2V/Div)
EN (2V/Div)
(500mV/Div)
SS (1V/Div)
VOUT (500mV/Div)
IOUT (1A/Div)
V OUT
COMP (500mV/Div)
SS (1V/Div)
Time (10ms/Div)
Time (10ms/Div)
Power On
Power Off
VOUT (500mV/Div)
VCC = EN (2V/Div)
VOUT (500mV/Div)
UGATE (10V/Div)
SS (2V/Div)
LGATE (10V/Div)
IOUT (10A/Div)
IOUT (2A/Div)
Time (10ms/Div)
Time (10ms/Div)
Power Off
Load Transient Response
LGATE (10V/Div)
VOUT (500mV/Div)
UGATE (20V/Div)
UGATE (10V/Div)
IL (10A/Div)
LGATE (10V/Div)
Time (20us/Div)
DS9232A-03 April 2011
V OUT
(2V/
IL (20A/Div)
Time (200us/Div)
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RT9232A
Load Transient Response
IL (10A/Div)
Load Transient Response
@IOUT = 30A to 1A
@IOUT = 1A to 30A
VOUT (500mV/Div)
VOUT (500mV/Div)
IL (10A/Div)
UGATE (20V/Div)
UGATE (20V/Div)
LGATE (10V/Div)
Time (10us/Div)
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LGATE
(10V/Div)
Time (4us/Div)
DS9232A-03 April 2011
RT9232A
Application Information
The RT9232A is a single-phase synchronous buck PWM
DC-DC converter controller designed to drive two N-Channel
MOSFETs. It provides a highly accurate, programmable
output voltage precisely regulated to low voltage
requirement with an internal 0.8V ±1% reference.
whichever is smaller dominates the behavior of the devices.
During T0~T1, since SS is smaller than the sawtooth valley,
the PWM comparator outputs low no matter what the
COMP voltage is.
Initialization
During T1~T2, EA keeps COMP voltage low that makes
the PWM output low.
The RT9232A automatically initiates its softstart cycle
only after VCC and VIN power and chip enabling signals
are ready. There is no special power-on sequence should
be took care especially while implement the chip in. The
internal Power-On Reset (POR) logic continually monitors
the voltage level of input power and enabling pin; in which
the IC supply power is monitored via VCC pin and input
power VIN is via SENSE pin. An internal current source
with driving capability of 200uA causes a fixed voltage
drop across the resistor connecting VIN to SENSE pin.
The RT9232A internal logic will deem the input voltage
ready once the voltage of SENSE pin is high than 1.5V.
The preferred VIN ready level could be set by selecting an
appropriate resistor RSENSE as:
VIN_READY − 1.5V
RSENSE <
Ω
200 μA
Once all voltages of VCC, SENSE, and EN pins ramp
higher than the internal specific thresholds. The internal
POR logic will initialize the softstart operation then.
Moreover, the POR inhibits driver operation while pulling
the EN pin low. Transitioning EN pin high after input supply
voltages ready to initialize soft-start operation.
T1~T2
T2~T3
SSE ramps up and dominates the behavior of EA during
T2~T3. EA regulates COMP appropriately so that FB
ramps up along the SSE curve. The output voltage ramps
up accordingly. Thus upper MOSFET turns on at a limited
duty and output current overshoot can be reduced.
It is noted that lower MOSFET keeps off before the upper
MOSFET starts switching. This method provides smooth
start up when there is residual voltage on output capacitors.
The output voltage delay time and ramp up time are
calculated as Equation (1) and (2) respectively.
T2 − T0 =
1.2V x CSS
(s)
10uA
(1)
T3 − T2 =
1.6V x CSS
(s)
10uA
(2)
SSE
FB
Soft-Start
The behavior of RT9232A Soft-Start can be simply
described as shown as Figure.1 below; and the Soft-Start
can be sliced to several time-frames with specific operation
respectively.
SS
EA
COMP
PWM
0.8V
5V
SS
T0~T1
The RT9232A initiates the softstart cycle as shown in
Figure 1 when POR function is OK. An internal 10uA current
source charges an external capacitor on SS pin (Css) to
5V. The softstart function produces an SSE signal that is
equal to (SS-1.2V)/2. Error Amplifier (EA) and PWM
comparator are triple-input devices. The non-inverting input
DS9232A-03 April 2011
SSE
COMP
1V
FB
0.8V
T0
T1T2
T3
Figure 1. Timing diagram of softstart
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RT9232A
Switching Frequency Setting
The default switching frequency is 200kHz when RT pin
left open. A resistor connected (RRT) from RT pin to ground
increases the switching frequency as Equation (3).
fOSC = 200kHz +
2.9 x 10 6
kHz (3) (RRT to GND)
RRT (Ω)
Conversely, connecting a pull-up resistor (RRT) from RT pin
reduces the switching frequency according to Equation (4)
fOSC = 200kHz −
circuit short as shown in Figure 2. The SCP will be
triggered while the POR is triggered 3 times including the
1st POR of system power on. While the SCP been
triggered, the fault is latched until the VCC power is
removed.
(2V/Div)
SS
(20V/Div)
6
33 x 10
kHz (4) (RRT to VCC = 12V)
RRT (Ω)
Under Voltage Protection
The under voltage protection is enabled when the RT9232A
is activated and SS voltage is higher than 4V. The UVP
function is specified for protecting the converter from an
instant output short circuit during normal operation. The
RT9232A continuously monitors the output voltage by
detecting the voltage on FB pin. The UVP function is
triggered and initiates the hiccup cycles when output
voltage lower than 75% of designated voltage with a 30us
delay.
Hiccup cycle turns off both upper and lower MOSFET first.
An internal 10uA current sink discharges the softstart
capacitor CSS. SS pin voltage ramps down linearly. When
SS pin voltage touches 0V, hiccup cycle releases and
normal softstart cycle takes over. When SS voltage is
higher than 4V, the UVP function is enabled again. The
hiccup cycle restarts if the output short event still remains.
The converter is shutdown permanently after 3 times hiccup
and only restarting supply voltages can enable the
converter.
Note that triggering the POR function or EN will reset the
hiccup counter. Make sure that VCC, EN and SENSE pin
voltages are higher than their respective trip level when
output short circuit occurs or the UVP function may not
latch up the converter causing permanent damage to the
converter.
UGATE
(2V/Div)
VIN
VOUT
(10V/Div)
POR1
POR2
POR3
Figure 2
As shown as Figure 3. The POR of the chip could be
triggered by three major signal including 5VBUS which is
applied for internal logic use only, 12V, and EN. The POR
will be issued if all of the 3 events are true.
Per RT9232A implementation, the EN is one of signals
will trigger SCP, and it's possible to mal-trigger SCP while
a unclear EN signals being applied. The enabling circuitry
should be took care specially while implementing the EN
circuit.
5VBUS
5VBUS
12V > VCC_ON
EN > VEN_ON
POR
Figure 3
Component Selection
Components should be appropriately selected to ensure
stable operation, fast transient response, high efficiency,
minimum BOM cost and maximum reliability.
Output Inductor Selection
Short Circuit Protection
There is a protection implemented in RT9232A for short
circuit protection, the protection can significantly protect
the power stage from burn-out while the congenital output
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The selection of output inductor is based on the
considerations of efficiency, output power and operating
frequency. For a synchronous buck converter, the ripple
current of inductor (ΔIL) can be calculated as follows:
DS9232A-03 April 2011
RT9232A
ΔIL = (VIN − VOUT) x
VOUT
VIN x fOSC x L
PUPPER = PCOND _UPPER + PSW_UPPER
(5)
Output Capacitor Selection
The output capacitors determine the output ripple voltage
(ΔVOUT) and the initial voltage drop after a high slew-rate
load transient. The selection of output capacitor depends
on the output ripple requirement. The output ripple voltage
is described as Equation (6).
VOUT
1
x 2
(1 − D)
8 fOSC
x L x COUT
(6)
For electrolytic capacitor application, typically 90~95%
of the output voltage ripple is contributed by the ESR of
output capacitors. Paralleling lower ESR ceramic capacitor
with the bulk capacitors could dramatically reduce the
equivalent ESR and consequently the ripple voltage.
Input Capacitor Selection
Use mixed types of input bypass capacitors to control
the input voltage ripple and switching voltage spike across
the MOSFETs. The buck converter draws pulsewise
current from the input capacitor during the on time of upper
MOSFET. The RMS value of ripple current flowing through
the input capacitor is described as:
IIN(RMS) = IOUT x D x (1 − D)
(7)
The input bulk capacitor must be cable of handling this
ripple current. Sometime, for higher efficiency the low ESR
capacitor is necessarily. Appropriate high frequency
ceramic capacitors physically near the MOSFETs
effectively reduce the switching voltage spikes.
MOSFET Selection
The selection of MOSFETs is based upon the
considerations of RDS(ON), gate driving requirements, and
thermal management requirements. The power loss of
upper MOSFET consists of conduction loss and switching
loss and is expressed as:
DS9232A-03 April 2011
1
IOUT x VIN x (TRISE + TFALL ) x fOSC
2
where TRISE and TFALL are rising and falling time of VDS of
= IOUT x RDS(ON) x D +
Generally, an inductor that limits the ripple current between
20% and 50% of output current is appropriate. Make sure
that the output inductor could handle the maximum output
current and would not saturate over the operation
temperature range.
ΔVOUT = ΔIL x ESR +
(8)
upper MOSFET respectively. RDS(ON) and QG should be
simultaneously considered to minimize power loss of upper
MOSFET.
The power loss of lower MOSFET consists of conduction
loss, reverse recovery loss of body diode, and conduction
loss of body diode and is express as:
PLOWER = PCOND _LOWER + PRR + PDIODE
(9)
= IOUT x RDS(ON) x (1 − D) + QRR x VIN x fOSC
1
x IOUT x VF x TDIODE x fOSC
2
where TDIODE is the conducting time of lower body diode.
+
Special control scheme is adopted to minimize body diode
conducting time. As a result, the RDS(ON) loss dominates
the power loss of lower MOSFET. Use MOSFET with
adequate RDS(ON) to minimize power loss and satisfy
thermal requirements.
Feedback Compensation
Figure 4 highlights the voltage-mode control loop for a
synchronous buck converter. Figure 5 shows the
corresponding Bode plot. The output voltage (VOUT) is
regulated to the reference voltage. The error amplifier EA
output (COMP) is compared with the oscillator (OSC)
sawtooth wave to provide a pulse-width modulated (PWM)
wave with an amplitude of VIN at the PHASE node. The
PWM wave is smoothed by the output filter (L and COUT).
The modulator transfer function is the small-signal transfer
function of VOUT/COMP. This function is dominated by a
DC gain and the output filter (L and COUT), with a double
pole break frequency at FP_LC and a zero at FZ_ESR. The
DC gain of the modulator is simply the input voltage (VIN)
divided by the peak-to-peak oscillator voltage ΔVOSC.
The break frequency FLC and FESR are expressed as
Equation (10) and (11) respectively.
FP_LC =
1
2π LC OUT
FZ_ESR =
1
2π x ESR x COUT
(10)
(11)
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RT9232A
The equations below relate the compensation network
poles, zeros and gain to the components (R1, R2, R3,
C1, C2, and C3) in Figure 4.
100
FZ1 FZ2
1
2π x R2 x C1
FZ2
Open Loop Error
AMP Gain
40
20
20LOG
(R1/R2)
0
-20
Closed Loop Gain
-40
FLC
-60
100
1K
FESR
10K
100K
1M
10M
Frequency (Hz)
(13)
Feedback Loop Design Procedure
C1 x C2
2π x R2 x
C1 + C2
1
2π x R3 x C3
(14)
Use these guidelines for locating the poles and zeros of
the compensation network:
(15)
1. Pick Gain (R2/R1) for desired 0dB crossing frequency
(FC).
2. Place 1ST zero FZ1 below modulator double pole FLC
(~75% FLC).
VIN
OSC
3. Place 2ND zero FZ2 at modulator double pole FLC.
Driver
PWM
Comparator
ΔVOSC
Compensation
Gain
Modulator
Gain
Figure 5
1
FP2 =
20LOG
(VIN/ΔVOSC)
(12)
1
=
2π x (R1 + R3) x C3
FP1 =
FP2
60
10
FZ1 =
FP1
80
Gain (dB)
The compensation network consists of the error amplifier
EA and the impedance networks ZIN and ZFB. The goal of
the compensation network is to provide a closed loop
transfer function with the highest DC gain, the highest
0dB crossing frequency (FC) and adequate phase margin.
Typically, FC in range 1/5~1/10 of switching frequency is
adequate. The higher FC is, the faster dynamic response
is. A phase margin in the range of 45°C~ 60°C is desirable.
L
-
Driver
+
PHASE
COUT
ESR
VE/A
ZFB
VOUT
4. Place 1ST pole FZ1 at the ESR zero FZ_ESR
5. Place 2ND pole FZ2 at half the switching frequency.
6. Check gain against error amplifier’s open-loop gain.
7. Pick RFB for desired output voltage.
ZIN
EA
+
8. Estimate phase margin and repeat if necessary.
REF
Layout Consideration
ZFB
C2
C1
R2
FB
REF
Figure 4
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12
R3
R1
COMP
EA
+
ZIN
C3
VOUT
Layout is very important in high frequency switching
converter design. If designed improperly, the PCB could
radiate excessive noise and contribute to the converter
instability. First, place the PWM power stage components.
Mount all the power components and connections in the
top layer with wide copper areas. The MOSFETs of Buck,
inductor, and output capacitor should be as close to each
other as possible. This can reduce the radiation of EMI
due to the high frequency current loop. If the output
capacitors are placed in parallel to reduce the ESR of
capacitor, equal sharing ripple current should be
considered. Place the input capacitor directly to the drain
DS9232A-03 April 2011
RT9232A
of high-side MOSFET. The MOSFETs of linear regulator
should have wide pad to dissipate the heat. In multilayer
PCB, use one layer as power ground and have a separate
control signal ground as the reference of the all signal. To
avoid the signal ground is effect by noise and have best
load regulation, it should be connected to the ground
terminal of output. Furthermore, follows below guidelines
can get better performance of IC:
(1). The IC needs a bypassing ceramic capacitor as a R-C
filter to isolate the pulse current from power stage and
supply to IC, so the ceramic capacitor should be placed
adjacent to the IC.
(2). Place the high frequency ceramic decoupling close
to the power MOSFETs.
(3). The feedback part should be placed as close to IC as
possible and keep away from the inductor and all noise
sources.
(4). The components of bootstraps should be closed to
each other and close to MOSFETs.
(5).The PCB trace from Ug and Lg of controller to
MOSFETs should be as short as possible and can carry
1A peak current.
(6). Place all of the components as close to IC as possible.
DS9232A-03 April 2011
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13
RT9232A
Outline Dimension
H
A
M
J
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
8.534
8.738
0.336
0.344
B
3.810
3.988
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.508
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.178
0.254
0.007
0.010
I
0.102
0.254
0.004
0.010
J
5.791
6.198
0.228
0.244
M
0.406
1.270
0.016
0.050
14–Lead SOP Plastic Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
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Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
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14
DS9232A-03 April 2011
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