RT8106/A 5V/12V Synchronous Buck PWM DC-DC Controller General Description Features The RT8106/A is a DC/DC synchronous buck PWM controller with embedded driver support up to 12V+12V boot-strapped voltage for high efficiency power driving. The part integrates full functions of voltage regulation, power monitoring and protection into a single small footprint WDFN-10L 3x3 (Exposed Pad) package. z Single 5 to 12V Bias Supply z Drive All Low Cost N-MOSFETs Support High Current Application up to 30A High-Gain Voltage Mode PWM Control 300kHz/600kHz Fixed Frequency Oscillator Fast Transient Response : ` High-Speed EA Amplifier ` 0 to 85% Duty Ratio ` External Compensation in The Control Loop Internal Soft-Start Adaptive Non-Overlapping Gate Driver Over Current Fault Monitor on low side MOSFET RoHS Compliant and 100% Lead (Pb)-Free z z z z z z z Ordering Information RT8106/A Package Type QW : WDFN-10L 3x3 (W-Type) Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free) Applications z z z z Graphic Card Motherboard, Desktop Servers IA and Telecom Equipment General High Power DC/DC Regulator Pin Configurations (TOP VIEW) 600kHz 300kHz BOOT LX UGATE LGATE GND Note : Richtek products are : ` 1 2 3 4 5 GND 11 10 9 8 7 9 The RT8106/A adopts a high-gain voltage mode PWM control for simple application design. An internal 0.8V reference allows the output voltage to be precisely regulated for low voltage requirement. Based on all RT8106/A features, the part provides an optimum compromise between efficiency, total B.O.M. count, and cost. z PGOOD VOS FB COMP/EN VCC WDFN-10L 3x3 RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. Marking Information RT8106GQW DY=YM DNN RT8106AGQW DY= : Product Code YMDNN : Date Code DS8106/A-04 April 2011 EP= : Product Code EP=YM DNN YMDNN : Date Code www.richtek.com 1 RT8106/A RT8106ZQW RT8106AZQW DY : Product Code EP : Product Code YMDNN : Date Code DY YM DNN YMDNN : Date Code EP YM DNN Typical Application Circuit VGD 6 VCC CBP 10 PGOOD 7 RT8106/A BOOT 1 VCC PGOOD D1 RBOOT Rf Q2 GND 5, Exposed Pad (11) R7 C7 RL RFB RB CB FB 8 9 VOS Cf L1 2 LGATE 4 CP VOUT Q1 ROCSET EN C4 CBOOT RUGATE UGATE 3 LX COMP/EN VIN RFB COUT ROFFSET ROFFSET Functional Pin Description Pin No. Pin Name Pin Function This pin is boot-strapped by external capacitor and is applied for the embedded 1 BOOT 2 LX Phase node of PWM. 3 UGATE High Side gate drive. 4 LGATE Low Side gate drive. It also acts as OC setup pin by adjusting a resistor connecting to GND. 5, 11 (Exposed Pad) GND 6 VCC 7 COMP/EN 8 FB 9 VOS 10 PGOOD High Side gate driver power. Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. VCC is generally applied for bias power for IC logics and gate driver control. To connect a 1μF bypass capacitor to GND is recommended. Compensation pin of PWM and Output of the PWM error amplifier. Connect www.richtek.com 2 compensation network between this pin and FB. This pin is also applied as Enable pin. PWM Feedback. The output feedback of PWM. The pin is applied for voltage regulation. The pin is scaled to be 0.8v and provides under voltage protection, over voltage protection and PGOOD function. This pin is an open drain driver and Indicates PWM output regulated in +/-10%. DS8106/A-04 April 2011 RT8106/A Function Block Diagram COMP/EN FB BOOT UGATE LX - 0.8V LGATE -1 + LX UV_level VOS IOC + + PGH_level - OC LGATE UV - OV_level + + OV Control Logic EN PGOOD + - PGL_level + DS8106/A-04 April 2011 GND www.richtek.com 3 RT8106/A Absolute Maximum Ratings (Note 1) Supply Voltage, VCC -------------------------------------------------------------------------------------- 15V BOOT to LX ------------------------------------------------------------------------------------------------- 15V z Input, Output or I/O Voltage ----------------------------------------------------------------------------- (GND−0.3V) to 7V z LX to GND DC ------------------------------------------------------------------------------------------------------------- −5V to 18V < 200ns ------------------------------------------------------------------------------------------------------ −10V to 30V z BOOT to GND DC ------------------------------------------------------------------------------------------------------------- −0.3V to 30V < 200ns ------------------------------------------------------------------------------------------------------ −0.3V to 42V z UGATE ------------------------------------------------------------------------------------------------------- (VLX − 0.3V) to (VBOOT + 0.3V) < 200ns ------------------------------------------------------------------------------------------------------ (VLX − 5V) to (VBOOT + 5V) z LGATE ------------------------------------------------------------------------------------------------------- (GND − 0.3V) to( VCC + 0.3V) < 200ns ------------------------------------------------------------------------------------------------------ (GND − 5V) to (VCC + 5V) z Power Dissipation, PD @ TA = 25°C (Note 2) WDFN-10L 3x3 --------------------------------------------------------------------------------------------- 1.429W z Package Thermal Resistance WDFN-10L 3x3, θJA --------------------------------------------------------------------------------------- 70°C/W WDFN-10L 3x3, θJC --------------------------------------------------------------------------------------- 8.2°C/W z Junction Temperature ------------------------------------------------------------------------------------- 150°C z Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------- 260°C z Storage Temperature Range ---------------------------------------------------------------------------- −65°C to 150°C z ESD Susceptibility (Note 3) HBM (Human Body Mode) ------------------------------------------------------------------------------ 2kV MM (Machine Mode) -------------------------------------------------------------------------------------- 200V z z Recommended Operating Conditions z z z (Note 4) Supply Voltage, VCC -------------------------------------------------------------------------------------- 12V ± 10%, 5V ± 5% Junction Temperature Range ---------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ---------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VCC = 12V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 4.75 12 13.2 V -- 4 -- mA 3.9 4.1 4.35 V -- 0.3 -- V 1.5 2.7 4 ms -- 0.8 -- V Output Voltage Accuracy −0.8 -- 0.8 % Thermal Shutdown Limit -- 140 -- °C General Supply Input Voltage VCC Nominal Supply Current I CC No Load for UGATE/ LGATE VCC POR Threshold VPOR VCC Rising VCC POR Hysteresis VPOR_Hys Soft-Start Interval TSS Reference Voltage VREF FB rising from 10% to 90% To be continued www.richtek.com 4 DS8106/A-04 April 2011 RT8106/A Parameter Symbol Test Conditions Min Typ Max Unit PWM Controller EA Open Loop Gain GEA -- 80 -- dB EA Bandwidth BW -- 15 -- MHz RT8106 -- 85 -- % RT8106A -- 80 -- % Maximum Duty UGATE Drive Source IUGATEsr 1.5 -- -- A LGATE Drive Source ILGATEsr 1.5 -- -- A UGATE Drive Sink RUGATEsk -- 1.1 -- Ω LGATE Drive Sink RLGATEsk -- 0.65 -- Ω -- 1.6 -- V -- 1.2 -- V 270 300 330 540 600 660 Ramp Valley ΔVOSC Ramp Amplitude PWM Frequency RT8106 RT8106A f OSC kHz Over Voltage Threshold OVP Relative to VOS 115 125 135 % Under Voltage Threshold UVP Relative to VOS 65 75 80 % PGOOD Threshold PGOOD Relative to VOS 90 -- 110 % OC Current Source IOC 9 10 11 μA OC Preset Trigger Voltage VOC_Preset -- 0.55 -- V Disable Threshold VDIS -- -- 0.5 V Relative to VOS Rising 85 -- 95 % Relative to VOS Falling 105 -- 115 % -- -- 0.4 V PGOOD Active Threshold PGOOD Low Level ROCSET is not Connected VOL_PGOOD Sink 4mA Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. The case point of θJC is on the expose pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. DS8106/A-04 April 2011 www.richtek.com 5 RT8106/A Typical Operating Characteristics Switching Frequency vs. Temperature 350 1.6060 340 Switching Frequency (kHz)1 Output Voltage (V) Output Voltage vs. Temperature 1.6065 1.6055 1.6050 1.6045 1.6040 1.6035 1.6030 1.6025 1.6020 VIN = 12V, ILOAD = 0A -20 0 20 40 330 320 310 300 290 280 270 260 VIN = 12V, VOUT = 1.6V, ILOAD = 0A 250 60 80 100 120 140 -20 0 Temperature (°C) 60 80 100 120 140 Load Transient Response LGATE (10V/Div) LGATE (10V/Div) UGATE (20V/Div) UGATE (20V/Div) VOUT (100mV/Div) VOUT (100mV/Div) VIN = 12V, VOUT = 1.6V, ILOAD = 0A to 20A 40 Temperature (°C) Load Transient Response I LOAD (10A/Div) 20 I LOAD (10A/Div) VIN = 12V, VOUT = 1.6V, ILOAD = 20A to 0A Time (10μs/Div) Time (10μs/Div) Load Transient Response Dead Time Rising UGATE LGATE (10V/Div) UGATE-PHASE UGATE (20V/Div) PHASE VOUT (100mV/Div) I LOAD (10A/Div) (5V/Div) LGATE VIN = 12V, VOUT = 1.6V, ILOAD = 0A to 20A to 0A Time (200μs/Div) www.richtek.com 6 VIN = 12V, VOUT = 1.6V, ILOAD = 5A Time (25ns/Div) DS8106/A-04 April 2011 RT8106/A Dead Time VIN = VCC Power On Falling UGATE LGATE (10V/Div) PHASE UGATE (20V/Div) UGATE-PHASE (5V/Div) LGATE VIN = 12V, VOUT = 1.6V, ILOAD = 5A V CC (10V/Div) VOUT (2V/Div) VCC = VIN = 12V, VOUT = 1.6V, ILOAD = 10A Time (25ns/Div) Time (2.5ms/Div) VIN = VCC Power Off COMP Enable Power On LGATE (10V/Div) LGATE (10V/Div) UGATE (20V/Div) UGATE (20V/Div) V CC (10V/Div) VCOMP (1V/Div) VOUT (2V/Div) VOUT (2V/Div) VCC = VIN = 12V, VOUT = 1.6V, ILOAD = 10A VIN = 12V, VOUT = 1.6V, ILOAD = 10A Time (1ms/Div) Time (1ms/Div) Efficiency vs. Load Current COMP Disable Power Off 95 90 LGATE (10V/Div) Efficiency (%) 85 UGATE (20V/Div) VCOMP (1V/Div) VOUT (2V/Div) 80 75 70 65 60 55 VIN = 12V, VOUT = 1.6V, ILOAD = 10A Time (1ms/Div) VIN = VCC = 12V, VOUT = 1.6V, f = 300kHz 50 0 5 10 15 20 25 30 Load Current (A) DS8106/A-04 April 2011 www.richtek.com 7 RT8106/A Application Information Overview The RT8106/A is a high efficiency synchronous buck PWM controller that can generate adjustable DC output voltage. This device is embedded with high current High Side and Low Side MOSFET drivers, and many protection functions (OCP, UVP, OVP) into a tiny package. Simple board design and low BOM cost can be easily achieved by the high integration feature to make this part to be an ideal solution for general applications. Chip Enable/Disable Pull pin 7 (COMP/EN) to be lower than 0.5V can shut down the device. This allows flexible power sequence control for specified application. Setting free this pin can enable the RT8106/A again. Power On Reset (POR) The RT8106/A automatically initializes upon applying of input power (at the VCC) pin. The power on reset function (POR) continually monitors the VCC supply voltage. The POR threshold is typically 4.1V at VCC rising. Input Power (Vin) Detection The RT8106/A continuously generates a 10kHz pulse train with 1us pulse width to turn on the upper MOSFET for detecting the existence of VIN after VCC POR and Comp/ EN pin enabled. As shown in Figure 1. the LX pin voltage is monitored during the detection period. If the LX pin voltage exceeds 1.5V threshold for four times, the VIN existence is recognized and the RT8106/A initiates its soft start cycle. LX + - 1.5V UGATE 1st 2nd 3rd 4th LX waveform Internal Counter will count (V LX > 1.5V) four times (rising & falling) to recognize V IN is ready. Figure 1. VIN Power Detection Soft Start A built-in soft-start is used to prevent surge current from V IN to V OUT during power on. The soft-start (SS) automatically begins once the existence of VIN is detected. www.richtek.com 8 The internal soft-start capacitor is charged and generates a linear ramping voltage across the capacitor. This voltage clamps the feedback voltage at the FB pin, causing PWM pulse width increasing slowly to reduce the output surge current. The soft-start cycle stops while the voltage across SS capacitor is higher than the nominal feedback voltage 0.8V. Output Voltage Setting The RT8106/A can regulate an output voltage as low to as 0.8V and maintains it within ±0.8% accuracy. Higher output voltage can be achieved by adding an offset resistor ROFFSET between FB pin and GND. The steady state output voltage will be set as the formula : RFB ⎞ VOUT = VREF × ⎛⎜ 1+ ⎟ ⎝ ROFFSET ⎠ Under Voltage Protection (UVP) The VOS pin voltage is monitored for under voltage protection after soft-start completes. If the VOS voltage drops to below UV threshold (typically 75% x VREF), the UVP is triggered and the RT8106/A turns off High Side and Low Side gate drivers. The RT8106/A will not be released from this latch condition unless VCC POR is recognized. Over Voltage Protection (OVP) The VOS pin is also acted as over voltage detection after POR. If the VOS voltage rises above OVP threshold (typically 125% x VREF), OVP is triggered. The RT8106/ A turns off High Side gatedriver and turns Low Side gate drivers always on. The Low Side gate driver will not be turned off until VOS falls below 0.4V. The RT8106/A will not be released from this latch condition unless VCC POR is recognized. PGOOD The RT8106/A will assert PGOOD signal after the softstart completes and the VOS voltage is within power good range. If VOS voltage runs outside of the range, the RT8106/A de-asserts the PGOOD signal but continues switching and regulating. The PGOOD is an open drain output pin and thus requires an external pull-up resistor. DS8106/A-04 April 2011 RT8106/A Over Current Protection Feedback Compensation While the High Side MOSFET is off and Low Side on, the output current (I OUT) flowing through the Low Side MOSFET results in a negative voltage drop (IOUT x MOSFET RDS(ON)) between the LX pin and GND. The RT8106/A senses IOUT by monitoring the LX pin voltage. The maximum current is set by adjusting an external resistor ROCSET connecting between LGATE and GND. The OCP is triggered if the LX voltage is lower than the LGATE voltage when low side MOSFET conducting. Because there is an internal current source 10uA flowing from the RT8106/A to the ROCSET, the maximum current (IMAX) can be easily derived from below equation : The RT8106/A is a voltage mode controller. The control loop is a single voltage feedback path including a compensator and a modulator as shown in Figure 3. The modulator consists of the PWM comparator and power stage. The PWM comparator compares error amplifier EA output (COMP) with oscillator (OSC) sawtooth wave to provide a pulse-width modulated (PWM) with an amplitude of VIN at the LX node. The PWM wave is smoothed by the output filter LOUT and COUT. The output voltage (VOUT) is sensed and fed to the inverting input of the error amplifier. IMAX × RDS(ON) = ROCSET × 10μ A In case ROCSET is not connected, RT8106/A can detect this condition and set the OC trigger voltage to a preset value (typ. 0.55V). When the OCP is triggered, the RT8106/A will turn off both UGATE and LGATE drivers and latches in the condition unless VCC POR is recognized. A well-designed compensator regulates the output voltage to the reference voltage VREF with fast transient response and good stability. In order to achieve fast transient response and accurate output regulation, an adequate compensator design is necessary. The goal of the compensation network is to provide adequate phase margin (usually greater than 45 degrees) and the highest bandwidth (0dB crossing frequency). It is also recommended to manipulate loop frequency response that its gain crosses over 0dB at a slope of -20dB/dec. V IN Pre-Bias Start Up OSC In order to prevent any potential negative spike on VOUT during start-up, the RT8106/A performs a special UGATE/ LGATE warm-up sequence. The UGATE keeps normal switching but the LGATE will turn on with a short pulse train instead of turning on for a long period. The Figure 2. shows that VOUT rises from its initial value and no negative undershoot will happen. Driver PWM Comparator ΔV OSC L V OUT - Driver + LX C OUT ESR Z FB COMP Z IN EA + REF Z FB C2 C1 EA + LGATE (5V/Div) UGATE (20V/Div) C3 R2 V OUT R3 R1 COMP VOUT (500mV/Div) Z IN FB REF Figure 3. Closed Loop VIN = 12V, VOUT = 1.6V, ILOAD = 0A Time (1ms/Div) Figure 2. Pre-Bias Function DS8106/A-04 April 2011 www.richtek.com 9 RT8106/A 1) Modulator Frequency Equations The modulator transfer function is the small-signal transfer function of VOUT/VCOMP (output voltage over the error amplifier output). This transfer function is dominated by a DC gain, a double pole, and an ESR zero as shown in Figure 3. The DC gain of the modulator is the input voltage (VIN) divided by the peak to peak oscillator voltage VOSC. The output LC filter introduces a double pole, 40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180 degrees. The resonant frequency of the LC filter is expressed as : fLC = Figure 5. shows the DC-DC converter's magnitude Bode Plot. The compensation gain uses external impedance networks ZC and ZF to provide a stable, high bandwidth loop. High crossover frequency is desirable for fast transient response, but it often jeopardize the system stability. In order to cancel one of the LC filter poles, place the zero before the LC filter resonant frequency. In the experience, place the zero at 75% of the LC filter resonant frequency. Crossover frequency should be higher than the ESR zero but less than 1/5 of the switching frequency. The second pole is placed at half the switching frequency. 1 80 80 2π L OUT × C OUT Loop Gain 60 The ESR zero is contributed by the ESR associated with the output capacitance. Note that this requires that the output capacitor should have enough ESR to satisfy stability requirements. The ESR zero of the output capacitor is expressed as follows : fESR = 40 40 Compensation Gain Gain (dB) 20 0 0 -20 1 2π × COUT × ESR Modulator Gain -40-40 -60-60 10Hz 10vdb(vo) 100Hz vdb(comp2)100 vdb(lo) 2) Compensation Frequency Equations The compensation network consists of the error amplifier and the impedance networks ZC and ZF as shown in Figure 4. ZF 10KHz ZC C2 R2 EA + R1 V OUT FB V REF Figure 4. Compensation Loop fZ1 = 1 2π x R2 x C2 fP1 = 1 2π x R2 x C1 x C2 C1 + C2 1.0MHz 1M Figure 5. Bode Plot Component Selection The selection of output inductor is based on the considerations of efficiency, output power and operating frequency. Low inductance value has smaller size, but results in low efficiency, large ripple current and high output ripple voltage. Generally, an inductor that limits the ripple current (ΔIL) between 20% and 50% of output current is appropriate. Figure 6. shows the typical topology of the synchronous step-down converter and its related waveforms. iS1 L IL + VL iS2 S1 V IN S2 IOUT iC + V OR - + rC RL V OUT + + V OC - www.richtek.com 10 100KHz 100k 1) Inductor Selection C1 COMP 1.0KHz 1k 10k Frequency (Hz) Frequency C OUT - DS8106/A-04 April 2011 RT8106/A TS Vg1 2) Output Capacitor Selection The selection of output capacitor depends on the output ripple voltage requirement. Practically, the output ripple voltage is a function of both capacitance value and the equivalent series resistance (ESR) rC. Figure 7. shows the related waveforms of output capacitor. TON TOFF Vg2 VIN - VOUT VL diL VIN-VOUT = L dt iL - VOUT diL VOUT dt = L IOUT TS iL ΔIL IL = IOUT iC 1/2ΔIL 0 ΔIL iS1 VOC ΔVOC iS2 VOR ΔIL x rc 0 Figure 6. The Waveforms of Synchronous Step-Down Converter According to Figure 6. the ripple current of inductor can be calculated as follows : VIN − VOUT V ΔI D = L L ; Δt = ; D = OUT Δt fs VIN L = (VIN − VOUT ) × VOUT VIN × fs × ΔIL (1) t1 t2 Figure 7. The Related Waveforms of Output Capacitor The AC impedance of output capacitor at operating frequency is quite smaller than the load impedance, so the ripple current (ΔIL) of the inductor current flows mainly through the output capacitor. The output ripple voltage is described as : Where : ΔVOUT = ΔVOR + ΔVOC (2) VIN = Maximum input voltage ΔVOUT = ΔIL × rc + 1 CO (3) VOUT = Output Voltage Δt = S1 turn on time ΔIL = Inductor current ripple fS = Switching frequency D = Duty Cycle rC = Equivalent series resistor of output capacitor DS8106/A-04 April 2011 t2 ∫t1 iC dt ΔVOUT = ΔIL × ΔIL × rc + 1 VOUT (1− D)TS2 8 COL (4) where ΔVOR is caused by ESR and ΔVOC by capacitance. For electrolytic capacitor application, typically 90% to 95% of the output voltage ripple is contributed by the ESR of the output capacitor. So Equation (4) can be simplified as: ΔVOUT = ΔIL x rC (5) www.richtek.com 11 RT8106/A Users can connect capacitors in parallel to get calculated ESR. Input Capacitor The selection of input capacitor is mainly based on its maximum ripple current capability. The buck converter draws pulsewise current from the input capacitor during the on time of the S1 as shown in Figure 6. The RMS value of ripple current flowing through the input capacitor is described as : Irms = IOUT D(1 − D) (A) (6) The input capacitor must be cable of handling this ripple current. Sometime, for higher efficiency, the low ESR capacitor is necessary. PCB Layout Considerations Note that the capacitors CIN and COUT each of them represents numerous physical capacitors. Use a dedicated grounding plane and use vias to ground all critical components to this layer. Apply another solid layer as a power plane and cut this plane into smaller islands of common voltage levels. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the LX node, but it is not necessary to oversize this particular island. Since the LX node is subjected to very high dV/dt voltages, the stray capacitance formed between these islands and the surrounding circuitry will tend to couple switching noise. Use the remaining printed circuit layers for small signal routing. The PCB traces between the PWM controller and the gate of MOSFET and also the traces connecting source of MOSFETs should be sized to carry 2A peak currents. IQ1 IL VOUT 5V/12V Q1 IQ2 + + + MOSFETs switch very fast and efficiently. The current transition speed between different derices causes voltage spikes across the interconnecting impedances and parasitic circuit elements. The voltage spikes can degrade efficiency and radiate noise that results in over-voltage stress on devices. Careful component placement layout and printed circuit design can minimize the voltage spikes induced in the converter. For example, during the period of upper MOSFETs turn-off transition, the upper MOSFET was carrying the full load current. During turn-off, current stops flowing in the upper MOSFET and is picked up by the low side MOSFET or schottky diode. Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selections, layout of the critical components, and use shorter and wider PCB traces help in minimizing the magnitude of voltage spikes. The RT8106/A DC-DC converter integrates two sets of critical components just as follows. The switching power components are most critical because they switch large amounts of energy, and as such, they tend to generate equally large amounts of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bypass current. the power switches. Place the output inductor and output capacitors between the MOSFETs and the load. Also locate the PWM controller near by the MOSFETs. A multilayer printed circuit board is recommended. Figure 8 shows the connections of the critical components in the converter. LOAD Q2 GND GND LGATE VCC RT8106/A UGATE FB Figure 8. The Connections of the Critical Components in the Converter For the proper layout of the RT8106/A the power components and the PWM controller should be placed firstly. And than place the input capacitors, especially the high-frequency ceramic decoupling capacitors, close to www.richtek.com 12 DS8106/A-04 April 2011 RT8106/A Figure 9. RT8106/A PCB (Component Side) DS8106/A-04 April 2011 Figure 10. RT8106/A PCB (Back-Side) www.richtek.com 13 RT8106/A Outline Dimension D2 D L E E2 1 SEE DETAIL A 2 e A A1 1 2 1 b DETAIL A Pin #1 ID and Tie Bar Mark Options A3 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 2.300 2.650 0.091 0.104 E 2.950 3.050 0.116 0.120 E2 1.500 1.750 0.059 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 10L DFN 3x3 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 14 DS8106/A-04 April 2011