ICS83058I 8:1, SINGLE-ENDED MULTIPLEXER GENERAL DESCRIPTION FEATURES The ICS83058I is a low skew, 8:1, Single-ended ICS Multiplexer and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS83058I has eight selectable singleended clock inputs and one single-ended clock output. The output has a VDDO pin which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage translation applications. An output enable pin places the output in a high impedance state which may be useful for testing or debug purposes. The device operates up to 250MHz and is packaged in a 16 TSSOP package. • 8:1 single-ended multiplexer • Q nominal output impedance: 7Ω (VDDO = 3.3V) • Maximum output frequency: 250MHz • Propagation delay: 3ns (maximum), VDD = VDDO = 3.3V • Input skew: 225ps (maximum), VDD = VDDO = 3.3V • Part-to-part skew: 475ps (maximum), VDD = VDDO = 3.3V • Additive phase jitter, RMS: 0.19ps (typical), 3.3V/3.3V • Operating supply modes: VDD/VDDO 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V • -40°C to 85°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM PIN ASSIGNMENT Q CLK7 OE CLK6 GND CLK5 SEL2 CLK4 CLK0 CLK1 CLK2 CLK3 Q CLK4 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDDO CLK0 SEL0 CLK1 VDD CLK2 SEL1 CLK3 ICS83058I 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View CLK5 CLK6 CLK7 SEL2 SEL1 SEL0 OE IDT ™ / ICS™ 8:1, SINGLE-ENDED MULTIPLEXER 1 ICS83058AGI REV. C MARCH 10, 2008 ICS83058I 8:1, SINGLE-ENDED MULTIPLEXER TABLE 1. PIN DESCRIPTIONS Number Name Type 1 2, 4, 6, 8, 9, 11, 13, 15 Q CLK7, CLK6, CLK5, CLK4, CLK3, CLK2, CLK1, CLK0 Output 3 OE Input 5 GND Power 7, 10, 14 SEL2, SEL1, SEL0 Input 12 VDD Power 16 VDDO Power Input Description Single-ended clock output. LVCMOS/LVTTL interface levels. Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. Output enable. When LOW, outputs are in HIGH impedance state. When HIGH, outputs are active. LVCMOS / LVTTL interface levels. Power supply ground. Clock select input. See Control Input Function Table. Pulldown LVCMOS / LVTTL interface levels. Core and input supply pin. Pullup Output supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Test Conditions Minimum Typical Maximum Units Symbol Parameter C IN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ CPD Power Dissipation Capacitance (per output) ROUT Output Impedance VDDO = 3.465V 18 pF VDDO = 2.625V 20 pF VDDO = 1.89V 30 pF VDDO = 3.465V 7 Ω VDDO = 2.625V 7 Ω VDDO = 1.89V 10 Ω TABLE 3. CONTROL INPUT FUNCTION TABLE SEL2 0 Control Inputs SEL1 0 SEL0 0 0 0 1 0 1 0 CLK2 0 1 1 CLK3 1 0 0 CLK4 1 0 1 CLK5 1 1 0 CLK6 1 1 1 CLK7 IDT ™ / ICS™ 8:1, SINGLE-ENDED MULTIPLEXER Input Selected to Q CLK0 CLK1 2 ICS83058AGI REV. C MARCH 10, 2008 ICS83058I 8:1, SINGLE-ENDED MULTIPLEXER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 89°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VDD Power Supply Voltage Test Conditions 3.135 3.3 3.465 V 3.135 3.3 VDDO Output Supply Voltage 3.465 V IDD Power Supply Current 40 mA IDDO Output Supply Current 5 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VDD Power Supply Voltage Test Conditions 3.135 3.3 3.465 V 2.375 2.5 VDDO Output Supply Voltage 2.625 V IDD Power Supply Current 40 mA IDDO Output Supply Current 5 mA TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 1.71 1.8 1.89 V IDD Power Supply Current 40 mA IDDO Output Supply Current 5 mA TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Power Supply Voltage 2.375 2.5 2.625 V 2.375 2.5 VDDO Output Supply Voltage 2.625 V IDD Power Supply Current 35 mA IDDO Output Supply Current 5 mA TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VDD VDDO Power Supply Voltage 2.375 2.5 2.625 V Output Supply Voltage 1.71 1.8 1.89 V IDD Power Supply Current 35 mA IDDO Output Supply Current 5 mA IDT ™ / ICS™ 8:1, SINGLE-ENDED MULTIPLEXER Test Conditions 3 ICS83058AGI REV. C MARCH 10, 2008 ICS83058I 8:1, SINGLE-ENDED MULTIPLEXER TABLE 4F. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C Symbol VIH VIL IIH IIL VOH VOL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK0:CLK5, SEL0:SEL2 OE CLK0:CLK5, SEL0:SEL2 OE Output HighVoltage Output Low Voltage Test Conditions Minimum Maximum Units VDD = 3.3V ± 5% 2 Typical VDD + 0.3 V VDD = 2.5V ± 5% 1.7 VDD + 0.3 V VDD = 3.3V ± 5% -0.3 0.8 V VDD = 2.5V ± 5% -0.3 0.7 V VDD = 3.3V or 2.5V ± 5% 150 µA VDD = 3.3V or 2.5V ± 5% 5 µA VDD = 3.3V or 2.5V ± 5% -5 µA VDD = 3.3V or 2.5V ± 5% -150 µA VDDO = 3.3V ± 5%; NOTE 1 2.6 V VDDO = 2.5V ± 5%; NOTE 1 1.8 V VDDO = 1.8V ± 5%; NOTE 1 VDD - 0.3 V VDDO = 3.3V ± 5%; NOTE 1 0.5 V VDDO = 2.5V ± 5%; NOTE 1 0.45 V VDDO = 1.8V ± 5%; NOTE 1 0.35 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams. TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units 250 MHz 3.0 ns fMAX Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 1.8 2.4 tpHL Propagation Delay, High to Low; NOTE 1 2.5 2.7 2.9 ns t sk(i) 55 225 ps t sk(pp) Input Skew; NOTE 2 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 3 Par t-to-Par t Skew; NOTE 2, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle tjit 155.52MHz, (12kHz to 20MHz) 20% to 80% 0.19 475 ps 50 500 ps 45 55 % MUXISOL MUX Isolation @ 100MHz 45 NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. IDT ™ / ICS™ 8:1, SINGLE-ENDED MULTIPLEXER 4 ps dB ICS83058AGI REV. C MARCH 10, 2008 ICS83058I 8:1, SINGLE-ENDED MULTIPLEXER TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units 250 MHz 2.5 3.1 ns 2.8 3.0 ns 150 ps fMAX Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 2.0 tpHL Propagation Delay, High to Low; NOTE 1 2.6 t sk(i) 45 t sk(pp) Input Skew; NOTE 2 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 3 Par t-to-Par t Skew; NOTE 2, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle tjit 155.52MHz, (12kHz to 20MHz) 20% to 80% 0.14 ps 400 ps 50 500 ps 45 55 % MUXISOL MUX Isolation @ 100MHz 45 NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. dB TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V ± 5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units 250 MHz 2.9 3.8 ns 3.3 3.8 ns 150 ps fMAX Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 2.3 tpHL Propagation Delay, High to Low; NOTE 1 2.8 t sk(i) 50 t sk(pp) Input Skew; NOTE 2 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 3 Par t-to-Par t Skew; NOTE 2, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle tjit 155.52MHz, (12kHz to 20MHz) 20% to 80% 0.16 475 ps 100 700 ps 45 55 % MUXISOL MUX Isolation @ 100MHz 45 NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. IDT ™ / ICS™ 8:1, SINGLE-ENDED MULTIPLEXER 5 ps dB ICS83058AGI REV. C MARCH 10, 2008 ICS83058I 8:1, SINGLE-ENDED MULTIPLEXER TABLE 5D. AC CHARACTERISTICS, VDD = VDDO = 2.5V ± 5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units 250 MHz 3.5 ns fMAX Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 1.9 2.7 tpHL Propagation Delay, High to Low; NOTE 1 2.5 2.9 3.4 ns t sk(i) 60 175 ps t sk(pp) Input Skew; NOTE 2 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 3 Par t-to-Par t Skew; NOTE 2, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle tjit 155.52MHz, (12kHz to 20MHz) 20% to 80% 0.21 ps 300 ps 100 500 ps 40 60 % MUXISOL MUX Isolation @ 100MHz 45 NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. dB TABLE 5E. AC CHARACTERISTICS, VDD = 2.5V ± 5%, VDDO = 1.8V ± -5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units 250 MHz fMAX Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 2.2 2.9 4.0 ns tpHL Propagation Delay, High to Low; NOTE 1 2.7 3.3 4.0 ns t sk(i) 50 150 ps t sk(pp) Input Skew; NOTE 2 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 3 Par t-to-Par t Skew; NOTE 2, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle tjit 155.52MHz, (12kHz to 20MHz) 20% to 80% 0.17 325 ps 100 700 ps 40 60 MUXISOL MUX Isolation @ 100MHz 45 NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. IDT ™ / ICS™ 8:1, SINGLE-ENDED MULTIPLEXER 6 ps % dB ICS83058AGI REV. C MARCH 10, 2008 ICS83058I 8:1, SINGLE-ENDED MULTIPLEXER ADDITIVE PHASE JITTER band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz Additive Phase Jitter @ 155.52MHz SSB PHASE NOISE dBc/HZ (12kHz to 20MHz) = 0.19ps typical OFFSET FROM CARRIER FREQUENCY (HZ) the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. As with most timing specifications, phase noise measurements has issues relatings to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of IDT ™ / ICS™ 8:1, SINGLE-ENDED MULTIPLEXER 7 ICS83058AGI REV. C MARCH 10, 2008 ICS83058I 8:1, SINGLE-ENDED MULTIPLEXER PARAMETER MEASUREMENT INFORMATION 1.65V±5% 1.25V±5% SCOPE VDD, VDDO SCOPE VDD, VDDO Qx Qx LVCMOS LVCMOS GND GND -1.65V±5% -1.25V±5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 2.05V±5% 2.4±5% 0.9V±5% 1.25V±5% SCOPE VDD VDDO SCOPE VDD VDDO Qx GND Qx GND LVCMOS LVCMOS -1.25V±5% -0.9V±5% 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 1.6V±5% 0.9V±5% Part 1 Qx SCOPE VDD VDDO Qx Part 2 GND Qy LVCMOS V DDO 2 V DDO 2 tsk(pp) -0.9V±5% 2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT IDT ™ / ICS™ 8:1, SINGLE-ENDED MULTIPLEXER PART-TO-PART SKEW 8 ICS83058AGI REV. C MARCH 10, 2008 ICS83058I 8:1, SINGLE-ENDED MULTIPLEXER VDD VDD CLK0:CLK7 VDDO Q 2 tpLH 80% 80% 2 2 VDDO Clock Outputs 2 tpHL PROPAGATION DELAY 20% 20% tR tF OUTPUT RISE/FALL TIME CLKx V DDO 2 Q Q t PW t tPD1 odc = PERIOD t PW x 100% t PERIOD CLKy Q tPD2 tsk(i) = ⏐tPD2 – tPD1⏐ INPUT SKEW IDT ™ / ICS™ 8:1, SINGLE-ENDED MULTIPLEXER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 9 ICS83058AGI REV. C MARCH 10, 2008 ICS83058I 8:1, SINGLE-ENDED MULTIPLEXER APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS: CLK INPUTS For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT ™ / ICS™ 8:1, SINGLE-ENDED MULTIPLEXER 10 ICS83058AGI REV. C MARCH 10, 2008 ICS83058I 8:1, SINGLE-ENDED MULTIPLEXER RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 89.0°C/W 200 500 118.2°C/W 81.8°C/W 106.8°C/W 78.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS83058I is: 874 PACKAGE OUTLINE AND PACKAGE DIMENSIONS PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N A Maximum 16 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ 8:1, SINGLE-ENDED MULTIPLEXER 11 ICS83058AGI REV. C MARCH 10, 2008 ICS83058I 8:1, SINGLE-ENDED MULTIPLEXER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS83058AGI 83058AGI 16 Lead TSSOP tube -40°C to 85°C ICS83058AGIT 83058AGI 16 Lead TSSOP 2500 tape & reel -40°C to 85°C ICS83058AGILF 83058AIL 16 Lead "Lead-Free" TSSOP tube -40°C to 85°C ICS83058AGILFT 83058AIL 16 Lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ 8:1, SINGLE-ENDED MULTIPLEXER 12 ICS83058AGI REV. C MARCH 10, 2008 ICS83058I 8:1, SINGLE-ENDED MULTIPLEXER REVISION HISTORY SHEET Rev Table T5A - T5E Page 1 4-6 7 4-6 B T5A - T5E T8 12 C Description of Change Features Section - added Additive Phase Jitter bullet. AC Characteristics Tables - added tjit row and spec. Added Additive Phase Jitter section. AC Characteristics Tables - changed minimum and typical propagation delay specs. Ordering Informaiton Table - added lead-free marking. IDT ™ / ICS™ 8:1, SINGLE-ENDED MULTIPLEXER 13 Date 01/04/07 03/10/08 ICS83058AGI REV. C MARCH 10, 2008 ICS83058I 8:1, SINGLE-ENDED MULTIPLEXER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Japan Asia Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) NIPPON IDT KK Sanbancho Tokyu Bld. 7F, 8-1 Sanbancho Chiyoda-ku, Tokyo 102-0075 +81 3 3221 9822 +81 3 3221 9824 (fax) Integrated Device Technology IDT (S) Pte. Ltd. 1 Kallang Sector, #07-01/06 Kolam Ayer Industrial Park Singapore 349276 +65 6 744 3356 +65 6 744 1764 (fax) IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 +44 (0) 1372 378851 (fax) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA