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The following document contains information on Cypress products.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04–21367–2E
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F72UL
■ DESCRIPTION
The Fujitsu Semiconductor MB15F72UL is a serial input Phase Locked Loop (PLL) frequency synthesizer
with a 1300 MHz and a 350 MHz prescalers. A 64/65 or a 128/129 for the 1300 MHz prescaler, and a 8/9
or a 16/17 for the 350 MHz prescaler can be selected for the prescaler that enables pulse swallow operation.
The BiCMOS process is used, as a result a supply current is typically 2.5 mA at 2.7 V. The supply voltage
range is from 2.4 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and
6 mA selectable by serial data. The data format is the same as the previous one MB15F02SL, MB12F72SP.
Fast locking is achieved for adopting the new circuit.
■ FEATURES
• High frequency operation : RF synthesizer : 1300 MHz Max
: IF synthesizer : 350 MHz Max
• Low power supply voltage : VCC = 2.4 to 3.6 V
• Ultra low power supply current : ICC = 2.5 mA Typ
(VCC = Vp = 2.7 V, SWIF = SWRF = 0, Ta = +25 °C, in IF, RF locking state)
• Direct power saving function : Power supply current in power saving mode
Typ 0.1 μA (VCC = Vp = 2.7 V, Ta = +25 °C)
Max 10 μA (VCC = Vp = 2.7 V)
• Software selectable charge pump current : 1.5 mA/6.0 mA Typ
• Dual modulus prescaler : 1300 MHz prescaler (64/65 or 128/129 ) /350 MHz prescaler (8/9 or 16/17)
• 23 bit shift resister
• Serial input 14-bit programmable reference divider : R = 3 to 16,383
• Serial input programmable divider consisting of :
- Binary 7-bit swallow counter : 0 to 127
- Binary 11-bit programmable counter : 3 to 2,047
• On−chip phase control for phase comparator
• On−chip phase comparator for fast lock and low noise
• Built-in digital locking detector circuit to detect PLL locking and unlocking.
• Operating temperature : Ta = −40 °C to +85 °C
• Serial data format compatible with MB15F02SL
Copyright©2001-2012 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2012.8
MB15F72UL
■ PIN ASSIGNMENTS
Clock
GND
19
Data
finIF
3
18
LE
XfinIF
4
17
finRF
GNDIF
5
16
VCCIF
6
PSIF
VpIF
20
19
18
17
16
2
14 XfinRF
15
GNDRF
GNDIF
3
13 GNDRF
7
14
VCCRF
VCCIF
4
12 VCCRF
8
13
PSRF
DoIF
9
12
VpRF
PSIF
5
11 PSRF
LD/fout
10
11
DoRF
6
7
8
9
10
VpRF
XfinIF
DoRF
XfinRF
LD/fout
15 finRF
DoIF
1
VpIF
finIF
(FPT-20P-M06)
2
LE
20
2
Data
1
Clock
OSCIN
OSCIN
(QFN-20)
TOP VIEW
GND
(TSSOP-20)
TOP VIEW
(LCC-20P-M63)
DS04–21367–2E
MB15F72UL
■ PIN DESCRIPTION
Pin no.
TSSOP QFN
Pin name I/O
I
Descriptions
The programmable reference divider input. TCXO should be connected with
an AC coupling capacitor.
1
19
OSCIN
2
20
GND
3
1
finIF
I
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be via AC coupling.
4
2
XfinIF
I
Prescaler complimentary input pin for the IF-PLL section.
This pin should be grounded via a capacitor.
5
3
GNDIF
6
4
VCCIF
⎯
Power supply voltage input pin for the IF-PLL section (except for the charge
pump circuit) , the OSC input buffer and the shift register circuit.
7
5
PSIF
I
Power saving mode control for the IF-PLL section. This pin must be set at “L”
when the power supply is started up. (Open is prohibited.)
PSIF = “H” ; Normal mode / PSIF = “L” ; Power saving mode
8
6
VpIF
⎯ Power supply voltage input pin for the IF-PLL charge pump.
9
7
DOIF
O
Charge pump output pin for the IF-PLL section.
10
8
LD/fout
O
Lock detect signal output (LD) /phase comparator monitoring
output (fout) pins.The output signal is selected by LDS bit in the serial data.
LDS bit = “H” ; outputs fout signal / LDS bit = “L” ; outputs LD signal
11
9
DORF
O
Charge pump output pin for the RF-PLL section.
12
10
VpRF
⎯ Power supply voltage input pin for the RF-PLL charge pump.
13
11
PSRF
I
Power saving mode control pin for the RF-PLL section. This pin must be set
at “L” when the power supply is started up. (Open is prohibited.)
PSRF = “H” ; Normal mode / PSRF = “L” ; Power saving mode
14
12
VCCRF
⎯
Power supply voltage input pin for the RF-PLL section (except for the charge
pump circuit)
15
13
GNDRF
16
14
XfinRF
I
Prescaler complimentary input pin for the RF-PLL section.
This pin should be grounded via a capacitor.
17
15
finRF
I
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.
18
16
LE
I
Load enable signal input pin (with the schmitt trigger circuit)
When LE is set “H”, data in the shift register is transferred to the
corresponding latch according to the control bit in the serial data.
⎯ Ground for OSC input buffer and the shift register circuit.
⎯ Ground for the IF-PLL section.
⎯ Ground for the RF-PLL section
19
17
Data
I
Serial data input pin (with the schmitt trigger circuit)
Data is transferred to the corresponding latch (IF-ref. counter, IF-prog.
counter, RF-ref. counter, RF-prog. counter) according to the control bit in
the serial data.
20
18
Clock
I
Clock input pin for the 23-bit shift register (with the schmitt trigger circuit)
One bit of data is shifted into the shift register on a rising edge of the clock.
DS04–21367–2E
3
MB15F72UL
■ BLOCK DIAGRAM
VpIF
8 (6)
VCCIF GNDIF
(4) 6
5 (3)
finIF 3
(1)
XfinIF 4
(2)
Intermittent
mode control
(IF-PLL)
FCIF
SWIF
3 bit latch
LDS
PSIF 7
(5)
7 bit latch
11 bit latch
fpIF
Binary 11-bit
Binary 7-bit
swallow counter programmable
counter (IF-PLL)
(IF-PLL)
Prescaler
(IF-PLL)
(8/9, 16/17
Charge
pump Current
(IF-PLL) Switch
Phase
comp.
(IF-PLL)
9 DoIF
(7)
Lock Det.
(IF-PLL)
2 bit latch
T1
T2
14 bit latch
1 bit latch
Binary 14-bit programmable ref.
counter(IF-PLL)
C/P setting
counter
LDIF
frIF
Fast
lock
Tuning
OSCIN 1
(19)
T1
OR
T2
2 bit latch
LE 18
(16)
(17)
Data 19
Clock 20
(18)
14 bit latch
1 bit latch
LD
frIF
frRF
fpIF
fpRF
10 LD/
(8) fout
Intermittent
mode control
(RF-PLL)
Schmitt
circuit
Schmitt
circuit
Schmitt
circuit
FCRF
Lock Det.
(RF-PLL)
Binary 11-bit
Binary 7-bit
swallow counter programmable
counter (RF-PLL)
(RF-PLL)
3 bit latch
7 bit latch
Phase
comp.
(RF-PLL)
Fast lock
Tuning
PSRF 13
(11)
C/P setting
counter
LDRF
SWRF
XfinRF 16
(14)
Binary 14-bit programmable ref.
counter (RF-PLL))
Prescaler
(RF-PLL)
(64/65, 128/129)
LDS
(15)
finRF 17
Selector
AND
frRF
Charge
Current
pump
Switch
(RF-PLL)
11 DoRF
(9)
fpRF
11 bit latch
Latch selector
C C
N N
1 2
23-bit shift register
2 (20)
GND
(12) 14
15 (13)
VCCRF GNDRF
12 (10)
VpRF
O : TSSOP
( ) : QFN
4
DS04–21367–2E
MB15F72UL
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Unit
Min
Max
VCC
−0.5
+4.0
V
Vp
VCC
4.0
V
VI
−0.5
VCC + 0.5
V
LD/fout
VO
GND
VCC
V
DoIF, DoRF
VDO
GND
Vp
V
Tstg
−55
+125
°C
Power supply voltage
Input voltage
Output voltage
Rating
Storage temperature
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Remarks
3.6
V
VCCRF = VCCIF
2.7
3.6
V
GND
⎯
VCC
V
−40
⎯
+85
°C
Min
Typ
Max
VCC
2.4
2.7
Vp
VCC
Input voltage
VI
Operating temperature
Ta
Power supply voltage
Notes : • VCCRF, VpRF, VCCIF and VpIF must supply equal voltage.
Even if either RF-PLL or IF-PLL is not used, power must be supplied to VCCRF, VpRF, VCCIF and VpIF
to keep them equal.
It is recommended that the non-use PLL is controlled by power saving function.
• Although this device contains an anti-static element to prevent electrostatic breakdown and the
circuitry has been improved in electrostatic protection, observe the following precautions when
handling the device.
• When storing and transporting the device, put it in a conductive case.
• Before handling the device, confirm the (jigs and) tools to be used have been uncharged
(grounded) as well as yourself. Use a conductive sheet on working bench.
• Before fitting the device into or removing it from the socket, turn the power supply off.
• When handling (such as transporting) the device mounted board, protect the leads with a
conductive sheet.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS04–21367–2E
5
MB15F72UL
■ ELECTRICAL CHARACTERISTICS
(VCC = 2.4 V to 3.6 V, Ta = −40 °C to +85 °C)
Symbol
Parameter
“L” level input voltage
“H” level input voltage
“L” level input voltage
“H” level input current
“L” level input current
“H” level input current
“L” level input current
Typ
Max
Unit
0.6
1.0
1.7
mA
ICCRF *1
finRF = 910 MHz
VCCRF = VpRF = 2.7 V
1.0
1.5
2.5
mA
IPSIF
PSIF = PSRF = “L”
⎯
0.1 *2
10
μA
IPSRF
PSIF = PSRF = “L”
⎯
0.1 *2
10
μA
finIF
IF PLL
50
⎯
350
MHz
fin *
finRF
RF PLL
100
⎯
1300
MHz
OSCIN
fOSC
3
⎯
40
MHz
finIF*3
“H” level input voltage
Min
finIF = 270 MHz
VCCIF = VpIF = 2.7 V
Power saving current
Input sensitivity
Value
ICCIF *1
Power supply current
Operating frequency
Condition
RF 3
⎯
finIF
PfinIF IF PLL, 50 Ω system
−15
⎯
+2
dBm
finRF
PfinRF RF PLL, 50 Ω system
−15
⎯
+2
dBm
OSCIN
VOSC
0.5
⎯
VCC
VP − P
Data,
LE,
Clock
VIH
Schmitt trigger input
0.7 VCC + 0.4
⎯
⎯
V
VIL
Schmitt trigger input
⎯
⎯
0.3 VCC − 0.4
V
PSIF,
PSRF
VIH
⎯
0.7 VCC
⎯
⎯
V
VIL
⎯
⎯
⎯
0.3 VCC
V
IIH*4
⎯
−1.0
⎯
+1.0
μA
IIL*4
⎯
−1.0
⎯
+1.0
μA
IIH
⎯
0
⎯
+100
μA
IIL*4
⎯
−100
⎯
0
μA
Data,
LE,
Clock,
PSIF,
PSRF
OSCIN
⎯
VOH
VCC = Vp = 2.7 V,
IOH = −1 mA
VCC − 0.4
⎯
⎯
V
“L” level output voltage
VOL
VCC = Vp = 2.7 V,
IOL = 1 mA
⎯
⎯
0.4
V
“H” level output voltage
VDOH
VCC = Vp = 2.7 V,
IDOH = −0.5 mA
Vp − 0.4
⎯
⎯
V
VDOL
VCC = Vp = 2.7 V,
IDOL = 0.5 mA
⎯
⎯
0.4
V
IOFF
VCC = Vp = 2.7 V
VOFF = 0.5 V to Vp −
0.5 V
⎯
⎯
2.5
nA
IOH*4
VCC = Vp = 2.7 V
⎯
⎯
−1.0
mA
IOL
VCC = Vp = 2.7 V
1.0
⎯
⎯
mA
“H” level output voltage
LD/fout
“L” level output voltage
High impedance
cutoff current
“H” level output current
“L” level output current
DoIF,
DoRF
DoIF,
DoRF
LD/fout
(Continued)
6
DS04–21367–2E
MB15F72UL
(Continued)
(VCC = 2.4 V to 3.6 V, Ta = −40 °C to +85 °C)
Parameter
Symbol
“H” level output
current
DoIF *8,
DoRF
IDOH *4
“L” level output
current
DoIF *8,
DoRF
IDOL
IDOL/IDOH IDOMT *5
Charge pump
current rate
Value
Condition
Unit
Min
Typ
Max
VCC = Vp = 2.7 V, CS bit = “H”
VDOH = Vp / 2,
CS bit = “L”
Ta = +25 °C
−8.2
−6.0
−4.1
mA
−2.2
−1.5
−0.8
mA
VCC = Vp = 2.7 V, CS bit = “H”
VDOL = Vp / 2,
CS bit = “L”
Ta = +25 °C
4.1
6.0
8.2
mA
0.8
1.5
2.2
mA
VDO = Vp / 2
⎯
3
⎯
%
vs. VDO
I
0.5 V ≤ VDO ≤ Vp − 0.5 V
⎯
10
⎯
%
vs.Ta
IDOTA *7
−40 °C ≤ Ta ≤ +85 °C,
VDO = Vp / 2
⎯
5
⎯
%
DOVD *6
*1 : Conditions ; fosc = 12.8 MHz, Ta = +25 °C, SW = “L” in locking state.
*2 : VCCIF = VpIF = VCCRF = VpRF = 2.7 V, fosc = 12.8 MHz, Ta = +25 °C, in power saving mode
PSIF = PSRF = GND, VIH = VCC VIL = GND (at CLK, Data, LE)
*3 : AC coupling. 1000 pF capacitor is connected under the condition of minimum operating frequency.
*4 : The symbol “–” (minus) means the direction of current flow.
*5 : VCC = Vp = 2.7 V, Ta = +25 °C (||I3| − |I4||) / [ (|I3| + |I4|) / 2] × 100 (%)
*6 : VCC = Vp = 2.7 V, Ta = +25°C [ (||I2| − |I1||) / 2] / [ (|I1| + |I2|) / 2] × 100 (%) (Applied to both lDOL and lDOH)
*7 : VCC = Vp = 2.7 V, [||IDO (+85°C) | − |IDO (–40°C) || / 2] / [|IDO (+85°C) | + |IDO (–40°C) | / 2] × 100 (%) (Applied to both
IDOL and IDOH)
*8 : When Charge pump current is measured, set LDS = “L” , T1 = “L” and T2 = “H”.
I1
I3
I2
IDOL
I4
IDOH
I1
0.5
Vp/2
Vp − 0.5
Vp
Charge pump output voltage (V)
DS04–21367–2E
7
MB15F72UL
■ FUNCTIONAL DESCRIPTION
1. Pulse swallow function :
fVCO = [ (P × N) + A] × fOSC ÷ R
fVCO : Output frequency of external voltage controlled oscillator (VCO)
P : Preset divide ratio of dual modulus prescaler (8 or 16 for IF-PLL, 64 or 128 for RF-PLL)
N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127, A < N)
fOSC : Reference oscillation frequency (OSCIN input frequency)
R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
2. Serial Data Input
The serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/
RF-PLL sections, and programmable reference dividers of IF/RF-PLL sections are controlled individually.
The serial data of binary data is entered through Data pin.
On a rising edge of Clock, one bit of the serial data is transferred into the shift register. On a rising edge of
load enable signal, the data stored in the shift register is transferred to one of latches depending upon the
control bit data setting.
The programmable The programmable
The programmable
The programmable
reference counter reference counter counter and the swallow counter and the swallow
for the IF-PLL
for the RF-PLL
counter for the IF-PLL
counter for the RF-PLL
CN1
0
1
0
1
CN2
0
0
1
1
(1) Shift Register Configuration
• Programmable Reference Counter
(LSB)
1
2
3
Data Flow
4
5
6
7
8
9 10 11 12 13 14
(MSB)
15
16
17
18
19 20 21 22 23
CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS
CS
R1 to R14
T1, T2
CN1, CN2
X
X
X
X
X
: Charge pump current select bit
: Divide ratio setting bits for the programmable reference counter (3 to 16,383)
: LD/fout output setting bit.
: Control bit
: Dummy bits (Set “0” or “1”)
Note : Data input with MSB first.
8
DS04–21367–2E
MB15F72UL
• Programmable Counter
(LSB)
1
2
Data Flow
3
CN1 CN2 LDS
4
5
6
SWIF FCIF/
/RF
A1 to A7
N1 to N11
LDS
SWIF/RF
FCIF/RF
CN1, CN2
7
8
(MSB)
9 10 11 12 13 14 15 16 17 18 19 20 21 22
23
A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11
RF
: Divide ratio setting bits for the swallow counter (0 to 127)
: Divide ratio setting bits for the programmable counter (3 to 2,047)
: LD/fout signal select bit
: Divide ratio setting bit for the prescaler (IF : SWIF, RF : SWRF)
: Phase control bit for the phase detector (IF : FCIF, RF : FCRF)
: Control bit
Note : Data input with MSB first.
(2) Data setting
• Binary 14-bit Programmable Reference Counter Data Setting (R1 to R14)
Divide ratio
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
•
•
•
16383
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
1
•
•
•
1
0
•
•
•
1
0
•
•
•
1
Note : Divide ratio less than 3 is prohibited.
• Binary 11-bit Programmable Counter Data Setting (N1 to N11)
Divide ratio
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
3
0
0
0
0
0
0
0
0
0
1
1
4
•
•
•
2047
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
1
•
•
•
1
0
•
•
•
1
0
•
•
•
1
Note : Divide ratio less than 3 is prohibited.
• Binary 7-bit Swallow Counter Data Setting (A1 to A7)
Divide ratio
A7
A6
A5
A4
A3
A2
A1
0
0
0
0
0
0
0
0
1
•
•
•
127
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
1
•
•
•
1
DS04–21367–2E
9
MB15F72UL
• Prescaler Data Setting (SW)
Divide ratio
SW = “1”
SW = “0”
Prescaler divide ratio IF-PLL
8/9
16/17
Prescaler divide ratio RF-PLL
64/65
128/129
• Charge Pump Current Setting (CS)
Current value
CS
±6.0 mA
1
±1.5 mA
0
• LD/fout output Selectable Bit Setting
LD/fout pin state
LDS
T1
T2
0
0
0
0
1
0
0
1
1
frIF
1
0
0
frRF
1
1
0
fpIF
1
0
1
fpRF
1
1
1
LD output
fout
outputs
• Phase Comparator Phase Switching Data Setting (FCIF, FCRF)
Phase comparator input
FCIF = “1”
FCRF = “1”
FCIF = “0”
FCRF = “0”
DoIF
DoRF
DoIF
DoRF
fr > fp
H
L
fr < fp
L
H
fr = fp
Z
Z
Z : High-impedance
Depending upon the VCO and LPF polarity, FC bit should be set.
High
(1)
(1) VCO polarity FC = “1”
(2) VCO polarity FC = “0”
VCO Output
Frequency
(2)
LPF Output voltage
Max.
Note : Give attention to the polarity for using active type LPF.
10
DS04–21367–2E
MB15F72UL
3. Power Saving Mode (Intermittent Mode Control Circuit)
Status
PSIF/PSRF pins
Normal mode
H
Power saving mode
L
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pins low, the device enters into the power saving mode, reducing the current consumption.
See the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pins high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal
operation. When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference
frequency (fr) which can cause a major change in the comparator output, resulting in a VCO frequency jump
and an increase in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the
error signal from the phase detector when it returns to normal operation.
Notes: • When power (VCC) is first applied, the device must be in standby mode, PSIF = PSRF = Low, for at least
1 μs.
• PS pins must be set at “L” at Power-ON.
OFF
ON
VCC
tV
1 s
Clock
Data
LE
tPS > 100 ns
PSIF
PSRF
(1)
(2)
(3)
(1) PSIF = PSRF = “L” (power saving mode) at Power-ON
(2) Set serial data at least 1 μs after the power supply becomes stable (VCC ≥ 2.2 V) .
(3) Release power saving mode (PSIF, PSRF : “L” → “H”) at least 100 ns after setting serial
data.
DS04–21367–2E
11
MB15F72UL
4. Serial Data Input Timing
Frequency multiplier setting is performed through a serial interface using the Data pin, Clock pin, and LE pin.
Setting data is read into the shift register at the rise of the clock signal, and transferred to a latch at the rise
of the LE signal. The following diagram shows the data input timing.
1st data
2nd data
Control bit
Data
MSB
Invalid data
LSB
Clock
t1
t2
t3
t6
t7
LE
t4
t5
Parameter
Min
Typ
Max
Unit
Parameter
Min
Typ
Max
Unit
t1
20
⎯
⎯
ns
t5
100
⎯
⎯
ns
t2
20
⎯
⎯
ns
t6
20
⎯
⎯
ns
t3
30
⎯
⎯
ns
t7
100
⎯
⎯
ns
t4
30
⎯
⎯
ns
Note : LE should be “L” when the data is transferred into the shift register.
12
DS04–21367–2E
MB15F72UL
■ PHASE COMPARATOR OUTPUT WAVEFORM
frIF/frRF
fpIF/fpRF
tWU
tWL
LD
(FC bit = "1")
H
DoIF/DoRF
Z
L
(FC bit = "0")
H
DoIF/DoRF
Z
L
• LD Output Logic
IF-PLL section
RF-PLL section
LD output
Locking state/Power saving state
Locking state/Power saving state
H
Locking state/Power saving state
Unlocking state
L
Unlocking state
Locking state/Power saving state
L
Unlocking state
Unlocking state
L
Notes : • Phase error detection range = −2π to +2π
• Pulses on DoIF/DoRF signals are output to prevent dead zone during locking state.
• LD output becomes low when phase error is tWU or more.
• LD output becomes high when phase error is tWL or less and continues to be so for three cycles
or more.
• tWU and tWL depend on OSCIN input frequency as follows.
tWU ≥ 2/fosc : e.g. tWU ≥ 156.3 ns when fosc = 12.8 MHz
tWU ≤ 4/fosc : e.g. tWL ≤ 312.5 ns when fosc = 12.8 MHz
DS04–21367–2E
13
MB15F72UL
■ TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
fout
Oscilloscope
1000 pF
VCCIF
VpIF
0.1 μF
1000 pF
50 Ω
0.1 μF
S.G.
1000 pF
LD/
fout
DoIF
VpIF
PSIF
VCCIF
GNDIF
XfinIF
finIF
GND
OSCIN
10
9
8
7
6
5
4
3
2
1
11
12
13
14
15
16
17
18
19
20
DoRF
VpRF
PSRF
VCCRF
GNDRF
XfinRF
finRF
LE
Data
Clock
50 Ω
S.G.
1000 pF
Controller
(divide ratio setting)
1000 pF
VCCRF
VpRF
0.1 μF
0.1 μF
50 Ω
S.G.
Note : Terminal number shows that of TSSOP-20.
14
DS04–21367–2E
MB15F72UL
■ TYPICAL CHARACTERISTICS
1. fin input sensitivity
RF-PLL input sensitivity vs. Input frequency
10
PfinRF (dBm)
0
SPEC
−10
−20
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
SPEC
−30
−40
−50
0
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
2400
finRF (MHz)
IF-PLL input sensitivity vs. Input frequency
10
PfinIF (dBm)
0
SPEC
−10
−20
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
SPEC
−30
−40
−50
0
100
200
300
400
500
600
700
800
finIF (MHz)
DS04–21367–2E
15
MB15F72UL
2. OSCIN input sensitivity
Input sensitivity vs. Input frequency
10
Input sensitivity VOSC (dBm)
SPEC
0
−10
−20
−30
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
SPEC
−40
−50
−60
0
50
100
150
200
250
300
Input frequency fOSC (MHz)
16
DS04–21367–2E
MB15F72UL
3. RF-PLL Do output current
• 1.5 mA mode
IDO - VDO
Charge pump output current IDO (mA)
10.0
VCC = Vp = 2.7 V
0
−10.0
0.0
1.0
2.0
3.0
Charge pump output voltage VDO (V)
• 6.0 mA mode
IDO - VDO
Charge pump output current IDO (mA)
10.0
VCC = Vp = 2.7 V
0
−10.0
0.0
1.0
2.0
3.0
Charge pump output voltage VDO (V)
DS04–21367–2E
17
MB15F72UL
4. IF-PLL Do output current
• 1.5 mA mode
IDO − VDO
Charge pump output current IDO (mA)
10.0
VCC = VP = 2.7 V
0
−10.0
0.0
2.0
1.0
3.0
Charge pump output voltage VDO (V)
• 6.0 mA mode
IDO − VDO
Charge pump output current IDO (mA)
10.0
VCC = Vp = 2.7 V
0
−10.0
0.0
1.0
2.0
3.0
Charge pump output voltage VDO (V)
18
DS04–21367–2E
MB15F72UL
5. fin input impedance
finRF input impedance
4 : 8.252 Ω
−58.291 Ω
2.1 pF
1 300.140 000 MHz
1 : 332.28 Ω
−811.72 Ω
100 MHz
2 : 21.805 Ω
−182.83 Ω
500 MHz
3 : 9.6133 Ω
−83.98 Ω
1 GHz
1
2
4
3
START 100.000 000 MHz
STOP 1 500.000 000 MHz
finIF input impedance
4 : 21.344 Ω
−181.55 Ω
1.7532 pF
500.000 000 MHz
1 : 939.62 Ω
−1.135 Ω
50 MHz
2 : 332.03 Ω
−802.69 Ω
100 MHz
3 : 45.953 Ω
−303.47 Ω
300 MHz
1
2
4 3
START 50.000 000 MHz
DS04–21367–2E
STOP 500.000 000 MHz
19
MB15F72UL
6. OSCIN input impedance
OSCIN input impedance
4 : 25.125 Ω
−686.59 Ω
2.318 pF
100.000 000 MHz
1 :10.781 kΩ
−13.358 kΩ
3 MHz
2 : 1.534 kΩ
−6.5593 kΩ
10 MHz
42
1
3
START 3.000 000 MHz
20
3 : 119.25 Ω
−1.7281 kΩ
40 MHz
STOP 100.000 000 MHz
DS04–21367–2E
MB15F72UL
■ REFERENCE INFORMATION
(for Lock-up Time, Phase Noise and Reference Leakage)
Test Circuit
S.G.
OSCIN
LPF
DO
fin
Spectrum
Analyzer
fVCO = 720.5 MHz
KV = 31
fr = 12.5 kHz
fOSC = 19.2 MHz
LPF
VCC = 3.0 V
VVCO = 3.0 V
Ta = +25 °C
CP : 6 mA mode
VCO
• PLL Reference Leakage
ATTEN 10 dB
RL 0 dBm
VAVG 24
10 dBm
MKR -70.33 dB
12.7 kHz
MKR
D 12.7 kHz
S -70.33 dB
CENTER 720.5000 MHz
RBW 1.0 kHz
VBW 1.0 kHz
SPAN 200.0 kHz
SWP 500 ms
• PLL Phase Noise
ATTEN 10 dB
RL 0 dBm
VAVG 34
10 dBm
MKR -50.16 dB
3.07 kHz
MKR
D 3.07 kHz
S -50.16 dB
CENTER 720.5000 MHz
RBW 100 Hz
VBW 100 Hz
SPAN 20.0 kHz
SWP 1.60 s
(Continued)
DS04–21367–2E
21
MB15F72UL
(Continued)
• PLL Lock Up time
• PLL Lock Up time
720.5 MHz→757.5 MHz within ± 1 kHz
Lch→Hch 2.533 ms
757.504500 MHz
720.504250 MHz
757.500500 MHz
720.500250 MHz
757.496500 MHz
720.496250 MHz
−5.000 ms
22
757.5 MHz→720.5 MHz within ± 1 kHz
Hch→Lch 2.511 ms
0.00 s
1.000 ms/div
5.000 ms
−5.000 ms
0.00 s
1.000 ms/div
5.000 ms
DS04–21367–2E
MB15F72UL
■ APPLICATION EXAMPLE
VCO
OUTPUT
2.7 V
1000 pF
from controller
LPF
2.7 V
1000 pF
0.1 μF
0.1 μF
Clock
Data
LE
finRF
XfinRF
GNDRF
VCCRF
PSRF
VpRF
DoRF
20
19
18
17
16
15
14
13
12
11
MB15F72UL
1
2
3
4
5
6
7
8
9
10
OSCIN
GND
finIF
XfinIF
GNDIF
VCCIF
PSIF
VpIF
DoIF
LD/fout
Lock Det.
1000 pF
1000 pF
2.7 V
2.7 V
1000 pF
0.1 μF
0.1 μF
TCXO
OUTPUT
VCO
LPF
Notes : • Clock, Data, LE : The schmitt trigger circuit is provided (insert a pull-down or pull-up
register to prevent oscillation when open-circuit in the input) .
• The terminal number shows that of TSSOP-20.
DS04–21367–2E
23
MB15F72UL
■ USAGE PRECAUTIONS
(1) VCCRF, VpRF, VCCIF and VpIF must be equal voltage.
Even if either RF-PLL or IF-PLL is not used, power must be supplied to VCCRF, VpRF, VCCIF and VpIF to
keep them equal. It is recommended that the non-use PLL is controlled by power saving function.
(2) To protect against damage by electrostatic discharge, note the following handling precautions :
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting or removing this device into or from a socket.
-Protect leads with conductive sheet, when transporting a board mounted device.
24
DS04–21367–2E
MB15F72UL
■ ORDERING INFORMATION
Part number
Package
MB15F72ULPFT
20-pin, plastic TSSOP
(FPT-20P-M06)
MB15F72ULWQN
20-pin, Plastic QFN
(LCC-20P-M63)
DS04–21367–2E
Remarks
25
MB15F72UL
■ PACKAGE DIMENSIONS
20-pin plastic TSSOP
Lead pitch
0.65 mm
Package width ×
package length
4.40 × 6.50 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.10 mm MAX
Weight
0.08g
Code
(Reference)
P-TSSOP20-4.4×6.5-0.65
(FPT-20P-M06)
20-pin plastic TSSOP
(FPT-20P-M06)
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max).
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
*1 6.50±0.10(.256±.004)
0.17±0.05
(.007±.002)
11
20
*2 4.40±0.10 6.40±0.20
(.173±.004) (.252±.008)
INDEX
Details of "A" part
1.05±0.05
(Mounting height)
(.041±.002)
LEAD No.
1
10
0.65(.026)
"A"
0.24±0.08
(.009±.003)
0.13(.005)
M
0~8°
+0.03
(0.50(.020))
0.10(.004)
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F20026S-c-3-5
0.60±0.15
(.024±.006)
+.001
0.07 –0.07 .003 –.003
(Stand off)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
(Continued)
26
DS04–21367–2E
MB15F72UL
(Continued)
20-pin plastic QFN
Lead pitch
0.50 mm
Package width ×
package length
4.00 mm × 4.00 mm
Sealing method
Plastic mold
Mounting height
0.80 mm MAX
Weight
0.04 g
(LCC-20P-M63)
20-pin plastic QFN
(LCC-20P-M63)
2.00±0.10
(.0.79±.004)
4.00±0.10
(.157±.004)
+0.05
4.00±0.10
(.157±.004)
0.25 –0.07
(.010 +.002
–.003 )
2.00±0.10
(.0.79±.004)
INDEX AREA
1PIN ID
(C0.35(C.014))
0.40±0.05
(.016±.002)
0.50(.020)
(TYP)
0.75±0.05
(.030±.002)
+0.03
0.02 –0.02
(.001 +.001
–.001 )
C
0.20(.008)
2012 FUJITSU SEMICONDUCTOR LIMITED HMbC20-63Sc-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS04–21367–2E
27
MB15F72UL
■ MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page
Section
Change Results
28
■ DESCRIPTION
Deleted the description.
1
■ FEATURES
Deleted the following description.
• Small package BCC20 (3.4 mm × 3.6 mm × 0.6 mm)
2
■ PIN ASSIGNMENTS
3
■ PIN DESCRIPTION
Revised the package code.
LCC-20P-M05 → LCC-20P-M63
25
■ ORDERING INFORMATION
Revised the ordering information.
27
■ PACKAGE DIMENSIONS
Revised the package code.
LCC-20P-M05 → LCC-20P-M63
DS04–21367–2E
MB15F72UL
MEMO
DS04–21367–2E
29
MB15F72UL
MEMO
30
DS04–21367–2E
MB15F72UL
MEMO
DS04–21367–2E
31
MB15F72UL
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Asia Pacific
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://sg.fujitsu.com/semiconductor/
Europe
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
30F, Kerry Parkside, 1155 Fang Dian Road, Pudong District,
Shanghai 201204, China
Tel : +86-21-6146-3688 Fax : +86-21-6146-3660
http://cn.fujitsu.com/fss/
Korea
FUJITSU SEMICONDUCTOR KOREA LTD.
902 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fsk/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
2/F, Green 18 Building, Hong Kong Science Park,
Shatin, N.T., Hong Kong
Tel : +852-2736-3232 Fax : +852-2314-4207
http://cn.fujitsu.com/fsp/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
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