A4411 Datasheet

A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
FEATURES AND BENEFITS
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Automotive AEC-Q100 qualified
3.5 to 36 VIN operating range, 40 VIN maximum
Buck or buck-boost pre-regulator (VREG)
Adjustable PWM switching frequency: 250 kHz to 2.4 MHz
PWM frequency can be synchronized to external clock
Synchronous buck regulator (ADJ) delivers 0.8 to 3.3 V
Two 5 V LDOs for “local” sensors (V5SNR) and
communications (V5CAN) with foldback short-circuit
protections
5 V internal tracking LDO for remote sensors with foldback
short-circuit and short-to-battery protections (V5P)
TRACK sets FBADJ or V5SNR as the reference for V5P
Programmable pulse-width window watchdog (PWWD)
with scalable activation delay and selectable tolerance
Internal Watchdog (WD) CLK with ±5% accuracy
Accepts external WD CLK for improving accuracy
Active-low Watchdog Enable pin (WDENn)
Dual bandgaps for increased reliability: BGVREF, BGFAULT
Power-on reset (NPOR) with fixed delay of 2 ms
Power OK output for 5 V LDOs UV/OV (POK5V)
Logic enable input for microprocessor control (ENB)
Continued on next page...
APPLICATIONS
□□ Electronic power steering (EPS) modules
□□ Automotive power trains
□□ CAN power supplies
□□ High-temperature applications
PACKAGE: 38-Pin eTSSOP (suffix LV)
DESCRIPTION
The A4411 is a power management IC that can be configured
as a buck or buck-boost pre-regulator to efficiently convert
automotive battery voltages into a tightly regulated intermediate
voltage complete with control, diagnostics, and protections.
The output of the pre-regulator supplies a 5 V / 150 mAMAX
LDO for “local” sensors (V5SNR), a 5 V / 200 mAMAX LDO
for communications (V5CAN), a 5 V / 120 mAMAX tracking/
protected LDO for remote sensors (V5P), and a 0.8 to
3.3 V / 800 mAMAX adjustable synchronous buck regulator
(ADJ). Designed to supply CAN or microprocessor power
supplies in high-temperature environments, the A4411 is ideal
for underhood applications.
The A4411 can be enabled by its logic level (ENB) or highvoltage (ENBAT) input. The A4411 includes a TRACK pin to
set the reference of the V5P tracking regulator to either V5SNR
or the buck FBADJ pin, so the A4411 can be adapted across
multiple platforms with different sensors and supply rails.
Diagnostic outputs from the A4411 include a power-on-reset
output (NPOR) with a fixed delay, an ENBAT status output,
and a Power OK output for the 5 V LDOs (POK5V). Dual
bandgaps, one for regulation and one for fault checking,
improve long-term reliability of the A4411.
The A4411 contains a Pulse-Width Window Watchdog (PWWD)
that can be programmed to detect pulse widths from 1 to
2 ms (WDADJ). The watchdog has an activation delay that
scales with the pulse-width setting to accommodate processor
startup. The tolerance of the Watchdog’s Window can be set to
±8%, ±13%, or ±18% using the WDTOL pin. The watchdog has
an active-low enable pin (WDENn) to facilitate initial factory
programming or field reflash programming.
Continued on next page...
Not to scale
5.35 V
(VREG)
Buck-Boost
Pre-Regulator
Dual
Bandgaps
5 V LDO
Communications
(V5CAN)
with Foldback
Protection
Charge
Pump
Thermal
Shutdown
(TSD)
5 V LDO
Local Sensor(s)
(V5SNR)
with Foldback
Protection
Adjustable (ADJ)
Sync. Buck
Regulator
0.8 to 3.3 VOUT
FBADJ
POK5V
Output
NPOR
Output
V5SNR
A4411 Simplified Block Diagram
A4411-DS, Rev. 3
Programmable
Pulse Width
Window Watchdog
with Selectable
Tolerance
Tracking
Control
2:1 MUX
5 V Protected
LDO (V5P) for
Remote Sensors
with Tracking,
Foldback, and
Short to VBAT
Protetction
REF
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
Features and Benefits (continued)
Description (continued)
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Protection features include under- and overvoltage lockout on all four
CPU supply rails. In case of a shorted output, all linear regulators
feature foldback overcurrent protection. In addition, the V5P output
is protected from a short-to-battery event. Both switching regulators
include pulse-by-pulse current limit, hiccup mode short-circuit
protection, LX short-circuit protection, missing asynchronous diode
protection (VREG only), and thermal shutdown.
High-voltage ignition enable input (ENBAT)
ENBAT status indicator output (ENBATS)
SLEW rate control pin helps reduce EMI/EMC
Frequency dithering helps reduce EMI/EMC
OV and UV protection for all four CPU supply rails
Pin-to-pin and pin-to-ground tolerant at every pin
Thermal shutdown protection
−40ºC to 150ºC junction temperature range
Selection Guide
Part Number
A4411KLVTR-T
1
Temperature Range
–40 to 135°C
The A4411 is supplied in a low-profile 38-lead eTSSOP package
(suffix “LV”) with exposed power pad.
Package
38-pin eTSSOP with thermal pad
Packing1
4000 pieces per 7-inch reel
Lead Frame
100% matte tin
Contact Allegro for additional packing options.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
SPECIFICATIONS
Absolute Maximum Ratings1
Characteristic
VIN
Symbol
Notes
Rating
Unit
−0.3 to 40
V
−13 to 40
V
−0.3 to 8
V
±75
mA
−0.3 to VVIN + 0.3
V
VVIN
VENBATx
ENBAT
With current limiting
resistor2
IENBATx
LX1, SLEW
t < 250 ns
−1.5
V
t < 50 ns
VVIN + 3 V
V
−0.3 to 50
V
VCP, CP1, CP2
V5P
VV5P
Independent of VVIN
All other pins
−1 to 40
V
−0.3 to 7
V
Ambient Temperature
TA
−40 to 135
ºC
Junction Temperature
TJ
−40 to 150
ºC
Storage Temperature Range
Tstg
−40 to 150
ºC
Range K for automotive
Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability
2 The higher ENBAT ratings (–13 V and 40 V) are measured at node “A” in the following circuit configuration:
1
Node “A”
≥450 Ω
ENBAT
VEN
+
-
A4411
GND
Thermal Characteristics: May require derating at maximum conditions; see application information
Characteristic
Junction to Pad Thermal Resistance
Symbol
RθJC
Test Conditions*
eTSSOP-38 (LV) Package
Value
Unit
30
ºC/W
*Additional thermal information available on the Allegro website.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
A4411
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
CP1
1.0 µF
CP2
0.22 µF
These components
required if VVIN < 6.0 V
2×4.7 µF
50 V
1210
100 µF
50 V/250 mΩ
KEY_SW
VREG
VIN
VIN
0.1 µF
0603
VCC
CVCC
1 µF
CP1
39 pF
RZ1
22.1 kΩ
CZ1
1.5 nF
SYNC
(optional)
CSS1
22 nF
VIN,START
VIN,STOP
VCC
COMP1
SS1
OSC1
FET/SYNC
BG1_UV, BG2_UV
VCC UV, VCP UV
VIN,UVLO
*VCP OV, *D1MISSING
*ILIM,LX1, *ILIM,LX2
VCC
20 kΩ
NPOR
CLK @ FOSC
MPOR
20 kΩ
POK5V
0.47 µF
IFB,ADJ
VSS2RST
3.3 kΩ
V_IGN
Optional CLK
Input for highest
precision WD
SELECT
0
2:1
MUX
WDENn
CLKIN
RADJ
22.1 kΩ for 1 ms pulse
widths at CLKIN
WDADJ
WDOSC
±5%
WDENn
WDIN
WDtol
5V
LDO
1
NPOR
VCC_UV
BG1_UV
CP2
39 pF
RFB2
1.52 kΩ
±0.5%
CZ2
1.5 nF
D5
MSS1P5
2.2 µF
V5P
120 mAMAX
500 kHz – 1 MHz
NPOR
RISING
EDGE
DELAY
V5SNR
150 mAMAX
V5SNR
2.2 µF
5V
LDO
ON/OFF
V5CAN
FALLING
SU/SD
DELAY
tdLDO,OFF
RESET
WDFAULT
ENBAT1
STATUS
ENBATS
VCC
20 kΩ
>WDMASTER_CLK
WDACTIVE
V5CAN
200 mAMAX
2.2 µF VCC
20 kΩ
PULSE WIDTH
WINDOW WATCHDOG
WDOUT
RESET
DOMINANT
S Q
EDGE DETECT
RWD,ENn
CSS2
22 nF
RZ2
10 kΩ
FOLDBACK
DEGLITCH
tdFILT
WDADJ = 0 V
WDRESET
3.3 VOUT
800 mAMAX
RFB1
4.75 kΩ
±0.5%
FBADJ
LDOs ON
60 kΩ
Ground using WDADJ if
using WDCLK,IN
V5P
FOLDBACK
3.3 VTYP↑
2.6 VTYP↓
DIV by
8
Short to
VBAT
Protection
2 × 10 µF
16 V/X7R/1206
(16–19 µf @ 3.3 V)
LDOs ON
BGVREF
WDCLK,IN
PGND
PGND
FBADJ
COMP2
SS2
5v
TRACKING
LDO
ADJ ON
ENB
EXT WD CLK
4 MHz – 8 MHz
V5PDISC
FOLDBACK
L2 2.2 µH, 61 MΩ
IHLP1616BEZER2R2M11
LX2
LX2
ADJ ON
REF
650 kΩ
VREG
74LVC1GX04
V5SNR
V5CAN
V5P
V5SNR
0.22 µF*
µC
ENABLE
XTAL
DRIVER
DEGLITCH
tdFILT
ENBAT
7.5 V
MMSZ
4693T1
7.5 kΩ
FBADJ
VREG ON
STARTUP/
SHUTDOWN
SEQUENCE
IBIASTRK
* For negative V_IGN
tranwsient suppression
BGVREF
DEGLITCH
tdFILT
V5PDISC
TRACK
COMP2 &
SS2 Reset
SYNCHRONOUS
BUCK
REGULATOR
(ADJ)
(w/Hiccup Mode)
CLK @
FOSC
REF
BGFAULT
MPOR
VCC UV SU/SD
VREG UV
FBADJ UV
V5SNR UV
V5CAN UV
V5P UV
VREG
TSD
OV/UV DETECT
& DELAYS
POK5V
2 kΩ
VSS1RST
SS OK
5×10 µF
16 V/X7R/1206
(38 – 43 µF @ 5.3 V)
D2
SS3P4
Q1:
NVTFS4823N or
SQS420EN or
STL10N3LLH5
D1
SS3P4
LG
FB
RST
REF
ON/OFF
SLEW UV/OV
FAULT
COMP1 & SS1 Reset
CLK1MHz
VCC
L1 4.7 µH, 37 mΩ
IHLP2525CZER4R7M01
LX1
LX1
1.5 V/ns
STOP PWM
OV/UV DETECT
& DELAYS
NPOR
RSLEW
22.1 kΩ
75 mΩ
BUCK-BOOST
PRE-REGULATOR
(VREG)
(w/Hiccup Mode)
FSET UV/OV
MASTER
IC POR
(MPOR)
*indicates a
latched fault
SLEW
BG2_UV
BGVREF
VREG ON
VCP UV
CLK1MHz
VCP
UV/OV
Charge
Pump
BGFAULT
BG2
SS1
OSC2
ISLEW
BGVREF
COMP1
IBIASFSET
RFSET
8.66 kΩ
VIN,UVLO
D4
MSS1P5
CP3
0.1 µF/50 V
BG1_UV
BG1
LDO
3.6 V
SU/SD
D3
BAS16J
CP2
Din
SS3P4
VCP
CP1
VBAT
WDOUT
WDOUT = 0 for
a WD Fault
R
GND
GND
±8% / ±13% / ±17%
A4411
Functional Block Diagram/Typical Schematic
Buck-Boost Mode (fOSC = 2 MHz)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
CP1
1.0 µF
CP2
0.22 µF
These components
required if VVIN < 6.0 V
Din
SS3P4
100 µF
50 V/250 mΩ
0.1 µF
0603
SLEW
LX1
LX1
RZ1
15 kΩ
RFSET
57.6 kΩ
FET/SYNC
RSLEW
42.2 kΩ
5×10 µF
10 V/X7R/1206
(~65 µF @ 5.3 V)
L1 22 µH, 66 mΩ
IHLP2525CZER4R7M01
COMP1
CZ1
4.7 nF
SYNC
(optional)
D4
MSS1P5
CP3
0.1 µF
50 V
VIN
VIN
2×4.7 µF
50 V
1210
CP1
39 pF
D3
BAS16J
CP2
VCP
CP1
VBAT
A4411
D1
SS3P4
D2
SS3P4
Q1:
NVTFS4823N or
SQS420EN or
STL10N3LLH5
LG
2 kΩ
VREG
0.47 µF
LX2
LX2
2 × 22 µF
10 V/X7R/1206
(~36 µf @ 3.3 V)
L2 22 µH, 135 MΩ
IHLP1616BEZER2R2M11
3.3 VOUT
800 mAMAX
RFB1
4.75 kΩ
±0.5%
PGND
PGND
FBADJ
COMP2
RZ2
17.4 kΩ
CP2
39 pF
RFB2
1.52 kΩ
±0.5%
CZ2
3.3 nF
Functional Block Diagram Modifications for Buck-Boost Mode (fOSC = 400 kHz)
A4411
CP1
27 pF
COMP1
RZ1
13.3 kΩ
CZ1
2.7 nF
D3
BAS16J
CP2
These components
required if VVIN < 6.0 V
CP1
A4411
D4
MSS1P5
0.1 µF/50 V
L1 4.7 µH, 37 mΩ
IHLP2525CZER4R7M01
LX1
LX1
5.35 VTYP
D1
SS2P4
3×10 µF
16 V/X7R/1206
(23 – 26 µF @ 5.3 V)
LG
VREG
0.47 µF
Functional Block Diagram Modifications for Buck Only Mode, fOSC = 2 MHz
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
Body Diode
VBAT
MODULE
Functional Block Diagram Using a PMOS FET for Reverse-Battery Protection Instead of a Series Schottky Diode
(DIN)
VBAT
MODULE
Body Diode
Functional Block Diagram Using an NMOS FET for Reverse-Battery Protection Instead of a Series Schottky Diode
(DIN)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
38 CP2
Terminal List Table
VCP
1
VIN
2
37 CP1
Number
Name
VIN 3
36 LX1
1
VCP
Charge pump reservoir capacitor
35 LX1
2, 3
VIN
Input voltage pins
GND
4
Function
VCC 5
34 SLEW
4, 18
GND
Ground pin
SS1 6
33 LG
5
VCC
Internal voltage regulator bypass capacitor pin
32 VREG
6
SS1
Soft-start programming pin for the buck-boost pre-regulator
NPOR 8
31 V5CAN
7
COMP1
POK5V 9
30 LX2
8
NPOR
Active-low, open-drain regulator fault detection output
29 LX2
9
POK5V
Power OK output indicating when either the V5SNR, V5CAN, or V5P rail is
undervoltage (UV)
COMP1 7
ENB 10
PAD
Error amplifier compensation network pin for the buck-boost pre-regulator
FSET/SYNC 11
28 PGND
TRACK 12
27 PGND
10
ENB
ENBAT 13
26 COMP2
11
FSET/
SYNC
Frequency setting and synchronization input
12
TRACK
Tracking control: Open/High – V5P tracks the FBADJ pin, GND/Low – V5P
tracks V5SNR
13
ENBAT
Ignition enable input from the key/switch via a series resistor
14
ENBATS
15
WDOUT
16
WDIN
Watchdog pulse train input from a microcontroller or DSP
17
V5SNR
5 V regulator output for local sensor(s)
19
WDCLK,IN
20
WDTOL
Selectable watchdog tolerance: low = ±8%, float = ±13%, high (to VCC)
= ±18%
21
WDADJ
The watchdog window time is set from 1 to 2 ms by connecting RADJ from
this pin to ground
22
WDENn
Active-low watchdog enable input from a microcontroller or DSP. Open/
Low = WD is enabled, High = WD is disabled
ENBATS 14
25 FBadj
WDOUT 15
24 SS2
WDIN 16
23 V5P
V5SNR 17
22 WDENn
GND 18
21 WDADJ
WDCLK,IN 19
20 WDtol
Package LV, 38-Pin eTSSOP
Pinout Diagram
Logic-enable input from a microcontroller or DSP
Open-drain ignition status output of ENBAT
Watchdog output, latched low if a watchdog fault is detected
WD clock input for highest WD accuracy. If this pin is used the WDADJ pin
must be grounded.
23
V5P
5 V tracking/protected regulator output
24
SS2
Soft-start programming pin for the adjustable synchronous buck regulator
25
FBADJ
26
COMP2
27, 28
PGND
29, 30
LX2
Feedback pin for the adjustable synchronous buck regulator
Error amplifier compensation network pin for the adjustable synchronous
buck regulator
Power ground for the adjustable synchronous regulator / gate driver
Switching node for the adjustable synchronous buck regulator
31
5VCAN
5 V regulator output for communications
32
VREG
Output of the pre-regulator and input to the LDOs and adjustable
synchronous buck
33
LG
Boost gate drive output for the buck-boost pre-regulator
34
SLEW
35, 36
LX1
Switching node for the buck-boost pre-regulator
Slew rate adjustment for the rise time of LX1
37
CP1
Charge pump capacitor connection
38
CP2
Charge pump capacitor connection
–
PAD
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
ELECTRICAL CHARACTERISTICS1: Valid at 3.5 V 4 < VIN < 36 V, –40ºC < TA = TJ < 150ºC, unless otherwise specified.
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Buck-Boost Mode, after VVIN > VINSTART, and
VENB > 2 V or VENBAT > 3.5 V, NPOR = 1,
POK5V = 1
3.5
13.5
36
V
Buck Only Mode, after VVIN > VINSTART, and
VENB > 2 V or VENBAT > 3.5 V,
NPOR = 1 and POK5V = 1
5.7
13.5
36
V
V
General Specifications
Operating Input Voltage
VVIN
VIN UVLO Start Voltage
VINSTART
VVIN rising, Buck or Boost Mode
5.10
5.40
5.70
VIN UVLO Stop Voltage
VINSTOP
VVIN falling, Buck or Boost Mode
2.88
3.04
3.20
V
VIN UVLO Hysteresis
VINHYS
VINSTART ‒ VINSTOP
–
2.7
–
V
VINSTOP1,BUCK
NPOR = 1, POK5V ↓
–
5.1
5.3
V
VINSTOP2,BUCK
VVCP < VCPUV,L and NPOR ↓, POK5V = 0
–
3.8
4.2
V
VVIN = 13.5 V, VENBAT ≥ 3.6 V or
VENB ≥ 2 V, VVREG = 5.6 V (no PWM)
–
13
–
mA
VVIN = 13.5 V, VENBAT ≤ 2.2 V and
VENB ≤ 0.8 V
–
–
10
µA
VIN Dropout Voltages Buck
Mode, VVIN Falling
Supply Quiescent Current
1
IQ
IQ,SLEEP
PWM Switching Frequency and Dithering
RFSET = 8.66 kΩ
Switching Frequency
Frequency Dithering
fOSC
ΔfOSC
1.8
2
2.2
MHz
RFSET = 20.5 kΩ 2
–
1
–
MHz
RFSET = 57.6 kΩ 2
343
400
457
kHz
–
±12
–
%
As a percent of fOSC
Dither/Slew START Threshold
VINDS,ON
8.5
9
9.6
V
Dither/Slew STOP Threshold
VINDS,OFF
7.8
8.3
8.9
V
–
700
–
mV
VVCP – VVIN, VVIN = 13.5 V, VVREG = 5.5 V,
IVCP = 6.5 mA, VCOMP1 = VCOMP2 = 0 V,
VENB = 3.3 V
4.1
6.6
–
V
VVCP – VVIN, VVIN = 6.5 V, VVREG = 5.5 V,
IVCP = 6.5 mA, VCOMP1 = VCOMP2 = 0 V,
VENB = 3.3 V
3.1
3.8
–
V
–
65
–
kHz
–
4.65
–
V
155
170
185
ºC
–
20
–
VIN Dithering/Slew Hysteresis
Charge Pump (VCP)
Output Voltage
Switching Frequency
VVCP
fSW,CP
VCC Pin Voltage
Output Voltage
VVCC
VVREG = 5.35 V
Thermal Shutdown Threshold 2
TTSD
TJ rising
Thermal Shutdown Hysteresis 2
THYS
Thermal Protection
1
2
Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking).
Ensured by design and characterization, not production tested.
Continued on next page...
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
ELECTRICAL CHARACTERISTICS (continued) 1: Valid at 3.5 V 4 < VIN < 36 V, –40ºC < TA = TJ < 150ºC, unless otherwise
specified.
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
VVREG
VVIN = 13.5 V, ENB = 1, 0.1 A < IVREG < 1.25 A
5.25
5.35
5.45
V
VCOMP1 for 0% duty cycle
–
400
–
mV
VVIN = 13.5 V, 10% to 90%, IVREG = 1 A,
RSLEW = 22.1 kΩ
–
0.9
–
V/ns
VVIN = 13.5 V, 10% to 90%, IVREG = 1 A,
RSLEW = 249 kΩ
–
0.3
–
V/ns
Output Voltage Specifications
Buck Output Voltage – Regulating
Pulse-Width Modulation (PWM)
PWM Ramp Offset
LX1 Rising Slew Rate Control 2
PWM1OFFS
LX1RISE
LX1 Falling Slew Rate 2
LX1FALL
Buck Minimum On-Time
tON,MIN,BUCK
Buck Maximum Duty Cycle
DMAX,BUCK
Boost Minimum Off-Time
tON,MIN,BST
Boost Duty Cycle
COMP1 to LX1 Current Gain
Slope Compensation 2
VVIN = 13.5 V, 90% to 10%, IVREG = 1 A
tOFF,BUCK < 50 ns
–
1.5
–
V/ns
–
100
150
ns
–
100
–
%
100
130
230
ns
DMIN,BST
After VVIN > VINSTART, VVIN = 6.5 V
–
20
–
%
DMAX,BST
After VVIN > VINSTART, VVIN = 3.5 V
–
58
68
%
gmPOWER1
SE1
–
4.5
–
A/V
fOSC = 2 MHz
1.04
1.48
1.92
A/µs
fOSC = 400 kHz
0.22
0.33
0.44
A/µs
Internal MOSFET
VVIN = 13.5 V, TJ = ‒40°C 2, IDS = 0.1 A
–
50
65
mΩ
VVIN = 13.5 V, TJ = 25°C 3, IDS = 0.1 A
–
75
90
mΩ
VVIN = 13.5 V, TJ = 150°C, IDS = 0.1 A
–
150
180
mΩ
IC disabled, VLX1 = 0 V, VVIN = 16 V, −40°C <
TJ < 85°C 3
–
–
10
µA
IC disabled, VLX1 = 0 V, VVIN = 16 V, −40°C <
TJ < 150°C
–
50
150
µA
–
60
–
dB
VSS1 = 750 mV
550
750
950
µA/V
VSS1 = 500 mV
275
375
475
µA/V
IEA1
–
±75
–
µA
Maximum Output Voltage
EA1VO(max)
1.3
1.7
2.1
V
Minimum Output Voltage
EA1VO(min)
–
–
300
mV
–
1
–
kΩ
MOSFET On-Resistance
MOSFET Leakage
RDSon
IFET,LKG
Error Amplifier
Open-Loop Voltage Gain
AVOL1
Transconductance
gmEA1
Output Current
COMP1 Pull-Down Resistance
1
2
3
RCOMP1
HICCUP1 = 1 or FAULT1 = 1 or
IC disabled, latched until VSS1 < VSS1RST
Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking).
Ensured by design and characterization, not production tested.
Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
Continued on next page...
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
ELECTRICAL CHARACTERISTICS (continued)1: Valid at 3.5 V 4 < VIN < 36 V, –40ºC < TA = TJ < 150ºC, unless otherwise
specified.
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
4.6
–
5.5
V
Boost MOSFET (LG) Gate Driver
LG High Output Voltage
VLG,ON
VVIN = 6 V, VVREG = 5.35 V
LG Low Output Voltage
VLG,OFF
VVIN = 13.5 V, VVREG = 5.35 V
–
0.2
0.4
V
LG Source Current 1
ILG,ON
VVIN = 6 V, VVREG = 5.35 V, VLG = 1 V
–
−300
–
mA
LG Sink Current 1
ILG,OFF
VVIN = 13.5 V, VVREG = 5.35 V, VLG = 1 V
–
150
–
mA
–
400
–
mV
mV
Soft-Start
SS1 Offset Voltage
VSS1OFFS
VSS1 rising due to ISS1SU
SS1 Fault/Hiccup Reset Voltage
VSS1RST
VSS1 falling due to HICCUP1 = 1 or
FAULT1 = 1 or IC disabled
140
200
275
SS1 Startup (Source) Current
ISS1SU
VSS1 = 100 mV, HICCUP1 = FAULT1 = 0
−10
−20
−30
µA
SS1 Hiccup (Sink) Current
ISS1HIC
VSS1 = 0.5 V, HICCUP1 = 1
5
10
15
µA
SS1 Delay Time
tSS1,DLY
CSS1 = 22 nF
–
440
–
µs
SS1 Ramp Time
tSS1
CSS1 = 22 nF
–
880
–
µs
FAULT1 = 1 or IC disabled, latched until
VSS1 < VSS1RST
–
3
–
kΩ
0 V < VVREG < 1.3 VTYP
–
fOSC/4
–
–
1.3 V < VVREG < 2.7 VTYP
–
fOSC/2
–
–
VVREG > 2.7 VTYP
–
fOSC
–
–
VSS1 > VHIC1,EN, VVREG < 1.3 VTYP, VCOMP =
EA1VO(max)
–
30
–
PWM
cycles
VSS1 > VHIC1,EN, VVREG > 1.3 VTYP, VCOMP =
EA1VO(max)
–
120
–
PWM
cycles
tON = tON(MIN)
3.8
4.3
4.8
A
Latched off after 1 detection
7.5
10
–
A
SS1 Pull-Down Resistance
SS1 PWM Frequency Foldback
RPDSS1
fSW1,SS
Hiccup Mode
Hiccup1 OCP PWM Counts
tHIC1,OCP
Current Protections
Pulse-by-Pulse Current Limit
LX1 Short-Circuit Current Limit
ILIM1,ton(min)
ILIM,LX1
Missing Asynchronous Diode (D1) Protection
Detection Level
VD,OPEN
−1.6
−1.3
−1
V
Time Filtering 2
tD,OPEN
50
–
250
ns
1
2
Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking).
Ensured by design and characterization, not production tested.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
ELECTRICAL CHARACTERISTICS – 1.25 V SYNCHRONOUS BUCK REGULATOR1: Valid at 3.6 V 4 < VIN < 36 V, –40ºC <
TA = TJ < 150ºC, unless otherwise specified.
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
787
800
813
mV
Feedback Reference Voltage
Reference Voltage
VFB,ADJ
Pulse-Width Modulation (PWM)
PWM Ramp Offset
PWM2OFFS
High-Side MOSFET Minimum On-Time
tON(MIN)
High-Side MOSFET Minimum Off-Time
tOFF(MIN)
Gate Driver Non-Overlap Time 2
COMP2 to LX2 Current Gain
Slope Compensation 2
VCOMP2 for 0% duty cycle
Does not include total gate driver non-overlap
time, tNO
−
350
−
mV
−
65
105
ns
−
80
110
ns
tNO
−
15
−
ns
gmPOWER2
−
2.5
−
A/V
fOSC = 2 MHz
0.45
0.63
0.81
A/μs
fOSC = 400 kHz
0.12
0.14
0.19
A/μs
TA = 25°C 3, IDS = 100 mA
−
150
180
mΩ
IDS = 100 mA
−
−
300
mΩ
VVREG = 5.5 V
−
12
−
ns
IC disabled, VLX2 = 0 V, VVREG = 5.5 V,
‒40˚C < TJ < 85˚C 3
−
−
2
μA
IC disabled, VLX2 = 0 V, VVREG = 5.5 V,
−40°C < TJ < 150°C
−
3
15
μA
SE2
Internal MOSFETs
High-Side MOSFET On-Resistance
LX2 Node Rise/Fall Time 2
High-Side MOSFET Leakage 1
RDSon(HS)
t R/F,LX2
IDSS (HS)
Low-Side MOSFET On-Resistance
RDSon(LS)
Low-Side MOSFET Leakage 1
IDSS (LS)
TA = 25°C 3, IDS = 100 mA
−
55
65
mΩ
IDS = 100 mA
−
−
110
mΩ
IC disabled, VLX2 = 5.5 V, ‒40˚C < TJ < 85˚C 3
−
−
1
μA
IC disabled, VLX2 = 5.5 V, −40°C < TJ < 150°C
−
4
10
μA
VCOMP2 = 0.8 V, VFB,ADJ regulated so that
ICOMP2 = 0 A
−
–150
−350
nA
−
60
–
dB
550
750
950
μA/V
–
250
–
μA/V
μA
Error Amplifier
Feedback Input Bias Current 1
IFB, ADJ
Open-Loop Voltage Gain 2
AVOL2
Transconductance
gmEA2
ICOMP2 = 0 μA, VSS2 > 500 mV
0 V < VSS2 < 500 mV
Source and Sink Current
IEA2
−
±50
−
Maximum Output Voltage
EA2VO(max)
1.00
1.25
1.50
V
Minimum Output Voltage
EA2VO(min)
–
–
150
mV
−
1.5
−
kΩ
COMP2 Pull-Down Resistance
RCOMP2
VCOMP2 = 1.5 V
HICCUP2 = 1 or FAULT2 = 1 or
VENBATx ≤ 2.2 V and VENB ≤ 0.8 V, latched until
VSS2 < VSS2RST
Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking).
Ensured by design and characterization, not production tested.
3 Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
1
2
Continued on next page...
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
ELECTRICAL CHARACTERISTICS – 1.25 V SYNCHRONOUS BUCK REGULATOR (continued)1: Valid at 3.6 V 4 < VIN <
36 V, –40ºC < TA = TJ < 150ºC, unless otherwise specified.
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Soft-Start
SS2 Offset Voltage
VSS2,OFFS
120
200
270
mV
VSS2 falling due to HICCUP2 = 1 or
FAULT2 = 1 or IC disabled
−
100
120
mV
ISS2,SU
VSS2 = 1 V, HICCUP2 = FAULT2 = 0
−10
–20
−30
μA
SS2 Hiccup (Sink) Current
ISS2,HIC
VSS2 = 0.5 V, HICCUP2 = 1
5
10
20
μA
SS2 to VADJ Delay Time
tSS2,DLY
CSS2 = 10 nF
−
100
−
μs
tSS2
CSS2 = 10 nF
−
400
−
μs
SS2 Fault/Hiccup Reset Voltage
SS2 Startup (Source) Current
VFB,ADJ Soft Start Ramp Time
VSS2,RST
VSS2 rising due to ISS2,SU
SS2 Pull Down Resistance
RPDSS2
FAULT2 = 1 or IC disabled, latched until VSS2
< VSS2RST
−
2
−
kΩ
VFB,ADJ < 300 mVTYP
−
fOSC/4
−
−
SS2 PWM Frequency Foldback
fSW2,SS
300 mVTYP < VFB,ADJ < 500 mVTYP
−
fOSC/2
−
−
VFB,ADJ > 500 mVTYP
−
fOSC
−
−
VSS2 rising
–
1.2
–
V
Hiccup Mode
Hiccup2 OCP Enable Threshold
Hiccup2 OCP Counts
VHIC2,EN
tHIC2,OCP
VSS2 > VHIC2,EN, VFB,ADJ < 300 mVTYP
–
30
–
PWM
cycles
VSS2 > VHIC2,EN, VFB,ADJ > 300 mVTYP
–
120
–
PWM
cycles
2.1
2.4
A
Current Protections
Pulse-by-Pulse Current Limit
LX2 Short-Circuit Protection
1
2
ILIM2,5%
Duty cycle = 5%
1.8
ILIM2,90%
Duty cycle = 90%
1.2
1.6
2.0
A
VLIM,LX2
VLX2 stuck low for more than 60 ns,
Hiccup mode after 1 detection
–
VVREG
–1.2 V
–
V
Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking).
Ensured by design and characterization, not production tested.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
ELECTRICAL CHARACTERISTICS – LINEAR REGULATOR (LDO) SPECIFICATIONS 1: Valid at 3.5 V 4 < VIN < 36 V,
−40ºC < TA = TJ < 150ºC, unless otherwise specified.
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
4.9
5
5.1
V
1
–
22
µF
4.9
5
5.1
V
1
–
22
µF
V5SNR, V5CAN, and V5P Linear Regulators
V5SNR Accuracy & Load Regulation
V5SNR Output Capacitance 2
V5CAN Accuracy & Load Regulation
V5CAN Output Capacitance 2
VV5,SNR
VV5,CAN
10 mA < IV5,CAN < 200 mA, VVREG = 5.25 V
COUT,V5,CAN
V5P Accuracy & Load Regulation
V5P Output Capacitance 2
10 mA < IV5,SNR < 150 mA, VVREG = 5.25 V
COUT,V5,SNR
VV5P
10 mA < IV5P < 120 mA, VVREG = 5.25 V
COUT,V5P
4.9
5
5.1
V
1.6
2.2
4.1
µF
VV5x,MIN1
VVIN = 5.35 V, VVREG = 5.19 V, VVCP = 9.4 V,
IV5,SNR = 50 mA, IV5,CAN = 200 mA, IV5P =
75 mA, I3V3 = 700 mA (510 mA to VREG)
4.86
4.95
–
V
VV5x,MIN2
VVIN = 4.50 V, VVREG = 4.34 V, VVCP = 8.5 V,
IV5,SNR = 50 mA, IV5,CAN = 200 mA, IV5P =
75 mA, I3V3 = 700 mA (610 mA to VREG)
4.06
4.29
–
V
V5P/ADJ Tracking Ratio
VV5P ÷ VFB,ADJ
6.218
6.250
6.282
–
V5P/ADJ Tracking Accuracy
TRACKADJ
735 mV < VFB, ADJ < 800 mV, TRACK = 1,
IV5P = 10 mA
−0.5
–
+0.5
%
TRACKV5,SNR
4.5 V < VV5,SNR < 5 V, TRACK = 0, IV5P =
IV5,SNR = 75 mA
−25
–
+25
mV
V5PILIM
VV5P = 5 V
−140
−200
–
mA
V5PIFBK
VV5P = 0 V
−10
−
−90
mA
V5 and V5P Minimum Output
Voltage2
V5P Tracking
V5P/V5SNR Tracking Accuracy
V5P Overcurrent Protection
V5P Current Limit 1
V5P Foldback Current
1
V5SNR Overcurrent Protection
V5SNR Current Limit 1
V5SNR,ILIM
VV5,SNR = 5 V
−175
−245
–
mA
V5SNR Foldback Current 1
V5SNR,IFBK
VV5,SNR = 0 V
−35
−70
−105
mA
V5CAN,ILIM
VV5,CAN = 5 V
−230
−325
–
mA
V5CAN,IFBK
VV5,CAN = 0 V
−50
−95
−140
mA
V5CAN Overcurrent Protection
V5CAN Current Limit 1
V5CAN Foldback Current
1
V5P & V5SNR, and V4CAN Startup Timing
V5P Startup Time 2
CV5P ≤ 2.9 µF, Load = 42 Ω ±5% (120 mA)
–
0.26
1.1
ms
2
CV5,SNR ≤ 2.9 µF, Load = 33 Ω ±5% (150 mA)
–
0.24
1
ms
V5CAN Startup Time 2
CV5,CAN ≤ 2.9 µF, Load = 25 Ω ±5% (200 mA)
–
0.22
1
ms
V5SNR Startup Time
1
2
4
Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking).
Ensured by design and characterization, not production tested.
The lowest operating voltage is only valid if the conditions VVIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
ELECTRICAL CHARACTERISTICS – CONTROL INPUTS 1: Valid at 3.5 V 4 < VIN < 36 V, –40ºC < TA = TJ < 150ºC, unless
otherwise specified.
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Ignition Enable (ENBAT) Inputs
ENBAT Thresholds
ENBAT Hysteresis
ENBAT Bias Current 1
ENBAT Pull-Down Resistance
VENBAT,H
VENBAT rising
2.9
3.1
3.5
V
VENBAT,L
VENBAT falling
2.2
2.6
2.9
V
VENBAT,H – VENBAT,L
–
500
–
mV
TJ = 25°C 3, VENBAT = 3.51 V
–
40
65
µA
VENBAT,HYS
IENBAT,BIAS
TJ = 150°C, VENBAT = 3.51 V
–
50
80
µA
RENBAT
VENBAT < 1.2 V
–
650
–
kΩ
VENB,H
VENB rising
–
–
2
V
Logic Enable (ENB) Input
ENB Thresholds
VENB,L
VENB falling
0.8
–
–
V
ENB Bias Current 1
IENB,IN
VENB = 3.3 V
–
–
175
µA
ENB Resistance
RENB
–
60
–
kΩ
EN td,FILT
10
15
20
µs
15
50
100
µs
ENB/ENBAT Filter/Deglitch
Enable Filter/Deglitch Time
ENB/ENBAT Shutdown Delay
LDO Shutdown Delay
td LDO,OFF
Measure tdLDO,OFF from the falling edge of
ENB and ENBAT to the time when all LDOs
begin to decay
TRACK Inputs
TRACK Thresholds
TRACK Bias
Current 1
VTH
VTRACK rising
–
–
2
V
VTL
VTRACK falling
0.8
–
–
V
–
−100
–
µA
–
800
–
mV
–
−100
–
nA
1 MHz PWM operation if open
–
3
–
µs
1 MHz PWM operation if shorted
–
3
–
µs
2
V
IBIASTRK
FSET/SYNC Inputs
FSET/SYNC Pin Voltage
VFSET/SYNC
FSET/SYNC Bias Current
IBIASFSET
FSET/SYNC Open Circuit
(Undercurrent) Detection Time
SYNC,UC
VFSET/
FSET/SYNC Short Circuit
(Overcurrent) Detection Time
SYNC,OC
VFSET/
No external SYNC signal
Sync. High Threshold
SYNCVIH
VSYNC rising
–
–
Sync. Low Threshold
SYNCVIL
VSYNC falling
0.5
–
–
V
Sync. Input Duty Cycle
DCSYNC
–
–
80
%
Sync. Input Pulse Width
twSYNC
200
–
–
ns
Sync. Input Transition Times 2
ttSYNC
–
10
15
ns
VSLEW
–
800
–
mV
SLEW Inputs
SLEW Pin Operating Voltage
SLEW Pin Open Circuit
(Undercurrent) Detection Time
VSLEW,UC
LX1 defaults to 1.5 V/ns if fault
–
3
–
µs
SLEW Pin Short Circuit (Overcurrent)
Detection Time
VSLEW,OC
LX1 defaults to 1.5 V/ns if fault
–
3
–
µs
–
−100
–
nA
SLEW Bias Current 1
1
2
4
ISLEW
Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking).
Ensured by design and characterization, not production tested.
The lowest operating voltage is only valid if the conditions VVIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
ELECTRICAL CHARACTERISTICS – DIAGNOSTIC OUTPUTS 1: Valid at 3.5 V 4 < VIN < 36 V, –40ºC < TA = TJ < 150ºC, un-
less otherwise specified.
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
NPOR OV/UV Protection Thresholds
FBADJ OV Thresholds
FBADJ OV Hysteresis
FBADJ UV Thresholds
FBADJ UV Hysteresis
VFB,ADJ,OV,H
VFB,ADJ rising
825
845
865
V
VFB,ADJ,OV,L
VFB,ADJ falling
–
838
–
V
VFB,ADJ,OV,HYS
VFB,ADJ,OV,H – VFB,ADJ,OV,L
3
7
14
mV
VFB,ADJ,UV,H
VFB,ADJ rising
–
762
–
V
VFB,ADJ,UV,L
VFB,ADJ falling
735
755
775
V
3
7
14
mV
1.6
2
2.4
ms
VFB,ADJ,UV,HYS
VFB,ADJ,UV,H – VFB,ADJ,UV,L
NPOR Turn-On and Turn-Off Delays
NPOR Turn-On Delay
tdNPOR,ON
VVFB,ADJ > VFB,ADJ,UV,H, see Figure 11 for
timing details
NPOR Turn-Off Delay
tdNPOR,OFF
ENB and ENBAT low for t > tdFILT,
see Figure 11 for timing details
–
–
3
µs
ENB or ENBAT high, VVIN ≥ 2.5 V,
INPOR = 4 mA
–
150
400
mV
ENB or ENBAT high, VVIN = 1.5 V,
INPOR = 2 mA
–
–
800
mV
VNPOR = 3.3 V
–
–
2
µA
NPOR Output Voltages
NPOR Output Low Voltage
NPOR Leakage Current 1
VNPOR,L
INPOR,LKG
NPOR and POK5V OV Delay Time
Overvoltage Detection Delay
tdOV
V5P, V5SNR, V5CAN, or FBADJ overvoltage
detection delay time (two independent
timers, NPOR and POK5V)
3.2
4
4.8
ms
tdFILT
Applies to undervoltage of the FBADJ, V5SNR,
V5CAN, and V5P voltages
10
15
20
µs
NPOR and POK5V UV Filtering/Deglitch
UV Filter/Deglitch Times
POK5V OV/UV Protection Thresholds
V5SNR and V5CAN OV Thresholds
V5SNR and V5CAN OV Hysteresis
V5SNR and V5CAN UV Thresholds
V5SNR and V5CAN UV Hysteresis
V5P Output Disconnect Threshold
V5P OV Thresholds
V5P OV Hysteresis
V5P UV Thresholds
V5P UV Hysteresis
1
2
4
VV5x,OV,H
VV5x rising
5.15
5.33
5.50
VV5x,OV,L
VV5x falling
–
5.30
–
VV5x,OV,HYS
V
VV5x,OV,H – VV5x,OV,L
15
30
50
VV5x,UV,H
VV5x rising
–
4.71
–
VV5x,UV,L
VV5x falling
4.50
4.68
4.85
15
30
50
mV
V
VV5x,UV,HYS
VV5x,UV,H – VV5x,UV,L
VV5P,DISC
VV5P rising
–
7.2
–
VV5P,OV,H
VV5P rising
5.15
5.33
5.50
VV5P,OV,L
VV5P falling
–
5.30
–
VV5P,OV,H – VV5P,OV,L
15
30
50
VV5P,OV,HYS
VV5P,UV,H
VV5P rising
–
4.71
–
VVP5,UV,L
VV5P falling
4.50
4.68
4.85
15
30
50
VV5P,UV,HYS
VV5P,UV,H – VV5P,UV,L
mV
V
V
mV
V
mV
Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking).
Ensured by design and characterization, not production tested.
The lowest operating voltage is only valid if the conditions VVIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.
Continued on next page...
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
15
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
ELECTRICAL CHARACTERISTICS – DIAGNOSTIC OUTPUTS (continued) 1: Valid at 3.5 V 4 < VIN < 36 V, –40ºC < TA = TJ
< 150ºC, unless otherwise specified.
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
ENB = 1 or ENBAT = 1,
VVIN ≥ 2.5 V, IPOK5V = 4 mA
–
150
400
mV
ENB = 1 or ENBAT= 1,
VVIN = 1.5 V, IPOK5V = 2 mA
–
–
800
mV
IPOK5V,LKG
VPOK5V = 3.3 V
–
–
2
µA
VREGOV,H
VVREG rising, LX1 PWM disabled
5.70
5.95
6.20
V
VREGOV,L
VVREG falling, LX1 PWM enabled
–
5.85
–
V
POK5V Output Voltages
POK5V Output Voltage
POK5V Leakage Current
VPOK5V,L
VREG, VCP, and BG Thresholds
VREG OV Thresholds
VREG OV Hysteresis
VREG UV Thresholds
VREGOV, HYS
VREGOV,H – VREGOV,L
VREGUV,H
VVREG rising, triggers rise of SS2
VREGUV,L
VVREG falling
–
100
–
mV
4.14
4.38
4.62
V
–
4.28
–
V
VREG UV Hysteresis
VREGUV, HYS
VREGUV,H – VREGUV,L
–
100
–
mV
VCP OV Thresholds
VCPOV,H
VVCP rising, latches all regulators off
11
12.5
14
V
VCPUV,H
VVCP rising, PWM enabled
2.95
3.15
3.35
V
VCPUV,L
VVCP falling, PWM disabled
–
2.8
–
V
VCP UV Thresholds
VCP UV Hysteresis
VCPUV,HYS
–
350
–
mV
BGVREF or BGFAULT rising
1.00
1.05
1.10
V
VENBATS,H
VENBATx rising
2.9
3.3
3.5
V
BGREF and BGFAULT UV Thresholds 2
BGxUV
VCPUV,H – VCPUV,L
Ignition Status (ENBATS) Specifications
ENBATS Thresholds
ENBATS Output Voltage
ENBATS Leakage Current 1
VENBATS,L
VENBATx falling
2.2
2.6
2.9
V
VOENBATS, LO
IENBATS = 4 mA
–
–
400
mV
IENBATS
VENBATS = 3.3 V
–
–
2
µA
Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking).
2 Ensured by design and characterization, not production tested.
4 The lowest operating voltage is only valid if the conditions V
VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.
1
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
ELECTRICAL CHARACTERISTICS – WINDOW WATCHDOG TIMER (WWDT) 1: Valid at 3.5 V 4 < VIN < 36 V, –40ºC < TA =
TJ < 150ºC, unless otherwise specified.
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
WD Enable\ Input (WDENn)
WDENn Voltage Thresholds
WDENn Input Resistance
WDENn,LO
VWDENn falling, WDT enabled
0.8
–
–
V
WDENn,HI
VWDENn rising, WDT disabled
–
–
2
V
–
60
–
kΩ
RWD,ENn
WDIN Voltage Thresholds and Current
WDIN Input Voltage Thresholds
WDIN Input Current 1
WDIN,LO
VWD,IN falling, WDADJ pulled low by RADJ
WDIN,HI
VWD,IN rising, WDADJ charging
WDI,IN
VWD,IN = 5 V
0.8
–
–
V
–
–
2
V
−10
±1
10
µA
WDOUT Specifications
WDOUT Output Voltage
WDOUT Leakage Current 1
VWD,OUT,LO
IWD,OUT = 4 mA
–
–
400
mV
IWD,OUT
VWD,OUT = 3.3 V
–
–
2
µA
Watchdog (WD) Oscillator, Pulse Width Selection, and Start Delay
WD Oscillator Tolerance
WD Startup Delay
WDIN Pulse-Width Programming
WD First Edge Timeout Delay
WD CLKIN Non-Activity Timeout
WDOSC,TOL
Typical value is at 25°C (2)
WDSTART,DLY Gated by WDENn = 0 × NPOR=
WDIN,PW
WDEDGE,TO
WDACT,TO
−5
±2.5
+5
%
1.6
2
2.4
ms
RADJ = 22.1 kΩ (WDOSC = 1 MHz)
0.95
1
1.05
ms
RADJ = 44.2 kΩ (WDOSC = 500 kHz)
1.9
2
2.1
ms
RADJ = 22.1 kΩ (WDOSC = 1 MHz)
4.7
5
5.3
ms
RADJ = 44.2 kΩ (WDOSC = 500 kHz)
9.4
10
10.6
ms
RADJ = 22.1 kΩ (WDOSC = 1 MHz)
15.2
16
16.8
ms
RADJ = 44.2 kΩ (WDOSC = 500 kHz)
30.4
32
33.6
ms
–
8
–
–
Watchdog Clock Input (WDCLK,IN)
Input Clock Divider
WDCLK,IN Voltage Thresholds
WDCLK,DIV
WDCLK,IN,LO
VWD,CLK,IN falling
0.8
–
–
V
WDCLK,IN,HI
VWD,CLK,IN rising
–
–
2
V
WDTOL pin connected to GND
−8
–
+8
%
WDTOL pin floating
−13
–
+13
%
WDTOL pin connected to VCC
−18
–
+18
%
Watchdog Window Tolerance Selection (WDWIN,TOL)
WD Window Tolerance Settings
WDWIN,TOL
Watchdog Pulse Width (PW) Error Counting
Counter Increment if PW Fault
WDINC
–
+10
–
counts
Counter Decrement if PW is OK
WDDEC
–
‒2
–
counts
WDCOUNT
–
160
–
counts
Counts to Latch WDFAULT Low
Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking).
2 Ensured by design and characterization, not production tested.
4 The lowest operating voltage is only valid if the conditions V
VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.
1
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
17
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
FUNCTIONAL DESCRIPTION
Overview
The pre-regulator provides protection and diagnostic functions.
The A4411 is a power management IC designed for automotive
applications. It contains a pre-regulator plus four DC postregulators to create the voltages necessary for typical automotive
applications, such as electrical power steering and automatic
transmission control.
1.
2.
3.
4.
5.
6.
The pre-regulator can be configured as a buck or buck-boost
regulator. Buck-boost is required for applications that need to
work at extremely low battery voltages. This pre-regulator generates a fixed 5.35 V and can deliver up to 1 A to power the internal
or external post-regulators. These post-regulators generate the
various voltage levels for the end system.
Overvoltage protection
High voltage rating for load dump
Switch-node-to-ground short-circuit protection
Open freewheeling diode protection
Pulse-by-pulse current limit
Hiccup mode short-circuit protection (refere to Figure 2)
The A4411 includes four internal post-regulators: three linear
regulators and one adjustable output synchronous buck regulator.
Buck-Boost Pre-Regulator (VREG)
The pre-regulator incorporates an internal high-side buck switch
and a boost switch gate driver. An external freewheeling Schottky
diode and an LC filter are required to complete the buck converter. By adding a MOSFET and a Schottky diode, the boost
configuration can maintain all outputs with input voltages as low
as 3.5 V. Typical boost performance is shown in Figure 1. The
A4411 includes a compensation pin (COMP1) and a soft-start pin
(SS1) for the pre-regulator.
Figure 2: Pre-Regulator Hiccup Mode Operation when
VREG is Shorted to GND and CSS1 = 22nF
CH1 = VREG, CH2 = COMP1, CH3 = SS1, CH4 = IL1, 1 ms/DIV
For the pre-regulator, hiccup mode is enabled when PWM
switching begins. If VVREG is less than 1.3 V, the number of
overcurrent pulses (OCP) is limited to only 30. If VVREG is
greater than 1.3 V, the number of OCP pulses is increased to 120
to accommodate the possibility of starting into a relatively high
output capacitance.
Adjustable Synchronous Buck Regulator
(ADJ)
Figure 1: Buck-Boost Performance with Relatively Fast
VVIN Transition Times for a Representative Start/Stop
Waveform
VVIN(TYP) = 12 V, VVIN(MIN) = 4 V, 20 ms/DIV
The A4411 integrates the high-side and low-side MOSFETs
necessary for implementing an adjustable output 750 mADC /
1 APEAK synchronous buck regulator. The synchronous buck is
powered by the 5.35 V pre-regulators output. An external LC
filter is required to complete the synchronous buck regulator.
The synchronous bucks output voltage is adjusted by a connecting a resistor divider from the bucks output to the feedback pin
(FBADJ). The A4411 includes a compensation pin (COMP2) and
a soft-start pin (SS2) for the synchronous buck.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
18
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
Protection and safety functions provided by the synchronous
buck are:
Undervoltage detection
Overvoltage detection
Switch-node-to-ground short-circuit protection
Pulse-by-pulse current limit
Hiccup mode short-circuit protection (shown in Figure 3)
100%
Vx
1.
2.
3.
4.
5.
2. Current limit with foldback short-circuit protection (see
Figure 4)
The protected 5 V regulator (V5P) includes protection against
accidental short-circuit to the battery voltage. This makes this
output most suitable for powering remote sensors or circuitry via
a wiring harness where short-to-battery is possible.
Ix
IFBKmin IFBKtyp
Figure 3: Synchronous Buck Hiccup Mode Operation
when VOUT is Shorted to GND and CSS2 = 22 nF
CH1=VOUT, CH2=COMP1, CH3=SS1, CH4=IL1, 500 µs/DIV
For the synchronous buck, hiccup mode is enabled when VSS2 =
VHIC2,EN (1.2 VTYP). If VFB,ADJ is less than 300 mVTYP the number of over current pulses (OCP) is limited to only 30. If VFB,ADJ
is greater than 300 mVTYP the number of OCP pulses is increased
to 120 to accommodate the possibility of starting into a relatively
high output capacitance.
All linear regulators provide the following protection features:
1. Undervoltage and overvoltage detection
ILIMtyp
Figure 4: LDO Foldback Characteristics
Tracking Input (TRACK)
The V5P LDO is a tracking regulator. It can be set to use either
V5 or VFB,ADJ as its reference by setting the TRACK input pin to
a logic low or high. If the TRACK input is left unconnected an
internal current source will set the TRACK pin to a logic high.
Low-Dropout Linear Regulators (LDOs)
The A4411 has three low-dropout linear regulators (LDOs), one
5 V / 200 mAMAX (V5CAN), one 5 V / 150 mAMAX (V5SNR), and
one high-voltage protected 5 V / 120 mAMAX (V5P). The switching pre-regulator efficiently regulates the battery voltage to an
intermediate value to power the LDOs. This pre-regulator topology reduces LDO power dissipation and junction temperature.
ILIMmin
5V
TRACKING
LDO
VREG
REFERENCE
100 µA
TRACK
V5P
SEL
2:1
MUX
0
1
V5 VFB,ADJ
Figure 5: The V5P reference is set by the TRACK input.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
19
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
A4411
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
Pulse-Width Window Watchdog (PWWD)
The A4411 pulse-width window watchdog circuit monitors an
external clock applied to the WDIN pin. This clock should be
generated by the primary microcontroller or DSP. The A4411
watchdog measures the time between two clock edges, either
rising or falling. So the watchdog effectively measures both the
“high” and “low” pulse widths, as shown in Figure 16.
If an incorrect pulse width is detected, the watchdog increments
its fault counter by 10. If a correct pulse width is detected, the
watchdog decrements its fault counter by 2. If the watchdog’s
fault counter exceeds 160, then the WD fault latch will be set and
the WDOUT pin will transition low. This fault condition is shown
in Figure 16.
The watchdog and its fault latch will be reset if:
1.
2.
3.
4.
WDADJ
RADJ
WDENn
WDIN
WDtol
DIV by
8
WDOSC
±5%
NPOR
VCC_UV
BG1_UV
WDADJ = 0 V
500 kHz – 1 MHz
NPOR
WDRESET
RISING
EDGE
DELAY
>WDMASTER_CLK
RESET
WDFAULT
EDGE DETECT
RWD,ENn
±8% / ±13% / ±17%
During normal operation, if clock activity is no longer detected
at WDIN for at least WDACT,TO , the A4411 will set the WD latch
and WDOUT will transition low. WDACT,TO varies with the value
of RADJ as shown in the Electrical Characteristics table. The “loss
of clock activity” condition is shown as (2) in Figure 17.
Table 1: WDTOL Pin Voltage Determines the WDIN Pulse
Width Tolerance or “Window”
PULSE WIDTH
WINDOW WATCHDOG
WDACTIVE
After startup, if no clock edges are detected at WDIN for at least
WDSTART,DLY + WDEDGE,TO , the A4411 will set the WD latch
and WDOUT will transition low. WDEDGE,TO varies with the
value of RADJ as shown in the Electrical Characteristics table.
The “edge timeout” condition is shown as (1) in Figure 17.
The nominal WDIN pulse width is set by the value of RADJ.
However, the pulse widths generated by a microcontroller or DSP
depend on many factors and will have some pulse-to-pulse variation. The A4411 accommodates pulse-width variations by allowing the designer to select a “window” of allowable variations. The
size of the window is chosen based on the voltage at the WDTOL
pin, as shown in Table 1.
The WDENn pin is set high (i.e. WD is disabled), or
NPOR goes low (i.e. ENB and ENBAT are low), or
The internal rail, VCC, is low (i.e. VVIN is removed), or
The bandgap, BG1, transitions low.
WDCLK,IN
This startup delay allows the microcontroller or DSP to complete
its initialization routines before delivering a clock to the WDIN
pin. The WDSTART,DLY time is shown in Figure 16.
RESET
DOMINANT
S Q
WDOUT
R
WD
FAULT
LATCH
Figure 6: Pulse-Width Window Watchdog
The expected pulse width (PW) is programed by connecting a
resistor (RADJ) from the WDADJ pin to ground. The relationship
between RADJ and PW is:
RADJ = 22.1 × PW
where PW is in ms and RADJ is the required external resistor
value in kΩ. The typical range for PW is 1 to 2 ms.
The watchdog will be enabled if the following two conditions are
satisfied:
1. The WDENn pin is a logic low, and
2. NPOR transitions high and remains high for at least
WDSTART,DLY (2 msTYP). This requires all regulators to be
above their undervoltage thresholds.
WDTOL (V)
Allowed WDIN Pulse-Width Tolerance
Low (0 V)
±8%
Float (Open)
±13%
High (VCC)
±18%
The watchdog performs its calculations based on an internally
generated clock. The internal clock typically has an accuracy of
±2.5%, but may vary as much as ±5% due to IC process shifts
and temperature variations. Variations in this clock result in a
shift of the “OK Region” (i.e. the expected pulse width) at WDIN,
shown as a green area in Figure 18.
If the internal clock does not provide enough pulse-width measurement accuracy, the A4411 allows the designer to accept a
high-precision clock at the WDCLK,IN pin. If the WDCLK,IN pin is
used, then the WDADJ pin must be grounded. Figure 7 shows an
example where a crystal and a tiny 6-pin driver (74LVC1GX04
by TI or NXP) are used to generate an external clock. The
external clock should be in the 4 to 8 MHz frequency range for
corresponding WDIN pulse widths of 1 to 2 ms.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
20
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
VREG
XTAL
DRIVER
EXT WD CLK
4 MHz – 8 MHz
WDCLK,IN
DIV by 0.5 MHz – 1 MHz
8
WDADJ
WDOSC
±5%
PULSE WIDTH
(PW) WINDOW
WATCHDOG
74LVC1GX04
>WDMASTER_CLK
Ground WDADJ if
using WDCLK,IN
WDADJ = 0 V
0.5 MHz → 1 ms PW
1.0 MHz → 2 ms PW
Figure 7: Applying an External Clock
Applying an external clock to the WDCLK,IN pin allows extremely
accurate pulse-width measurements.
Dual Bandgaps (BGVREF, BGFAULT)
Dual bandgaps, or references, are implemented within the
A4411. One bandgap (BGVREF) is dedicated solely to closed-loop
control of the output voltages. The second bandgap (BGFAULT)
is employed for fault monitoring functions. Having redundant
bandgaps improves reliability of the A4411.
If the reference bandgap is out of specification (BGVREF), then
the output voltages will be out of specification and the monitoring bandgap will report a fault condition by setting NPOR and/or
POK5V low.
If the monitoring bandgap is out of specification (BGFAULT), then
the outputs will remain in regulation, but the monitoring circuits
will report a fault condition by setting NPOR and/or POK5V low.
The reference and monitoring bandgap circuits include two
smaller secondary bandgaps that are used to detect undervoltage
of the main bandgaps during power-up.
Adjustable Frequency and Synchronization
(FSET/SYNC)
The PWM switching frequency of the A4411 is adjustable from
250 kHz to 2.4 MHz. Connecting a resistor from the FSET/
SYNC pin to ground sets the switching frequency. An FSET
resistor with ±1% tolerance is recommended. The FSET resistor
can be calculated using the following equation:
RFSET =
(
fOSC
12724
The PWM frequency of the A4411 may be increased or decreased
by applying a clock to the FSET/SYNC pin. The clock must satisfy the voltage thresholds and timing requirements shown in the
Electrical Characteristics table.
-1.175
)
where RFSET is in kΩ and fOSC is the desired oscillator (PWM)
frequency in kHz.
A graph of switching frequency versus FSET resistor values is
shown in Figure 8.
2250
Oscillator Frequency (kHz)
A4411
2000
1750
1500
1250
1000
750
500
250
5
10
15
20
25
30
35
40
45
50
55
60
RFSET (kΩ)
Figure 8: Switching Frequency vs. FSET Resistor
Values
Frequency Dithering and LX1 Slew Rate Control
The A4411 includes two innovative techniques to help reduce
EMI/EMC for demanding automotive applications.
First, the A4411 performs pseudo-random dithering of the PWM
frequency. Dithering the PWM frequency spreads the energy
above and below the base frequency set by RFSET. A typical fixedfrequency PWM regulator will create distinct “spikes” of energy
at fOSC, and at higher frequency multiples of fOSC. Conversely,
the A4411 spreads the spectrum around fOSC , thus creating a
lower magnitude at any comparable frequency. Frequency dithering is disabled if SYNC is used or VVIN drops below approximately 8.3 V.
Second, the A4411 includes a pin to adjust the turn-on slew rate
of the LX1 pin by simply changing the value of the resistor from
the SLEW pin to ground. Slower rise times of LX1 reduce ringing and high-frequency harmonics of the regulator. The rise time
may be adjusted to be quite long and will increase thermal dissipation of the pre-regulator if set too slow. Typical values of rise
time versus RSLEW are listed in Table 2.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
21
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
A4411
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
LX1 Rise Time (ns)
8.66
7
44.2
11
100
20
Enable Inputs (ENB, ENBAT)
Two enable pins are available on the A4411. A logic high on
either of these pins enables the A4411. One enable (ENB) is logic
level compatible for microcontroller or DSP control. The other
input (ENBAT) must be connected to the high-voltage ignition
(IGN) or accessory (ACC) switch through a relatively low-value
series resistance, 2 to 3.6 kΩ. For transient suppression, it is
strongly recommended that a 0.22 to 0.47 µF capacitor be placed
after the series resistance to form a low-pass filter to the ENBAT
pin as shown in the Applications Schematic.
Bias Supply (VCC)
The bias supply (VCC) is generated by an internal linear regulator.
This supply is the first rail to start up. Most of the internal control
circuitry is powered by this supply. The bias supply includes
some unique features to ensure reliable operation of the A4411.
These features include:
1.
2.
3.
4.
Input voltage (VVIN) undervoltage lockout
Undervoltage detection
Short-to-ground protection
Operation from either VVIN or VVREG, whichever is higher
Charge Pump (VCP, CP1, CP2)
A charge pump provides the voltage necessary to drive the highside n-channel MOSFETs in the pre-regulator and the linear
regulators.
Two external capacitors are required for charge pump operation. During the first half of the charge pump cycle, the flying
capacitor between pins CP1 and CP2 is charged from either VVIN
or VVREG, whichever is highest. During the second half of the
charge pump cycle, the voltage on the flying capacitor charges
the VCP capacitor. For most conditions, the VVCP minus VVIN
voltage is regulated to approximately 6.5 V.
The charge pump can provide enough current to operate the
pre-regulator and the LDOs at 2.2 MHz (full load) and 125°C
CP2
0.22 µF
Required if VREG
is fully loaded and
VVIN < 6.0 V
CP2
RSLEW (kΩ)
ambient, provided VVIN is greater than 6 V. Optional components
D3, D4, and CP3 (refer to Figure 9) must be included if VVIN
drops below 6 V. Diode D3 should be a silicon diode rated for at
least 200 mA / 50 V with less than 50 µA of leakage current when
VR = 13 V and TA = 125ºC. Diode D4 should be a 1 A Schottky
diode with a very low forward voltage (VF) rated to withstand at
least 30 V.
CP1
Table 2: Typical LX1 Rising Slew Rate vs. RSLEW
D3
BAS16J
D4
MSS1P5
CP3
0.1 µF/50 V
LX1
LX1
LG
Figure 9: Charge pump enhancement components D3,
D4, and CP3 are required if VVIN < 6 V.
The charge pump incorporates some protection features:
1. Undervoltage lockout of PWM switching
2. Overvoltage “latched” shutdown of the A4411
Startup and Shutdown Sequences
The startup and shutdown sequences of the A4411 are fixed. If
no faults exist and ENBAT or ENB transition high, the A4411
will perform its startup routine. If ENBAT and ENB are low for
at least ENtd,FILT + tdLDO, OFF (typically 65 µs), the A4411 will
enter a shutdown sequence. The startup and shutdown sequences
are summarized in Table 3 and shown in a timing diagram in
Figure 11.
Fault Reporting (NPOR, POK5V)
The A4411 includes two open-drain outputs for error reporting.
The NPOR comparator monitors the feedback pin of the synchronous buck (VFB,ADJ) for under- and overvoltage, as shown
in Figure 10, Figure 11, and Figure 14. The POK5V comparators
monitor the V5CAN, V5SNR, and V5P pins for under- and overvoltage, as shown in Figure 10, Figure 11, and Figure 15.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
22
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
A4411
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
The NPOR circuit includes a 2 ms delay after the synchronous
bucks output has risen above its undervoltage threshold. This delay
allows the microcontroller or DSP plenty of time to power-up
and complete its initialization routines. There is minimal NPOR
delay if the synchronous buck’s output falls below its undervoltage
threshold. The NPOR pin incorporates a 4 ms delay if the synchronous buck’s output exceeds its overvoltage threshold.
OV/UV DETECT
& DELAYS
NPOR
WDFAULT
WDSTART
TSD
CLK1MHz
RST
REF
ON/OFF
There are no significant delays on the POK5V output after
V5CAN, V5SNR, and V5P have risen above or fallen below their
undervoltage thresholds. Similar to the NPOR pin, the POK5V
pin incorporates a 4 ms delay if any of the 5 V outputs exceed its
overvoltage threshold.
OV/UV DETECT
& DELAYS
POK5V
The V5P monitor is unique: if V5P is accidently connected to the
battery voltage, then POK5V will bypass the normal 4 ms overvoltage delay and set itself low immediately.
FBADJ
DEGLITCH
tdFILT
V5SNR
V5CAN
V5P
V5PDISC
REF
BGFAULT
DEGLITCH
tdFILT
Figure 10: Fault Reporting Circuit
The fault modes and their effects on NPOR and POK5V are covered in detail in Table 4.
Table 3: Startup and Shutdown Logic (signal names consistent with Functional Block Diagram)
Regulator Control Bits
(0 = OFF, 1 = ON)
A4411 Status Signals
A4411
MODE
ON/OFF
MPOR
VREG UV
SS1 LOW
ADJ UV
SS2 LOW
3×LDO UV
VREG ON
ADJ ON
LDOs ON
X
1
1
1
1
1
1
0
0
0
RESET
0
0
1
1
1
1
1
0
0
0
OFF
1
0
1
1
1
1
1
1
0
0
STARTUP
1
0
0
0
1
1
1
1
1
0
↓
1
0
0
0
0
0
1
1
1
1
↓
1
0
0
0
0
0
0
1
1
1
RUN
0
0
0
0
0
0
0
1
1
1
DEGLITCH
+ DELAY
0
0
0
0
0
0
0
1
1
0
SHUTTING
DOWN
0
0
0
0
0
X
1
1
0
0
↓
0
0
0
X
1
1
1
0
0
0
↓
0
0
1
1
1
1
1
0
0
0
OFF
X = DON’T CARE
ON/OFF = ENBAT + ENB
3×LDO UV = V5SNR_UV + V5CAN_UV + V5P_UV
MPOR = VIN_UV + VCC_UV + VCP_UV + BG1_UV + BG2_UV + TSD +
VCP_OV (latched) + D1MISSING (latched) + ILIM,LX1 (latched)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
23
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
Table 4: Summary of Fault Mode Operation
FAULT TYPE and
CONDITION
A4411 RESPONSE TO FAULT
NPOR
VFB,ADJ
POK5V
V5SNR/
V5CAN/V5P
LATCHED
FAULT?
RESET METHOD
V5P short-to-VBAT
POK5V goes low when a V5P disconnect occurs.
The other two 5 V LDOs remain active.
Not affected
Low if V5P
disconnect
occurs
NO
Check for shortcircuits on V5P
Either V5SNR, V5CAN, or V5P are
overvoltage (OV)
If OV condition persists for more than tdOV then set
POK5V low. The other two 5 V LDOs must remain
active.
Not affected
Low if
t > tdOV
NO
Check for shortcircuits on V5SNR,
V5CAN, V5P
FBADJ overvoltage (OV)
If OV condition persists for more than tdOV then set
NPOR low. All 5 V LDOs must remain active.
Low if
t > tdOV
Not
affected
NO
Check for shortcircuits on FBADJ
Either V5SNR, V5CAN, or V5P are
undervoltage (UV)
Closed-loop control will try to raise the LDOs voltage
but may be constrained by the foldback current limit.
Note: LDO(s) may be soft-starting.
Not affected
Low
NO
Decrease the
load or wait for
SS to finish
FBADJ undervoltage (UV)
Closed-loop control will try to raise the voltage but
may be constrained by the pulse-by-pulse current
limit. The ADJ regulator may need to enter hiccup
mode. Also, the ADJ regulator may be simply softstarting.
Low
Not
affected
NO
Decrease the
load or wait for
SS to finish
Either V5SNR, V5CAN, or V5P are
overcurrent (OC)
Foldback current limit will reduce the output voltage
of the overloaded LDO. The other 5 V LDOs must
operate normally.
Not affected
Low if any
5 V output
voltage
droops
NO
Decrease the
load
FBADJ pin open circuit after
soft-start is finished. Soft-start
finished if SS1 and POK5V are
high.
A small internal current sink pulls the voltage at
the FBADJ pin high and mimics an ADJ regulator
overvoltage condition.
Low
because
VFB,ADJ >
VFB,ADJ,OV,H
Not
affected
NO
Connect the
FBADJ pin
FBADJ pin open circuit before
soft-start is finished. Soft-start
not finished if SS1 is high and
POK5V is low.
A small internal current sink pulls the voltage at
the FBADJ pin high and mimics an ADJ regulator
overvoltage condition.
Low
because
VFB,ADJ >
VFB,ADJ,OV,H
Low, Stuck
in soft-start
sequence
N/A
Stuck in
soft-start
sequence
Connect the
FBADJ pin
FBADJ regulator overcurrent (i.e.
hard short-to-ground) VSS2 <
VHIC2,EN, VFB,ADJ < 300 mV
Continue to PWM but turn off LX2 when the highside MOSFET current exceeds ILIM2.
Low
Not
affected
NO
Remove the
short-circuit
FBADJ regulator overcurrent (i.e.
hard short-to-ground) VSS2 >
VHIC2,EN, VFB,ADJ < 300 mV
Enters hiccup mode after 30 OCP faults.
Low
Not
affected
NO
Decrease the
load
FBADJ regulator overcurrent (i.e.
soft short-to-ground) VSS2 >
VHIC2,EN, VFB,ADJ > 300 mV
Enters hiccup mode after 120 OCP faults.
Low if
VFB,ADJ <
VFB,ADJ,UV,L
Not
affected
NO
Decrease the
load
VREG pin open circuit
VVREG will decay to 0 V and LX1 will switch at
max. duty cycle. The voltage on the VREG output
capacitors will be very close to VIN/VBAT.
Low if ADJ
output
voltage
droops
Low if any
5 V output
voltage
droops
NO
Connect the
VREG pin
VREG overcurrent (i.e. hard
short-to-ground) VVREG < 1.3 V,
VCOMP1 = EA1VO(MAX)
Enters hiccup mode after 30 OCP faults.
Low
Low
NO
Decrease the
load
Enters hiccup mode after 120 OCP faults.
Low if ADJ
output
voltage
droops
Low if any
5 V output
voltage
droops
NO
Decrease the
load
VREG overcurrent (i.e. soft
short-to-ground) VVREG > 1.3 V,
VCOMP1 = EA1VO(MAX)
Continued on next page...
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
24
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
Table 4: Summary of Fault Mode Operation (continued)
FAULT TYPE and
CONDITION
A4411 RESPONSE TO FAULT
NPOR
VFB,ADJ
POK5V
V5SNR/
V5CAN/V5P
LATCHED
FAULT?
RESET METHOD
VREG overvoltage (OV) VVREG >
VREGOV,HI
Control loop will temporarily stop PWM switching of
LX1. LX1 will resume switching when VVREG returns
to its normal range.
Low if ADJ
output
voltage
droops
Low if any
5 V output
voltage
droops
NO
None
VREG asynchronous diode (D1)
missing
Results in a Master Power-On Reset (MPOR) after
1 detection. All regulators are shut off.
Low if ADJ
output
voltage
droops
Low if any
5 V output
voltage
droops
YES
Place D1 then
cycle EN or VIN
Asynchronous diode (D1) shortcircuited or LX1 shorted to
ground
Results in an MPOR after 1 detection of the highside MOSFET current exceeding ILIM,LX1, so all
regulators are shut off.
Low if ADJ
output
voltage
droops
Low if any
5 V output
voltage
droops
YES
Remove the short
then cycle EN or
VIN
LX2 shorted to ground
If LX2 is less than VVREG ‒ 1.2 V after the internal
blanking time (~60 ns), the high-side FET will be
shut off.
Low if ADJ
output
voltage
droops
Not
affected
NO
Remove the short
Slew pin open circuit (SLEW_OV)
Results in a “default” Slew Rate of 1.5 V/ns for LX1
Operates
normally
Operates
normally
NO
Place the slew
rate resistor
Slew pin shorted to ground
(SLEW_UV)
Results in a “default” Slew Rate of 1.5 V/ns for for
LX1
Operates
normally
Operates
normally
NO
Place the slew
rate resistor
FSET/SYNC pin open circuit
(FSET/SYNC_OV)
Results in “default” PWM frequency of 1 MHz
Operates
normally
Operates
normally
NO
Connect the
FSET/SYNC pin
FSET/SYNC pin shorted to
ground (FSET/SYNC_UV)
Results in “default” PWM frequency of 1 MHz
Operates
normally
Operates
normally
NO
Remove the
short-circuit
Charge pump (VCP) overvoltage
(OV)
Results in an MPOR, so all regulators are off
Low
Low
YES
Check VCP/CP1/
CP2, then cycle
EN or VIN
Charge pump (VCP)
undervoltage (UV)
Results in an MPOR, so all regulators are off
Low
Low
NO
Check VCP/CP1/
CP2 components
CP1 or CP2 pin open circuit
Results in VCP_UV and an MPOR, so all regulators
are off
Low
Low
NO
Connect CP1 or
CP2 pins
CP1 pin shorted to ground
Results in VCP_UV and an MPOR, so all regulators
are off
Low
Low
NO
Remove the
short-circuit
CP2 pin shorted to ground
Results in high current from the charge pump and
(intentional) fusing of an internal trace. Also results
in MPOR so all regulators are off.
Low
Low
N/A
Remove shortcircuit, replace
the A4411
BGVREF or BGFAULT undervoltage
(UV)
Results in an MPOR, so all regulators are off
Low
Low
NO
Raise VIN or wait
for BGs to power
up
BGVREF or BGFAULT overvoltage
(OV)
If BGVREF is too high, all regulators will appear to be
OV (because BGFAULT is good).
If BGFAULT is too high, all regulators will appear to be
UV (because BGVREF is good)
Low
Low
N/A
Replace the
A4411
VCC undervoltage or pin shorted
to ground
Results in an MPOR, so all regulators are off
Low
Low
NO
Raise VIN or
remove short at
VCC pin
Thermal shutdown (TSD)
Results in an MPOR, so all regulators are off
Low
Low
NO
Let the A4411
cool down
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
25
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
TIMING DIAGRAMS
(Not to Scale)
13.5 V
VIN
SHUTDOWN SEQUENCE MUST FINISH
BEFORE RESTART IS ACKNOWLEDGED
ENB × ENBAT LOW
ENB + ENBAT HIGH
ON/OFF
ENtd,FILT
t < ENtd,FILT
tdLDO,OFF
VSS1OFFS
SS1
PWM1OFFS
COMP1
fOSC /2
fOSC
LX1
tSS1
5.35 V
VVREG,UV,H
tSS1,DLY
VREG
VSS2OFFS
SS2
PWM2OFFS
COMP2
fOSC
LX2
tSS2
V1V25,UV,H
tSS2,DLY
t > tdFILT
FBADJ
VV5,SNR,UV,H
VV5,SNR,UV,L
t > tdFILT
t > tdFILT
V5SNR
VV5,CAN,UV,H
VV5,CSAN,UV,L
VV5P,UV,H
POK5V
NPOR
WDSTART
V5P < VV5P,UV,L +
V5SNR < VV5,SNR, UV, L +
V5CAN < VV5,CAN,UV,L
t > tdFILT
V5CAN
V5P
VFB,ADJ × V5P ×
V5SNR × V5CAN
are UV
NOTE: SS1 and POK5V are both HIGH, so this
glitch does not put the LDOs back into SS mode.
If VFBD,ADJ is very low, the ADJ regulator may need
to enter hiccup mode without resetting the LDOs.
VV5P,UV,L
V5P < VV5P,UV,L +
V5SNR < VV5,SNR, UV, L +
V5CAN < VV5,CAN,UV,L
V5P > VV5P,UV,H ×
V5SNR > VV5,SNR,UV,H ×
V5CAN > VV5,CAN,UV,H
FBADJ > VVFB,ADJ,UV,H
tdFILT
tdNPOR,ON
WDSTART,DLY
tdNPOR,OFF
tdFILT
ON/OFF↓ forces NPOR LOW
WDSTART,DLY
NPOR↓ forces WDSTART LOW
NPOR↓ forces WDSTART LOW
Figure 11: Startup and Shutdown by ENBAT or ENB (Also shows “glitch” reactions)
× is for “and”, + is for “or”
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
26
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
VIN PIN: ~5.6 V @ 25ºC
13.5 V
VVIN > VIN,STOP
VIN
ON/OFF
SS1
COMP1
100% Duty Cycle
fOSC
fOSC
LX1
5.35 V
~5.15 V @ 25ºC
VREG
SS2
COMP2
fOSC
LX2
VFB,ADJ,UV,H
VFB,ADJ,UV,L
FBADJ
VV5,SNR,UV,H
VV5,SNR,UV,L
V5SNR
VV5,CAN,UV,H
VV5,CAN,UV,L
V5CAN
VV5P,UV,H
VV5P,UV,L
V5P
POK5V
NPOR
WDSTART
V5P < VV5P,UV,H ×
V5SNR < VV5,SNR,UV,H ×
V5CAN < VV5,CAN,UV,H
V5P < VV5P,UV,L +
V5SNR < VV5,SNR,UV,L +
V5CAN < VV5,CAN,UV,L
tdFILT
tdFILT
tdFILT
NPOR↓ forces WDSTART LOW
tdNPOR,ON
WDSTART,DLY
Figure 12: Input Voltage (VIN) Undervoltage, VVIN > VINSTOP
× is for “and”, + is for “or”
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
27
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
13.5 V
~5.6 V @ 25ºC
VVIN < VIN,STOP
VIN
MPOR
ON/OFF
Discharged by RPDSS1
SS1
VVSS1 < VVSS1,RST × VVSS2 < VVSS2,RST
VSS1OFFS
PWM1OFFS
COMP1
100% Duty Cycle
fOSC
fOSC
LX1
~5.15 V @ 25ºC
VREG
VVSS2 < VVSS2,RST
Discharged by RPDSS2
VSS2OFFS
SS2
PWM2OFFS
COMP2
fOSC
fOSC
LX2
VFB,ADJ,UV,H
VFB,ADJ,UV,L
FBADJ
VV5,SNR,UV,H
VV5,SNR,UV,L
V5SNR
VV5,CAN,UV,H
VV5,CAN,UV,L
V5CAN
VV5P,UV,H
VV5P,UV,L
V5P
POK5V
NPOR
WDSTART
V5P > VV5P,UV,H ×
V5SNR > VV5,SNR,UV,L ×
V5CAN > VV5,CAN,UV,L
V5P > VV5P,UV,L +
V5SNR > VV5,SNR,UV,L +
V5CAN > VV5,CAN,UV,L +
tdFILT
tdFILT
MPOR↑ forces NPOR LOW
NPOR↓ forces WDSTART LOW
tdNPOR,ON
WDSTART,DLY
Figure 13: Input Voltage (VIN) Undervoltage, VVIN < VINSTOP
× is for “and”, + is for “or”
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
28
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
PWM1OFFS
COMP1
fOSC
fOSC
LX1
VREG
SS2
PWM2OFFS
COMP2
fOSC
fOSC
LX2
VFB,ADJ,OV,H
VADJ,OV,H
VFB,ADJ,OV,L
t < tdOV
V3V3,UV,L
FBADJ
t < tdFILT
t > tdOV
POK5V
NPOR
ADJ OV forces NPOR LOW after tdOV
WDSTART
NPOR↓ forces WDSTART LOW
tdNPOR,ON
WDSTART,DLY
Figure 14: VREG and FBADJ Overvoltage Operation
× is for “and”, + is for “or”
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
29
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
VV5,SNR,OV,H
V5SNR
V5SNR
VV5,CAN,OV,H
V5CAN
V5P output disconnect
FET opens, so internal
“intermediate” node
fails to 0 V.
V5CAN
VBAT
VBAT
VV5P,DISC
VV5P,DISC
VV5P,OV,H
VV5P,OV,H
VV5P,OV,L
t = tdOV
V5P
V5P
V5P or V5SNR or V5CAN OV forces POK5V LOW
tdFILT
POK5V
POK5V
NPOR
NPOR
Case 1: VV5P,DISC > V5P > VV5P,OV,H or
V5CAN > VV5,OV,H or V5SNR > VV5,OV,H
tdFILT
Case 2: V5P > VV5P,DISC
Figure 15: Overvoltage Cases for V5P, V5SNR, and V5CAN
× is for “and”, + is for “or”
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
30
A4411
WDRESET
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
VCC_UV = 0 × BG1_UV = 0 × NPOR = 1
NPOR
WDENn
WDACTIVE
WDENn = 0 × NPOR
Correct Pulse Widths
WDSTART,DLY
WDSTART,DLY
+10
+10
+10 +10
+10
+10
-2 -2 -2 -2
WDIN
+10
+10
+10
+10
+10
-2
+10
+10
-2
+10
+10
+10
+10
+10
WDOUT
WDCOUNTER
RESET by WDENn↑ or
ENB × ENBAT = 0 or
MPOR = 1 (i.e. VIN IVLO)
Correct Pulse Widths
0
10
20
30
40
68 66 64 62 72
82
92
102 100 110
120
130 140 138 148
50 60 70
168
168
0
158
WDFAULT
(latched state)
Figure 16: Watchdog (WD) Operation with Both Correct and Incorrect Pulse Widths
WDRESET
1. Incorrect pulse widths increment the WD counter by 10.
2. Correct pulse widths decrement the WD counter by 2.
3. A WD fault occurs if the total fault count exceeds 160.
VCC_UV = 0 × BG1_UV = 0 × NPOR = 1
NPOR
WDENn
WDACTIVE
WDENn = 0 × NPOR
WDSTART,DLY
WDIN
WDOUT
WDCOUNTER
WDSTART,DLY
WDEDGE,TO
WDSTART,DLY
WDACT,TO
No WDIN
ACTIVITY
WDIN ACTIVITY
STOPS
1
2
0
WDFAULT
(latched state)
WDFAULT
(latched state)
WD FAULT REST by
WDENn↑ or VCC_UV or BG1_UV
(ENB × ENBAT = or VIN UVLO)
WD FAULT REST by
WDENn↑ or VCC_UV or BG1_UV
(ENB × ENBAT = or VIN UVLO)
Figure 17: Watchdog Operation with Faults from:
1. No WDIN Activity for WDSTART,DLY + WDEDGE,TO
2. WDIN Activity Stops
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
31
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
A4411
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
Watchdog Detects Rising
Edge and Starts Monitoring
Internal WD Clock Set by RADJ: t OSC = 1/(1 MHz) = 1 µs
Internal WD Timer Period: t WD = 1000 × 1 µs = 1000 µs
Assume MCU
Output Perfect
1 ms ±0%
1 ms ±0%
Guaranteed
OK, ±80 µs
Minimum Count (920)
tMIN = 920 × 1 µs = 920 µs
WD Window with
±8% Programmed
Window Tolerance
AND 0% WD
Oscillator Error
t WD = 1000 µs
Guaranteed Fault Detection
Maximum Count (1080)
NMAX = 1080 × 1 µs = 1080 µs
Guaranteed Fault Detection
OK
REGION
-8% of 1 ms = 920 µs
+8% of 1 ms = 1080 µs
t OSC = 1000 µs
Guaranteed
OK, ±84 µs
WD Window with
±8% Programmed
Window Tolerance
AND 5% WD
Oscillator Error
t WD = 1050 µs
Minimum Count (920)
tMIN = 920 × 1.05 µs = 966 µs
OK
REGION
Guaranteed Fault Detection
Guaranteed Fault Detection
t OSC = 1050 µs
Guaranteed
OK, ±76 µs
WD Window with
±8% Programmed
Window Tolerance
AND -5% WD
Oscillator Error
t WD = 950 µs
Minimum Count (920)
tMIN = 920 × 0.95 µs = 874 µs
Maximum Count (1080)
NMAX = 1080 × 1.05 µs = 1134 µs
OK
REGION
WD Output is always correct
Maximum Count (1080)
NMAX = 1080 × 0.95 µs = 1026 µs
Guaranteed Fault Detection
Guaranteed Fault Detection
t OSC = 950 µs
WD Output is always correct
+26 µs
1000 µs
-34 µs
Required System Clock
Figure 18: Watchdog Timer System Level Functionality (times are not to scale)
A4411 and System Operating Parameters:
1. 1 ms pulse widths coming from the microcontroller
2. ±8% WD Window Tolerance Selected (WDADJ = GND)
3. ±5% WD Oscillator Tolerance (worst case maximum)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
32
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
DESIGN AND COMPONENT SELECTION
PWM Switching Frequency (RFSET)
When the PWM switching frequency is chosen, the designer
should be aware of the minimum controllable on-time, tON(MIN),
of the A4411. If the system’s required on-time is less than the
A4411 minimum controllable on-time, then switch node jitter
will occur and the output voltage will have increased ripple or
oscillations.
The PWM switching frequency should be calculated using equation 1, where tON(MIN) is the minimum controllable on-time of
the A4411 (100 nsTYP) and VIN,MAX is the maximum required
operational input voltage (not the peak surge voltage).
5.35 V
fOSC <
tON,MIN × VIN,MAX
Charge Pump Capacitors
The charge pump requires two capacitors: a 1 µF connected from
pin VCP to VIN, and a 0.22 µF connected between pins CP1 and
CP2. These capacitors should be high-quality ceramic capacitors,
such as X5R or X7R, with voltage ratings of at least 16 V.
Pre-Regulator Output Inductor (L1)
For peak current mode control, it is well known that the system
will become unstable when the duty cycle is above 50% without
adequate Slope Compensation (SE). However, the slope compensation in the A4411 is a fixed value based on the oscillator frequency (fOSC). Therefore, it’s important to calculate an inductor
value so the falling slope of the inductor current (SF) will work
well with the A4411’s fixed slope compensation.
Equation 2 can be used to calculate a range of values for the
output inductor for the pre-regulator. In equation 2, slope compensation (SE1) is a function of the switching frequency (fOSC)
according to equation 3, and VF is the asynchronous diodes
forward voltage.
SE1 = 0.00072 × fOSC + 0.0425
If equation 2 yields an inductor value that is not a standard value,
then the next highest standard value should be used. The final
inductor value should allow for 10%-20% of initial tolerance and
20%-30% of inductor saturation.
The inductor should not saturate given the peak operating current
according to equation 4. In equation 4, VVIN,MAX is the maximum
continuous input voltage, such as 18 V, and VF is the asynchronous diodes forward voltage.
IPEAK1 = 4.8 A –
(1)
If the A4411’s synchronization function is used, then the base
oscillator frequency should be chosen such that jitter will not
result at the maximum synchronized switching frequency according to equation 1.
(5.25 V + VF )
(5.45 V + VF )
≤ L1 ≤
SE1
SE1
2
When using equations 2 and 3, fOSC is in kHz, SE1 is in A/µs, and
L1 will be in µH.
The inductor ripple current can be calculated using equation 5.
ΔIL1 =
(VVIN – 5.35 V) × 5.35 V
fOSC × L1 × VVIN
(5)
Pre-Regulator Output Capacitance
The output capacitors filter the output voltage to provide an
acceptable level of ripple voltage, and they store energy to help
maintain voltage regulation during a load transient. The voltage
rating of the output capacitors must support the output voltage
with sufficient design margin.
Within the first few PWM cycles, the deviation of VVREG will
depend mainly on the magnitude of the load step (ΔILOAD1), the
value of the output inductor (L1), the output capacitance (COUT),
and the maximum duty cycle of the pre-regulator (DMAX1).
Equations 6 and 7 can be used to calculate a minimum output
capacitance to maintain VVREG within 0.5% of its target for a
750 mA load step at only 7 VIN.
2
L1 × (750 mA)
2 × (7.0 V – 5.25 V) × (0.005 × 5.25 V) × DMAX1
DMAX =
(3)
(4)
After an inductor is chosen, it should be tested during output
short-circuit conditions. The inductor current should be monitored using a current probe. A good design should ensure the
inductor or the regulator are not damaged when the output is
shorted to ground at maximum continuous input voltage and the
highest expected ambient temperature.
COUT ≥
(2)
SE1 × (5.25 V + VF )
1.1 × fOSC × (VVIN,MAX + VF )
(
1
fOSC
)
–80 ns × fOSC
(6)
(7)
After the load transient occurs, the output voltage will deviate
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33
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
from its nominal value until the error amplifier can bring the
output voltage back to its nominal value. The speed at which the
error amplifier will bring the output voltage back to its setpoint
will depend mainly on the closed-loop bandwidth of the system.
Selection of the compensation components (RZ1, CZ1, CP1) are
discussed in more detail in the Pre-Regulator Compensation section of this datasheet.
ple, a 0.1 µF/X7R/0603 and a 220 pF/COG/0402 capacitor will
address frequencies up to 20 MHz and 200 MHz, respectively.
The output voltage ripple (ΔVVREG) is a function of the output
capacitors parameters: COUT, ESRCo, and ESLCo according to
equation 8.
The highest average current in the asynchronous diode occurs
when VVIN is at its maximum, DBOOST = 0%, and DBUCK = minimum (10%),
ΔVVREG = Δ IL × ESRCo +
VVIN – VVREG
Δ IL
(8)
× ESLCo +
LO
8 × fOSC × COUT
The type of output capacitors will determine which terms of
equation 8 are dominant. For the A4411 and automotive environments, only ceramic capacitors are recommended. The ESRCO
and ESLCO of ceramic capacitors are virtually zero, so the peakto-peak output voltage ripple of VVREG will be dominated by the
third term of equation 8.
IL
VVREG,PP =
8 × fOSC × COUT
(9)
Pre-Regulator Ceramic Input Capacitance
The ceramic input capacitors must limit the voltage ripple at the
VIN pin to a relatively low voltage during maximum load. Equation 10 can be used to calculate the minimum input capacitance,
CIN ≥
IVREG,MAX × 0.25
0.90 × fOSC × 50 mVPP
(10)
where IVREG,MAX is the maximum current from the pre-regulator,
IVREG,MAX = IV5,CAN + IV5,SNR + IV5P +
VOUT,ADJ × IOUT,ADJ
+ 20 mA (11)
5.25 V × 80%
A good design should consider the DC bias effect on a ceramic
capacitor—as the applied voltage approaches the rated value, the
capacitance value decreases. The X5R- and X7R-type capacitors
should be the primary choices due to their stability versus both
DC bias and temperature. For all ceramic capacitors, the DC bias
effect is even more pronounced on smaller case sizes, so a good
design will use the largest affordable case size (i.e. 1206/16 V or
1210/50 V).
Also, for improved EMI/EMC performance, it is recommended
that two small capacitors be placed as close as physically possible
to the VIN pins to address frequencies above 10 MHz. For exam-
Pre-Regulator Asynchronous Diode (D1)
The highest peak current in the asynchronous diode (D1) occurs
during overload and is limited by the A4411. Equation 4 can be
used to calculate this current.
IAVG = (1 – DBUCK) × IVREG.MAX = 0.9 × IVREG.MAX
(12)
where IVREG,MAX is calculated using equation 11.
Pre-Regulator Boost MOSFET (Q1)
The maximum RMS current in the boost MOSFET (Q1) occurs
when VVIN is very low and the boost operates at its maximum
duty cycle,
IQ1,RMS =
√
DMAX,BST ×
[(I
PEAK1
–
IL1
2
) + I12 ]
2
L1
(13)
where IPEAK1 and ΔIL1 are derived using equations 4 and 5,
respectively, and DMAX,BST is identified in the Electrical Characteristics table.
The boost MOSFET should have a total gate charge of less than
14 nC at a VGS of 5 V. The VDS rating of the boost MOSFET
should be at least 20 V. Several recommended part numbers are
shown in the Functional Block Diagram / Typical Schematic.
Pre-Regulator Boost Diode (D2)
The maximum average current in this diode is simply the output
current, calculated with equation 11. However, in buck-boost mode,
the peak currents in this diode may increase significantly. The A4411
will limit the current to the value calculated by equation 4.
Pre-Regulator Soft-Start and Hiccup Timing
(CSS1)
The soft-start time of the pre-regulator is determined by the value
of the capacitance at the soft-start pin (CSS1).
If the A4411 is starting into a very heavy load, a very fast softstart time may cause the regulator to exceed the pulse-by-pulse
overcurrent threshold. This occurs because the total of the full
load current, the inductor ripple current, and the additional cur-
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34
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
rent required to charge the output capacitors (IC,OUT = COUT ×
VOUT / tSS) is higher than the pulse-by-pulse current threshold, as
shown in Figure 19.
Pre-Regulator Compensation (RZ1, CZ1, CP1)
}
ILIM
Although the A4411 can operate in buck-boost mode at low
input voltages, it still can be considered a buck converter when
examining the control loop. The following equations can be used
to calculate the compensation components.
ILOAD
Output
Capacitor
Current, IC,OUT
tSS
Figure 19: Output Current (ICO) During Startup
To avoid prematurely triggering hiccup mode, the soft-start time
(tSS1) should be calculated using equation 14,
COUT
tSS1 = 5.35 V ×
(14)
IC,OUT
where COUT is the output capacitance, and IC,OUT is the amount
of current allowed to charge the output capacitance during softstart (recommend 0.1 A < IC,OUT < 0.3 A). Higher values of
IC,OOUT result in faster soft-start time, and lower values of IC,OUT
ensure that hiccup mode is not falsely triggered. Allegro recommends starting the design with an IC,OUT of 0.1 A and increasing
it only if the soft-start time is too slow.
Then, CSS1 can be calculated based on equation 15:
CSS1 ≥
ISS1,SU × tSS1
0.8 V
(15)
If a non-standard capacitor value for CSS1 is calculated, the next
higher value should be used.
The voltage at the soft-start pin will start from 0 V and will
be charged by the soft-start current (ISS1,SU). However, PWM
switching will not begin immediately because the voltage at
the soft-start pin must rise above the soft-start offset voltage
(VSS1,OFFS). The soft-start delay (tSS1,DELAY) can be calculated
using equation 16.
tSS1,DELAY = CSS1 ×
VSS1.OFFS
ISS1,SU
the hiccup period. During a startup attempt, the soft-start pin
charges the soft-start capacitor with ISS1,SU and discharges the
same capacitor with ISS1,HIC between startup attempts.
(16)
When the A4411 is in hiccup mode, the soft-start capacitor sets
First, select the target crossover frequency for the final system.
While switching at over 2 MHz, the crossover is governed by
the required phase margin. Since a type II compensation scheme
is used, the system is limited to the amount of phase that can be
added. Hence, a crossover frequency (fC1) in the region of 40
kHz is selected. The total system phase will drop off at higher
crossover frequencies. The RZ1 calculation is based on the gain
required to set the crossover frequency and can be calculated by
equation 17.
13.38 × π × fC1 × COUT
RZ1 =
(17)
gmPOWER1 × gmEA1
The series capacitor (CZ1) along with the resistor (RZ1) set the
location of the compensation zero. This zero should be placed no
lower than ¼ of the crossover frequency and should be kept to
minimum value. Equation 18 can be used to estimate this capacitor value.
CZ1 >
4
2π × RZ1 × fC1
(18)
Allegro recommends adding a small capacitor (CP1) in parallel
with the series combination of RZ1/CZ1 to roll off the error amps
gain at high frequency. This capacitor usually helps reduce LX1
pulse-width jitter, but if too large, it will also decrease the loop’s
phase margin.
Allegro recommends using this capacitor to set a pole at approximately 8× the loop’s crossover frequency (fC1), as shown in equation 19. If a non-standard capacitor value results, the next higher
available value should be used.
CP1 ≈
1
2π × RZ1 × 8 × fC1
(19)
Finally, look at the combined bode plot of both the power stage
and the compensated error amp—the red curves shown in Figure
20. Careful examination of this plot shows that the magnitude and
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35
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
A4411
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
phase of the entire system are simply the sum of the error amp
response (blue) and the power stage response (green). As shown
in Figure 20, the bandwidth of this system (fC1) is 43 kHz, the
phase margin is 67 degrees, and the gain margin is 23 dB.
135
60
PM = 67º
40
Gain (dB)
0
0
Phase (º)
fC1 = 43 kHz
-45
-20
-90
Total Gain
E/A Gain
GM = 23 dB
Total Phase
Power Gain
E/A Phase
10
1
-135
Power Phase
-60
0.1
100
-180
1000
Frequency (kHz)
Figure 20: Bode Plot for the Pre-Regulator
RZ1 = 22.1 kΩ, CZ1 = 1.5 nF, CP1 = 15 pF
Lo = 4.7 µH, Co = 5 × 10 µF/16 V/1206
Similar design methods can be used for the synchronous buck;
however, the complexity of variable input voltage and boost
operation are removed.
Setting the Output Voltage (RFB1 and RFB2)
The A4411 allows the user to program the output voltage of the
synchronous buck from 0.8 to 3.3 V. This is achieved by adding
a resistor divider from its output to ground and connecting the
center point to the FBADJ pin; see Figure 21 below.
The ratio of the feedback resistors can be calculated based on
equation 20.
(800V mV – 1)
OUT,ADJ
A4411
Figure 21: Setting the Synchronous Buck Output
Synchronous Buck Output Inductor (L2)
Equation 21 can be used to calculate a range of values for the output inductor for the synchronous buck regulator. Slope compensation (SE2) can be calculated using equation 22.
VOUT,ADJ
VOUT,ADJ
≤ L2 ≤
SE2
2 × SE2
(21)
SE2 = 0.0003 × fOSC + 0.0175
(22)
When working with equations 21 and 22, fOSC is in kHz, SE2 is in
A/µs, and L2 will be in µH.
Synchronous Buck Component Selection
RFB1
=
RFB2
FBADJ
RFB2
45
-40
RFB1
90
20
VOUT,ADJ
LX2
ADJ. SYNC.
BUCK
REGULATOR
180
80
L2
(20)
If equation 21 yields an inductor value that is not a standard
value, then the next closest available value should be used. The
final inductor value should allow for 10%-20% of initial tolerance and 20%-30% for inductor saturation.
The inductor should not saturate given the peak current at overload according to equation 23.
IPEAK2 = 2.4 A –
SE2 × VOUT,ADJ
1.1 × fOSC × 5.45 V
(23)
After an inductor is chosen, it should be tested during output
short-circuit conditions. The inductor current should be monitored using a current probe. A good design should ensure the
inductor or the regulator are not damaged when the output is
shorted to ground at maximum input voltage and the highest
expected ambient temperature.
Once the inductor value is known, the ripple current can be calculated using equation 24.
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36
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
A4411
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
IL2 =
(5.35 V × VOUT,ADJ ) × VOUT,ADJ
fOSC × L2 × 5.35 V
(24)
Synchronous Buck Output Capacitance
Within the first few PWM cycles, the deviation of VOUT,ADJ will
depend mainly on the magnitude of the load step (ΔILOAD2),
the value of the output inductor (L2), the output capacitance
(COUT,ADJ), and the maximum duty cycle of the synchronous
converter (DMAX2). Equations 25 and 26 can be used to calculate
a minimum output capacitance to maintain VOUT,ADJ within 0.5%
of its target for a 400 mA load step.
2
COUT,ADJ ≥
L2 × (400 mA)
(25)
2 × (5.25 V – VOUT,ADJ ) × (0.005 × VOUT,ADJ ) × DMAX2
DMAX2 =
(
1
fOSC
)
– 110 ns × fOSC
(26)
After the load transient occurs, the output voltage will deviate
from its nominal value until the error amplifier can bring the
output voltage back to its nominal value. The speed at which the
error amplifier will bring the output voltage back to its setpoint
will depend mainly on the closed-loop bandwidth of the system.
Selection of the compensation components (RZ2, CZ2, CP2) are
discussed in more detail in the Synchronous Buck Compensation
section of this datasheet.
The series capacitor (CZ2) along with the resistor (RZ2) set the
location of the compensation zero. This zero should be placed no
lower than ¼ of the crossover frequency and should be kept to
minimum value. Equation 29 can be used to estimate this capacitor value.
CZ2 >
Allegro recommends using this capacitor to set a pole at approximately 8× the loop’s crossover frequency (fC2), as shown in equation 30. If a non-standard capacitor value results, use the next
higher available value.
CP2 ≈
(30)
Finally, look at the combined bode plot of both the power stage
and the compensated error amp—the red curves shown in Figure
22. The bandwidth of this system (fC2) is 56 kHz, the phase margin is 70°, and the gain margin is 28 dB.
180
80
135
60
90
PM = 70º
40
(27)
Again, similar techniques as used with the pre-regulator can be
used to compensate the synchronous buck.
For the synchronous buck, select 55 kHz for the crossover frequency (fC2) of the synchronous buck. Then, equation 28 can be
used to calculate RZ2.
(28)
Gain (dB)
45
Synchronous Buck Compensation (RZ2, CZ2,
CP2)
VOUT,ADJ × 2π × fC2 × COUT,ADJ
RZ2 =
800 mV × gmPOWER2 × gmEA2
1
2π × R Z2 × 8 × f C2
20
fC1 = 56 kHz
0
0
Phase (º)
IL2
8 × fOSC × COUT,ADJ
(29)
Allegro recommends adding a small capacitor (CP2) in parallel
with the series combination of RZ2/CZ2 to roll off the error amp
gain at high frequency. This capacitor usually helps reduce LX2
pulse-width jitter, but if too large, it will also decrease the loop’s
phase margin.
Allegro recommends the use of ceramic capacitors for the synchronoous buck. The peak-to-peak voltage ripple of the synchronous buck (ΔVOUT,ADJ,PP) can be calculated with equation 27.
VVOUT,ADJ,PP =
4
2π × R Z2 × f C2
-45
GM = 28 dB
-20
-40
Total Gain
E/A Gain
Power Gain
Total Phase
E/A Phase
Power Phase
-135
-60
0.1
1
10
-90
100
-180
1000
Frequency (kHz)
Figure 22: Bode Plot for the Sync. Buck at 3.3 VOUT
RZ2 = 10 kΩ, CZ2 = 1.5 nF, CP2 = 15 pF
L2 = 4.7 µH, COUT,ADJ = 2 × 10 µF/16 V/1206
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37
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
Synchronous Buck Soft-Start and Hiccup Timing
The soft-start time of the synchronous buck is determined by the
value of the capacitance at the soft-start pin (CSS2).
If the A4411 is starting into a very heavy load, a very fast softstart time may cause the regulator to exceed the pulse-by-pulse
overcurrent threshold. To avoid prematurely triggering hiccup
mode, the soft-start time (tSS2) should be calculated according to
equation 31,
tSS2 = VOUT,ADJ ×
COUT,ADJ
IC,OUT
(31)
where VOUT,ADJ is the output voltage, COUT,ADJ is the output
capacitance, IC,OUT is the amount of current allowed to charge the
output capacitance during soft-start (recommend 75 mA < IC,OUT
< 150 mA). Higher values of IC,OUT result in faster soft-start
times and lower values of IC,OUT ensure that hiccup mode is not
falsely triggered. For the synchronous buck, Allegro recommends
starting the design with an IC,OUT of 100 mA and increasing it
only if the soft-start time is too slow.
Then, CSS2 can be selected based on equation 32,
CSS2 >
ISS2,SU × tSS2
800 mV
(32)
If a non-standard capacitor value for CSS2 is calculated, the next
larger value should be used.
The voltage at the soft-start pin will start from 0 V and will be
charged by the soft-start current (ISS2,SU). However, PWM switching will not begin instantly because the voltage at the soft-start pin
must rise above the soft-start offset voltage (VSS2,OFFS). The softstart delay (tSS2,DELAY) can be calculated using equation 33,
tSS2,DELAY = CSS2 >
( IV )
SS2,OFFS
(33)
When the A4411 is in hiccup mode, the soft-start capacitor sets
the hiccup period. During a startup attempt, the soft-start pin
charges the soft-start capacitor with ISS2,SU and discharges the
same capacitor with ISS1,HIC between startup attempts.
Linear Regulators
The three linear regulators only require a single ceramic capacitor
located near the A4411 to ensure stable operation. The range of
acceptable values is shown in the Electrical Characteristics table.
A 2.2 μF capacitor per regulator is a good starting point.
As the LDO outputs are routed throughout the PCB, it is recommended that a 0.1 µF/0603 ceramic capacitor be placed as close
as possible to each load point for local filtering and high-frequency noise reduction.
Also, since the V5P output may be used to power remote circuitry, its load may include external wiring. The inductance of
this wiring will cause LC-type ringing and negative spikes at the
V5P pin if a “fast” short-to-ground occurs. It is recommended
that a small Schottky diode be placed close to the V5P pin to limit
the negative voltages, as shown in the Applications Schematic.
The MSS1P5 (or equivalent) is a good choice.
Internal Bias (VCC)
The internal bias voltage should be decoupled at the VCC pin
using a 1 μF ceramic capacitor. It is not recommended to use this
pin as a source.
Signal Pins, (NPOR, POK5V, WDOUT, ENBATS)
The A4411 has many signal-level pins. The NPOR, POK5V,
WDOUT, and ENBATS are open-drain outputs and require external pull-up resistors. Allegro recommends sizing the external
pull-up resistors so each pin will sink less than 2 mA when it is a
logic low.
SS2,SU
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38
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
PCB LAYOUT RECOMMENDATIONS
Figure 23: PCB Layout #1
The input ceramic capacitors (C3, C4, C5, C6, C34) must be located as close as possible to the VIN pins. In general, the smaller capacitors
(0402, 0603) must be placed very close to the VIN pin. The larger capacitors (4.7 µF, 50 V, 1210) should be placed within 0.5 inches of the VIN
pin. There must not be any vias between the input capacitors and the VIN pin.
Figure 24: PCB Layout #2
The pre-buck asynchronous diode (D1), input ceramic capacitors (C4, C5, C6), and RC snubber (RN, CN) must be routed on one layer and
“star” grounded at a single location with multiple vias.
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39
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
Figure 25: PCB Layout #3
The pre-buck output inductor (L1) should be located close to the LX1 pins.
The LX1 trace widths (to L1, D1, RN) should be relatively wide and preferably on the same layer as the IC.
Figure 26: PCB Layout #4
The pre-buck regulators output ceramic capacitors (C10-C14) should be located near the VREG pin.
There must be 1 or 2 smaller ceramic capacitors (C8, C9) as close as possible to the VREG pin.
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40
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
Figure 27: PCB Layout #5
The synchronous buck output inductor should be located near the LX2 pins. The trace from the LX2 pins to the output inductor (L2) should be
relatively wide and preferably on the same layer as the IC.
Figure 28: PCB Layout #6
The two feedback resistors (R15, R16) must be located near the FBADJ pin. The output capacitors (C16-C18) should be located near the load.
The output voltage sense trace (to R15) must connect at the load for the best regulation.
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41
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
Figure 29: PCB Layout #7
The charge pump capacitors (C1, C2) must be placed as close as possible to VCP and CP1/CP2.
Figure 30: PCB Layout #8
The ceramic capacitors for the LDOs (3V3, V5, V5P, V5CAN, V5SNR, etc) must be placed near their output pins.
The V5P output must have a 1 A / 40 V schottky diode (D5) located very close to its pin to limit negative voltages.
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42
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
Figure 31: PCB Layout #9
Figure 32: PCB Layout #10
The FSET resistor must be placed very close to the FSET/SYNC pin.
Similarly, the VCC bypass capacitor must be placed very close to the
VCC pin.
The COMP network for both buck regulators (CZx, RZx, CPx) must be
located very close to the COMPx pin.
Figure 33: PCB Layout #11
Figure 34: PCB Layout #12
The thermal pad under the A4411 must connect to the ground
plane(s) with multiple vias.
The boost MOSFET (Q1) and the boost diode (D2) must be placed
very close to each other. Q1 should have thermal vias to a polygon
on the bottom layer. Also, there should be “local” bypass capacitors
(C33, C35).
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1.508.853.5000; www.allegromicro.com
43
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
A4411
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
PACKAGE OUTLINE DRAWING
For Reference Only – Not for Tooling Use
(Reference JEDEC MO-153 BDT-1)
Dimensions in millimeters
NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
9.70 ±0.10
8º
0º
6.50 ±0.10
38
0.20
0.09
B
3.00 ±0.10 4.40 ±0.10 6.40 BSC
A
0.60 ±0.15
1.00 REF
1 2
Branded Face
C
38X
0.90 ±0.05 1.10 MAX
0.10 C
0.27
0.17
0.25 BSC
SEATING PLANE
GAUGE PLANE
SEATING
PLANE
0.15
0.00
0.50 BSC
0.50
0.30
38
1.70
3.00
A
Terminal #1 mark area
6.5
B
Exposed thermal pad (bottom surface)
PCB Layout Reference View
C
Reference land pattern layout (reference IPC7351 SOP50P640X120-39M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
1 2
C
6.00
Figure 35: Package LV, 38-Pin eTSSOP
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
44
A4411
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V
Revision History
Revision
Revision Date
Description of Revision
–
April 3, 2015
1
June 25, 2015
2
October 26, 2015
Updated WDIN Pulse-Width Programming minimum (page 17) and MPOR definition (page 23).
December 9, 2015
Corrected Functional Block Diagram (page 4), Figure 6 (page 20), and Figures 16 and 17 (page 31);
updated Watchdog decription (page 20).
3
Initial Release
Dither/Slew START and STOP Threshold on page 8 updated to account for high temperature drift
Copyright ©2015, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
45
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