A4410 Datasheet

A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
FEATURES AND BENEFITS
•
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•
•
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•
•
•
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•
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Automotive AEC-Q100 qualified
2.8 VIN to 36 VIN operating range, 40 VIN maximum
Buck or buck/boost pre-regulator (VREG)
Adjustable PWM switching frequency: 250 kHz –
2.4 MHz
PWM frequency can be synchronized to external clock
1.25 V/750 mADC/1 APEAK synchronous buck (1V25)
3.3 V (3V3) and 5 V (V5) internal LDO regulators with
fold back short circuit protections
5 V (V5P) internal tracking LDO regulator with fold
back short circuit and short-to-battery protections
TRACK sets either 3V3 or V5 as the reference for V5P
Power-on reset with fixed delay of 15 ms for 1V25/3V3
UV and OV protection (NPOR)
Programmable watchdog timer with a 30 ms activation
delay
Active low, watchdog timer enable/disable pin (WDENn)
Dual band gaps for increased reliability: BGVREF,
BGFAULT
Continued on next page...
APPLICATIONS
• Automotive Control Modules for:
□□ Electronic Power
□□ Emissions Control
Steering (EPS)
Modules
□□ Transmission Control
□□ Other automotive
(TCU)
applications
□□ Advanced Braking
Systems (ABS)
PACKAGE: 38-Pin eTSSOP (suffix LV)
DESCRIPTION
The A4410 is power management IC that uses a buck or buck/
boost pre-regulator to efficiently convert automotive battery
voltages into a tightly regulated intermediate voltage complete
with control, diagnostics, and protections. The output of the
pre-regulator supplies a 5 V/250 mAMAX tracking/protected
LDO, a 3.3 V/160 mAMAX LDO, a 5 V/150 mAMAX LDO,
and a 1.25 V/750 mADC/1 APEAK synchronous buck regulator.
Designed to supply CAN or microprocessor power supplies in
high temperature environments the A4410 is ideal for under
hood applications.
Enable inputs to the A4410 include a logic level (ENB) and two
high-voltage (ENBAT1 and ENBAT2). The A4410 provides
flexibility by including a TRACK pin to set the reference of
the tracking regulator to either the 5 V or the 3.3 V output,
so the A4410 can be adapted across multiple platforms with
different sensors and supply rails.
Diagnostic outputs from the A4410 include a power-on-reset
output (NPOR) with a fixed 15 ms delay, an ENBAT1 and
ENBAT2 status outputs, and a PowerOK output for the 5 V
and 5 V protected LDOs (POK5V). Dual bandgaps, one for
regulation and one for fault checking, improve long-term
reliability of the A4410.
The A4410 contains a Window Watchdog timer that can be
programmed to accept a wide range of clock frequencies
(WDADJ). The watchdog timer has a fixed 30 ms activation
delay to accommodate processor startup. The watchdog timer
has an enable/disable pin (active LOW, WDENn) to facilitate
initial factory programming or field re-flash programming.
Protection features include under and over voltage lockout on
all four CPU supply rails. In case of a shorted output, all linear
regulators feature fold back over current protection. In addition,
the V5P output is protected from a short-to-battery event. Both
Continued on next page...
Not to scale
5.35 V
(VREG)
Buck-Boost
Pre-regulator
3.3 V LDO
(3V3)
with Foldback
Protection
1.25 V
(1V25)
Sync. Buck
Regulator
Programmable
Pulse Width
Watchdog
Timer with
Activation Delay
5 V LDO
(V5)
with Foldback
Protection
3V3
Dual
Bandgaps
Charge
Pump
Thermal
Shutdown
(TSD)
POK5V
Output
NPOR
Output
V5
A4410 Simplified Block Diagram
A4410-DS
Tracking
Control
2:1 MUX
5 V LDO
(V5P)
with Tracking,
Foldback, and
Short to VBAT
Protetction
REF
A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
Features and Benefits (continued)
Description (continued)
•
•
•
•
•
•
•
•
•
•
switching regulators include pulse-by-pulse current limit, hiccup
mode short circuit protection, LX short circuit protection, missing
asynchronous diode protection (VREG only) and thermal shutdown.
PowerOK output for V5/V5P UV and OV (POK5V)
Logic enable input (ENB) for microprocessor control
Two ignition enable inputs (ENBAT1 and ENBAT2)
ENBAT1 and ENBAT2 status indicator outputs
SLEW rate control pin helps reduce EMI/EMC
Frequency dithering helps reduce EMI/EMC
OV and UV protection for all four CPU supply rails
Pin-to-pin and pin-to-ground tolerant at every pin
Thermal shutdown protection
−40ºC to 150ºC junction temperature range
Selection Guide
1
Part Number
Temp. Range
A4410KLVTR-T
–40 to 135°C
The A4410 is supplied in a low profile, 38-lead eTSSOP package
(suffix “LV”) with exposed power pad.
Package
38-pin eTSSOP w/ thermal
pad
Packing1
Lead Frame
4000 pieces per 7-in reel
100% Matte Tin
Contact Allegro for additional packing options.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
A4410
SPECIFICATIONS
Absolute Maximum Ratings1
Characteristic
Symbol
VIN
Notes
VVIN
VENBATx
ENBAT1, ENBAT2
With current limiting
resistor2
Rating
Unit
−0.3 to 40
V
−13 to 40
V
−0.3 to 8
IENBATx
±75
mA
−0.3 to VVIN+0.3
LX1, SLEW
t < 250 ns
−1.5
t < 50 ns
VVIN+3 V
VCP, CP1, CP2
V
−0.3 to 50
V5P
VV5P
−1.0 to 40
All other pins
V
V
3
−0.3 to 7
V
Ambient Temperature
TA
−40 to 135
ºC
Junction Temperature
TJ
−40 to 150
ºC
Storage Temperature Range
TS
−40 to 150
ºC
Range K for automotive
Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability
2 The higher ENBAT1 and ENBAT2 ratings (-13 V and 40 V) are measured at node “A” in the following circuit configuration:
1
Node “A”
≥450 Ω
ENBATx
VEN
+
-
A4410
GND
3
Independent of VVIN.
Table 3: Thermal Characteristics
(may require derating at maximum conditions, see application information)
Characteristic
Junction to Pad Thermal Resistance
Symbol
RθJC
Test Conditions*
eTSSOP-38 (LV) Package
Value
Unit
30
ºC/W
*Additional thermal information available on the Allegro website.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
A4410
CP2
0.22 µF
VBAT
Required if VREG
is fully loaded and
VVIN < 6.0 V
Din
SS3P4
100 µF
50 V/250 mΩ
2×4.7 µF
50 V
1210
0.1 µF
0603
VCC
CZ1
1.5 nF
SYNC
(optional)
BGVREF
OSC2
BGVREF
VREG ON
VCP UV
CLK1MHz
CLK @ FOSC
FET/SYNC
BG1_UV, BG2_UV
VCC UV, VCP UV
VIN,UVLO
*VCP OV, *D1MISSING
*SLEW UV/OV
*ILIM,LX1
VCC
20 k
NPOR
COMP1 & SS1 Reset
2 kΩ
VREG
MPOR
MASTER
IC POR
(MPOR)
*indicates a
latched fault
VSS1RST
SS OK
0.47 µF
VSS2RST
TSD
RST
REF
N/C
OV/UV DETECT
& DELAYS
POK5V
POK5V
SU/SD
DEGLITCH
tdFILT
1.25 V
DEGLITCH
tdFILT
V5
BGVREF
PGND
PGND
FB1V25
COMP2
SS2
1V25 ON
3.3 V
V5P
REF
V5PDISC
FOLDBACK
0
7.5 k
D5
MSS1P5
2:1
MUX
60 kΩ
3.3 V
LDO
2.2 µF
3V3
5V
LDO
LDOs ON
2.2 µF
DEGLITCH
tdFILT
ON/OFF
FALLING
SU/SD
DELAY
tdLDO,OFF
20 k
650 kΩ
WD
OSC
WDIN
WDENn
ENBAT1
STATUS
ENBAT2S
ENBAT2
STATUS
WDCLK
WDENn = 0 or OPEN enables WD
60 kΩ
20 k
ENBAT1S
ENBAT2
0.22 µF*
V5
150 mAMAX
V5
VCC
650 kΩ
0.22 µF*
WDADJ
If RADJ 64.9 k
WDTO,FAST = 5 ms
WDTO,SLOW = 20 ms
VSP
250 mAMAX
3V3
160 mAMAX
3V3
1
BGVREF
3.3 VTYP↑
2.6 VTYP↓
3.3 VTYP↑
2.6 VTYP↓
WDENn
2.2 µF
FOLDBACK
3.3 k
CLKIN
CP2
22 pF
V5P
FOLDBACK
V5
ENB
* For negative V_IGN or
V_ACC tranwsient
suppression
7.6 V
MMSZ
4693T1
RZ2
15 k
CSS2
10 nF
CZ2
3.3 nF
ENBAT1
V_IGN
1.25 V
750 mADC
1 APEAK
LDOs ON
100 µA
7.6 V
MMSZ
4693T1
3 × 10 µF
L2 2.2 µH, 61 MΩ
16V/X7R/1206
IHLP1616BEZER2R2M11 (27–30 µf @ 1.25 V)
Short to
VBAT
Protection
5v
TRACKING
LDO
1V25 ON
SELECT
TRACK
SYNCHRONOUS
BUCK
REGULATOR
(1V25)
(w/Hiccup Mode)
CLK @
FOSC
VREG ON
STARTUP/
SHUTDOWN
SEQUENCE
LX2
LX2
COMP2 & SS2 Reset
V5PDISC
REF
BGFAULT
MPOR
VCC UV
1V25 UV
3V3 UV
V5 UV
V5P UV
7.5 k
5×10 µF
16V/X7R/1206
(38 – 43 µF @ 5.3 V)
D2
SS3P4
Q1:
NVTFS4823N or
SQS420EN or
STL10N3LLH5
LG
FSET UV/OV
CLK1MHz
ON/OFF
3.3 k
D1
SS3P4
STOP PWM
WDFAULT
WDSTART
VCC
V_ACC
LX1
LX1
OV/UV DETECT
& DELAYS
NPOR
µC
ENABLE
L1 4.7 µH, 37 mΩ
IHLP2525CZER4R7M01
FB
RFSET
8.66 kΩ
20 k
BUCK-BOOST
PRE-REGULATOR
(VREG)
(w/Hiccup Mode)
SS1
OSC1
RSLEW
22.1 kΩ
75 mΩ
COMP1
100 mA
SLEW
BG2_UV
VCC
COMP1
SS1
CSS1
22 nF
Charge
Pump
BGFAULT
BG2
VIN,START
VIN,STOP
RZ1
22.1 k
VCP
UV/OV
BG1_UV
VIN,UVLO
D4
MSS1P5
CP3
0.1 µF/50 V
BG1
LDO
3.6 V
EN
CP1
15 pF
D3
BAS16J
VREG
VIN
VIN
KEY_SW
CVCC
1 µF
CP2
VCP
CP1
CP1
1.0 µF
WINDOW
WATCHDOG
TIMER
CLK1MHz
ONE SHOT
2 msTYP
GND
GND
WDFAULT
WDSTART
A4410
Functional Block Diagram/Typical Schematic
Buck-Boost Mode (fOSC = 2 MHz)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
Required if VREG
is fully loaded and
VVIN < 6.0 V
CP2
A4410
CP1
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
A4410
L1 4.7 µH, 37 mΩ
IHLP2525CZER4R7M01
LX1
LX1
RZ1
13.3 k
D4
MSS1P5
CP3
0.1 µF/50 V
COMP1
CP1
27 pF
D3
BAS16J
CZ1
2.7 nF
5.35 VTYP
D1
SS2P4
3×10 µf
16V/X7R/1206
(23 – 26 µF @ 5.3 V)
LG
VREG
0.47 µf
Functional Block Diagram Modifications for Buck Only Mode (fOSC = 2.0 MHz)
Body Diode
VBAT
MODULE
Functional Block Diagram Using a PMOS FET for Reverse Battery Protection Instead of a Series Schottky Diode
(DIN)
VBAT
MODULE
Body Diode
Functional Block Diagram Using an NMOS FET for Reverse Battery Protection Instead of a Series Schottky Diode
(DIN)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
A4410
Terminal List Table
VCP
1
38 CP2
VIN
2
37 CP1
Number
Name
VIN 3
36 LX1
1
VCP
Charge pump reservoir capacitor
35 LX1
2,3
VIN
Input voltage
34 SLEW
GND
4
N/C 5
Function
4,9
GND
Ground
VCC 6
33 LG
5
N/C
No Connect
SS1 7
32 VREG
6
VCC
Internal voltage regulator bypass capacitor pin
31 V5
7
SS1
Soft start programming pin for the buck/boost pre-regulator
30 LX2
8
COMP1
Error amplifier compensation network pin for the buck/boost pre-regulator
10
TRACK
Tracking control: Open/High – V5P tracks 3V3, GND/Low – V5P tracks
V5
COMP1 8
GND 9
TRACK 10
NPOR 11
PAD
29 LX2
28 PGND
27 PGND
11
NPOR
Active LOW, open-drain regulator fault detection output
ENBAT1S 13
26 COMP2
12
POK5V
ENBAT2S 14
25 FB1V25
PowerOK output indicating when either the V5 or V5P rail is undervoltage (UV)
POK5V 12
FSET/SYNC 15
24 SS2
13
ENBAT1S
Open drain ignition status output, for ENBAT1 only
ENBAT1 16
23 V5P
14
ENBAT2S
Open drain ignition status output, for ENBAT2 only
ENBAT2 17
22 WDENn
15
ENB 18
21 WDADJ
FSET/
SYNC
3V3 19
20 WDIN
16
ENBAT1
Ignition enable input from the key/switch via a 1K of resistance
17
ENBAT2
Ignition enable input from the key/switch via a 1K of resistance
18
ENB
Logic enable input from the micro-controller
19
3V3
3.3 V regulator output
20
WDIN
Watchdog refresh input (rising edge triggered) from a micro-controller or
DSP
21
WDADJ
The watchdog wait/delay time is programmed by connecting RADJ from
this pin to ground
22
WDENn
Watchdog enable pin: Open/Low – WD is enabled, High – WD is disabled
Package LV, 38-Pin eTSSOP
Pin-out Diagram
Frequency setting and synchronization input
23
V5P
5 V tracking/protected regulator output
24
SS2
Soft start programming pin for the 1.25 V synchronous buck
25
FB1V25
Feedback pin for the 1.25 V regulator
26
COMP2
Error amplifier compensation network pin for the 1.25 V synchronous
regulator
27,28
PGND
29,30
LX2
Switching node for the 1.25 V synchronous regulator
31
V5
5 V regulator output
32
VREG
33
LG
Power ground for the 1.25 V synchronous regulator / gate driver
Output of the buck-boost and input for the LDOs and 1.25 VOUT sync.
Buck
Boost gate drive output for the buck/boost pre-regulator
34
SLEW
35,36
LX1
Slew rate adjustment for the rise time of LX1
Switching node for the buck/boost pre-regulator
37
CP1
Charge pump capacitor connection
38
CP2
Charge pump capacitor connection
–
PAD
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
ELECTRICAL CHARACTERISTICS – GENERAL SPECIFICATIONS1: valid at 3.6 V 4 < VIN < 36 V, –40ºC < TA = TJ < 150ºC,
unless otherwise specified.
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
After VVIN > VINSTART, and VENB > 2.0 V or
VENBATx > 3.5V, Buck-Boost Mode
2.8
13.5
36
After VVIN > VINSTART, and VENB > 2.0 V or
VENBATx > 3.5V, Buck Mode
5.1
13.5
36
Unit
General Specifications
Operating Input Voltage
VVIN
V
VIN UVLO START Voltage
VINSTART
VVIN rising
4.55
4.80
5.05
V
VIN UVLO STOP Voltage
VINSTOP
VVIN falling, VENBATx ≥ 3.6 V or
VENB ≥ 2.0 V, VVREG = 5.2 V
2.52
2.65
2.78
V
VIN UVLO Hysteresis
VINHYS
VINSTART ‒ VINSTOP
—
2.2
—
V
VVIN = 13.5 V, VENBATx ≥ 3.6 V or
VENB ≥ 2.0 V, VVREG = 5.6 V (no PWM)
—
13
—
mA
VVIN = 13.5 V, VENBATx ≤ 2.2 V and
VENB ≤ 0.8 V
—
—
10
µA
RFSET = 8.66 kΩ
1.8
2.0
2.2
—
1.0
—
343
400
457
kHz
IQ
Supply Quiescent Current 1
IQ,SLEEP
PWM Switching Frequency and Dithering
Switching Frequency
fOSC
RFSET = 20.5 kΩ
2
RFSET = 57.6 kΩ 2
Frequency Dithering
ΔfOSC
As a percent of fOSC
MHz
—
±12
—
%
Dither/Slew START Threshold
VINDS,ON
8.5
9.0
9.5
V
Dither/Slew STOP Threshold
VINDS,OFF
7.8
8.3
8.8
V
—
700
—
mV
VVCP – VVIN, VVIN = 13.5 V, VVREG = 5.50 V,
IVCP = 6.5 mA, VCOMP1 = VCOMP2 = 0 V,
VENB = 3.3 V
4.1
6.6
—
VVCP – VVIN, VVIN = 6.5 V, VVREG = 5.50 V,
IVCP = 6.5 mA, VCOMP1 = VCOMP2 = 0 V,
VENB = 3.3 V
3.1
3.8
—
—
65
—
kHz
—
4.65
—
V
155
170
185
ºC
—
20
—
VIN Dithering/Slew Hysteresis
Charge Pump (VCP)
Output Voltage
VVCP
Switching Frequency
fSW,CP
V
VCC Pin Voltage
Output Voltage
VVCC
VVREG = 5.35 V
Thermal Shutdown Threshold 2
TTSD
TJ rising
Thermal Shutdown Hysteresis
THYS
Thermal Protection
2
Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking).
2 Ensured by design and characterization, not production tested.
3 Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4 The lowest operating voltage is only valid if the conditions V
VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.
1
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
ELECTRICAL CHARACTERISTICS – BUCK AND BUCK-BOOST PRE-REGULATOR SPECIFICATIONS1: valid at 3.6 V
4
< VIN < 36 V, –40ºC < TA = TJ < 150ºC, unless otherwise specified.
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
VVREG
VVIN = 13.5 V, ENB = 1, 0.1 A < IVREG < 1.25 A
5.25
5.35
5.45
V
VCOMP1 for 0% duty cycle
—
400
—
mV
VVIN = 13.5 V, 10% to 90%, IVREG = 1 A,
RSLEW = 22.1 k
—
0.9
—
VVIN = 13.5 V, 10% to 90%, IVREG = 1 A,
RSLEW = 249 k
—
0.3
—
Output Voltage Specifications
Buck Output Voltage – Regulating
Pulse Width Modulation (PWM)
PWM Ramp Offset
LX1 Rising Slew Rate Control 2
LX1 Falling Slew Rate 2
Buck Min. Controllable ON-time
PWM1OFFS
LX1RISE
LX1FALL
Buck Maximum Duty Cycle
DMAX,BUCK
Boost Minimum OFF-time
tON,MIN,BST
Boost Maximum Duty Cycle
DMAX,BST
COMP1 to LX1 Current Gain
gmPOWER1
Slope Compensation (2)
VVIN = 13.5 V, 90% to 10%, IVREG = 1 A
tON,MIN,BUCK
SE1
tOFF,BUCK < 50 ns
After VVIN > VINSTART, VVIN = 3.6 V
V/ns
—
1.5
—
V/ns
—
195
—
ns
—
100
—
%
—
100
130
ns
—
65
—
%
—
4.5
—
A/V
fOSC = 2.0 MHz
1.04
1.48
1.92
fOSC = 400 kHz
0.22
0.33
0.44
VVIN = 13.5 V, TJ = ‒40°C 2, IDS = 0.1 A
—
50
65
mΩ
VVIN = 13.5 V, TJ = 25°C
A/µs
Internal MOSFET
MOSFET On Resistance
MOSFET Leakage
RDSon
IFET,LKG
3,
IDS = 0.1 A
—
75
90
mΩ
VVIN = 13.5 V, TJ = 150°C, IDS = 0.1 A
—
150
180
mΩ
VENBATx ≤ 2.2 V and VENB ≤ 0.8 V, VLX1 = 0 V,
VVIN = 16 V, −40°C < TJ < 85°C 3
—
—
10
µA
VENBATx ≤ 2.2 V and VENB ≤ 0.8 V, VLX1 = 0 V,
VVIN = 16 V, −40°C < TJ < 150°C
—
50
150
µA
dB
Error Amplifier
Open Loop Voltage Gain
Transconductance
Output Current
AVOL1
gmEA1
—
60
—
VSS1 = 750 mV
550
750
950
VSS1 = 500 mV
275
400
525
µA/V
IEA1
—
±75
—
µA
Maximum Output Voltage
EA1VO(max)
1.10
1.45
1.85
V
Minimum Output Voltage
EA1VO(min)
—
—
300
mV
—
1
—
KΩ
COMP1 Pull Down Resistance
RCOMP1
HICCUP1 = 1 or FAULT1 = 1 or
VENBATx ≤ 2.2 V and VENB ≤0.8 V, latched until
VSS1 < VSS1RST
Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking).
Ensured by design and characterization, not production tested.
3 Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4 The lowest operating voltage is only valid if the conditions V
VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.
1
2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
ELECTRICAL CHARACTERISTICS – BUCK AND BUCK-BOOST PRE-REGULATOR SPECIFICATIONS (continued)1:
valid at 3.6 V 4 < VIN < 36 V, –40ºC < TA = TJ < 150ºC, unless otherwise specified.
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
4.6
—
5.5
V
Boost MOSFET (LG) Gate Driver
LG High Output Voltage
VLG,ON
VVIN = 6 V, VVREG = 5.35 V
LG Low Output Voltage
VLG,OFF
VVIN = 13.5 V, VVREG =5.35 V
—
0.2
0.4
V
LG Source Current 1
ILG,ON
VVIN =6 V, VVREG =5.35 V, VLG = 1 V
—
−300
—
mA
LG Sink Current 1
ILG,OFF
VVIN =13.5 V, VVREG = 5.35 V, VLG = 1 V
—
150
—
mA
—
400
—
mV
Soft Start
SS1 Offset Voltage
VSS1OFFS
VSS1 rising due to ISS1SU
SS1 Fault/Hiccup Reset Voltage
VSS1RST
VSS1 falling due to HICCUP1 = 1 or
FAULT1 = 1 or VENBATx ≤ 2.2 V and
VENB ≤ 0.8 V
140
200
275
mV
−10
−20
−30
µA
SS1 Startup (Source) Current
ISS1SU
VSS1 = 100 mV, HICCUP1 = FAULT1 = 0
SS1 Hiccup (Sink) Current
ISS1HIC
VSS1 = 0.5 V, HICCUP1 = 1
5
10
15
µA
SS1 Delay Time
tSS1,DLY
CSS1 = 22 nF
—
440
—
µs
SS1 Ramp Time
tSS1
CSS1 = 22 nF
—
880
—
µs
SS1 Pull Down Resistance
RPDSS1
FAULT1 = 1 or VENBATx ≤ 2.2 V and
VENB ≤ 0.8 V, latched until VSS1 < VSS1RST
—
3
—
kΩ
VVREG < 2.7 VTYP & VCOMP1 = EA1VO(max)
—
fOSC/4
—
—
SS1 PWM Frequency Foldback
fSW1,SS
VVREG < 2.7 VTYP
—
fOSC/2
—
—
VVREG > 2.7 VTYP
—
fOSC
—
—
VSS1 > VHIC1,EN, VVREG < 1.95 VTYP, VCOMP =
EA1VO(max)
—
30
—
PWM
cycles
VSS1 > VHIC1,EN, VVREG > 1.95 VTYP, VCOMP =
EA1VO(max)
—
120
—
PWM
cycles
tON = tON(MIN)
3.6
4.1
4.6
A
Latched OFF after 1 detection
7.5
10
—
A
Hiccup Mode
Hiccup1 OCP PWM Counts
tHIC1,OCP
Current Protections
Pulse by pulse current limit
LX1 Short Circuit Current Limit
ILIM1,ton(min)
ILIM,LX1
Missing Asynchronous Diode (D1) Protection
Detection Level
VD,OPEN
−1.50
−1.30
−0.80
V
Time Filtering
tD,OPEN
50
—
250
ns
2
Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking).
2 Ensured by design and characterization, not production tested.
3 Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4 The lowest operating voltage is only valid if the conditions V
VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.
1
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
A4410
ELECTRICAL CHARACTERISTICS – 1.25 V SYNCHRONOUS BUCK REGULATOR1: valid at 3.6 V 4 < VIN < 36 V, –40ºC <
TA = TJ < 150ºC, unless otherwise specified.
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
1.23
1.25
1.27
V
−
350
−
mV
−
65
105
ns
−
100
130
ns
−
15
−
ns
A/V
1V25 Output Voltage
Output Voltage Accuracy
V1V25
50 mA < I1V25 < 750 mA
Pulse Width Modulation (PWM)
PWM Ramp Offset
PWM2OFFS
High-Side MOSFET Minimum ONTime
tON(MIN)
High-Side MOSFET Minimum OFFTime
tOFF(MIN)
Gate Driver Non-Overlap Time 2
COMP2 to LX2 Current gain
VCOMP2 for 0% duty cycle
Does not include total gate driver non-overlap
time, tNO
tNO
gmPOWER2
Slope Compensation 2
SE2
−
2.5
−
fOSC = 2.0 MHz
0.45
0.63
0.81
fOSC = 400 kHz
0.12
0.14
0.19
TA = 25°C 3, IDS = 100 mA
−
200
235
mΩ
IDS = 100 mA
−
−
400
mΩ
VVREG = 5.5 V
−
12
−
ns
VENBATx ≤ 2.2 V and VENB ≤ 0.8 V, VLX2 = 0 V,
VVREG = 5.5 V, ‒40˚C < TJ < 85˚C 3
−
−
2
μA
VENBATx ≤ 2.2 V and VENB ≤ 0.8 V, VLX2 = 0 V,
VVREG = 5.5 V, −40°C < TJ < 150°C
−
3
15
μA
TA = 25°C 3, IDS = 100 mA
−
55
65
mΩ
IDS = 100 mA
−
−
110
mΩ
VENBATx ≤ 2.2 V and VENB ≤ 0.8 V,
VLX2 = 5.5 V, ‒40˚C < TJ < 85˚C 3
−
−
1
μA
VENBATx ≤ 2.2 V and VENB ≤ 0.8 V,
VLX2 = 5.5 V, −40°C < TJ < 150°C
−
8
20
μA
A/μs
Internal MOSFETs
High-Side MOSFET ON Resistance
LX2 Node Rise/Fall Time 2
High-Side MOSFET Leakage
RDSON (HS)
t R/F,LX2
1
Low-Side MOSFET ON Resistance
Low-Side MOSFET Leakage 1
IDSS (HS)
RDSON (LS)
IDSS (LS)
Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking).
Ensured by design and characterization, not production tested.
3 Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4 The lowest operating voltage is only valid if the conditions V
VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.
1
2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
ELECTRICAL CHARACTERISTICS – 1.25 V SYNCHRONOUS BUCK REGULATOR (continued)1: valid at 3.6 V 4 < VIN <
36 V, –40ºC < TA = TJ < 150ºC, unless otherwise specified.
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
1V25 Output Voltage
Open Loop Voltage Gain 2
Transconductance
Source & Sink Current
AVOL2
gmEA2
IEA2
−
60
−
dB
550
750
950
μA/V
0 V < VSS2 < 500 mV
–
250
–
μA/V
VCOMP2 = 1.5 V
−
±50
−
μA
ICOMP2 = 0 μA, VSS2 > 500 mV
Maximum Output Voltage
EA2VO(max)
1.00
1.25
1.50
V
Minimum Output Voltage
EA2VO(min)
–
–
150
mV
−
1.5
−
kΩ
120
200
270
mV
VSS2 falling due to HICCUP2 = 1 or
FAULT2 = 1 or VENBATx ≤ 2.2 V and
VENB ≤ 0.8 V
−
100
120
mV
COMP2 Pull Down Resistance
RCOMP2
HICCUP2 = 1 or FAULT2 = 1 or
VENBATx ≤ 2.2 V and VENB ≤ 0.8 V, latched until
VSS2 < VSS2RST
Soft Start
SS2 Offset Voltage
SS2 Fault/Hiccup Reset Voltage
VSS2OFFS
VSS2RST
VSS2 rising due to ISS2SU
SS2 Startup (Source) Current
ISS2SU
VSS2 = 1 V, HICCUP2 = FAULT2 = 0
−10
–20
−30
μA
SS2 Hiccup (Sink) Current
ISS2HIC
VSS2 = 0.5 V, HICCUP2 = 1
5
10
20
μA
SS2 to V1V2 Delay Time
tSS2,DLY
CSS2 = 10 nF
−
100
−
μs
V1V2 Soft Start Ramp Time
tSS2
CSS2 = 10 nF
−
400
−
μs
SS2 Pull Down Resistance
RPDSS2
FAULT2 = 1 or VENBATx ≤ 2.2 V and
VENB ≤ 0.8 V, latched until VSS2 < VSS2RST
−
2
−
kΩ
V1V25 < 315 mVTYP
−
fOSC/4
−
−
SS2 PWM Frequency Foldback
fSW2,SS
315 mVTYP < V1V25 < 740 mVTYP
−
fOSC/2
−
−
V1V25 > 740 mVTYP
−
fOSC
−
−
VSS2 rising
–
1.2
–
V
VSS2 > VHIC2,EN, V1V25 < 315 mVTYP
–
30
–
PWM
cycles
VSS2 > VHIC2,EN, V1V25 > 315 mVTYP
–
120
–
PWM
cycles
1.8
2.1
2.4
A
Hiccup Mode
Hiccup2 OCP Enable Threshold
Hiccup2 OCP Counts
VHIC2,EN
tHIC2,OCP
Current Protections
Pulse-by-Pulse Current Limit
ILIM2,ton(min)
tON = tON(MIN)
Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking).
2 Ensured by design and characterization, not production tested.
3 Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4 The lowest operating voltage is only valid if the conditions V
VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.
1
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
A4410
ELECTRICAL CHARACTERISTICS – LINEAR REGULATOR (LDO) SPECIFICATIONS 1: valid at 3.6 V 4 < VIN < 36 V,
–40ºC < TA = TJ < 150ºC, unless otherwise specified.
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
4.9
5.0
5.1
V
1.0
–
22
µF
4.9
5.0
5.1
V
1.6
2.2
4.1
µF
VV5x,MIN1
VVCP = 9 V, TRACK = 1, IV5 = 25 mA,
IV5P = 80 mA, I3V3 = 150 mA, I1V25 = 700 mA
(192 mA to VREG)
1) TA = 150ºC, VVIN = 5.12 V, VVREG = 5.01 V
2) TA = ‒40ºC 2, VVIN = 5.12 V, VVREG = 5.06 V
4.85
–
–
VV5x,MIN2
VVCP = 8.5 V, TRACK = 1, IV5 = 25 mA,
IV5P = 80 mA, I3V3 = 150 mA, I1V25 = 700 mA
(213 mA to VREG)
1) TA = 150ºC, VVIN = 4.50 V, VVREG = 4.39 V
2) TA = ‒40ºC 2, VVIN = 4.50 V, VVREG = 4.44 V
4.25
–
–
VV5P ÷ V3V3
1.505
1.515
1.525
–
V5 and V5P Linear Regulators
V5 Accuracy & Load Regulation
VV5
V5 Output Capacitance Range 2
COUT,V5
V5P Accuracy & Load Regulation
V5P Output Capacitance 2
VV5P
10 mA < IV5 < 155 mA, VVREG = 5.25 V
10 mA < IV5P < 255 mA, VVREG = 5.25 V
COUT,V5P
V5 and V5P Minimum Output Voltage2
V
V5P Tracking
V5P/3V3 Tracking Ratio
V5P/3V3 Tracking Accuracy
TRACK3V3
3.0 V < V3V3 < 3.3 V, TRACK = 1,
I3V3 = IV5P = 75 mA
−0.66
–
+0.66
%
V5P/V5 Tracking Accuracy
TRACKV5
3.5 V < VV5 < 5.0 V, TRACK = 0,
IV5P = IV5 = 75 mA
−35
–
+35
mV
V5P Over Current Protection
V5P Current Limit 1
V5PILIM
VV5P = 5 V
−285
−400
–
mA
V5P Foldback Current 1
V5PIFBK
VV5P = 0 V
−60
−115
−170
mA
V5ILIM
VV5 = 5 V
−175
−245
–
mA
V5IFBK
VV5 = 0 V
−35
−70
−105
mA
V5 Over Current Protection
V5 Current Limit 1
V5 Foldback Current
1
V5P & V5 Startup Timing
V5P Startup Time 2
CV5P ≤ 2.9 µF, Load = 25 Ω ±5% (200 mA)
–
0.17
0.60
ms
V5 Startup Time 2
CV5 ≤ 2.9 µF, Load = 33 Ω ±5% (150 mA)
–
0.24
1.0
ms
Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking).
Ensured by design and characterization, not production tested.
3 Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4 The lowest operating voltage is only valid if the conditions V
VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.
1
2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
A4410
ELECTRICAL CHARACTERISTICS – CONTROL INPUTS 1: valid at 3.6 V 4 < VIN < 36 V, –40ºC < TA = TJ < 150ºC, unless
otherwise specified.
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
3.23
3.30
3.37
V
1.0
–
22
µF
V3V3,MIN1
VVCP = 9 V, TRACK = 1, IV5 = 25 mA,
IV5P = 80 mA, I3V3 = 150 mA, I1V25 = 700 mA
(192 mA to VREG)
1) TA = 150ºC, VVIN = 5.12 V, VVREG = 5.01 V
2) TA = ‒40ºC 2, VVIN = 5.12 V, VVREG = 5.06 V
3.23
3.30
–
V3V3,MIN2
VVCP = 8.5 V, TRACK = 1, IV5 = 25 mA,
IV5P = 80 mA, I3V3 = 150 mA, I1V25 = 700 mA
(213 mA to VREG)
1) TA = 150ºC, VVIN = 4.50 V, VVREG = 4.39 V
2) TA = ‒40ºC 2, VVIN = 4.50 V, VVREG = 4.44 V
3.15
3.30
–
3V3ILIM
V3V3 = 3.3 V
−185
−260
–
mA
3V3IFBK
V3V3 = 0 V
−40
−75
−130
mA
–
0.17
0.55
ms
3V3 Linear Regulator
3V3 Accuracy & Load Regulation
V3V3
3V3 Output Capacitance Range 2
COUT,3V3
3V3 Minimum Output Voltage 2
10 mA < I3V3 < 165 mA, VVREG = 5.25 V
V
3V3 Over Current Protection
3V3 Current Limit 1
3V3 Foldback Current
1
3V3 Startup Timing
3V3 Startup Time 2
C3V3 ≤ 2.9 µF, Load = 33 Ω ±5% (100 mA)
Ignition Enable (ENBAT1 and ENBAT2) Inputs
ENBAT1, ENBAT2 Thresholds
ENBAT1, ENBAT2 Hysteresis
ENBAT1, ENBAT2 Bias Current 1
ENBAT1, ENBAT2 Pull-Down
Resistance
VENBATx,H
VENBATx rising
2.9
3.3
3.5
V
VENBATx,L
VENBATx falling
2.2
2.6
2.9
V
VENBATx,H – VENBATx,L
–
700
–
mV
TJ = 25°C 3, VENBATx = 3.51 V
–
28
45
TJ = 150°C, VENBATx = 3.51 V
–
35
55
RENBATx
VENBATx < 1.2 V
–
650
–
kΩ
VENB,H
VENB rising
–
–
2.0
V
VENBATx,HYS
IENBATx,BIAS
µA
Logic Enable (ENB) Input
ENB Thresholds
VENB,L
VENB falling
0.8
–
–
V
ENB Bias Current 1
IENB,IN
VENB = 3.3 V
–
–
175
µA
ENB Resistance
RENB
–
60
–
kΩ
EN td,FILT
10
15
20
µs
15
50
100
µs
ENB/ENBATx Filter/Deglitch
Enable Filter/Deglitch Time
ENB/ENBATx Shutdown Delay
LDO Shutdown Delay
td LDO,OFF
Measure tdLDO,OFF from the falling edge of
ENB and ENBAT1 and ENBAT2 to the time
when all LDOs begin to decay
Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking).
Ensured by design and characterization, not production tested.
Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4 The lowest operating voltage is only valid if the conditions V
VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.
1
2
3
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
A4410
ELECTRICAL CHARACTERISTICS – CONTROL INPUTS (continued) 1: valid at 3.6 V 4 < VIN < 36 V, –40ºC < TA = TJ <
150ºC, unless otherwise specified.
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
TRACK Input
TRACK Thresholds
TRACK Bias Current
1
VTH
VTRACK rising
–
–
2.0
V
VTL
VTRACK falling
0.8
–
–
V
–
−100
–
µA
No external SYNC signal
–
800
–
mV
PWM switching disabled upon detection
–
3
–
µs
PWM switching disabled upon detection
–
3
–
µs
IBT
FSET/SYNC Input
FSET/SYNC Pin Voltage
VFSET/SYNC
FSET/SYNC Open Circuit (Under
Current) Detection Time
VFSET/
SYNC,UC
FSET/SYNC Short Circuit (Over
Current) Detection Time
SYNC,OC
VFSET/
Sync. High Threshold
SYNCVIH
VSYNC rising
–
–
2.0
V
Sync. Low Threshold
SYNCVIL
VSYNC falling
0.5
–
–
V
Sync. Input Duty Cycle
DCSYNC
–
–
80
%
Sync. Input Pulse Width
twSYNC
200
–
–
ns
Sync. Input Transition Times 2
ttSYNC
–
10
15
ns
VSLEW
–
800
–
mV
SLEW Input
SLEW Pin Operating Voltage
SLEW Pin Open Circuit (Under
Current) Detection Time
VSLEW,UC
PWM latched off upon detection
–
3
–
µs
SLEW Pin Short Circuit (Over
Current) Detection Time
VSLEW,OC
PWM latched off upon detection
–
3
–
µs
–
−100
–
nA
SLEW Bias Current 1
ISLEW
Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking).
2 Ensured by design and characterization, not production tested.
3 Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4 The lowest operating voltage is only valid if the conditions V
VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.
1
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
ELECTRICAL CHARACTERISTICS – DIAGNOSTIC OUTPUTS 1: valid at 3.6 V 4 < VIN < 36 V, –40ºC < TA = TJ < 150ºC, unless otherwise specified.
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
NPOR OV/UV Protection Thresholds
3V3 OV Thresholds
3V3 OV Hysteresis
3V3 UV Thresholds
3V3 UV Hysteresis
1V25 OV Thresholds
1V25 OV Hysteresis
1V25 UV Thresholds
1V25 UV Hysteresis
V3V3,OV,H
V3V3 rising
3.41
3.51
3.60
V3V3,OV,L
V3V3 falling
–
3.49
–
V3V3,OV,HYS
V3V3,OV,H – V3V3,OV,L
10
20
40
V3V3,UV,H
V3V3 rising
–
3.12
–
V3V3,UV,L
V3V3 falling
3.00
3.10
3.19
10
20
40
V3V3,UV,HYS
V3V3,UV,H – V3V3,UV,L
V1V25,OV,H
V1V25 rising
1.29
1.32
1.35
V1V25,OV,L
V1V25 falling
–
1.31
–
V3V3,OV,HYS
V
mV
V
mV
V
V1V25,OV,H – V1V25,OV,L
5
10
20
V1V25,UV,H
V1V25 rising, triggers turn on of LDOs
–
1.19
–
V1V25,UV,L
V1V25 falling
1.15
1.18
1.21
5
10
20
mV
V3V3,UV,HYS
V1V25,UV,H – V1V25,UV,L
mV
V
NPOR Turn-on and Turn-off Delays
NPOR Turn-on Delay
NPOR Turn-off Propagation Delay
tdNPOR,ON
tdNPOR,OFF
12
15
18
ms
ENB and ENBAT1 and ENBAT2 low to NPOR
low
–
15
23
µs
ENB or ENBAT1 or ENBAT2 high, VIN ≥ 2.5 V,
INPOR = 4 mA
–
150
400
ENB or ENBAT1 or ENBAT2 high, VIN = 1.5 V,
INPOR = 2 mA
–
–
800
VNPOR = 3.3 V
–
–
2
µA
NPOR Output Voltages
NPOR Output Low Voltage
NPOR Leakage Current 1
VNPOR,L
INPOR,LKG
mV
NPOR and POK5V OV Delay Time
Over Voltage Detection Delay
tdOV
V5P, V5, 3V3, and 1V25 over voltage detection
delay time, WDENn = 0
6.40
8.00
9.60
ms
tdFILT
Applies to under-voltage of the 3V3, 1V25, V5,
and V5P voltages
10
15
20
µs
NPOR and POK5V UV Filtering/Deglitch
UV Filter/Deglitch Times
Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking).
Ensured by design and characterization, not production tested.
3 Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4 The lowest operating voltage is only valid if the conditions V
VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.
1
2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
15
A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
ELECTRICAL CHARACTERISTICS – DIAGNOSTIC OUTPUTS (continued) 1: valid at 3.6 V 4 < VIN < 36 V, –40ºC < TA = TJ
< 150ºC, unless otherwise specified.
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
POK5V OV/UV Protection Thresholds
V5 OV Thresholds
V5 OV Hysteresis
V5 UV Thresholds
VV5,OV,H
VV5 rising
5.15
5.33
5.50
VV5,OV,L
VV5 falling
–
5.30
–
VV5,OV,HYS
VV5,OV,H – VV5,OV,L
15
30
50
VV5,UV,H
VV5 rising
–
4.71
–
VV5,UV,L
VV5 falling
4.50
4.68
4.85
15
30
50
mV
V
V5 UV Hysteresis
VV5,UV,HYS
VV5,UV,H – VV5,UV,L
V5P Output Disconnect Threshold
VV5P,DISC
VV5P rising
–
7.2
–
VV5P,OV,H
VV5P rising
5.15
5.33
5.50
VV5P,OV,L
VV5P falling
–
5.30
–
VV5P,OV,H – VV5P,OV,L
15
30
50
V5P OV Thresholds
V5P OV Hysteresis
V5P UV Thresholds
V5P UV Hysteresis
V
VV5P,OV,HYS
VV5P,UV,H
VV5P rising
–
4.71
–
VVP5,UV,L
VV5P falling
4.50
4.68
4.85
VV5P,UV,H – VV5P,UV,L
15
30
50
ENB = 1 or ENBAT1 = 1 or ENBAT2 = 1,
VVIN ≥ 2.5 V, IPOK5V = 4 mA
–
150
400
ENB = 1 or ENBAT1 = 1, ENBAT2 = 1,
VVIN = 1.5 V, IPOK5V = 2 mA
–
–
800
IPOK5V,LKG
VPOK5V = 3.3 V
–
–
2
VREGOV,H
VVREG rising, LX1 PWM disabled
5.70
5.95
6.20
VREGOV,L
VVREG falling, LX1 PWM enabled
–
5.85
–
VREGOV,H – VREGOV,L
–
100
–
VV5P,UV,HYS
mV
V
V
mV
V
mV
POK5V Output Voltages
POK5V Output Voltage
POK5V Leakage Current
VPOK5V,L
mV
µA
VREG, VCP, and BG Thresholds
VREG OV Thresholds
VREG OV Hysteresis
VREG UV Thresholds
VREGOV,
HYS
VVREG rising, triggers rise of SS2
4.14
4.38
4.62
VREGUV,L
VVREG falling
–
4.28
–
VREGUV,H – VREGUV,L
–
100
–
mV
V
VREGUV,
VCP OV Thresholds
VCPOV,H
VVCP rising, latches all regulators off
11.0
12.5
14.0
VCPUV,H
VVCP rising, PWM enabled
2.95
3.15
3.35
VCPUV,L
VVCP falling, PWM disabled
–
2.8
–
VCP UV Hysteresis
BGREF & BGFAULT UV Thresholds 2
mV
VREGUV,H
VREG UV Hysteresis
VCP UV Thresholds
V
HYS
VCPUV,HYS
V
–
350
–
mV
BGVREF or BGFAULT rising
1.00
1.05
1.10
V
VENBATxS,H
VENBATx rising
2.9
3.3
3.5
V
VENBATxS,L
VENBATx falling
2.2
2.6
2.9
V
IENBATS = 4 mA
–
–
400
mV
VENBATS = 3.3 V
–
–
1
µA
BGxUV
VCPUV,H – VCPUV,L
V
Ignition Status (ENBAT1S and ENBAT2S)
ENBATxS Thresholds
ENBATxS Output Voltage
ENBATxS Leakage Current (1)
VOENBATxS,
LO
IENBATxS
Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking).
2 Ensured by design and characterization, not production tested.
3 Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4 The lowest operating voltage is only valid if the conditions V
VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.
1
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
A4410
ELECTRICAL CHARACTERISTICS – WINDOW WATCHDOG TIMER (WWDT) 1: valid at 3.6 V 4 < VIN < 36 V, –40ºC < TA =
TJ < 150ºC, unless otherwise specified.
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
WD Enable\ Input (WDENn)
WDENn Voltage Thresholds
WDENn Input Resistance
WDENn,LO
VWDENn falling, WDT enabled
0.8
–
–
V
WDENn,HI
VWDENn rising, WDT disabled
–
–
2.0
V
–
60
–
kΩ
RWD,ENn
WDIN Voltage Thresholds & Current
WDIN Input Voltage Thresholds
WDIN Input Current 1
WDIN,LO
VWD,IN falling, WDADJ pulled low by RADJ
WDIN,HI
VWD,IN rising, WDADJ charging
WDI,IN
VWD,IN = 5 V
0.8
–
–
V
–
–
2.0
V
−10
±1
10
µA
Hz
WDIN Timing Specifications
WDIN Frequency
WDIN,FREQ
–
–
750
WDIN Duty Cycle
WDIN,DUTY
20
50
80
%
WDSTART,DLY
24
30
36
ms
1.0
–
25
ms
ms
Watchdog Activation Delay
WD Programming (WDADJ)
WD Timeout FAST Range 2
WD Timeout SLOW Range
2
—
WD Timeout, FAST Clock
WDTO,FAST
WD Timeout, SLOW Clock
WDTO,SLOW
4.0
–
100
RADJ = 13 kΩ
0.8
1.0
1.2
RADJ = 324 kΩ
20
25
30
RADJ = 13 kΩ
3.2
4.0
4.8
RADJ = 324 kΩ
80
100
120
1.6
2.0
2.4
ms
ms
WD One-Shot Time
WD Pulse Time after a WD Fault
tWD,FAULT
ms
Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking).
2 Ensured by design and characterization, not production tested.
3 Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4 The lowest operating voltage is only valid if the conditions V
VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.
1
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
17
A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
FUNCTIONAL DESCRIPTION
Overview
The pre-regulator provides protection and diagnostic functions.
The A4410 is a power management IC designed for automotive applications. It contains a pre-regulator plus four DC post
regulators to create the voltages necessary for typical automotive applications such as electrical power steering and automatic
transmission control.
1.
2.
3.
4.
5.
6.
The pre-regulator can be configured as a buck or buck boost
regulator. Buck boost is required for applications that need to
work with extremely low battery voltages. This pre-regulator
generates a fixed 5.35 V and can deliver up to 1.2 A to power the
internal or external post-regulators. These post-regulators generate the various voltage levels for the end system.
Over voltage protection
High voltage rating for load dump
Switch node to ground short circuit protection
Open freewheeling diode protection
Pulse-by-pulse current limit
Hiccup mode short circuit protection (shown below)
The A4410 includes four internal post regulators; three linear
regulators and one fixed output synchronous buck regulator.
Buck-Boost Pre-Regulator (VREG)
The pre-regulator incorporates an internal high side buck switch
and a boost switch gate driver. An external freewheeling diode
and LC filter are required to complete the buck converter. By
adding a MOSFET and boost diode the boost functionality can
maintain all outputs with input voltages down to 2.8 V. The
A4410 includes a compensation pin (COMP1) and a soft-start pin
(SS1) for the pre-regulator.
Figure 2: Pre-regulator Hiccup Mode when VREG is
Shorted to GND
CH1 = VREG, CH2 = COMP1, CH3 = SS1, CH4 = IL1, 1 ms/DIV
Synchronous Buck Regulator (1V25)
The A4410 integrates the high-side and low-side MOSFETs necessary for implementing a 1.25 V/750 mADC/1 APEAK synchronous buck regulator. The synchronous buck is powered by the
5.35 V pre-regulator output. An LC filter is required to complete
the synchronous buck regulator. The A4410 includes a compensation pin (COMP2) and a soft-start pin (SS2) for the synchronous buck.
Protection and safety functions provided by the synchronous
buck are:
Figure 1: Performance for Representative VIN
Start/Stop Transients
VINTYP = 12 V, VINMIN = 4 V, 20 ms/DIV
1.
2.
3.
4.
5.
Under voltage detection
Over voltage detection
Switch node to ground short circuit protection
Pulse-by-pulse current limit
Hiccup mode short circuit protection (shown below)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
18
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
A4410
All linear regulators provide the following protection features;
1. Under voltage and over voltage detection
2. Current limit with fold back short circuit protection
The protected 5 V regulator (V5P) includes protection against
accidental short circuit to the battery voltage. This makes this
output most suitable for powering remote sensors or circuitry via
a wiring harness where short to battery is possible.
Tracking Input (TRACK)
The V5P LDO is a tracking regulator. It can be set to use either
V5 or 3V3 as its reference by setting the TRACK input pin to
a logic low or high. If the TRACK input is left unconnected an
internal current source will set the TRACK pin to a logic high.
CH1=VOUT, CH2=COMP1, CH3=SS1, CH4=IL1, 500 µs/DIV
SEL
TRACK
V5P
REFERENCE
100 µA
Low Dropout Linear Regulators (LDOs)
The A4410 has three low dropout linear regulators (LDOs), one
3.3 V/160 mAMAX (3V3), one 5 V/150 mAMAX (V5), and one
high-voltage protected 5 V/250 mAMAX (V5P). The switching
pre-regulator efficiently regulates the battery voltage to an intermediate value to power the LDOs. This pre-regulator topology
reduces LDO power dissipation and junction temperature.
5V
TRACKING
LDO
VREG
Figure 3: Synchronous Buck Hiccup Mode when VOUT
is Shorted to GND
2:1
MUX
1
0
V5
3V3
Figure 5: TRACK Input Circuit
Window Watchdog Timer (WDT)
The A4410s window watchdog circuit monitors an external clock
applied to the WDIN pin. This clock should be generated by the
micro-controller or DSP. The time between rising edges of the
clock must fall within an acceptable “window” or a watchdog
fault is generated. A watchdog fault will set NPOR for tWD,FAULT
(typically 2 ms). A watchdog fault will occur if the time between
rising edges is either too short (a FAST fault) or too long (a
SLOW fault).
Vx
100%
WDADJ
CLKIN
WDENn
RADJ
WD
OSC
WDCLK
WDIN
WINDOW
WATCHDOG
TIMER
WDFAULT
WDENn
WDSTART
Ix
IFBKmin IFBKtyp
ILIMmin
ILIMtyp
Figure 6: Window Watchdog Timer
Figure 4: LDO Foldback Protection
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
19
A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
The watchdogs time “window” is programmable via the WDADJ
pin according to the following equations:
WDTO,FAST = WDTO,SLOW / 4
Where WDTO,SLOW is the nominal watchdog timeout (in ms)
and RADJ is the required external resistor value (in kΩ) from the
WDADJ pin to ground. Typical watchdog operation and FAST
and SLOW fault conditions are shown in Figures 13a and 13b.
The watchdog is enabled if two conditions are met: (1) the
WDENn pin is a logic low and (2) all the regulators (1V25, 3V3,
V5, and V5P) have been above their under voltage thresholds for
at least 30 msTYP (WDSTART,DLY).
After startup, if no clock edges are detected at WDIN for at least
WDSTART,DLY + WDTO,SLOW the A4410 will set NPOR low for
tWD,FAULT and reset its counters. This process will repeat until the
system recovers and clock edges are applied to WDIN. A timing
diagram for the “missing clock” situation is shown in Figure 13c.
Dual Band Gaps (BGVREF, BGFAULT)
Dual band gaps, or references, are implemented within the
A4410. One band gap (BGVREF) is dedicated solely to closed
loop control of the output voltages. The second band gap
(BGFAULT) is employed for fault monitoring functions. Having
redundant band gaps improves reliability of the A4410.
If the reference band gap is out of specification (BGVREF) then
the output voltages will be out of specification and the monitoring band gap will report a fault condition by setting NPOR and/or
POK5V low.
If the monitoring band gap is out of specification (BGFAULT) then
the outputs will remain in regulation but the monitoring circuits
will report a fault condition by setting NPOR and/or POK5V low.
The reference and monitoring band gap circuits include two,
smaller secondary band gaps that are used to detect under voltage
of the main band gaps during power-up.
Adjustable Frequency and Synchronization
(FSET/SYNC)
The PWM switching frequency of the A4410 is adjustable from
250 kHz to 2.4 MHz. Connecting a resistor from the FSET/
SYNC pin to ground sets the switching frequency. An FSET
resistor with ±1% tolerance is recommended. The FSET resistor
can be calculated using the following equation:
(
fOSC
12724
-1.175
)
Where RFSET is in kΩ and fOSC is the desired oscillator (PWM)
frequency in kHz.
A graph of switching frequency versus FSET resistor values is
shown below.
2250
Oscillator Frequency (kHz)
RADJ = 3.240 * WDTO,SLOW
RFSET =
2000
1750
1500
1250
1000
750
500
250
5
10
15
20
25
30
35
40
45
50
55
60
RFSET (kΩ)
Figure 7: Switching Frequency vs. FSET Resistor
Values
The PWM frequency of the A4410 may be increased or decreased
by applying a clock to the FSET/SYNC pin. The clock must satisfy the voltage thresholds and timing requirements shown in the
electrical characteristics table.
Frequency Dithering and LX1 Slew Rate Control
The A4410 includes two innovative techniques to help reduce
EMI/EMC for demanding automotive applications.
First, the A4410 performs pseudo-random dithering of the PWM
frequency. Dithering the PWM frequency spreads the energy
above and below the base frequency set by RFSET. A typical fixedfrequency PWM regulator will create distinct “spikes” of energy
at fOSC, and at higher frequency multiples of fOSC. Conversely,
the A4410 spreads the spectrum around fOSC thus creating a lower
magnitude at any comparative frequency. Frequency dithering is
disabled if SYNC is used or VIN drops below approximately
8.3 V.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
20
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
A4410
Second, the A4410 includes a pin to adjust the turn on slew rate
of the LX1 pin by simply changing the value of the resistor from
the SLEW pin to ground. Slower rise times of LX1 reduce ringing and high frequency harmonics of the regulator. The rise time
may be adjusted to be quite long and will increase thermal dissipation of the pre-regulator if set too slow. Typical values of rise
time versus RSLEW are
Table 1: RSLEW vs. Rise Time
RSLEW (kΩ)
LX1 Rise Time (ns)
8.66
7
44.2
11
100
20
charge pump cycle the voltage on the flying capacitor charges the
VCP capacitor. For most conditions the VCP minus VIN voltage
is regulated to approximately 6.5 V.
The charge pump can provide enough current to operate the preregulator and the LDOs at full load provided VIN is greater than
6.0 V. Optional components D3, D4, and CP3 must be included
if VIN drops below 6.0 V. Diode D3 should be a silicon diode
rated for at least 200 mA/50 V with less than 50 µA of leakage
current when VR = 13 V and TA = 125ºC. Diode D4 should be a
1 A schottky diode with a very low forward voltage (VF) rated to
withstand at least 30 V.
CP2
0.22 µF
Bias Supply (VCC)
The bias supply (VCC) is generated by an internal linear regulator. This supply is the first rail to start up. Most of the internal
control circuitry is powered by this supply. The bias supply
includes some unique features to ensure reliable operation of the
A4410. These features include;
1.
2.
3.
4.
Input voltage (VIN) under voltage lockout
Under voltage detection
Short-to-ground protection
Operation from either VIN or VREG for low battery voltage
operation
Charge Pump (VCP, CP1, CP2)
A charge pump provides the voltage necessary to drive the highside n-channel MOSFETs in the pre-regulator and the linear
regulators.
Two external capacitors are required for charge pump operation. During the first half of the charge pump cycle, the flying
capacitor between pins CP1 and CP2, is charged from either VIN
or VREG, whichever is highest. During the second half of the
Required if VREG
is fully loaded and
VVIN < 6.0 V
CP2
Three enable pins are available on the A4410. A high signal on
any of these pins enables the A4410. One enable (ENB) is logic
level compatible for micro-controller control. The other inputs
(ENBAT1 and ENBAT2) must be connected to the ignition (IGN)
or accessory (ACC) switch through a relatively low value series
resistance, 2 kΩ – 3.6 kΩ. For transient suppression it is recommended that a 0.1 µF – 0.22 µF capacitor be placed after the
series resistance to form a low pass filter for the ENBAT1 and
ENBAT2 pins as shown in the Applications Schematic.
CP1
Enable Inputs (ENB, ENBAT1, ENBAT2)
D4
MSS1P5
D3
BAS16J
CP3
0.1 µF/50 V
LX1
LX1
LG
Figure 8: Charge Pump Circuit
The charge pump incorporates some protection features;
1. Under voltage lockout of PWM switching
2. Over voltage “latched” shutdown of the A4410
Startup and Shutdown Sequences
The startup and shutdown sequences of the A4410 are fixed.
If no faults exist and ENBAT1 or ENBAT2 or ENB transition
high the A4410 will perform its startup routine. If ENBAT1 and
ENBAT2 and ENB are low for at least ENtd,FILT + tdLDO, OFF
(typically 65 µs) the A4410 will enter a shutdown sequence. The
startup and shutdown sequences are summarized in Table 2 and
shown in a timing diagram in Figure 9.
Fault Reporting (NPOR, POK5V)
The A4410 includes two open-drain outputs for error reporting.
The NPOR pin monitors the 1V25 and 3V3 outputs for under and
over voltage. The POK5V pin monitors the V5 and V5P pin for
under and over voltage.
The NPOR pin incorporates a 15 ms delay after both the 1V25
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
21
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
A4410
and 3V3 outputs have risen above their under voltage thresholds.
This relatively long delay allows the micro-controller plenty of
time to power-up and complete its initialization. There is virtually
no NPOR delay if either the 1V25 or 3V3 falls below the under
voltage threshold. The NPOR pin incorporates an 8 ms delay if
either of the 1V25 or 3V3 outputs exceeds its over voltage threshold.
There are no significant delays on the POK5V output after V5
and V5P have risen above or fallen below their under voltage
thresholds. Similar to the NPOR pin, the POK5V pin incorporates
an 8 ms delay if either the V5 or V5P outputs exceed its over
voltage threshold.
The fault modes and their effects on NPOR and POK5V are covered in detail in Table 3.
OV/UV DETECT
& DELAYS
NPOR
WDFAULT
WDSTART
TSD
CLK1MHz
OV/UV DETECT
& DELAYS
POK5V
The V5P monitor is a bit unique. If V5P is accidently connected
to the battery voltage then POK5V will bypass the normal 8 ms
over voltage delay and set itself low immediately.
DEGLITCH
tdFILT
RST
REF
ON/OFF
3.3 V
V5
V5P
V5PDISC
REF
BGFAULT
DEGLITCH
tdFILT
1.25 V
Figure 9: Fault Reporting Circuit
Table 2: Startup and Shutdown Logic (signal names consistent with Functional Block Diagram)
Regulator Control Bits
(0=OFF, 1=ON)
A4410 Status Signals
A4410
MODE
EN
MPOR
VREG UV
1V25 UV
3xLDO UV
VREG ON
1V25 ON
LDOs ON
X
1
X
X
X
0
0
0
0
0
1
1
1
0
0
0
OFF
1
0
1
1
1
1
0
0
STARTUP
1
0
0
1
1
1
1
0
↓
1
0
0
0
1
1
1
1
↓
1
0
0
0
0
1
1
1
RUN
RESET
0
0
0
0
1
1
1
0
0
0
0
0
1
1
0
SHUTTING
DOWN
0
0
0
0
1
1
0
0
↓
0
0
0
1
1
0
0
0
↓
0
0
1
1
1
0
0
0
OFF
TIME
0
DEGLITCH +
DELAY
X = DON’T CARE
EN = ENBAT1 + ENBAT2 + ENB
3xLDO UV = 3V3 + V5_UV + V5P_UV
MPOR = VCC_UV + VCP_UP + BG1_UV + BG2_UV + SLEW_UV/OV (latched) +FSET_UV/OV + TSD + VCP_OV (latched) +
D1MISSING (latched) + ILIM,LX1 (latched)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
22
A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
Table 3: Summary of Fault Mode Operation
FAULT TYPE and
CONDITION
A4410 RESPONSE TO FAULT
NPOR
POK5V
LATCHED
FAULT?
RESET METHOD
V5P short to VBAT
POK5V goes low when V5P disconnect occurs, if the fault
persists longer than tdOV then set NPOR low and turn off all
regulators
Low if fault
lasts more
than tdOV
Low when
V5P
disconnect
occurs
NO
Check for short
circuits on V5P
V5, V5P over voltage
If OV condition persists for more than tdOV then set POK5V
low
Not
effected
Low
NO
Check for short
circuits on V5 or
V5P
3V3 or 1V25 over
voltage
If OV condition persists for more than tdOV then set NPOR
low and shut off all regulators
Low
Low if fault
lasts more
than tdOV
YES
Check for short
circuits then cycle
EN or VIN
V5 or V5P under voltage
Closed loop control will try to raise the voltage but may be
constrained by the foldback current limit
Not
effected
Low
NO
Decrease the
load
3V3 or 1V25 under
voltage
Closed loop control will try to raise the voltage but may be
constrained by the foldback or pulse-by-pulse current limit
Low
Not
effected
NO
Decrease the
load
V5 or V5P over current
Foldback current limit will reduce the output voltage
Not
effected
Low if V5
or V5P are
too low
NO
Decrease the
load
3V3 over current
Foldback current limit will reduce the output voltage
Low if 3V3
< V3V3,UV,L
Not
effected
NO
Decrease the
load
FB1V25 shorted to ground
VSS2 < VHIC2,EN, V1V25 <
470 mV
Continue to PWM but turn off LX2 when the high side
MOSFET current exceeds ILIM2
Low
Not
effected
NO
Remove the short
circuit
1V25 over current VSS2
> VHIC2,EN & V1V25 <
470 mV
Enters hiccup mode after 30 OCP faults
Low
Not
effected
NO
Decrease the
load
1V25 over current VSS2
> VHIC2,EN & V1V25 >
470 mV
Enters hiccup mode after 120 OCP faults
Low if 1V25
< V1V25,UV,L
Not
effected
NO
Decrease the
load
VREG pin open circuit
VREG will decay to 0 V, LX1 will switch at maximum duty
cycle so the voltage on the output capacitors will be very
close to VBAT
Low if 3V3
or 1V25 are
too low
Low if V5
or V5P are
too low
NO
Connect the
VREG pin
VREG over current
VVREG < 1.95 V &
VCOMP1 = EA1VO(MAX)
Enters hiccup mode after 30 OCP faults
Low
Low
NO
Decrease the
load
VREG over current
VVREG > 1.95 V &
VCOMP1 = EA1VO(MAX)
Enters hiccup mode after 120 OCP faults
Low if 3V3
or 1V25 are
too low
Low if V5
or V5P are
too low
NO
Decrease the
load
VREG over voltage
VREGOV,H1 < VVREG
Stop PWM switching of LX1
Low if 3V3
or 1V25 are
too low
Low if V5
or V5P are
too low
NO
None
VREG asynchronous
diode (D1) missing
Results in an MPOR after 1 detection, so all regulators are
shut off
Low if 3V3
or 1V25 are
too low
Low if V5
or V5P are
too low
YES
Place D1 then
cycle EN or VIN
Asynchronous diode
(D1) short circuited or
LX1 shorted to ground
Results in an MPOR after the high side MOSFET current
exceeds ILIM,LX1 so all regulators are shut off
Low if 3V3
or 1V25 are
too low
Low if V5
or V5P are
too low
YES
Remove the short
then cycle EN or
VIN
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23
A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
Table 3: Summary of Fault Mode Operation (continued)
FAULT TYPE and
CONDITION
A4410 RESPONSE TO FAULT
NPOR
POK5V
LATCHED
FAULT?
RESET METHOD
Slew pin open circuit
(SLEW_UC)
Results in an MPOR, so all regulators are shut off
Low
Low
YES
Connect SLEW
pin then cycle EN
or VIN
Slew pin shorted to
ground (SLEW_OC)
Results in an MPOR, so all regulators are shut off
Low
Low
YES
Remove the short
then cycle EN or
VIN
The A4410 operates at a default oscillator frequency of 450
kHz. If the fault occurs before power up: 1V25 and 3 LDOs
are OFF. VREG (unloaded) runs in pulse skipping mode.
Low
Low
The A4410 operates at a default oscillator frequency of
450 kHz. If the fault occurs after power up: 1V25 is OFF and
3 LDOs are ON.
NO
Low
High
Remove the short
circuit or connect
the pin
Charge pump (VCP)
over voltage
Results in an MPOR, so all regulators are shut off
Low
Low
YES
Check VCP/
CP1/CP2 pins &
components, then
cycle EN or VIN
Charge pump (VCP)
under voltage
Results in an MPOR, so all regulators are shut off
Low
Low
NO
Check VCP/CP1/
CP2 pins and
components
VCP pin open circuit
Results in VCP_UV and an MPOR, so all regulators are
shut off
Low
Low
NO
Connect the VCP
pin
VCP pin shorted to
ground
Results on high current from the charge pump and
(intentional) fusing of an internal trace. Also results in
MPOR so all regulators are shut off.
Low
Low
NO
Remove the
short circuit
and replace the
A4410
CP1 or CP2 pin open
circuit
Results in VCP_UV and an MPOR, so all regulators are
shut off
Low
Low
NO
Connect the CP1
or CP2 pins
CP1 pin shorted to
ground
Results in VCP_UV and an MPOR, so all regulators are
shut off
Low
Low
NO
Remove the short
circuit
CP2 pin shorted to
ground
Results on high current from the charge pump and
(intentional) fusing of an internal trace. Also results in
MPOR so all regulators are shut off.
Low
Low
NO
Remove the
short circuit
and replace the
A4410
BGVREF or BGFAULT
under voltage
Results in an MPOR, so all regulators are shut off
Low
Low
NO
Raise VIN or wait
for BGs to power
up
BGVREF or BGFAULT over
voltage
If BGVREF is too high, all regulators will appear to be OV
(because BGFAULT is good). If BGFAULT is too high, all
regulators will appear to be UV (because BGVREF is good)
Low
Low
NO
Replace the
A4410
VCC under voltage or
shorted to ground
Results in an MPOR, so all regulators are shut off
Low
Low
NO
Raise VIN or
remove short
from VCC pin
WDADJ pin shorted to
ground or open circuit
A WDADJ fault only effects the NPOR output. The remainder
of the A4410 operates normally.
Low
High
NO
Remove the short
circuit or connect
the pin
Thermal shutdown
Results in an MPOR, so all regulators are shut off
Low
Low
NO
Let the A4410
cool
FSET/SYNC pin shorted
to ground or open circuit
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24
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
A4410
TIMING DIAGRAMS
(Not to Scale)
13.5 V
VIN
ENB + ENBAT1 + ENBAT2 HIGH
EN
SHUTDOWN SEQUENCE MUST FINISH
BEFORE RESTART IS ACKNOWLEDGED
ENB × ENBAT1 × ENBAT2 LOW
T < ENtd,FILT
ENtd,FILT
VSS1OFFS
SS1
tdLDO,OFF
PWMOFFS
COMP1
fOSC
LX1
tSS1
5.35 V
VVREG,UV,H
tSS1,DLY
VREG
VSS2OFFS
SS2
PWM2OFFS
COMP2
fOSC
LX2
tSS2
tSS2,DLY
V1V25,UV,H
1V25 * 3V3 * V5P * V5
are UV
V1V25,UV,L
1.25 V
V3V3,UV,H
V3V3,UV,L
t > V5td,FILT
t > V5Ptd,FILT
3.3 V
VV5P,UV,H
VV5P,UV,L
3V3 < V3V3,UV,L +
V5P < VV5P,UV,L +
V5 < VV5,UV,L
5V
VV5,UV,H
VV5,UV,L
V5P
POK5V
V5P > VV5P,UV,H*
V5 > VV5,UV,H
V5P < VV5P,UV,L +
V5 < VV5, UV, L
tdFILT
tdFILT
tdNPOR,ON
NPOR
WDSTART
tdNPOR,OFF
3V3 > VV3V3,UV,H*
1V25 > V1V25,UV,H
EN↓ forces NPOR LOW
NPOR↓ forces WDSTART LOW
WDSTART,DLY
Figure 9: Startup and Shutdown by Enable
* is for “and”, + is for “or”
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25
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
A4410
13.5 V
VIN PIN: ~5.6 V @ 25ºC
Decay rate of the VIN pin will depend on
the total capacitance and loads.
VVIN < VIN,STOP
VIN
ENB + ENBAT1 + ENBAT2 HIGH
EN
MPOR
Discharged by RPDSS1
VVSS1 < VVSS1,RST * VVSS2 < VVSS2,RST
VSS1OFFS
SS1
PWMOFFS
COMP1
100% Duty Cycle
fOSC
LX1
fOSC
tSS1
VVREG,UV,H
tSS1,DLY
~5.15 V @ 25ºC
VREG
VVSS2 < VVSS2,RST
Discharged by RPDSS2
VSS2OFFS
SS2
PWM2OFFS
COMP2
fOSC
fOSC
LX2
tSS2
tSS2,DLY
V1V25,UV,H
V1V25,UV,L
1.25 V
V3V3,UV,H
V3V3,UV,L
3.3 V
VV5P,UV,H
VV5P,UV,L
5V
VV5,UV,H
VV5,UV,L
V5P
V5P > VV5P,UV,H*
V5 > VV5,UV,H
POK5V
tdNPOR,ON
NPOR
WDSTART
3V3 > VV3V3,UV,H*
1V25 > V1V25,UV,H
tdFILT
V5P > VV5P,UV,L +
V5 > VV5,UV,L
tdFILT
V5P > VV5P,UV,H*
V5 > VV5,UV,H
tdNPOR,ON
MPOR↑ forces NPOR LOW
NPOR↓ forces WDSTART LOW
tdFILT
3V3 > VV3V3,UV,H*
1V25 > V1V25,UV,H
WDSTART,DLY
WDSTART,DLY
Figure 10: Input Voltage (VIN) Under Voltage for Buck Mode
* is for “and”, + is for “or”
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26
A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
Figure 11: Over Voltage Operation for 1V25 and 3V3
* is for “and”, + is for “or”
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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27
A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
Figure 12: Over Voltage Operation for V5P and V5
* is for “and”, + is for “or”
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115 Northeast Cutoff
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28
A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
Figure 13a: Window Watchdog Timer FAST Clock Detection
Figure 13b: Window Watchdog Timer SLOW Clock Detection
Figure 13c: Watchdog Timer Operation with CLKIN Stuck LOW or HIGH at Startup
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115 Northeast Cutoff
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29
A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
DESIGN AND COMPONENT SELECTION
PWM Switching Frequency (RFSET)
ance and 20% − 30% of inductor saturation.
When the PWM switching frequency is chosen the designer
should be aware of the minimum controllable on time, tON( MIN)
of the A4410. If the system’s required on time is less than the
A4410’s minimum controllable on time then switch node jitter
will occur and the output voltage will have increased ripple or
oscillations.
The inductors should not saturate given the peak operating current according to equations 4a and 4b. In equation 4a VIN,MAX is
the maximum continuous input voltage, such as 16 V, and VF is
the asynchronous diodes forward voltage.
The PWM switching frequency should be calculated using equation 1, where tON(MIN) is the minimum controllable ON time of
the A4410 (195 nsTYP), and VIN,MAX is the maximum required
operational input voltage (not the peak surge voltage).
5.35 V
fOSC <
tON,MIN × VIN,TYP
(1)
If the A4410’s synchronization function is used then the base
oscillator frequency should be chosen such that jitter will not
result at the maximum synchronized switching frequency according to equation 1.
Output Inductors (L1 and L2)
For peak current mode control it is well known that the system
will become unstable when the duty cycle is above 50% without
adequate Slope Compensation (SE). However, the slope compensation in the A4410 is a fixed value based on the oscillator frequency (fOSC). Therefore, it is important to calculate an inductor
value so the falling slope of the inductor current (SF) will work
well with the A4410’s slope compensation.
Equations 2 and 3 can be used to calculate a range of values for
the output inductor for the buck-boost and synchronous buck
regulators. In equation 2a and 3a, slope compensation is a function of the switching frequency (fOSC) according to equations 2b
and 3b, and VF is the asynchronous diodes forward voltage.
SE is in A/µs, fOSC is in kHz, and L will be in µH
5.35 V + VF
2 × (5.35 V + VF )
≤ L1 ≤
SE1
SE1
SE1 = 0.0007 × fOSC + 0.0425
1.25 V
1.25 V
≤ L2 ≤
SE2
2 × SE2
SE2 = 0.0003 × fOSC + 0.0175
(2a)
(2b)
(3a)
(3b)
If equations 2a or 3a yield an inductor value that is not a standard
value then the next closest available value should be used. The
final inductor value should allow for 10% − 20% of initial toler-
IPEAK1 = 4.6 A –
SE1 × (5.35 V + VF )
0.9 × fOSC × (VIN,MAX + VF )
(4a)
SE2 × 1.25 V
0.9 × fOSC × 5.45 V
(4b)
IPEAK2 = 2.4 A –
After an inductor is chosen it should be tested during output short
circuit conditions. The inductor current should be monitored
using a current probe. A good design should be sure the inductor
or the regulator are not damaged when the output is shorted to
ground at maximum input voltage and the highest expected ambient temperature.
Output Capacitors
The output capacitors filter the output voltage to provide an
acceptable level of ripple voltage and they store energy to help
maintain voltage regulation during a load transient. The voltage
rating of the output capacitors must support the output voltage
with sufficient design margin.
The output voltage ripple (ΔVOUT ) is a function of the output
capacitors parameters: CO, ESRCO, ESLCO.
VOUT = IL × ESRCO +
VIN – VOUT
IL
× ESLCO +
LO
8fOSCCOUT
(5)
The type of output capacitors will determine which terms of
equation 8 are dominant. For ceramic output capacitors the
ESRCO and ESLCO are virtually zero so the output voltage ripple
will be dominated by the third term of equation 5.
IL
(6)
VOUT =
8fOSCCOUT
To reduce the voltage ripple of a design using ceramic output
capacitors simply increase the total capacitance, reduce the inductor current ripple (i.e. increase the inductor value), or increase the
switching frequency.
The transient response of the regulator depends on the number
and type of output capacitors. In general, minimizing the ESR of
the output capacitance will result in a better transient response.
The ESR can be minimized by simply adding more capacitors in
parallel or by using higher quality capacitors. At the instant of a
fast load transient (di/dt), the output voltage will change by the
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30
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
A4410
amount
di
ESLCO
VOUT = ILOAD × ESRCO +
dt
(7)
After the load transient occurs, the output voltage will deviate
from its nominal value for a short time. This time will depend
on the system bandwidth, the output inductor value, and output
capacitance. Eventually, the error amplifier will bring the output
voltage back to its nominal value.
The speed at which the error amplifier will bring the output voltage back to its setpoint will depend mainly on the closed-loop
bandwidth of the system. A higher bandwidth usually results in a
shorter time to return to the nominal voltage. However, a higher
bandwidth system may be more difficult to obtain acceptable gain
and phase margins. Selection of the compensation components
(RZ, CZ, CP) are discussed in more detail in the Compensation
Components section of this data sheet.
Ceramic Input Capacitors
The ceramic input capacitor(s) must limit the voltage ripple at the
VIN pin to a relatively low voltage during maximum load. Equation 8 can be used to calculate the minimum input capacitance,
CIN ≥
IOUT,MAX × 0.25
0.90 × fOSC × 50 mV
(8)
Where IOUT,MAX is the maximum current from the pre-regulator,
IOUT,MAX = I3V3 + IV5P + IV5 + 0.3 × I1V25 + 20 mA
(9)
A good design should consider the dc-bias effect on a ceramic
capacitor – as the applied voltage approaches the rated value, the
capacitance value decreases. The X5R and X7R type capacitors
should be the primary choices due to their stability versus both
DC bias and temperature. For all ceramic capacitors, the DC bias
effect is even more pronounced on smaller case sizes so a good
design will use the largest affordable case size (i.e. 1206/16 V or
1210/50 V).
Buck-Boost Asynchronous Diode (D1)
The highest peak current in the asynchronous diode (D1) occurs
when VIN is very low (2.8 V) and both the buck and boost operate at their maximum duty cycles (approximately 84% and 67%,
respectively),
IB/B =
1.88
0.9 × fOSC × L1
(
IPK,B/B = 1.5 × IOUT,MAX + 0.16 ×
(10)
IB/B
2
)
(11)
Where IOUT,MAX is the maximum current from the pre-regulator
defined by equation 9.
The highest average current in the asynchronous diode occurs
when VIN is at its maximum, DBOOST = 0%, and DBUCK = minimum (16% at 2 MHz),
IAVG = IOUT,MAX × (1 – DBUCK,MIN ) = IOUT.MAX × 0.84
(12)
Where IOUT,MAX is calculated using equation 9.
Boost MOSFET (Q1)
The RMS current in the boost MOSFET (Q1) occurs when VIN
is very low (2.8 V) and both the buck and boost operate at their
maximum duty cycles (approximately 84% and 67%, respectively),
IQ1,RMS =
√
[(
0.67 ×
IPK,B/B –
IB/B
2
) + I12 ]
2
B/B
(13)
Where ΔIB/B and IPK,B/B are derived using equations 10 and 11,
respectively.
The boost MOSFET should have a total gate charge of less than
14 nC at a VGS of 5 V. The VDS rating of the boost MOSFET
should be at least 20 V. Several recommendations are shown in
the Functional Block Diagram/Typical Schematic.
Boost Diode (D2)
In buck mode this diode will simply conduct the output current.
However, in buck boost mode the currents in this diode may
increase quite a bit.
(
IPK,B/B = 1.5 × IOUT,MAX + 0.16 ×
IAVG = 0.33 × IPK,B/B – 0.16 ×
IB/B
2
)
IB/B
2
(14)
(15)
Where ΔIB/B is derived using equation 10.
Charge Pump Capacitors
The charge pump requires two capacitors: a 1 µF connected from
pin VCP to VIN and 0.22 µF connected between pins CP1 and
CP2 These capacitors should be a high-quality ceramic capacitor,
such as an X5R or X7R, with a voltage rating of at least 16 V.
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31
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
A4410
Soft Start and Hiccup Mode Timing (CSS1,
CSS2)
capacitor value for CSSn is calculated, the next larger value should
be used.
The soft start times of the buck converters are determined by the
value of the capacitance at the soft start pin, CSSn (n = 1 or 2 for
the pre-regulator or synchronous buck, respectively).
The voltage at the soft start pin will start from 0 V and will be
charged by the soft start current, ISSnSU (n = 1 or 2). However,
PWM switching will not begin instantly because the voltage
at the soft start pin must rise above the soft start offset voltage
(VSSnOFFS). The soft start delay (tSSn,DELAY) can be calculated
using equation 16,
tSSn,DELAY = CSSn ×
( VSSn
ISSn )
OFFS
(16)
SU
If the A4410 is starting into a very heavy load a very fast soft
start time may cause the regulator to exceed the pulse-by-pulse
over current threshold. This occurs because the total of the full
load current, the inductor ripple current, and the additional current required to charge the output capacitors (ICO = CO x VOUT /
tSS) is higher than the pulse-by-pulse current threshold, as shown
in Figure 14.
}
ILIM
ILOAD
Output
Capacitor
Current, ICO
tSS
Figure 14: Output Current (ICO) During Startup
To avoid prematurely triggering hiccup mode the soft start
capacitor, CSSn, should be calculated according to equation 17,
ISSnSU × VOUT × COUT
(17)
CSSn ≥
0.8 V × ICO
Where VOUT is the output voltage, COUT is the output capacitance, ICO is the amount of current allowed to charge the output
capacitance during soft start (recommend 0.1 A < ICO < 0.3 A).
Higher values of ICO result in faster soft start time and lower
values of ICO insure that hiccup mode is not falsely triggered. We
recommend starting the design with an ICO of 0.1 A and increasing it only if the soft start time is too slow. If a non-standard
The output voltage ramp time, tSSn, can be calculated by using
equation 18,
tSSn + VOUT ×
COUT
ICO
(18)
When the A4410 is in hiccup mode, the soft start capacitor sets
the hiccup period. During a startup attempt, the soft start pin
charges the soft start capacitor with ISSnSU and discharges the
same capacitor with ISSnHIC between startup attempts.
Compensation Components (RZ, CZ, CP)
To compensate the system it’s important to understand where the
buck power stage, load resistance, and output capacitance form
their poles and zeros in frequency. Also, its important to understand that the (Type II) compensated error amplifier introduces
a zero and two more poles and where these should be placed to
maximize the system’s stability, provide a high bandwidth, and
optimize the transient response.
First, we will take a look at the power stage of the A4410, the
output capacitors, and the load resistance. This circuitry is commonly referred as the “control to output” transfer function. The
low frequency gain of this section depends on the COMP to SW
current gain (gmPOWER), and the value of the load resistor (RL).
The DC gain (GCO0HZ) of the control-to-output is
GCO0Hz = gmPOWER × RL
(19)
The control to output transfer function has a pole (fP1) formed by
the output capacitance (COUT) and load resistance (RL) at
fP1 =
1
2π × RL × COUT
(20)
The control to output transfer function also has a zero (fZ1)
formed by the output capacitance (COUT) and its associated ESR
fZ1 =
1
2π × ESR × COUT
(21)
For a design with very low-ESR type output capacitors (i.e.
ceramic or OSCON output capacitors), the ESR zero, fZ1, is usually at a very high frequency so it can be ignored. On the other
hand, if the ESR zero falls below or near the 0 dB crossover
frequency of the system (as is the case with electrolytic output
capacitors), then it should be cancelled by the pole formed by the
CP capacitor and the RZ resistor (discussed and identified later as
fP3).
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32
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
A4410
A bode plot of the control-to-output transfer function for the
A4410 application circuit shown on page 2 (VOUT = 5.0 V, IOUT =
2.5 A, RL = 2 Ω) is shown in Figure 15. The pole at fP1 can easily
be seen at 1.9 kHz while the ESR zero, fZ1, occurs at a very high
frequency, 636 kHz (this is typical for a design using ceramic
output capacitors). Note, there is more than 90° of total phase
shift because of the double-pole at half the switching frequency.
60
40
GCO0HZ = 15.1 dB
fP2 =
1
2π × RO × CZ
(23)
The transfer function of the Type-II error amp also has a low
frequency zero (fZ2) dominated by the RZ resistor and the CZ
capacitor.
80
fP1 = 1.9 kHz
20
The transfer function of the Type-II compensated error amp
has a (very) low frequency pole (fP2) dominated by the output
error amplifier’s output impedance RO and the CZ compensation
capacitor,
fZ2 =
0
1
2π × RZ × CZ
(24)
-20
Lastly, the transfer function of the Type-II compensated error
amp has a (very) high frequency pole (fP3) dominated by the RZ
resistor and the CP capacitor
-40
SEL>>
-60
DB (V(VOUT)/V(COMP))
180d
90d
fP3 =
1
2π × RZ × CP
(25)
00d
Double Pole at
212.5 kHz
-90d
-180d
10 Hz
100 Hz
1.0 kHz
10 kHz
100 kHz
1.0 MHz
Figure 15: Control-to-Output Bode Plot
Next, we will take a look at the feedback resistor divider, (RFB1
and RFB2), the error amplifier (gm), and its compensation network RZ/CZ/CP. It greatly simplifies the transfer function derivation if RO >> RZ, and CZ >> CP. In most cases, RO > 2 MΩ, 1
kΩ < RZ < 100 kΩ, 220 pF < CZ < 47 nF, and CP < 50 pF, so the
following equations are very accurate.
The low frequency gain of the control section (GC0Hz) is formed
by the feedback resistor divider and the error amplifier. It can be
calculated using equation 24, where VOUT is the output voltage,
VFB is the reference voltage (0.8 V), gm is the error amplifier
transconductance (750 µA/V), and RO is the error amplifier output impedance (AVOL/gm).
RFB2
× gm × RO
RFB1 + RFB2
VFB
=
× gm × RO
VOUT
VFB
=
× AVOL
VOUT
A bode plot of the error amplifier and its compensation network is shown in Figure 16, fP2, fP3, and fZ2 are indicated on the
magnitude plot. Notice that the zero (fZ2 at 3.8 kHz) has been
placed so that it is just above the pole at fP1 previously shown in
the control-to-output bode plot at 1.9 kHz, Figure 15. Placing fZ2
just above fP1 will result in excellent phase margin, but relatively
slow transient recovery time, as we will see later.
80
60
40
GC0HZ = 49 dB
fZ2 = 3.8 kHz
fP2 = 80 Hz
fP3 ≈ 90 kHz
20
0
-20
-40
SEL>>
-60
DB (V(COMP)/V(VAC))
180d
90d
00d
GC0Hz =
-90d
(22)
-180d
10 Hz
100 Hz
1.0 kHz
10 kHz
100 kHz
1.0 MHz
Figure 16: Type-II Compensated Error Amplifier
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A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
Finally, we take a look at the combined bode plot of both the
control-to-output and the compensated error amp – see the red
curve shown in Figure 17. Careful examination of this plot shows
that the magnitude and phase of the entire system (in red) are
simply the sum of the error amp response (blue) and the control
to output response (green). As shown in Figure 17, the bandwidth
of this system (fc) is 60 kHz, the phase margin is 69 degrees, and
the gain margin is 14 dB.
80
60
40
20
GM = 14 dB
0
fP1 = 60 kHz
-20
-40
SEL>>
-60
DB (V(COMP)/V(VAC))
DB (V(VOUT)/V(COMP))
DB (V(VOUT)/V(VAC))
180d
PM = 69º
90d
00d
-90d
-180d
10 Hz
100 Hz
1.0 kHz
10 kHz
100 kHz
1.0 MHz
Figure 17: Bode Plot of the Complete System
(red curve)
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A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
PCB LAYOUT RECOMMENDATIONS
Figure 18: PCB Layout #1
The input ceramic capacitors (C3, C4, C5, C6, C34) must be located as close as possible to the VIN pins. In general, the smaller capacitors
(0402, 0603) must be placed very close to the VIN pin. The larger capacitors (4.7 F, 50 V, 1210) should be placed within 0.5 inches of the VIN
pin. There must not be any vias between the input capacitors and the VIN pins.
Figure 19: PCB Layout #2
The pre-buck asynchronous diode (D1), input ceramic capacitors (C4, C5, C6), and RC snubber (RN, CN) must be routed on one layer and
“star” grounded at a single location with multiple vias.
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115 Northeast Cutoff
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A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
Figure 20: PCB Layout #3
The pre-buck output inductor (L1) should be located close to the LX1 pins.
The LX1 trace widths (to L1, D1, RN) should be relatively wide and preferably on the same layer as the IC.
Figure 21: PCB Layout #4
The pre-buck regulators output ceramic capacitors (C10 – C14) should be located near the VREG pin.
There must be 1 or 2 smaller ceramic capacitors (C8, C9) as close as possible to the VREG pin.
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A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
Figure 22: PCB Layout #5
The synchronous buck output inductor should be located near the LX2 pins. The trace from the LX2 pins to the output inductor (L2) should
be relatively wide and preferably on the same layer as the IC.
Figure 23: PCB Layout #6
If the synchronous buck is adjustable, the two feedback resistors (R15, R16) must be located near either the
FBADJ or FB1V25 pin. The output capacitors (C16 – C18) should be located near the load.
The output voltage sense trace (to R15) must connect at the load for the best regulation.
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A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
Figure 24: PCB Layout #7
The charge pump capacitors (C1, C2) must be placed as close as possible to VCP and CP1/CP2.
Figure 25: PCB Layout #8
The ceramic capacitors for the LDOs (3V3, V5, V5P, V5CAN, V5SNR, etc) must be placed near their output pins.
The V5P output must have a 1 A/40 V schottky diode (D5) located very close to its pin to limit negative voltages.
Allegro MicroSystems, LLC
115 Northeast Cutoff
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38
A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
Figure 26: PCB Layout #9
Figure 27: PCB Layout #10
The FSET resistor must be placed very close to the FSET/SYNC pin.
Similarly, the VCC bypass capacitor must be placed very close to the
VCC pin.
The COMP network for both buck regulators (CZx, RZx, CPx) must be
located very close to the COMPx pin.
Figure 28: PCB Layout #11
Figure 29: PCB Layout #12
The thermal pad under the A44xx must connect to the ground
plane(s) with multiple vias.
The boost MOSFET (Q1) and the boost diode (D2) must be placed
very close to each other. Q1 should have thermal vias to a polygon
on the bottom layer. Also, there should be “local” bypass capacitors
(C33, C35).
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Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
A4410
PACKAGE OUTLINE DRAWING
For Reference Only – Not for Tooling Use
(Reference JEDEC MO-153 BDT-1)
Dimensions in millimeters
NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
9.70 ±0.10
8º
0º
6.50 ±0.10
38
0.20
0.09
B
3.00 ±0.10 4.40 ±0.10 6.40 BSC
A
0.60 ±0.15
1.00 REF
1 2
Branded Face
C
38X
0.90 ±0.05 1.10 MAX
0.10 C
0.27
0.17
0.25 BSC
SEATING PLANE
GAUGE PLANE
SEATING
PLANE
0.15
0.00
0.50 BSC
0.50
0.30
38
1.70
3.00
A
Terminal #1 mark area
6.5
B
Exposed thermal pad (bottom surface)
PCB Layout Reference View
C
Reference land pattern layout (reference IPC7351 SOP50P640X120-39M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
1 2
C
6.00
Figure 30: Package LV, 38-Pin eTSSOP
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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A4410
Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
Revision History
Revision
Revision Date
–
April 3, 2015
Description of Revision
Initial Release
Copyright ©2015, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
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41
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