MICROCHIP PIC18F46J11

PIC18F46J11 Family
Data Sheet
28/44-Pin, Low-Power,
High-Performance Microcontrollers
with nanoWatt XLP Technology
© 2009 Microchip Technology Inc.
DS39932C
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39932C-page 2
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
28/44-Pin, Low-Power, High-Performance Microcontrollers
Power Management Features with
nanoWatt XLP™ for Extreme Low Power:
Peripheral Highlights (Continued):
• 5.5V Tolerant Inputs (digital only pins)
• Low-Power, High-Speed CMOS Flash Technology
• C Compiler Optimized Architecture for Re-Entrant
Code
• Priority Levels for Interrupts
• Self-Programmable under Software Control
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• Single-Supply In-Circuit Serial Programming™
(ICSP™) via Two Pins
• In-Circuit Debug (ICD) with Three Breakpoints via
Two Pins
• Operating Voltage Range of 2.0V to 3.6V
• On-Chip 2.5V Regulator
• Flash Program Memory of 10,000 Erase/Write
Cycles Minimum and 20-Year Data Retention
• Four Programmable External Interrupts
• Four Input Change Interrupts
• Two Enhanced Capture/Compare/PWM (ECCP)
modules:
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-shutdown and auto-restart
- Pulse steering control
• Two Master Synchronous Serial Port (MSSP)
modules featuring:
- 3-wire SPI (all 4 modes)
- 1024-byte SPI Direct Memory Access (DMA)
channel
- I2C™ Master and Slave modes
• 8-Bit Parallel Master Port/Enhanced Parallel
Slave Port
• Two-Rail – Rail Analog Comparators with Input
Multiplexing
• 10-Bit, up to 13-Channel Analog-to-Digital (A/D)
Converter module:
- Auto-acquisition capability
- Conversion available during Sleep
- Self-Calibration
• High/Low-Voltage Detect module
• Charge Time Measurement Unit (CTMU):
- Supports capacitive touch sensing for touch
screens and capacitive switches
- Provides a Precise Resolution Time
Measurement for Both Flow Measurement
and Simple Temperature Sensing
• Two Enhanced USART modules:
- Supports RS-485, RS-232 and LIN/J2602
- Auto-wake-up on Start bit
• Auto-Baud Detect
Peripheral Highlights:
Flexible Oscillator Structure:
• Peripheral Pin Select:
- Allows independent I/O mapping of many
peripherals
- Continuous hardware integrity checking and
safety interlocks prevent unintentional
configuration changes
• Hardware Real-Time Clock and Calendar (RTCC):
- Provides clock, calendar and alarm functions
• High-Current Sink/Source 25 mA/25 mA
(PORTB and PORTC)
• 1% Accurate High-Precision Internal Oscillator
• Two External Clock modes, up to 48 MHz (12 MIPS)
• Internal 31 kHz Oscillator, Internal Oscillators
Tunable at 31 kHz and 8 MHz or 48 MHz with PLL
• Secondary Oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if any clock stops
• Two-Speed Oscillator Start-up
• Programmable Reference Clock Output Generator
• Deep Sleep mode: CPU off, Peripherals off,
Currents Down to 13 nA and 850 nA with RTCC
- Able to wake-up on external triggers,
programmable WDT or RTCC alarm
- Ultra Low-Power Wake-up (ULPWU)
• Sleep mode: CPU off, Peripherals off, SRAM on,
Fast Wake-up, Currents Down to 105 nA Typical
• Idle: CPU off, Peripherals on, Currents Down to
2.3 μA Typical
• Run: CPU on, Peripherals on, Currents Down to
6.2 μA Typical
• Timer1 Oscillator/w RTCC: 1 μA, 32 kHz Typical
• Watchdog Timer: 2.2 μA, 2V Typical
Special Microcontroller Features:
© 2009 Microchip Technology Inc.
DS39932C-page 3
PIC18F/LF(1)
Device
Pins
Program
Memory (bytes)
SRAM (bytes)
Remappable
Pins
Timers
8/16-Bit
ECCP/(PWM)
EUSART
SPI w/DMA
I2C™
10-Bit A/D (ch)
Comparators
Deep Sleep
PMP/PSP
CTMU
RTCC
PIC18F46J11 FAMILY
PIC18F24J11
28
16K
3776
16
2/3
2
2
2
Y
Y
10
2
Y
N
Y
Y
PIC18F25J11
28
32K
3776
16
2/3
2
2
2
Y
Y
10
2
Y
N
Y
Y
PIC18F26J11
28
64K
3776
16
2/3
2
2
2
Y
Y
10
2
Y
N
Y
Y
PIC18F44J11
44
16K
3776
22
2/3
2
2
2
Y
Y
13
2
Y
Y
Y
Y
PIC18F45J11
44
32K
3776
22
2/3
2
2
2
Y
Y
13
2
Y
Y
Y
Y
PIC18F46J11
44
64K
3776
22
2/3
2
2
2
Y
Y
13
2
Y
Y
Y
Y
PIC18LF24J11
28
16K
3776
16
2/3
2
2
2
Y
Y
10
2
N
N
Y
Y
PIC18LF25J11
28
32K
3776
16
2/3
2
2
2
Y
Y
10
2
N
N
Y
Y
PIC18LF26J11
28
64K
3776
16
2/3
2
2
2
Y
Y
10
2
N
N
Y
Y
PIC18LF44J11
44
16K
3776
22
2/3
2
2
2
Y
Y
13
2
N
Y
Y
Y
PIC18LF45J11
44
32K
3776
22
2/3
2
2
2
Y
Y
13
2
N
Y
Y
Y
PIC18LF46J11
44
64K
3776
22
2/3
2
2
2
Y
Y
13
2
N
Y
Y
Y
Note 1:
MSSP
See Section 1.3 “Details on Individual Family Devices”, Section 3.6 “Deep Sleep Mode” and Section 25.3
“On-Chip Voltage Regulator” for details describing the functional differences between PIC18F and PIC18LF
variants in this device family.
DS39932C-page 4
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
Pin Diagrams
28-Pin SPDIP/SOIC/SSOP(1)
PIC18F2XJ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RA1/AN1/C2INA/RP0
RA0/AN0/C1INA/ULPWU/RP1
MCLR
RB7/KBI3/PGD/RP10
RB6/KBI2/PGC/RP9
RB5/KBI1/RP8
RB4/KBI0/RP7
MCLR
RA0/AN0/C1INA/ULPWU/RP0
RA1/AN1/C2INA/RP1
RA2/AN2/VREF-/CVREF/C2INB
RA3/AN3/VREF+/C1INB
VDDCORE/VCAP(2)
RA5/AN4/SS1/HLVDIN/RP2
VSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI/RP11
RC1/T1OSI/RP12
RC2/AN11/CTPLS/RP13
RC3/SCK1/SCL1/RP14
= Pins are up to 5V tolerant
28-Pin QFN(1,3)
RB7/KBI3/PGD/RP10
RB6/KBI2/PGC/RP9
RB5/KBI1/RP8
RB4/KBI0/RP7
RB3/AN9/CTEDG2/RP6
RB2/AN8/CTEDG1/REFO/RP5
RB1/AN10/RTCC/RP4
RB0/AN12/INT0/RP3
VDD
VSS
RC7/RX1/DT1/RP18
RC6/TX1/CK1/RP17
RC5/SDO1/RP16
RC4/SDI1/SDA1/RP15
= Pins are up to 5V tolerant
28 27 26 25 24 23 22
1
2
3
4
5
6
7
PIC18F2XJ11
8 9 1011 12 13 14
21
20
19
18
17
16
15
RB3/AN9/CTEDG2/RP6
RB2/AN8/CTEDG1/REFO/RP5
RB1/AN10/RTCC/RP4
RB0/AN12/INT0/RP3
VDD
VSS
RC7/RX1/DT1/RP18
RC0/T1OSO/T1CKI/RP11
RC1/T1OSI/RP12
RC2/AN11/CTPLS/RP13
RC3\SCK1\SCL1\RP14
RC4/SDA1RP15
RC5/SDO1/RP16
RC6/TX1/CK1/RP17
RA2/AN2/VREF-/CVREF/C2INB
RA3/AN3/VREF+/C1INB
VDDCORE/VCAP(2)
RA5/AN4/SS1/HLVDIN/RP2
VSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
Legend: RPn represents remappable pins.
Note 1: Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be
dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table 9-13 and
Table 9-14, respectively. For details on configuring the PPS module, see Section 9.7 “Peripheral Pin
Select (PPS)”.
2: See Section 25.3 “On-Chip Voltage Regulator” for details on how to connect the VDDCORE/VCAP pin.
3: For the QFN package, it is recommended that the bottom pad be connected to VSS.
© 2009 Microchip Technology Inc.
DS39932C-page 5
PIC18F46J11 FAMILY
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
44
43
42
41
40
39
38
37
36
35
34
RC6/PMA5/TX1/CK1/RP17
RC5/SDO1/RP16
RC4/SDI1/SDA1\RP15
RD3/PMD3/RP20
RD2/PMD2/RP19
RD1/PMD1/SDA2
RD0/PMD0/SCL2
RC3\SCK1/SCL1/RP14
RC2/AN11/CTPLS/RP13
RC1/T1OSI/RP12
RC0/T1OSO/T1CKI/RP11
44-Pin QFN(1,3)
PIC18F4XJ11
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
AVSS
VDD
AVDD
RE2/AN7/PMCS
RE1/AN6/PMWR
RE0/AN5/PMRD
RA5/AN4/SS1/HLVDIN/RP2
VDDCORE/VCAP(2)
RB3/AN9/CTEDG2/PMA2/RP6
NC
RB4/PMA1/KBI0/RP7
RB5/PMA0/KBI1/RP8
RB6/KBI2/PGC/RP9
RB7/KBI3/PGD/RP10
MCLR
RA0/AN0/C1INA/ULPWU/PMA6/RP0
RA1/AN1/C2INA/PMA7/RP1
RA2/AN2/VREF-/CVREF-/C2INB
RA3/AN3/VREF+/C1INB
RC7/PMA4/RX1/DT1/RP18
RD4/PMD4/RP21
RD5/PMD5/RP22
RD6/PMD6/RP23
RD7/PMD7/RP24
VSS
AVDD
VDD
RB0/AN12/INT0/RP3
RB1/AN10/PMBE/RTCC/RP4
RB2/AN8/CTEDG1/PMA3/REFO/RP5
Legend: RPn represents remappable pins.
Note 1: Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be
dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table 9-13 and
Table 9-14, respectively. For details on configuring the PPS module, see Section 9.7 “Peripheral Pin
Select (PPS)”.
2: See Section 25.3 “On-Chip Voltage Regulator” for details on how to connect the VDDCORE/VCAP pin.
3: For the QFN package, it is recommended that the bottom pad be connected to VSS.
DS39932C-page 6
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
RC6/PMA5/TX1/CK1/RP17
RC5/SDO1/RP16
RC4/SDI1/SDA1/RP15
RD3/PMD3/RP20
RD2/PMD2/RP19
RD1/PMD1/SDA2
RD0/PMD0/SCL2
RC3/SCK1/SCL1/RP14
RC2/AN11/CTPLS/RP13
RC1/T1OSI/RP12
NC
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
44
43
42
41
40
39
38
37
36
35
34
44-Pin TQFP(1)
PIC18F4XJ11
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
NC
RC0/T1OSO/T1CKI/RP11
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
VDD
RE2/AN7/PMCS
RE1/AN6/PMWR
RE0/AN5/PMRD
RA5/AN4/SS1/HLVDIN/RP2
VDDCORE/VCAP(2)
NC
NC
RB4/PMA1/KBI0/RP7
RB5/PMA0/KBI1/RP8
RB6/KBI2/PGC/RP9
RB7/KBI3/PGD/RP10
MCLR
RA0/AN0/C1INA/ULPWU/PMA6/RP0
RA1/AN1/C2INA/PMA7/RP1
RA2/AN2/VREF-/CVREF-/C2INB
RA3/AN3/VREF+/C1INB
RC7/PMA4/RX1/DT1/RP18
RD4/PMD4/RP21
RD5/PMD5/RP22
RD6/PMD6/RP23
RD7/PMD7/RP24
VSS
VDD
RB0/AN12/INT0/RP3
RB1/AN10/PMBE/RTCC/RP4
RB2/AN8/CTEDG1/PMA3/REFO/RP5
RB3/AN9/CTEDG2/PMA2/RP6
Legend: RPn represents remappable pins.
Note 1: Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be
dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table 9-13 and
Table 9-14, respectively. For details on configuring the PPS module, see Section 9.7 “Peripheral Pin
Select (PPS)”.
2: See Section 25.3 “On-Chip Voltage Regulator” for details on how to connect the VDDCORE/VCAP pin.
© 2009 Microchip Technology Inc.
DS39932C-page 7
PIC18F46J11 FAMILY
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 Oscillator Configurations ............................................................................................................................................................ 31
3.0 Low-Power Modes...................................................................................................................................................................... 41
4.0 Reset .......................................................................................................................................................................................... 57
5.0 Memory Organization ................................................................................................................................................................. 71
6.0 Flash Program Memory .............................................................................................................................................................. 97
7.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 107
8.0 Interrupts .................................................................................................................................................................................. 109
9.0 I/O Ports ................................................................................................................................................................................... 125
10.0 Parallel Master Port (PMP)....................................................................................................................................................... 165
11.0 Timer0 Module ......................................................................................................................................................................... 191
12.0 Timer1 Module ......................................................................................................................................................................... 195
13.0 Timer2 Module ......................................................................................................................................................................... 207
14.0 Timer3 Module ......................................................................................................................................................................... 209
15.0 Timer4 Module ......................................................................................................................................................................... 219
16.0 Real-Time Clock and Calendar (RTCC) ................................................................................................................................... 221
17.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 241
18.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 265
19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 321
20.0 10-bit Analog-to-Digital Converter (A/D) Module ...................................................................................................................... 345
21.0 Comparator Module.................................................................................................................................................................. 355
22.0 Comparator Voltage Reference Module ................................................................................................................................... 363
23.0 High/Low Voltage Detect (HLVD) ............................................................................................................................................. 367
24.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 373
25.0 Special Features of the CPU .................................................................................................................................................... 389
26.0 Instruction Set Summary .......................................................................................................................................................... 407
27.0 Development Support............................................................................................................................................................... 457
28.0 Electrical Characteristics .......................................................................................................................................................... 461
29.0 Packaging Information.............................................................................................................................................................. 499
Appendix A: Revision History............................................................................................................................................................. 511
Appendix B: Device Differences......................................................................................................................................................... 511
The Microchip Web Site ..................................................................................................................................................................... 525
Customer Change Notification Service .............................................................................................................................................. 525
Customer Support .............................................................................................................................................................................. 525
Reader Response .............................................................................................................................................................................. 526
Product Identification System............................................................................................................................................................. 527
DS39932C-page 8
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TO OUR VALUED CUSTOMERS
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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© 2009 Microchip Technology Inc.
DS39932C-page 9
PIC18F46J11 FAMILY
NOTES:
DS39932C-page 10
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC18F24J11
• PIC18LF24J11
• PIC18F25J11
• PIC18LF25J11
• PIC18F26J11
• PIC18LF26J11
• PIC18F44J11
• PIC18LF44J11
• PIC18F45J11
• PIC18LF45J11
• PIC18F46J11
• PIC18LF46J11
1.1
1.1.1
Core Features
nanoWatt TECHNOLOGY
All of the devices in the PIC18F46J11 family incorporate
a range of features that can significantly reduce power
consumption during operation. Key features are:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal RC
oscillator, power consumption during code
execution can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operational requirements.
• On-the-Fly Mode Switching: The
power-managed modes are invoked by user code
during operation, allowing the users to incorporate
power-saving ideas into their application’s
software design.
1.1.2
OSCILLATOR OPTIONS AND
FEATURES
All of the devices in the PIC18F46J11 family offer five
different oscillator options, allowing users a range of
choices in developing application hardware. These
include:
• Two Crystal modes using crystals or ceramic
resonators.
• Two External Clock modes offering the option of a
divide-by-4 clock output.
• An internal oscillator block, which provides an
8 MHz clock and an INTRC source (approximately 31 kHz, stable over temperature and VDD),
as well as a range of six user-selectable clock
frequencies, between 125 kHz to 4 MHz, for a
total of eight clock frequencies. This option frees
an oscillator pin for use as an additional general
purpose I/O.
• A Phase Lock Loop (PLL) frequency multiplier,
available to the high-speed crystal, and external
and internal oscillators, providing a clock speed
up to 48 MHz.
The internal oscillator block provides a stable reference
source that gives the PIC18F46J11 family additional
features for robust operation:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset (POR), or wake-up from
Sleep mode, until the primary clock source is
available.
1.1.3
EXPANDED MEMORY
The PIC18F46J11 family provides ample room for
application code, from 16 Kbytes to 64 Kbytes of code
space. The Flash cells for program memory are rated
to last in excess of 10000 erase/write cycles. Data
retention without refresh is conservatively estimated to
be greater than 20 years.
The Flash program memory is readable and writable
during normal operation. The PIC18F46J11 family also
provides plenty of room for dynamic application data
with up to 3.8 Kbytes of data RAM.
© 2009 Microchip Technology Inc.
DS39932C-page 11
PIC18F46J11 FAMILY
1.1.4
EXTENDED INSTRUCTION SET
The PIC18F46J11 family implements the optional
extension to the PIC18 instruction set, adding eight
new instructions and an Indexed Addressing mode.
Enabled as a device configuration option, the extension
has been specifically designed to optimize re-entrant
application code originally developed in high-level
languages, such as C.
1.1.5
EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device.
The PIC18F46J11 family is also pin compatible with
other PIC18 families, such as the PIC18F4620,
PIC18F4520 and PIC18F45J10. This allows a new
dimension to the evolution of applications, allowing
developers to select different price points within
Microchip’s PIC18 portfolio, while maintaining the
same feature set.
1.2
Other Special Features
• Communications: The PIC18F46J11 family
incorporates a range of serial and parallel
communication peripherals. This device also
includes two independent Enhanced USARTs and
two Master Synchronous Serial Port (MSSP)
modules, capable of both Serial Peripheral Interface (SPI) and I2C™ (Master and Slave) modes of
operation. The device also has a parallel port and
can be configured to serve as either a Parallel
Master Port (PMP) or as a Parallel Slave Port
(PSP).
• ECCP Modules: All devices in the family
incorporate three Enhanced
Capture/Compare/PWM (ECCP) modules to
maximize flexibility in control applications. Up to
four different time bases may be used to perform
several different operations at once. Each of the
ECCPs offers up to four PWM outputs, allowing for
a total of eight PWMs. The ECCPs also offer many
beneficial features, including polarity selection, programmable dead time, auto-shutdown and restart
and Half-Bridge and Full-Bridge Output modes.
DS39932C-page 12
• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period, and
thus, reducing code overhead.
• Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit prescaler,
allowing an extended time-out range that is stable
across operating voltage and temperature. See
Section 28.0 “Electrical Characteristics” for
time-out periods.
1.3
Details on Individual Family
Devices
Devices in the PIC18F46J11 family are available in
28-pin and 44-pin packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.
The devices are differentiated from each other in two
ways:
• Flash program memory (three sizes: 16 Kbytes
for the PIC18FX4J11, 32 Kbytes for PIC18FX5J11
devices and 64 Kbytes for PIC18FX6J11)
• I/O ports (three bidirectional ports on 28-pin
devices, five bidirectional ports on 44-pin devices)
All other features for devices in this family are identical.
These are summarized in Table 1-1 and Table 1-2.
The pinouts for the PIC18F2XJ11 devices are listed in
Table 1-3 and the pinouts for the PIC18F4XJ11 devices
are listed in Table 1-4.
The PIC18F46J11 family of devices provides an
on-chip voltage regulator to supply the correct voltage
levels to the core. Parts designated with an “F” part
number (such as PIC18F46J11) have the voltage
regulator enabled.
These parts can run from 2.15V-3.6V on VDD, but should
have the VDDCORE pin connected to VSS through a
low-ESR capacitor. Parts designated with an “LF” part
number (such as PIC18LF46J11) do not enable the voltage regulator. For “LF” parts, an external supply of
2.0V-2.7V has to be supplied to the VDDCORE pin with
2.0V-3.6V supplied to VDD (VDDCORE should never
exceed VDD).
For more details about the internal voltage regulator,
see Section 25.3 “On-Chip Voltage Regulator”.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 1-1:
DEVICE FEATURES FOR THE PIC18F2XJ11 (28-PIN DEVICES)
Features
PIC18F24J11
PIC18F25J11
PIC18F26J11
DC – 48 MHz
DC – 48 MHz
DC – 48 MHz
16K
32K
64K
Program Memory (Instructions)
8,192
16,384
32,768
Data Memory (Bytes)
3.8K
3.8K
3.8K
Operating Frequency
Program Memory (Bytes)
Interrupt Sources
30
I/O Ports
Ports A, B, C
Timers
5
Enhanced Capture/Compare/PWM Modules
2
Serial Communications
MSSP (2), Enhanced USART (2)
Parallel Communications (PMP/PSP)
No
10-Bit Analog-to-Digital Module
Resets (and Delays)
Instruction Set
75 Instructions, 83 with Extended Instruction Set Enabled
Packages
TABLE 1-2:
10 Input Channels
POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
28-Pin QFN, SOIC, SSOP and SPDIP (300 mil)
DEVICE FEATURES FOR THE PIC18F4XJ11 (44-PIN DEVICES)
Features
Operating Frequency
Program Memory (Bytes)
PIC18F44J11
PIC18F45J11
PIC18F46J11
DC – 48 MHz
DC – 48 MHz
DC – 48 MHz
16K
32K
64K
Program Memory (Instructions)
8,192
16,384
32,768
Data Memory (Bytes)
3.8K
3.8K
3.8K
Interrupt Sources
I/O Ports
Timers
Enhanced Capture/Compare/PWM Modules
Serial Communications
Parallel Communications (PMP/PSP)
10-Bit Analog-to-Digital Module
Resets (and Delays)
Instruction Set
Packages
© 2009 Microchip Technology Inc.
30
Ports A, B, C, D, E
5
2
MSSP (2), Enhanced USART (2)
Yes
13 Input Channels
POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
75 Instructions, 83 with Extended Instruction Set Enabled
44-Pin QFN and TQFP
DS39932C-page 13
PIC18F46J11 FAMILY
FIGURE 1-1:
PIC18F2XJ11 (28-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
20
Address Latch
PCU PCH PCL
Program Counter
12
Data Address<12>
31-Level Stack
4
BSR
Address Latch
STKPTR
Program Memory
(16 Kbytes-64 Kbytes)
12
PORTC
RC0:RC7(1)
inc/dec
logic
Table Latch
Address
Decode
ROM Latch
Instruction Bus <16>
PORTB
RB0:RB7(1)
4
Access
Bank
12
FSR0
FSR1
FSR2
Data Latch
8
RA0:RA7(1)
Data Memory
(3.8 Kbytes)
PCLATU PCLATH
21
PORTA
Data Latch
8
8
inc/dec logic
IR
Instruction
Decode and
Control
Timing
Generation
OSC2/CLKO
OSC1/CLKI
PRODH PRODL
3
Power-up
Timer
8 MHz
INTOSC
8
State Machine
Control Signals
8
CTMU
Note 1:
2:
ECCP1
ADC
10-Bit
8
ALU<8>
8
Brown-out
Reset(2)
VDDCORE/VCAP
LVD
8
8
Watchdog
Timer
Voltage
Regulator
RTCC
W
8
Power-on
Reset
Precision
Band Gap
Reference
8
BITOP
Oscillator
Start-up Timer
INTRC
Oscillator
8 x 8 Multiply
VDD, VSS
Timer0
ECCP2
MCLR
Timer1
EUSART1
Timer2
Timer3
EUSART2
Timer4
MSSP1
Comparators
MSSP2
See Table 1-3 for I/O port pin descriptions.
BOR functionality is provided when the on-chip voltage regulator is enabled.
DS39932C-page 14
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
FIGURE 1-2:
PIC18F4XJ11 (44-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
inc/dec logic
21
31-Level Stack
Address Latch
System Bus Interface
Address Latch
PCU PCH PCL
Program Counter
PORTB
RB0:RB7(1)
12
Data Address<12>
4
4
12
BSR
STKPTR
Program Memory
(16 Kbytes-64 Kbytes)
RA0:RA7(1)
Data Memory
(3.8 Kbytes)
PCLATU PCLATH
20
PORTA
Data Latch
8
8
FSR0
FSR1
FSR2
Data Latch
PORTC
Access
Bank
RC0:RC7(1)
12
inc/dec
logic
8
Table Latch
PORTD
RD0:RD7(1)
Address
Decode
ROM Latch
Instruction Bus <16>
PORTE
IR
RE0:RE2(1)
AD<15:0>, A<19:16>
(Multiplexed with PORTD
and PORTE)
8
Timing
Generation
OSC2/CLKO
OSC1/CLKI
PRODH PRODL
Instruction
Decode and
Control
State Machine
Control Signals
3
8
W
BITOP
8
Power-up
Timer
8 MHz
INTOSC
8 x 8 Multiply
8
Oscillator
Start-up Timer
INTRC
Oscillator
Precision
Band Gap
Reference
8
Watchdog
Timer
Brown-out
Reset(2)
Voltage
Regulator
VDDCORE/VCAP
PMP
LVD
CTMU
Note 1:
2:
ADC
10-Bit
ECCP1
8
ALU<8>
Power-on
Reset
RTCC
8
8
VDD, VSS
Timer0
MCLR
Timer1
ECCP2
Timer2
EUSART1
Timer3
Timer4
EUSART2
Comparators
MSSP1
MSSP2
See Table 1-4 for I/O port pin descriptions.
BOR functionality is provided when the on-chip voltage regulator is enabled.
© 2009 Microchip Technology Inc.
DS39932C-page 15
PIC18F46J11 FAMILY
TABLE 1-3:
PIC18F2XJ11 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
28-SPDIP/
SSOP/
28-QFN
SOIC
MCLR
1
26
OSC1/CLKI/RA7
OSC1
9
6
Pin Buffer
Type Type
I
ST
I
ST
I
CMOS
I/O
TTL
O
—
CLKO
O
—
RA6(1)
I/O
TTL
CLKI
RA7(1)
OSC2/CLKO/RA6
OSC2
10
7
Description
Master Clear (Reset) input. This pin is an
active-low Reset to the device.
Oscillator crystal input or external clock source
input. ST buffer when configured in RC mode;
CMOS otherwise. Main oscillator input
connection.
External clock source input; always associated
with pin function OSC1 (see related OSC1/CLKI
pins).
Digital I/O.
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
Main oscillator feedback output connection.
In RC mode, OSC2 pin outputs CLKO, which
has 1/4 the frequency of OSC1 and denotes
the instruction cycle rate.
Digital I/O.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
DIG = Digital output
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
DS39932C-page 16
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 1-3:
PIC18F2XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
28-SPDIP/
SSOP/
28-QFN
SOIC
Pin Buffer
Type Type
Description
PORTA is a bidirectional I/O port.
RA0/AN0/C1INA/ULPWU/RP0
RA0
AN0
C1INA
ULPWU
RP0
2
RA1/AN1/C2INA/RP1
RA1
AN1
C2INA
RP1
3
RA2/AN2/VREF-/CVREF/C2INB
RA2
AN2
VREFCVREF
C2INB
4
RA3/AN3/VREF+/C1INB
RA3
AN3
VREF+
C1INB
5
RA5/AN4/SS1/HLVDIN/
RP2
RA5
AN4
SS1
HLVDIN
RP2
7
RA6(1)
RA7(1)
27
I/O
I
I
I
I/O
DIG
Analog
Analog
Analog
DIG
Digital I/O.
Analog input 0.
Comparator 1 input A.
Ultra low-power wake-up input.
Remappable peripheral pin 0.
I
O
I
I/O
DIG
Analog
Analog
DIG
Digital I/O.
Analog input 1.
Comparator 2 input A.
Remappable peripheral pin 1.
I/O
I
O
I
I
DIG
Analog
Analog
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Comparator reference voltage output.
Comparator 2 input B.
I/O
I
I
I
DIG
Analog
Analog
Analog
Digital I/O
Analog input 3
A/D reference voltage (high) input
Comparator 1 input B
I/O
I
I
I
I/O
DIG
Analog
TTL
Analog
DIG
Digital I/O.
Analog input 4.
SPI slave select input.
High/low-voltage detect input.
Remappable peripheral pin 2.
28
1
2
4
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
DIG = Digital output
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
© 2009 Microchip Technology Inc.
DS39932C-page 17
PIC18F46J11 FAMILY
TABLE 1-3:
PIC18F2XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
28-SPDIP/
SSOP/
28-QFN
SOIC
Pin Buffer
Type Type
Description
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-ups
on all inputs.
RB0/AN12/INT0/RP3
RB0
AN12
INT0
RP3
21
RB1/AN10/RTCC/RP4
RB1
AN10
RTCC
RP4
22
RB2/AN8/CTEDG1/
REFO/RP5
RB2
AN8
CTEDG1
REFO
RP5
23
RB3/AN9/CTEDG2/RP6
RB3
AN9
CTEDG2
RP6
24
RB4/KBI0/RP7
RB4
KBI0
RP7
25
RB5/KBI1/RP8
RB5
KBI1
RP8
26
18
I/O
I
I
I/O
DIG
Analog
ST
DIG
Digital I/O.
Analog input 12.
External interrupt 0.
Remappable peripheral pin 3.
I/O
I
O
I/O
DIG
Analog
DIG
DIG
Digital I/O.
Analog input 10.
Asynchronous serial transmit data output.
Remappable peripheral pin 4.
I/O
I
I
O
I/O
DIG
Analog
ST
DIG
DIG
Digital I/O.
Analog input 8.
CTMU edge 1 input.
Reference output clock.
Remappable peripheral pin 5.
I/O
I
I/O
I
DIG
Analog
ST
DIG
Digital I/O.
Analog input 9.
CTMU edge 2 input.
Remappable peripheral pin 6.
I/O
I
I/O
DIG
TTL
DIG
Digital I/O.
Interrupt-on-change pin.
Remappable peripheral pin 7.
I/O
I/O
I/O
DIG
DIG
DIG
Digital I/O.
Parallel Master Port address.
Remappable peripheral pin 8.
19
20
21
22
23
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
DIG = Digital output
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
DS39932C-page 18
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 1-3:
PIC18F2XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
28-SPDIP/
SSOP/
28-QFN
SOIC
Pin Buffer
Type Type
Description
PORTB (continued)
RB6/KBI2/PGC/RP9
RB6
KBI2
PGC
RP9
27
RB7/KBI3/PGD/RP10
RB7
KBI3
PGD
28
RP10
24
I/O
I
I
I/O
DIG
TTL
ST
DIG
Digital I/O.
Interrupt-on-change pin.
ICSP™ clock input.
Remappable peripheral pin 9.
I/O
I
I/O
DIG
TTL
ST
I/O
DIG
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming
data pin.
Remappable peripheral pin 10.
25
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
DIG = Digital output
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
© 2009 Microchip Technology Inc.
DS39932C-page 19
PIC18F46J11 FAMILY
TABLE 1-3:
PIC18F2XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
28-SPDIP/
SSOP/
28-QFN
SOIC
Pin Buffer
Type Type
Description
PORTC is a bidirectional I/O port
RC0/T1OSO/T1CKI/RP11
RC0
T1OSO
T1CKI
RP11
11
RC1/T1OSI/RP12
RC1
T1OSI
RP12
12
RC2/AN11/CTPLS/RP13
RC2
AN11
CTPLS
RP13
13
RC3/SCK1/SCL1/RP14
RC3
SCK1
14
8
I/O
O
I
I/O
ST
Analog
ST
DIG
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
Remappable peripheral pin 11.
I/O
I
I/O
ST
Analog
DIG
Digital I/O.
Timer1 oscillator input.
Remappable peripheral pin 12.
I/O
I
O
I/O
ST
Analog
DIG
DIG
Digital I/O.
Analog input 11.
CTMU pulse generator output.
Remappable peripheral pin 13.
I/O
I/O
ST
DIG
SCL1
I/O
I2C
RP14
I/O
DIG
Digital I/O.
Synchronous serial clock input/output for
SPI mode.
Synchronous serial clock input/output for
I2C™ mode.
Remappable peripheral pin 14.
I/O
I
I/O
I/O
ST
ST
I2C
DIG
Digital I/O.
SPI data input.
I2C data I/O.
Remappable peripheral pin 15.
I/O
O
I/O
ST
DIG
DIG
Digital I/O.
SPI data output.
Remappable peripheral pin 16.
I/O
O
I/O
ST
DIG
ST
I/O
DIG
Digital I/O.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related
RX1/DT1).
Remappable peripheral pin 17.
I/O
I
I/O
I/O
ST
ST
ST
DIG
Digital I/O.
Asynchronous serial receive data input.
Synchronous serial data output/input.
Remappable peripheral pin 18.
RC4/SDI1/SDA1/RP15
RC4
SDI1
SDA1
RP15
15
RC5/SDO1/RP16
RC5
SDO1
RP16
16
RC6/TX1/CK1/RP17
RC6
TX1
CK1
17
9
10
11
12
13
14
RP17
RC7/RX1/DT1/RP18
RC7
RX1
DT1
RP18
18
15
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
DIG = Digital output
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
DS39932C-page 20
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 1-3:
PIC18F2XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
28-SPDIP/
SSOP/
28-QFN
SOIC
Pin Buffer
Type Type
VSS1
8
5
P
—
VSS2
19
16
—
—
VDD
20
17
P
—
VDDCORE/VCAP
6
3
VDDCORE
P
—
VCAP
P
—
Description
Ground reference for logic and I/O pins.
Positive supply for peripheral digital logic and I/O
pins.
Core logic power or external filter capacitor
connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator
enabled).
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
DIG = Digital output
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
© 2009 Microchip Technology Inc.
DS39932C-page 21
PIC18F46J11 FAMILY
TABLE 1-4:
PIC18F4XJ11 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
Pin Buffer
4444- Type Type
QFN TQFP
MCLR
18
18
I
ST
OSC1/CLKI/RA7
OSC1
32
30
I
ST
I
CMOS
I/O
TTL
O
—
CLKO
O
—
RA6(1)
I/O
TTL
CLKI
RA7(1)
OSC2/CLKO/RA6
OSC2
33
31
Description
Master Clear (Reset) input; this is an active-low
Reset to the device.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source
input. ST buffer when configured in RC mode;
otherwise CMOS. Main oscillator input
connection.
External clock source input; always associated
with pin function OSC1 (see related OSC1/CLKI
pins).
Digital I/O.
Oscillator crystal or clock output
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
Main oscillator feedback output connection
in RC mode, OSC2 pin outputs CLKO, which
has 1/4 the frequency of OSC1 and denotes
the instruction cycle rate.
Digital I/O.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
DIG = Digital output
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
DS39932C-page 22
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 1-4:
PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin Buffer
4444- Type Type
QFN TQFP
Description
PORTA is a bidirectional I/O port.
RA0/AN0/C1INA/ULPWU/PMA6/
RP0
RA0
AN0
C1INA
ULPWU
PMA6
RP0
19
RA1/AN1/C2INA/PMA7/RP1
RA1
AN1
C2INA
PMA7
RP1
20
RA2/AN2/VREF-/CVREF/C2INB
RA2
AN2
VREFCVREF
C2INB
21
RA3/AN3/VREF+/C1INB
RA3
AN3
VREF+
C1INB
22
RA5/AN4/SS1/HLVDIN/RP2
RA5
AN4
SS1
HLVDIN
RP2
24
RA6(1)
RA7(1)
19
I/O
I
I
I
I/O
I/O
DIG
Analog
Analog
Analog
DIG
DIG
Digital I/O.
Analog input 0.
Comparator 1 input A.
Ultra low-power wake-up input.
Parallel Master Port digital I/O.
Remappable peripheral pin 0.
I
O
I
I/O
I/O
DIG
Analog
Analog
DIG
DIG
Digital I/O.
Analog input 1.
Comparator 2 input A.
Parallel Master Port digital I/O.
Remappable peripheral pin 1.
I/O
I
O
I
I
DIG
Analog
Analog
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Comparator reference voltage output.
Comparator 2 input B.
I/O
I
I
I
DIG
Analog
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
Comparator 1 input B.
I/O
I
I
I
I/O
DIG
Analog
TTL
Analog
DIG
Digital I/O.
Analog input 4.
SPI slave select input.
High/low-voltage detect input.
Remappable peripheral pin 2.
20
21
22
24
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
DIG = Digital output
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
© 2009 Microchip Technology Inc.
DS39932C-page 23
PIC18F46J11 FAMILY
TABLE 1-4:
PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin Buffer
4444- Type Type
QFN TQFP
Description
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-ups on
all inputs.
RB0/AN12/INT0/RP3
RB0
AN12
INT0
RP3
9
RB1/AN10/PMBE/RTCC/RP4
RB1
AN10
PMBE
RTCC
RP4
10
RB2/AN8/CTEDG1/PMA3/REFO/
RP5
RB2
AN8
CTEDG1
PMA3
REFO
RP5
11
RB3/AN9/CTEDG2/PMA2/RP6
RB3
AN9
CTEDG2
PMA2
RP6
12
8
I/O
I
I
I/O
DIG
Analog
ST
DIG
Digital I/O.
Analog input 12.
External interrupt 0.
Remappable peripheral pin 3.
I/O
I
O
O
I/O
DIG
Analog
DIG
DIG
DIG
Digital I/O.
Analog input 10.
Parallel Master Port byte enable.
Asynchronous serial transmit data output.
Remappable peripheral pin 4.
I/O
I
I
O
O
I/O
DIG
Analog
ST
DIG
DIG
DIG
Digital I/O.
Analog input 8.
CTMU edge 1 input.
Parallel Master Port address.
Reference output clock.
Remappable peripheral pin 5.
I/O
I
I
O
I/O
DIG
Analog
ST
DIG
DIG
Digital I/O.
Analog input 9.
CTMU edge 2 input.
Parallel Master Port address.
Remappable peripheral pin 6.
9
10
11
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
DIG = Digital output
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
DS39932C-page 24
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 1-4:
PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin Buffer
4444- Type Type
QFN TQFP
Description
PORTB (continued)
RB4/PMA1/KBI0/RP7
RB4
PMA1
KBI0
RP7
14
RB5/PMA0/KBI1/RP8
RB5
PMA0
KBI1
RP8
15
RB6/KBI2/PGC/RP9
RB6
KBI2
PGC
RP9
16
RB7/KBI3/PGD/RP10
RB7
KBI3
PGD
17
RP10
14
I/O
I/O
I
I/O
DIG
DIG
TTL
DIG
Digital I/O.
Parallel Master Port address.
Interrupt-on-change pin.
Remappable peripheral pin 7
I/O
I/O
I
I/O
DIG
DIG
TTL
DIG
Digital I/O.
Parallel Master Port address.
Interrupt-on-change pin.
Remappable peripheral pin 8.
I/O
I
I
I/O
DIG
TTL
ST
DIG
Digital I/O.
Interrupt-on-change pin.
ICSP™ clock input.
Remappable peripheral pin 9.
I/O
I
I/O
DIG
TTL
ST
I/O
DIG
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming
data pin.
Remappable peripheral pin 10.
15
16
17
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
DIG = Digital output
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
© 2009 Microchip Technology Inc.
DS39932C-page 25
PIC18F46J11 FAMILY
TABLE 1-4:
PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin Buffer
4444- Type Type
QFN TQFP
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI/RP11
RC0
T1OSO
T1CKI
RP11
34
RC1/T1OSI/RP12
RC1
T1OSI
RP12
35
RC2/AN11/CTPLS/RP13
RC2
AN11
CTPLS
RP13
36
RC3/SCK1/SCL1/RP14
RC3
SCK1
37
32
I/O
O
I
I/O
ST
Analog
ST
DIG
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
Remappable peripheral pin 11.
I/O
I
I/O
ST
Analog
DIG
Digital I/O.
Timer1 oscillator input.
Remappable peripheral pin 12.
I/O
I
O
I/O
ST
Analog
DIG
DIG
Digital I/O.
Analog input 11.
CTMU pulse generator output.
Remappable peripheral pin 13.
I/O
I/O
ST
DIG
SCL1
I/O
I2C
RP14
I/O
DIG
Digital I/0.
Synchronous serial clock input/output for
SPI mode.
Synchronous serial clock input/output for
I2C™ mode.
Remappable peripheral pin 14.
I/O
I
I/O
I/O
ST
ST
I2C
DIG
Digital I/O.
SPI data input.
I2C data I/O.
Remappable peripheral pin 15.
I/O
O
I/O
ST
DIG
DIG
Digital /O.
SPI data output.
Remappable peripheral pin 16.
RC4/SDI1/SDA1/RP15
RC4
SDI1
SDA1
RP15
42
RC5/SDO1/RP16
RC5
SDO1
RP16
43
35
36
37
42
43
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
DIG = Digital output
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
DS39932C-page 26
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 1-4:
PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin Buffer
4444- Type Type
QFN TQFP
Description
PORTC (continued)
RC6/PMA5/TX1/CK1/RP17
RC6
PMA5
TX1
CK1
44
44
RP17
RC7/PMA4/RX1/DT1/RP18
RC7
PMA4
RX1
DT1
RP18
1
I/O
I/O
O
I/O
ST
DIG
DIG
ST
I/O
DIG
I/O
I/O
I
ST
DIG
ST
I/O
I/O
ST
DIG
Digital I/O.
Parallel Master Port address.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related
RX1/DT1).
Remappable peripheral pin 17.
1
EUSART1 asynchronous receive.
Parallel Master Port address.
EUSART1 synchronous data (see related
TX1/CK1).
Synchronous serial data output/input.
Remappable peripheral pin 18.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
DIG = Digital output
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
© 2009 Microchip Technology Inc.
DS39932C-page 27
PIC18F46J11 FAMILY
TABLE 1-4:
PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin Buffer
4444- Type Type
QFN TQFP
Description
PORTD is a bidirectional I/O port.
RD0/PMD0/SCL2
RD0
PMD0
SCL2
38
RD1/PMD1/SDA2
RD1
PMD1
SDA2
39
RD2/PMD2/RP19
RD2
PMD2
RP19
40
RD3/PMD3/RP20
RD3
PMD3
RP20
41
RD4/PMD4/RP21
RD4
PMD4
RP21
2
RD5/PMD5/RP22
RD5
PMD5
RP22
3
RD6/PMD6/RP23
RD6
PMD6
RP23
4
RD7/PMD7/RP24
RD7
PMD7
RP24
5
38
I/O
I/O
I/O
ST
DIG
I2C
Digital I/O.
Parallel Master Port data.
I2C™ data input/output.
I/O
I/O
I/O
ST
DIG
I2C
Digital I/O.
Parallel Master Port data.
I2C data input/output.
I/O
I/O
I/O
ST
DIG
DIG
Digital I/O.
Parallel Master Port data.
Remappable peripheral pin 19.
I/O
I/O
I/O
ST
DIG
DIG
Digital I/O.
Parallel Master Port data.
Remappable peripheral pin 20.
I/O
I/O
I/O
ST
DIG
DIG
Digital I/O.
Parallel Master Port data.
Remappable peripheral pin 21.
I/O
I/O
I/O
ST
DIG
DIG
Digital I/O.
Parallel Master Port data.
Remappable peripheral pin 22.
I/O
I/O
I/O
ST
DIG
DIG
Digital I/O.
Parallel Master Port data.
Remappable peripheral pin 23.
I/O
I/O
I/O
ST
DIG
DIG
Digital I/O.
Parallel Master Port data.
Remappable peripheral pin 24.
39
40
41
2
3
4
5
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
DIG = Digital output
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
DS39932C-page 28
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 1-4:
PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin Buffer
4444- Type Type
QFN TQFP
Description
PORTE is a bidirectional I/O port.
RE0/AN5/PMRD
RE0
AN5
PMRD
25
RE1/AN6/PMWR
RE1
AN6
PMWR
26
RE2/AN7/PMCS
RE2
AN7
PMCS
27
25
I/O
I
I/O
ST
Analog
DIG
Digital I/O.
Analog input 5.
Parallel Master Port input/output.
I/O
I
I/O
ST
Analog
DIG
Digital I/O.
Analog input 6.
Parallel Master Port write strobe.
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 7.
Parallel Master Port byte enable.
Ground reference for logic and I/O pins.
26
27
VSS1
6
6
P
—
VSS2
31
29
—
—
AVSS1
30
—
P
—
Ground reference for analog modules.
VDD1
8
7
P
—
VDD2
29
28
P
—
Positive supply for peripheral digital logic and
I/O pins.
VDDCORE/VCAP
23
23
VDDCORE
P
—
VCAP
P
—
Core logic power or external filter capacitor
connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator
enabled).
AVDD1
7
—
P
—
Positive supply for analog modules.
AVDD2
28
—
—
—
Positive supply for analog modules.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
DIG = Digital output
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
© 2009 Microchip Technology Inc.
DS39932C-page 29
PIC18F46J11 FAMILY
NOTES:
DS39932C-page 30
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
2.0
2.1
OSCILLATOR
CONFIGURATIONS
Overview
Devices in the PIC18F46J11 family incorporate a
different oscillator and microcontroller clock system
than general purpose PIC18F devices.
TABLE 2-1:
OSCILLATOR MODES
Mode
Description
ECPLL
External Clock Input mode, the PLL can
be enabled or disabled in software,
CLKO on RA6, apply external clock
signal to RA7.
EC
The PIC18F46J11 family has additional prescalers and
postscalers, which have been added to accommodate
a wide range of oscillator frequencies. Figure 2-1
provides an overview of the oscillator structure.
External Clock Input mode, the PLL is
always disabled, CLKO on RA6, apply
external clock signal to RA7.
HSPLL
Other oscillator features used in PIC18 enhanced
microcontrollers, such as the internal oscillator block
and clock switching, remain the same. They are
discussed later in this chapter.
High-Speed Crystal/Resonator mode,
PLL can be enabled or disabled in
software, crystal/resonator connected
between RA6 and RA7.
HS
High-Speed Crystal/Resonator mode,
PLL always disabled, crystal/resonator
connected between RA6 and RA7.
2.1.1
OSCILLATOR CONTROL
The operation of the oscillator in PIC18F46J11 family
devices is controlled through three Configuration registers and two control registers. Configuration registers,
CONFIG1L, CONFIG1H and CONFIG2L, select the
oscillator mode, PLL prescaler and CPU divider
options. As Configuration bits, these are set when the
device is programmed and left in that configuration until
the device is reprogrammed.
The OSCCON register (Register 2-2) selects the Active
Clock mode; it is primarily used in controlling clock
switching in power-managed modes. Its use is
discussed in Section 2.3.1 “Oscillator Control
Register”.
The OSCTUNE register (Register 2-1) is used to trim the
INTOSC frequency source and select the low-frequency
clock source that drives several special features. The
OSCTUNE register is also used to activate or disable the
Phase Locked Loop (PLL). Its use is described in
Section 2.2.5.1 “OSCTUNE Register”.
2.2
INTOSCPLLO Internal Oscillator mode, PLL can be
enabled or disabled in software, CLKO
on RA6, port function on RA7, the
internal oscillator block is used to derive
both the primary clock source and the
postscaled internal clock.
INTOSCPLL Internal Oscillator mode, PLL can be
enabled or disabled in software, port
function on RA6 and RA7, the internal
oscillator block is used to derive both the
primary clock source and the postscaled
internal clock.
INTOSCO
Internal Oscillator mode, PLL is always
disabled, CLKO on RA6, port function on
RA7, the output of the INTOSC
postscaler serves as both the postscaled
internal clock and the primary clock
source.
INTOSC
Internal Oscillator mode, PLL is always
disabled, port function on RA6 and RA7,
the output of the INTOSC postscaler
serves as both the postscaled internal
clock and the primary clock source.
Oscillator Types
PIC18F46J11 family devices can be operated in eight
distinct oscillator modes. Users can program the
FOSC<2:0> Configuration bits to select one of the
modes listed in Table 2-1. For oscillator modes which
produce a clock output (CLKO) on pin RA6, the output
frequency will be one fourth of the peripheral clock
frequency. The clock output stops when in Sleep mode,
but will continue during Idle mode (see Figure 2-1).
© 2009 Microchip Technology Inc.
DS39932C-page 31
PIC18F46J11 FAMILY
2.2.1
OSCILLATOR MODES
Figure 2-1 helps in understanding the oscillator
structure of the PIC18F46J11 family of devices.
FIGURE 2-1:
PIC18F46J11 FAMILY CLOCK DIAGRAM
PIC18F46J11 Family
Primary Oscillator
HS, EC
OSC2
OSCTUNE<7>
Sleep
4 x PLL(1)
OSC1
HSPLL, ECPLL, INTPLL
Secondary Oscillator
T1OSCEN
Enable
Oscillator
T1OSI
OSCCON<6:4>
OSCCON<6:4>
8 MHz
4 MHz
Internal
Oscillator
Block
2 MHz
8 MHz
(INTOSC)
Postscaler
8 MHz
Source
1 MHz
500 kHz
250 kHz
125 kHz
Internal Oscillator
Note 1:
31 kHz (INTRC)
CPU
111
110
IDLEN
101
100
011
010
001
1 31 kHz
000
0
INTRC
Source
Peripherals
MUX
T1OSC
MUX
T1OSO
Clock
Control
FOSC<2:0>
OSCCON<1:0>
Clock Source Option
for Other Modules
OSCTUNE<7>
WDT, PWRT, FSCM
and Two-Speed Start-up
8 MHz and 4 MHz are valid INTOSC postscaler settings for the PLL. Selecting other INTOSC postscaler
settings will operate the PLL outside of the specification.
DS39932C-page 32
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
2.2.2
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In HS and HSPLL Oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-2 displays
the pin connections.
The oscillator design requires the use of a parallel cut
crystal.
Note:
Use of a series cut crystal may give a frequency out of the crystal manufacturer’s
specifications.
FIGURE 2-2:
C1(1)
CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS OR HSPLL
CONFIGURATION)
OSC1
XTAL
RF(3)
Note 1:
2:
3:
PIC18F46J11
OSC2
See Table 2-2 and Table 2-3 for initial values
of C1 and C2.
A series resistor (RS) may be required for AT
strip cut crystals.
RF varies with the selected oscillator mode.
TABLE 2-2:
Osc Type
HS
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Crystal
Freq
Typical Capacitor Values
Tested:
C1
C2
4 MHz
27 pF
27 pF
8 MHz
22 pF
22 pF
20 MHz
15 pF
15 pF
Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
are not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following this table for additional
information.
Crystals Used:
4 MHz
Sleep
RS(2)
C2(1)
To
Internal
Logic
TABLE 2-3:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Typical Capacitor Values Used:
Mode
Freq
OSC1
OSC2
HS
8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
Capacitor values are for design guidance only.
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values are not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
8 MHz
20 MHz
Note 1: Higher capacitance not only increases
the stability of oscillator, but also
increases the start-up time.
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
3: Rs may be required to avoid overdriving
crystals with low drive level specification.
4: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
An internal postscaler allows users to select a clock
frequency other than that of the crystal or resonator.
Frequency division is determined by the CPDIV
Configuration bits. Users may select a clock frequency
of the oscillator frequency, or 1/2, 1/3 or 1/6 of the
frequency.
See the notes following Table 2-3 for additional
information.
Resonators Used:
4.0 MHz
8.0 MHz
16.0 MHz
© 2009 Microchip Technology Inc.
DS39932C-page 33
PIC18F46J11 FAMILY
2.2.3
EXTERNAL CLOCK INPUT
The EC and ECPLL Oscillator modes require an
external clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset (POR) or after an exit from Sleep
mode.
In the EC Oscillator mode, the oscillator frequency
divided-by-4 is available on the OSC2 pin. In the
ECPLL Oscillator mode, the PLL output divided-by-4 is
available on the OSC2 pin. This signal may be used for
test purposes or to synchronize other logic. Figure 2-3
displays the pin connections for the EC Oscillator
mode.
FIGURE 2-3:
OSC1/CLKI
Clock from
Ext. System
PIC18F46J11
FOSC/4
2.2.4
EXTERNAL CLOCK INPUT
OPERATION (EC AND
ECPLL CONFIGURATION)
OSC2/CLKO
PLL FREQUENCY MULTIPLIER
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator.
DS39932C-page 34
2.2.5
INTERNAL OSCILLATOR BLOCK
The PIC18F46J11 family devices include an internal
oscillator block which generates two different clock
signals; either can be used as the microcontroller’s
clock source. The internal oscillator may eliminate the
need for external oscillator circuits on the OSC1 and/or
OSC2 pins.
The main output (INTOSC) is an 8 MHz clock source
which can be used to directly drive the device clock. It
also drives the INTOSC postscaler, which can provide
a range of clock frequencies from 31 kHz to 8 MHz.
Additionally, the INTOSC may be used in conjunction
with the PLL to generate clock frequencies up to
32 MHz.
The other clock source is the internal RC oscillator
(INTRC), which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source. It is also enabled automatically when any of the
following are enabled:
•
•
•
•
Power-up Timer
Fail-Safe Clock Monitor
Watchdog Timer
Two-Speed Start-up
These features are discussed in more detail in
Section 25.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (page 38).
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
2.2.5.1
OSCTUNE Register
The internal oscillator’s output has been calibrated at
the factory but can be adjusted in the user’s application. This is done by writing to the OSCTUNE register
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.
When the OSCTUNE register is modified, the INTOSC
frequency will begin shifting to the new frequency. The
INTOSC clock will stabilize, typically within 1 μs. Code
execution continues during this shift. There is no
indication that the shift has occurred.
The OSCTUNE register also contains the INTSRC bit.
The INTSRC bit allows users to select which internal
oscillator provides the clock source when the 31 kHz
frequency option is selected. This is covered in more
detail in Section 2.3.1 “Oscillator Control Register”.
The 4x Phase Locked Loop (PLL) can be used with
the internal oscillator block to produce faster device
clock speeds than are normally possible with the
internal oscillator sources. When enabled, the PLL
produces a clock speed up to 32 MHz.
PLL operation is controlled through software. The
control bit, PLLEN (OSCTUNE<6>), is used to enable
or disable its operation. The PLL is available only to
INTOSC when the device is configured to use one of
the INTPLL modes as the primary clock source,
SCS<1:0> = 00 (FOSC<2:0> = 011 or 010).
Additionally, the PLL will only function when the
selected output frequency is either 4 MHz or 8 MHz
(OSCCON<6:4> = 111 or 110).
When configured for one of the PLL enabled modes, setting the PLLEN bit does not immediately switch the
device clock to the PLL output. The PLL requires up to
two milliseconds to start-up and lock, during which time,
the device continues to be clocked. Once the PLL output
is ready, the microcontroller core will automatically
switch to the PLL derived frequency.
2.2.5.2
Internal Oscillator Output Frequency
and Drift
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz.
However, this frequency may drift as VDD or temperature changes, which can affect the controller operation
in a variety of ways.
2.2.5.3
Compensating for INTOSC Drift
It is possible to adjust the INTOSC frequency by
modifying the value in the OSCTUNE register. This has
no effect on the INTRC clock source frequency.
Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should be
made, and in some cases, how large a change is
needed. When using the EUSART, for example, an
adjustment may be required when it begins to generate
framing errors or receives data with errors while in
Asynchronous mode. Framing errors indicate that the
device clock frequency is too high; to adjust for this,
decrement the value in OSCTUNE to reduce the clock
frequency. On the other hand, errors in data may suggest that the clock speed is too low; to compensate,
increment OSCTUNE to increase the clock frequency.
It is also possible to verify device clock speed against
a reference clock. Two timers may be used: one timer
is clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator. Both timers are cleared, but the timer
clocked by the reference generates interrupts. When
an interrupt occurs, the internally clocked timer is read
and both timers are cleared. If the internally clocked
timer value is greater than expected, then the internal
oscillator block is running too fast. To adjust for this,
decrement the OSCTUNE register.
Finally, an ECCP module can use free-running Timer1
(or Timer3), clocked by the internal oscillator block and
an external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
If the measured time is greater than the calculated time,
the internal oscillator block is running too fast; to
compensate, decrement the OSCTUNE register. If the
measured time is less than the calculated time, the internal oscillator block is running too slow; to compensate,
increment the OSCTUNE register.
The low-frequency INTRC oscillator operates independently of the INTOSC source. Any changes in INTOSC
across voltage and temperature are not necessarily
reflected by changes in INTRC and vice versa.
© 2009 Microchip Technology Inc.
DS39932C-page 35
PIC18F46J11 FAMILY
REGISTER 2-1:
OSCTUNE: OSCILLATOR TUNING REGISTER (ACCESS F9Bh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INTSRC
PLLEN
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived directly from INTRC internal oscillator
bit 6
PLLEN: Frequency Multiplier Enable bit
1 = PLL enabled
0 = PLL disabled
bit 5-0
TUN<5:0>: Frequency Tuning bits
011111 = Maximum frequency
011110
•
•
•
000001
000000 = Center frequency; oscillator module is running at the calibrated frequency
111111
•
•
•
100000 = Minimum frequency
2.3
Clock Sources and Oscillator
Switching
Like previous PIC18 enhanced devices, the
PIC18F46J11 family includes a feature that allows the
device clock source to be switched from the main
oscillator to an alternate, low-frequency clock source.
PIC18F46J11 family devices offer two alternate clock
sources. When an alternate clock source is enabled,
the various power-managed operating modes are
available.
Essentially, there are three clock sources for these
devices:
• Primary Oscillators
• Secondary Oscillators
• Internal Oscillator Block
The Primary Oscillators include the External Crystal
and Resonator modes, the External Clock modes and
the internal oscillator block. The particular mode is
defined by the FOSC<2:0> Configuration bits. The
details of these modes are covered earlier in this
chapter.
DS39932C-page 36
The Secondary Oscillators are external sources that
are not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power-managed mode.
PIC18F46J11 family devices offer the Timer1 oscillator
as a secondary oscillator. This oscillator, in all
power-managed modes, is often the time base for
functions such as a Real-Time Clock (RTC). Most often,
a 32.768 kHz watch crystal is connected between the
RC0/T1OSO/T1CKI/RP11 and RC1/T1OSI/RP12 pins.
Like the HS Oscillator mode circuits, loading capacitors
are also connected from each pin to ground. The Timer1
oscillator is discussed in more detail in Section 12.5
“Timer1 Oscillator”.
In addition to being a primary clock source, the
postscaled internal clock is available as a
power-managed mode clock source. The INTRC
source is also used as the clock source for several
special features, such as the WDT and Fail-Safe Clock
Monitor (FSCM).
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
2.3.1
OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 2-2) controls several
aspects of the device clock’s operation, both in
full-power operation and in power-managed modes.
The System Clock Select bits, SCS<1:0>, select the
clock source. The available clock sources are the
primary clock (defined by the FOSC<2:0> Configuration bits), the secondary clock (Timer1 oscillator) and
the postscaled internal clock.The clock source changes
immediately, after one or more of the bits is written to,
following a brief clock transition interval. The SCS bits
are cleared on all forms of Reset.
The Internal Oscillator Frequency Select bits,
IRCF<2:0>, select the frequency output provided on the
postscaled internal clock line. The choices are the
INTRC source, the INTOSC source (8 MHz) or one of
the frequencies derived from the INTOSC postscaler
(31 kHz to 4 MHz). If the postscaled internal clock is
supplying the device clock, changing the states of these
bits will have an immediate change on the internal oscillator’s output. On device Resets, the default output
frequency of the INTOSC postscaler is set at 4 MHz.
When an output frequency of 31 kHz is selected
(IRCF<2:0> = 000), users may choose the internal
oscillator, which acts as the source. This is done with
the INTSRC bit in the OSCTUNE register
(OSCTUNE<7>). Setting this bit selects INTOSC as a
31.25 kHz clock source by enabling the divide-by-256
output of the INTOSC postscaler. Clearing INTSRC
selects INTRC (nominally 31 kHz) as the clock source.
This option allows users to select the tunable and more
precise INTOSC as a clock source, while maintaining
power savings with a very low clock speed. Regardless
of the setting of INTSRC, INTRC always remains the
clock source for features such as the WDT and the
FSCM.
The IDLEN bit determines if the device goes into Sleep
mode, or one of the Idle modes, when the SLEEP
instruction is executed.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0
“Low-Power Modes”.
Note 1: The Timer1 crystal driver is enabled by
setting the T1OSCEN bit in the Timer1
Control register (T1CON<3>). If the
Timer1 oscillator is not enabled, then any
attempt to select the Timer1 clock source
will be ignored, unless the CONFIG2L
register’s T1DIG bit is set.
2: If Timer1 is driving a crystal, it is recommended that the Timer1 oscillator be
operating and stable prior to switching to
it as the clock source; otherwise, a very
long delay may occur while the Timer1
oscillator starts.
2.3.2
OSCILLATOR TRANSITIONS
PIC18F46J11 family devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum
of two cycles of the old clock source and three to four
cycles of the new clock source. This formula assumes
that the new clock source is stable.
Clock transitions are discussed in more detail in
Section 3.1.2 “Entering Power-Managed Modes”.
The OSTS and T1RUN bits indicate which clock source
is currently providing the device clock. The OSTS bit
indicates that the Oscillator Start-up Timer (OST) has
timed out and the primary clock is providing the device
clock in primary clock modes. The T1RUN bit
(T1CON<6>) indicates when the Timer1 oscillator is
providing the device clock in secondary clock modes.
In power-managed modes, only one of these bits will
be set at any time. If none of these bits are set, the
INTRC is providing the clock or the internal oscillator
block has just started and is not yet stable.
© 2009 Microchip Technology Inc.
DS39932C-page 37
PIC18F46J11 FAMILY
REGISTER 2-2:
OSCCON: OSCILLATOR CONTROL REGISTER (ACCESS FD3h)
R/W-0
R/W-1
R/W-1
R/W-0
R-1(1)
U-1
R/W-0
R/W-0
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
—
SCS1
SCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IDLEN: Idle Enable bit
1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Sleep mode on SLEEP instruction
bit 6-4
IRCF<2:0>: Internal Oscillator Frequency Select bits
111 = 8 MHz (INTOSC drives clock directly)
110 = 4 MHz(2)
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (from either INTOSC/256 or INTRC directly)(3)
bit 3
OSTS: Oscillator Start-up Time-out Status bit(1)
1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running
0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready
bit 2
Unimplemented: Read as ‘1’
bit 1-0
SCS<1:0>: System Clock Select bits
11 = Postscaled internal clock (INTRC/INTOSC derived)
10 = Reserved
01 = Timer1 oscillator
00 = Primary clock source (INTOSC postscaler output when FOSC<2:0> = 001 or 000)
00 = Primary clock source (CPU divider output for other values of FOSC<2:0>)
Note 1:
2:
3:
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
Default output frequency of INTOSC on Reset (4 MHz).
Source selected by the INTSRC bit (OSCTUNE<7>).
DS39932C-page 38
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
2.4
Reference Clock Output
The ROSSLP and ROSEL bits (REFOCON<5:4>)
control the availability of the reference output during
Sleep mode. The ROSEL bit determines if the oscillator
is on OSC1 and OSC2, or the current system clock
source is used for the reference clock output. The
ROSSLP bit determines if the reference source is
available on RB2 when the device is in Sleep mode.
In addition to the peripheral clock/4 output in certain
oscillator modes, the device clock in the PIC18F46J11
family can also be configured to provide a reference
clock output signal to a port pin. This feature is available in all oscillator configurations and allows the user
to select a greater range of clock submultiples to drive
external devices in the application.
To use the reference clock output in Sleep mode, both
the ROSSLP and ROSEL bits must be set. The device
clock must also be configured for an EC or HS mode;
otherwise, the oscillator on OSC1 and OSC2 will be
powered down when the device enters Sleep mode.
Clearing the ROSEL bit allows the reference output
frequency to change as the system clock changes
during any clock switches.
This reference clock output is controlled by the
REFOCON register (Register 2-3). Setting the ROON
bit (REFOCON<7>) makes the clock signal available
on the REFO (RB2) pin. The RODIV<3:0> bits enable
the selection of 16 different clock divider options.
REGISTER 2-3:
REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER (BANKED F3Dh)
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ROON
—
ROSSLP
ROSEL
RODIV3
RODIV2
RODIV1
RODIV0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
ROON: Reference Oscillator Output Enable bit
1 = Reference oscillator enabled on REFO pin
0 = Reference oscillator disabled
bit 6
Unimplemented: Read as ‘0’
bit 5
ROSSLP: Reference Oscillator Output Stop in Sleep bit
1 = Reference oscillator continues to run in Sleep
0 = Reference oscillator is disabled in Sleep
bit 4
ROSEL: Reference Oscillator Source Select bit
1 = Primary oscillator used as the base clock(1)
0 = System clock used as the base clock; base clock reflects any clock switching of the device
bit 3-0
RODIV<3:0>: Reference Oscillator Divisor Select bits
1111 = Base clock value divided by 32,768
1110 = Base clock value divided by 16,384
1101 = Base clock value divided by 8,192
1100 = Base clock value divided by 4,096
1011 = Base clock value divided by 2,048
1010 = Base clock value divided by 1,024
1001 = Base clock value divided by 512
1000 = Base clock value divided by 256
0111 = Base clock value divided by 128
0110 = Base clock value divided by 64
0101 = Base clock value divided by 32
0100 = Base clock value divided by 16
0011 = Base clock value divided by 8
0010 = Base clock value divided by 4
0001 = Base clock value divided by 2
0000 = Base clock value
Note 1:
The crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in
Sleep mode.
© 2009 Microchip Technology Inc.
DS39932C-page 39
PIC18F46J11 FAMILY
2.5
Effects of Power-Managed Modes
on Various Clock Sources
When the PRI_IDLE mode is selected, the designated
primary oscillator continues to run without
interruption. In secondary clock modes (SEC_RUN
and SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the device clock
source. The 31 kHz INTRC output can be used directly
to provide the clock and may be enabled to support
various special features regardless of the
power-managed mode (see Section 25.2 “Watchdog
Timer (WDT)”, Section 25.4 “Two-Speed Start-up”
and Section 25.5 “Fail-Safe Clock Monitor” for more
information on WDT, FSCM and Two-Speed Start-up).
The INTOSC output at 8 MHz may be used directly to
clock the device or may be divided down by the
postscaler. The INTOSC output is disabled if the clock
is provided directly from the INTRC output.
If Sleep mode is selected, all clock sources, which are
no longer required, are stopped. Since all the transistor
switching currents have been stopped, Sleep mode
achieves the lowest current consumption of the device
(only leakage currents) outside of Deep Sleep mode.
2.6
Power-up Delays
Power-up delays are controlled by two timers so that no
external Reset circuitry is required for most applications. The delays ensure that the device is kept in
Reset until the device power supply is stable under
normal circumstances and the primary clock is operating and stable. For additional information on power-up
delays, see Section 4.6 “Power-up Timer (PWRT)”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 28-13).
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (HS mode). The OST does
this by counting 1024 oscillator cycles before allowing
the oscillator to clock the device.
There is a delay of interval, TCSD (parameter 38,
Table 28-13), following POR, while the controller
becomes ready to execute instructions. This delay runs
concurrently with any other delays. This may be the only
delay that occurs when any of the internal oscillator or
EC modes are used as the primary clock source.
Enabling any on-chip feature that will operate during
Sleep mode increases the current consumed during
Sleep mode. The INTRC is required to support WDT
operation. The Timer1 oscillator may be operating to
support an RTC. Other features may be operating that
do not require a device clock source (i.e., MSSP slave,
PMP, INTx pins, etc.). Peripherals that may add
significant current consumption are listed in
Section 28.2 “DC Characteristics: Power-Down and
Supply Current PIC18F46J50 Family (Industrial)”.
DS39932C-page 40
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
3.0
LOW-POWER MODES
The IDLEN bit (OSCCON<7>) controls CPU clocking
and the SCS<1:0> bits (OSCCON<1:0>) select the
clock source. The individual modes, bit settings, clock
sources and affected modules are summarized in
Table 3-1.
The PIC18F46J11 family devices can manage power
consumption through clocking to the CPU and the
peripherals. In general, reducing the clock frequency
and the amount of circuitry being clocked reduces power
consumption.
3.1.1
For managing power in an application, the primary
modes of operation are:
The SCS<1:0> bits allow the selection of one of three
clock sources for power-managed modes. They are:
•
•
•
•
• Primary clock source – Defined by the
FOSC<2:0> Configuration bits
• Timer1 clock – Provided by the secondary
oscillator
• Postscaled internal clock – Derived from the
internal oscillator block
Run Mode
Idle Mode
Sleep Mode
Deep Sleep Mode
Additionally, there is an Ultra Low-Power Wake-up
(ULPWU) mode for generating an interrupt-on-change
on RA0.
These modes define which portions of the device are
clocked and at what speed.
• The Run and Idle modes can use any of the three
available clock sources (primary, secondary or
internal oscillator blocks).
• The Sleep mode does not use a clock source.
The ULPWU mode on RA0 allows a slow falling voltage
to generate an interrupt-on-change on RA0 without
excess current consumption. See Section 3.7 “Ultra
Low-Power Wake-up”.
The power-managed modes include several
power-saving features offered on previous PIC®
devices, such as clock switching, ULPWU and Sleep
mode. In addition, the PIC18F46J11 family devices add
a new power-managed Deep Sleep mode.
3.1
Selecting Power-Managed Modes
Selecting a power-managed mode requires these
decisions:
• Will the CPU be clocked?
• If so, which clock source will be used?
© 2009 Microchip Technology Inc.
3.1.2
CLOCK SOURCES
ENTERING POWER-MANAGED
MODES
Switching from one clock source to another begins by
loading the OSCCON register. The SCS<1:0> bits
select the clock source.
Changing these bits causes an immediate switch to the
new clock source, assuming that it is running. The
switch also may be subject to clock transition delays.
These delays are discussed in Section 3.1.3 “Clock
Transitions and Status Indicators” and subsequent
sections.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many transitions may be done by changing the oscillator select
bits, the IDLEN bit or the DSEN bit prior to issuing a
SLEEP instruction.
If the IDLEN and DSEN bits are already configured
correctly, it may only be necessary to perform a SLEEP
instruction to switch to the desired mode.
DS39932C-page 41
PIC18F46J11 FAMILY
TABLE 3-1:
LOW-POWER MODES
DSCONH<7>
Mode
DSEN(1)
OSCCON<7,1:0>
(1)
IDLEN
SCS<1:0>
Module Clocking
CPU
Peripherals
Available Clock and Oscillator Source
Sleep
0
0
N/A
Off
Off
Timer1 oscillator and/or RTCC optionally enabled
Deep
Sleep(2)
PRI_RUN
1
0
N/A
Off
—
0
N/A
00
Clocked
Clocked
SEC_RUN
RC_RUN
PRI_IDLE
0
0
0
N/A
N/A
1
01
11
00
Clocked
Clocked
Off
Clocked
Clocked
Clocked
RTCC can run uninterrupted using the Timer1 or
internal low-power RC oscillator
The normal, full-power execution mode. Primary clock
source (defined by FOSC<2:0>)
Secondary – Timer1 oscillator
Postscaled internal clock
Primary clock source (defined by FOSC<2:0>)
SEC_IDLE
0
1
01
Off
Clocked Secondary – Timer1 oscillator
RC_IDLE
0
1
11
Off
Clocked Postscaled internal clock
Note 1: IDLEN and DSEN reflect their values when the SLEEP instruction is executed.
2: Deep Sleep entirely shuts off the voltage regulator for ultra low-power consumption. See Section 3.6 “Deep
Sleep Mode” for more information.
3.1.3
CLOCK TRANSITIONS AND STATUS
INDICATORS
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Two bits indicate the current clock source and its
status:
OSTS
(OSCCON<3>)
and
T1RUN
(T1CON<6>). In general, only one of these bits will be
set in a given power-managed mode. When the OSTS
bit is set, the primary clock would be providing the
device clock. When the T1RUN bit is set, the Timer1
oscillator would be providing the clock. If neither of
these bits is set, INTRC would be clocking the device.
Note:
3.1.4
Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep or Deep
Sleep mode, or one of the Idle modes,
depending on the setting of the IDLEN bit.
MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN and DSEN bits at the time the instruction is executed. If another SLEEP instruction is executed, the
device will enter the power-managed mode specified
by IDLEN and DSEN at that time. If IDLEN or DSEN
have changed, the device will enter the new
power-managed mode specified by the new setting.
3.2
Run Modes
3.2.1
PRI_RUN MODE
The PRI_RUN mode is the normal, full-power execution mode of the microcontroller. This is also the default
mode upon a device Reset unless Two-Speed Start-up
is enabled (see Section 25.4 “Two-Speed Start-up”
for details). In this mode, the OSTS bit is set (see
Section 2.3.1 “Oscillator Control Register”).
3.2.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of low-power consumption while still using a
high-accuracy clock source.
SEC_RUN mode is entered by setting the SCS<1:0>
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 3-1), the primary
oscillator is shut down, the T1RUN bit (T1CON<6>) is
set and the OSTS bit is cleared.
Note:
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS<1:0> bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, device clocks will be delayed until
the oscillator has started. In such situations, initial oscillator operation is far from
stable and unpredictable operation may
result.
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
DS39932C-page 42
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
from the Timer1 oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
FIGURE 3-1:
Figure 3-2). When the clock switch is complete, the
T1RUN bit is cleared, the OSTS bit is set and the
primary clock would be providing the clock. The IDLEN
and SCS bits are not affected by the wake-up; the
Timer1 oscillator continues to run.
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
1
T1OSI
2
3
n-1
Q3
Q4
Q1
Q2
Q3
n
Clock Transition
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
PC
FIGURE 3-2:
PC + 2
PC + 4
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1
Q2
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
TOST(1)
TPLL(1)
1
PLL Clock
Output
2
n-1 n
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
SCS<1:0> Bits Changed
Note 1:
PC + 2
PC
PC + 4
OSTS Bit Set
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
© 2009 Microchip Technology Inc.
DS39932C-page 43
PIC18F46J11 FAMILY
3.2.3
RC_RUN MODE
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
block while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 3-4). When the clock
switch is complete, the OSTS bit is set and the primary
clock is providing the device clock. The IDLEN and
SCS bits are not affected by the switch. The INTRC
clock source will continue to run if either the WDT or the
FSCM is enabled.
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. This mode provides the best power conservation of all the Run modes while still executing code.
It works well for user applications, which are not highly
timing-sensitive or do not require high-speed clocks at
all times.
This mode is entered by setting the SCS<1:0> bits
(OSCCON<1:0>) to ‘11’. When the clock source is
switched to the internal oscillator block (see
Figure 3-3), the primary oscillator is shut down and the
OSTS bit is cleared.
FIGURE 3-3:
TRANSITION TIMING TO RC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
1
INTRC
2
3
n-1
Q3
Q4
Q1
Q2
Q3
n
Clock Transition
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
PC
FIGURE 3-4:
PC + 2
PC + 4
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q1
Q2
Q3
Q4
Q2 Q3 Q4 Q1 Q2 Q3
Q1
INTRC
OSC1
TOST(1)
TPLL(1)
1
PLL Clock
Output
2
n-1 n
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
SCS<1:0> Bits Changed
Note 1:
DS39932C-page 44
PC + 2
PC
PC + 4
OSTS Bit Set
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
3.3
Sleep Mode
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS<1:0> bits
becomes ready (see Figure 3-6), or it will be clocked
from the internal oscillator if either the Two-Speed
Start-up or the FSCM is enabled (see Section 25.0
“Special Features of the CPU”). In either case, the
OSTS bit is set when the primary clock is providing the
device clocks. The IDLEN and SCS bits are not
affected by the wake-up.
The power-managed Sleep mode is identical to the
legacy Sleep mode offered in all other PIC devices. It is
entered by clearing the IDLEN bit (the default state on
device Reset) and executing the SLEEP instruction.
This shuts down the selected oscillator (Figure 3-5). All
clock source status bits are cleared.
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep mode. If
the WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
FIGURE 3-5:
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
PC
FIGURE 3-6:
PC + 2
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
OSC1
TOST(1)
PLL Clock
Output
TPLL(1)
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
Note 1:
PC + 2
PC + 4
PC + 6
OSTS Bit Set
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
© 2009 Microchip Technology Inc.
DS39932C-page 45
PIC18F46J11 FAMILY
3.4
Idle Modes
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS<1:0> bits; however, the
CPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instruction provides a quick method of switching from a
given Run mode to its corresponding Idle mode.
If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD
(parameter 38, Table 28-13) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle or Sleep mode, a WDT time-out will
result in a WDT wake-up to the Run mode currently
specified by the SCS<1:0> bits.
3.4.1
PRI_IDLE MODE
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing-sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm up” or transition from another
oscillator.
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval, TCSD, is
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the
wake-up, the OSTS bit remains set. The IDLEN and
SCS bits are not affected by the wake-up (see
Figure 3-8).
3.4.2
SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set IDLEN first, then
set SCS<1:0> to ‘01’ and execute SLEEP. When the
clock source is switched to the Timer1 oscillator, the
primary oscillator is shut down, the OSTS bit is cleared
and the T1RUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After an interval
of TCSD following the wake event, the CPU begins executing code being clocked by the Timer1 oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 3-8).
Note:
The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, peripheral clocks will be delayed
until the oscillator has started. In such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN
first, then set the SCS bits to ‘00’ and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC<1:0> Configuration bits. The OSTS bit
remains set (see Figure 3-7).
DS39932C-page 46
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
FIGURE 3-7:
TRANSITION TIMING FOR ENTRY TO IDLE MODE
Q1
Q4
Q3
Q2
Q1
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
FIGURE 3-8:
PC
PC + 2
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1
Q2
Q3
Q4
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
© 2009 Microchip Technology Inc.
DS39932C-page 47
PIC18F46J11 FAMILY
3.4.3
RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the internal
oscillator block. This mode allows for controllable
power conservation during Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then
clear the SCS bits and execute SLEEP. When the clock
source is switched to the INTOSC block, the primary
oscillator is shut down and the OSTS bit is cleared.
When a wake event occurs, the peripherals continue to
be clocked from the internal oscillator block. After a
delay of TCSD following the wake event, the CPU
begins executing code being clocked by the INTRC.
The IDLEN and SCS bits are not affected by the
wake-up. The INTRC source will continue to run if
either the WDT or the FSCM is enabled.
3.5
Exiting Idle and Sleep Modes
An exit from Sleep mode, or any of the Idle modes, is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes sections (see Section 3.2 “Run Modes”,
Section 3.3 “Sleep Mode” and Section 3.4 “Idle
Modes”).
3.5.1
EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode, or the Sleep mode, to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 8.0 “Interrupts”).
A fixed delay of interval, TCSD, following the wake
event, is required when leaving Sleep and Idle modes.
This delay is required for the CPU to prepare for
execution. Instruction execution resumes on the first
clock cycle following this delay.
3.5.2
EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
DS39932C-page 48
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see Section 3.2 “Run
Modes” and Section 3.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 25.2 “Watchdog
Timer (WDT)”).
The WDT and postscaler are cleared by one of the
following events:
• Executing a SLEEP or CLRWDT instruction
• The loss of a currently selected clock source (if
the FSCM is enabled)
3.5.3
EXIT BY RESET
Exiting an Idle or Sleep mode by Reset automatically
forces the device to run from the INTRC.
3.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode (where the primary clock source
is not stopped) and the primary clock source is
the EC mode
• PRI_IDLE mode and the primary clock source is
the ECPLL mode
In these instances, the primary clock source either does
not require an oscillator start-up delay, since it is already
running (PRI_IDLE), or normally does not require an
oscillator start-up delay (EC). However, a fixed delay of
interval, TCSD, following the wake event, is still required
when leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes on
the first clock cycle following this delay.
3.6
Deep Sleep Mode
Deep Sleep mode brings the device into its lowest
power consumption state without requiring the use of
external switches to remove power from the device.
During deep sleep, the on-chip VDDCORE voltage
regulator is powered down, effectively disconnecting
power to the core logic of the microcontroller.
Note:
Since Deep Sleep mode powers down the
microcontroller by turning off the on-chip
VDDCORE voltage regulator, Deep Sleep
capability is available only on PIC18FXXJ
members in the device family. The on-chip
voltage regulator is not available in
PIC18LFXXJ members of the device
family, and therefore, they do not support
Deep Sleep.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
On devices that support it, the Deep Sleep mode is
entered by:
• Setting the REGSLP (WDTCON<7>) bit (the
default state on device Reset)
• Clearing the IDLEN bit (the default state on device
Reset)
• Setting the DSEN bit (DSCONH<7>)
• Executing the SLEEP instruction immediately after
setting DSEN (no delay in between)
In order to minimize the possibility of inadvertently entering Deep Sleep, the DSEN bit is cleared in hardware
two instruction cycles after having been set. Therefore,
in order to enter Deep Sleep, the SLEEP instruction must
be executed in the immediate instruction cycle after setting DSEN. If DSEN is not set when Sleep is executed,
the device will enter conventional Sleep mode instead.
During Deep Sleep, the core logic circuitry of the
microcontroller is powered down to reduce leakage
current. Therefore, most peripherals and functions of
the microcontroller become unavailable during Deep
Sleep. However, a few specific peripherals and functions are powered directly from the VDD supply rail of
the microcontroller, and therefore, can continue to
function in Deep Sleep.
Entering Deep Sleep mode clears the DSWAKEL register. However, if the Real-Time Clock and Calendar
(RTCC) is enabled prior to entering Deep Sleep, it will
continue to operate uninterrupted.
The device has dedicated low-power Brown-out Reset
(DSBOR) and Watchdog Timer Reset (DSWDT) for
monitoring voltage and time-out events in Deep Sleep.
The DSBOR and DSWDT are independent of the standard BOR and WDT used with other power-managed
modes (Run, Idle and Sleep).
When a wake event occurs in Deep Sleep mode (by
MCLR Reset, RTCC alarm, INT0 interrupt, ULPWU or
DSWDT), the device will exit Deep Sleep mode and
perform a Power-on Reset (POR). When the device is
released from Reset, code execution will resume at the
device’s Reset vector.
3.6.1
PREPARING FOR DEEP SLEEP
Because VDDCORE could fall below the SRAM retention
voltage while in Deep Sleep mode, SRAM data could
be lost in Deep Sleep. Exiting Deep Sleep mode
causes a POR; as a result, most Special Function
Registers will reset to their default POR values.
3.6.2
I/O PINS DURING DEEP SLEEP
During Deep Sleep, the general purpose I/O pins will
retain their previous states.
Pins that are configured as inputs (TRIS bit set) prior to
entry into Deep Sleep will remain high-impedance
during Deep Sleep.
Pins that are configured as outputs (TRIS bit clear)
prior to entry into Deep Sleep will remain as output pins
during Deep Sleep. While in this mode, they will drive
the output level determined by their corresponding LAT
bit at the time of entry into Deep Sleep.
When the device wakes back up, the I/O pin behavior
depends on the type of wake-up source.
If the device wakes back up by an RTCC alarm, INT0
interrupt, DSWDT or ULPWU event, all I/O pins will
continue to maintain their previous states, even after the
device has finished the POR sequence and is executing
application code again. Pins configured as inputs during
Deep Sleep will remain high-impedance, and pins configured as outputs will continue to drive their previous
value.
After waking up, the TRIS and LAT registers will be
reset, but the I/O pins will still maintain their previous
states. If firmware modifies the TRIS and LAT values for
the I/O pins, they will not immediately go to the newly
configured states. Once the firmware clears the
RELEASE bit (DSCONL<0>), the I/O pins will be
“released”. This causes the I/O pins to take the states
configured by their respective TRIS and LAT bit values.
If the Deep Sleep BOR (DSBOR) circuit is enabled, and
VDD drops below the DSBOR and VDD rail POR thresholds, the I/O pins will be immediately released similar to
clearing the RELEASE bit. All previous state information will be lost, including the general purpose DSGPR0
and DSGPR1 contents. See Section 3.6.5 “Deep
Sleep Brown Out Reset (DSBOR)” for additional
details about this scenario.
If a MCLR Reset event occurs during Deep Sleep, the I/O
pins will also be released automatically, but in this case,
the DSGPR0 and DSGPR1 contents will remain valid.
In all other Deep Sleep wake-up cases, application
firmware needs to clear the RELEASE bit in order to
reconfigure the I/O pins.
Applications needing to save a small amount of data
throughout a Deep Sleep cycle can save the data to the
general purpose DSGPR0 and DSGPR1 registers. The
contents of these registers are preserved while the
device is in Deep Sleep, and will remain valid throughout
an entire Deep Sleep entry and wake-up sequence.
© 2009 Microchip Technology Inc.
DS39932C-page 49
PIC18F46J11 FAMILY
3.6.3
DEEP SLEEP WAKE-UP SOURCES
While in Deep Sleep mode, the device can be awakened
by a MCLR, POR, RTCC, INT0 I/O pin interrupt,
DSWDT or ULPWU event. After waking, the device performs a POR. When the device is released from Reset,
code execution will begin at the device’s Reset vector.
The software can determine if the wake-up was caused
from an exit from Deep Sleep mode by reading the DS
bit (WDTCON<3>). If this bit is set, the POR was
caused by a Deep Sleep exit. The DS bit must be
manually cleared by the software.
The software can determine the wake event source by
reading the DSWAKEH and DSWAKEL registers.
When the application firmware is done using the
DSWAKEH and DSWAKEL status registers, individual
bits do not need to be manually cleared before entering
Deep Sleep again. When entering Deep Sleep mode,
these registers are automatically cleared.
3.6.3.1
Wake-up Event Considerations
Deep Sleep wake-up events are only monitored while
the processor is fully in Deep Sleep mode. If a wake-up
event occurs before Deep Sleep mode is entered, the
event status will not be reflected in the DSWAKE registers. If the wake-up source asserts prior to entering
Deep Sleep, the CPU may go to the interrupt vector (if
the wake source has an interrupt bit and the interrupt is
fully enabled), and may abort the Deep Sleep entry
sequence by executing past the SLEEP instruction. In
this case, a wake-up event handler should be placed
after the SLEEP instruction to process the event and
re-attempt entry into Deep Sleep if desired.
When the device is in Deep Sleep with more than one
wake-up source simultaneously enabled, only the first
wake-up source to assert will be detected and logged
in the DSWAKEH/DSWAKEL status registers.
DS39932C-page 50
3.6.4
DEEP SLEEP WATCHDOG TIMER
(DSWDT)
Deep Sleep has its own dedicated WDT (DSWDT) with
a postscaler for time-outs of 2.1 ms to 25.7 days,
configurable through the bits, DSWDTPS<3:0>
(CONFIG3L<7:4>).
The DSWDT can be clocked from either the INTRC or
the T1OSC/T1CKI input. If the T1OSC/T1CKI source will
be used with a crystal, the T1OSCEN bit in the T1CON
register needs to be set prior to entering Deep Sleep.
The reference clock source is configured through the
DSWDTOSC bit (CONFIG3L<0>).
DSWDT is enabled through the DSWDTEN bit
(CONFIG3L<3>). Entering Deep Sleep mode automatically clears the DSWDT. See Section 25.0 “Special
Features of the CPU” for more information.
3.6.5
DEEP SLEEP BROWN OUT RESET
(DSBOR)
The Deep Sleep module contains a dedicated Deep
Sleep BOR (DSBOR) circuit. This circuit may be
optionally enabled through the DSBOREN Configuration
bit (CONFIG3L<2>).
The DSBOR circuit monitors the VDD supply rail
voltage. The behavior of the DSBOR circuit is
described in Section 4.4 “Brown-out Reset (BOR)”.
3.6.6
RTCC PERIPHERAL AND DEEP
SLEEP
The RTCC can operate uninterrupted during Deep
Sleep mode. It can wake the device from Deep Sleep by
configuring an alarm.
The RTCC clock source is configured with the RTCOSC
bit (CONFIG3L<1>). The available reference clock
sources are the INTRC and T1OSC/T1CKI. If the INTRC
is used, the RTCC accuracy will directly depend on the
INTRC tolerance. For more information on configuring
the RTCC peripheral, see Section 16.0 “Real-Time
Clock and Calendar (RTCC)”.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
3.6.7
TYPICAL DEEP SLEEP SEQUENCE
This section gives the typical sequence for using the
Deep Sleep mode. Optional steps are indicated, and
additional information is given in notes at the end of the
procedure.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
Enable DSWDT (optional).(1)
Configure DSWDT clock source (optional).(2)
Enable DSBOR (optional).(1)
Enable RTCC (optional).(3)
Configure the RTCC peripheral (optional).(3)
Configure the ULPWU peripheral (optional).(4)
Enable the INT0 Interrupt (optional).(4)
Context save SRAM data by writing to the
DSGPR0 and DSGPR1 registers (optional).
Set the REGSLP bit (WDTCON<7>) and clear
the IDLEN bit (OSCCON<7>).
If using an RTCC alarm for wake-up, wait until
the RTCSYNC (RTCCFG<4>) bit is clear.
Enter Deep Sleep mode by setting the DSEN bit
(DSCONH<7>) and issuing a SLEEP instruction.
These two instructions must be executed back
to back.
Once a wake-up event occurs, the device will
perform a POR reset sequence. Code execution
resumes at the device’s Reset vector.
Determine if the device exited Deep Sleep by
reading the Deep Sleep bit, DS (WDTCON<3>).
This bit will be set if there was an exit from Deep
Sleep mode.
Clear the Deep Sleep bit, DS (WDTCON<3>).
Determine the wake-up source by reading the
DSWAKEH and DSWAKEL registers.
Determine if a DSBOR event occurred during
Deep Sleep mode by reading the DSBOR bit
(DSCONL<1>).
Read the DSGPR0 and DSGPR1 context save
registers (optional).
Clear the RELEASE bit (DSCONL<0>).
3.6.8
DEEP SLEEP FAULT DETECTION
If during Deep Sleep the device is subjected to unusual
operating conditions, such as an Electrostatic Discharge (ESD) event, it is possible that the internal
circuit states used by the Deep Sleep module could
become corrupted. If this were to happen, the device
may exhibit unexpected behavior, such as a failure to
wake back up.
In order to prevent this type of scenario from occurring,
the Deep Sleep module includes automatic
self-monitoring capability. During Deep Sleep, critical
internal nodes are continuously monitored in order to
detect possible Fault conditions (which would not
ordinarily occur). If a Fault condition is detected, the
circuitry will set the DSFLT status bit (DSWAKEL<7>)
and automatically wake the microcontroller from Deep
Sleep, causing a POR Reset.
During Deep Sleep, the Fault detection circuitry is
always enabled and does not require any specific
configuration prior to entering Deep Sleep.
Note 1: DSWDT and DSBOR are enabled
through the devices’ Configuration bits.
For more information, see Section 25.1
“Configuration Bits”.
2: The DSWDT and RTCC clock sources
are selected through the devices’ Configuration bits. For more information, see
Section 25.1 “Configuration Bits”.
3: For more information, see Section 16.0
“Real-Time Clock and Calendar
(RTCC)”.
4: For more information on configuring this
peripheral, see Section 3.7 “Ultra
Low-Power Wake-up”.
© 2009 Microchip Technology Inc.
DS39932C-page 51
PIC18F46J11 FAMILY
3.6.9
DEEP SLEEP MODE REGISTERS
Deep Sleep mode registers are
Register 3-1 through Register 3-6.
REGISTER 3-1:
provided
in
DSCONH: DEEP SLEEP CONTROL HIGH BYTE REGISTER (BANKED F4Dh)
R/W-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
DSEN(1)
—
—
—
—
(Reserved)
DSULPEN
RTCWDIS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
DSEN: Deep Sleep Enable bit(1)
1 = Deep Sleep mode is entered on a SLEEP command
0 = Sleep mode is entered on a SLEEP command
bit 6-3
Unimplemented: Read as ‘0’
bit 2
(Reserved): Always write ‘0’ to this bit
bit 1
DSULPEN: Ultra Low-Power Wake-up Module Enable bit
1 = ULPWU module is enabled in Deep Sleep
0 = ULPWU module is disabled in Deep Sleep
bit 0
RTCWDIS: RTCC Wake-up Disable bit
1 = Wake-up from RTCC is disabled
0 = Wake-up from RTCC is enabled
Note 1:
x = Bit is unknown
In order to enter Deep Sleep, Sleep must be executed immediately after setting DSEN.
REGISTER 3-2:
DSCONL: DEEP SLEEP CONTROL LOW BYTE REGISTER (BANKED F4Ch)
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0(1)
R/W-0(1)
—
—
—
—
—
ULPWDIS
DSBOR
RELEASE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-3
Unimplemented: Read as ‘0’
bit 2
ULPWDIS: Ultra Low-Power Wake-up Disable bit
1 = ULPWU wake-up source is disabled
0 = ULPWU wake-up source is enabled (must also set DSULPEN = 1)
bit 1
DSBOR: Deep Sleep BOR Event Status bit
1 = DSBOREN was enabled and VDD dropped below the DSBOR arming voltage during Deep Sleep,
but did not fall below VDSBOR
0 = DSBOREN was disabled or VDD did not drop below the DSBOR arming voltage during Deep Sleep
bit 0
RELEASE: I/O Pin State Release bit
Upon waking from Deep Sleep, the I/O pins maintain their previous states. Clearing this bit will
release the I/O pins and allow their respective TRIS and LAT bits to control their states.
Note 1:
This is the value when VDD is initially applied.
DS39932C-page 52
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 3-3:
DSGPR0: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 0
(BANKED F4Eh)
R/W-xxxx(1)
Deep Sleep Persistent General Purpose bits
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
x = Bit is unknown
Deep Sleep Persistent General Purpose bits
Contents are retained even in Deep Sleep mode.
All register bits are maintained unless: VDDCORE drops below the normal BOR threshold outside of Deep
Sleep, or the device is in Deep Sleep and the dedicated DSBOR is enabled and VDD drops below the
DSBOR threshold, or DSBOR is enabled or disabled, but VDD is hard cycled to near VSS.
REGISTER 3-4:
DSGPR1: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 1
(BANKED F4Fh)
R/W-xxxx(1)
Deep Sleep Persistent General Purpose bits
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
x = Bit is unknown
Deep Sleep Persistent General Purpose bits
Contents are retained even in Deep Sleep mode.
All register bits are maintained unless: VDDCORE drops below the normal BOR threshold outside of Deep
Sleep, or, the device is in Deep Sleep and the dedicated DSBOR is enabled and VDD drops below the
DSBOR threshold, or DSBOR is enabled or disabled, but VDD is hard cycled to near VSS.
© 2009 Microchip Technology Inc.
DS39932C-page 53
PIC18F46J11 FAMILY
REGISTER 3-5:
DSWAKEH: DEEP SLEEP WAKE HIGH BYTE REGISTER (BANKED F4Bh)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
DSINT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-1
Unimplemented: Read as ‘0’
bit 0
DSINT0: Interrupt-on-Change bit
1 = Interrupt-on-change was asserted during Deep Sleep
0 = Interrupt-on-change was not asserted during Deep Sleep
REGISTER 3-6:
DSWAKEL: DEEP SLEEP WAKE LOW BYTE REGISTER (BANKED F4Ah)
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-1
DSFLT
—
DSULP(2)
DSWDT(2)
DSRTC(2)
DSMCLR(2)
—
DSPOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
DSFLT: Deep Sleep Fault Detected bit
1 = A Deep Sleep Fault was detected during Deep Sleep
0 = A Deep Sleep fault was not detected during Deep Sleep
bit 6
Unimplemented: Read as ‘0’
bit 5
DSULP: Ultra Low-Power Wake-up status bit(2)
1 = An Ultra Low-Power Wake-up event occurred during Deep Sleep
0 = An Ultra Low-Power Wake-up event did not occur during Deep Sleep
bit 4
DSWDT: Deep Sleep Watchdog Timer Time-out bit(2)
1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep
0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep
bit 3
DSRTC: Real-Time Clock and Calendar Alarm bit(2)
1 = The Real-Time Clock/Calendar triggered an alarm during Deep Sleep
0 = The Real-Time Clock /Calendar did not trigger an alarm during Deep Sleep
bit 2
DSMCLR: MCLR Event bit(2)
1 = The MCLR pin was asserted during Deep Sleep
0 = The MCLR pin was not asserted during Deep Sleep
bit 1
Unimplemented: Read as ‘0’
bit 0
DSPOR: Power-on Reset Event bit
1 = The VDD supply POR circuit was active and a POR event was detected(1)
0 = The VDD supply POR circuit was not active, or was active, but did not detect a POR event
Note 1:
2:
Unlike the other bits in this register, this bit can be set outside of Deep Sleep.
If multiple wake-up triggers are fired around the same time, only the first wake-up event triggered will have
its wake-up status bit set.
DS39932C-page 54
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
3.7
Ultra Low-Power Wake-up
The Ultra Low-Power Wake-up (ULPWU) on RA0 allows
a slow falling voltage to generate an interrupt without
excess current consumption.
Follow these steps to use this feature:
1.
2.
3.
4.
5.
6.
7.
8.
Configure a remappable output pin to output the
ULPOUT signal.
Map an INTx interrupt-on-change input function
to the same pin as used for the ULPOUT output
function. Alternatively, in step 1, configure
ULPOUT to output onto a PORTB
interrupt-on-change pin.
Charge the capacitor on RA0 by configuring the
RA0 pin to an output and setting it to ‘1’.
Enable interrupt for the corresponding pin
selected in step 2.
Stop charging the capacitor by configuring RA0
as an input.
Discharge the capacitor by setting the ULPEN
and ULPSINK bits in the WDTCON register.
Configure Sleep mode.
Enter Sleep mode.
When the voltage on RA0 drops below VIL, an interrupt
will be generated, which will cause the device to
wake-up and execute the next instruction.
This feature provides a low-power technique for
periodically waking up the device from Sleep mode.
The time-out is dependent on the discharge time of the
RC circuit on RA0.
When the ULPWU module causes the device to
wake-up from Sleep mode, the WDTCON<ULPLVL>
bit is set. When the ULPWU module causes the device
to wake-up from Deep Sleep, the DSULP
(DSWAKEL<5>) bit is set. Software can check these
bits upon wake-up to determine the wake-up source.
Also in Sleep mode, only the remappable output function, ULPWU, will output this bit value to an RPn pin for
externally detecting wake-up events.
© 2009 Microchip Technology Inc.
See Example 3-1 for initializing the ULPWU module.
Note:
For module-related bit definitions, see the
WDTCON register in Section 25.2
“Watchdog Timer (WDT)” and the
DSWAKEL register (Register 3-6).
A series resistor between RA0 and the external
capacitor provides overcurrent protection for the
RA0/AN0/C1INA/ULPWU/RP0 pin and can allow for
software calibration of the time-out (see Figure 3-9).
FIGURE 3-9:
RA0
SERIAL RESISTOR
R1
C1
A timer can be used to measure the charge time and
discharge time of the capacitor. The charge time can
then be adjusted to provide the desired interrupt delay.
This technique will compensate for the affects of
temperature, voltage and component accuracy. The
peripheral can also be configured as a simple Programmable Low-Voltage Detect (LVD) or temperature
sensor.
Note:
For more information, refer to AN879,
“Using the Microchip Ultra Low-Power
Wake-up Module” application note
(DS00879).
DS39932C-page 55
PIC18F46J11 FAMILY
EXAMPLE 3-1:
ULTRA LOW-POWER WAKE-UP INITIALIZATION
//*********************************************************************************
//Configure a remappable output pin with interrupt capability
//for ULPWU function (RP21 => RD4/INT1 in this example)
//*********************************************************************************
RPOR21 = 13;// ULPWU function mapped to RP21/RD4
RPINR1 = 21;// INT1 mapped to RP21 (RD4)
//***************************
//Charge the capacitor on RA0
//***************************
TRISAbits.TRISA0 = 0;
PORTAbits.RA0 = 1;
for(i = 0; i < 10000; i++) Nop();
//**********************************
//Stop Charging the capacitor on RA0
//**********************************
TRISAbits.TRISA0 = 1;
//*****************************************
//Enable the Ultra Low Power Wakeup module
//and allow capacitor discharge
//*****************************************
WDTCONbits.ULPEN = 1;
WDTCONbits.ULPSINK = 1;
//******************************************
//For Sleep, Enable Interrupt for ULPW.
//******************************************
INTCON3bits.INT1IF = 0;
INTCON3bits.INT1IE = 1;
//********************
//Configure Sleep Mode
//********************
//For Sleep
OSCCONbits.IDLEN = 0;
//For Deep Sleep
OSCCONbits.IDLEN = 0;// enable deep sleep
DSCONHbits.DSEN = 1;// Note: must be set just before executing Sleep();
//****************
//Enter Sleep Mode
//****************
Sleep();
// for sleep, execution will resume here
// for deep sleep, execution will restart at reset vector (use WDTCONbits.DS to detect)
DS39932C-page 56
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
4.0
RESET
The PIC18F46J11 family of devices differentiates
among various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
i)
j)
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog Timer (WDT) Reset (during
execution)
Configuration Mismatch (CM)
Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
Deep Sleep Reset
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers.
Figure 4-1 provides a simplified block diagram of the
on-chip Reset circuit.
4.1
RCON Register
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the register
indicate that a specific Reset event has occurred. In
most cases, these bits can only be set by the event and
must be cleared by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 4.7 “Reset State of
Registers”.
The ECON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 8.0 “Interrupts”.
For information on WDT Resets, see Section 25.2
“Watchdog Timer (WDT)”. For Stack Reset events,
see Section 5.1.4.4 “Stack Full and Underflow
Resets” and for Deep Sleep mode, see Section 3.6
“Deep Sleep Mode”.
FIGURE 4-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET Instruction
Configuration Word Mismatch
Stack
Pointer
Stack Full/Underflow Reset
External Reset
MCLR
( )_IDLE
Deep Sleep Reset
Sleep
WDT
Time-out
VDD Rise
Detect
POR Pulse
VDD
Brown-out
Reset(1)
S
PWRT
32 ms
PWRT
INTRC
Note 1:
66 ms
11-Bit Ripple Counter
R
Q
Chip_Reset
The Brown-out Reset is not available in PIC18LF2XJ11 and PIC18LF4XJ11 devices.
© 2009 Microchip Technology Inc.
DS39932C-page 57
PIC18F46J11 FAMILY
REGISTER 4-1:
RCON: RESET CONTROL REGISTER (ACCESS FD0h)
R/W-0
U-0
R/W-1
R/W-1
R-1
R-1
R/W-0
R/W-0
IPEN
—
CM
RI
TO
PD
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6
Unimplemented: Read as ‘0’
bit 5
CM: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has not occurred
0 = A Configuration Mismatch Reset has occurred (must be set in software after a Configuration
Mismatch Reset occurs)
bit 4
RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset (must be set in software after a
Brown-out Reset occurs)
bit 3
TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2
PD: Power-Down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
bit 1
POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent
Power-on Resets may be detected.
2: If the on-chip voltage regulator is disabled, BOR remains ‘0’ at all times. See Section 4.4.1 “Detecting
BOR” for more information.
3: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘1’ by software immediately after a Power-on Reset).
DS39932C-page 58
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
4.2
Master Clear (MCLR)
The Master Clear Reset (MCLR) pin provides a method
for triggering a hard external Reset of the device. A
Reset is generated by holding the pin low. PIC18
extended microcontroller devices have a noise filter in
the MCLR Reset path, which detects and ignores small
pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
4.3
Power-on Reset (POR)
A POR condition is generated on-chip whenever VDD
rises above a certain threshold. This allows the device
to start in the initialized state when VDD is adequate for
operation.
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 kΩ to 10 kΩ) to VDD. This will
eliminate external RC components usually needed to
create a POR delay.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
POR events are captured by the POR bit (RCON<1>).
The state of the bit is set to ‘0’ whenever a Power-on
Reset occurs; it does not change for any other Reset
event. POR is not reset to ‘1’ by any hardware event.
To capture multiple events, the user manually resets
the bit to ‘1’ in software following any POR.
4.4
Brown-out Reset (BOR)
“F” devices incorporate two types of BOR circuits: one
which monitors VDDCORE and one which monitors VDD.
Only one BOR circuit can be active at a time. When in
normal Run mode, Idle or normal Sleep modes, the
BOR circuit that monitors VDDCORE is active and will
cause the device to be held in BOR if VDDCORE drops
below VBOR (parameter D005). Once VDDCORE rises
back above VBOR, the device will be held in Reset until
the expiration of the Power-up Timer, with period,
TPWRT (parameter 33).
Additionally, if any I/O pins had been configured as outputs during Deep Sleep, these pins will be tri-stated
and the device will no longer be held in Deep Sleep.
Once the VDD voltage recovers back above the
VDSBOR threshold, and once the core voltage regulator
achieves a VDDCORE voltage above VBOR, the device
will begin executing code again normally, but the DS bit
in the WDTCON register will not be set. The device
behavior will be similar to hard cycling all power to the
device.
On “LF” devices, the VDDCORE BOR circuit is always
disabled because the internal core voltage regulator is
disabled. Instead of monitoring VDDCORE, PIC18LF
devices in this family can use the VDD BOR circuit to
monitor VDD excursions below the VDSBOR threshold.
The VDD BOR circuit can be disabled by setting the
DSBOREN bit = 0.
The VDD BOR circuit is enabled when DSBOREN = 1
on “LF” devices, or on “F” devices while in Deep Sleep
with DSBOREN = 1. When enabled, the VDD BOR
circuit is extremely low power (typ. 200 nA) during normal operation above ~2.3V on VDD. If VDD drops below
this DSBOR arming level when the VDD BOR circuit is
enabled, the device may begin to consume additional
current (typ. 50 μA) as internal features of the circuit
power up. The higher current is necessary to achieve
more accurate sensing of the VDD level. However, the
device will not enter Reset until VDD falls below the
VDSBOR threshold.
4.4.1
DETECTING BOR
The BOR bit always resets to ‘0’ on any VDDCORE, BOR
or POR event. This makes it difficult to determine if a
Brown-out Reset event has occurred just by reading
the state of BOR alone. A more reliable method is to
simultaneously check the state of both POR and BOR.
This assumes that the POR bit is reset to ‘1’ in software
immediately after any Power-on Reset event. If BOR is
‘0’ while POR is ‘1’, it can be reliably assumed that a
Brown-out Reset event has occurred.
If the voltage regulator is disabled (LF devices), the
VDDCORE BOR functionality is disabled. In this case,
the BOR bit cannot be used to determine a Brown-out
Reset event. The BOR bit is still cleared by a Power-on
Reset event.
During Deep Sleep operation, the on-chip core voltage
regulator is disabled and VDDCORE is allowed to drop to
ground levels. If the Deep Sleep BOR circuit is enabled
by the DSBOREN Configuration bit (CONFIG3L<2> = 1),
it will monitor VDD. If VDD drops below the VDSBOR
threshold, the device will be held in a Reset state
similar to POR. All registers will be set back to their POR
Reset values and the contents of the DSGPR0 and
DSGPR1 holding registers will be lost.
© 2009 Microchip Technology Inc.
DS39932C-page 59
PIC18F46J11 FAMILY
4.5
Configuration Mismatch (CM)
4.6
The Configuration Mismatch (CM) Reset is designed to
detect, and attempt to recover from, random memory
corrupting events. These include Electrostatic
Discharge (ESD) events, which can cause widespread
single bit changes throughout the device and result in
catastrophic failure.
In PIC18FXXJ Flash devices, the device Configuration
registers (located in the configuration memory space)
are continuously monitored during operation by comparing their values to complimentary shadow registers.
If a mismatch is detected between the two sets of
registers, a CM Reset automatically occurs. These
events are captured by the CM bit (RCON<5>). The
state of the bit is set to ‘0’ whenever a CM event occurs;
it does not change for any other Reset event.
A CM Reset behaves similarly to a MCLR, RESET
instruction, WDT time-out or Stack Event Resets. As
with all hard and power Reset events, the device
Configuration Words are reloaded from the Flash
Configuration Words in program memory as the device
restarts.
FIGURE 4-2:
Power-up Timer (PWRT)
PIC18F46J11 family devices incorporate an on-chip
PWRT to help regulate the POR process. The PWRT is
always enabled. The main function is to ensure that the
device voltage is stable before code is executed.
The Power-up Timer (PWRT) of the PIC18F46J11 family
devices is a 5-bit counter which uses the INTRC source
as the clock input. This yields an approximate time
interval of 32 x 32 μs = 1 ms. While the PWRT is
counting, the device is held in Reset.
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation. See DC parameter 33 (TPWRT) for
details.
4.6.1
TIME-OUT SEQUENCE
The PWRT time-out is invoked after the POR pulse has
cleared. The total time-out will vary based on the status
of the PWRT. Figure 4-2, Figure 4-3, Figure 4-4 and
Figure 4-5 all depict time-out sequences on power-up
with the PWRT.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the PWRT will expire. Bringing
MCLR high will begin execution immediately if a clock
source is available (Figure 4-4). This is useful for
testing purposes, or to synchronize more than one
PIC18FXXXX device operating in parallel.
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
DS39932C-page 60
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
FIGURE 4-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 4-4:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
FIGURE 4-5:
SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
3.3V
VDD
0V
1V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
© 2009 Microchip Technology Inc.
DS39932C-page 61
PIC18F46J11 FAMILY
4.7
Reset State of Registers
TO, PD, POR and BOR) are set or cleared differently in
different Reset situations, as indicated in Table 4-1.
These bits are used in software to determine the nature
of the Reset.
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Table 4-2 describes the Reset states for all of the
Special Function Registers. These are categorized by
POR and BOR, MCLR and WDT Resets, and WDT
wake-ups.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register (CM, RI,
TABLE 4-1:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Condition
Program
Counter(1)
RCON Register
STKPTR Register
CM
RI
TO
PD
POR
BOR
STKFUL STKUNF
Power-on Reset
0000h
1
1
1
1
0
0
0
0
RESET instruction
0000h
u
0
u
u
u
u
u
u
Brown-out Reset
0000h
1
1
1
1
u
0
u
u
Configuration Mismatch Reset
0000h
0
u
u
u
u
u
u
u
MCLR Reset during
power-managed Run modes
0000h
u
u
1
u
u
u
u
u
MCLR Reset during
power-managed Idle modes and
Sleep mode
0000h
u
u
1
0
u
u
u
u
MCLR Reset during full-power
execution
0000h
u
u
u
u
u
u
u
u
Stack Full Reset (STVREN = 1)
0000h
u
u
u
u
u
u
1
u
Stack Underflow Reset
(STVREN = 1)
0000h
u
u
u
u
u
u
u
1
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h
u
u
u
u
u
u
u
1
WDT time-out during full-power
or power-managed Run modes
0000h
u
u
0
u
u
u
u
u
WDT time-out during
power-managed Idle or Sleep
modes
PC + 2
u
u
0
0
u
u
u
u
Interrupt exit from
power-managed modes
PC + 2
u
u
u
0
u
u
u
u
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
DS39932C-page 62
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Applicable Devices
Power-on Reset,
Brown-out Reset,
Wake From
Deep Sleep
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
TOSU
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---0 0000(1)
TOSH
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu(1)
TOSL
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu(1)
STKPTR
PIC18F2XJ11
PIC18F4XJ11
00-0 0000
uu-0 0000
uu-u uuuu(1)
PCLATU
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
PCLATH
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
PCL
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
PC + 2(2)
TBLPTRU
PIC18F2XJ11
PIC18F4XJ11
--00 0000
--00 0000
--uu uuuu
TBLPTRH
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
TBLPTRL
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
TABLAT
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
PRODH
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
INTCON
PIC18F2XJ11
PIC18F4XJ11
0000 000x
0000 000u
uuuu uuuu(3)
INTCON2
PIC18F2XJ11
PIC18F4XJ11
1111 1111
1111 1111
uuuu uuuu(3)
INTCON3
PIC18F2XJ11
PIC18F4XJ11
1100 0000
1100 0000
uuuu uuuu(3)
INDF0
PIC18F2XJ11
PIC18F4XJ11
N/A
N/A
N/A
POSTINC0
PIC18F2XJ11
PIC18F4XJ11
N/A
N/A
N/A
POSTDEC0
PIC18F2XJ11
PIC18F4XJ11
N/A
N/A
N/A
PREINC0
PIC18F2XJ11
PIC18F4XJ11
N/A
N/A
N/A
PLUSW0
PIC18F2XJ11
PIC18F4XJ11
N/A
N/A
N/A
FSR0H
PIC18F2XJ11
PIC18F4XJ11
---- xxxx
---- uuuu
---- uuuu
FSR0L
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
PIC18F2XJ11
PIC18F4XJ11
N/A
N/A
N/A
POSTINC1
PIC18F2XJ11
PIC18F4XJ11
N/A
N/A
N/A
POSTDEC1
PIC18F2XJ11
PIC18F4XJ11
N/A
N/A
N/A
PREINC1
PIC18F2XJ11
PIC18F4XJ11
N/A
N/A
N/A
PLUSW1
PIC18F2XJ11
PIC18F4XJ11
N/A
N/A
N/A
FSR1H
PIC18F2XJ11
PIC18F4XJ11
---- xxxx
---- uuuu
---- uuuu
FSR1L
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
BSR
PIC18F2XJ11
PIC18F4XJ11
---- 0000
---- 0000
---- uuuu
INDF2
PIC18F2XJ11
PIC18F4XJ11
N/A
N/A
N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
5: Not implemented for PIC18F2XJ11 devices.
© 2009 Microchip Technology Inc.
DS39932C-page 63
PIC18F46J11 FAMILY
TABLE 4-2:
Register
POSTINC2
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
PIC18F2XJ11
PIC18F4XJ11
Power-on Reset,
Brown-out Reset,
Wake From
Deep Sleep
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
N/A
N/A
N/A
POSTDEC2
PIC18F2XJ11
PIC18F4XJ11
N/A
N/A
N/A
PREINC2
PIC18F2XJ11
PIC18F4XJ11
N/A
N/A
N/A
PLUSW2
PIC18F2XJ11
PIC18F4XJ11
N/A
N/A
N/A
FSR2H
PIC18F2XJ11
PIC18F4XJ11
---- xxxx
---- uuuu
---- uuuu
FSR2L
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
PIC18F2XJ11
PIC18F4XJ11
---x xxxx
---u uuuu
---u uuuu
TMR0H
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
TMR0L
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
PIC18F2XJ11
PIC18F4XJ11
1111 1111
1111 1111
uuuu uuuu
OSCCON
PIC18F2XJ11
PIC18F4XJ11
0110 q000
0110 q000
0110 q00u
CM1CON
PIC18F2XJ11
PIC18F4XJ11
0001 1111
uuuu uuuu
uuuu uuuu
CM2CON
PIC18F2XJ11
PIC18F4XJ11
0001 1111
uuuu uuuu
uuuu uuuu
(4)
RCON
PIC18F2XJ11
PIC18F4XJ11
0-11 1100
0-qq qquu
u-qq qquu
TMR1H
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1L
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
PIC18F2XJ11
PIC18F4XJ11
0000 0000
u0uu uuuu
uuuu uuuu
TMR2
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
PR2
PIC18F2XJ11
PIC18F4XJ11
1111 1111
1111 1111
uuuu uuuu
T2CON
PIC18F2XJ11
PIC18F4XJ11
-000 0000
-000 0000
-uuu uuuu
SSP1BUF
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSP1ADD
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
SSP1MSK
PIC18F2XJ11
PIC18F4XJ11
1111 1111
uuuu uuuu
uuuu uuuu
SSP1STAT
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
SSP1CON1
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
SSP1CON2
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
ADRESH
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESL
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
ADCON1
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
WDTCON
PIC18F2XJ11
PIC18F4XJ11
1qq- 0000
0qq- 0000
uqq- uuuu
PSTR1CON
PIC18F2XJ11
PIC18F4XJ11
00-0 0001
00-0 0001
uu-u uuuu
ECCP1AS
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
5: Not implemented for PIC18F2XJ11 devices.
DS39932C-page 64
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset,
Wake From
Deep Sleep
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
ECCP1DEL
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
CCPR1H
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1L
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
PSTR2CON
PIC18F2XJ11
PIC18F4XJ11
00-0 0001
00-0 0001
uu-u uuuu
ECCP2AS
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
ECCP2DEL
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
CCPR2H
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2L
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
CTMUCONH
PIC18F2XJ11
PIC18F4XJ11
0-00 000-
0-00 000-
u-uu uuu-
CTMUCONL
PIC18F2XJ11
PIC18F4XJ11
0000 00xx
0000 00xx
uuuu uuuu
CTMUICON
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
SPBRG1
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
RCREG1
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
TXREG1
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXSTA1
PIC18F2XJ11
PIC18F4XJ11
0000 0010
0000 0010
uuuu uuuu
RCSTA1
PIC18F2XJ11
PIC18F4XJ11
0000 000x
0000 000x
uuuu uuuu
SPBRG2
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
RCREG2
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
TXREG2
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
TXSTA2
PIC18F2XJ11
PIC18F4XJ11
0000 0010
0000 0010
uuuu uuuu
EECON2
PIC18F2XJ11
PIC18F4XJ11
---- ----
---- ----
---- ----
EECON1
PIC18F2XJ11
PIC18F4XJ11
--00 x00-
--00 u00-
--00 u00-
IPR3
PIC18F2XJ11
PIC18F4XJ11
1111 1111
1111 1111
uuuu uuuu
PIR3
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu(3)
PIE3
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
IPR2
PIC18F2XJ11
PIC18F4XJ11
1111 1111
1111 1111
uuuu uuuu
PIR2
PIC18F2XJ11
PIC18F4XJ11
000- 0000
000- 0000
uuu- uuuu(3)
PIE2
PIC18F2XJ11
PIC18F4XJ11
000- 0000
000- 0000
uuu- uuuu
IPR1
PIC18F2XJ11
PIC18F4XJ11
1111 1111
1111 1111
uuuu uuuu
PIR1
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu(3)
PIE1
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
5: Not implemented for PIC18F2XJ11 devices.
© 2009 Microchip Technology Inc.
DS39932C-page 65
PIC18F46J11 FAMILY
TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset,
Wake From
Deep Sleep
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
uuuu uuuu
RCSTA2
PIC18F2XJ11
PIC18F4XJ11
0000 000x
0000 000x
OSCTUNE
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
T1GCON
PIC18F2XJ11
PIC18F4XJ11
0000 0x00
0000 0x00
uuuu uuuu
RTCVALH
PIC18F2XJ11
PIC18F4XJ11
0xxx xxxx
0uuu uuuu
0uuu uuuu
RTCVALL
PIC18F2XJ11
PIC18F4XJ11
0xxx xxx
0uuu uuuu
0uuu uuuu
T3GCON
PIC18F2XJ11
PIC18F4XJ11
0000 0x00
uuuu uxuu
uuuu uxuu
TRISE(5)
PIC18F2XJ11
PIC18F4XJ11
---- -111
---- -111
---- -uuu
(5)
TRISD
PIC18F2XJ11
PIC18F4XJ11
1111 1111
1111 1111
uuuu uuuu
TRISC
PIC18F2XJ11
PIC18F4XJ11
1111 1111
1111 1111
uuuu uuuu
TRISB
PIC18F2XJ11
PIC18F4XJ11
1111 1111
1111 1111
uuuu uuuu
TRISA
PIC18F2XJ11
PIC18F4XJ11
111- 1111
111- 1111
uuu- uuuu
ALRMCFG
PIC18F2XJ11
PIC18F4XJ11
0000 0000
uuuu uuuu
uuuu uuuu
ALRMRPT
PIC18F2XJ11
PIC18F4XJ11
0000 0000
uuuu uuuu
uuuu uuuu
ALRMVALH
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
ALRMVALL
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
(5)
LATE
PIC18F2XJ11
PIC18F4XJ11
---- -xxx
---- -uuu
---- -uuu
LATD(5)
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATC
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATB
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATA
PIC18F2XJ11
PIC18F4XJ11
xxx- xxxx
uuu- uuuu
uuu- uuuu
DMACON1
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
DMACON2
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
HLVDCON
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
(5)
PORTE
PIC18F2XJ11
PIC18F4XJ11
00-- -xxx
uu-- -uuu
uu-- -uuu
PORTD(5)
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTB
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
PIC18F2XJ11
PIC18F4XJ11
xxx- xxxx
uuu- uuuu
uuu- uuuu
SPBRGH1
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
BAUDCON1
PIC18F2XJ11
PIC18F4XJ11
0100 0-00
0100 0-00
uuuu u-uu
SPBRGH2
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
BAUDCON2
PIC18F2XJ11
PIC18F4XJ11
0100 0-00
0100 0-00
uuuu u-uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
5: Not implemented for PIC18F2XJ11 devices.
DS39932C-page 66
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset,
Wake From
Deep Sleep
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
TMR3H
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
T3CON
PIC18F2XJ11
PIC18F4XJ11
0000 -000
uuuu -uuu
uuuu -uuu
TMR4
PIC18F2XJ11
PIC18F4XJ11
0000 0000
uuuu uuuu
uuuu uuuu
PR4
PIC18F2XJ11
PIC18F4XJ11
1111 1111
1111 1111
uuuu uuuu
T4CON
PIC18F2XJ11
PIC18F4XJ11
-000 0000
-000 0000
-uuu uuuu
SSP2BUF
PIC18F2XJ11
PIC18F4XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSP2ADD
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
SSP2MASK
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
SSP2STAT
PIC18F2XJ11
PIC18F4XJ11
1111 1111
1111 1111
uuuu uuuu
SSP2CON1
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
SSP2CON2
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
CMSTAT
PIC18F2XJ11
PIC18F4XJ11
---- --11
---- --11
---- --uu
PMADDRH
PIC18F2XJ11
PIC18F4XJ11
-000 0000
-000 0000
-uuu uuuu
PMDOUT1H(5)
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
PMADDRL
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
PMDOUT1L
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
PMDIN1H
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
PMDIN1L
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
(5)
TXADDRL
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
TXADDRH
PIC18F2XJ11
PIC18F4XJ11
---- 0000
---- 0000
---- uuuu
RXADDRL
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
RXADDRH
PIC18F2XJ11
PIC18F4XJ11
---- 0000
---- 0000
---- uuuu
DMABCL
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
DMABCH
PIC18F2XJ11
PIC18F4XJ11
---- --00
---- --00
---- --uu
PMCONH
PIC18F2XJ11
PIC18F4XJ11
0-00 0000
0-00 0000
u-uu uuuu
PMCONL
PIC18F2XJ11
PIC18F4XJ11
000- 0000
000- 0000
uuu- uuuu
PMMODEH
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
PMMODEL
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
PMDOUT2H
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
PMDOUT2L
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
PMDIN2H
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
PMDIN2L
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
5: Not implemented for PIC18F2XJ11 devices.
© 2009 Microchip Technology Inc.
DS39932C-page 67
PIC18F46J11 FAMILY
TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on Reset,
Brown-out Reset,
Wake From
Deep Sleep
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
Applicable Devices
PMEH
PIC18F2XJ11
PMEL
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
PMSTATH
PIC18F2XJ11
PIC18F4XJ11
00-- 0000
00-- 0000
uu-- uuuu
PMSTATL
PIC18F2XJ11
PIC18F4XJ11
10-- 1111
10-- 1111
uu-- uuuu
CVRCON(5)
PIC18F2XJ11
PIC18F4XJ11
0000 0000
0000 0000
uuuu uuuu
ANCON1
PIC18F2XJ11
PIC18F4XJ11
00-0 0000
uu-u uuuu
uu-u uuuu
ANCON0
PIC18F2XJ11
PIC18F4XJ11
0000 0000
uuuu uuuu
uuuu uuuu
ODCON1
PIC18F2XJ11
PIC18F4XJ11
---- --00
---- --uu
---- --uu
ODCON2
PIC18F2XJ11
PIC18F4XJ11
---- --00
---- --uu
---- --uu
ODCON3
PIC18F2XJ11
PIC18F4XJ11
---- --00
---- --uu
---- --uu
RTCCFG
PIC18F2XJ11
PIC18F4XJ11
0-00 0000
u-uu uuuu
u-uu uuuu
RTCCAL
PIC18F2XJ11
PIC18F4XJ11
0000 0000
uuuu uuuu
uuuu uuuu
REFOCON
PIC18F2XJ11
PIC18F4XJ11
0-00 0000
u-uu uuuu
u-uu uuuu
PADCFG1
PIC18F2XJ11
PIC18F4XJ11
---- -000
---- -uuu
---- -uuu
RPINR24
PIC18F2XJ11
PIC18F4XJ11
---1 1111
---1 1111
---u uuuu
RPINR23
PIC18F2XJ11
PIC18F4XJ11
---1 1111
---1 1111
---u uuuu
RPINR22
PIC18F2XJ11
PIC18F4XJ11
---1 1111
---1 1111
---u uuuu
RPINR21
PIC18F2XJ11
PIC18F4XJ11
---1 1111
---1 1111
---u uuuu
RPINR17
PIC18F2XJ11
PIC18F4XJ11
---1 1111
---1 1111
---u uuuu
RPINR16
PIC18F2XJ11
PIC18F4XJ11
---1 1111
---1 1111
---u uuuu
RPINR13
PIC18F2XJ11
PIC18F4XJ11
---1 1111
---1 1111
---u uuuu
RPINR12
PIC18F2XJ11
PIC18F4XJ11
---1 1111
---1 1111
---u uuuu
RPINR8
PIC18F2XJ11
PIC18F4XJ11
---1 1111
---1 1111
---u uuuu
RPINR7
PIC18F2XJ11
PIC18F4XJ11
---1 1111
---1 1111
---u uuuu
RPINR6
PIC18F2XJ11
PIC18F4XJ11
---1 1111
---1 1111
---u uuuu
RPINR4
PIC18F2XJ11
PIC18F4XJ11
---1 1111
---1 1111
---u uuuu
RPINR3
PIC18F2XJ11
PIC18F4XJ11
---1 1111
---1 1111
---u uuuu
RPINR2
PIC18F2XJ11
PIC18F4XJ11
---1 1111
---1 1111
---u uuuu
RPINR1
PIC18F2XJ11
PIC18F4XJ11
---1 1111
---1 1111
---u uuuu
RPOR24
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR23
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR22
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR21
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
5: Not implemented for PIC18F2XJ11 devices.
DS39932C-page 68
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset,
Wake From
Deep Sleep
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
RPOR20
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR19
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR18
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR17
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR16
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR15
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR14
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR13
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR12
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR11
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR10
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR9
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR8
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR7
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR6
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR5
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR4
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR3
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR2
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR1
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
RPOR0
PIC18F2XJ11
PIC18F4XJ11
---0 0000
---0 0000
---u uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
5: Not implemented for PIC18F2XJ11 devices.
© 2009 Microchip Technology Inc.
DS39932C-page 69
PIC18F46J11 FAMILY
NOTES:
DS39932C-page 70
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
5.0
MEMORY ORGANIZATION
There are two types of memory in PIC18 Flash
microcontrollers:
• Program Memory
• Data RAM
As Harvard architecture devices, the data and program
memories use separate busses; this allows for
concurrent access of the two memory spaces.
Section 6.0 “Flash Program Memory” provides
additional information on the operation of the Flash
program memory.
FIGURE 5-1:
5.1
Program Memory Organization
PIC18 microcontrollers implement a 21-bit program
counter, which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2-Mbyte address returns all ‘0’s (a
NOP instruction).
The PIC18F46J11 family offers a range of on-chip
Flash program memory sizes, from 16 Kbytes (up to
8,192 single-word instructions) to 64 Kbytes
(32,768 single-word instructions).
Figure 5-1 provides the program memory maps for
individual family devices.
MEMORY MAPS FOR PIC18F46J11 FAMILY DEVICES
CALL, CALLW, RCALL,
RETURN, RETFIE, RETLW,
ADDULNK, SUBULNK
PC<20:0>
21
Stack Level 1
•••
Stack Level 31
PIC18FX4J11
PIC18FX5J50
PIC18FX6J11
On-Chip
Memory
On-Chip
Memory
On-Chip
Memory
Config. Words
000000h
003FFFh
Config. Words
Config. Words
Unimplemented
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
Read as ‘0’
00FFFFh
User Memory Space
007FFFh
1FFFFFF
Note:
Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail.
© 2009 Microchip Technology Inc.
DS39932C-page 71
PIC18F46J11 FAMILY
5.1.1
HARD MEMORY VECTORS
5.1.2
FLASH CONFIGURATION WORDS
All PIC18 devices have a total of three hard-coded
return vectors in their program memory space. The
Reset vector address is the default value to which the
program counter returns on all device Resets; it is
located at 0000h.
Because PIC18F46J11 family devices do not have
persistent configuration memory, the top four words of
on-chip program memory are reserved for configuration
information. On Reset, the configuration information is
copied into the Configuration registers.
PIC18 devices also have two interrupt vector
addresses for handling high-priority and low-priority
interrupts. The high-priority interrupt vector is located at
0008h and the low-priority interrupt vector at 0018h.
Figure 5-2 provides their locations in relation to the
program memory map.
The Configuration Words are stored in their program
memory location in numerical order, starting with the
lower byte of CONFIG1 at the lowest address and
ending with the upper byte of CONFIG4.
FIGURE 5-2:
HARD VECTOR AND
CONFIGURATION WORD
LOCATIONS FOR
PIC18F46J11 FAMILY
DEVICES
Reset Vector
0000h
High-Priority Interrupt Vector
0008h
Low-Priority Interrupt Vector
0018h
Table 5-1 provides the actual addresses of the Flash
Configuration Word for devices in the PIC18F46J11
family. Figure 5-2 displays their location in the memory
map with other memory vectors.
Additional details on the device Configuration Words
are provided in Section 25.1 “Configuration Bits”.
TABLE 5-1:
Device
PIC18F24J11
PIC18F44J11
On-Chip
Program Memory
PIC18F25J11
PIC18F45J11
PIC18F26J11
PIC18F46J11
Flash Configuration Words
FLASH CONFIGURATION
WORD FOR PIC18F46J11
FAMILY DEVICES
Program
Memory
(Kbytes)
Configuration
Word
Addresses
16
3FF8h to 3FFFh
32
7FF8h to 7FFFh
64
FFF8h to FFFFh
(Top of Memory-7)
(Top of Memory)
Read as ‘0’
1FFFFFh
Legend:
(Top of Memory) represents upper boundary
of on-chip program memory space (see
Figure 5-1 for device-specific values).
Shaded area represents unimplemented
memory. Areas are not shown to scale.
DS39932C-page 72
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
5.1.3
PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes to
PCL. Similarly, the upper 2 bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 5.1.6.1 “Computed
GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit (LSb) of PCL is
fixed to a value of ‘0’. The PC increments by two to
address sequential instructions in the program
memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
5.1.4
RETURN ADDRESS STACK
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALL or RCALL instruction is executed, or an interrupt is Acknowledged. The
PC value is pulled off the stack on a RETURN, RETLW
or a RETFIE instruction (and on ADDULNK and
SUBULNK instructions if the extended instruction set is
enabled). PCLATU and PCLATH are not affected by
any of the RETURN or CALL instructions.
FIGURE 5-3:
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer (SP), STKPTR. The stack space is
not part of either program or data space. The Stack
Pointer is readable and writable, and the address on
the top of the stack is readable and writable through the
Top-of-Stack Special Function Registers (SFRs). Data
can also be pushed to, or popped from, the stack using
these registers.
A CALL type instruction causes a push onto the stack.
The Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURN type instruction causes
a pop from the stack. The contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full, has overflowed or has underflowed.
5.1.4.1
Top-of-Stack Access
Only the top of the return address stack (TOS) is readable and writable. A set of three registers,
TOSU:TOSH:TOSL, holds the contents of the stack
location pointed to by the STKPTR register
(Figure 5-3). This allows users to implement a software
stack if necessary. After a CALL, RCALL or interrupt
(and ADDULNK and SUBULNK instructions if the
extended instruction set is enabled), the software can
read
the
pushed
value
by
reading
the
TOSU:TOSH:TOSL registers. These values can be
placed on a user-defined software stack. At return time,
the software can return these values to
TOSU:TOSH:TOSL and do a return.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack <20:0>
Top-of-Stack Registers
TOSU
00h
TOSH
1Ah
TOSL
34h
Top-of-Stack
© 2009 Microchip Technology Inc.
11111
11110
11101
001A34h
000D58h
Stack Pointer
STKPTR<4:0>
00010
00011
00010
00001
00000
DS39932C-page 73
PIC18F46J11 FAMILY
5.1.4.2
Return Stack Pointer (STKPTR)
The STKPTR register (Register 5-1) contains the Stack
Pointer value, the STKFUL (Stack Full) and the
STKUNF (Stack Underflow) status bits. The value of
the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. On Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System (RTOS) for return stack maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
Power-on Reset (POR).
The action that takes place when the stack becomes
full depends on the state of the Stack Overflow Reset
Enable (STVREN) Configuration bit.
Refer to Section 25.1 “Configuration Bits” for device
Configuration bits’ description.
If STVREN is set (default), the 31st push will push the
(PC + 2) value onto the stack, set the STKFUL bit and
reset the device. The STKFUL bit will remain set and
the Stack Pointer will be set to zero.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and the STKPTR will remain at 31.
REGISTER 5-1:
When the stack has been popped enough times to
unload the stack, the next pop will return zero to the PC
and set the STKUNF bit, while the Stack Pointer
remains at zero. The STKUNF bit will remain set until
cleared by software or until a POR occurs.
Note:
5.1.4.3
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack, without disturbing normal program execution
is necessary. The PIC18 instruction set includes two
instructions, PUSH and POP, that permit the TOS to be
manipulated under software control. TOSU, TOSH and
TOSL can be modified to place data or a return address
on the stack.
The PUSH instruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
The POP instruction discards the current TOS by
decrementing the Stack Pointer. The previous value
pushed onto the stack then becomes the TOS value.
STKPTR: STACK POINTER REGISTER (ACCESS FFCh)
R/C-0
R/C-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STKFUL(1)
STKUNF(1)
—
SP4
SP3
SP2
SP1
SP0
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
STKFUL: Stack Full Flag bit(1)
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6
STKUNF: Stack Underflow Flag bit(1)
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5
Unimplemented: Read as ‘0’
bit 4-0
SP<4:0>: Stack Pointer Location bits
Note 1:
x = Bit is unknown
Bits 7 and 6 are cleared by user software or by a POR.
DS39932C-page 74
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
5.1.4.4
Stack Full and Underflow Resets
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration register 1L. When STVREN is set, a full
or underflow condition sets the appropriate STKFUL or
STKUNF bit and then causes a device Reset. When
STVREN is cleared, a full or underflow condition sets
the appropriate STKFUL or STKUNF bit, but does not
cause a device Reset. The STKFUL or STKUNF bits
are cleared by the user software or a POR.
5.1.5
FAST REGISTER STACK (FRS)
5.1.6
LOOK-UP TABLES IN PROGRAM
MEMORY
There may be programming situations that require the
creation of data structures or look-up tables in program
memory. For PIC18 devices, look-up tables can be
implemented in two ways:
• Computed GOTO
• Table Reads
5.1.6.1
Computed GOTO
A computed GOTO is accomplished by adding an offset
to the PC. An example is shown in Example 5-2.
A Fast Register Stack (FRS) is provided for the
STATUS, WREG and BSR registers to provide a “fast
return” option for interrupts. This stack is only one level
deep and is neither readable nor writable. It is loaded
with the current value of the corresponding register
when the processor vectors for an interrupt. All interrupt sources push values into the Stack registers. The
values in the registers are then loaded back into the
working registers if the RETFIE, FAST instruction is
used to return from the interrupt.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
executed instruction will be one of the RETLW nn
instructions that returns the value ‘nn’ to the calling
function.
If both low-priority and high-priority interrupts are
enabled, the Stack registers cannot be used reliably to
return from low-priority interrupts. If a high-priority
interrupt occurs while servicing a low-priority interrupt,
the Stack register values stored by the low-priority
interrupt will be overwritten. In these cases, users must
save the key registers in software during a low-priority
interrupt.
In this method, only one byte may be stored in each
instruction location; room on the return address stack is
required.
If interrupt priority is not used, all interrupts may use the
FRS for returns from interrupt. If no interrupts are used,
the FRS can be used to restore the STATUS, WREG
and BSR registers at the end of a subroutine call. To
use the Fast Register Stack for a subroutine call, a
CALL label, FAST instruction must be executed to
save the STATUS, WREG and BSR registers to the
Fast Register Stack. A RETURN, FAST instruction is
then executed to restore these registers from the FRS.
Example 5-1 provides a source code example that
uses the FRS during a subroutine call and return.
EXAMPLE 5-1:
CALL SUB1, FAST
•
•
•
•
RETURN FAST
FAST REGISTER STACK
CODE EXAMPLE
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
SUB1
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
© 2009 Microchip Technology Inc.
The offset value (in WREG) specifies the number of
bytes that the PC should advance and should be
multiples of 2 (LSb = 0).
EXAMPLE 5-2:
ORG
TABLE
5.1.6.2
MOVF
CALL
nn00h
ADDWF
RETLW
RETLW
RETLW
.
.
.
COMPUTED GOTO USING
AN OFFSET VALUE
OFFSET, W
TABLE
PCL
nnh
nnh
nnh
Table Reads
A better method of storing data in program memory
allows two bytes to be stored in each instruction
location.
Look-up table data may be stored two bytes per
program word while programming. The Table Pointer
(TBLPTR) specifies the byte address and the Table
Latch (TABLAT) contains the data that is read from the
program memory. Data is transferred from program
memory one byte at a time.
Table read operation is discussed further
Section 6.1 “Table Reads and Table Writes”.
in
DS39932C-page 75
PIC18F46J11 FAMILY
5.2
PIC18 Instruction Cycle
5.2.1
5.2.2
An “Instruction Cycle” consists of four Q cycles, Q1
through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction
cycle, while the decode and execute take another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the PC to change (e.g., GOTO), then
two cycles are required to complete the instruction
(Example 5-3).
CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by ‘4’ to
generate four non-overlapping quadrature clocks (Q1,
Q2, Q3 and Q4). Internally, the PC is incremented on
every Q1; the instruction is fetched from the program
memory and latched into the Instruction Register (IR)
during Q4. The instruction is decoded and executed
during the following Q1 through Q4. Figure 5-4
illustrates the clocks and instruction execution flow.
FIGURE 5-4:
INSTRUCTION FLOW/PIPELINING
A fetch cycle begins with the PC incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the IR in cycle Q1. This instruction is then decoded
and executed during the Q2, Q3 and Q4 cycles. Data
memory is read during Q2 (operand read) and written
during Q4 (destination write).
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
Phase
Clock
Q3
Q4
PC
PC
PC + 2
PC + 4
OSC2/CLKO
(RC mode)
Execute INST (PC – 2)
Fetch INST (PC)
EXAMPLE 5-3:
1. MOVLW 55h
TCY0
TCY1
Fetch 1
Execute 1
3. BRA SUB_1
PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
Note:
Execute INST (PC + 2)
Fetch INST (PC + 4)
INSTRUCTION PIPELINE FLOW
2. MOVWF PORTB
4. BSF
Execute INST (PC)
Fetch INST (PC + 2)
Fetch 2
TCY2
TCY3
TCY4
TCY5
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush (NOP)
Fetch SUB_1 Execute SUB_1
All instructions are single-cycle, except for any program branches. These take two cycles since the
fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then
executed.
DS39932C-page 76
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
5.2.3
INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes. Instructions are stored as 2 bytes or 4 bytes in program
memory. The Least Significant Byte (LSB) of an
instruction word is always stored in a program memory
location with an even address (LSB = 0). To maintain
alignment with instruction boundaries, the PC
increments in steps of 2 and the LSB will always read
‘0’ (see Section 5.1.3 “Program Counter”).
Figure 5-5 provides an example of how instruction
words are stored in the program memory.
FIGURE 5-5:
INSTRUCTIONS IN PROGRAM MEMORY
Program Memory
Byte Locations →
5.2.4
The CALL and GOTO instructions have the absolute
program memory address embedded into the instruction. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-5 displays how the
instruction, GOTO 0006h, is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 26.0 “Instruction Set Summary”
provides further details of the instruction set.
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
0006h
Instruction 3:
MOVFF
123h, 456h
TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instructions always has
‘1111’ as its four Most Significant bits (MSbs); the other
12 bits are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence immediately after the first
word, the data in the second word is accessed and
EXAMPLE 5-4:
LSB = 1
LSB = 0
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
Word Address
↓
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
used by the instruction sequence. If the first word is
skipped for some reason, and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC. Example 5-4 illustrates how this works.
Note:
See Section 5.5 “Program Memory and
the Extended Instruction Set” for information on two-word instructions in the
extended instruction set.
TWO-WORD INSTRUCTIONS
CASE 1:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
; is RAM location 0?
1100 0001 0010 0011
MOVFF
REG1, REG2
; No, skip this word
1111 0100 0101 0110
0010 0100 0000 0000
; Execute this word as a NOP
ADDWF
REG3
; continue code
CASE 2:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
; is RAM location 0?
1100 0001 0010 0011
MOVFF
REG1, REG2
; Yes, execute this word
ADDWF
REG3
; continue code
1111 0100 0101 0110
0010 0100 0000 0000
© 2009 Microchip Technology Inc.
; 2nd word of instruction
DS39932C-page 77
PIC18F46J11 FAMILY
5.3
Note:
Data Memory Organization
The operation of some aspects of data
memory is changed when the PIC18
extended instruction set is enabled. See
Section 5.6 “Data Memory and the
Extended Instruction Set” for more
information.
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each. The
PIC18F46J11 family implements all available banks
and provides 3.8 Kbytes of data memory available to
the user. Figure 5-6 provides the data memory
organization for the devices.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
section.
To ensure that commonly used registers (select SFRs
and select GPRs) can be accessed in a single cycle,
PIC18 devices implement an Access Bank. This is a
256-byte memory space that provides fast access to
select SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 5.3.2 “Access Bank”
provides a detailed description of the Access RAM.
5.3.1
Most instructions in the PIC18 instruction set make use
of the Bank Pointer, known as the Bank Select Register
(BSR). This SFR holds the 4 MSbs of a location’s
address; the instruction itself includes the 8 LSbs. Only
the four lower bits of the BSR are implemented
(BSR<3:0>). The upper four bits are unused; they will
always read ‘0’ and cannot be written to. The BSR can
be loaded directly by using the MOVLB instruction.
The value of the BSR indicates the bank in data
memory. The 8 bits in the instruction show the location
in the bank and can be thought of as an offset from the
bank’s lower boundary. The relationship between the
BSR’s value and the bank division in data memory is
illustrated in Figure 5-7.
Since, up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h while the BSR
is 0Fh, will end up resetting the PC.
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory map in
Figure 5-6 indicates which banks are implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.
BANK SELECT REGISTER
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is
accomplished with a RAM banking scheme. This
divides the memory space into 16 contiguous banks of
256 bytes. Depending on the instruction, each location
can be addressed directly by its full 12-bit address, or
an 8-bit low-order address and a 4-bit Bank Pointer.
DS39932C-page 78
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
FIGURE 5-6:
DATA MEMORY MAP FOR PIC18F46J11 FAMILY DEVICES
BSR3:BSR0
00h
= 0000
= 0001
= 0010
= 0011
= 0100
= 0101
= 0110
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
= 1111
When a = 0:
Data Memory Map
Access RAM
Bank 0
Bank 1
FFh
00h
GPR
GPR
1FFh
200h
FFh
00h
Bank 2
GPR
FFh
00h
Bank 3
2FFh
300h
Bank 4
When a = 1:
The BSR specifies the bank
used by the instruction.
4FFh
500h
GPR
FFh
00h
5FFh
600h
GPR
Bank 6
FFh
00h
6FFh
700h
GPR
Bank 7
FFh
00h
FFh
00h
Bank 9
7FFh
800h
FFh
00h
Bank 10
GPR
GPR
FFh
00h
GPR
FFh
00h
Bank 12
FFh
00h
FFh
00h
GPR
Access Bank
Access RAM Low
GPR
Bank 8
Bank 15
The remaining 160 bytes are
Special Function Registers
(from Bank 15).
GPR, BDT
Bank 5
Bank 14
The first 96 bytes are general
purpose RAM (from Bank 0).
3FFh
400h
FFh
00h
Bank 13
The BSR is ignored and the
Access Bank is used.
GPR
FFh
00h
Bank 11
000h
05Fh
060h
0FFh
100h
00h
5Fh
Access RAM High 60h
(SFRs)
FFh
8FFh
900h
9FFh
A00h
AFFh
B00h
BFFh
C00h
CFFh
D00h
GPR
GPR
C0h
Non-Access SFR(1)
FFh
00h
Non-Access SFR(1)
60h
DFFh
E00h
EBFh
EC0h
EFFh
F00h
F5Fh
Access SFRs
FFh
Note 1:
FFFh
Addresses EC0h through F5Fh are not part of the Access Bank. Either the BANKED or the MOVFF instruction should
be used to access these SFRs.
© 2009 Microchip Technology Inc.
DS39932C-page 79
PIC18F46J11 FAMILY
FIGURE 5-7:
USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
BSR(1)
7
0
0
0
0
0
0
0
Bank Select(2)
1
0
000h
Data Memory
Bank 0
100h
Bank 1
200h
300h
Bank 2
00h
7
FFh
00h
11
From Opcode(2)
11
11
11
11
1
0
1
1
FFh
00h
FFh
00h
Bank 3
through
Bank 13
E00h
Bank 14
F00h
FFFh
Note 1:
2:
5.3.2
Bank 15
FFh
00h
FFh
00h
FFh
The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
The MOVFF instruction embeds the entire 12-bit address in the instruction.
ACCESS BANK
While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of
data memory, it also means that the user must always
ensure that the correct bank is selected. Otherwise,
data may be read from or written to the wrong location.
This can be disastrous if a GPR is the intended target
of an operation, but an SFR is written to instead.
Verifying and/or changing the BSR for each read or
write to data memory can become very inefficient.
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of
memory (00h-5Fh) in Bank 0 and the last 160 bytes of
memory (60h-FFh) in Bank 15. The lower half is known
as the Access RAM and is composed of GPRs. The
upper half is where the device’s SFRs are mapped.
These two areas are mapped contiguously in the
Access Bank and can be addressed in a linear fashion
by an 8-bit address (Figure 5-6).
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.
DS39932C-page 80
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle without
updating the BSR first. For 8-bit addresses of 60h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detail
in Section 5.6.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.
5.3.3
GENERAL PURPOSE
REGISTER FILE
PIC18 devices may have banked memory in the GPR
area. This is data RAM, which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upward toward the bottom of
the SFR area. GPRs are not initialized by a POR and
are unchanged on all other Resets.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
5.3.4
SPECIAL FUNCTION REGISTERS
The SFRs are registers used by the CPU and peripheral modules for controlling the desired operation of the
device. These registers are implemented as static
RAM. SFRs start at the top of data memory (FFFh) and
extend downward to occupy more than the top half of
Bank 15 (F40h to FFFh). Table 5-2, Table 5-3 and
Table 5-4 provide a list of these registers.
ALU’s STATUS register is described later in this section.
Registers related to the operation of the peripheral
features are described in the chapter for that peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s
Note:
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and Interrupt registers
are described in their corresponding chapters, while the
TABLE 5-2:
Address
The SFRs located between EC0h and
F5Fh are not part of the Access Bank.
Either banked instructions (using BSR) or
the MOVFF instruction should be used to
access these locations. When programming in MPLAB® C18, the compiler will
automatically
use
the
appropriate
addressing mode.
ACCESS BANK SPECIAL FUNCTION REGISTER MAP
Name
Address
Name
(1)
INDF2
Address
Name
Address
Name
Address
Name
FFFh
TOSU
FDFh
FBFh
PSTR1CON
F9Fh
IPR1
F7Fh
SPBRGH1
FFEh
TOSH
FDEh
POSTINC2(1)
FBEh
ECCP1AS
F9Eh
PIR1
F7Eh
BAUDCON1
FFDh
TOSL
FDDh
POSTDEC2(1)
FBDh
ECCP1DEL
F9Dh
PIE1
F7Dh
SPBRGH2
FFCh
STKPTR
FDCh
PREINC2(1)
FBCh
CCPR1H
F9Ch
RCSTA2
F7Ch
BAUDCON2
FFBh
PCLATU
FDBh
PLUSW2(1)
FBBh
CCPR1L
F9Bh
OSCTUNE
F7Bh
TMR3H
FFAh
PCLATH
FDAh
FSR2H
FBAh
CCP1CON
F9Ah
T1GCON
F7Ah
TMR3L
FF9h
PCL
FD9h
FSR2L
FB9h
PSTR2CON
F99h
RTCVALH
F79h
T3CON
FF8h
TBLPTRU
FD8h
STATUS
FB8h
ECCP2AS
F98h
RTCVALL
F78h
TMR4
FF7h
TBLPTRH
FD7h
TMR0H
FB7h
ECCP2DEL
F97h
T3GCON
F77h
PR4
FF6h
TBLPTRL
FD6h
TMR0L
FB6h
CCPR2H
F96h
TRISE
F76h
T4CON
FF5h
TABLAT
FD5h
T0CON
FB5h
CCPR2L
F95h
TRISD
F75h
SSP2BUF
FF4h
PRODH
FD4h
—(5)
FB4h
CCP2CON
F94h
TRISC
F74h
SSP2ADD(3)
FF3h
PRODL
FD3h
OSCCON
FB3h
CTMUCONH
F93h
TRISB
F73h
SSP2STAT
FF2h
INTCON
FD2h
CM1CON
FB2h
CTMUCONL
F92h
TRISA
F72h
SSP2CON1
SSP2CON2
FF1h
INTCON2
FD1h
CM2CON
FB1h
CTMUICON
F91h
ALRMCFG
F71h
FF0h
INTCON3
FD0h
RCON
FB0h
SPBRG1
F90h
ALRMRPT
F70h
CMSTAT
FEFh
INDF0(1)
FCFh
TMR1H
FAFh
RCREG1
F8Fh
ALRMVALH
F6Fh
PMADDRH(2,4)
FEEh
POSTINC0(1)
FCEh
TMR1L
FAEh
TXREG1
F8Eh
ALRMVALL
FEDh
(1)
FECh
POSTDEC0
FCDh
(1)
FCCh
(1)
PREINC0
T1CON
FADh
TMR2
FACh
TXSTA1
F8Dh
RCSTA1
F8Ch
F6Eh
PMADDRL(2,4)
(2)
F6Dh
PMDIN1H(2)
(2)
F6Ch
PMDIN1L(2)
LATE
LATD
FEBh
PLUSW0
FCBh
PR2
FABh
SPBRG2
F8Bh
LATC
F6Bh
TXADDRL
FEAh
FSR0H
FCAh
T2CON
FAAh
RCREG2
F8Ah
LATB
F6Ah
TXADDRH
FE9h
FSR0L
FC9h
SSP1BUF
FA9h
TXREG2
F89h
LATA
F69h
RXADDRL
FE8h
WREG
FC8h
SSP1ADD(3)
FA8h
TXSTA2
F88h
DMACON1
F68h
RXADDRH
FE7h
INDF1(1)
FC7h
SSP1STAT
FA7h
EECON2
F87h
—(5)
F67h
DMABCL
FE6h
(1)
POSTINC1
FC6h
SSP1CON1
FA6h
EECON1
F86h
DMACON2
F66h
DMABCH
FE5h
POSTDEC1(1)
FC5h
SSP1CON2
FA5h
IPR3
F85h
HLVDCON
F65h
—(5)
F84h
(2)
F64h
—(5)
(2)
F63h
—(5)
FE4h
(1)
PREINC1
(1)
FC4h
ADRESH
FA4h
PIR3
PORTE
FE3h
PLUSW1
FC3h
ADRESL
FA3h
PIE3
F83h
FE2h
FSR1H
FC2h
ADCON0
FA2h
IPR2
F82h
PORTC
F62h
—(5)
FE1h
FSR1L
FC1h
ADCON1
FA1h
PIR2
F81h
PORTB
F61h
—(5)
FE0h
BSR
FC0h
WDTCON
FA0h
PIE2
F80h
PORTA
F60h
—(5)
Note 1:
2:
3:
4:
5:
PORTD
This is not a physical register.
This register is not available on 28-pin devices.
SSPxADD and SSPxMSK share the same address.
PMADDRH and PMDOUTH share the same address and PMADDRL and PMDOUTL share the same address.
PMADDRx is used in Master modes and PMDOUTx is used in Slave modes.
Reserved: Do not write to this location.
© 2009 Microchip Technology Inc.
DS39932C-page 81
PIC18F46J11 FAMILY
TABLE 5-3:
Address
NON-ACCESS BANK SPECIAL FUNCTION REGISTER MAP
Name
Address
Name
Address
Name
Address
Name
Address
Name
F5Fh
PMCONH
F3Fh
RTCCFG
F1Fh
—
EFFh
PPSCON
EDFh
—
F5Eh
PMCONL
F3Eh
RTCCAL
F1Eh
—
EFEh
RPINR24
EDEh
RPOR24(1)
F5Dh
PMMODEH
F3Dh
REFOCON
F1Dh
—
EFDh
RPINR23
EDDh
RPOR23(1)
F5Ch
PMMODEL
F3Ch
PADCFG1
F1Ch
—
EFCh
RPINR22
EDCh
RPOR22(1)
F5Bh
PMDOUT2H
F3Bh
—
F1Bh
—
EFBh
RPINR21
EDBh
RPOR21(1)
F5Ah
PMDOUT2L
F3Ah
—
F1Ah
—
EFAh
—
EDAh
RPOR20(1)
F59h
PMDIN2H
F39h
—
F19h
—
EF9h
—
ED9h
RPOR19(1)
F58h
PMDIN2L
F38h
—
F18h
—
EF8h
—
ED8h
RPOR18
F57h
PMEH
F37h
—
F17h
—
EF7h
RPINR17
ED7h
RPOR17
F56h
PMEL
F36h
—
F16h
—
EF6h
RPINR16
ED6h
RPOR16
F55h
PMSTATH
F35h
—
F15h
—
EF5h
—
ED5h
RPOR15
F54h
PMSTATL
F34h
—
F14h
—
EF4h
—
ED4h
RPOR14
F53h
CVRCON
F33h
—
F13h
—
EF3h
—
ED3h
RPOR13
F52h
TCLKCON
F32h
—
F12h
—
EF2h
—
ED2h
RPOR12
F51h
—
F31h
—
F11h
—
EF1h
—
ED1h
RPOR11
F50h
—
F30h
—
F10h
—
EF0h
—
ED0h
RPOR10
F4Fh
DSGPR1(2)
F2Fh
—
F0Fh
—
EEFh
—
ECFh
RPOR9
F4Eh
DSGPR0(2)
F2Eh
—
F0Eh
—
EEEh
RPINR8
ECEh
RPOR8
F4Dh
DSCONH(2)
F2Dh
—
F0Dh
—
EEDh
RPINR7
ECDh
RPOR7
F4Ch
DSCONL(2)
F2Ch
—
F0Ch
—
EECh
RPINR6
ECCh
RPOR6
F4Bh
DSWAKEH(2)
F2Bh
—
F0Bh
—
EEBh
—
ECBh
RPOR5
F4Ah
DSWAKEL(2)
F2Ah
—
F0Ah
—
EEAh
RPINR4
ECAh
RPOR4
F49h
ANCON1
F29h
—
F09h
—
EE9h
RPINR3
EC9h
RPOR3
F48h
ANCON0
F28h
—
F08h
—
EE8h
RPINR2
EC8h
RPOR2
F47h
—
F27h
—
F07h
—
EE7h
RPINR1
EC7h
RPOR1
F46h
—
F26h
—
F06h
—
EE6h
RPINR0
EC6h
RPOR0
F45h
—
F25h
—
F05h
—
EE5h
—
EC5h
—
F44h
—
F24h
—
F04h
—
EE4h
—
EC4h
—
F43h
—
F23h
—
F03h
—
EE3h
—
EC3h
—
F42h
ODCON1
F22h
—
F02h
—
EE2h
—
EC2h
—
F41h
ODCON2
F21h
—
F01h
—
EE1h
—
EC1h
—
F40h
ODCON3
F20h
—
F00h
—
EE0h
—
EC0h
—
Note 1:
2:
This register is not available on 28-pin devices.
Deep Sleep registers are not available on LF devices.
DS39932C-page 82
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
5.3.4.1
Context Defined SFRs
• PMADDRH/L and PMDOUT2H/L: In this case,
these named buffer pairs are actually the same
physical registers. The Parallel Master Port (PMP)
module’s operating mode determines what function the registers take on. See Section 10.1.2
“Data Registers” for additional details.
There are several registers that share the same
address in the SFR space. The register’s definition and
usage depends on the operating mode of its associated
peripheral. These registers are:
• SSPxADD and SSPxMSK: These are two
separate hardware registers, accessed through a
single SFR address. The operating mode of the
MSSP modules determines which register is
being accessed. See Section 18.5.3.4 “7-Bit
Address Masking Mode” for additional details.
TABLE 5-4:
File Name
TOSU
REGISTER FILE SUMMARY (PIC18F46J11 FAMILY)
Bit 7
Bit 6
Bit 5
—
—
—
TOSH
Top-of-Stack High Byte (TOS<15:8>)
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
STKPTR
STKFUL
STKUNF
—
PCLATU
—
—
bit 21(1)
PCLATH
Holding Register for PC<15:8>
PCL
PC Low Byte (PC<7:0>)
TBLPTRU
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Top-of-Stack Upper Byte (TOS<20:16>)
Value on
POR, BOR
Details
on
Page:
---0 0000 63, 75
0000 0000 63, 73
0000 0000 63, 73
SP4
SP3
SP2
SP1
SP0
Holding Register for PC<20:16>
00-0 0000 63, 74
---0 0000 63, 73
0000 0000 63, 73
0000 0000 63, 73
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000 63, 106
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000 63, 106
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000 63, 106
TABLAT
Program Memory Table Latch
0000 0000 63, 106
PRODH
Product Register High Byte
xxxx xxxx 63, 63
PRODL
Product Register Low Byte
xxxx xxxx 63, 107
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 63, 111
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT3IP
RBIP
1111 1111 63, 112
INT2IF
INT1IF
1100 0000 63, 113
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
POSTINC0
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
63, 92
POSTDEC0
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
63, 92
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
63, 92
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A
63, 92
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte
63, 91
---- xxxx 63, 91
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx 63, 91
xxxx xxxx 63, 75
WREG
Working Register
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
POSTINC1
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
63, 92
POSTDEC1
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
63, 92
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
63, 92
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
63, 92
Legend:
Note 1:
2:
3:
4:
5:
6:
63, 91
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming (SP) modes.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 18.5.3.2 “Address
Masking Modes” for details.
These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 44-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have
different functions determined by the module’s operating mode. See Section 10.1.2 “Data Registers” for more information.
© 2009 Microchip Technology Inc.
DS39932C-page 83
PIC18F46J11 FAMILY
TABLE 5-4:
File Name
REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
—
—
—
—
FSR1H
FSR1L
Bit 3
Bit 2
Bit 1
Bit 0
Indirect Data Memory Address Pointer 1 High Byte
Indirect Data Memory Address Pointer 1 Low Byte
BSR
—
—
—
—
Value on
POR, BOR
Details
on
Page:
---- xxxx 63, 91
xxxx xxxx 63, 91
Bank Select Register
---- 0000 63, 78
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
63, 91
POSTINC2
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
64, 92
POSTDEC2
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
64, 92
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
64, 92
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A
64, 92
FSR2H
—
FSR2L
—
—
—
Indirect Data Memory Address Pointer 2 High Byte
Indirect Data Memory Address Pointer 2 Low Byte
STATUS
—
—
—
N
---- xxxx 64, 91
xxxx xxxx 64, 91
OV
Z
DC
C
---x xxxx 64, 89
TMR0H
Timer0 Register High Byte
0000 0000
64
TMR0L
Timer0 Register Low Byte
xxxx xxxx
64
T0CON
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
OSCCON
IDLEN
IRCF2
IRCF1
IRCF0
OSTS(2)
—
CM1CON
CON
COE
CPOL
EVPOL1
EVPOL0
CREF
CM2CON
CON
COE
CPOL
EVPOL1
EVPOL0
CREF
RCON
IPEN
—
CM
RI
TO
PD
T0PS1
T0PS0
1111 1111 64, 191
SCS1
SCS0
0110 q-00 64, 38
CCH1
CCH0
0001 1111 64, 356
CCH1
CCH0
0001 1111 64, 356
POR
BOR
0-11 1100 64, 123
TMR1H
Timer1 Register High Byte
xxxx xxxx
64
TMR1L
Timer1 Register Low Byte
xxxx xxxx
64
T1CON
TMR1CS1
TMR1CS0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
RD16
TMR1ON
0000 0000 64, 195
TMR2
Timer2 Register
0000 0000
64
PR2
Timer2 Period Register
1111 1111
64
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1
T2OUTPS0
TMR2ON
T2CKPS1
T2CKPS0 -000 0000 64, 207
SSP1BUF
MSSP1 Receive Buffer/Transmit Register
xxxx xxxx
64
SSP1ADD
MSSP1 Address Register (I2C™ Slave mode), MSSP1 Baud Rate Reload Register (I2C Master mode)
0000 0000
64
SSP1MSK(4)
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
1111 1111 64, 289
SSP1STAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 64, 286
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000 64, 287
ACKDT
ACKEN
0000 0000 64, 288
SSP1CON2
GCEN
ACKSTAT
GCEN
ACKSTAT
ADMSK5(4) ADMSK4(4)
RCEN
PEN
RSEN
SEN
ADMSK3(4)
ADMSK2(4)
ADMSK1(4)
SEN
ADRESH
A/D Result Register High Byte
xxxx xxxx
64
ADRESL
A/D Result Register Low Byte
xxxx xxxx
64
ADCON0
VCFG1
VCFG0
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
0000 0000 64, 345
ADCON1
ADFM
ADCAL
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
0000 0000 64, 346
WDTCON
REGSLP
LVDSTAT
ULPLVL
—
DS
ULPEN
ULPSINK
SWDTEN
1xx- 0000 64, 400
CMPL1
CMPL0
—
STRSYNC
STRA
00-0 0001 64, 261
PSTR1CON
ECCP1AS
ECCP1DEL
ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0
P1RSEN
P1DC6
P1DC5
P1DC4
STRD
STRC
STRB
PSS1AC1
PSS1AC0
PSS1BD1
P1DC3
P1DC2
P1DC1
PSS1BD0 0000 0000
P1DC0
64
0000 0000
65
CCPR1H
Capture/Compare/PWM Register 1 HIgh Byte
xxxx xxxx
65
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx
65
0000 0000
65
CCP1CON
Legend:
Note 1:
2:
3:
4:
5:
6:
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming (SP) modes.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 18.5.3.2 “Address
Masking Modes” for details.
These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 44-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have
different functions determined by the module’s operating mode. See Section 10.1.2 “Data Registers” for more information.
DS39932C-page 84
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 5-4:
File Name
PSTR2CON
ECCP2AS
ECCP2DEL
REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
CMPL1
CMPL0
—
STRSYNC
ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0
P2RSEN
P2DC6
P2DC5
P2DC4
Bit 3
Bit 2
Bit 1
STRD
STRC
STRB
PSS2AC1
PSS2AC0
PSS2BD1
P2DC3
P2DC2
P2DC1
Details
on
Page:
Bit 0
Value on
POR, BOR
STRA
00-0 0001 65, 261
PSS2BD0 0000 0000
P2DC0
65
0000 0000
65
CCPR2H
Capture/Compare/PWM Register 2 High Byte
xxxx xxxx
65
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx
65
65
CCP2CON
P2M1
P2M0
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
0000 0000
CTMUCONH
CTMUEN
—
CTMUSIDL
TGEN
EDGEN
EDGSEQEN
IDISSEN
—
0-00 000-
65
CTMUCONL
EDG2POL
EDG1POL
EDG1SEL1
EDG1SEL0
EDG2STAT
EDG1STAT 0000 0000
65
ITRIM2
ITRIM1
ITRIM0
IRNG1
CTMUICON
ITRIM5
EDG2SEL1 EDG2SEL0
0000 0000
65
SPBRG1
EUSART1 Baud Rate Generator Register Low Byte
ITRIM4
0000 0000
65
RCREG1
EUSART1 Receive Register
0000 0000
65
TXREG1
EUSART1 Transmit Register
xxxx xxxx
65
TXSTA1
CSRC
TX9
RCSTA1
SPEN
RX9
ITRIM3
SPBRG2
IRNG0
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010 65, 322
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x 65, 323
0000 0000
65
RCREG2
EUSART2 Receive Register
0000 0000
65
TXREG2
EUSART2 Transmit Register
0000 0000
65
TXSTA2
EECON2
EECON1
EUSART2 Baud Rate Generator Register Low Byte
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
Program Memory Control Register 2 (not a physical register)
0000 0010 65, 322
---- ----
65
—
—
WPROG
FREE
WRERR
WREN
WR
—
--00 x00- 65, 99
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CTMUIP
TMR3GIP
RTCCIP
1111 1111 65, 122
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CTMUIF
TMR3GIF
RTCCIF
0000 0000 65, 116
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CTMUIE
TMR3GIE
RTCCIE
0000 0000 65, 119
IPR2
OSCFIP
CM2IP
CM1IP
—
BCL1IP
LVDIP
TMR3IP
CCP2IP
111- 1111 65, 121
PIR2
OSCFIF
CM2IF
CM1IF
—
BCL1IF
LVDIF
TMR3IF
CCP2IF
000- 0000 65, 115
PIE2
OSCFIE
CM2IE
CM1IE
—
BCL1IE
LVDIE
TMR3IE
CCP2IE
000- 0000 65, 118
IPR1
PMPIP(5)
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
1111 1111 65, 120
PIR1
PMPIF(5)
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
0000 0000 65, 114
PIE1
PMPIE(5)
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
0000 0000 65, 117
RCSTA2
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x 66, 323
OSCTUNE
INTSRC
PLLEN
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
0000 0000 66, 36
T1GCON
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
T1DONE
T1GVAL
T1GSS1
T1GSS0
0000 0x00 66, 196
RTCVALH
RTCC Value Register Window High Byte, Based on RTCPTR<1:0>
0xxx xxxx
66
RTCVALL
RTCC Value Register Window Low Byte, Based on RTCPTR<1:0>
0xxx xxxx
66
T3GCON
TMR3GE
T3GPOL
T3GTM
T3GSPM
T3GGO/
T3DONE
T3GVAL
T3GSS1
T3GSS0
0000 0x00 66, 210
TRISE
—
—
—
—
—
TRISE2
TRISE1
TRISE0
---- -111
66
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
1111 1111
66
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
66
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
66
TRISA
TRISA7
TRISA6
TRISA5
—
TRISA3
TRISA2
TRISA1
TRISA0
111- 1111
66
ALRMEN
CHIME
AMASK3
AMASK2
AMASK1
AMASK0
ALRMCFG
Legend:
Note 1:
2:
3:
4:
5:
6:
ALRMPTR1 ALRMPTR0 0000 0000 66, 225
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming (SP) modes.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 18.5.3.2 “Address
Masking Modes” for details.
These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 44-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have
different functions determined by the module’s operating mode. See Section 10.1.2 “Data Registers” for more information.
© 2009 Microchip Technology Inc.
DS39932C-page 85
PIC18F46J11 FAMILY
TABLE 5-4:
File Name
ALRMRPT
REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ARPT7
ARPT6
ARPT5
ARPT4
ARPT3
ARPT2
ARPT1
ARPT0
Value on
POR, BOR
Details
on
Page:
0000 0000 66, 226
ALRMVALH
Alarm Value Register Window High Byte, Based on ALRMPTR<1:0>
xxxx xxxx
ALRMVALL
Alarm Value Register Window Low Byte, Based on ALRMPTR<1:0>
xxxx xxxx
66
66
LATE0
---- -xxx
66
LATE
—
—
—
—
—
LATD
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
xxxx xxxx
66
LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
xxxx xxxx
66
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
xxxx xxxx
66
LATA
LATA7
LATA6
LATA5
—
LATA3
LATA2
LATA1
LATA0
xxx- xxxx
66
SSCON1
SSCON0
TXINC
RXINC
DUPLEX1
DUPLEX0
DLYINTEN
DMAEN
DMACON1
DMATXBUF
LATE2
LATE1
SPI DMA Transmit Buffer
0000 0000 66, 278
xxxx xxxx
66
DMACON2
DLYCYC3
DLYCYC2
DLYCYC1
DLYCYC0
INTLVL3
INTLVL2
INTLVL1
INTLVL0
0000 0000 66, 279
HLVDCON
VDIRMAG
BGVST
IRVST
HLVDEN
HLVDL3
HLVDL2
HLVDL1
HLVDL0
0000 0000
66
PORTE
RDPU
REPU
—
—
—
RE2
RE1
RE0
00-- -xxx
66
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
66
PORTC
RC7
RC6
RC5
RC4
RC4
RC2
RC1
RC0
xxxx xxxx
66
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
66
PORTA
RA7
RA6
RA5
—
RA3
RA2
RA1
RA0
xxx- xxxx
66
0000 0000
66
BRG16
—
WUE
ABDEN
BRG16
—
WUE
ABDEN
SPBRGH1
EUSART1 Baud Rate Generator Register High Byte
BAUDCON1
ABDOVF
SPBRGH2
RCIDL
RXDTP
TXCKP
EUSART2 Baud Rate Generator Register High Byte
BAUDCON2
ABDOVF
RCIDL
RXDTP
TXCKP
0100 0-00 66, 324
0000 0000
66
0100 0-00 66, 324
TMR3H
Timer3 Register High Byte
xxxx xxxx
67
TMR3L
Timer3 Register Low Byte
xxxx xxxx
67
T3CON
TMR3CS1
TMR3CS0
T3CKPS1
T3CKPS0
—
T3SYNC
RD16
TMR3ON
0000 -000 67, 209
TMR4
Timer4 Register
0000 0000
67
PR4
Timer4 Period Register
1111 1111
67
T4CON
—
T4OUTPS3 T4OUTPS2 T4OUTPS1
T4OUTPS0
TMR4ON
T4CKPS1
T4CKPS0 -000 0000 67, 219
SSP2BUF
MSSP2 Receive Buffer/Transmit Register
xxxx xxxx
SSP2ADD/
MSSP2 Address Register (I2C™ Slave mode), MSSP2 Baud Rate Reload Register (I2C Master mode)
0000 0000 67, 289
67
SSP2MSK(4)
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
0000 0000 67, 289
SSP2STAT
SMP
CKE
D/A
P
S
R/W
UA
BF
1111 1111 67, 267
SSP2CON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000 67, 287
SSP2CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000 67, 288
GCEN
ACKSTAT
ADMSK3(4)
ADMSK2(4)
ADMSK1(4)
SEN
CMSTAT
—
—
—
—
COUT2
COUT1
PMADDRH/
—
CS1
ADMSK5(4) ADMSK4(4)
—
—
Parallel Master Port Address High Byte
---- --11 67, 357
-000 0000 67, 173
PMDOUT1H(5)
Parallel Port Out Data High Byte (Buffer 1)
PMADDRL/
Parallel Master Port Address Low Byte
0000 0000 67, 173
PMDOUT1L(5)
Parallel Port Out Data Low Byte (Buffer 0)
0000 0000 67, 173
PMDIN1H(5)
Parallel Port In Data High Byte (Buffer 1)
0000 0000
67
PMDIN1L(5)
Parallel Port In Data Low Byte (Buffer 0)
0000 0000
67
TXADDRL
SPI DMA Transit Data Pointer Low Byte
xxxx xxxx
67
Legend:
Note 1:
2:
3:
4:
5:
6:
0000 0000 67, 173
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming (SP) modes.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 18.5.3.2 “Address
Masking Modes” for details.
These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 44-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have
different functions determined by the module’s operating mode. See Section 10.1.2 “Data Registers” for more information.
DS39932C-page 86
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 5-4:
File Name
TXADDRH
RXADDRL
REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
—
—
—
—
Bit 3
Bit 2
Bit 1
Bit 0
SPI DMA Transit Data Pointer High Byte
SPI DMA Receive Data Pointer Low Byte
RXADDRH
—
DMABCL
—
—
—
SPI DMA Receive Data Pointer High Byte
—
—
—
—
—
SPI DMA Byte Count Low Byte
DMABCH
—
SPI DMA Receive Data
Pointer High Byte
Value on
POR, BOR
Details
on
Page:
---- xxxx
67
xxxx xxxx
67
---- xxxx
67
xxxx xxxx
67
---- --xx
67
PMCONH(5)
PMPEN
—
PSIDL
ADRMUX1
ADRMUX0
PTBEEN
PTWREN
PTRDEN
0-00 0000 67, 166
PMCONL(5)
CSF1
CSF0
ALP
—
CS1P
BEP
WRSP
RDSP
000- 0000 67, 167
0000 0000 67, 168
PMMODEH(5)
BUSY
IRQM1
IRQM0
INCM1
INCM0
MODE16
MODE1
MODE0
PMMODEL(5)
WAITB1
WAITB0
WAITM3
WAITM2
WAITM1
WAITM0
WAITE1
WAITE0
0000 0000 67, 169
PMDOUT2H(5)
Parallel Port Out Data High Byte (Buffer 3)
0000 0000
67
PMDOUT2L(5)
Parallel Port Out Data Low Byte (Buffer 2)
0000 0000
67
PMDIN2H(5)
Parallel Port In Data High Byte (Buffer 3)
0000 0000
67
PMDIN2L(5)
Parallel Port In Data Low Byte (Buffer 2)
0000 0000
67
PMEH(5)
PTEN15
PTEN14
PTEN13
PTEN12
PTEN11
PTEN10
PTEN9
PTEN8
PMEL(5)
PTEN7
PTEN6
PTEN5
PTEN4
PTEN3
PTEN2
PTEN1
PTEN0
0000 0000 67, 170
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
00-- 0000 67, 171
10-- 1111 67, 171
PMSTATH(5)
PMSTATL(5)
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
CVRCON(5)
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
TCLKCON
—
—
—
T1RUN
—
—
T3CCP2
T3CCP1
0000 0000 67, 170
0000 0000 67, 364
---0 --00
197
DSGPR1
Deep Sleep Persistent General Purpose Register (contents retained even in Deep Sleep)
xxxx xxxx
53
DSGPR0
Deep Sleep Persistent General Purpose Register (contents retained even in Deep Sleep)
xxxx xxxx
53
52
DSCONH
DSEN
—
—
—
—
(Reserved)
DSULPEN
RTCWDIS 0--- -000
DSCONL
—
—
—
—
—
ULPWDIS
DSBOR
RELEASE ---- -000
DSWAKEH
—
—
—
—
—
—
—
DSINT0
---- ---0
54
DSWAKEL
DSFLT
—
DSULP
DSWDT
DSRTC
DSMCLR
—
DSPOR
0-00 00-1
54
ANCON1
VBGEN
r
—
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
00-0 0000 67, 347
ANCON0
PCFG7(5)
PCFG6(5)
PCFG5(5)
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
0000 0000 67, 347
ODCON1
—
—
—
—
—
—
ECCP20D
ODCON2
—
—
—
—
—
—
U2OD
U1OD
---- --00 67, 127
ODCON3
—
—
—
—
—
—
SPI2OD
SPI1OD
---- --00 67, 128
RTCCFG
RTCEN
—
RTCWREN
RTCSYNC
HALFSEC
RTCOE
RTCPTR1
RTCCAL
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
REFOCON
ROON
—
ROSSLP
ROSEL
RODIV3
RODIV2
RODIV1
RODIV0
0-00 0000 67, 39
PADCFG1
—
—
—
—
—
PMPTTL
---- -000 67, 128
—
IOLOCK
---- ---0
52
ECCP10D ---- --00 67, 127
RTCPTR0 0-00 0000 67, 223
RTSECSEL1 RTSECSEL0
0000 0000 67, 224
PPSCON
—
—
—
RPINR24
—
—
—
RPINR23
—
—
—
Input Function SS2 to Input Pin Mapping Bits
---1 1111 68, 154
RPINR22
—
—
—
Input Function SCK2 to Input Pin Mapping Bits
---1 1111 68, 154
RPINR21
—
—
—
Input Function SDI2 to Input Pin Mapping Bits
---1 1111 68, 153
RPINR17
—
—
—
Input Function CK2 to Input Pin Mapping Bits
---1 1111 68, 153
RPINR16
—
—
—
Input Function RX2DT2 to Input Pin Mapping Bits
RPINR13
—
—
—
Input Function T3G to Input Pin Mapping Bits
Legend:
Note 1:
2:
3:
4:
5:
6:
—
—
—
Input Function FLT0 to Input Pin Mapping Bits
149
---1 1111 68, 154
---1 1111
153
---1 1111 68, 152
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming (SP) modes.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 18.5.3.2 “Address
Masking Modes” for details.
These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 44-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have
different functions determined by the module’s operating mode. See Section 10.1.2 “Data Registers” for more information.
© 2009 Microchip Technology Inc.
DS39932C-page 87
PIC18F46J11 FAMILY
TABLE 5-4:
File Name
REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) (CONTINUED)
Bit 5
RPINR12
—
—
—
Input Function T1G to Input Pin Mapping Bits
---1 1111 69, 152
RPINR8
—
—
—
Input Function IC2 to Input Pin Mapping Bits
---1 1111 68, 152
RPINR7
—
—
—
Input Function IC1 to Input Pin Mapping Bits
---1 1111 68, 151
RPINR6
—
—
—
Input Function T3CKI to Input Pin Mapping Bits
---1 1111 68, 151
RPINR4
—
—
—
Input Function T0CKI to Input Pin Mapping Bits
---1 1111 68, 151
RPINR3
—
—
—
Input Function INT3 to Input Pin Mapping Bits
---1 1111 68, 150
RPINR2
—
—
—
Input Function INT2 to Input Pin Mapping Bits
---1 1111
RPINR1
—
—
—
Input Function INT1 to Input Pin Mapping Bits
---1 1111 68, 150
RPOR24(5)
—
—
—
Remappable Pin RP24 Output Signal Select Bits
---0 0000 68, 163
RPOR23(5)
—
—
—
Remappable Pin RP23 Output Signal Select Bits
---0 0000 68, 163
RPOR22(5)
—
—
—
Remappable Pin RP22 Output Signal Select Bits
---0 0000 68, 162
RPOR21(5)
—
—
—
Remappable Pin RP21 Output Signal Select Bits
---0 0000 68, 162
RPOR20(5)
—
—
—
Remappable Pin RP20 Output Signal Select Bits
---0 0000 68, 162
RPOR19(5)
—
—
—
Remappable Pin RP19 Output Signal Select Bits
---0 0000 68, 161
RPOR18
—
—
—
Remappable Pin RP18 Output Signal Select Bits
---0 0000 68, 161
RPOR17
—
—
—
Remappable Pin RP17 Output Signal Select Bits
---0 0000 69, 161
RPOR16
—
—
—
Remappable Pin RP13 Output Signal Select Bits
---0 0000 69, 160
RPOR15
—
—
—
Remappable Pin RP13 Output Signal Select Bits
---0 0000 69, 160
RPOR14
—
—
—
Remappable Pin RP13 Output Signal Select Bits
---0 0000 69, 160
RPOR13
—
—
—
Remappable Pin RP13 Output Signal Select Bits
---0 0000 69, 159
RPOR12
—
—
—
Remappable Pin RP12 Output Signal Select Bits
---0 0000 69, 159
RPOR11
—
—
—
Remappable Pin RP11 Output Signal Select Bits
---0 0000 69, 159
RPOR10
—
—
—
Remappable Pin RP10 Output Signal Select Bits
---0 0000 69, 158
RPOR9
—
—
—
Remappable Pin RP9 Output Signal Select Bits
---0 0000 69, 158
RPOR8
—
—
—
Remappable Pin RP8 Output Signal Select Bits
---0 0000 69, 157
RPOR7
—
—
—
Remappable Pin RP7 Output Signal Select Bits
---0 0000 69, 157
RPOR6
—
—
—
Remappable Pin RP6 Output Signal Select Bits
---0 0000 69, 157
RPOR5
—
—
—
Remappable Pin RP5 Output Signal Select Bits
---0 0000 69, 156
RPOR4
—
—
—
Remappable Pin RP4 Output Signal Select Bits
---0 0000 69, 156
RPOR3
—
—
—
Remappable Pin RP3 Output Signal Select Bits
---0 0000 69, 156
RPOR2
—
—
—
Remappable Pin RP2 Output Signal Select Bits
---0 0000 69, 155
RPOR1
—
—
—
Remappable Pin RP1 Output Signal Select Bits
---0 0000 69, 155
RPOR0
—
—
—
Remappable Pin RP0 Output Signal Select Bits
---0 0000 69, 155
5:
6:
Bit 3
Bit 2
Bit 1
Bit 0
Details
on
Page:
Bit 6
Legend:
Note 1:
2:
3:
4:
Bit 4
Value on
POR, BOR
Bit 7
68
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming (SP) modes.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 18.5.3.2 “Address
Masking Modes” for details.
These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 44-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have
different functions determined by the module’s operating mode. See Section 10.1.2 “Data Registers” for more information.
DS39932C-page 88
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
5.3.5
STATUS REGISTER
The STATUS register in Register 5-2, contains the
arithmetic status of the ALU. The STATUS register can
be the operand for any instruction, as with any other
register. If the STATUS register is the destination for an
instruction that affects the Z, DC, C, OV or N bits, then
the write to these five bits is disabled.
These bits are set or cleared according to the device
logic. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended. For example, CLRF STATUS will set the Z bit
but leave the other bits unchanged. The STATUS
REGISTER 5-2:
U-0
For other instructions not affecting any Status bits, see
the instruction set summary in Table 26-2 and
Table 26-3.
Note:
The C and DC bits operate as a borrow
and digit borrow bits respectively, in
subtraction.
STATUS REGISTER (ACCESS FD8h)
U-0
—
register then reads back as ‘000u u1uu’. It is recommended, therefore, that only BCF, BSF, SWAPF, MOVFF
and MOVWF instructions are used to alter the STATUS
register because these instructions do not affect the Z,
C, DC, OV or N bits in the STATUS register.
U-0
—
—
R/W-x
N
R/W-x
OV
R/W-x
R/W-x
R/W-x
Z
DC(1)
C(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative
(ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude,
which causes the sign bit (bit 7) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit(1)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/borrow bit(2)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the MSb of the result occurred
0 = No carry-out from the MSb of the result occurred
Note 1:
2:
For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.
For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the
source register.
© 2009 Microchip Technology Inc.
DS39932C-page 89
PIC18F46J11 FAMILY
5.4
Data Addressing Modes
Note:
The execution of some instructions in the
core PIC18 instruction set is changed when
the PIC18 extended instruction set is
enabled. See Section 5.6 “Data Memory
and the Extended Instruction Set” for
more information.
While the program memory can be addressed in only
one way, through the PC, information in the data
memory space can be addressed in several ways. For
most instructions, the addressing mode is fixed. Other
instructions may use up to three modes, depending on
which operands are used and whether or not the
extended instruction set is enabled.
The addressing modes are:
•
•
•
•
Inherent
Literal
Direct
Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is
discussed in more detail in Section 5.6.1 “Indexed
Addressing with Literal Offset”.
5.4.1
INHERENT AND LITERAL
ADDRESSING
Many PIC18 control instructions do not need any
argument at all; they either perform an operation that
globally affects the device, or they operate implicitly on
one register. This addressing mode is known as
Inherent Addressing. Examples include SLEEP, RESET
and DAW.
Other instructions work in a similar way, but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode, because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
5.4.2
DIRECT ADDRESSING
Direct Addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.
In the core PIC18 instruction set, bit-oriented and
byte-oriented instructions use some version of Direct
Addressing by default. All of these instructions include
some 8-bit Literal Address as their LSB. This address
specifies either a register address in one of the banks
of data RAM (Section 5.3.3 “General Purpose
DS39932C-page 90
Register File”), or a location in the Access Bank
(Section 5.3.2 “Access Bank”) as the data source for
the instruction.
The Access RAM bit, ‘a’, determines how the address
is interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 5.3.1 “Bank Select Register”) are used with
the address to determine the complete 12-bit address
of the register. When ‘a’ is ‘0’, the address is interpreted
as being a register in the Access Bank. Addressing that
uses the Access RAM is sometimes also known as
Direct Forced Addressing mode.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
The destination of the operation’s results is determined
by the destination bit, ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its
original contents. When ‘d’ is ‘0’, the results are stored
in the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction; their
destination is either the target register being operated
on or the W register.
5.4.3
INDIRECT ADDRESSING
Indirect Addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations to be read or written
to. Since the FSRs are themselves located in RAM as
SFRs, they can also be directly manipulated under
program control. This makes FSRs very useful in
implementing data structures such as tables and arrays
in data memory.
The registers for Indirect Addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code using
loops, such as the example of clearing an entire RAM
bank in Example 5-5. It also enables users to perform
Indexed Addressing and other Stack Pointer
operations for program memory in data memory.
EXAMPLE 5-5:
NEXT
LFSR
CLRF
BTFSS
BRA
CONTINUE
HOW TO CLEAR RAM
(BANK 1) USING INDIRECT
ADDRESSING
FSR0, 100h ;
POSTINC0
; Clear INDF
; register then
; inc pointer
FSR0H, 1
; All done with
; Bank1?
NEXT
; NO, clear next
; YES, continue
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
5.4.3.1
FSR Registers and the INDF
Operand (INDF)
SFR space but are not physically implemented. Reading or writing to a particular INDF register actually
accesses its corresponding FSR register pair. A read
from INDF1, for example, reads the data at the address
indicated by FSR1H:FSR1L. Instructions that use the
INDF registers as operands actually use the contents
of their corresponding FSR as a pointer to the instruction’s target. The INDF operand is just a convenient
way of using the pointer.
At the core of Indirect Addressing are three sets of
registers: FSR0, FSR1 and FSR2. Each represents a
pair of 8-bit registers, FSRnH and FSRnL. The four
upper bits of the FSRnH register are not used, so each
FSR pair holds a 12-bit value. This represents a value
that can address the entire range of the data memory
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations.
Because Indirect Addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
Indirect Addressing is accomplished with a set of INDF
operands, INDF0 through INDF2. These can be presumed to be “virtual” registers: they are mapped in the
FIGURE 5-8:
INDIRECT ADDRESSING
000h
Using an instruction with one of the
Indirect Addressing registers as the
operand....
Bank 0
ADDWF, INDF1, 1
100h
Bank 1
200h
...uses the 12-bit address stored in
the FSR pair associated with that
register....
300h
FSR1H:FSR1L
7
0
x x x x 1 1 1 1
7
0
Bank 2
Bank 3
through
Bank 13
1 1 0 0 1 1 0 0
...to determine the data memory
location to be used in that operation.
In this case, the FSR1 pair contains
FCCh. This means the contents of
location FCCh will be added to that
of the W register and stored back in
FCCh.
E00h
Bank 14
F00h
FFFh
Bank 15
Data Memory
© 2009 Microchip Technology Inc.
DS39932C-page 91
PIC18F46J11 FAMILY
5.4.3.2
FSR Registers and POSTINC,
POSTDEC, PREINC and PLUSW
In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers that cannot be indirectly
read or written to. Accessing these registers actually
accesses the associated FSR register pair, but also
performs a specific action on its stored value. They are:
• POSTDEC: accesses the FSR value, then
automatically decrements it by ‘1’ thereafter
• POSTINC: accesses the FSR value, then
automatically increments it by ‘1’ thereafter
• PREINC: increments the FSR value by ‘1’, then
uses it in the operation
• PLUSW: adds the signed value of the W register
(range of 127 to 128) to that of the FSR and uses
the new value in the operation
In this context, accessing an INDF register uses the
value in the FSR registers without changing them.
Similarly, accessing a PLUSW register gives the FSR
value offset by the value in the W register; neither value
is actually changed in the operation. Accessing the
other virtual registers changes the value of the FSR
registers.
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over
to the FSRnH register. On the other hand, results of
these operations do not change the value of any flags
in the STATUS register (e.g., Z, N, OV, etc.).
The PLUSW register can be used to implement a form
of Indexed Addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
5.4.3.3
Operations by FSRs on FSRs
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses Indirect Addressing.
Similarly, operations by Indirect Addressing are generally permitted on all other SFRs. Users should exercise
appropriate caution that they do not inadvertently
change settings that might affect the operation of the
device.
5.5
Program Memory and the
Extended Instruction Set
The operation of program memory is unaffected by the
use of the extended instruction set.
Enabling the extended instruction set adds five
additional two-word commands to the existing PIC18
instruction set: ADDFSR, CALLW, MOVSF, MOVSS and
SUBFSR. These instructions are executed as described
in Section 5.2.4 “Two-Word Instructions”.
5.6
Data Memory and the Extended
Instruction Set
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifically,
the use of the Access Bank for many of the core PIC18
instructions is different. This is due to the introduction of
a new addressing mode for the data memory space.
This mode also alters the behavior of Indirect
Addressing using FSR2 and its associated operands.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect Addressing
with FSR0 and FSR1 also remains unchanged.
Indirect Addressing operations that target other FSRs
or virtual registers represent special cases. For
example, using an FSR to point to one of the virtual
registers will not result in successful operations. As a
specific case, assume that FSR0H:FSR0L contains
FE7h, the address of INDF1. Attempts to read the
value of the INDF1, using INDF0 as an operand, will
return 00h. Attempts to write to INDF1, using INDF0 as
the operand, will result in a NOP.
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to
FSR2H:FSR2L.
DS39932C-page 92
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
5.6.1
INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes
the behavior of Indirect Addressing using the FSR2
register pair and its associated file operands. Under
proper conditions, instructions that use the Access
Bank, that is, most bit and byte-oriented instructions,
can invoke a form of Indexed Addressing using an
offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal
Offset, or Indexed Literal Offset mode.
When using the extended instruction set, this
addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0);
and
• The file address argument is less than or equal to
5Fh.
Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in Direct Addressing) or as
an 8-bit address in the Access Bank. Instead, the value
is interpreted as an offset value to an Address Pointer
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.
© 2009 Microchip Technology Inc.
5.6.2
INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use Direct
Addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all byte
and bit-oriented instructions, or almost one-half of the
standard PIC18 instruction set. Instructions that only
use Inherent or Literal Addressing modes are
unaffected.
Additionally, byte and bit-oriented instructions are not
affected if they use the Access Bank (Access RAM bit is
‘1’) or include a file address of 60h or above. Instructions
meeting these criteria will continue to execute as before.
A comparison of the different possible addressing
modes when the extended instruction set is enabled is
provided in Figure 5-9.
Those who desire to use byte or bit-oriented instructions in the Indexed Literal Offset mode should note the
changes to assembler syntax for this mode. This is
described in more detail in Section 26.2.1 “Extended
Instruction Syntax”.
DS39932C-page 93
PIC18F46J11 FAMILY
FIGURE 5-9:
COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED
INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When a = 0 and f ≥ 60h:
The instruction executes in
Direct Forced mode. ‘f’ is
interpreted as a location in the
Access RAM between 060h
and FFFh. This is the same as
locations F60h to FFFh
(Bank 15) of data memory.
Locations below 060h are not
available in this addressing
mode.
000h
060h
Bank 0
100h
00h
Bank 1
through
Bank 14
F00h
60h
Valid range
for ‘f’
Access RAM
FFh
Bank 15
F60h
SFRs
FFFh
When a = 0 and f ≤ 5Fh:
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Note that in this mode, the
correct syntax is:
ADDWF [k], d
where ‘k’ is same as ‘f’.
When a = 1 (all values of f):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is
interpreted as a location in
one of the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
Data Memory
000h
Bank 0
060h
100h
001001da ffffffff
Bank 1
through
Bank 14
FSR2H
FSR2L
F00h
Bank 15
F60h
SFRs
FFFh
Data Memory
BSR
00000000
000h
Bank 0
060h
100h
Bank 1
through
Bank 14
001001da ffffffff
F00h
Bank 15
F60h
SFRs
FFFh
DS39932C-page 94
Data Memory
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
5.6.3
MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the lower part of Access RAM
(00h to 5Fh) is mapped. Rather than containing just the
contents of the bottom part of Bank 0, this mode maps
the contents from Bank 0 and a user-defined “window”
that can be located anywhere in the data memory
space. The value of FSR2 establishes the lower
boundary of the addresses mapped to the window,
while the upper boundary is defined by FSR2 plus 95
(5Fh). Addresses in the Access RAM above 5Fh are
mapped as previously described (see Section 5.3.2
“Access Bank”). Figure 5-10 provides an example of
Access Bank remapping in this addressing mode.
FIGURE 5-10:
Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is ‘1’) will continue
to use Direct Addressing as before. Any Indirect or
Indexed Addressing operation that explicitly uses any
of the indirect file operands (including FSR2) will continue to operate as standard Indirect Addressing. Any
instruction that uses the Access Bank, but includes a
register address of greater than 05Fh, will use Direct
Addressing and the normal Access Bank map.
5.6.4
BSR IN INDEXED LITERAL OFFSET
MODE
Although the Access Bank is remapped when the
extended instruction set is enabled, the operation of the
BSR remains unchanged. Direct Addressing, using the
BSR to select the data memory bank, operates in the
same manner as previously described.
REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING
Example Situation:
ADDWF f, d, a
FSR2H:FSR2L = 120h
Locations in the region
from the FSR2 Pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
000h
05Fh
Bank 0
100h
120h
17Fh
200h
Window
Bank 1
00h
Bank 1 “Window”
5Fh
60h
Special Function Registers
at F60h through FFFh are
mapped to 60h through
FFh, as usual.
Bank 0 addresses below
5Fh are not available in
this mode. They can still
be addressed by using the
BSR.
Not Accessible
Bank 2
through
Bank 14
SFRs
FFh
Access Bank
F00h
Bank 15
F60h
FFFh
SFRs
Data Memory
© 2009 Microchip Technology Inc.
DS39932C-page 95
PIC18F46J11 FAMILY
NOTES:
DS39932C-page 96
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
6.0
FLASH PROGRAM MEMORY
6.1
Table Reads and Table Writes
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
A read from program memory is executed on 1 byte at
a time. A write to program memory is executed on
blocks of 64 bytes at a time or 2 bytes at a time.
Program memory is erased in blocks of 1024 bytes at
a time. A bulk erase operation may not be issued from
user code.
• Table Read (TBLRD)
• Table Write (TBLWT)
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Table read operations retrieve data from program
memory and place it into the data RAM space.
Figure 6-1 illustrates the operation of a table read with
program memory and data RAM.
Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 6.5 “Writing
to Flash Program Memory”. Figure 6-2 illustrates the
operation of a table write with program memory and data
RAM.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word-aligned. Therefore, a table block can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word-aligned.
FIGURE 6-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
Table Pointer(1)
TBLPTRU
TBLPTRH
Table Latch (8-bit)
TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Note 1:
Table Pointer register points to a byte in program memory.
© 2009 Microchip Technology Inc.
DS39932C-page 97
PIC18F46J11 FAMILY
FIGURE 6-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
Table Pointer(1)
TBLPTRU
TBLPTRH
Table Latch (8-bit)
TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Note 1:
6.2
Table Pointer actually points to one of 64 holding registers, the address of which is determined by
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
Section 6.5 “Writing to Flash Program Memory”.
Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. Those are:
•
•
•
•
EECON1 register
EECON2 register
TABLAT register
TBLPTR registers
6.2.1
EECON1 AND EECON2 REGISTERS
The EECON1 register (Register 6-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The WPROG bit, when set, will allow programming
two bytes per word on the execution of the WR
command. If this bit is cleared, the WR command will
result in programming on a block of 64 bytes.
DS39932C-page 98
The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WR bit is set, and cleared
when the internal programming timer expires and the
write operation is complete.
Note:
During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset, or a write operation was
attempted improperly.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the write operation.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 6-1:
EECON1: EEPROM CONTROL REGISTER 1 (ACCESS FA6h)
U-0
U-0
R/W-0
R/W-0
R/W-x
R/W-0
R/S-0
U-0
—
—
WPROG
FREE
WRERR
WREN
WR
—
bit 7
bit 0
Legend:
S = Settable bit (cannot be cleared in software)
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5
WPROG: One Word-Wide Program bit
1 = Program 2 bytes on the next WR command
0 = Program 64 bytes on the next WR command
bit 4
FREE: Flash Erase Enable bit
1 = Perform an erase operation on the next WR command (cleared by hardware after completion of
erase)
0 = Perform write only
bit 3
WRERR: Flash Program Error Flag bit
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation, or an improper write attempt)
0 = The write operation completed
bit 2
WREN: Flash Program Write Enable bit
1 = Allows write cycles to Flash program memory
0 = Inhibits write cycles to Flash program memory
bit 1
WR: Write Control bit
1 = Initiates a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.)
0 = Write cycle is complete
bit 0
Unimplemented: Read as ‘0’
© 2009 Microchip Technology Inc.
DS39932C-page 99
PIC18F46J11 FAMILY
6.2.2
TABLE LATCH REGISTER (TABLAT)
6.2.4
TABLE POINTER BOUNDARIES
The Table Latch (TABLAT) is an 8-bit register mapped
into the Special Function Register (SFR) space. The
Table Latch register is used to hold 8-bit data during
data transfers between program memory and data
RAM.
TBLPTR is used in reads, writes and erases of the
Flash program memory.
6.2.3
When a TBLWT is executed, the seven Least Significant
bits (LSbs) of the Table Pointer register (TBLPTR<6:0>)
determine which of the 64 program memory holding
registers is written to. When the timed write to program
memory begins (via the WR bit), the 12 Most Significant
bits (MSbs) of the TBLPTR (TBLPTR<21:10>)
determine which program memory block of 1024 bytes
is written to. For more information, see Section 6.5
“Writing to Flash Program Memory”.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
TABLE POINTER REGISTER
(TBLPTR)
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three registers
join to form a 22-bit wide pointer. The low-order 21 bits
allow the device to address up to 2 Mbytes of program
memory space. The 22nd bit allows access to the device
ID, the user ID and the Configuration bits.
When an erase of program memory is executed, the
12 MSbs of the Table Pointer register point to the
1024-byte block that will be erased. The LSbs are
ignored.
The Table Pointer register, TBLPTR, is used by the
TBLRD and TBLWT instructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation.
Figure 6-3 illustrates the relevant boundaries of
TBLPTR based on Flash program memory operations.
Table 6-1 provides these operations. These operations
on the TBLPTR only affect the low-order 21 bits.
TABLE 6-1:
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLRD*TBLWT*-
TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+*
TBLPTR is incremented before the read/write
FIGURE 6-3:
21
TABLE POINTER BOUNDARIES BASED ON OPERATION
TBLPTRU
16
15
TBLPTRH
8
7
TBLPTRL
0
ERASE: TBLPTR<20:10>
TABLE WRITE: TBLPTR<20:6>
TABLE READ: TBLPTR<21:0>
DS39932C-page 100
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
6.3
Reading the Flash Program
Memory
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
The TBLRD instruction is used to retrieve data from
program memory and places it into data RAM. Table
reads from program memory are performed one byte at
a time.
The internal program memory is typically organized by
words. The LSb of the address selects between the high
and low bytes of the word.
Figure 6-4 illustrates the interface between the internal
program memory and the TABLAT.
FIGURE 6-4:
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx1
Instruction Register
(IR)
EXAMPLE 6-1:
FETCH
TBLRD
TBLPTR = xxxxx0
TABLAT
Read Register
READING A FLASH PROGRAM MEMORY WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the word
READ_WORD
TBLRD*+
MOVF
MOVWF
TBLRD*+
MOVF
MOVWF
TABLAT, W
WORD_EVEN
TABLAT, W
WORD_ODD
© 2009 Microchip Technology Inc.
; read into TABLAT and increment
; get data
; read into TABLAT and increment
; get data
DS39932C-page 101
PIC18F46J11 FAMILY
6.4
Erasing Flash Program Memory
The minimum erase block is 512 words or 1024 bytes.
Only through the use of an external programmer, or
through ICSP control, can larger blocks of program
memory be bulk erased. Word erase in the Flash array
is not supported.
When initiating an erase sequence from the microcontroller itself, a block of 1024 bytes of program
memory is erased. The Most Significant 12 bits of the
TBLPTR<21:10> point to the block being erased.
TBLPTR<9:0> are ignored.
The EECON1 register commands the erase operation.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation. For
protection, the write initiate sequence for EECON2
must be used.
6.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory location is:
1.
2.
3.
4.
5.
6.
7.
8.
Load Table Pointer register with address of row
being erased.
Set the WREN and FREE bits (EECON1<2,4>)
to enable the erase operation.
Disable interrupts.
Write 55h to EECON2.
Write 0AAh to EECON2.
Set the WR bit; this will begin the erase cycle.
The CPU will stall for the duration of the erase
for TIE (see parameter D133B).
Re-enable interrupts.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
EXAMPLE 6-2:
ERASING FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; load TBLPTR with the base
; address of the memory block
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
EECON1,
EECON1,
INTCON,
55h
EECON2
0AAh
EECON2
EECON1,
INTCON,
; enable write to memory
; enable Erase operation
; disable interrupts
ERASE_ROW
Required
Sequence
DS39932C-page 102
WREN
FREE
GIE
; write 55h
WR
GIE
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
6.5
Writing to Flash Program Memory
The on-chip timer controls the write time. The
write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
The programming block is 32 words or 64 bytes.
Programming one word or 2 bytes at a time is also
supported.
Note 1: Unlike previous PIC® devices, devices of
the PIC18F46J11 family do not reset the
holding registers after a write occurs. The
holding registers must be cleared or
overwritten before a programming
sequence.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 64 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte, the
TBLWT instruction may need to be executed 64 times for
each programming operation (if WPROG = 0). All of the
table write operations will essentially be short writes
because only the holding registers are written. At the
end of updating the 64 holding registers, the EECON1
register must be written to in order to start the
programming operation with a long write.
2: To maintain the endurance of the program
memory cells, each Flash byte should not
be programmed more than once between
erase operations. Before attempting to
modify the contents of the target cell a
second time, an erase of the target page,
or a bulk erase of the entire memory, must
be performed.
The long write is necessary for programming the
internal Flash. Instruction execution is halted while in a
long write cycle. The long write will be terminated by
the internal programming timer.
FIGURE 6-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
TBLPTR = xxxxx0
8
TBLPTR = xxxxx2
TBLPTR = xxxxx1
Holding Register
Holding Register
8
TBLPTR = xxxx3F
Holding Register
Holding Register
Program Memory
6.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
Read 1024 bytes into RAM.
Update data values in RAM as necessary.
Load Table Pointer register with address being
erased.
Execute the erase procedure.
Load Table Pointer register with address of first
byte being written, minus 1.
Write the 64 bytes into the holding registers with
auto-increment.
Set the WREN bit (EECON1<2>) to enable byte
writes.
© 2009 Microchip Technology Inc.
8.
9.
10.
11.
12.
Disable interrupts.
Write 55h to EECON2.
Write 0AAh to EECON2.
Set the WR bit. This will begin the write cycle.
The CPU will stall for the duration of the write for
TIW (see parameter D133A).
13. Re-enable interrupts.
14. Repeat steps 6 through 13 until all 1024 bytes
are written to program memory.
15. Verify the memory (table read).
An example of the required code is provided in
Example 6-3 on the following page.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 bytes in
the holding register.
DS39932C-page 103
PIC18F46J11 FAMILY
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base address
; of the memory block, minus 1
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
MOVLW
MOVWF
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
D'16'
WRITE_COUNTER
; enable write to memory
; enable Erase operation
; disable interrupts
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
D'64'
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
ERASE_BLOCK
; write 55h
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
; Need to write 16 blocks of 64 to write
; one erase block of 1024
RESTART_BUFFER
; point to buffer
FILL_BUFFER
...
; read the new data from I2C, SPI,
; PSP, USART, etc.
WRITE_BUFFER
MOVLW
MOVWF
WRITE_BYTE_TO_HREGS
MOVFF
MOVWF
TBLWT+*
D’64
COUNTER
; number of bytes in holding register
POSTINC0, WREG
TABLAT
;
;
;
;
;
DECFSZ COUNTER
BRA
WRITE_BYTE_TO_HREGS
get low byte of buffer data
present data to table latch
write data, perform a short write
to internal TBLWT holding register.
loop until buffers are full
PROGRAM_MEMORY
Required
Sequence
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
EECON1,
INTCON,
55h
EECON2
0AAh
EECON2
EECON1,
INTCON,
EECON1,
WREN
GIE
; write 55h
WR
GIE
WREN
DECFSZ WRITE_COUNTER
BRA
RESTART_BUFFER
DS39932C-page 104
; enable write to memory
; disable interrupts
;
;
;
;
write 0AAh
start program (CPU stall)
re-enable interrupts
disable write to memory
; done with one write cycle
; if not done replacing the erase block
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
6.5.2
FLASH PROGRAM MEMORY WRITE
SEQUENCE (WORD PRORAMMING).
3.
The PIC18F46J11 family of devices has a feature that
allows programming a single word (two bytes). This
feature is enabled when the WPROG bit is set. If the
memory location is already erased, the following
sequence is required to enable this feature:
1.
2.
4.
5.
6.
7.
8.
Load the Table Pointer register with the address
of the data to be written. (It must be an even
address.)
Write the 2 bytes into the holding registers by
performing table writes. (Do not post-increment
on the second table write.)
EXAMPLE 6-4:
9.
Set the WREN bit (EECON1<2>) to enable
writes and the WPROG bit (EECON1<5>) to
select Word Write mode.
Disable interrupts.
Write 55h to EECON2.
Write 0AAh to EECON2.
Set the WR bit; this will begin the write cycle.
The CPU will stall for the duration of the write for
TIW (see parameter D133A).
Re-enable interrupts.
SINGLE-WORD WRITE TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
; Load TBLPTR with the base address
MOVWF
TBLPTRL
MOVLW
MOVWF
TBLWT*+
MOVLW
MOVWF
TBLWT*
DATA0
TABLAT
; LSB of word to be written
DATA1
TABLAT
; MSB of word to be written
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
BCF
EECON1,
EECON1,
INTCON,
55h
EECON2
0AAh
EECON2
EECON1,
INTCON,
EECON1,
EECON1,
; The table pointer must be loaded with an even
address
; The last table write must not increment the table
pointer! The table pointer needs to point to the
MSB before starting the write operation.
PROGRAM_MEMORY
Required
Sequence
© 2009 Microchip Technology Inc.
WPROG
WREN
GIE
; enable single word write
; enable write to memory
; disable interrupts
; write 55h
WR
GIE
WPROG
WREN
;
;
;
;
;
write AAh
start program (CPU stall)
re-enable interrupts
disable single word write
disable write to memory
DS39932C-page 105
PIC18F46J11 FAMILY
6.5.3
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.5.4
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and
TABLE 6-2:
reprogrammed if needed. If the write operation is
interrupted by a MCLR Reset or a WDT time-out Reset
during normal operation, the user can check the
WRERR bit and rewrite the location(s) as needed.
6.6
Flash Program Operation During
Code Protection
See Section 25.6 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Name
Bit 7
Bit 6
Bit 5
TBLPTRU
—
—
bit 21
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
Page:
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
63
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
63
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
63
TABLAT
63
Program Memory Table Latch
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
EECON2
Program Memory Control Register 2 (not a physical register)
EECON1
—
—
WPROG
INT0IE
FREE
RBIE
WRERR
TMR0IF
WREN
INT0IF
RBIF
63
65
WR
—
65
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash program memory access.
DS39932C-page 106
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
7.0
8 x 8 HARDWARE MULTIPLIER
7.1
Introduction
EXAMPLE 7-1:
MOVF
MULWF
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
ARG1, W
ARG2
EXAMPLE 7-2:
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applications previously reserved for digital signal processors.
Table 7-1 provides a comparison of various hardware
and software multiply operations, along with the
savings in memory and execution time.
7.2
8 x 8 UNSIGNED MULTIPLY
ROUTINE
;
; ARG1 * ARG2 ->
; PRODH:PRODL
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVF
MULWF
ARG1, W
ARG2
BTFSC
SUBWF
ARG2, SB
PRODH, F
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
;
;
;
;
;
ARG1 * ARG2 ->
PRODH:PRODL
Test Sign Bit
PRODH = PRODH
- ARG1
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
Operation
Example 7-1 provides the instruction sequence for an
8 x 8 unsigned multiplication. Only one instruction is
required when one of the arguments is already loaded
in the WREG register.
Example 7-2 provides the instruction sequence for an
8 x 8 signed multiplication. To account for the sign bits
of the arguments, each argument’s Most Significant bit
(MSb) is tested and the appropriate subtractions are
done.
TABLE 7-1:
PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
Routine
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
Multiply Method
Program
Memory
(Words)
Cycles
(Max)
Without hardware multiply
13
Hardware multiply
1
Without hardware multiply
33
Hardware multiply
6
Without hardware multiply
Time
@ 48 MHz
@ 10 MHz
@ 4 MHz
69
5.7 μs
27.6 μs
69 μs
1
83.3 ns
400 ns
1 μs
91
7.5 μs
36.4 μs
91 μs
6
500 ns
2.4 μs
6 μs
21
242
20.1 μs
96.8 μs
242 μs
Hardware multiply
28
28
2.3 μs
11.2 μs
28 μs
Without hardware multiply
52
254
21.6 μs
102.6 μs
254 μs
Hardware multiply
35
40
3.3 μs
16.0 μs
40 μs
© 2009 Microchip Technology Inc.
DS39932C-page 107
PIC18F46J11 FAMILY
Example 7-3 provides the instruction sequence for a
16 x 16 unsigned multiplication. Equation 7-1 provides
the algorithm that is used. The 32-bit result is stored in
four registers (RES<3:0>).
EQUATION 7-1:
RES3:RES0
=
=
EXAMPLE 7-3:
EQUATION 7-2:
RES3:RES0
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
ARG1H:ARG1L · ARG2H:ARG2L
(ARG1H · ARG2H · 216) +
(ARG1H · ARG2L · 28) +
(ARG1L · ARG2H · 28) +
(ARG1L · ARG2L)
EXAMPLE 7-4:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1L, W
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
; ARG1L * ARG2L->
; PRODH:PRODL
;
;
ARG1L * ARG2H->
PRODH:PRODL
Add cross
products
ARG1H * ARG2L->
PRODH:PRODL
Add cross
products
Example 7-4 provides the sequence to do a 16 x 16
signed multiply. Equation 7-2 provides the algorithm
used. The 32-bit result is stored in four registers
(RES<3:0>). To account for the sign bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.
DS39932C-page 108
MOVF
MULWF
ARG1L, W
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
ARG1H, W
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
ARG2H, W
RES3
; ARG1H:ARG1L neg?
; no, done
;
;
;
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
;
;
;
;
;
;
;
;
ARG1L * ARG2H ->
PRODH:PRODL
Add cross
products
;
;
;
;
;
;
;
;
;
;
;
16 x 16 SIGNED MULTIPLY
ROUTINE
;
;
;
;
;
;
;
;
;
;
ARG1H:ARG1L · ARG2H:ARG2L
(ARG1H · ARG2H · 216) +
(ARG1H · ARG2L · 28) +
(ARG1L · ARG2H · 28) +
(ARG1L · ARG2L) +
(-1 · ARG2H<7> · ARG1H:ARG1L · 216) +
(-1 · ARG1H<7> · ARG2H:ARG2L · 216)
;
;
; ARG1H * ARG2H->
; PRODH:PRODL
;
;
=
=
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
;
;
;
;
;
;
;
;
;
ARG1H * ARG2L ->
PRODH:PRODL
Add cross
products
;
;
SIGN_ARG1
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
;
CONT_CODE
:
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
8.0
INTERRUPTS
Devices of the PIC18F46J11 family have multiple interrupt sources and an interrupt priority feature that allows
most interrupt sources to be assigned a high-priority
level or a low-priority level. The high-priority interrupt
vector is at 0008h and the low-priority interrupt vector
is at 0018h. High-priority interrupt events will interrupt
any low-priority interrupts that may be in progress.
There are 13 registers, which are used to control
interrupt operation. These registers are:
•
•
•
•
•
•
•
RCON
INTCON
INTCON2
INTCON3
PIR1, PIR2, PIR3
PIE1, PIE2, PIE3
IPR1, IPR2, IPR3
It is recommended that the Microchip header files
supplied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the
assembler/compiler to automatically take care of the
placement of these bits within the specified register.
In general, interrupt sources have three bits to control
their operation. They are:
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all
interrupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address 0008h or 0018h,
depending on the priority bit setting. Individual
interrupts can be disabled through their corresponding
enable bits.
© 2009 Microchip Technology Inc.
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PIC® mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit,
which enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit, which enables/disables all
interrupt sources. All interrupts branch to address
0008h in Compatibility mode.
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High-priority interrupt sources can interrupt a
low-priority interrupt. Low-priority interrupts are not
processed while high-priority interrupts are in progress.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address (0008h
or 0018h). Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bits must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.
For external interrupt events, such as the INTx pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.
Note:
Do not use the MOVFF instruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
DS39932C-page 109
PIC18F46J11 FAMILY
FIGURE 8-1:
PIC18F46J11 FAMILY INTERRUPT LOGIC
Wake-up if in
Idle or Sleep modes
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
PIR1<7:0>
PIE1<7:0>
IPR1<7:0>
PIR2<7:0>
PIE2<7:0>
IPR2<7:0>
Interrupt to CPU
Vector to Location
0008h
GIE/GIEH
IPEN
PIR3<7:0>
PIE3<7:0>
IPR3<7:0>
IPEN
PEIE/GIEL
IPEN
High-Priority Interrupt Generation
Low-Priority Interrupt Generation
PIR1<7:0>
PIE1<7:0>
IPR1<7:0>
PIR2<7:0>
PIE2<7:0>
IPR2<7:0>
PIR3<7:0>
PIE3<7:0>
IPR3<7:0>
DS39932C-page 110
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
Interrupt to CPU
Vector to Location
0018h
IPEN
GIE/GIEH
PEIE/GIEL
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
8.1
INTCON Registers
Note:
The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.
REGISTER 8-1:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.
INTCON: INTERRUPT CONTROL REGISTER (ACCESS FF2h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all high-priority interrupts
0 = Disables all interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low-priority peripheral interrupts
0 = Disables all low-priority peripheral interrupts
bit 5
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4
INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit(1)
1 = At least one of the RB<7:4> pins changed state (must be cleared in software)
0 = None of the RB<7:4> pins have changed state
Note 1:
A mismatch condition will continue to set this bit. Reading PORTB and waiting 1 TCY will end the mismatch
condition and allow the bit to be cleared.
© 2009 Microchip Technology Inc.
DS39932C-page 111
PIC18F46J11 FAMILY
REGISTER 8-2:
INTCON2: INTERRUPT CONTROL REGISTER 2 (ACCESS FF1h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5
INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4
INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 3
INTEDG3: External Interrupt 3 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 2
TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
INT3IP: INT3 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Note:
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
DS39932C-page 112
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 8-3:
INTCON3: INTERRUPT CONTROL REGISTER 3 (ACCESS FF0h)
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
INT2IP: INT2 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
INT1IP: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
INT3IE: INT3 External Interrupt Enable bit
1 = Enables the INT3 external interrupt
0 = Disables the INT3 external interrupt
bit 4
INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2
INT3IF: INT3 External Interrupt Flag bit
1 = The INT3 external interrupt occurred (must be cleared in software)
0 = The INT3 external interrupt did not occur
bit 1
INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur
Note:
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
© 2009 Microchip Technology Inc.
DS39932C-page 113
PIC18F46J11 FAMILY
8.2
PIR Registers
Note 1: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2, PIR3).
REGISTER 8-4:
2: User software should ensure the
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (ACCESS F9Eh)
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
PMPIF(1)
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PMPIF: Parallel Master Port Read/Write Interrupt Flag bit(1)
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5
RC1IF: EUSART1 Receive Interrupt Flag bit
1 = The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read)
0 = The EUSART1 receive buffer is empty
bit 4
TX1IF: EUSART1 Transmit Interrupt Flag bit
1 = The EUSART1 transmit buffer, TXREG1, is empty (cleared when TXREG1 is written)
0 = The EUSART1 transmit buffer is full
bit 3
SSP1IF: Master Synchronous Serial Port 1 Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2
CCP1IF: ECCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1:
These bits are unimplemented on 28-pin devices.
DS39932C-page 114
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 8-5:
R/W-0
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (ACCESS FA1h)
R/W-0
OSCFIF
R/W-0
CM2IF
CM1IF
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
BCL1IF
LVDIF
TMR3IF
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
OSCFIF: Oscillator Fail Interrupt Flag bit
1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = Device clock operating
bit 6
CM2IF: Comparator 2 Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 5
CM1IF: Comparator 1 Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 4
Unimplemented: Read as ‘0’
bit 3
BCL1IF: Bus Collision Interrupt Flag bit (MSSP1 module)
1 = A bus collision occurred (must be cleared in software)
0 = No bus collision occurred
bit 2
LVDIF: High/Low-Voltage Detect (HLVD) Interrupt Flag bit
1 = A high/low-voltage condition occurred (must be cleared in software)
0 = An HLVD event has not occurred
bit 1
TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be cleared in software)
0 = TMR3 register did not overflow
bit 0
CCP2IF: ECCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
© 2009 Microchip Technology Inc.
DS39932C-page 115
PIC18F46J11 FAMILY
REGISTER 8-6:
PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 (ACCESS FA4h)
R/W-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CTMUIF
TMR3GIF
RTCCIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 6
BCL2IF: Bus Collision Interrupt Flag bit (MSSP2 module)
1 = A bus collision occurred (must be cleared in software)
0 = No bus collision occurred
bit 5
RC2IF: EUSART2 Receive Interrupt Flag bit
1 = The EUSART2 receive buffer, RCREG2, is full (cleared when RCREG2 is read)
0 = The EUSART2 receive buffer is empty
bit 4
TX2IF: EUSART2 Transmit Interrupt Flag bit
1 = The EUSART2 transmit buffer, TXREG2, is empty (cleared when TXREG2 is written)
0 = The EUSART2 transmit buffer is full
bit 3
TMR4IF: TMR4 to PR4 Match Interrupt Flag bit
1 = TMR4 to PR4 match occurred (must be cleared in software)
0 = No TMR4 to PR4 match occurred
bit 2
CTMUIF: Charge Time Measurement Unit Interrupt Flag bit
1 = A CTMU event has occurred (must be cleared in software)
0 = CTMU event has not occurred
bit 1
TMR3GIF: Timer3 Gate Event Interrupt Flag bit
1 = A Timer3 gate event completed (must be cleared in software)
0 = No Timer3 gate event completed
bit 0
RTCCIF: RTCC Interrupt Flag bit
1 = RTCC interrupt occurred (must be cleared in software)
0 = No RTCC interrupt occurred
DS39932C-page 116
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
8.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2, PIE3). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.
REGISTER 8-7:
R/W-0
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ACCESS F9Dh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
(1)
PMPIE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
PMPIE: Parallel Master Port Read/Write Interrupt Enable bit(1)
1 = Enables the PMP read/write interrupt
0 = Disables the PMP read/write interrupt
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5
RC1IE: EUSART1 Receive Interrupt Enable bit
1 = Enables the EUSART1 receive interrupt
0 = Disables the EUSART1 receive interrupt
bit 4
TX1IE: EUSART1 Transmit Interrupt Enable bit
1 = Enables the EUSART1 transmit interrupt
0 = Disables the EUSART1 transmit interrupt
bit 3
SSP1IE: Master Synchronous Serial Port 1 Interrupt Enable bit
1 = Enables the MSSP1 interrupt
0 = Disables the MSSP1 interrupt
bit 2
CCP1IE: ECCP1 Interrupt Enable bit
1 = Enables the ECCP1 interrupt
0 = Disables the ECCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1:
x = Bit is unknown
These bits are unimplemented on 28-pin devices.
© 2009 Microchip Technology Inc.
DS39932C-page 117
PIC18F46J11 FAMILY
REGISTER 8-8:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ACCESS FA0h)
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
OSCFIE
CM2IE
CM1IE
—
BCL1IE
LVDIE
TMR3IE
CCP2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
OSCFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6
CM2IE: Comparator 2 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 5
CM1IE: Comparator 1 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4
Unimplemented: Read as ‘0’
bit 3
BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module)
1 = Enabled
0 = Disabled
bit 2
LVDIE: High/Low-Voltage Detect Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1
TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0
CCP2IE: ECCP2 Interrupt Enable bit
1 = Enabled
0 = Disabled
DS39932C-page 118
x = Bit is unknown
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 8-9:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 (ACCESS FA3h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CTMUIE
TMR3GIE
RTCCIE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6
BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module)
1 = Enabled
0 = Disabled
bit 5
RC2IE: EUSART2 Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4
TX2IE: EUSART2 Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2
CTMUIE: Charge Time Measurement Unit (CTMU) Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1
TMR3GIE: Timer3 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0
RTCCIE: RTCC Interrupt Enable bit
1 = Enabled
0 = Disabled
© 2009 Microchip Technology Inc.
x = Bit is unknown
DS39932C-page 119
PIC18F46J11 FAMILY
8.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority registers (IPR1, IPR2, IPR3). Using
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
REGISTER 8-10:
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 (ACCESS F9Fh)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
PMPIP(1)
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
PMPIP: Parallel Master Port Read/Write Interrupt Priority bit(1)
1 = High priority
0 = Low priority
bit 6
ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
RC1IP: EUSART1 Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TX1IP: EUSART1 Transmit Interrupt Priority bit
x = Bit is unknown
1 = High priority
0 = Low priority
bit 3
SSP1IP: Master Synchronous Serial Port Interrupt Priority bit (MSSP1 module)
1 = High priority
0 = Low priority
bit 2
CCP1IP: ECCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
Note 1:
These bits are unimplemented on 28-pin devices.
DS39932C-page 120
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 8-11:
IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 (ACCESS FA2h)
R/W-1
R/W-1
R/W-1
U-0
R/W-1
R/W-1
R/W-1
R/W-1
OSCFIP
CM2IP
CM1IP
—
BCL1IP
LVDIP
TMR3IP
CCP2IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
OSCFIP: Oscillator Fail Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
CM2IP: Comparator 2 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
C12IP: Comparator 1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
Unimplemented: Read as ‘0’
bit 3
BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module)
1 = High priority
0 = Low priority
bit 2
LVDIP: High/Low-Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
CCP2IP: ECCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
© 2009 Microchip Technology Inc.
x = Bit is unknown
DS39932C-page 121
PIC18F46J11 FAMILY
REGISTER 8-12:
IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 (ACCESS FA5h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CTMUIP
TMR3GIP
RTCCIP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module)
1 = High priority
0 = Low priority
bit 5
RC2IP: EUSART2 Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TX2IP: EUSART2 Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
TMR4IE: TMR4 to PR4 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
CTMUIP: Charge Time Measurement Unit (CTMU) Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR3GIP: Timer3 Gate Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
RTCCIP: RTCC Interrupt Priority bit
1 = High priority
0 = Low priority
DS39932C-page 122
x = Bit is unknown
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
8.5
RCON Register
The RCON register contains bits used to determine the
cause of the last Reset or wake-up from Idle or Sleep
mode. RCON also contains the bit that enables
interrupt priorities (IPEN).
REGISTER 8-13:
RCON: RESET CONTROL REGISTER (ACCESS FD0h)
R/W-0
U-0
R/W-1
R/W-1
R-1
R-1
R/W-0
R/W-0
IPEN
—
CM
RI
TO
PD
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6
Unimplemented: Read as ‘0’
bit 5
CM: Configuration Mismatch Flag bit
For details on bit operation, see Register 4-1.
bit 4
RI: RESET Instruction Flag bit
For details on bit operation, see Register 4-1.
bit 3
TO: Watchdog Timer Time-out Flag bit
For details on bit operation, see Register 4-1.
bit 2
PD: Power-Down Detection Flag bit
For details on bit operation, see Register 4-1.
bit 1
POR: Power-on Reset Status bit
For details on bit operation, see Register 4-1.
bit 0
BOR: Brown-out Reset Status bit
For details on bit operation, see Register 4-1.
© 2009 Microchip Technology Inc.
x = Bit is unknown
DS39932C-page 123
PIC18F46J11 FAMILY
8.6
INTx Pin Interrupts
External interrupts on the INT0, INT1, INT2 and INT3
pins are edge-triggered. If the corresponding INTEDGx
bit in the INTCON2 register is set (= 1), the interrupt is
triggered by a rising edge; if the bit is clear, the trigger
is on the falling edge. When a valid edge appears on
the INTx pin, the corresponding flag bit and INTxIF are
set. This interrupt can be disabled by clearing the
corresponding enable bit, INTxIE. Flag bit, INTxIF,
must be cleared in software in the Interrupt Service
Routine before re-enabling the interrupt.
All external interrupts (INT0, INT1, INT2 and INT3) can
wake-up the processor from the power-managed
modes if bit, INTxIE, was set prior to going into the
power-managed modes. If the Global Interrupt Enable
bit, GIE, is set, the processor will branch to the interrupt
vector following wake-up.
Interrupt priority for INT1, INT2 and INT3 is determined
by the value contained in the Interrupt Priority bits,
INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and
INT3IP (INTCON2<1>). There is no priority bit
associated with INT0. It is always a high-priority
interrupt source.
8.7
TMR0 Interrupt
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L register
EXAMPLE 8-1:
MOVWF
MOVFF
MOVFF
;
; USER
;
MOVFF
MOVF
MOVFF
pair (FFFFh → 0000h) will set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON<5>). Interrupt priority for Timer0 is
determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2<2>). See Section 11.0
“Timer0 Module” for further details on the Timer0
module.
8.8
PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
8.9
Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the Fast Return Stack. If a fast
return from interrupt is not used (see Section 5.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 8-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
ISR CODE
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
DS39932C-page 124
; Restore BSR
; Restore WREG
; Restore STATUS
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
9.0
I/O PORTS
9.1
I/O Port Pin Capabilities
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
When developing an application, the capabilities of the
port pins must be considered. Outputs on some pins
have higher output drive strength than others. Similarly,
some pins can tolerate higher than VDD input levels.
Each port has three registers for its operation. These
registers are:
The output pin drive strengths vary for groups of pins
intended to meet the needs for a variety of applications.
PORTB and PORTC are designed to drive higher
loads, such as LEDs. All other ports are designed for
small loads, typically indication only. Table 9-1 summarizes the output capabilities. Refer to Section 28.0
“Electrical Characteristics” for more details.
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (Data Latch)
The Data Latch (LAT register) is useful for read-modifywrite operations on the value that the I/O pins are
driving.
9.1.1
TABLE 9-1:
OUTPUT DRIVE LEVELS
Port
Figure 9-1 displays a simplified model of a generic I/O
port, without the interfaces to other peripherals.
PORTA
FIGURE 9-1:
PORTE
GENERIC I/O PORT
OPERATION
PIN OUTPUT DRIVE
Drive
PORTD
Minimum Intended for indication.
PORTB
High
PORTC
9.1.2
RD LAT
Data
Bus
WR LAT
or PORT
D
Q
I/O pin(1)
CK
Data Latch
D
WR TRIS
Q
CK
TRIS Latch
Input
Buffer
RD TRIS
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Pins that are used
as digital only inputs are able to handle DC voltages up
to 5.5V; a level typical for digital logic circuits. In contrast,
pins that also have analog input functions of any kind
can only tolerate voltages up to VDD. Voltage excursions
beyond VDD on these pins should be avoided. Table 9-2
summarizes the input capabilities. Refer to
Section 28.0 “Electrical Characteristics” for more
details.
D
Port or Pin
ENEN
PORTA<7:0>
RD PORT
PORTB<3:0>
PORTC<2:0>
Note 1:
I/O pins have diode protection to VDD and
VSS.
INPUT VOLTAGE LEVELS
Tolerated
Input
Description
VDD
Only VDD input levels
tolerated.
5.5V
Tolerates input levels
above VDD, useful for
most standard logic.
PORTE<2:0>
PORTB<7:4>
PORTC<7:3>
PORTD<7:0>
© 2009 Microchip Technology Inc.
Suitable for direct LED drive
levels.
INPUT PINS AND VOLTAGE
CONSIDERATIONS
TABLE 9-2:
Q
Description
DS39932C-page 125
PIC18F46J11 FAMILY
9.1.3
INTERFACING TO A 5V SYSTEM
Though the VDDMAX of the PIC18F46J11 family is 3.6V,
these devices are still capable of interfacing with 5V
systems, even if the VIH of the target system is above
3.6V. This is accomplished by adding a pull-up resistor
to the port pin (Figure 9-2), clearing the LAT bit for that
pin and manipulating the corresponding TRIS bit
(Figure 9-1) to either allow the line to be pulled high or
to drive the pin low. Only port pins that are tolerant of
voltages up to 5.5V can be used for this type of
interface (refer to Section 9.1.2 “Input Pins and
Voltage Considerations”).
FIGURE 9-2:
+5V SYSTEM HARDWARE
INTERFACE
PIC18F46J11
+5V
The open-drain option is implemented on port pins
specifically associated with the data and clock outputs
of the EUSARTs, the MSSP modules (in SPI mode) and
the ECCP modules. It is selectively enabled by setting
the open-drain control bit for the corresponding module
in the ODCON registers (Register 9-1, Register 9-2
and Register 9-3). Their configuration is discussed in
more detail with the individual port where these
peripherals are multiplexed.
When the open-drain option is required, the output pin
must also be tied through an external pull-up resistor
provided by the user to a higher voltage level, up to
5.5V (Figure 9-3). When a digital logic high signal is
output, it is pulled up to the higher voltage level.
FIGURE 9-3:
USING THE OPEN-DRAIN
OUTPUT (USART SHOWN
AS EXAMPLE)
+5V Device
+5V
3.3V
PIC18F46J11
RD7
VDD
EXAMPLE 9-1:
BCF
BCF
BCF
9.1.4
LATD, 7
TRISD, 7
TRISD, 7
TXX
(at logic ‘1’)
5V
COMMUNICATING WITH
THE +5V SYSTEM
;
;
;
;
;
set up LAT register so
changing TRIS bit will
drive line low
send a 0 to the 5V system
send a 1 to the 5V system
OPEN-DRAIN OUTPUTS
The output pins for several peripherals are also
equipped with a configurable open-drain output option.
This allows the peripherals to communicate with
external digital logic operating at a higher voltage level,
without the use of level translators.
DS39932C-page 126
9.1.5
TTL INPUT BUFFER OPTION
Many of the digital I/O ports use Schmitt Trigger (ST)
input buffers. While this form of buffering works well
with many types of input, some applications may
require TTL level signals to interface with external logic
devices. This is particularly true for the Parallel Master
Port (PMP), which is likely to be interfaced to TTL level
logic or memory devices.
The inputs for the PMP can be optionally configured for
TTL buffers with the PMPTTL bit in the PADCFG1 register (Register 9-4). Setting this bit configures all data
and control input pins for the PMP to use TTL buffers.
By default, these PMP inputs use the port’s ST buffers.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 9-1:
ODCON1: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 1 (BANKED F42h)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
ECCP2OD
ECCP1OD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1
ECCP2OD: ECCP2 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
bit 0
ECCP1OD: ECCP1 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
REGISTER 9-2:
x = Bit is unknown
ODCON2: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 2 (BANKED F41h)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
U2OD
U1OD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1
U2OD: USART2 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
bit 0
U1OD: USART1 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
© 2009 Microchip Technology Inc.
x = Bit is unknown
DS39932C-page 127
PIC18F46J11 FAMILY
REGISTER 9-3:
ODCON3: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 3 (BANKED F40h)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
SPI2OD
SPI1OD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1
SPI2OD: SPI2 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
bit 0
SPI1OD: SPI1 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
REGISTER 9-4:
U-0
x = Bit is unknown
PADCFG1: PAD CONFIGURATION CONTROL REGISTER 1 (BANKED F3Ch)
U-0
—
—
U-0
—
U-0
—
U-0
R/W-0
R/W-0
R/W-0
—
RTSECSEL1(1)
RTSECSEL0(1)
PMPTTL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-3
Unimplemented: Read as ‘0’
bit 2-1
RTSECSEL<1:0>: RTCC Seconds Clock Output Select bits(1)
11 = Reserved; do not use
10 = RTCC source clock is selected for the RTCC pin (can be INTRC or T1OSC, depending on the
RTCOSC (CONFIG3L<1>) setting)
01 = RTCC seconds clock is selected for the RTCC pin
00 = RTCC alarm pulse is selected for the RTCC pin
bit 0
PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffers
Note 1:
To enable the actual RTCC output, the RTCOE (RTCCFG<2>) bit needs to be set.
DS39932C-page 128
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
9.2
PORTA, TRISA and LATA Registers
PORTA is a 7-bit wide, bidirectional port. It may
function as a 5-bit port, depending on the oscillator
mode selected. Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., put the
corresponding output driver in a high-impedance
mode). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., put the
contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.
The Data Latch (LATA) register is also memory mapped.
Read-modify-write operations on the LATA register read
and write the latched output value for PORTA.
EXAMPLE 9-2:
CLRF
CLRF
MOVLW
MOVWF
MOVWF
MOVWF
MOVLW
MOVWF
PORTA
;
;
;
LATA
;
;
;
07h
;
ADCON1 ;
07h
;
CMCON
;
0CFh
;
;
;
TRISA
;
;
INITIALIZING PORTA
Initialize PORTA by
clearing output
data latches
Alternate method
to clear output
data latches
Configure A/D
for digital inputs
Configure comparators
for digital input
Value used to
initialize data
direction
Set RA<3:0> as inputs
RA<5:4> as outputs
The other PORTA pins are multiplexed with analog
inputs, the analog VREF+ and VREF- inputs and the comparator voltage reference output. The operation of pins,
RA<3:0> and RA5, as A/D converter inputs is selected
by clearing or setting the control bits in the ADCON1
register (A/D Control Register 1).
Pins, RA0 and RA3, may also be used as comparator
inputs and by setting the appropriate bits in the CMCON
register. To use RA<3:0> as digital inputs, it is also
necessary to turn off the comparators.
Note:
On a Power-on Reset (POR), RA5 and
RA<3:0> are configured as analog inputs
and read as ‘0’.
All PORTA pins have TTL input levels and full CMOS
output drivers.
The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
© 2009 Microchip Technology Inc.
DS39932C-page 129
PIC18F46J11 FAMILY
TABLE 9-3:
PORTA I/O SUMMARY
Pin
Function
TRIS
Setting
RA0/AN0/C1INA/
ULPWU/RP0
RA0
1
0
DIG
PORTA<0> data input; disabled when analog input enabled.
TTL
LATA<0> data output; not affected by analog input.
I
ANA
A/D input channel 0 and Comparator C1- input. Default input
configuration on POR; does not affect digital output.
C1INA
1
I
ANA
Comparator 1 input A.
ULPWU
1
I
ANA
Ultra low-power wake-up input.
RP0
1
RA1
1/O
ST
Remappable peripheral pin 0 input.
DIG
Remappable peripheral pin 0 output.
1
I
DIG
PORTA<1> data input; disabled when analog input enabled.
0
O
TTL
LATA<1> data output; not affected by analog input.
AN1
1
I
ANA
A/D input channel 1 and Comparator C2- input. Default input
configuration on POR; does not affect digital output.
C2INA
1
I
ANA
Comparator 1 input A.
PMA7(1)
1
Parallel Master Port.
I/O
ST/
TTL
0
DIG
Parallel Master Port address.
1
ST
Remappable peripheral pin 1 input.
I/O
DIG
Remappable peripheral pin 1 output
0
O
DIG
LATA<2> data output; not affected by analog input. Disabled
when CVREF output enabled.
1
I
TTL
PORTA<2> data input. Disabled when analog functions
enabled; disabled when CVREF output enabled.
AN2
1
I
ANA
A/D input channel 2 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
0
RA3/AN3/VREF+/
C1INB
Description
1
RP1
RA2/AN2/
VREF-/CVREF/
C2INB
I/O
I/O
Type
AN0
0
RA1/AN1/C2INA/
PMA7/RP1
I/O
RA2
VREF-
1
I
ANA
A/D and comparator voltage reference low input.
CVREF
x
O
ANA
Comparator voltage reference output. Enabling this feature
disables digital I/O.
C2INB
I
I
ANA
Comparator 2 input B.
0
O
ANA
CTMU pulse generator charger for the C2INB comparator
input.
RA3
0
O
DIG
LATA<3> data output; not affected by analog input.
1
I
TTL
PORTA<3> data input; disabled when analog input enabled.
AN3
1
I
ANA
A/D input channel 3 and Comparator C1+ input. Default input
configuration on POR.
VREF+
1
I
ANA
A/D and comparator voltage reference high input.
C1INB
1
I
ANA
Comparator 1 input B
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Note 1: This bit is only available on 44-pin devices.
DS39932C-page 130
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 9-3:
PORTA I/O SUMMARY (CONTINUED)
Pin
Function
TRIS
Setting
I/O
I/O
Type
RA5
0
O
DIG
LATA<5> data output; not affected by analog input.
1
I
TTL
PORTA<5> data input; disabled when analog input enabled.
AN4
1
I
ANA
A/D input channel 4. Default configuration on POR.
SS1
1
I
TTL
Slave select input for MSSP1.
High/Low-Voltage Detect external trip point reference input.
RA5/AN4/SS1/
HLVDIN/RP2
OSC2/CLKO/
RA6
OSC1/CLKI/RA7
Description
HLVDIN
1
I
ANA
RP2
1
I
ST
0
O
DIG
Remappable Peripheral pin 2 output.
OSC2
x
O
ANA
Main oscillator feedback output connection (HS mode).
CLKO
x
O
DIG
System cycle clock output (FOSC/4) in RC and EC Oscillator
modes.
RA6
1
I
TTL
PORTA<6> data input.
0
O
DIG
LATA<6> data output.
1
I
ANA
Main oscillator input connection.
OSC1
Remappable Peripheral pin 2 input.
CLKI
1
I
ANA
Main clock input connection.
RA7
1
I
TTL
PORTA<6> data input.
0
O
DIG
LATA<6> data output.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Note 1: This bit is only available on 44-pin devices.
TABLE 9-4:
Name
PORTA
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
RA7
RA6
RA5
—
RA3
RA2
RA1
RA0
81
LATA
LAT7
LAT6
LAT5
—
LAT3
LAT2
LAT1
LAT0
81
TRISA
TRIS7
TRIS6
TRISA5
—
TRISA3
TRISA2
TRISA1
TRISA0
81
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
82
ANCON0
PCFG7(1) PCFG6(1) PCFG5(1)
CMxCON
CON
COE
CPOL
EVPOL1
EVPOL0
CREF
CCH1
CCH0
81
CVRCON
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
82
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: These bits are only available in 44-pin devices.
© 2009 Microchip Technology Inc.
DS39932C-page 131
PIC18F46J11 FAMILY
9.3
PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
EXAMPLE 9-3:
CLRF
INITIALIZING PORTB
PORTB
;
;
;
CLRF LATB
;
;
;
MOVLW 0x3F
;
MOVFF WREG ADCON1 ;
Initialize PORTB by
clearing output
data latches
Alternate method
to clear output
data latches
Configure as digital I/O
pins in this example
MOVLW 0CFh
Value used to
initialize data
direction
Set RB<3:0> as inputs
RB<5:4> as outputs
RB<7:6> as inputs
MOVWF TRISB
;
;
;
;
;
;
Four of the PORTB pins (RB<7:4>) have an interrupton-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB<7:4> pin
configured as an output is excluded from the interrupton-change comparison). The input pins (of RB<7:4>)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB<7:4>
are ORed together to generate the RB Port Change
Interrupt with Flag bit, RBIF (INTCON<0>).
This interrupt can wake the device from Sleep mode or
any of the Idle modes. The user, in the Interrupt Service
Routine (ISR), can clear the interrupt using the following
steps:
1.
2.
3.
Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction).
Wait one instruction cycle (such as executing a
NOP instruction).
Clear flag bit, RBIF.
A mismatch condition continues to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared after one instruction
cycle of delay.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
The RB5 pin is multiplexed with the Timer0 module
clock input and one of the comparator outputs to
become the RB5/KBI1/SDI1/SDA1/RP8 pin.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a POR.
Note:
On a POR, the RB<3:0> bits are
configured as analog inputs by default and
read as ‘0’; RB<7:4> bits are configured
as digital inputs.
DS39932C-page 132
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 9-5:
Pin
RB0/AN12/
INT0/RP3
PORTB I/O SUMMARY
Function
TRIS
Setting
I/O
I/O
Type
RB0
1
1
TTL
PORTB<0> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input enabled.(1)
0
O
DIG
LATB<0> data output; not affected by analog input.
1
I
ANA
A/D input channel 12.(1)
AN12
RB1/AN10/
RTCC/RP4
RB2/AN8/
CTEDG1/
REFO/RP5
RB3/AN9/
CTEDG2/
PMA2/RP6
Description
INT0
1
I
ST
External interrupt 0 input.
RP3
1
I
ST
Remappable peripheral pin 3 input.
0
O
DIG
Remappable peripheral pin 3 output.
RB1
1
I
TTL
PORTB<1> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input enabled.(1)
0
O
DIG
LATB<1> data output; not affected by analog input.
AN10
1
I
ANA
A/D input channel 10.(1)
RTCC
0
O
DIG
Asynchronous serial transmit data output (USART module).
RP4
1
I
ST
Remappable peripheral pin 4 input.
0
O
DIG
Remappable peripheral pin 4 output.
RB2
1
I
TTL
PORTB<2> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input enabled.(1)
0
O
DIG
LATB<2> data output; not affected by analog input.
AN8
1
I
ANA
A/D input channel 8.(1)
CTEDG1
1
I
ST
CTMU Edge 1 input.
REFO
0
O
DIG
Reference output clock.
RP5
1
I
ST
Remappable peripheral pin 5 input.
0
O
DIG
Remappable peripheral pin 5 output.
0
O
DIG
LATB<3> data output; not affected by analog input.
1
I
TTL
PORTB<3> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input enabled.(1)
AN9
1
I
ANA
A/D input channel 9.(1)
CTEDG2
1
I
ST
CTMU edge 2 input.
(3)
0
O
DIG
Parallel Master Port address.
1
I
ST
Remappable peripheral pin 6 input.
0
O
DIG
Remappable peripheral pin 6 output.
RB3
PMA2
RP6
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Note 1: Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog
inputs by default when PBADEN is set and digital inputs when PBADEN is cleared.
2: All other pin functions are disabled when ICSP™ or ICD are enabled.
3: This bit is not available on 28-pin devices.
© 2009 Microchip Technology Inc.
DS39932C-page 133
PIC18F46J11 FAMILY
TABLE 9-5:
Pin
PORTB I/O SUMMARY (CONTINUED)
Function
TRIS
Setting
I/O
I/O
Type
RB4
0
O
DIG
LATB<4> data output; not affected by analog input.
1
I
TTL
PORTB<4> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input enabled.(1)
0
O
DIG
Parallel Master Port address.
RB4/PMA1/
KBI0/RP7
PMA1(3)
RB5/PMA0/
KBI1/RP8
KBI0
1
I
TTL
Interrupt-on-change pin.
RP7
1
I
ST
Remappable peripheral pin 7 input.
0
O
DIG
Remappable peripheral pin 7 output.
RB5
0
O
DIG
LATB<5> data output.
1
I
TTL
PORTB<5> data input; weak pull-up when RBPU bit is
cleared.
0
O
DIG
Parallel Master Port address.
PMA0(3)
RB6/KBI2/
PGC/RP9
RB7/KBI3/
PGD/RP10
Description
KBI1
1
I
TTL
Interrupt-on-change pin.
RP8
1
I
ST
Remappable peripheral pin 8 input.
0
O
DIG
Remappable peripheral pin 8 output.
RB6
0
O
DIG
LATB<6> data output.
1
I
TTL
PORTB<6> data input; weak pull-up when RBPU bit is
cleared.
KBI2
1
I
TTL
Interrupt-on-change pin.
PGC
x
I
ST
Serial execution (ICSP™) clock input for ICSP and ICD
operation.(2)
RP9
1
I
ST
Remappable peripheral pin 9 input.
0
O
DIG
Remappable peripheral pin 9 output.
RB7
0
O
DIG
LATB<7> data output.
1
I
TTL
PORTB<7> data input; weak pull-up when RBPU bit is
cleared.
KBI3
1
I
TTL
Interrupt-on-change pin.
PGD
x
O
DIG
Serial execution data output for ICSP and ICD operation.(2)
x
I
ST
Serial execution data input for ICSP and ICD operation.(2)
1
I
ST
Remappable peripheral pin 10 input.
0
O
ST
Remappable peripheral pin 10 output.
RP10
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Note 1: Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog
inputs by default when PBADEN is set and digital inputs when PBADEN is cleared.
2: All other pin functions are disabled when ICSP™ or ICD are enabled.
3: This bit is not available on 28-pin devices.
DS39932C-page 134
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 9-6:
Name
PORTB
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
81
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
81
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
81
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
81
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP
INT3IP
RBIP
81
INTCON
INTCON2
GIE/GIEH PEIE/GIEL
RBPU
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
81
ADCON0
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
81
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.
© 2009 Microchip Technology Inc.
DS39932C-page 135
PIC18F46J11 FAMILY
9.4
PORTC, TRISC and LATC
Registers
PORTC is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for
PORTC.
PORTC is multiplexed with several peripheral functions
(see Table ). The pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for additional information.
Unlike other PORTC pins, RC4 and RC5 do not have
TRISC bits associated with them. As digital ports, they
can only function as digital inputs. If an external transceiver is used, RC4 and RC5 always function as inputs
from the transceiver. If the on-chip transceiver is used,
the data direction is determined by the operation being
performed by the module at that time.
DS39932C-page 136
Note:
On a Power-on Reset, PORTC pins
(except RC2, RC4 and RC5) are configured as digital inputs. RC2 will default as
an analog input (controlled by the
ANCON1 register).
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
EXAMPLE 9-4:
CLRF
PORTC
INITIALIZING PORTC
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTC by
clearing output
data latches
CLRF LATC
Alternate method
to clear output
data latches
MOVLW 0x3F
Value used to
initialize data
direction
MOVWF TRISC
Set RC<5:0> as inputs
RC<7:6> as outputs
MOVLB 0x0F
ANCON register is not in
Access Bank
BSF
ANCON1,PCFG11
;Configure RC2/AN11 as
digital input
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 9-7:
Pin
RC0/T1OSO/
T1CKI/RP11
RC1/T1OSI/
RP12
RC2/AN11/
CTPLS/RP13
RC3/SCK1/
SCL1/RP14
PORTC I/O SUMMARY(1)
Function
TRIS
Setting
I/O
I/O
Type
RC0
1
I
ST
PORTC<0> data input.
0
O
DIG
LATC<0> data output.
T1OSO
x
O
ANA
Timer1 oscillator output; enabled when Timer1 oscillator
enabled. Disables digital I/O.
T1CKI
1
I
ST
Timer1 counter input.
RP11
1
I
ST
Remappable peripheral pin 11 input.
0
O
DIG
Remappable peripheral pin 11 output.
RC1
1
I
ST
PORTC<1> data input.
0
O
DIG
LATC<1> data output.
T1OSI
x
I
ANA
Timer1 oscillator input; enabled when Timer1 oscillator
enabled. Disables digital I/O.
RP12
1
I
ST
0
O
DIG
Remappable peripheral pin 12 output.
1
I
ST
PORTC<2> data input.
RC2
Remappable peripheral pin 12 input.
0
O
DIG
LATC<2> data output.
AN11
1
I
ANA
A/D input channel 11.
CTPLS
0
O
DIG
CTMU pulse generator output.
RP13
1
I
ST
Remappable peripheral pin 13 input.
0
O
DIG
Remappable peripheral pin 13 output.
1
I
ST
PORTC<3> data input.
0
O
DIG
LATC<3> data output.
1
I
0
O
1
I
0
O
RC3
SCK1
SCL1
RP14
RC4/SDI1/
SDA1/RP15
Description
RC4
ST/TTL Parallel Master Port io_addr_in<1>.
DIG
Parallel Master Port address.
I2C™ clock input (MSSP1 module).
I2C/
SMBus
DIG
I2C clock output (MSSP1 module).
1
I
ST
Remappable peripheral pin 14 input.
0
O
DIG
Remappable peripheral pin 14 output.
1
I
ST
PORTC<4> data input.
0
O
DIG
LATC<4> data output.
SDI1
1
I
ST
SPI data input (MSSP1 module).
SDA1
1
I
0
O
DIG
I2C/SMBus.
1
I
ST
Remappable peripheral pin 15 input.
0
O
DIG
Remappable peripheral pin 15 output.
RP15
I2C data input (MSSP1 module).
I2C/
SMBus
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
input/output; I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or
is overridden for this option)
Note 1: Enhanced PWM output is available only on PIC18F4XJ11 devices.
2: This bit is only available on 44-pin devices.
© 2009 Microchip Technology Inc.
DS39932C-page 137
PIC18F46J11 FAMILY
TABLE 9-7:
Pin
PORTC I/O SUMMARY(1) (CONTINUED)
Function
TRIS
Setting
I/O
I/O
Type
RC5
1
I
DIG
0
O
DIG
LATC<5> data output.
0
O
DIG
SPI data output (MSSP1 module).
RC5/SDO1/
RP16
SDO1
RP16
RC6/PMA5/
TX1/CK1/RP17
RC6
(2)
PORTC<5> data input.
1
I
ST
Remappable peripheral pin 16 input.
0
O
DIG
Remappable peripheral pin 16 output.
1
I
ST
PORTC<6> data input.
0
O
DIG
LATC<6> data output.
1
I
0
O
DIG
Parallel Master Port address.
TX1
0
O
DIG
Asynchronous serial transmit data output (EUSART
module); takes priority over port data. User must configure
as output.
CK1
1
I
ST
Synchronous serial clock input (EUSART module).
0
O
DIG
Synchronous serial clock output (EUSART module); takes
priority over port data.
PMA5
RP17
RC7/RX1/DT1/
RP18
Description
RC7
ST/TTL Parallel Master Port io_addr_in<5>.
1
I
ST
Remappable peripheral pin 17 input.
0
O
DIG
Remappable peripheral pin 17 output.
1
I
ST
PORTC<7> data input.
0
O
DIG
LATC<7> data output.
RX1
1
I
ST
Asynchronous serial receive data input (EUSART module).
DT1
1
1
ST
Synchronous serial data input (EUSART module). User
must configure as an input.
0
O
DIG
Synchronous serial data output (EUSART module); takes
priority over port data.
RP18
1
I
ST
Remappable peripheral pin 18 input.
0
O
DIG
Remappable peripheral pin 18 output.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
input/output; I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or
is overridden for this option)
Note 1: Enhanced PWM output is available only on PIC18F4XJ11 devices.
2: This bit is only available on 44-pin devices.
TABLE 9-8:
Name
PORTC
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page:
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
81
LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
81
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
81
DS39932C-page 138
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
9.5
Note:
PORTD, TRISD and LATD
Registers
PORTD is available only in 44-pin devices.
PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
All pins on PORTD are implemented with Schmitt Trigger
input buffers. Each pin is individually configurable as an
input or output.
Note:
On a POR, these pins are configured as
digital inputs.
EXAMPLE 9-5:
CLRF
PORTD
CLRF
LATD
MOVLW 0CFh
MOVWF TRISD
INITIALIZING PORTD
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTD by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RD<3:0> as inputs
RD<5:4> as outputs
RD<7:6> as inputs
Each of the PORTD pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is performed by setting bit, RDPU (PORTE<7>). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disabled on a
POR.
Note that the pull-ups can be used for any set of
features, similar to the pull-ups found on PORTB.
© 2009 Microchip Technology Inc.
DS39932C-page 139
PIC18F46J11 FAMILY
TABLE 9-9:
Pin
PORTD I/O SUMMARY
Function
TRIS
Setting
I/O
I/O
Type
RD0
1
I
ST
PORTD<0> data input.
0
O
DIG
LATD<0> data output.
1
I
0
O
DIG
Parallel Master Port data out.
1
I
I2C/
SMB
I2C™ clock input (MSSP2 module); input type depends on
module setting.
0
O
DIG
I2C™ clock output (MSSP2 module); takes priority over port
data.
RD0/PMD0/
SCL2
PMD0
SCL2
RD1/PMD1/
SDA2
RD1
I
ST
PORTD<1> data input.
0
O
DIG
LATD<1> data output.
1
I
TTL
Parallel Master Port data in.
0
O
DIG
Parallel Master Port data out.
1
I
I2C/
SMB
I2C data input (MSSP2 module); input type depends on
module setting.
0
O
DIG
I2C data output (MSSP2 module); takes priority over port
data.
RD2
1
II
ST
PORTD<2> data input.
0
O
DIG
LATD<2> data output.
PMD2
1
I
TTL
Parallel Master Port data in.
0
O
DIG
Parallel Master Port data out.
1
I
ST
Remappable peripheral pin 19 input.
0
O
DIG
Remappable peripheral pin 19 output.
1
I
DIG
PORTD<3> data input.
0
O
DIG
LATD<3> data output.
1
I
0
O
DIG
Parallel Master Port data out.
1
I
ST
Remappable peripheral pin 20 input.
0
O
DIG
Remappable peripheral pin 20 output.
1
I
ST
PORTD<4> data input.
0
O
DIG
LATD<4> data output.
1
I
TTL
Parallel Master Port data in.
0
O
DIG
Parallel Master Port data out.
1
I
ST
Remappable peripheral pin 21 input.
0
O
DIG
Remappable peripheral pin 21 output.
1
I
ST
PORTD<5> data input.
0
O
DIG
LATD<5> data output.
1
I
TTL
Parallel Master Port data in.
0
O
DIG
Parallel Master Port data out.
1
I
ST
Remappable peripheral pin 22 input.
0
O
DIG
Remappable peripheral pin 22 output.
SDA2
RP19
RD3/PMD3/
RP20
RD3
PMD3
RP20
RD4/PMD4/
RP21
RD4
PMD4
RP21
RD5/PMD5/
RP22
ST/TTL Parallel Master Port data in.
1
PMD1
RD2/PMD2/
RP19
Description
RD5
PMD5
RP22
ST/TTL Parallel Master Port data in.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I2C/SMB = I2C/SMBus
input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
DS39932C-page 140
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 9-9:
PORTD I/O SUMMARY (CONTINUED)
Pin
Function
TRIS
Setting
I/O
I/O
Type
RD6
1
I
ST
PORTD<6> data input.
0
O
DIG
LATD<6> data output.
1
I
TTL
Parallel Master Port data in.
0
O
DIG
Parallel Master Port data out.
1
I
ST
Remappable peripheral pin 23 input.
0
O
DIG
Remappable peripheral pin 23 output.
RD6/PMD6/
RP23
PMD6
RP23
RD7/PMD7/
RP24
RD7
PMD7
RP24
Description
1
I
ST
PORTD<7> data input.
0
O
DIG
LATD<7> data output.
1
I
TTL
Parallel Master Port data in.
0
O
DIG
Parallel Master Port data out.
1
I
ST
Remappable peripheral pin 24 input.
0
O
DIG
Remappable peripheral pin 24 output.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I2C/SMB = I2C/SMBus
input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 9-10:
Name
PORTD(1)
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
86
LATD(1)
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
86
TRISD(1)
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
86
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
Note 1: These registers are not available in 28-pin devices.
© 2009 Microchip Technology Inc.
DS39932C-page 141
PIC18F46J11 FAMILY
9.6
Note:
PORTE, TRISE and LATE
Registers
PORTE is available only in 44-pin devices.
Depending on the particular PIC18F46J11 family
device selected, PORTE is implemented in two
different ways.
For 44-pin devices, PORTE is a 3-bit wide port. Three
pins (RE0/AN5/PMRD, RE1/AN6/PMWR and RE2/
AN7/PMCS) are individually configurable as inputs or
outputs. These pins have Schmitt Trigger input buffers.
When selected as analog inputs, these pins will read as
‘0’s.
The corresponding Data Direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISE bit
(= 0) will make the corresponding PORTE pin an output
(i.e., put the contents of the output latch on the selected
pin).
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
Note:
On a POR, RE<2:0> are configured as
analog inputs.
DS39932C-page 142
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
EXAMPLE 9-6:
CLRF
PORTE
CLRF
LATE
MOVLW
MOVWF
MOVLW
0Ah
ADCON1
03h
MOVWF
TRISE
INITIALIZING PORTE
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTE by
clearing output
data latches
Alternate method
to clear output
data latches
Configure A/D
for digital inputs
Value used to
initialize data
direction
Set RE<0> as inputs
RE<1> as outputs
RE<2> as inputs
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is performed by setting bit, REPU (PORTE<6>). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disabled on a
POR.
Note that the pull-ups can be used for any set of
features, similar to the pull-ups found on PORTB.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 9-11:
Pin
PORTE I/O SUMMARY
Function
TRIS
Setting
I/O
I/O
Type
RE0
1
I
ST
0
O
DIG
LATE<0> data output; not affected by analog input.
1
I
ANA
A/D input channel 5; default input configuration on POR.
RE0/AN5/
PMRD
AN5
PMRD
RE1/AN6/
PMWR
RE1
I
O
PORTE<0> data input; disabled when analog input enabled.
ST/TTL Parallel Master Port io_rd_in.
DIG
Parallel Master Port read strobe.
1
I
ST
PORTE<1> data input; disabled when analog input enabled.
0
O
DIG
LATE<1> data output; not affected by analog input.
AN6
1
I
ANA
A/D input channel 6; default input configuration on POR.
PMWR
1
I
0
O
DIG
Parallel Master Port write strobe.
1
I
ST
PORTE<2> data input; disabled when analog input enabled.
RE2/AN7/
PMCS
RE2
ST/TTL Parallel Master Port io_wr_in.
0
O
DIG
LATE<2> data output; not affected by analog input.
AN7
1
I
ANA
A/D input channel 7; default input configuration on POR.
PMCS
0
O
DIG
Parallel Master Port byte enable.
—
—
P
—
Ground reference for logic and I/O pins.
—
—
P
—
Ground reference for analog modules.
—
—
P
—
Positive supply for peripheral digital logic and I/O pins.
VDDCORE
—
P
—
Positive supply for microcontroller core logic (regulator disabled).
VCAP
—
P
—
External filter capacitor connection (regulator enabled).
—
—
—
Positive supply for analog modules.
VSS1
VSS2
AVSS1
VDD1
VDD2
VDDCORE/VCAP
1
0
Description
AVDD1
AVDD2
P
—
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
I = Input; O = Output; P = Power
TABLE 9-12:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
RDPU(3)
REPU(4)
—
—
—
RE2
LATE
—
—
—
—
—
LATE2
TRISE(1)
—
—
—
—
TRISE2
ANCON0
PCFG7(2)
PCFG4
PCFG3
PCFG2
PORTE(1)
(1)
—
(2)
PCFG6
PCFG5
(2)
Bit 2
Bit 0
Reset
Values
on page
RE1
RE0
86
LATE1
LATE0
86
TRISE1
TRISE0
85
PCFG1
PCFG0
87
Bit 1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: These registers are not available in 28-pin devices.
2: These bits are only available in 44-pin devices.
Note 1: PORTD Pull-up Enable bit
0 = All PORTD pull-ups are disabled
1 = PORTD pull-ups are enabled for any input pad
2: PORTE Pull-up Enable bit
0 = All PORTE pull-ups are disabled
1 = PORTE pull-ups are enabled for any input pad
© 2009 Microchip Technology Inc.
DS39932C-page 143
PIC18F46J11 FAMILY
9.7
Peripheral Pin Select (PPS)
A major challenge in general purpose devices is providing the largest possible set of peripheral features while
minimizing the conflict of features on I/O pins. The
challenge is even greater on low pin count devices
similar to the PIC18F46J11 family. In an application
that needs to use more than one peripheral multiplexed
on single pin, inconvenient workarounds in application
code or a complete redesign may be the only option.
The Peripheral Pin Select (PPS) feature provides an
alternative to these choices by enabling the user’s
peripheral set selection and their placement on a wide
range of I/O pins. By increasing the pinout options
available on a particular device, users can better tailor
the microcontroller to their entire application, rather than
trimming the application to fit the device.
The PPS feature operates over a fixed subset of digital
I/O pins. Users may independently map the input and/
or output of any one of the many digital peripherals to
any one of these I/O pins. PPS is performed in software
and generally does not require the device to be
reprogrammed. Hardware safeguards are included that
prevent accidental or spurious changes to the
peripheral mapping once it has been established.
9.7.1
AVAILABLE PINS
The PPS feature is used with a range of up to 22 pins;
the number of available pins is dependent on the
particular device and its pin count. Pins that support the
PPS feature include the designation “RPn” in their full
pin designation, where “RP” designates a remappable
peripheral and “n” is the remappable pin number. See
Table 1-2 for pinout options in each package offering.
9.7.2
AVAILABLE PERIPHERALS
The peripherals managed by the PPS are all digital
only peripherals. These include general serial communications (UART and SPI), general purpose timer clock
inputs, timer-related peripherals (input capture and
output compare) and external interrupt inputs. Also
included are the outputs of the comparator module,
since these are discrete digital signals.
The PPS module is not applied to I2C, change notification inputs, RTCC alarm outputs or peripherals with
analog inputs. Additionally, the MSSP1 and EUSART1
modules are not routed through the PPS module.
A key difference between pin select and non-pin select
peripherals is that pin select peripherals are not associated with a default I/O pin. The peripheral must
always be assigned to a specific I/O pin before it can be
used. In contrast, non PPS peripherals are always
available on a default pin, assuming that the peripheral
is active and not conflicting with another peripheral.
9.7.2.1
Peripheral Pin Select Function
Priority
When a pin selectable peripheral is active on a given I/O
pin, it takes priority over all other digital I/O and digital
communication peripherals associated with the pin.
Priority is given regardless of the type of peripheral that
is mapped. Pin select peripherals never take priority
over any analog functions associated with the pin.
9.7.3
CONTROLLING PERIPHERAL PIN
SELECT
PPS features are controlled through two sets of Special
Function Registers (SFRs): one to map peripheral
inputs and the other to map outputs. Because they are
separately controlled, a particular peripheral’s input
and output (if the peripheral has both) can be placed on
any selectable function pin without constraint.
The association of a peripheral to a peripheral selectable
pin is handled in two different ways, depending on
whether an input or an output is being mapped.
DS39932C-page 144
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
9.7.3.1
Input Mapping
The inputs of the PPS options are mapped on the basis
of the peripheral; that is, a control register associated
with a peripheral dictates the pin it will be mapped to.
The RPINRx registers are used to configure peripheral
input mapping (see Register 9-6 through Register 9-20).
Each register contains a 5-bit field, which is associated
TABLE 9-13:
with one of the pin selectable peripherals. Programming
a given peripheral’s bit field with an appropriate 5-bit
value maps the RPn pin with that value to that
peripheral. For any given device, the valid range of
values for any of the bit fields corresponds to the
maximum number of peripheral pin selections supported
by the device.
SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1)
Input Name
Function Name
Register
External Interrupt 1
INT1
RPINR1
External Interrupt 2
INT2
RPINR2
External Interrupt 3
INT3
RPINR3
Timer0 External Clock Input
T0CKI
RPINR4
Timer3 External Clock Input
T3CKI
RPINR6
Input Capture 1
CCP1
RPINR7
Input Capture 2
CCP2
RPINR8
Timer1 Gate Input
T1G
RPINR12
Timer3 Gate Input
T3G
RPINR13
EUSART2 Asynchronous Receive/Synchronous
RX2/DT2
RPINR16
Receive
EUSART2 Asynchronous Clock Input
CK2
RPINR17
SPI2 Data Input
SDI2
RPINR21
SPI2 Clock Input
SCK2IN
RPINR22
SPI2 Slave Select Input
SS2IN
RPINR23
PWM Fault Input
FLT0
RPINR24
Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.
© 2009 Microchip Technology Inc.
Configuration
Bits
INTR1R<4:0>
INTR2R<4:0>
INTR3R<4:0>
T0CKR<4:0>
T3CKR<4:0>
IC1R<4:0>
IC2R<4:0>
T1GR<4:0>
T3GR<4:0>
RX2DT2R<4:0>
CK2R<4:0>
SDI2R<4:0>
SCK2R<4:0>
SS2R<4:0>
OCFAR<4:0>
DS39932C-page 145
PIC18F46J11 FAMILY
9.7.3.2
Output Mapping
In contrast to inputs, the outputs of the PPS options are
mapped on the basis of the pin. In this case, a control
register associated with a particular pin dictates the
peripheral output to be mapped. The RPORx registers
are used to control output mapping. The value of the bit
field corresponds to one of the peripherals and that
peripheral’s output is mapped to the pin (see Table 9-14).
TABLE 9-14:
Because of the mapping technique, the list of
peripherals for output mapping also includes a null
value of ‘00000’. This permits any given pin to remain
disconnected from the output of any of the pin
selectable peripherals.
SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT)
Function
Output Function
Number(1)
Output Name
NULL
0
NULL(2)
C1OUT
1
Comparator 1 Output
C2OUT
2
Comparator 2 Output
TX2/CK2
5
EUSART2 Asynchronous Transmit/Asynchronous Clock Output
DT2
6
EUSART2 Synchronous Transmit
SDO2
9
SPI2 Data Output
SCK2
10
SPI2 Clock Output
SSDMA
12
SPI DMA Slave Select
ULPOUT
13
Ultra Low-Power Wake-up Event
CCP1/P1A
14
ECCP1 Compare or PWM Output Channel A
P1B
15
ECCP1 Enhanced PWM Output, Channel B
P1C
16
ECCP1 Enhanced PWM Output, Channel C
P1D
17
ECCP1 Enhanced PWM Output, Channel D
CCP2/P2A
18
ECCP2 Compare or PWM Output
P2B
19
ECCP2 Enhanced PWM Output, Channel B
P2C
20
ECCP2 Enhanced PWM Output, Channel C
P2D
21
ECCP2 Enhanced PWM Output, Channel D
Note 1: Value assigned to the RPn<4:0> pins corresponds to the peripheral output function number.
2: The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function.
DS39932C-page 146
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
9.7.3.3
Mapping Limitations
The control schema of the PPS is extremely flexible.
Other than systematic blocks that prevent signal contention caused by two physical pins being configured
as the same functional input or two functional outputs
configured as the same pin, there are no hardware
enforced lock outs. The flexibility extends to the point of
allowing a single input to drive multiple peripherals or a
single functional output to drive multiple output pins.
9.7.4
CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC18F devices include three features to
prevent alterations to the peripheral map:
• Control register lock sequence
• Continuous state monitoring
• Configuration bit remapping lock
9.7.4.1
Control Register Lock
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes will
appear to execute normally, but the contents of the
registers will remain unchanged. To change these registers, they must be unlocked in hardware. The register
lock is controlled by the IOLOCK bit (PPSCON<0>).
Setting IOLOCK prevents writes to the control
registers; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence
must be executed:
1.
2.
3.
Write 55h to EECON2<7:0>.
Write AAh to EECON2<7:0>.
Clear (or set) IOLOCK as a single operation.
IOLOCK remains in one state until changed. This
allows all of the PPS registers to be configured with a
single unlock sequence followed by an update to all
control registers, then locked with a second lock
sequence.
9.7.4.2
Continuous State Monitoring
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a Configuration Mismatch Reset will
be triggered.
© 2009 Microchip Technology Inc.
9.7.4.3
Configuration Bit Pin Select Lock
As an additional level of safety, the device can be configured to prevent more than one write session to the
RPINRx and RPORx registers. The IOL1WAY
(CONFIG3H<0>) Configuration bit blocks the IOLOCK
bit from being cleared after it has been set once. If
IOLOCK remains set, the register unlock procedure will
not execute and the PPS control registers cannot be
written to. The only way to clear the bit and re-enable
peripheral remapping is to perform a device Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows users unlimited access (with the
proper use of the unlock sequence) to the PPS
registers.
9.7.5
CONSIDERATIONS FOR
PERIPHERAL PIN SELECTION
The ability to control peripheral pin selection introduces
several considerations into application design that
could be overlooked. This is particularly true for several
common peripherals that are available only as
remappable peripherals.
The main consideration is that the PPS is not available
on default pins in the device’s default (Reset) state.
Since all RPINRx registers reset to ‘11111’ and all
RPORx registers reset to ‘00000’, all PPS inputs are
tied to RP31 and all PPS outputs are disconnected.
Note:
In tying PPS inputs to RP31, RP31 does
not have to exist on a device for the
registers to be reset to it.
This situation requires the user to initialize the device
with the proper peripheral configuration before any
other application code is executed. Since the IOLOCK
bit resets in the unlocked state, it is not necessary to
execute the unlock sequence after the device has
come out of Reset.
For application safety, however, it is best to set
IOLOCK and lock the configuration after writing to the
control registers.
Because the unlock sequence is timing critical, it must
be executed as an assembly language routine. If the
bulk of the application is written in C or another highlevel language, the unlock sequence should be
performed by writing in-line assembly.
DS39932C-page 147
PIC18F46J11 FAMILY
Choosing the configuration requires the review of all
PPSs and their pin assignments, especially those that
will not be used in the application. In all cases, unused
pin selectable peripherals should be disabled completely. Unused peripherals should have their inputs
assigned to an unused RPn pin function. I/O pins with
unused RPn functions should be configured with the
null peripheral output.
The assignment of a peripheral to a particular pin does
not automatically perform any other configuration of the
pin’s I/O circuitry. In theory, this means adding a pin
selectable output to a pin may mean inadvertently driving an existing peripheral input when the output is
driven. Users must be familiar with the behavior of
other fixed peripherals that share a remappable pin and
know when to enable or disable them. To be safe, fixed
digital peripherals that share the same pin should be
disabled when not in use.
Along these lines, configuring a remappable pin for a
specific peripheral does not automatically turn that
feature on. The peripheral must be specifically configured for operation and enabled, as if it were tied to a
fixed pin. Where this happens in the application code
(immediately following device Reset and peripheral
configuration or inside the main application routine)
depends on the peripheral and its use in the
application.
A final consideration is that the PPS functions neither
override analog inputs nor reconfigure pins with analog
functions for digital I/O. If a pin is configured as an
analog input on device Reset, it must be explicitly
reconfigured as digital I/O when used with a PPS.
Example 9-7 provides a configuration for bidirectional
communication with flow control using EUSART2. The
following input and output functions are used:
• Input Function RX2
• Output Function TX2
EXAMPLE 9-7:
CONFIGURING EUSART2
INPUT AND OUTPUT
FUNCTIONS
//*************************************
// Unlock Registers
//*************************************
_asm
; PPS registers are in BANK 14
MOVLB
0x0E
MOVLW
0x55
MOVWF
EECON2, 0
MOVLW
0xAA
MOVWF
EECON2, 0
; PPS Write Protect off
BCF
PPSCON, IOLOCK, BANKED
_endasm
//***************************
// Configure Input Functions
// (See Table 9-13)
//***************************
//***************************
// Assign RX2 To Pin RP0
//***************************
_asm
MOVLW
0x00
MOVWF
RPINR16, BANKED
_endasm
//***************************
// Configure Output Functions
// (See Table 9-14)
//***************************
//***************************
// Assign TX2 To Pin RP1
//***************************
_asm
MOVLW
0x05
MOVWF
RPOR1, BANKED
_endasm
//*************************************
// Lock Registers
//*************************************
_asm
MOVLW
0x55
MOVWF
EECON2, 0
MOVLW
0xAA
MOVWF
EECON2, 0
; PPS Write Protected
BSF
PPSCON, IOLOCK, BANKED
_endasm
Note:
DS39932C-page 148
If the Configuration bit, IOL1WAY = 1,
once the IOLOCK bit is set, it cannot be
cleared, preventing any future RP register
changes. The IOLOCK bit is cleared back
to ‘0’ on any device Reset.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
9.7.6
PERIPHERAL PIN SELECT
REGISTERS
Note:
The PIC18F46J11 family of devices implements a total
of 37 registers for remappable peripheral configuration
of 44-pin devices. The 28-pin devices have 31 registers
for remappable peripheral configuration.
REGISTER 9-5:
Input and output register values can only
be changed if PPS<IOLOCK> = 0. See
Example 9-7 for a specific command
sequence.
PPSCON: PERIPHERAL PIN SELECT INPUT REGISTER 0 (BANKED EFFh)(1)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
IOLOCK
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-1
Unimplemented: Read as ‘0’
bit 0
IOLOCK: I/O Lock Enable bit
1 = I/O lock active, RPORx and RPINRx registers are write-protected
0 = I/O lock not active, pin configurations can be changed
Note 1:
x = Bit is unknown
Register values can only be changed if PPSCON<IOLOCK> = 0.
© 2009 Microchip Technology Inc.
DS39932C-page 149
PIC18F46J11 FAMILY
REGISTER 9-6:
RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 (BANKED EE7h)
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
INTR1R4
INTR1R3
INTR1R2
INTR1R1
INTR1R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
INTR1R<4:0>: Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bits
REGISTER 9-7:
RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 (BANKED EE8h)
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
INTR2R4
INTR2R3
INTR2R2
INTR2R1
INTR2R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
INTR2R<4:0>: Assign External Interrupt 2 (INT2) to the Corresponding RPn pin bits
REGISTER 9-8:
RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 (BANKED EE9h)
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
INTR3R4
INTR3R3
INTR3R2
INTR3R1
INTR3R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
INTR3R<4:0>: Assign External Interrupt 3 (INT3) to the Corresponding RPn Pin bits
DS39932C-page 150
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 9-9:
RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 (BANKED EEAh)
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
T0CKR4
T0CKR3
T0CKR2
T0CKR1
T0CKR0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
T0CKR<4:0>: Timer0 External Clock Input (T0CKI) to the Corresponding RPn Pin bits
REGISTER 9-10:
RPINR6: PERIPHERAL PIN SELECT INPUT REGISTER 6 (BANKED EECh)
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
T3CKR4
T3CKR3
T3CKR2
T3CKR1
T3CKR0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
T3CKR<4:0>: Timer 3 External Clock Input (T3CKI) to the Corresponding RPn Pin bits
REGISTER 9-11:
RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 (BANKED EEDh)
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
IC1R4
IC1R3
IC1R2
IC1R1
IC1R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
IC1R<4:0>: Assign Input Capture 1 (ECCP1) to the Corresponding RPn Pin bits
© 2009 Microchip Technology Inc.
DS39932C-page 151
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REGISTER 9-12:
RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 (BANKED EEEh)
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
IC2R4
IC2R3
IC2R2
IC2R1
IC2R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
IC2R<4:0>: Assign Input Capture 2 (ECCP2) to the Corresponding RPn Pin bits
REGISTER 9-13:
RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12 (BANKED EF2h)
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
T1GR4
T1GR3
T1GR2
T1GR1
T1GR0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
T1GR<4:0>: Timer1 Gate Input (T1G) to the Corresponding RPn Pin bits
REGISTER 9-14:
RPINR13: PERIPHERAL PIN SELECT INPUT REGISTER 13 (BANKED EF3h)
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
T3GR4
T3GR3
T3GR2
T3GR1
T3GR0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
T3GR<4:0>: Timer3 Gate Input (T3G) to the Corresponding RPn Pin bits
DS39932C-page 152
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 9-15:
RPINR16: PERIPHERAL PIN SELECT INPUT REGISTER 16 (BANKED EF6h)
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
RX2DT2R4
RX2DT2R3
RX2DT2R2
RX2DT2R1
RX2DT2R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RX2DT2R<4:0>: EUSART2 Synchronous/Asynchronous Receive (RX2/DT2) to the Corresponding
RPn Pin bits
REGISTER 9-16:
RPINR17: PERIPHERAL PIN SELECT INPUT REGISTER 17 (BANKED EF7h)
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
CK2R4
CK2R3
CK2R2
CK2R1
CK2R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
CK2R<4:0>: EUSART2 Clock Input (CK2) to the Corresponding RPn Pin bits
REGISTER 9-17:
RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 (BANKED EFBh)
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
SDI2R4
SDI2R3
SDI2R2
SDI2R1
SDI2R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
SDI2R<4:0>: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits
© 2009 Microchip Technology Inc.
DS39932C-page 153
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REGISTER 9-18:
RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 (BANKED EFCh)
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
SCK2R4
SCK2R3
SCK2R2
SCK2R1
SCK2R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
SCK2R<4:0>: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits
REGISTER 9-19:
RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 (BANKED EFDh)
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
SS2R4
SS2R3
SS2R2
SS2R1
SS2R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
SS2R<4:0>: Assign SPI2 Slave Select Input (SS2IN) to the Corresponding RPn Pin bits
REGISTER 9-20:
RPINR24: PERIPHERAL PIN SELECT INPUT REGISTER 24 (BANKED EFEh)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
OCFAR4
OCFAR3
OCFAR2
OCFAR1
OCFAR0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
OCFAR<4:0>: Assign PWM Fault Input (FLT0) to the Corresponding RPn Pin bits
DS39932C-page 154
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 9-21:
RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 (BANKED EC6h)(1)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP0R4
RP0R3
RP0R2
RP0R1
RP0R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP0R<4:0>: Peripheral Output Function is Assigned to RP0 Output Pin bits
(see Table 9-14 for peripheral function numbers)
Note 1:
Register values can be changed only if PPSCON<IOLOCK> = 0.
REGISTER 9-22:
RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 (BANKED EC7h)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP1R4
RP1R3
RP1R2
RP1R1
RP1R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP1R<4:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits
(see Table 9-14 for peripheral function numbers)
REGISTER 9-23:
RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 (BANKED EC8h)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP2R4
RP2R3
RP2R2
RP2R1
RP2R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits
(see Table 9-14 for peripheral function numbers)
© 2009 Microchip Technology Inc.
DS39932C-page 155
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REGISTER 9-24:
RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 (BANKED EC9h)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP3R4
RP3R3
RP3R2
RP3R1
RP3R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits
(see Table 9-14 for peripheral function numbers)
REGISTER 9-25:
RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 (BANKED ECAh)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP4R4
RP4R3
RP4R2
RP4R1
RP4R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP4R<4:0>: Peripheral Output Function is Assigned to RP4 Output Pin bits
(see Table 9-14 for peripheral function numbers)
REGISTER 9-26:
RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 (BANKED ECBh)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP5R4
RP5R3
RP5R2
RP5R1
RP5R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP5R<4:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits
(see Table 9-14 for peripheral function numbers)
DS39932C-page 156
© 2009 Microchip Technology Inc.
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REGISTER 9-27:
RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 (BANKED ECCh)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP6R4
RP6R3
RP6R2
RP6R1
RP6R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits
(see Table 9-14 for peripheral function numbers)
REGISTER 9-28:
RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 (BANKED ECDh)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP7R4
RP7R3
RP7R2
RP7R1
RP7R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits
(see Table 9-14 for peripheral function numbers)
REGISTER 9-29:
RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 (BANKED ECEh)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP8R4
RP8R3
RP8R2
RP8R1
RP8R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP8R<4:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits
(see Table 9-14 for peripheral function numbers)
© 2009 Microchip Technology Inc.
DS39932C-page 157
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REGISTER 9-30:
RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 (BANKED ECFh)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP9R4
RP9R3
RP9R2
RP9R1
RP9R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP9R<4:0>: Peripheral Output Function is Assigned to RP9 Output Pin bits
(see Table 9-14 for peripheral function numbers)
REGISTER 9-31:
RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 (BANKED ED0h)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP10R4
RP10R3
RP10R2
RP10R1
RP10R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits
(see Table 9-14 for peripheral function numbers)
REGISTER 9-32:
RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11 (BANKED ED1h)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP11R4
RP11R3
RP11R2
RP11R1
RP11R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits
(see Table 9-14 for peripheral function numbers)
DS39932C-page 158
© 2009 Microchip Technology Inc.
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REGISTER 9-33:
RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 (BANKED ED2h)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP12R4
RP12R3
RP12R2
RP12R1
RP12R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP12R<4:0>: Peripheral Output Function is Assigned to RP12 Output Pin bits
(see Table 9-14 for peripheral function numbers)
REGISTER 9-34:
RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13 (BANKED ED3h)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP13R4
RP13R3
RP13R2
RP13R1
RP13R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP13R<4:0>: Peripheral Output Function is Assigned to RP13 Output Pin bits
(see Table 9-14 for peripheral function numbers)
REGISTER 9-35:
RPOR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14 (BANKED ED4h)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP14R4
RP14R3
RP14R2
RP14R1
RP14R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits
(see Table 9-14 for peripheral function numbers)
© 2009 Microchip Technology Inc.
DS39932C-page 159
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REGISTER 9-36:
RPOR15: PERIPHERAL PIN SELECT OUTPUT REGISTER 15 (BANKED ED5h)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP15R4
RP15R3
RP15R2
RP15R1
RP15R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits
(see Table 9-14 for peripheral function numbers)
REGISTER 9-37:
RPOR16: PERIPHERAL PIN SELECT OUTPUT REGISTER 16 (BANKED ED6h)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP16R4
RP16R3
RP16R2
RP16R1
RP16R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP16R<4:0>: Peripheral Output Function is Assigned to RP16 Output Pin bits
(see Table 9-14 for peripheral function numbers)
REGISTER 9-38:
RPOR17: PERIPHERAL PIN SELECT OUTPUT REGISTER 17 (BANKED ED7h)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP17R4
RP17R3
RP17R2
RP17R1
RP17R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP17R<4:0>: Peripheral Output Function is Assigned to RP17 Output Pin bits
(see Table 9-14 for peripheral function numbers)
DS39932C-page 160
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 9-39:
RPOR18: PERIPHERAL PIN SELECT OUTPUT REGISTER 18 (BANKED ED8h)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP18R4
RP18R3
RP18R2
RP18R1
RP18R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP18R<4:0>: Peripheral Output Function is Assigned to RP18 Output Pin bits
(see Table 9-14 for peripheral function numbers)
REGISTER 9-40:
RPOR19: PERIPHERAL PIN SELECT OUTPUT REGISTER 19 (BANKED ED9h)(1)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP19R4
RP19R3
RP19R2
RP19R1
RP19R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP19R<4:0>: Peripheral Output Function is Assigned to RP19 Output Pin bits
(see Table 9-14 for peripheral function numbers)
Note 1:
RP19 pins are not available on 28-pin devices.
REGISTER 9-41:
RPOR20: PERIPHERAL PIN SELECT OUTPUT REGISTER 20 (BANKED EDAh)(1)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP20R4
RP20R3
RP20R2
RP20R1
RP20R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP20R<4:0>: Peripheral Output Function is Assigned to RP20 Output Pin bits
(see Table 9-14 for peripheral function numbers)
Note 1:
RP20 pins are not available on 28-pin devices.
© 2009 Microchip Technology Inc.
DS39932C-page 161
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REGISTER 9-42:
RPOR21: PERIPHERAL PIN SELECT OUTPUT REGISTER 21 (BANKED EDBh)(1)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP21R4
RP21R3
RP21R2
RP21R1
RP21R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP21R<4:0>: Peripheral Output Function is Assigned to RP21 Output Pin bits
(see Table 9-14 for peripheral function numbers)
Note 1:
RP21 pins are not available on 28-pin devices.
REGISTER 9-43:
RPOR22: PERIPHERAL PIN SELECT OUTPUT REGISTER 22 (BANKED EDCh)(1)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP22R4
RP22R3
RP22R2
RP22R1
RP22R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP22R<4:0>: Peripheral Output Function is Assigned to RP22 Output Pin bits
(see Table 9-14 for peripheral function numbers)
Note 1:
RP22 pins are not available on 28-pin devices.
REGISTER 9-44:
RPOR23: PERIPHERAL PIN SELECT OUTPUT REGISTER 23 (BANKED EDDh)(1)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP23R4
RP23R3
RP23R2
RP23R1
RP23R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP23R<4:0>: Peripheral Output Function is Assigned to RP23 Output Pin bits
(see Table 9-14 for peripheral function numbers)
Note 1:
RP23 pins are not available on 28-pin devices.
DS39932C-page 162
© 2009 Microchip Technology Inc.
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REGISTER 9-45:
RPOR24: PERIPHERAL PIN SELECT OUTPUT REGISTER 24 (BANKED EDEh)(1)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP24R4
RP24R3
RP24R2
RP24R1
RP24R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits
(see Table 9-14 for peripheral function numbers)
Note 1:
RP24 pins are not available on 28-pin devices.
© 2009 Microchip Technology Inc.
DS39932C-page 163
PIC18F46J11 FAMILY
NOTES:
DS39932C-page 164
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
10.0
PARALLEL MASTER PORT
(PMP)
The Parallel Master Port module (PMP) is an 8-bit
parallel I/O module, specifically designed to communicate with a wide variety of parallel devices, such as
communication peripherals, LCDs, external memory
devices and microcontrollers. Because the interface to
parallel peripherals varies significantly, the PMP is
highly configurable. The PMP module can be
configured to serve as either a PMP or as a Parallel
Slave Port (PSP).
FIGURE 10-1:
Key features of the PMP module are:
• Up to 16 bits of Addressing when Using
Data/Address Multiplexing
• Up to 8 Programmable Address Lines
• One Chip Select Line
• Programmable Strobe Options:
- Individual Read and Write Strobes or;
- Read/Write Strobe with Enable Strobe
• Address Auto-Increment/Auto-Decrement
• Programmable Address/Data Multiplexing
• Programmable Polarity on Control Signals
• Legacy Parallel Slave Port Support
• Enhanced Parallel Slave Support:
- Address Support
- 4-Byte Deep, Auto-Incrementing Buffer
• Programmable Wait States
• Selectable Input Voltage Levels
PMP MODULE OVERVIEW
Address Bus
Data Bus
PIC18
Parallel Master Port
PMA<0>
PMALL
Control Lines
PMA<1>
PMALH
Up to 8-Bit Address
EEPROM
PMA<7:2>
PMCS
PMBE
PMRD
PMRD/PMWR
Microcontroller
LCD
FIFO
Buffer
PMWR
PMENB
PMD<7:0>
PMA<7:0>
PMA<15:8>
© 2009 Microchip Technology Inc.
8-Bit Data
DS39932C-page 165
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10.1
Module Registers
The
PMCON
registers
(Register 10-1
and
Register 10-2) control basic module operations, including turning the module on or off. They also configure
address multiplexing and control strobe configuration.
The PMP module has a total of 14 Special Function
Registers (SFRs) for its operation, plus one additional
register to set configuration options. Of these, eight
registers are used for control and six are used for PMP
data transfer.
10.1.1
The PMMODE registers (Register 10-3 and
Register 10-4) configure the various Master and Slave
modes, the data width and interrupt generation.
CONTROL REGISTERS
The PMEH and PMEL registers (Register 10-5 and
Register 10-6) configure the module’s operation at the
hardware (I/O pin) level.
The eight PMP Control registers are:
• PMCONH and PMCONL
• PMEH and PMEL
The
PMSTAT
registers
(Register 10-5
and
Register 10-6) provide status flags for the module’s
input and output buffers, depending on the operating
mode.
REGISTER 10-1:
PMCONH: PARALLEL PORT CONTROL REGISTER HIGH BYTE (BANKED F5Fh)(1)
• PMMODEH and PMMODEL
• PMSTATL and PMSTATH
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMPEN
—
PSIDL
ADRMUX1
ADRMUX0
PTBEEN
PTWREN
PTRDEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PMPEN: Parallel Master Port Enable bit
1 = PMP enabled
0 = PMP disabled, no off-chip access performed
bit 6
Unimplemented: Read as ‘0’
bit 5
PSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 4-3
ADRMUX<1:0>: Address/Data Multiplexing Selection bits
11 = Reserved
10 = All 16 bits of address are multiplexed on PMD<7:0> pins
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins (only eight bits of address are
available in this mode)
00 = Address and data appear on separate pins (only eight bits of address are available in this mode)
bit 2
PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode)
1 = PMBE port enabled
0 = PMBE port disabled
bit 1
PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port enabled
0 = PMWR/PMENB port disabled
bit 0
PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port enabled
0 = PMRD/PMWR port disabled
Note 1:
This register is only available in 44-pin devices.
DS39932C-page 166
© 2009 Microchip Technology Inc.
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REGISTER 10-2:
PMCONL: PARALLEL PORT CONTROL REGISTER LOW BYTE (BANKED F5Eh)(1)
R/W-0
R/W-0
R/W-0(2)
U-0
R/W-0(2)
R/W-0
R/W-0
R/W-0
CSF1
CSF0
ALP
—
CS1P
BEP
WRSP
RDSP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
CSF<1:0>: Chip Select Function bits
11 = Reserved
10 = Chip select function is enabled and PMCS1 acts as chip select (in Master mode). Up to
13 address bits only can be generated.
01 = Reserved
00 = Chip select function is disabled (in Master mode). All 16 address bits can be generated.
bit 5
ALP: Address Latch Polarity bit(2)
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
bit 4
Unimplemented: Maintain as ‘0’
bit 3
CS1P: Chip Select Polarity bit(2)
1 = Active-high (PMCS)
0 = Active-low (PMCS)
bit 2
BEP: Byte Enable Polarity bit
1 = Byte enable active-high (PMBE)
0 = Byte enable active-low (PMBE)
bit 1
WRSP: Write Strobe Polarity bit
For Slave modes and Master Mode 2 (PMMODEH<1:0> = 00,01,10):
1 = Write strobe active-high (PMWR)
0 = Write strobe active-low (PMWR)
For Master Mode 1 (PMMODEH<1:0> = 11):
1 = Enable strobe active-high (PMENB)
0 = Enable strobe active-low (PMENB)
bit 0
RDSP: Read Strobe Polarity bit
For Slave modes and Master Mode 2 (PMMODEH<1:0> = 00,01,10):
1 = Read strobe active-high (PMRD)
0 = Read strobe active-low (PMRD)
For Master Mode 1 (PMMODEH<1:0> = 11):
1 = Read/write strobe active-high (PMRD/PMWR)
0 = Read/write strobe active-low (PMRD/PMWR)
Note 1:
2:
This register is only available in 44-pin devices.
These bits have no effect when their corresponding pins are used as address lines.
© 2009 Microchip Technology Inc.
DS39932C-page 167
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REGISTER 10-3:
PMMODEH: PARALLEL PORT MODE REGISTER HIGH BYTE (BANKED F5Dh)(1)
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUSY
IRQM1
IRQM0
INCM1
INCM0
MODE16
MODE1
MODE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
BUSY: Busy bit (Master mode only)
1 = Port is busy
0 = Port is not busy
bit 6-5
IRQM<1:0>: Interrupt Request Mode bits
11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only)
10 = No interrupt generated, processor stall activated
01 = Interrupt generated at the end of the read/write cycle
00 = No interrupt generated
bit 4-3
INCM<1:0>: Increment Mode bits
11 = PSP read and write buffers auto-increment (Legacy PSP mode only)
10 = Decrement ADDR<15,13:0> by 1 every read/write cycle
01 = Increment ADDR<15,13:0> by 1 every read/write cycle
00 = No increment or decrement of address
bit 2
MODE16: 8/16-Bit Mode bit
1 = 16-bit mode: Data register is 16 bits, a read or write to the Data register invokes two 8-bit transfers
0 = 8-bit mode: Data register is 8 bits, a read or write to the Data register invokes one 8-bit transfer
bit 1-0
MODE<1:0>: Parallel Port Mode Select bits
11 = Master Mode 1 (PMCS, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>)
10 = Master Mode 2 (PMCS, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)
01 = Enhanced PSP, control signals (PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0>)
00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD<7:0>)
Note 1:
This register is only available in 44-pin devices.
DS39932C-page 168
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 10-4:
R/W-0
WAITB1
PMMODEL: PARALLEL PORT MODE REGISTER LOW BYTE (BANKED F5Ch)(1)
R/W-0
(2)
R/W-0
(2)
WAITB0
WAITM3
R/W-0
WAITM2
R/W-0
WAITM1
R/W-0
WAITM0
R/W-0
WAITE1
(2)
R/W-0
WAITE0(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
WAITB<1:0>: Data Setup to Read/Write Wait State Configuration bits(2)
11 = Data wait of 4 TCY; multiplexed address phase of 4 TCY
10 = Data wait of 3 TCY; multiplexed address phase of 3 TCY
01 = Data wait of 2 TCY; multiplexed address phase of 2 TCY
00 = Data wait of 1 TCY; multiplexed address phase of 1 TCY
bit 5-2
WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits
1111 = Wait of additional 15 TCY
.
.
.
0001 = Wait of additional 1 TCY
0000 = No additional Wait cycles (operation forced into one TCY)
bit 1-0
WAITE<1:0>: Data Hold After Strobe Wait State Configuration bits(2)
11 = Wait of 4 TCY
10 = Wait of 3 TCY
01 = Wait of 2 TCY
00 = Wait of 1 TCY
Note 1:
2:
x = Bit is unknown
This register is only available in 44-pin devices.
WAITBx and WAITEx bits are ignored whenever WAITM<3:0> = 0000.
© 2009 Microchip Technology Inc.
DS39932C-page 169
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REGISTER 10-5:
PMEH: PARALLEL PORT ENABLE REGISTER HIGH BYTE (BANKED F57h)(1)
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
—
PTEN14
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6
PTEN14: PMCS1 Port Enable bit
1 = PMCS1 chip select line
0 = PMCS1 functions as port I/O
bit 5-0
Unimplemented: Read as ‘0’
Note 1:
x = Bit is unknown
This register is only available in 44-pin devices.
REGISTER 10-6:
PMEL: PARALLEL PORT ENABLE REGISTER LOW BYTE (BANKED F56h)(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTEN7
PTEN6
PTEN5
PTEN4
PTEN3
PTEN2
PTEN1
PTEN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
PTEN<7:2>: PMP Address Port Enable bits
1 = PMA<7:2> function as PMP address lines
0 = PMA<7:2> function as port I/O
bit 1-0
PTEN<1:0>: PMALH/PMALL Strobe Enable bits
1 = PMA<1:0> function as either PMA<1:0> or PMALH and PMALL
0 = PMA<1:0> pads functions as port I/O
Note 1:
x = Bit is unknown
This register is only available in 44-pin devices.
DS39932C-page 170
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 10-7:
PMSTATH: PARALLEL PORT STATUS REGISTER HIGH BYTE (BANKED F55h)(1)
R-0
R/W-0
U-0
U-0
R-0
R-0
R-0
R-0
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IBF: Input Buffer Full Status bit
1 = All writable input buffer registers are full
0 = Some or all of the writable input buffer registers are empty
bit 6
IBOV: Input Buffer Overflow Status bit
1 = A write attempt to a full input byte register occurred (must be cleared in software)
0 = No overflow occurred
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
IB3F:IB0F: Input Buffer x Status Full bits
1 = Input buffer contains data that has not been read (reading buffer will clear this bit)
0 = Input buffer does not contain any unread data
Note 1:
This register is only available in 44-pin devices.
REGISTER 10-8:
PMSTATL: PARALLEL PORT STATUS REGISTER LOW BYTE (BANKED F54h)(1)
R-1
R/W-0
U-0
U-0
R-1
R-1
R-1
R-1
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
OBE: Output Buffer Empty Status bit
1 = All readable output buffer registers are empty
0 = Some or all of the readable output buffer registers are full
bit 6
OBUF: Output Buffer Underflow Status bit
1 = A read occurred from an empty output byte register (must be cleared in software)
0 = No underflow occurred
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
OB3E:OB0E: Output Buffer x Status Empty bits
1 = Output buffer is empty (writing data to the buffer will clear this bit)
0 = Output buffer contains data that has not been transmitted
Note 1:
This register is only available in 44-pin devices.
© 2009 Microchip Technology Inc.
DS39932C-page 171
PIC18F46J11 FAMILY
10.1.2
DATA REGISTERS
The PMP module uses eight registers for transferring
data into and out of the microcontroller. They are
arranged as four pairs to allow the option of 16-bit data
operations:
•
•
•
•
PMDIN1H and PMDIN1L
PMDIN2H and PMDIN2L
PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L
PMDOUT2H and PMDOUT2L
The PMDIN1 register is used for incoming data in Slave
modes and both input and output data in Master
modes. The PMDIN2 register is used for buffering input
data in select Slave modes.
The PMADDR/PMDOUT1 registers are actually a
single register pair; the name and function are dictated
by the module’s operating mode. In Master modes, the
registers function as the PMADDRH and PMADDRL
registers and contain the address of any incoming or
outgoing data. In Slave modes, the registers function
as PMDOUT1H and PMDOUT1L and are used for
outgoing data.
DS39932C-page 172
PMADDRH differs from PMADDRL in that it can also
have limited PMP control functions. When the module is
operating in select Master mode configurations, the
upper two bits of the register can be used to determine
the operation of chip select signals. If these are not
used, PMADDR simply functions to hold the upper 8 bits
of the address. Register 10-9 provides the function of
the individual bits in PMADDRH.
The PMDOUT2H and PMDOUT2L registers are only
used in Buffered Slave modes and serve as a buffer for
outgoing data.
10.1.3
PAD CONFIGURATION CONTROL
REGISTER
In addition to the module level configuration options,
the PMP module can also be configured at the I/O pin
for electrical operation. This option allows users to
select either the normal Schmitt Trigger input buffer on
digital I/O pins shared with the PMP, or use TTL level
compatible buffers instead. Buffer configuration is
controlled by the PMPTTL bit in the PADCFG1 register.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 10-9:
PMADDRH: PARALLEL PORT ADDRESS REGISTER HIGH BYTE –
MASTER MODES ONLY (ACCESS F6Fh)(1)
R/W-0
R/W-0
—
CS1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Parallel Master Port Address High Byte<13:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6
CS1: Chip Select bit
If PMCON<7:6> = 10:
1 = Chip select is active
0 = Chip select is inactive
If PMCON<7:6> = 11 or 00:
Bit functions as ADDR<14>.
bit 5-0
Parallel Master Port Address: High Byte<13:8> bits
Note 1:
r = Reserved
x = Bit is unknown
In Enhanced Slave mode, PMADDRH functions as PMDOUT1H, one of the Output Data Buffer registers.
REGISTER 10-10: PMADDRL: PARALLEL PORT ADDRESS REGISTER LOW BYTE –
MASTER MODES ONLY (ACCESS F6Eh)(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Parallel Master Port Address Low Byte<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
r = Reserved
x = Bit is unknown
Parallel Master Port Address: Low Byte<7:0> bits
In Enhanced Slave mode, PMADDRL functions as PMDOUT1L, one of the Output Data Buffer registers.
© 2009 Microchip Technology Inc.
DS39932C-page 173
PIC18F46J11 FAMILY
10.2
Slave Port Modes
The primary mode of operation for the module is
configured using the MODE<1:0> bits in the
PMMODEH register. The setting affects whether the
module acts as a slave or a master, and it determines
the usage of the control pins.
10.2.1
LEGACY MODE (PSP)
In Legacy mode (PMMODEH<1:0> = 00 and
PMPEN = 1), the module is configured as a Parallel
Slave Port (PSP) with the associated enabled module
FIGURE 10-2:
pins dedicated to the module. In this mode, an external
device, such as another microcontroller or microprocessor, can asynchronously read and write data
using the 8-bit data bus (PMD<7:0>), the read (PMRD),
write (PMWR) and chip select (PMCS1) inputs. It acts
as a slave on the bus and responds to the read/write
control signals.
Figure 10-2 displays the connection of the PSP.
When chip select is active and a write strobe occurs
(PMCS = 1 and PMWR = 1), the data from
PMD<7:0> is captured into the PMDIN1L register.
LEGACY PARALLEL SLAVE PORT EXAMPLE
Master
PIC18 Slave
PMD<7:0>
DS39932C-page 174
PMD<7:0>
PMCS1
PMCS
PMRD
PMRD
PMWR
PMWR
Address Bus
Data Bus
Control Lines
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
10.2.2
WRITE TO SLAVE PORT
When chip select is active and a write strobe occurs
(PMCS = 1 and PMWR = 1), the data from PMD<7:0>
is captured into the lower PMDIN1L register. The
PMPIF and IBF flag bits are set when the write
ends.The timing for the control signals in Write mode is
displayed in Figure 10-3. The polarity of the control
signals are configurable.
FIGURE 10-3:
10.2.3
READ FROM SLAVE PORT
When chip select is active and a read strobe occurs
(PMCS = 1 and PMRD = 1), the data from the
PMDOUT1L register (PMDOUT1L<7:0>) is presented
onto PMD<7:0>. Figure 10-4 provides the timing for the
control signals in Read mode.
PARALLEL SLAVE PORT WRITE WAVEFORMS
|
Q4
|
Q1
|
Q2
|
Q3
|
Q4
Q4
|
Q1
|
Q2
|
Q3
|
Q4
PMCS1
PMWR
PMRD
PMD<7:0>
IBF
OBE
PMPIF
FIGURE 10-4:
PARALLEL SLAVE PORT READ WAVEFORMS
|
PMCS1
PMWR
PMRD
PMD<7:0>
IBF
OBE
PMPIF
© 2009 Microchip Technology Inc.
DS39932C-page 175
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10.2.4
BUFFERED PARALLEL SLAVE
PORT MODE
10.2.4.2
Buffered Parallel Slave Port mode is functionally
identical to the legacy PSP mode with one exception,
the implementation of 4-level read and write buffers.
Buffered PSP mode is enabled by setting the INCM bits
in the PMMODEH register. If the INCM<1:0> bits are
set to ‘11’, the PMP module will act as the Buffered
PSP.
When the Buffered mode is active, the PMDIN1L,
PMDIN1H, PMDIN2L and PMDIN2H registers become
the write buffers and the PMDOUT1L, PMDOUT1H,
PMDOUT2L and PMDOUT2H registers become the
read buffers. Buffers are numbered 0 through 3, starting with the lower byte of PMDIN1L to PMDIN2H as the
read buffers and PMDOUT1L to PMDOUT2H as the
write buffers.
10.2.4.1
READ FROM SLAVE PORT
For read operations, the bytes will be sent out
sequentially, starting with Buffer 0 (PMDOUT1L<7:0>)
and ending with Buffer 3 (PMDOUT2H<7:0>) for every
read strobe. The module maintains an internal pointer
to keep track of which buffer is to be read. Each buffer
has a corresponding read status bit, OBxE, in the
PMSTATL register. This bit is cleared when a buffer
contains data that has not been written to the bus, and
is set when data is written to the bus. If the current buffer location being read from is empty, a buffer underflow
is generated, and the Buffer Overflow flag bit, OBUF, is
set. If all four OBxE status bits are set, then the Output
Buffer Empty flag (OBE) will also be set.
FIGURE 10-5:
WRITE TO SLAVE PORT
For write operations, the data has to be stored
sequentially, starting with Buffer 0 (PMDIN1L<7:0>)
and ending with Buffer 3 (PMDIN2H<7:0>). As with
read operations, the module maintains an internal
pointer to the buffer that is to be written next.
The input buffers have their own write status bits, IBxF
in the PMSTATH register. The bit is set when the buffer
contains unread incoming data, and cleared when the
data has been read. The flag bit is set on the write
strobe. If a write occurs on a buffer when its associated
IBxF bit is set, the Buffer Overflow flag, IBOV, is set;
any incoming data in the buffer will be lost. If all four
IBxF flags are set, the Input Buffer Full Flag (IBF) is set.
In Buffered Slave mode, the module can be configured
to generate an interrupt on every read or write strobe
(IRQM<1:0> = 01). It can be configured to generate an
interrupt on a read from Read Buffer 3 or a write to
Write Buffer 3, which is essentially an interrupt every
fourth read or write strobe (RQM<1:0> = 11). When
interrupting every fourth byte for input data, all input
buffer registers should be read to clear the IBxF flags.
If these flags are not cleared, then there is a risk of
hitting an overflow condition.
PARALLEL MASTER/SLAVE CONNECTION BUFFERED EXAMPLE
PIC18 Slave
Master
PMD<7:0>
PMD<7:0>
Write
Address
Pointer
Read
Address
Pointer
PMDOUT1L (0)
PMDIN1L (0)
PMDOUT1H (1)
PMDIN1H (1)
PMCS1
PMCS
PMRD
PMRD
PMDOUT2L (2)
PMDIN2L (2)
PMWR
PMDOUT2H (3)
PMDIN2H (3)
PMWR
Data Bus
Control Lines
DS39932C-page 176
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
10.2.5
ADDRESSABLE PARALLEL SLAVE
PORT MODE
In the Addressable Parallel Slave Port mode
(PMMODEH<1:0> = 01), the module is configured with
two extra inputs, PMA<1:0>, which are the address
lines 1 and 0. This makes the 4-byte buffer space
directly addressable as fixed pairs of read and write
buffers. As with Legacy Buffered mode, data is output
from PMDOUT1L, PMDOUT1H, PMDOUT2L and
PMDOUT2H, and is read in on PMDIN1L, PMDIN1H,
PMDIN2L and PMDIN2H. Table 10-1 provides the
buffer addressing for the incoming address to the input
and output registers.
FIGURE 10-6:
TABLE 10-1:
SLAVE MODE BUFFER
ADDRESSING
Output
Register
(Buffer)
PMA<1:0>
Input Register
(Buffer)
00
PMDOUT1L (0)
PMDIN1L (0)
01
PMDOUT1H (1)
PMDIN1H (1)
10
PMDOUT2L (2)
PMDIN2L (2)
11
PMDOUT2H((3)
PMDIN2H (3)
PARALLEL MASTER/SLAVE CONNECTION ADDRESSED BUFFER EXAMPLE
Master
PIC18F Slave
PMA<1:0>
PMA<1:0>
PMD<7:0>
PMD<7:0>
Write
Address
Decode
Read
Address
Decode
PMDOUT1L (0)
PMDIN1L (0)
PMDOUT1H (1)
PMDIN1H (1)
PMCS1
PMCS
PMRD
PMRD
PMDOUT2L (2)
PMDIN2L (2)
PMWR
PMDOUT2H (3)
PMDIN2H (3)
PMWR
Address Bus
Data Bus
Control Lines
10.2.5.1
READ FROM SLAVE PORT
When chip select is active and a read strobe occurs
(PMCS = 1 and PMRD = 1), the data from one of the
four output bytes is presented onto PMD<7:0>. Which
byte is read depends on the 2-bit address placed on
ADDR<1:0>. Table 10-1 provides the corresponding
FIGURE 10-7:
output registers and their associated address. When an
output buffer is read, the corresponding OBxE bit is set.
The OBxE flag bit is set when all the buffers are empty.
If any buffer is already empty, OBxE = 1, the next read
to that buffer will generate an OBUF event.
PARALLEL SLAVE PORT READ WAVEFORMS
|
Q4
|
Q1
|
Q2
|
Q3
|
Q4
PMCS
PMWR
PMRD
PMD<7:0>
PMA<1:0>
OBE
PMPIF
© 2009 Microchip Technology Inc.
DS39932C-page 177
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10.2.5.2
WRITE TO SLAVE PORT
When chip select is active and a write strobe occurs
(PMCS = 1 and PMWR = 1), the data from PMD<7:0>
is captured into one of the four input buffer bytes.
Which byte is written depends on the 2-bit address
placed on ADDRL<1:0>.
When an input buffer is written, the corresponding IBxF
bit is set. The IBF flag bit is set when all the buffers are
written. If any buffer is already written (IBxF = 1), the
next write strobe to that buffer will generate an OBUF
event and the byte will be discarded.
Table 10-1 provides the corresponding input registers
and their associated address.
FIGURE 10-8:
PARALLEL SLAVE PORT WRITE WAVEFORMS
|
Q4
|
Q1
|
Q2
|
Q3
|
Q4
PMCS
PMWR
PMRD
PMD<7:0>
PMA<1:0>
IBF
PMPIF
DS39932C-page 178
© 2009 Microchip Technology Inc.
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10.3
MASTER PORT MODES
In its Master modes, the PMP module provides an 8-bit
data bus, up to 16 bits of address, and all the necessary
control signals to operate a variety of external parallel
devices, such as memory devices, peripherals and
slave microcontrollers. To use the PMP as a master,
the module must be enabled (PMPEN = 1) and the
mode must be set to one of the two possible Master
modes (PMMODEH<1:0> = 10 or 11).
Because there are a number of parallel devices with a
variety of control methods, the PMP module is designed
to be extremely flexible to accommodate a range of
configurations. Some of these features include:
•
•
•
•
•
•
•
8-Bit and 16-Bit Data modes on an 8-bit data bus
Configurable address/data multiplexing
Up to two chip select lines
Up to 16 selectable address lines
Address auto-increment and auto-decrement
Selectable polarity on all control lines
Configurable Wait states at different stages of the
read/write cycle
10.3.1
PMP AND I/O PIN CONTROL
Multiple control bits are used to configure the presence
or absence of control and address signals in the
module. These bits are PTBEEN, PTWREN, PTRDEN
and PTEN<15:0>. They give the user the ability to conserve pins for other functions and allow flexibility to
control the external address. When any one of these
bits is set, the associated function is present on its
associated pin; when clear, the associated pin reverts
to its defined I/O port function.
Setting a PTENx bit will enable the associated pin as
an address pin and drive the corresponding data
contained in the PMADDR register. Clearing a PTENx
bit will force the pin to revert to its original I/O function.
For the pins configured as chip select (PMCS1 or
PMCS2) with the corresponding PTENx bit set, the
PTEN0 and PTEN1 bits will also control the PMALL
and PMALH signals. When multiplexing is used, the
associated address latch signals should be enabled.
10.3.2
READ/WRITE CONTROL
The PMP module supports two distinct read/write
signaling methods. In Master Mode 1, read and write
strobes are combined into a single control line,
PMRD/PMWR. A second control line, PMENB, determines when a read or write action is to be taken. In
Master Mode 2, separate read and write strobes
(PMRD and PMWR) are supplied on separate pins.
All control signals (PMRD,
PMAL and PMCSx) can be
either positive or negative
controlled by separate bits
Note that the polarity of control signals that share the
same output pin (for example, PMWR and PMENB) are
controlled by the same bit; the configuration depends
on which Master Port mode is being used.
10.3.3
DATA WIDTH
The PMP supports data widths of both 8 bits and
16 bits. The data width is selected by the MODE16 bit
(PMMODEH<2>). Because the data path into and out
of the module is only 8 bits wide, 16-bit operations are
always handled in a multiplexed fashion, with the Least
Significant Byte (LSB) of data being presented first. To
differentiate data bytes, the byte enable control strobe,
PMBE, is used to signal when the Most Significant Byte
(MSB) of data is being presented on the data lines.
10.3.4
ADDRESS MULTIPLEXING
In either of the Master modes (PMMODEH<1:0> = 1x),
the user can configure the address bus to be multiplexed
together with the data bus. This is accomplished by
using the ADRMUX<1:0> bits (PMCONH<4:3>). There
are three address multiplexing modes available; typical
pinout configurations for these modes are displayed in
Figure 10-9, Figure 10-10 and Figure 10-11.
In Demultiplexed mode (PMCONH<4:3> = 00), data and
address information are completely separated. Data bits
are presented on PMD<7:0> and address bits are
presented on PMADDRH<6:0> and PMADDRL<7:0>.
In Partially Multiplexed mode (PMCONH<4:3> = 01), the
lower eight bits of the address are multiplexed with the
data pins on PMD<7:0>. The upper eight bits of address
are unaffected and are presented on PMADDRH<6:0>.
The PMA0 pin is used as an address latch, and presents
the address latch low enable strobe (PMALL). The read
and write sequences are extended by a complete CPU
cycle during which the address is presented on the
PMD<7:0> pins.
In Fully Multiplexed mode (PMCONH<4:3> = 10), the
entire 16 bits of the address are multiplexed with the
data pins on PMD<7:0>. The PMA0 and PMA1 pins are
used to present address latch low enable (PMALL) and
address latch high enable (PMALH) strobes,
respectively. The read and write sequences are
extended by two complete CPU cycles. During the first
cycle, the lower eight bits of the address are presented
on the PMD<7:0> pins with the PMALL strobe active.
During the second cycle, the upper eight bits of the
address are presented on the PMD<7:0> pins with the
PMALH strobe active. In the event the upper address
bits are configured as chip select pins, the
corresponding address bits are automatically forced
to ‘0’.
PMWR, PMBE, PMENB,
individually configured as
polarity. Configuration is
in the PMCONL register.
© 2009 Microchip Technology Inc.
DS39932C-page 179
PIC18F46J11 FAMILY
FIGURE 10-9:
DEMULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES
WITH CHIP SELECT)
PIC18F
PMA<7:0>
PMD<7:0>
PMCS
PMRD
Address Bus
Data Bus
PMWR
FIGURE 10-10:
Control Lines
PARTIALLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE
STROBES WITH CHIP SELECT)
PIC18F
PMD<7:0>
PMA<7:0>
PMCS
PMALL
PMRD
PMWR
FIGURE 10-11:
Address Bus
Multiplexed
Data and
Address Bus
Control Lines
FULLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE
STROBES WITH CHIP SELECT)
PIC18F
PMD<7:0>
PMA<13:8>
PMCS
PMALL
PMALH
DS39932C-page 180
PMRD
Multiplexed
Data and
Address Bus
PMWR
Control Lines
© 2009 Microchip Technology Inc.
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10.3.5
CHIP SELECT FEATURES
Up to two chip select lines, PMCS1 and PMCS2, are
available for the Master modes of the PMP. The two
chip select lines are multiplexed with the Most Significant bit (MSb) of the address bus (PMADDRH<6>).
When a pin is configured as a chip select, it is not
included in any address auto-increment/decrement.
The function of the chip select signals is configured
using the chip select function bits (PMCONL<7:6>).
10.3.6
AUTO-INCREMENT/DECREMENT
While the module is operating in one of the Master
modes, the INCMx bits (PMMODEH<4:3>) control the
behavior of the address value. The address can be
made to automatically increment or decrement after
each read and write operation. The address increments
once each operation is completed and the BUSY bit
goes to ‘0’. If the chip select signals are disabled and
configured as address bits, the bits will participate in
the increment and decrement operations; otherwise,
the CS1 bit values will be unaffected.
10.3.7
WAIT STATES
In Master mode, the user has control over the duration
of the read, write and address cycles by configuring the
module Wait states. Three portions of the cycle, the
beginning, middle and end, are configured using the
corresponding WAITBx, WAITMx and WAITEx bits in
the PMMODEL register.
The WAITBx bits (PMMODEL<7:6>) set the number of
Wait cycles for the data setup prior to the
PMRD/PMWT strobe in Mode 10, or prior to the
PMENB strobe in Mode 11. The WAITMx bits
(PMMODEL<5:2>) set the number of Wait cycles for
the PMRD/PMWT strobe in Mode 10, or for the PMENB
strobe in Mode 11. When this Wait state setting is ‘0’,
then WAITB and WAITE have no effect. The WAITE
bits (PMMODEL<1:0>) define the number of Wait
cycles for the data hold time after the PMRD/PMWT
strobe in Mode 10, or after the PMENB strobe in
Mode 11.
10.3.8
Note that the read data obtained from the PMDIN1L
register is actually the read value from the previous
read operation. Hence, the first user read will be a
dummy read to initiate the first bus read and fill the read
register. Also, the requested read value will not be
ready until after the BUSY bit is observed low. Thus, in
a back-to-back read operation, the data read from the
register will be the same for both reads. The next read
of the register will yield the new value.
10.3.9
WRITE OPERATION
To perform a write onto the parallel bus, the user writes
to the PMDIN1L register. This causes the module to
first output the desired values on the chip select lines
and the address bus. The write data from the PMDIN1L
register is placed onto the PMD<7:0> data bus. Then
the write line (PMWR) is strobed. If the 16-bit mode is
enabled (MODE16 = 1), the write to the PMDIN1L
register will initiate two bus writes. First write will
consist of the data contained in PMDIN1L and the
second write will contain the PMDIN1H.
10.3.10
10.3.10.1
PARALLEL MASTER PORT STATUS
The BUSY Bit
In addition to the PMP interrupt, a BUSY bit is provided
to indicate the status of the module. This bit is used
only in Master mode. While any read or write operation
is in progress, the BUSY bit is set for all but the very last
CPU cycle of the operation. In effect, if a single-cycle
read or write operation is requested, the BUSY bit will
never be active. This allows back-to-back transfers.
While the bit is set, any request by the user to initiate a
new operation will be ignored (i.e., writing or reading
the lower byte of the PMDIN1L register will neither
initiate a read nor a write).
10.3.10.2
Interrupts
When the PMP module interrupt is enabled for Master
mode, the module will interrupt on every completed
read or write cycle; otherwise, the BUSY bit is available
to query the status of the module.
READ OPERATION
To perform a read on the PMP, the user reads the
PMDIN1L register. This causes the PMP to output the
desired values on the chip select lines and the address
bus. Then the read line (PMRD) is strobed. The read
data is placed into the PMDIN1L register.
If the 16-bit mode is enabled (MODE16 = 1), the read
of the low byte of the PMDIN1L register will initiate two
bus reads. The first read data byte is placed into the
PMDIN1L register, and the second read data is placed
into the PMDIN1H.
© 2009 Microchip Technology Inc.
DS39932C-page 181
PIC18F46J11 FAMILY
10.3.11
MASTER MODE TIMING
This section contains a number of timing examples that
represent the common Master mode configuration
options. These options vary from 8-bit to 16-bit data,
fully demultiplexed to fully multiplexed address and
Wait states.
FIGURE 10-12:
READ AND WRITE TIMING, 8-BIT DATA, DEMULTIPLEXED ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS1
PMD<7:0>
PMA<7:0>
PMWR
PMRD
PMPIF
BUSY
FIGURE 10-13:
READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS1
Address<7:0>
PMD<7:0>
Data
PMWR
PMRD
PMALL
PMPIF
BUSY
FIGURE 10-14:
READ TIMING, 8-BIT DATA, WAIT STATES ENABLED, PARTIALLY MULTIPLEXED
ADDRESS
Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - -
PMCS1
PMD<7:0>
Address<7:0>
Data
PMRD
PMWR
PMALL
PMPIF
BUSY
WAITB<1:0> = 01
DS39932C-page 182
WAITE<1:0> = 00
WAITM<3:0> = 0010
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
FIGURE 10-15:
WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS1
Address<7:0>
PMD<7:0>
Data
PMWR
PMRD
PMALL
PMPIF
BUSY
FIGURE 10-16:
WRITE TIMING, 8-BIT DATA, WAIT STATES ENABLED, PARTIALLY MULTIPLEXED
ADDRESS
Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - -
PMCS1
Address<7:0>
PMD<7:0>
Data
PMWR
PMRD
PMALL
PMPIF
BUSY
WAITB<1:0> = 01
WAITE<1:0> = 00
WAITM<3:0> = 0010
FIGURE 10-17:
READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE
STROBE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS1
PMD<7:0>
Address<7:0>
Data
PMRD/PMWR
PMENB
PMALL
PMPIF
BUSY
© 2009 Microchip Technology Inc.
DS39932C-page 183
PIC18F46J11 FAMILY
FIGURE 10-18:
WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE
STROBE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS1
PMD<7:0>
Address<7:0>
Data
PMRD/PMWR
PMENB
PMALL
PMPIF
BUSY
FIGURE 10-19:
READ TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS1
Address<7:0>
PMD<7:0>
Data
Address<13:8>
PMWR
PMRD
PMALL
PMALH
PMPIF
BUSY
FIGURE 10-20:
WRITE TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS1
PMD<7:0>
Address<7:0>
Address<13:8>
Data
PMWR
PMRD
PMALL
PMALH
PMPIF
BUSY
DS39932C-page 184
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
FIGURE 10-21:
READ TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS1
LSB
PMD<7:0>
MSB
PMA<7:0>
PMWR
PMRD
PMBE
PMPIF
BUSY
FIGURE 10-22:
WRITE TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS1
LSB
PMD<7:0>
MSB
PMA<7:0>
PMWR
PMRD
PMBE
PMPIF
BUSY
FIGURE 10-23:
READ TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS1
PMD<7:0>
Address<7:0>
LSB
MSB
PMWR
PMRD
PMBE
PMALL
PMPIF
BUSY
© 2009 Microchip Technology Inc.
DS39932C-page 185
PIC18F46J11 FAMILY
FIGURE 10-24:
WRITE TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED
ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS1
PMD<7:0>
Address<7:0>
LSB
MSB
PMWR
PMRD
PMBE
PMALL
PMPIF
BUSY
FIGURE 10-25:
READ TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT
ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS1
Address<7:0>
PMD<7:0>
Address<13:8>
LSB
MSB
PMWR
PMRD
PMBE
PMALH
PMALL
PMPIF
BUSY
FIGURE 10-26:
WRITE TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT
ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS1
PMD<7:0>
Address<7:0>
Address<13:8>
LSB
MSB
PMWR
PMRD
PMBE
PMALH
PMALL
PMPIF
BUSY
DS39932C-page 186
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
10.4
Application Examples
10.4.1
This section introduces some potential applications for
the PMP module.
FIGURE 10-27:
Figure 10-27 demonstrates the hookup of a memory or
another addressable peripheral in Full Multiplex mode.
Consequently, this mode achieves the best pin saving
from the microcontroller perspective. However, for this
configuration, there needs to be some external latches
to maintain the address.
EXAMPLE – MULTIPLEXED ADDRESSING APPLICATION
PIC18F
PMD<7:0>
PMALL
A<7:0>
373
A<13:0>
D<7:0>
373
PMALH
10.4.2
MULTIPLEXED MEMORY OR
PERIPHERAL
D<7:0>
CE
A<15:8>
OE
WR
PMCS
Address Bus
PMRD
Data Bus
PMWR
Control Lines
PARTIALLY MULTIPLEXED
MEMORY OR PERIPHERAL
an external latch. If the peripheral has internal latches,
as displayed in Figure 10-29, then no extra circuitry is
required except for the peripheral itself.
Partial multiplexing implies using more pins; however,
for a few extra pins, some extra performance can be
achieved. Figure 10-28 provides an example of a
memory or peripheral that is partially multiplexed with
FIGURE 10-28:
EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION
PIC18F
PMD<7:0>
373
PMALL
A<7:0>
D<7:0>
A<7:0>
D<7:0>
CE
PMCS
OE
WR
Address Bus
PMRD
Data Bus
PMWR
Control Lines
FIGURE 10-29:
EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION
PIC18F
PMD<7:0>
PMALL
Parallel Peripheral
AD<7:0>
ALE
PMCS
CS
Address Bus
PMRD
RD
Data Bus
PMWR
WR
Control Lines
© 2009 Microchip Technology Inc.
DS39932C-page 187
PIC18F46J11 FAMILY
10.4.3
PARALLEL EEPROM EXAMPLE
Figure 10-30 provides an example connecting parallel
EEPROM to the PMP. Figure 10-31 demonstrates a
slight variation to this, configuring the connection for
16-bit data from a single EEPROM.
FIGURE 10-30:
PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT DATA)
PIC18F
Parallel EEPROM
PMA<n:0>
A<n:0>
PMD<7:0>
D<7:0>
PMCS
CE
PMRD
OE
PMWR
WR
FIGURE 10-31:
Data Bus
Control Lines
PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 16-BIT DATA)
PIC18F
Parallel EEPROM
PMA<n:0>
A<n:1>
PMD<7:0>
D<7:0>
PMBE
10.4.4
Address Bus
A0
PMCS
CE
PMRD
OE
PMWR
WR
Address Bus
Data Bus
Control Lines
LCD CONTROLLER EXAMPLE
The PMP module can be configured to connect to a
typical LCD controller interface, as displayed in
Figure 10-32. In this case, the PMP module is configured for active-high control signals since common LCD
displays require active-high control.
FIGURE 10-32:
LCD CONTROL EXAMPLE (BYTE MODE OPERATION)
PIC18F
PM<7:0>
PMA0
PMRD/PMWR
PMCS
LCD Controller
D<7:0>
RS
R/W
E
Address Bus
Data Bus
Control Lines
DS39932C-page 188
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 10-2:
Name
REGISTERS ASSOCIATED WITH PMP MODULE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
63
PIR1
PMPIF(2)
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
65
PIE1
PMPIE(2)
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
65
IPR1
PMPIP
(2)
ADIP
RC1IP
TX1IP
SSP1IP
PMCONH(2)
PMPEN
—
PSIDL
PMCONL(2)
CSF1
CSF0
ALP
—
CS1
PMADDRH(1,2)
/
ADRMUX1 ADRMUX0
—
CS1P
CCP1IP
TMR2IP
TMR1IP
65
PTBEEN
PTWREN
PTRDEN
67
BEP
WRSP
RDSP
67
Parallel Master Port Address High Byte
67
PMDOUT1H(1,2) Parallel Port Out Data High Byte (Buffer 1)
PMADDRL(1,2)/
67
Parallel Master Port Address Low Byte
67
PMDOUT1L(1,2) Parallel Port Out Data Low Byte (Buffer 0)
67
PMDOUT2H(2)
Parallel Port Out Data High Byte (Buffer 3)
67
(2)
PMDOUT2L
Parallel Port Out Data Low Byte (Buffer 2)
67
PMDIN1H(2)
Parallel Port In Data High Byte (Buffer 1)
67
PMDIN1L(2)
Parallel Port In Data Low Byte (Buffer 0)
67
PMDIN2H(2)
Parallel Port In Data High Byte (Buffer 3)
67
PMDIN2L(2)
Parallel Port In Data Low Byte (Buffer 2)
67
PMMODEH(2)
BUSY
IRQM1
IRQM0
INCM1
INCM0
MODE16
MODE1
MODE0
PMMODEL(2)
WAITB1
WAITB0
WAITM3
WAITM2
WAITM1
WAITM0
WAITE1
WAITE0
67
PMEH(2)
—
PTEN14
—
—
—
—
—
—
68
PMEL(2)
67
PTEN7
PTEN6
PTEN5
PTEN4
PTEN3
PTEN2
PTEN1
PTEN0
68
PMSTATH(2)
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
68
PMSTATL(2)
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
68
—
—
—
—
—
PADCFG1
Legend:
Note 1:
2:
RTSECSEL1 RTSECSEL0 PMPTTL
68
— = unimplemented, read as ‘0’. Shaded cells are not used during PMP operation.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and
addresses, but have different functions determined by the module’s operating mode.
These bits and/or registers are only available in 44-pin devices.
© 2009 Microchip Technology Inc.
DS39932C-page 189
PIC18F46J11 FAMILY
NOTES:
DS39932C-page 190
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
11.0
TIMER0 MODULE
The Timer0 module incorporates the following features:
• Software selectable operation as a timer or
counter in both 8-bit or 16-bit modes
• Readable and writable registers
• Dedicated 8-bit, software programmable
prescaler
• Selectable clock source (internal or external)
• Edge select for external clock
• Interrupt-on-overflow
REGISTER 11-1:
The T0CON register (Register 11-1) controls all
aspects of the module’s operation, including the
prescale selection. It is both readable and writable.
Figure 11-1 provides a simplified block diagram of the
Timer0 module in 8-bit mode. Figure 11-2 provides a
simplified block diagram of the Timer0 module in 16-bit
mode.
T0CON: TIMER0 CONTROL REGISTER (ACCESS FD5h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TMR0ON: Timer0 On/Off Control bit
1 = Enables Timer0
0 = Stops Timer0
bit 6
T08BIT: Timer0 8-Bit/16-Bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5
T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4
T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Timer0 Prescaler Assignment bit
1 = Timer0 prescaler is not assigned. Timer0 clock input bypasses prescaler.
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0
T0PS<2:0>: Timer0 Prescaler Select bits
111 = 1:256 Prescale value
110 = 1:128 Prescale value
101 = 1:64 Prescale value
100 = 1:32 Prescale value
011 = 1:16 Prescale value
010 = 1:8 Prescale value
001 = 1:4 Prescale value
000 = 1:2 Prescale value
© 2009 Microchip Technology Inc.
DS39932C-page 191
PIC18F46J11 FAMILY
11.1
Timer0 Operation
Timer0 can operate as either a timer or a counter. The
mode is selected with the T0CS bit (T0CON<5>). In
Timer mode (T0CS = 0), the module increments on
every clock by default unless a different prescaler value
is selected (see Section 11.3 “Prescaler”). If the
TMR0 register is written to, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
The Counter mode is selected by setting the T0CS bit
(= 1). In this mode, Timer0 increments either on every
rising edge or falling edge of pin, T0CKI. The
incrementing edge is determined by the Timer0 Source
Edge Select bit, T0SE (T0CON<4>); clearing this bit
selects the rising edge. Restrictions on the external
clock input are discussed below.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements to ensure
that the external clock can be synchronized with the
FIGURE 11-1:
internal phase clock (TOSC). There is a delay between
synchronization and the onset of incrementing the
timer/counter.
11.2
Timer0 Reads and Writes in 16-Bit
Mode
TMR0H is not the actual high byte of Timer0 in 16-bit
mode. It is actually a buffered version of the real high
byte of Timer0, which is not directly readable nor
writable (refer to Figure 11-2). TMR0H is updated with
the contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without having to verify that the read of the high
and low byte were valid, due to a rollover between
successive reads of the high and low byte.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FOSC/4
0
1
1
Programmable
Prescaler
T0CKI pin
T0SE
T0CS
0
Sync with
Internal
Clocks
Set
TMR0IF
on Overflow
TMR0L
(2 TCY Delay)
8
3
T0PS<2:0>
8
PSA
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 11-2:
FOSC/4
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
0
1
1
T0CKI pin
T0SE
T0CS
Programmable
Prescaler
0
Sync with
Internal
Clocks
TMR0
High Byte
TMR0L
8
Set
TMR0IF
on Overflow
(2 TCY Delay)
3
Read TMR0L
T0PS<2:0>
Write TMR0L
PSA
8
8
TMR0H
8
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
DS39932C-page 192
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
11.3
Prescaler
11.3.1
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable.
Its value is set by the PSA and T0PS<2:0> bits
(T0CON<3:0>), which determine the prescaler
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When it is assigned, prescale values
from 1:2 through 1:256 in power-of-2 increments are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
TABLE 11-1:
Name
SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
11.4
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
from FFFFh to 0000h in 16-bit mode. This overflow sets
the TMR0IF flag bit. The interrupt can be masked by
clearing the TMR0IE bit (INTCON<5>). Before
re-enabling the interrupt, the TMR0IF bit must be
cleared in software by the Interrupt Service Routine
(ISR).
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
REGISTERS ASSOCIATED WITH TIMER0
Bit 7
Bit 6
Bit 5
TMR0L
Timer0 Register Low Byte
TMR0H
Timer0 Register High Byte
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
T0CON
TMR0ON
T08BIT
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
84
84
T0CS
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
83
T0SE
PSA
T0PS2
T0PS1
T0PS0
84
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0.
© 2009 Microchip Technology Inc.
DS39932C-page 193
PIC18F46J11 FAMILY
NOTES:
DS39932C-page 194
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
12.0
TIMER1 MODULE
The Timer1 timer/counter module incorporates these
features:
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR1H
and TMR1L)
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt-on-overflow
• Reset on ECCP Special Event Trigger
• Device clock status flag (T1RUN)
• Timer with gated control
REGISTER 12-1:
Figure 12-1 displays a simplified block diagram of the
Timer1 module.
The module incorporates its own low-power oscillator
to provide an additional clocking option. The Timer1
oscillator can also be used as a low-power clock source
for the microcontroller in power-managed operation.
Timer1 is controlled through the T1CON Control
register (Register 12-1). It also contains the Timer1
oscillator Enable bit (T1OSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON (T1CON<0>).
The FOSC clock source (TMR1CS<1:0> = 01) should
not be used with the ECCP capture/compare features.
If the timer will be used with the capture or compare
features, always select one of the other timer clocking
options.
T1CON: TIMER1 CONTROL REGISTER (ACCESS FCDh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TMR1CS1
TMR1CS0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
RD16
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
TMR1CS<1:0>: Timer1 Clock Source Select bits
10 = Timer1 clock source is T1OSC or T1CKI pin
01 = Timer1 clock source is system clock (FOSC)(1)
00 = Timer1 clock source is instruction clock (FOSC/4)
bit 5-4
T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
T1OSCEN: Timer1 Crystal Oscillator Enable bit
1 = Timer1 oscillator circuit enabled
0 = Timer1 oscillator circuit disabled
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Select bit
TMR1CS<1:0> = 10:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS<1:0> = 0x:
This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 0x.
bit 1
RD16: 16-Bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer1 in one 16-bit operation
0 = Enables register read/write of Timer1 in two 8-bit operations
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Note 1:
The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare
features.
© 2009 Microchip Technology Inc.
DS39932C-page 195
PIC18F46J11 FAMILY
12.1
Timer1 Gate Control Register
The Timer1 Gate Control register (T1GCON),
displayed in Register 12-2, is used to control the
Timer1 gate.
REGISTER 12-2:
T1GCON: TIMER1 GATE CONTROL REGISTER (F9Ah)(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-x
R/W-0
R/W-0
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/T1DONE
T1GVAL
T1GSS1
T1GSS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TMR1GE: Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored.
If TMR1ON = 1:
1 = Timer1 counting is controlled by the Timer1 gate function
0 = Timer1 counts regardless of Timer1 gate function
bit 6
T1GPOL: Timer1 Gate Polarity bit
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5
T1GTM: Timer1 Gate Toggle Mode bit
1 = Timer1 Gate Toggle mode is enabled
0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4
T1GSPM: Timer1 Gate Single Pulse Mode bit
1 = Timer1 Gate Single Pulse mode is enabled and is controlling Timer1 gate
0 = Timer1 Gate Single Pulse mode is disabled
bit 3
T1GGO/T1DONE: Timer1 Gate Single Pulse Acquisition Status bit
1 = Timer1 gate single pulse acquisition is ready, waiting for an edge
0 = Timer1 gate single pulse acquisition has completed or has not been started
This bit is automatically cleared when T1GSPM is cleared.
bit 2
T1GVAL: Timer1 Gate Current State bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L; unaffected by
Timer1 Gate Enable (TMR1GE) bit.
bit 1-0
T1GSS<1:0>: Timer1 Gate Source Select bits
00 = Timer1 gate pin
01 = Timer0 overflow output
10 = TMR2 to match PR2 output
Note 1:
Programming the T1GCON prior to T1CON is recommended.
DS39932C-page 196
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 12-3:
TCLKCON: TIMER CLOCK CONTROL REGISTER (BANKED F52h)
U-0
U-0
U-0
R-0
U-0
U-0
R/W-0
R/W-0
—
—
—
T1RUN
—
—
T3CCP2
T3CCP1
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4
T1RUN: Timer1 Run Status bit
1 = Device is currently clocked by T1OSC/T1CKI
0 = System clock comes from an oscillator other than T1OSC/T1CKI
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
T3CCP<2:1>: ECCP Timer Assignment bits
10 = ECCP1 and ECCP2 both use Timer3 (capture/compare) and Timer4 (PWM)
01 = ECCP1 uses Timer1 (compare/capture) and Timer2 (PWM); ECCP2 uses Timer3
(capture/compare) and Timer4 (PWM)
00 = ECCP1 and ECCP2 both use Timer1 (capture/compare) and Timer2 (PWM)
© 2009 Microchip Technology Inc.
DS39932C-page 197
PIC18F46J11 FAMILY
12.2
Timer1 Operation
12.3.2
The Timer1 module is an 8-bit or 16-bit incrementing
counter,
which
is
accessed
through
the
TMR1H:TMR1L register pair.
When used with an internal clock source, the module is
a timer and increments on every instruction cycle.
When used with an external clock source, the module
can be used as either a timer or counter and
increments on every selected edge of the external
source.
Timer1 is enabled by configuring the TMR1ON and
TMR1GE bits in the T1CON and T1GCON registers,
respectively.
When the external clock source is selected, the Timer1
module may work as a timer or a counter.
When enabled to count, Timer1 is incremented on the
rising edge of the external clock input, T1CKI, or the
capacitive sensing oscillator signal. Either of these
external clock sources can be synchronized to the
microcontroller system clock or they can run
asynchronously.
When used as a timer with a clock oscillator, an
external 32.768 kHz crystal can be used in conjunction
with the dedicated internal oscillator circuit.
Note:
When Timer1 is enabled, the RC1/T1OSI/RP12 and
RC0/T1OSO/T1CKI/RP11 pins become inputs. This
means the values of TRISC<1:0> are ignored and the
pins are read as ‘0’.
12.3
Clock Source Selection
The TMR1CS<1:0> and T1OSCEN bits of the T1CON
register are used to select the clock source for Timer1.
Register 12-1 displays the clock source selections.
12.3.1
EXTERNAL CLOCK SOURCE
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
• Timer1 enabled after POR Reset
• Write to TMR1H or TMR1L
• Timer1 is disabled
• Timer1 is disabled (TMR1ON = 0)
when T1CKI is high, then Timer1 is
enabled (TMR1ON = 1) when T1CKI is
low.
INTERNAL CLOCK SOURCE
When the internal clock source is selected, the
TMR1H:TMR1L register pair will increment on multiples
of FOSC as determined by the Timer1 prescaler.
TABLE 12-1:
TIMER1 CLOCK SOURCE SELECTION
TMR1CS1
TMR1CS0
T1OSCEN
0
1
x
Clock Source (FOSC)
0
0
x
Instruction Clock (FOSC/4)
1
0
0
External Clock on T1CKI Pin
1
0
1
Oscillator Circuit on T1OSI/T1OSO Pin
DS39932C-page 198
Clock Source
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
T1GSS<1:0>
T1G
00
From Timer0
Overflow
01
From Timer2
Match PR2
10
T1GSPM
T1GVAL
0
Single Pulse
TMR1ON
T1GPOL
0
T1G_IN
D
Q
CK
R
Q
1
Acq. Control
1
Q1
Data Bus
D
Q
RD
T1GCON
EN
Interrupt
T1GGO/T1DONE
Set
RTCCIF
det
T1GTM
TMR1GE
Set Flag bit
TMR1IF on
Overflow
TMR1ON
TMR1(2)
TMR1H
EN
TMR1L
Q
D
T1CLK
Synchronized
Clock Input
0
1
TMR1CS<1:0>
T1OSO/T1CKI
T1OSC
T1OSI
T1SYNC
OUT
1
10
EN
0
T1OSCEN
(1)
FOSC
Internal
Clock
01
FOSC/4
Internal
Clock
00
Synchronize(3)
Prescaler
1, 2, 4, 8
det
2
T1CKPS<1:0>
FOSC/2
Internal
Clock
Sleep Input
T1CKI
Note 1:
2:
3:
ST Buffer is high-speed type when using T1CKI.
Timer1 register increments on rising edge.
Synchronize does not operate while in Sleep.
© 2009 Microchip Technology Inc.
DS39932C-page 199
PIC18F46J11 FAMILY
12.4
Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes.
When the RD16 control bit (T1CON<1>) is set, the
address for TMR1H is mapped to a buffer register for
the high byte of Timer1. A read from TMR1L loads the
contents of the high byte of Timer1 into the Timer1 High
Byte Buffer register. This provides the user with the
ability to accurately read all 16 bits of Timer1 without
having to determine whether a read of the high byte,
followed by a read of the low byte, has become invalid
due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. The Timer1 high
byte is updated with the contents of TMR1H when a
write occurs to TMR1L. This allows a user to write all
16 bits to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
12.5
Timer1 Oscillator
An on-chip crystal oscillator circuit is incorporated
between pins, T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting the Timer1 Oscillator
Enable bit, T1OSCEN (T1CON<3>). The oscillator is a
low-power circuit rated for 32 kHz crystals. It will
continue to run during all power-managed modes. The
circuit for a typical LP oscillator is depicted in
Figure 12-2. Table 12-2 provides the capacitor selection
for the Timer1 oscillator.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
FIGURE 12-2:
EXTERNAL COMPONENTS
FOR THE TIMER1 LP
OSCILLATOR
C1
12 pF
PIC18F46J11
T1OSI
XTAL
32.768 kHz
T1OSO
C2
12 pF
Note:
See the Notes with Table 12-2 for additional
information about capacitor selection.
DS39932C-page 200
TABLE 12-2:
CAPACITOR SELECTION FOR
THE TIMER
OSCILLATOR(2,3,4,5)
Oscillator
Type
Freq.
C1
C2
LP
32 kHz
12 pF(1)
12 pF(1)
Note 1: Microchip suggests these values as a
starting point in validating the oscillator
circuit.
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
4: Capacitor values are for design
guidance only. Values listed would be
typical of a CL = 10 pF rated crystal,
when LPT1OSC = 1.
5: Incorrect capacitance value may result in
a frequency not meeting the crystal
manufacturer’s tolerance specification.
The Timer1 crystal oscillator drive level is determined
based on the LPT1OSC (CONFIG2L<4>) Configuration bit. The higher drive level mode, LPT1OSC = 1, is
intended to drive a wide variety of 32.768 kHz crystals
with a variety of load capacitance (CL) ratings.
The lower drive level mode is highly optimized for
extremely low-power consumption. It is not intended to
drive all types of 32.768 kHz crystals. In the low drive
level mode, the crystal oscillator circuit may not work if
excessively large discrete capacitors are placed on the
T1OSI and T1OSO pins. This mode is only designed to
work with discrete capacitances of approximately
3 pF-10 pF on each pin.
Crystal manufacturers usually specify a CL (load
capacitance) rating for their crystals. This value is
related to, but not necessarily the same as, the values
that should be used for C1 and C2 in Figure 12-2. See
the crystal manufacturer’s applications’ information for
more details on how to select the optimum C1 and C2
for a given crystal. The optimum value depends in part
on the amount of parasitic capacitance in the circuit,
which is often unknown. Therefore, after values have
been selected, it is highly recommended that thorough
testing and validation of the oscillator be performed.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
12.5.1
USING TIMER1 AS A
CLOCK SOURCE
FIGURE 12-3:
The Timer1 oscillator is also available as a clock source
in power-managed modes. By setting the clock select
bits, SCS<1:0> (OSCCON<1:0>), to ‘01’, the device
switches to SEC_RUN mode; both the CPU and
peripherals are clocked from the Timer1 oscillator. If the
IDLEN bit (OSCCON<7>) is cleared and a SLEEP
instruction is executed, the device enters SEC_IDLE
mode. Additional details are available in Section 3.0
“Low-Power Modes”.
Whenever the Timer1 oscillator is providing the clock
source, the Timer1 system clock status flag, T1RUN
(TCLKCON<4>), is set. This can be used to determine
the controller’s current clocking mode. It can also
indicate the clock source currently being used by the
Fail-Safe Clock Monitor. If the Clock Monitor is enabled
and the Timer1 oscillator fails while providing the clock,
polling the T1RUN bit will indicate whether the clock is
being provided by the Timer1 oscillator or another
source.
12.5.2
TIMER1 OSCILLATOR LAYOUT
CONSIDERATIONS
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity. This is especially true when
the oscillator is configured for extremely low power
mode (LPT1OSC = 0).
The oscillator circuit, displayed in Figure 12-2, should
be located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
If a high-speed circuit must be located near the
oscillator (such as the ECCP1 pin in Output Compare
or PWM mode, or the primary oscillator using the
OSC2 pin), a grounded guard ring around the oscillator
circuit, as displayed in Figure 12-3, may be helpful
when used on a single-sided PCB or in addition to a
ground plane.
© 2009 Microchip Technology Inc.
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
VDD
VSS
OSC1
OSC2
RC0
RC1
RC2
Note: Not drawn to scale.
In the low drive level mode, LPT1OSC = 0, it is critical
that RC2 I/O pin signals be kept away from the oscillator
circuit. Configuring RC2 as a digital output, and toggling
it, can potentially disturb the oscillator circuit, even with
relatively good PCB layout. If possible, it is recommended to either leave RC2 unused, or use it as an input
pin with a slew rate limited signal source. If RC2 must be
used as a digital output, it may be necessary to use the
higher drive level oscillator mode (LPT1OSC = 1) with
many PCB layouts. Even in the higher drive level mode,
careful layout procedures should still be followed when
designing the oscillator circuit.
In addition to dV/dt induced noise considerations, it is
also important to ensure that the circuit board is clean.
Even a very small amount of conductive soldering flux
residue can cause PCB leakage currents, which can
overwhelm the oscillator circuit.
12.6
Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled or disabled
by setting or clearing the Timer1 Interrupt Enable bit,
TMR1IE (PIE1<0>).
DS39932C-page 201
PIC18F46J11 FAMILY
12.7
Resetting Timer1 Using the ECCP
Special Event Trigger
If ECCP1 or ECCP2 is configured to use Timer1 and to
generate a Special Event Trigger in Compare mode
(CCPxM<3:0> = 1011), this signal will reset Timer3.
The trigger from ECCP2 will also start an A/D conversion if the A/D module is enabled (see Section 17.3.4
“Special Event Trigger” for more information).
The module must be configured as either a timer or a
synchronous counter to take advantage of this feature.
When used this way, the CCPRxH:CCPRxL register
pair effectively becomes a Period register for Timer1.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
Special Event Trigger, the write operation will take
precedence.
Note:
12.8
The Special Event Trigger from the
ECCPx module will not set the TMR1IF
interrupt flag bit (PIR1<0>).
12.8.1
TIMER1 GATE COUNT ENABLE
The Timer1 Gate Enable mode is enabled by setting
the TMR1GE bit of the T1GCON register. The polarity
of the Timer1 Gate Enable mode is configured using
the T1GPOL bit of the T1GCON register.
When Timer1 Gate Enable mode is enabled, Timer1
will increment on the rising edge of the Timer1 clock
source. When Timer1 Gate Enable mode is disabled,
no incrementing will occur and Timer1 will hold the
current count. See Figure 12-4 for timing details.
TABLE 12-3:
TIMER1 GATE ENABLE
SELECTIONS
T1CLK
T1GPOL
T1G
Timer1 Operation
↑
0
0
Counts
↑
0
1
Holds Count
↑
1
0
Holds Count
↑
1
1
Counts
Timer1 Gate
Timer1 can be configured to count freely or the count can
be enabled and disabled using the Timer1 gate circuitry.
This is also referred to as Timer1 gate count enable.
The Timer1 gate can also be driven by multiple
selectable sources.
DS39932C-page 202
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
FIGURE 12-4:
TIMER1 GATE COUNT ENABLE MODE
TMR1GE
T1GPOL
T1G_IN
T1CKI
T1GVAL
Timer1
12.8.2
N
TIMER1 GATE SOURCE
SELECTION
The Timer1 gate source can be selected from one of
four different sources. Source selection is controlled by
the T1GSSx bits of the T1GCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the T1GPOL bit of the
T1GCON register.
TABLE 12-4:
T1GSS<1:0>
TIMER1 GATE SOURCES
Timer1 Gate Source
00
Timer1 Gate Pin
01
Overflow of Timer0
(TMR0 increments from FFh to 00h)
10
TMR2 to Match PR2
(TMR2 increments to match PR2)
© 2009 Microchip Technology Inc.
N+1
N+2
12.8.2.1
N+3
N+4
T1G Pin Gate Operation
The T1G pin is one source for Timer1 gate control. It
can be used to supply an external source to the Timer1
gate circuitry.
12.8.2.2
Timer0 Overflow Gate Operation
When Timer0 increments from FFh to 00h, a
low-to-high pulse will automatically be generated and
internally supplied to the Timer1 gate circuitry.
12.8.2.3
Timer2 Match Gate Operation
The TMR2 register will increment until it matches the
value in the PR2 register. On the very next increment
cycle, TMR2 will be reset to 00h. When this Reset
occurs, a low-to-high pulse will automatically be
generated and internally supplied to the Timer1 gate
circuitry.
DS39932C-page 203
PIC18F46J11 FAMILY
12.8.3
TIMER1 GATE TOGGLE MODE
When Timer1 Gate Toggle mode is enabled, it is
possible to measure the full cycle length of a Timer1
gate signal, as opposed to the duration of a single level
pulse.
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. See Figure 12-5 for timing details.
FIGURE 12-5:
The T1GVAL bit will indicate when the Toggled mode is
active and the timer is counting.
The Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
Timer1
DS39932C-page 204
N
N+1 N+2 N+3
N+4
N+5 N+6 N+7
N+8
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
12.8.4
TIMER1 GATE SINGLE PULSE
MODE
When Timer1 Gate Single Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer1
Gate Single Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/T1DONE bit in the T1GCON register must be
set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse,
the T1GGO/T1DONE bit will automatically be cleared.
No other gate events will be allowed to increment
Timer1 until the T1GGO/T1DONE bit is once again set
in software.
FIGURE 12-6:
Clearing the T1GSPM bit of the T1GCON register will
also clear the T1GGO/T1DONE bit. See Figure 12-6
for timing details.
Enabling the Toggle mode and the Single Pulse mode,
simultaneously, will permit both sections to work together.
This allows the cycle times on the Timer1 gate source to
be measured. See Figure 12-7 for timing details.
12.8.5
TIMER1 GATE VALUE STATUS
When the Timer1 gate value status is utilized, it is
possible to read the most current level of the gate
control value. The value is stored in the T1GVAL bit in
the T1GCON register. The T1GVAL bit is valid even
when the Timer1 gate is not enabled (TMR1GE bit is
cleared).
TIMER1 GATE SINGLE PULSE MODE
TMR1GE
T1GPOL
T1GSPM
T1GGO/
Cleared by Hardware on
Falling Edge of T1GVAL
Set by Software
T1DONE
Counting Enabled on
Rising Edge of T1G
T1G_IN
T1CKI
T1GVAL
Timer1
RTCCIF
N
Cleared by Software
© 2009 Microchip Technology Inc.
N+1
N+2
Set by Hardware on
Falling Edge of T1GVAL
Cleared by
Software
DS39932C-page 205
PIC18F46J11 FAMILY
FIGURE 12-7:
TIMER1 GATE SINGLE PULSE AND TOGGLE COMBINED MODE
TMR1GE
T1GPOL
T1GSPM
T1GTM
T1GGO/
Cleared by Hardware on
Falling Edge of T1GVAL
Set by Software
T1DONE
Counting Enabled on
Rising Edge of T1G
T1G_IN
T1CKI
T1GVAL
Timer1
Cleared by Software
RTCCIF
TABLE 12-5:
Name
N+1
N
N+2
N+4
N+3
Set by Hardware on
Falling Edge of T1GVAL
Cleared by
Software
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
83
PIR1
PMPIF(1)
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
85
PIE1
PMPIE
(1)
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
85
IPR1
PMPIP(1)
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
85
TMR1L
Timer1 Register Low Byte
84
TMR1H
Timer1 Register High Byte
84
T1CON
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
RD16
TMR1ON
84
T1GCON
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
T1DONE
T1GVAL
T1GSS1
T1GSS0
85
—
—
—
T1RUN
—
—
T3CCP2
T3CCP1
87
TCLKCON
Legend: Shaded cells are not used by the Timer1 module.
Note 1: These bits are only available in 44-pin devices.
DS39932C-page 206
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
13.0
TIMER2 MODULE
13.1
Timer2 Operation
• 8-bit Timer and Period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler
(1:1, 1:4 and 1:16)
• Software programmable postscaler
(1:1 through 1:16)
• Interrupt on TMR2 to PR2 match
• Optional use as the shift clock for the
MSSP modules
In normal operation, TMR2 is incremented from 00h on
each clock (FOSC/4). A 4-bit counter/prescaler on the
clock input gives direct input, divide-by-4 and
divide-by-16 prescale options. These are selected by
the
prescaler
control
bits,
T2CKPS<1:0>
(T2CON<1:0>). The value of TMR2 is compared to that
of the Period register, PR2, on each clock cycle. When
the two values match, the comparator generates a
match signal as the timer output. This signal also resets
the value of TMR2 to 00h on the next cycle and drives
the output counter/postscaler (see Section 13.2
“Timer2 Interrupt”).
The module is controlled through the T2CON register
(Register 13-1) which enables or disables the timer and
configures the prescaler and postscaler. Timer2 can be
shut off by clearing control bit, TMR2ON (T2CON<2>),
to minimize power consumption.
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, while the PR2 register initializes at FFh.
Both the prescaler and postscaler counters are cleared
on the following events:
A simplified block diagram of the module is shown in
Figure 13-1.
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (Power-on Reset (POR), MCLR
Reset, Watchdog Timer Reset (WDTR) or
Brown-out Reset (BOR))
The Timer2 module incorporates the following features:
TMR2 is not cleared when T2CON is written.
REGISTER 13-1:
T2CON: TIMER2 CONTROL REGISTER (ACCESS FCAh)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
T2OUTPS3
T2OUTPS2
T2OUTPS1
T2OUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
T2OUTPS<3:0>: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
© 2009 Microchip Technology Inc.
x = Bit is unknown
DS39932C-page 207
PIC18F46J11 FAMILY
13.2
Timer2 Interrupt
13.3
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 Match Interrupt Flag,
which is latched in TMR2IF (PIR1<1>). The interrupt is
enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE (PIE1<1>).
Timer2 Output
The unscaled output of TMR2 is available primarily to
the ECCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP modules operating in SPI mode.
Additional information is provided in Section 18.0
“Master Synchronous Serial Port (MSSP) Module”.
A range of 16 postscaler options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0> (T2CON<6:3>).
FIGURE 13-1:
TIMER2 BLOCK DIAGRAM
4
1:1 to 1:16
Postscaler
T2OUTPS<3:0>
Set TMR2IF
2
T2CKPS<1:0>
TMR2/PR2
Match
Reset
1:1, 1:4, 1:16
Prescaler
FOSC/4
TMR2
TMR2 Output
(to PWM or MSSPx)
Comparator
8
PR2
8
8
Internal Data Bus
TABLE 13-1:
Name
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 7
Bit 6
INTCON GIE/GIEH PEIE/GIEL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
83
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
PMPIF(1)
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
85
PIE1
PMPIE(1)
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
85
IPR1
PMPIP(1)
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
85
TMR2
Timer2 Register
T2CON
PR2
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON
84
T2CKPS1 T2CKPS0
Timer2 Period Register
84
84
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: These bits are only available in 44-pin devices.
DS39932C-page 208
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
14.0
TIMER3 MODULE
The Timer3 timer/counter module incorporates these
features:
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR3H
and TMR3L)
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt-on-overflow
• Module Reset on ECCP Special Event Trigger
REGISTER 14-1:
A simplified block diagram of the Timer3 module is
shown in Figure 14-1.
The Timer3 module is controlled through the T3CON
register (Register 14-1). It also selects the clock source
options for the ECCP modules; see Section 17.1.1
“ECCP Module and Timer Resources” for more
information.
The FOSC clock source (TMR3CS<1:0> = 01) should
not be used with the ECCP capture/compare features.
If the timer will be used with the capture or compare
features, always select one of the other timer clocking
options.
T3CON: TIMER3 CONTROL REGISTER (ACCESS F79h)
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
TMR3CS1
TMR3CS0
T3CKPS1
T3CKPS0
—
T3SYNC
RD16
TMR3ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
TMR3CS<1:0>: Timer3 Clock Source Select bits
10 = Timer3 clock source is the T3CKI input pin (assigned in the PPS module)
01 = Timer3 clock source is the system clock (FOSC)(1)
00 = Timer3 clock source is the instruction clock (FOSC/4)
bit 5-4
T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
Reserved: Program as ‘0’
bit 2
T3SYNC: Timer3 External Clock Input Synchronization Control bit
When TMR3CS<1:0> = 10:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS<1:0> = 0x:
This bit is ignored; Timer3 uses the internal clock.
bit 1
RD16: 16-Bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer3 in one 16-bit operation
0 = Enables register read/write of Timer3 in two 8-bit operations
bit 0
TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
Note 1:
The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare
features.
© 2009 Microchip Technology Inc.
DS39932C-page 209
PIC18F46J11 FAMILY
14.1
Timer3 Gate Control Register
The Timer3 Gate Control register (T3GCON), provided
in Register 14-2, is used to control the Timer3 gate.
REGISTER 14-2:
T3GCON: TIMER3 GATE CONTROL REGISTER (ACCESS F97h)(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-x
R/W-0
R/W-0
TMR3GE
T3GPOL
T3GTM
T3GSPM
T3GGO/T3DONE
T3GVAL
T3GSS1
T3GSS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TMR3GE: Timer3 Gate Enable bit
If TMR3ON = 0:
This bit is ignored.
If TMR3ON = 1:
1 = Timer3 counting is controlled by the Timer3 gate function
0 = Timer3 counts regardless of Timer3 gate function
bit 6
T3GPOL: Timer3 Gate Polarity bit
1 = Timer3 gate is active-high (Timer3 counts when gate is high)
0 = Timer3 gate is active-low (Timer3 counts when gate is low)
bit 5
T3GTM: Timer3 Gate Toggle Mode bit
1 = Timer3 Gate Toggle mode is enabled
0 = Timer3 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer3 gate flip-flop toggles on every rising edge.
bit 4
T3GSPM: Timer3 Gate Single Pulse Mode bit
1 = Timer3 Gate Single Pulse mode is enabled and is controlling Timer3 gate
0 = Timer3 Gate Single Pulse mode is disabled
bit 3
T3GGO/T3DONE: Timer3 Gate Single Pulse Acquisition Status bit
1 = Timer3 gate single pulse acquisition is ready, waiting for an edge
0 = Timer3 gate single pulse acquisition has completed or has not been started
This bit is automatically cleared when T3GSPM is cleared.
bit 2
T3GVAL: Timer3 Gate Current State bit
Indicates the current state of the Timer3 gate that could be provided to TMR3H:TMR3L. Unaffected by
Timer3 Gate Enable bit (TMR3GE).
bit 1-0
T3GSS<1:0>: Timer3 Gate Source Select bits
10 = TMR2 to match PR2 output
01 = Timer0 overflow output
00 = Timer3 gate pin (T3G)
Note 1:
Programming the T3GCON prior to T3CON is recommended.
DS39932C-page 210
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 14-3:
TCLKCON: TIMER CLOCK CONTROL REGISTER (BANKED F52h)
U-0
U-0
U-0
R-0
U-0
U-0
R/W-0
R/W-0
—
—
—
T1RUN
—
—
T3CCP2
T3CCP1
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4
T1RUN: Timer1 Run Status bit
1 = Device is currently clocked by T1OSC/T1CKI
0 = System clock comes from an oscillator other than T1OSC/T1CKI
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
T3CCP<2:1>: ECCP Timer Assignment bits
10 = ECCP1 and ECCP2 both use Timer3 (capture/compare) and Timer4 (PWM)
01 = ECCP1 uses Timer1 (compare/capture) and Timer2 (PWM); ECCP2 uses Timer3
(capture/compare) and Timer4 (PWM)
00 = ECCP1 and ECCP2 both use Timer1 (capture/compare) and Timer2 (PWM)
© 2009 Microchip Technology Inc.
DS39932C-page 211
PIC18F46J11 FAMILY
14.2
Timer3 Operation
The operating mode is determined by the clock select
bits, TMR3CSx (T3CON<7:6>). When the TMR3CSx bits
are cleared (= 00), Timer3 increments on every internal
instruction cycle (FOSC/4). When TMR3CSx = 01, the
Timer3 clock source is the system clock (FOSC), and
when it is ‘10’, Timer3 works as a counter from the
external clock from the T3CKI pin (on the rising edge
after the first falling edge) or the Timer1 oscillator.
Timer3 can operate in one of three modes:
•
•
•
•
Timer
Synchronous Counter
Asynchronous Counter
Timer with Gated Control
FIGURE 14-1:
TIMER3 BLOCK DIAGRAM
T3GSS<1:0>
T3G
00
From Timer0
Overflow
01
From Timer2
Match PR2
10
T3GSPM
T3GVAL
0
Single Pulse
TMR3ON
T3GPOL
0
T3G_IN
D
Q
CK
R
Q
1
Acq. Control
1
Q1
D
RD
T3GCON
EN
Interrupt
T3GGO/T3DONE
Data Bus
Q
det
Set
TMR3GIF
T3GTM
TMR3GE
Set Flag bit,
TMR3IF, on
Overflow
TMR3ON
TMR3(2)
TMR3H
EN
TMR3L
Q
D
T3CLK
Synchronized
Clock Input
0
1
TMR3CS<1:0>
T3SYNC
T3CKI
10
Note 1:
2:
3:
FOSC
Internal
Clock
01
FOSC/4
Internal
Clock
00
Synchronize(3)
Prescaler
1, 2, 4, 8
det
2
T3CKPS<1:0>
FOSC/2
Internal
Clock
Sleep Input
ST Buffer is high-speed type when using T3CKI.
Timer3 register increments on rising edge.
Synchronize does not operate while in Sleep.
DS39932C-page 212
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
14.3
Timer3 16-Bit Read/Write Mode
The Timer1 oscillator is described in Section 12.0
“Timer1 Module”.
Timer3 can be configured for 16-bit reads and writes
(see Section 14.3 “Timer3 16-Bit Read/Write
Mode”). When the RD16 control bit (T3CON<1>) is
set, the address for TMR3H is mapped to a buffer register for the high byte of Timer3. A read from TMR3L
will load the contents of the high byte of Timer3 into the
Timer3 High Byte Buffer register. This provides the user
with the ability to accurately read all 16 bits of Timer3
without having to determine whether a read of the high
byte, followed by a read of the low byte, has become
invalid due to a rollover between reads.
14.5
Timer3 can be configured to count freely, or the count
can be enabled and disabled using Timer3 gate
circuitry. This is also referred to as Timer3 gate count
enable.
Timer3 gate can also be driven by multiple selectable
sources.
14.5.1
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bits to both the high and low bytes of Timer3 at once.
When Timer3 Gate Enable mode is enabled, Timer3
will increment on the rising edge of the Timer3 clock
source. When Timer3 Gate Enable mode is disabled,
no incrementing will occur and Timer3 will hold the
current count. See Figure 14-2 for timing details.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
TABLE 14-1:
Using the Timer1 Oscillator as the
Timer3 Clock Source
TIMER3 GATE ENABLE
SELECTIONS
T3CLK
T3GPOL
T3G
↑
0
0
Counts
↑
0
1
Holds Count
↑
1
0
Holds Count
↑
1
1
Counts
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting the T1OSCEN (T1CON<3>) bit. To use it as the
Timer3 clock source, the TMR3CS bit must also be set.
As previously noted, this also configures Timer3 to
increment on every rising edge of the oscillator source.
FIGURE 14-2:
TIMER3 GATE COUNT ENABLE
The Timer3 Gate Enable mode is enabled by setting
the TMR3GE bit of the T3GCON register. The polarity
of the Timer3 Gate Enable mode is configured using
the T3GPOL bit of the T3GCON register.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register.
14.4
Timer3 Gate
Timer3 Operation
TIMER3 GATE COUNT ENABLE MODE
TMR3GE
T3GPOL
T3G_IN
T1CKI
T3GVAL
Timer3
N
© 2009 Microchip Technology Inc.
N+1
N+2
N+3
N+4
DS39932C-page 213
PIC18F46J11 FAMILY
14.5.2
TIMER3 GATE SOURCE
SELECTION
The Timer3 gate source can be selected from one of
four different sources. Source selection is controlled by
the T3GSSx bits of the T3GCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the T3GPOL bit of the
T3GCON register.
TABLE 14-2:
TIMER3 GATE SOURCES
T3GSS<1:0>
Timer3 Gate Source
00
Timer3 Gate Pin
01
Overflow of Timer0
(TMR0 increments from FFh to 00h)
10
TMR2 to Match PR2
(TMR2 increments to match PR2)
11
Reserved
14.5.2.1
T3G Pin Gate Operation
The T3G pin is one source for Timer3 gate control. It
can be used to supply an external source to the Timer3
gate circuitry.
14.5.2.2
14.5.2.3
Timer2 Match Gate Operation
The TMR2 register will increment until it matches the
value in the PR2 register. On the very next increment
cycle, TMR2 will be reset to 00h. When this Reset
occurs, a low-to-high pulse will automatically be
generated and internally supplied to the Timer3 gate
circuitry.
14.5.3
TIMER3 GATE TOGGLE MODE
When Timer3 Gate Toggle mode is enabled, it is
possible to measure the full cycle length of a Timer3
gate signal, as opposed to the duration of a single level
pulse.
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. See Figure 14-3 for timing details.
The T3GVAL bit will indicate when the Toggled mode is
active and the timer is counting.
Timer3 Gate Toggle mode is enabled by setting the
T3GTM bit of the T3GCON register. When the T3GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
Timer0 Overflow Gate Operation
When Timer0 increments from FFh to 00h, a
low-to-high pulse will automatically be generated and
internally supplied to the Timer3 gate circuitry.
FIGURE 14-3:
TIMER3 GATE TOGGLE MODE
TMR3GE
T3GPOL
T3GTM
T3G_IN
T1CKI
T3GVAL
Timer3
DS39932C-page 214
N
N+1 N+2 N+3
N+4
N+5 N+6 N+7
N+8
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
14.5.4
TIMER3 GATE SINGLE PULSE
MODE
When Timer3 Gate Single Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer3
Gate Single Pulse mode is first enabled by setting the
T3GSPM bit in the T3GCON register. Next, the
T3GGO/T3DONE bit in the T3GCON register must be
set.
The Timer3 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the
T3GGO/T3DONE bit will automatically be cleared. No
FIGURE 14-4:
other gate events will be allowed to increment Timer3
until the T3GGO/T3DONE bit is once again set in
software.
Clearing the T3GSPM bit of the T3GCON register will
also clear the T3GGO/T3DONE bit. See Figure 14-4
for timing details.
Enabling the Toggle mode and the Single Pulse mode,
simultaneously, will permit both sections to work
together. This allows the cycle times on the Timer3 gate
source to be measured. See Figure 14-5 for timing
details.
TIMER3 GATE SINGLE PULSE MODE
TMR3GE
T3GPOL
T3GSPM
T3GGO/
Cleared by Hardware on
Falling Edge of T3GVAL
Set by Software
T3DONE
Counting Enabled on
Rising Edge of T3G
T3G_IN
T1CKI
T3GVAL
Timer3
TMR3GIF
N
Cleared by Software
© 2009 Microchip Technology Inc.
N+1
N+2
Set by Hardware on
Falling Edge of T3GVAL
Cleared by
Software
DS39932C-page 215
PIC18F46J11 FAMILY
FIGURE 14-5:
TIMER3 GATE SINGLE PULSE AND TOGGLE COMBINED MODE
TMR3GE
T3GPOL
T3GSPM
T3GTM
T3GGO/
Cleared by Hardware on
Falling Edge of T3GVAL
Set by Software
T3DONE
Counting Enabled on
Rising Edge of T3G
T3G_IN
T1CKI
T3GVAL
Timer3
TMR3GIF
14.5.5
N
N+1
Cleared by Software
TIMER3 GATE VALUE STATUS
When Timer3 gate value status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the T3GVAL bit in the T3GCON
register. The T3GVAL bit is valid even when the Timer3
gate is not enabled (TMR3GE bit is cleared).
N+2
N+4
N+3
Set by Hardware on
Falling Edge of T3GVAL
14.5.6
Cleared by
Software
TIMER3 GATE EVENT INTERRUPT
When the Timer3 gate event interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of T3GVAL
occurs, the TMR3GIF flag bit in the PIR3 register will be
set. If the TMR3GIE bit in the PIE3 register is set, then
an interrupt will be recognized.
The TMR3GIF flag bit operates even when the Timer3
gate is not enabled (TMR3GE bit is cleared).
DS39932C-page 216
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
14.6
Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF (PIR2<1>).
This interrupt can be enabled or disabled by setting or
clearing the Timer3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
14.7
Resetting Timer3 Using the ECCP
Special Event Trigger
If ECCP1 or ECCP2 is configured to use Timer3 and to
generate a Special Event Trigger in Compare mode
(CCPxM<3:0> = 1011), this signal will reset Timer3.
TABLE 14-3:
Name
The trigger from ECCP2 will also start an A/D conversion if the A/D module is enabled (see Section 17.3.4
“Special Event Trigger” for more information).
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPRxH:CCPRxL register
pair effectively becomes a Period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timer3 coincides with a
Special Event Trigger from an ECCP module, the write
will take precedence.
Note:
The Special Event Triggers from the
ECCPx module will not set the TMR3IF
interrupt flag bit (PIR1<0>).
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
83
PIR2
OSCFIF
CM2IF
CM1IF
—
BCL1IF
LVDIF
TMR3IF
CCP2IF
85
PIE2
OSCFIE
CM2IE
CM1IE
—
BCL1IE
LVDIE
TMR3IE
CCP2IE
85
IPR2
OSCFIP
CM2IP
CM1IP
—
BCL1IP
LVDIP
TMR3IP
CCP2IP
85
INTCON
GIE/GIEH PEIE/GIEL
TMR3L
Timer3 Register Low Byte
86
TMR3H
Timer3 Register High Byte
86
T1CON
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
—
T3SYNC
TMR1ON
84
RD16
TMR3ON
86
RD16
T3CON
TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0
T3GCON
TMR3GE
T3GPOL
T3GTM
T3GSPM
T3GGO/
T3DONE
T3GVAL
T3GSS1
T3GSS0
85
—
—
—
T1RUN
—
—
T3CCP2
T3CCP1
87
TCLKCON
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CTMUIF
TMR3GIF
RTCCIF
85
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CTMUIE
TMR3GIE
RTCCIE
85
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CTMUIP
TMR3GIP
RTCCIP
85
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
© 2009 Microchip Technology Inc.
DS39932C-page 217
PIC18F46J11 FAMILY
NOTES:
DS39932C-page 218
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
15.0
TIMER4 MODULE
15.1
The Timer4 timer module has the following features:
•
•
•
•
•
•
8-Bit Timer register (TMR4)
8-Bit Period register (PR4)
Readable and writable (both registers)
Software programmable prescaler (1:1, 1:4, 1:16)
Software programmable postscaler (1:1 to 1:16)
Interrupt on TMR4 match of PR4
Timer4 has a control register shown in Register 15-1.
Timer4 can be shut off by clearing control bit, TMR4ON
(T4CON<2>), to minimize power consumption. The
prescaler and postscaler selection of Timer4 is also
controlled by this register. Figure 15-1 is a simplified
block diagram of the Timer4 module.
Timer4 Operation
Timer4 can be used as the PWM time base for the
PWM mode of the ECCP modules. The TMR4 register
is readable and writable and is cleared on any device
Reset. The input clock (FOSC/4) has a prescale option
of 1:1, 1:4 or 1:16, selected by control bits,
T4CKPS<1:0> (T4CON<1:0>). The match output of
TMR4 goes through a 4-bit postscaler (which gives a
1:1 to 1:16 scaling inclusive) to generate a TMR4
interrupt, latched in flag bit, TMR4IF (PIR3<3>).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR4 register
• a write to the T4CON register
• any device Reset (Power-on Reset (POR), MCLR
Reset, Watchdog Timer Reset (WDTR) or
Brown-out Reset (BOR))
TMR4 is not cleared when T4CON is written.
REGISTER 15-1:
T4CON: TIMER4 CONTROL REGISTER (ACCESS F76h)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
T4OUTPS3
T4OUTPS2
T4OUTPS1
T4OUTPS0
TMR4ON
T4CKPS1
T4CKPS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
T4OUTPS<3:0>: Timer4 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2
TMR4ON: Timer4 On bit
1 = Timer4 is on
0 = Timer4 is off
bit 1-0
T4CKPS<1:0>: Timer4 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
© 2009 Microchip Technology Inc.
x = Bit is unknown
DS39932C-page 219
PIC18F46J11 FAMILY
15.2
Timer4 Interrupt
15.3
The Timer4 module has an 8-bit Period register, PR4,
which is both readable and writable. Timer4 increments
from 00h until it matches PR4 and then resets to 00h on
the next increment cycle. The PR4 register is initialized
to FFh upon Reset.
FIGURE 15-1:
Output of TMR4
The output of TMR4 (before the postscaler) is used
only as a PWM time base for the ECCP modules. It is
not used as a baud rate clock for the MSSP modules as
is the Timer2 output.
TIMER4 BLOCK DIAGRAM
4
1:1 to 1:16
Postscaler
T4OUTPS<3:0>
Set TMR4IF
2
T4CKPS<1:0>
TMR4 Output
(to PWM)
TMR4/PR4
Match
Reset
1:1, 1:4, 1:16
Prescaler
FOSC/4
TMR4
Comparator
8
PR4
8
8
Internal Data Bus
TABLE 15-1:
Name
REGISTERS ASSOCIATED WITH TIMER4 AS A TIMER/COUNTER
Bit 7
Bit 6
INTCON GIE/GIEH PEIE/GIEL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
83
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CTMUIP
TMR3GIP
RTCIP
85
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CTMUIF
TMR3GIF
RTCIF
85
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CTMUIE
TMR3GIE
RTCIE
85
PIE3
TMR4
T4CON
PR4
Timer4 Register
—
86
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0
Timer4 Period Register
86
86
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer4 module.
DS39932C-page 220
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
16.0
REAL-TIME CLOCK AND
CALENDAR (RTCC)
The key features of the Real-Time Clock and Calendar
(RTCC) module are:
•
•
•
•
•
•
•
•
•
•
•
•
Time: hours, minutes and seconds
24-hour format (military time)
Calendar: weekday, date, month and year
Alarm configurable
Year range: 2000 to 2099
Leap year correction
BCD format for compact firmware
Optimized for low-power operation
User calibration with auto-adjust
Calibration range: ±2.64 seconds error per month
Requirements: external 32.768 kHz clock crystal
Alarm pulse or seconds clock output on RTCC pin
FIGURE 16-1:
The RTCC module is intended for applications where
accurate time must be maintained for an extended
period with minimum to no intervention from the CPU.
The module is optimized for low-power usage in order
to provide extended battery life while keeping track of
time.
The module is a 100-year clock and calendar with automatic leap year detection. The range of the clock is
from 00:00:00 (midnight) on January 1, 2000 to
23:59:59 on December 31, 2099. Hours are measured
in 24-hour (military time) format. The clock provides a
granularity of one second with half-second visibility to
the user.
RTCC BLOCK DIAGRAM
RTCC Clock Domain
32.768 kHz Input
from Timer1 Oscillator
or Internal RC
CPU Clock Domain
RTCCFG
RTCC Prescalers
ALRMRPT
YEAR
0.5s
RTCC Timer
Alarm
Event
MTHDY
RTCVALx
WKDYHR
MINSEC
Comparator
ALMTHDY
Compare Registers
with Masks
ALRMVALx
ALWDHR
ALMINSEC
Repeat Counter
RTCC Interrupt
RTCC Interrupt Logic
Alarm Pulse
RTCC Pin
RTCOE
© 2009 Microchip Technology Inc.
DS39932C-page 221
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16.1
RTCC MODULE REGISTERS
The RTCC module registers are divided into following
categories:
RTCC Control Registers
•
•
•
•
•
RTCCFG
RTCCAL
PADCFG1
ALRMCFG
ALRMRPT
RTCC Value Registers
Alarm Value Registers
• ALRMVALH and ALRMVALL – Can access the
following registers:
- ALRMMNTH
- ALRMDAY
- ALRMWD
- ALRMHR
- ALRMMIN
- ALRMSEC
Note:
The RTCVALH and RTCVALL registers
can be accessed through RTCRPT<1:0>.
ALRMVALH and ALRMVALL can be
accessed through ALRMPTR<1:0>.
• RTCVALH and RTCVALL – Can access the
following registers
- YEAR
- MONTH
- DAY
- WEEKDAY
- HOUR
- MINUTE
- SECOND
DS39932C-page 222
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
16.1.1
RTCC CONTROL REGISTERS
REGISTER 16-1:
R/W-0
RTCCFG: RTCC CONFIGURATION REGISTER (BANKED F3Fh)(1)
U-0
RTCEN(2)
—
R/W-0
RTCWREN
R-0
R-0
(3)
RTCSYNC HALFSEC
R/W-0
R/W-0
R/W-0
RTCOE
RTCPTR1
RTCPTR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
RTCEN: RTCC Enable bit(2)
1 = RTCC module is enabled
0 = RTCC module is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5
RTCWREN: RTCC Value Registers Write Enable bit
1 = RTCVALH and RTCVALL registers can be written to by the user
0 = RTCVALH and RTCVALL registers are locked out from being written to by the user
bit 4
RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTCVALH, RTCVALL and ALRMRPT registers can change while reading due to a rollover ripple
resulting in an invalid data read
If the register is read twice and results in the same data, the data can be assumed to be valid.
0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple
bit 3
HALFSEC: Half-Second Status bit(3)
1 = Second half period of a second
0 = First half period of a second
bit 2
RTCOE: RTCC Output Enable bit
1 = RTCC clock output enabled
0 = RTCC clock output disabled
bit 1-0
RTCPTR<1:0>: RTCC Value Register Window Pointer bits
Points to the corresponding RTCC Value registers when reading the RTCVALH<7:0> and
RTCVALL<7:0> registers; the RTCPTR<1:0> value decrements on every read or write of
RTCVALH<7:0> until it reaches ‘00’.
RTCVALH<7:0>:
00 = Minutes
01 = Weekday
10 = Month
11 = Reserved
RTCVALL<7:0>:
00 = Seconds
01 = Hours
10 = Day
11 = Year
Note 1:
2:
3:
The RTCCFG register is only affected by a POR.
A write to the RTCEN bit is only allowed when RTCWREN = 1.
This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.
© 2009 Microchip Technology Inc.
DS39932C-page 223
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REGISTER 16-2:
RTCCAL: RTCC CALIBRATION REGISTER (BANKED F3Eh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
CAL<7:0>: RTC Drift Calibration bits
01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every minute
.
.
.
00000001 = Minimum positive adjustment; adds four RTC clock pulses every minute
00000000 = No adjustment
11111111 = Minimum negative adjustment; subtracts four RTC clock pulses every minute
.
.
.
10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every minute
REGISTER 16-3:
PADCFG1: PAD CONFIGURATION REGISTER (BANKED F3Ch)
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
RTSECSEL1(1) RTSECSEL0(1)
bit 7
R/W-0
PMPTTL
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-3
Unimplemented: Read as ‘0’
bit 2-1
RTSECSEL<1:0>: RTCC Seconds Clock Output Select bits(1)
11 = Reserved, do not use
10 = RTCC source clock is selected for the RTCC pin (pin can be INTRC or T1OSC, depending on the
RTCOSC (CONFIG3L<1>) setting)
01 = RTCC seconds clock is selected for the RTCC pin
00 = RTCC alarm pulse is selected for the RTCC pin
bit 0
PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt input buffers
Note 1:
To enable the actual RTCC output, the RTCOE (RTCCFG<2>) bit must be set.
DS39932C-page 224
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 16-4:
ALRMCFG: ALARM CONFIGURATION REGISTER (ACCESS F91h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALRMEN
CHIME
AMASK3
AMASK2
AMASK1
AMASK0
ALRMPTR1
ALRMPTR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
ALRMEN: Alarm Enable bit
1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 0000 0000
and CHIME = 0)
0 = Alarm is disabled
bit 6
CHIME: Chime Enable bit
1 = Chime is enabled; ALRMRPT<7:0> bits are allowed to roll over from 00h to FFh
0 = Chime is disabled; ALRMRPT<7:0> bits stop once they reach 00h
bit 5-2
AMASK<3:0>: Alarm Mask Configuration bits
0000 = Every half second
0001 = Every second
0010 = Every 10 seconds
0011 = Every minute
0100 = Every 10 minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29th, once every four years)
101x = Reserved – do not use
11xx = Reserved – do not use
bit 1-0
ALRMPTR<1:0>: Alarm Value Register Window Pointer bits
Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL
registers. The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches
‘00’.
ALRMVALH<15:8>:
00 = ALRMMIN
01 = ALRMWD
10 = ALRMMNTH
11 = Unimplemented
ALRMVALL<7:0>:
00 = ALRMSEC
01 = ALRMHR
10 = ALRMDAY
11 = Unimplemented
© 2009 Microchip Technology Inc.
DS39932C-page 225
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REGISTER 16-5:
ALRMRPT: ALARM CALIBRATION REGISTER (ACCESS F90h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ARPT7
ARPT6
ARPT5
ARPT4
ARPT3
ARPT2
ARPT1
ARPT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
ARPT<7:0>: Alarm Repeat Counter Value bits
11111111 = Alarm will repeat 255 more times
.
.
.
00000000 = Alarm will not repeat
The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to
FFh unless CHIME = 1.
DS39932C-page 226
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
16.1.2
RTCVALH AND RTCVALL
REGISTER MAPPINGS
REGISTER 16-6:
RESERVED REGISTER (ACCESS F99h, PTR 11b)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
Unimplemented: Read as ‘0’
REGISTER 16-7:
YEAR: YEAR VALUE REGISTER (ACCESS F98h, PTR 11b)(1)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
YRTEN3
YRTEN2
YRTEN1
YRTEN0
YRONE3
YRONE2
YRONE1
YRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit bits
Contains a value from 0 to 9.
bit 3-0
YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit bits
Contains a value from 0 to 9.
Note 1:
A write to the YEAR register is only allowed when RTCWREN = 1.
REGISTER 16-8:
MONTH: MONTH VALUE REGISTER (ACCESS F99h, PTR 10b)(1)
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
—
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
Unimplemented: Read as ‘0’
bit 4
MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of 0 or 1.
bit 3-0
MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits
Contains a value from 0 to 9.
Note 1:
x = Bit is unknown
A write to this register is only allowed when RTCWREN = 1.
© 2009 Microchip Technology Inc.
DS39932C-page 227
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REGISTER 16-9:
DAY: DAY VALUE REGISTER (ACCESS F98h, PTR 10b)(1)
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
DAYTEN1
DAYTEN0
DAYONE3
DAYONE2
DAYONE1
DAYONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DAYTEN<1:0>: Binary Coded Decimal value of Day’s Tens Digit bits
Contains a value from 0 to 3.
bit 3-0
DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits
Contains a value from 0 to 9.
Note 1:
A write to this register is only allowed when RTCWREN = 1.
REGISTER 16-10: WKDY: WEEKDAY VALUE REGISTER (ACCESS F99h, PTR 01b)(1)
U-0
U-0
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
—
—
—
—
—
WDAY2
WDAY1
WDAY0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits
Contains a value from 0 to 6.
Note 1:
x = Bit is unknown
A write to this register is only allowed when RTCWREN = 1.
DS39932C-page 228
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 16-11: HOURS: HOURS VALUE REGISTER (ACCESS F98h, PTR 01b)(1)
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits
Contains a value from 0 to 2.
bit 3-0
HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits
Contains a value from 0 to 9.
Note 1:
A write to this register is only allowed when RTCWREN = 1.
REGISTER 16-12: MINUTES: MINUTES VALUE REGISTER (ACCESS F99h, PTR 00b)
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0
MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits
Contains a value from 0 to 9.
REGISTER 16-13: SECONDS: SECONDS VALUE REGISTER (ACCESS F98h, PTR 00b)
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0
SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits
Contains a value from 0 to 9.
© 2009 Microchip Technology Inc.
DS39932C-page 229
PIC18F46J11 FAMILY
16.1.3
ALRMVALH AND ALRMVALL
REGISTER MAPPINGS
REGISTER 16-14: ALRMMNTH: ALARM MONTH VALUE REGISTER (ACCESS F8Fh, PTR 10b)(1)
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
—
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4
MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of 0 or 1.
bit 3-0
MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits
Contains a value from 0 to 9.
Note 1:
A write to this register is only allowed when RTCWREN = 1.
REGISTER 16-15: ALRMDAY: ALARM DAY VALUE REGISTER (ACCESS F8Eh, PTR 10b)(1)
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
DAYTEN1
DAYTEN0
DAYONE3
DAYONE2
DAYONE1
DAYONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits
Contains a value from 0 to 3.
bit 3-0
DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits
Contains a value from 0 to 9.
Note 1:
x = Bit is unknown
A write to this register is only allowed when RTCWREN = 1.
DS39932C-page 230
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 16-16: ALRMWD: ALARM WEEKDAY VALUE REGISTER (ACCESS F8Fh, PTR 01b)(1)
U-0
U-0
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
—
—
—
—
—
WDAY2
WDAY1
WDAY0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits
Contains a value from 0 to 6.
Note 1:
A write to this register is only allowed when RTCWREN = 1.
REGISTER 16-17: ALRMHR: ALARM HOURS VALUE REGISTER (ACCESS F8Eh, PTR 01b)(1)
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits
Contains a value from 0 to 2.
bit 3-0
HRONE3:HRONE0: Binary Coded Decimal Value of Hour’s Ones Digit bits
Contains a value from 0 to 9.
Note 1:
A write to this register is only allowed when RTCWREN = 1.
© 2009 Microchip Technology Inc.
DS39932C-page 231
PIC18F46J11 FAMILY
REGISTER 16-18: ALRMMIN: ALARM MINUTES VALUE REGISTER (ACCESS F8Fh, PTR 00b)
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0
MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits
Contains a value from 0 to 9.
REGISTER 16-19: ALRMSEC: ALARM SECONDS VALUE REGISTER (ACCESS F8Eh, PTR 00b)
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0
SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits
Contains a value from 0 to 9.
DS39932C-page 232
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
16.1.4
16.2
RTCEN BIT WRITE
An attempt to write to the RTCEN bit while
RTCWREN = 0 will be ignored. RTCWREN must be
set before a write to RTCEN can take place.
Like the RTCEN bit, the RTCVALH<15:8> and
RTCVALL<7:0> registers can only be written to when
RTCWREN = 1. A write to these registers, while
RTCWREN = 0, will be ignored.
FIGURE 16-2:
FIGURE 16-3:
The register interface for the RTCC and alarm values is
implemented using the Binary Coded Decimal (BCD)
format. This simplifies the firmware, when using the
module, as each of the digits is contained within its own
4-bit value (see Figure 16-2 and Figure 16-3).
Day
Month
0-9
0-1
Hours
(24-hour format)
0-2
0-9
0-9
0-3
Minutes
0-5
Day Of Week
0-9
Seconds
0-9
0-5
0-9
0-6
1/2 Second Bit
(binary format)
0/1
ALARM DIGIT FORMAT
Day
Month
0-1
Hours
(24-hour format)
0-2
REGISTER INTERFACE
TIMER DIGIT FORMAT
Year
0-9
16.2.1
Operation
0-9
© 2009 Microchip Technology Inc.
0-9
0-3
Minutes
0-5
Day Of Week
0-9
0-6
Seconds
0-9
0-5
0-9
DS39932C-page 233
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16.2.2
CLOCK SOURCE
As mentioned earlier, the RTCC module is intended to
be clocked by an external Real-Time Clock crystal
oscillating at 32.768 kHz, but also can be clocked by
the internal RC oscillator. The RTCC clock selection is
decided by the RTCOSC bit (CONFIG3L<1>).
FIGURE 16-4:
Calibration of the crystal can be done through this
module to yield an error of 3 seconds or less per month.
(For further details, see Section 16.2.9 “Calibration”.)
CLOCK SOURCE MULTIPLEXING
32.768 kHz XTAL
from T1OSC
1:16384
Half-Second
Clock
Half Second(1)
Clock Prescaler(1)
Internal RC
One-Second Clock
CONFIG 3L<1>
Second
Note 1:
16.2.2.1
Hour:Minute
Day
Month
Day of Week
Year
Writing to the lower half of the MINSEC register resets all counters, allowing fraction of a second synchronization;
the clock prescaler is held in Reset when RTCEN = 0.
Real-Time Clock Enable
For the day to month rollover schedule, see Table 16-2.
The RTCC module can be clocked by an external,
32.768 kHz crystal (Timer1 oscillator) or the internal RC
oscillator, which can be selected in CONFIG3L<1>.
Considering that the following values are in BCD
format, the carry to the upper BCD digit will occur at a
count of 10 and not at 16 (SECONDS, MINUTES,
HOURS, WEEKDAY, DAYS and MONTHS).
If the external clock is used, the Timer1 oscillator
should be enabled by setting T1CON<3> (T1OSCEN).
If INTRC is providing the clock, the INTRC clock can be
brought out to the RTCC pin by the RTSECSEL<1:0>
bits in the PADCFG register.
16.2.3
DIGIT CARRY RULES
This section explains which timer values are affected
when there is a rollover.
• Time of Day: From 23:59:59 to 00:00:00 with a
carry to the Day field
• Month: From 12/31 to 01/01 with a carry to the
Year field
• Day of Week: From 6 to 0 with no carry (see
Table 16-1)
• Year Carry: From 99 to 00; this also surpasses the
use of the RTCC
DS39932C-page 234
TABLE 16-1:
DAY OF WEEK SCHEDULE
Day of Week
Sunday
0
Monday
1
Tuesday
2
Wednesday
3
Thursday
4
Friday
5
Saturday
6
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 16-2:
DAY TO MONTH ROLLOVER
SCHEDULE
Month
Maximum Day Field
01 (January)
31
02 (February)
28 or 29(1)
03 (March)
31
04 (April)
30
05 (May)
31
06 (June)
30
07 (July)
31
08 (August)
31
16.2.6
SAFETY WINDOW FOR REGISTER
READS AND WRITES
The RTCSYNC bit indicates a time window during
which the RTCC Clock Domain registers can be safely
read and written without concern about a rollover.
When RTCSYNC = 0, the registers can be safely
accessed by the CPU.
Whether RTCSYNC = 1 or 0, the user should employ a
firmware solution to ensure that the data read did not
fall on a rollover boundary, resulting in an invalid or
partial read. This firmware solution would consist of
reading each register twice and then comparing the two
values. If the two values matched, then, a rollover did
not occur.
09 (September)
30
10 (October)
31
16.2.7
11 (November)
30
12 (December)
31
In order to perform a write to any of the RTCC Timer
registers, the RTCWREN bit (RTCCFG<5>) must be
set.
Note 1:
16.2.4
See Section 16.2.4 “Leap Year”.
LEAP YEAR
Since the year range on the RTCC module is 2000 to
2099, the leap year calculation is determined by any
year divisible by ‘4’ in the above range. Only February
is effected in a leap year.
February will have 29 days in a leap year and 28 days in
any other year.
16.2.5
GENERAL FUNCTIONALITY
All Timer registers containing a time value of seconds or
greater are writable. The user configures the time by
writing the required year, month, day, hour, minutes and
seconds to the Timer registers, via Register Pointers
(see Section 16.2.8 “Register Mapping”).
The timer uses the newly written values and proceeds
with the count from the required starting point.
The RTCC is enabled by setting the RTCEN bit
(RTCCFG<7>). If enabled, while adjusting these
registers, the timer still continues to increment. However,
any time the MINSEC register is written to, both of the
timer prescalers are reset to ‘0’. This allows fraction of a
second synchronization.
The Timer registers are updated in the same cycle as
the write instruction’s execution by the CPU. The user
must ensure that when RTCEN = 1, the updated
registers will not be incremented at the same time. This
can be accomplished in several ways:
• By checking the RTCSYNC bit (RTCCFG<4>)
• By checking the preceding digits from which a
carry can occur
• By updating the registers immediately following
the seconds pulse (or alarm interrupt)
WRITE LOCK
To avoid accidental writes to the RTCC Timer register,
it is recommended that the RTCWREN bit
(RTCCFG<5>) be kept clear at any time other than
while writing to. For the RTCWREN bit to be set, there
is only one instruction cycle time window allowed
between the 55h/AA sequence and the setting of
RTCWREN. For that reason, it is recommended that
users follow the code example in Example 16-1.
EXAMPLE 16-1:
movlb
movlw
movwf
movlw
movwf
bsf
16.2.8
SETTING THE RTCWREN
BIT
0x0f
0x55
EECON2,0
0xAA
EECON2,0
RTCCFG,5,1
REGISTER MAPPING
To limit the register interface, the RTCC Timer and
Alarm Timer registers are accessed through
corresponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the
RTCPTR bits (RTCCFG<1:0>) to select the required
Timer register pair.
By reading or writing to the RTCVALH register, the
RTCC Pointer value (RTCPTR<1:0>) decrements by 1
until it reaches ‘00’. Once it reaches ‘00’, the MINUTES
and SECONDS value will be accessible through
RTCVALH and RTCVALL until the pointer value is
manually changed.
The user has visibility to the half-second field of the
counter. This value is read-only and can be reset only
by writing to the lower half of the SECONDS register.
© 2009 Microchip Technology Inc.
DS39932C-page 235
PIC18F46J11 FAMILY
TABLE 16-3:
RTCPTR<1:0>
RTCVALH AND RTCVALL
REGISTER MAPPING
RTCC Value Register Window
RTCVALH<15:8> RTCVALL<7:0>
00
MINUTES
SECONDS
01
WEEKDAY
HOURS
10
MONTH
DAY
11
—
YEAR
To calibrate the RTCC module:
1.
2.
EQUATION 16-1:
60 = Error Clocks per Minute
By reading or writing to the ALRMVALH register, the
Alarm Pointer value, ALRMPTR<1:0>, decrements
by 1 until it reaches ‘00’. Once it reaches ‘00’, the
ALRMMIN and ALRMSEC value will be accessible
through ALRMVALH and ALRMVALL until the pointer
value is manually changed.
ALRMPTR<1:0>
16.2.9
ALRMVAL REGISTER
MAPPING
3.
Alarm Value Register Window
ALRMVALH<15:8> ALRMVALL<7:0>
00
ALRMMIN
ALRMSEC
01
ALRMWD
ALRMHR
10
ALRMMNTH
ALRMDAY
11
—
—
CALIBRATION
CONVERTING ERROR
CLOCK PULSES
(Ideal Frequency (32,758) – Measured Frequency) *
The Alarm Value register window (ALRMVALH and
ALRMVALL) uses the ALRMPTR bits (ALRMCFG<1:0>)
to select the desired Alarm register pair.
TABLE 16-4:
Use another timer resource on the device to find
the error of the 32.768 kHz crystal.
Convert the number of error clock pulses per
minute (see Equation 16-1).
• If the oscillator is faster than ideal (negative
result from step 2), the RTCCALL register value
needs to be negative. This causes the specified
number of clock pulses to be subtracted from
the timer counter once every minute.
• If the oscillator is slower than ideal (positive
result from step 2), the RTCCALL register value
needs to be positive. This causes the specified
number of clock pulses to be added to the timer
counter once every minute.
Load the RTCCAL register with the correct
value.
Writes to the RTCCAL register should occur only when
the timer is turned off, or immediately after the rising
edge of the seconds pulse.
Note:
In determining the crystal’s error value, it
is the user’s responsibility to include the
crystal’s initial error from drift due to
temperature or crystal aging.
The real-time crystal input can be calibrated using the
periodic auto-adjust feature. When properly calibrated,
the RTCC can provide an error of less than three
seconds per month.
To perform this calibration, find the number of error
clock pulses and store the value in the lower half of the
RTCCAL register. The 8-bit, signed value – loaded into
RTCCAL – is multiplied by ‘4’ and will either be added
or subtracted from the RTCC timer, once every minute.
DS39932C-page 236
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
16.3
Alarm
The alarm can also be configured to repeat based on a
preconfigured interval. The number of times this occurs
after the alarm is enabled is stored in the ALRMRPT
register.
The alarm features and characteristics are:
• Configurable from half a second to one year
• Enabled using the ALRMEN bit (ALRMCFG<7>,
Register 16-4)
• Offers one-time and repeat alarm options
16.3.1
Note:
While the alarm is enabled (ALRMEN = 1),
changing any of the registers – other than
the RTCCAL, ALRMCFG and ALRMRPT
registers and the CHIME bit – can result in
a false alarm event leading to a false
alarm interrupt. To avoid this, only change
the timer and alarm values while the alarm
is disabled (ALRMEN = 0). It is recommended that the ALRMCFG and
ALRMRPT registers and CHIME bit be
changed when RTCSYNC = 0.
CONFIGURING THE ALARM
The alarm feature is enabled using the ALRMEN bit.
This bit is cleared when an alarm is issued. The bit will
not be cleared if the CHIME bit = 1 or if ALRMRPT ≠ 0.
The interval selection of the alarm is configured
through the ALRMCFG bits (AMASK<3:0>). (See
Figure 16-5.) These bits determine which and how
many digits of the alarm must match the clock value for
the alarm to occur.
FIGURE 16-5:
ALARM MASK SETTINGS
Alarm Mask Setting
AMASK<3:0>
Day of the
Week
Month
Day
Hours
Minutes
Seconds
0000 – Every half second
0001 – Every second
0010 – Every 10 seconds
s
0011 – Every minute
s
s
m
s
s
m
m
s
s
0100 – Every 10 minutes
0101 – Every hour
0110 – Every day
0111 – Every week
d
1000 – Every month
1001 – Every year(1)
Note 1:
m
m
h
h
m
m
s
s
h
h
m
m
s
s
d
d
h
h
m
m
s
s
d
d
h
h
m
m
s
s
Annually, except when configured for February 29.
© 2009 Microchip Technology Inc.
DS39932C-page 237
PIC18F46J11 FAMILY
When ALRMCFG = 00 and the CHIME bit = 0
(ALRMCFG<6>), the repeat function is disabled and
only a single alarm will occur. The alarm can be
repeated up to 255 times by loading the ALRMRPT
register with FFh.
After each alarm is issued, the ALRMRPT register is
decremented by one. Once the register has reached
‘00’, the alarm will be issued one last time.
After the alarm is issued a last time, the ALRMEN bit is
cleared automatically and the alarm turned off. Indefinite
repetition of the alarm can occur if the CHIME bit = 1.
When CHIME = 1, the alarm is not disabled when the
ALRMRPT register reaches ‘00’, but it rolls over to FF
and continues counting indefinitely.
16.3.2
ALARM INTERRUPT
At every alarm event, an interrupt is generated. Additionally, an alarm pulse output is provided that operates
at half the frequency of the alarm.
The alarm pulse output is completely synchronous with
the RTCC clock and can be used as a trigger clock to
other peripherals. This output is available on the RTCC
pin. The output pulse is a clock with a 50% duty cycle
and a frequency half that of the alarm event (see
Figure 16-6).
The RTCC pin also can output the seconds clock. The
user can select between the alarm pulse, generated by
the RTCC module, or the seconds clock output.
The RTSECSEL (PADCFG1<1:0>) bits select between
these two outputs:
• Alarm pulse – RTSECSEL<1:0> = 00
• Seconds clock – RTSECSEL<1:0> = 0
FIGURE 16-6:
TIMER PULSE GENERATION
RTCEN bit
ALRMEN bit
RTCC Alarm Event
RTCC Pin
16.4
Low-Power Modes
16.5.2
POWER-ON RESET (POR)
The timer and alarm can optionally continue to operate
while in Sleep, Idle and even Deep Sleep mode. An
alarm event can be used to wake-up the microcontroller
from any of these Low-Power modes.
The RTCCFG and ALRMRPT registers are reset only
on a POR. Once the device exits the POR state, the
clock registers should be reloaded with the desired
values.
16.5
The timer prescaler values can be reset only by writing
to the SECONDS register. No device Reset can affect
the prescalers.
16.5.1
Reset
DEVICE RESET
When a device Reset occurs, the ALCFGRPT register
is forced to its Reset state causing the alarm to be disabled (if enabled prior to the Reset). If the RTCC was
enabled, it will continue to operate when a basic device
Reset occurs.
DS39932C-page 238
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
16.6
Register Maps
Table 16-5, Table 16-6 and Table 16-7 summarize the
registers associated with the RTCC module.
TABLE 16-5:
File Name
RTCC CONTROL REGISTERS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000
RTCCFG
RTCEN
—
RTCWREN
RTCSYNC
HALFSEC
RTCOE
RTCPTR1
RTCPTR0
RTCCAL
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
0000
PADCFG1
—
—
—
—
—
PMPTTL
0000
ALRMCFG
ALRMEN
CHIME
AMASK3
AMASK2
AMASK1
RTSECSEL1 RTSECSEL0
AMASK0
ALRMPTR1 ALRMPTR0
0000
ALRMRPT
ARPT7
ARPT6
ARPT5
ARPT4
ARPT3
ARPT2
ARPT1
ARPT0
0000
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CTMUIP
TMR3GIP
RTCCIP
1111
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CTMUIF
TMR3GIF
RTCCIF
0000
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CTMUIE
TMR3GIE
RTCCIE
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 44-pin devices.
TABLE 16-6:
File Name
RTCC VALUE REGISTERS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RTCVALH
RTCC Value Register Window High Byte, Based on RTCPTR<1:0>
RTCVALL
RTCC Value Register Window Low Byte, Based on RTCPTR<1:0>
RTCEN
—
ALRMEN
CHIME
RTCCFG
ALRMCFG
RTCWREN RTCSYNC HALFSEC
AMASK3
AMASK2
AMASK1
Bit 1
Bit 0
All Resets
xxxx
xxxx
RTCOE
RTCPTR1
RTCPTR0
0000
AMASK0
ALRMPTR1
ALRMPTR0
0000
ALRMVALH Alarm Value Register Window High Byte, Based on ALRMPTR<1:0>
xxxx
ALRMVALL
xxxx
Legend:
Alarm Value Register Window Low Byte, Based on ALRMPTR<1:0>
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 44-pin devices.
TABLE 16-7:
File Name
ALRMRPT
ALARM VALUE REGISTERS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ARPT7
ARPT6
ARPT5
ARPT4
ARPT3
ARPT2
ARPT1
ARPT0
0000
ALRMVALH Alarm Value Register Window High Byte, Based on ALRMPTR<1:0>
xxxx
ALRMVALL Alarm Value Register Window Low Byte, Based on ALRMPTR<1:0>
RTCCAL
CAL7
CAL6
CAL5
CAL4
CAL3
xxxx
CAL2
CAL1
CAL0
0000
RTCVALH
RTCC Value Register Window High Byte, Based on RTCPTR<1:0>
xxxx
RTCVALL
RTCC Value Register Window Low Byte, Based on RTCPTR<1:0>
xxxx
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 44-pin devices.
© 2009 Microchip Technology Inc.
DS39932C-page 239
PIC18F46J11 FAMILY
NOTES:
DS39932C-page 240
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
17.0
ENHANCED
CAPTURE/COMPARE/PWM
(ECCP) MODULE
PIC18F46J11 family devices have two Enhanced
Capture/Compare/PWM (ECCP) modules: ECCP1 and
ECCP2. These modules contain a 16-bit register, which
can operate as a 16-bit Capture register, a 16-bit
Compare register or a PWM Master/Slave Duty Cycle
register. These ECCP modules are upward compatible
with CCP
Note:
Register and bit names referencing one of
the two ECCP modules substitute an ‘x’ for
the module number. For example, registers CCP1CON and CCP2CON, which
have the same definitions, are called
CCPxCON. Figures and diagrams use
ECCP1-based names, but those names
also apply to ECCP2, with a “2” replacing
the illustration name’s “1”.
When writing firmware, the “x” in register
and bit names must be replaced with the
appropriate module number.
© 2009 Microchip Technology Inc.
ECCP1 and ECCP2 are implemented as standard CCP
modules with enhanced PWM capabilities. These
include:
•
•
•
•
•
Provision for two or four output channels
Output Steering modes
Programmable polarity
Programmable dead-band control
Automatic shutdown and restart
The enhanced features are discussed in detail in
Section 17.5 “PWM (Enhanced Mode)”.
Note:
PxA, PxB, PxC and PxD are associated
with the remappable pins (RPn).
DS39932C-page 241
PIC18F46J11 FAMILY
REGISTER 17-1:
CCPxCON: ECCPx CONTROL (ACCESS FBAh/FB4h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PxM1
PxM0
DCxB1
DCxB0
CCPxM3
CCPxM2
CCPxM1
CCPxM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
PxM<1:0>: Enhanced PWM Output Configuration bits
If CCPxM<3:2> = 00, 01, 10:
xx = PxA assigned as capture/compare input/output; PxB, PxC and PxD assigned as port pins
If CCPxM<3:2> = 11:
00 = Single output: PxA, PxB, PxC and PxD controlled by steering (see Section 17.5.7 “Pulse Steering
Mode”)
01 = Full-bridge output forward: PxD modulated; PxA active; PxB, PxC inactive
10 = Half-bridge output: PxA, PxB modulated with dead-band control; PxC and PxD assigned as
port pins
11 = Full-bridge output reverse: PxB modulated; PxC active; PxA and PxD inactive
bit 5-4
DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found
in CCPRxL.
bit 3-0
CCPxM<3:0>: ECCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match
0011 = Capture mode
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, initialize ECCPx pin low, set output on compare match (set CCPxIF)
1001 = Compare mode, initialize ECCPx pin high, clear output on compare match (set CCPxIF)
1010 = Compare mode, generate software interrupt only, ECCPx pin reverts to I/O state
1011 = Compare mode, trigger special event (ECCPx resets TMR1 or TMR3, starts A/D conversion,
sets CCxIF bit)
1100 = PWM mode; PxA and PxC active-high; PxB and PxD active-high
1101 = PWM mode; PxA and PxC active-high; PxB and PxD active-low
1110 = PWM mode; PxA and PxC active-low; PxB and PxD active-high
1111 = PWM mode; PxA and PxC active-low; PxB and PxD active-low
DS39932C-page 242
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
In addition to the expanded range of modes available
through the CCPxCON and ECCPxAS registers, the
ECCP modules have two additional registers associated
with Enhanced PWM operation and auto-shutdown
features. They are:
• ECCPxDEL (Enhanced PWM Control)
• PSTRxCON (Pulse Steering Control)
17.1
ECCP Outputs and Configuration
The Enhanced CCP module may have up to four PWM
outputs, depending on the selected operating mode.
These outputs, designated PxA through PxD, are
routed through the Peripheral Pin Select (PPS)
module. Therefore, individual functions may be
mapped to any of the remappable I/O pins, RPn. The
outputs that are active depend on the ECCP operating
mode selected. The pin assignments are summarized
in Table 17-4.
To configure the I/O pins as PWM outputs, the proper
PWM mode must be selected by setting the PxM<1:0>
and CCPxM<3:0> bits. The appropriate TRIS direction
bits for the port pins must also be set as outputs and the
output functions need to be assigned to I/O pins in the
PPS module. (For details on configuring the module,
see Section 9.7 “Peripheral Pin Select (PPS)”.)
17.1.1
ECCP MODULE AND TIMER
RESOURCES
The ECCP modules utilize Timers 1, 2, 3 or 4, depending
on the mode selected. Timer1 and Timer3 are available
to modules in Capture or Compare modes, while Timer2
and Timer4 are available for modules in PWM mode.
TABLE 17-1:
ECCP MODE – TIMER
RESOURCE
ECCP Mode
Timer Resource
Capture
Timer1 or Timer3
Compare
Timer1 or Timer3
PWM
Timer2 or Timer4
The assignment of a particular timer to a module is
determined by the Timer-to-ECCP enable bits in the
TCLKCON register (Register 12-3). The interactions
between the two modules are depicted in Figure 17-1.
Capture operations are designed to be used when the
timer is configured for Synchronous Counter mode.
Capture operations may not work as expected if the
associated timer is configured for Asynchronous Counter
mode.
© 2009 Microchip Technology Inc.
17.2
Capture Mode
In Capture mode, the CCPRxH:CCPRxL register pair
captures the 16-bit value of the TMR1 or TMR3
registers when an event occurs on the corresponding
ECCPx pin. An event is defined as one of the following:
•
•
•
•
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
The event is selected by the mode select bits,
CCPxM<3:0>, of the CCPxCON register. When a
capture is made, the interrupt request flag bit, CCPxIF,
is set; it must be cleared by software. If another capture
occurs before the value in register CCPRx is read, the
old captured value is overwritten by the new captured
value.
17.2.1
ECCP PIN CONFIGURATION
In Capture mode, the appropriate ECCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
Additionally, the ECCPx input function needs to be
assigned to an I/O pin through the Peripheral Pin
Select module. For details on setting up the
remappable pins, see Section 9.7 “Peripheral Pin
Select (PPS)”.
Note:
17.2.2
If the ECCPx pin is configured as an output, a write to the port can cause a capture
condition.
TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode
or Synchronized Counter mode. In Asynchronous
Counter mode, the capture operation may not work.
The timer to be used with each ECCP module is
selected in the TCLKCON register (Register 12-3).
17.2.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit clear to avoid false interrupts.
The interrupt flag bit, CCPxIF, should also be cleared
following any such change in operating mode.
DS39932C-page 243
PIC18F46J11 FAMILY
17.2.4
ECCP PRESCALER
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
There are four prescaler settings in Capture mode; they
are specified as part of the operating mode selected by
the mode select bits (CCPxM<3:0>). Whenever the
ECCP module is turned off, or Capture mode is disabled, the prescaler counter is cleared. This means
that any Reset will clear the prescaler counter.
EXAMPLE 17-1:
CLRF
MOVLW
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 17-1 provides the
FIGURE 17-1:
MOVWF
CCP1CON
; Turn CCP module off
NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP ON
CCP1CON
; Load CCP1CON with
; this value
CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H
Set CCP1IF
T3CCP1
ECCP1 pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
CCP1CON<3:0>
Q1:Q4
4
TMR3L
TMR3
Enable
CCPR1H
T3CCP1
DS39932C-page 244
CHANGING BETWEEN
CAPTURE PRESCALERS
CCPR1L
TMR1
Enable
TMR1H
TMR1L
4
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
17.3
Compare Mode
17.3.2
TIMER1/TIMER3 MODE SELECTION
In Compare mode, the 16-bit CCPRx register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the ECCPx
pin can be:
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the ECCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation will not work reliably.
•
•
•
•
17.3.3
Driven high
Driven low
Toggled (high-to-low or low-to-high)
Remain unchanged (that is, reflects the state of
the I/O latch)
The action on the pin is based on the value of the mode
select bits (CCPxM<3:0>). At the same time, the
interrupt flag bit, CCPxIF, is set.
17.3.1
ECCP PIN CONFIGURATION
Users must configure the ECCPx pin as an output by
clearing the appropriate TRIS bit.
Note:
Clearing the CCPxCON register will force
the ECCPx compare output latch (depending on device configuration) to the default
low level. This is not the PORTx I/O data
latch.
FIGURE 17-2:
SOFTWARE INTERRUPT MODE
When the Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the ECCPx pin is not affected;
only the CCPxIF interrupt flag is affected.
17.3.4
SPECIAL EVENT TRIGGER
The ECCP module is equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCPxM<3:0> = 1011).
The Special Event Trigger resets the Timer register pair
for whichever timer resource is currently assigned as the
module’s time base. This allows the CCPRx registers to
serve as a programmable period register for either timer.
The Special Event Trigger can also start an A/D conversion. In order to do this, the A/D converter must already
be enabled.
COMPARE MODE OPERATION BLOCK DIAGRAM
0
TMR1H
TMR1L
1
TMR3H
TMR3L
Special Event Trigger
(Timer1/Timer3 Reset, A/D Trigger)
T3CCP1
Set CCP1IF
Comparator
CCPR1H
CCPR1L
Compare
Match
ECCP1 Pin
Output
Logic
4
S
Q
R
TRIS
Output Enable
CCP1CON<3:0>
© 2009 Microchip Technology Inc.
DS39932C-page 245
PIC18F46J11 FAMILY
17.4
PWM Mode
17.4.1
In Pulse-Width Modulation (PWM) mode, the CCPx pin
produces up to a 10-bit resolution PWM output.
Note:
Clearing the CCPxCON register will force
the output latch (depending on device
configuration) to the default low level. This
is not the LATx data latch.
Figure 17-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up a CCP
module for PWM operation, see Section 17.4.3
“Setup for PWM Operation”.
FIGURE 17-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
Duty Cycle Register
9
0
CCPxCON<5:4>
CCPRxL
EQUATION 17-1:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period].
When TMR2 (TMR4) is equal to PR2 (PR4), the
following three events occur on the next increment
cycle:
• TMR2 (TMR4) is cleared
• The CCPx pin is set (exception: if PWM duty
cycle = 0%, the CCPx pin will not be set)
• The PWM duty cycle is latched from CCPRxL into
CCPRxH
(1)
CCPRxH
S
Comparator
Q
R
Reset
CCPx
pin
TMRx
TMRx = PRx
Match
2 LSbs latched
from Q clocks
Comparator
PRx
TRIS
Output Enable
Set CCPx pin
Note 1:
The PWM period is specified by writing to the PR2
(PR4) register. The PWM period can be calculated
using Equation 17-1:
Note:
Latch
Duty Cycle
The two LSbs of the Duty Cycle register are held by a
2-bit latch that is part of the module’s hardware. It is
physically separate from the CCPRx registers.
PWM PERIOD
17.4.2
The Timer2 and Timer 4 postscalers (see
Section 13.0 “Timer2 Module” and
Section 15.0 “Timer4 Module”) are not
used in the determination of the PWM
frequency. The postscaler could be used
to have a servo update rate at a different
frequency than the PWM output.
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPRxL register and to the CCPxCON<5:4> bits. Up
to 10-bit resolution is available. The CCPRxL contains
the eight MSbs and the CCPxCON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPRxL:CCPxCON<5:4>. Equation 17-2 is used to
calculate the PWM duty cycle in time.
A PWM output (Figure 17-4) has a time base (period)
and a time that the output stays high (duty cycle).
The frequency of the PWM is the inverse of the
period (1/period).
EQUATION 17-2:
FIGURE 17-4:
CCPRxL and CCPxCON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPRxH until after a match between PR2 (PR4) and
TMR2 (TMR4) occurs (i.e., the period is complete). In
PWM mode, CCPRxH is a read-only register.
PWM OUTPUT
Period
PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) •
TOSC • (TMR2 Prescale Value)
Duty Cycle
TMR2 (TMR4) = PR2 (PR4)
TMR2 (TMR4) = Duty Cycle
TMR2 (TMR4) = PR2 (TMR4)
DS39932C-page 246
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
The CCPRxH register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPRxH and 2-bit latch match TMR2
(TMR4), concatenated with an internal 2-bit Q clock or
2 bits of the TMR2 (TMR4) prescaler, the CCPx pin is
cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by Equation 17-3:
17.4.3
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
3.
4.
EQUATION 17-3:
(
FOSC
log FPWM
PWM Resolution (max) =
log(2)
Note:
)
SETUP FOR PWM OPERATION
5.
Set the PWM period by writing to the PR2 (PR4)
register.
Set the PWM duty cycle by writing to the
CCPRxL register and CCPxCON<5:4> bits.
Make the CCPx pin an output by clearing the
appropriate TRIS bit.
Set the TMR2 (TMR4) prescale value, then
enable Timer2 (Timer4) by writing to T2CON
(T4CON).
Configure the CCPx module for PWM operation.
bits
If the PWM duty cycle value is longer than
the PWM period, the CCPx pin will not be
cleared.
TABLE 17-2:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
© 2009 Microchip Technology Inc.
2.44 kHz
9.77 kHz
39.06 kHz
156.25 kHz
312.50 kHz
416.67 kHz
16
4
1
1
1
1
FFh
FFh
FFh
3Fh
1Fh
17h
10
10
10
8
7
6.58
DS39932C-page 247
PIC18F46J11 FAMILY
TABLE 17-3:
Name
INTCON
REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4
Bit 7
Bit 6
GIE/GIEH PEIE/GIEL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
63
IPEN
—
CM
RI
TO
PD
POR
BOR
64
PIR1
PMPIF
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
65
PIE1
PMPIE
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
65
IPR1
PMPIP
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
65
RCON
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF
CCP3IF
65
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CCP5IE
CCP4IE
CCP3IE
65
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CCP5IP
CCP4IP
CCP3IP
65
—
—
—
TRISG4
TRISG3
TRISG2
TRISG1
TRISG0
65
TRISG
TMR2(1)
Timer2 Register
64
PR2(1)
Timer2 Period Register
64
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
TMR4
Timer4 Register
PR4(1)
Timer4 Period Register
T4CON
—
64
67
67
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0
67
CCPR4L
Capture/Compare/PWM Register 4 Low Byte
67
CCPR4H
Capture/Compare/PWM Register 4 High Byte
67
CCPR5L
Capture/Compare/PWM Register 5 Low Byte
67
CCPR5H
Capture/Compare/PWM Register 5 High Byte
67
CCP4CON
—
—
DC4B1
DC4B0
CCP4M3
CCP4M2
CCP4M1
CCP4M0
67
CCP5CON
—
—
DC5B1
DC5B0
CCP5M3
CCP5M2
CCP5M1
CCP5M0
67
ODCON1(2)
—
—
—
CCP5OD
CCP4OD ECCP3OD ECCP2OD ECCP1OD
68
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM, Timer2 or Timer4.
Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0.
2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
DS39932C-page 248
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
17.5
PWM (Enhanced Mode)
The PWM outputs are multiplexed with I/O pins and are
designated: PxA, PxB, PxC and PxD. The polarity of the
PWM pins is configurable and is selected by setting the
CCPxM bits in the CCPxCON register appropriately.
The Enhanced PWM mode can generate a PWM signal
on up to four different output pins with up to 10 bits of
resolution. It can do this through four different PWM
Output modes:
•
•
•
•
Table 17-1 provides the pin assignments for each
Enhanced PWM mode.
Single PWM
Half-Bridge PWM
Full-Bridge PWM, Forward mode
Full-Bridge PWM, Reverse mode
Figure 17-5 provides an example of a simplified block
diagram of the Enhanced PWM module.
Note:
To select an Enhanced PWM mode, the PxM bits of the
CCPxCON register must be set appropriately.
FIGURE 17-5:
To prevent the generation of an
incomplete waveform when the PWM is
first enabled, the ECCP module waits until
the start of a new PWM period before
generating a PWM signal.
EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
Duty Cycle Registers
DC1B<1:0>
CCPxM<3:0>
4
PxM<1:0>
2
CCPR1L
ECCPx/PxA(2)
ECCP1/RPn
TRIS
CCPR1H (Slave)
PxB(2)
R
Comparator
Q
Output
Controller
RPn
TRIS
PxC(2)
TMR2
Comparator
PR2
Note 1:
2:
(1)
PRn
TRIS
S
PxD(2)
Clear Timer2,
toggle PWM pin and
latch duty cycle
PRn
TRIS
ECCP1DEL
The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to
create the 10-bit time base.
These pins are remappable.
Note 1: The TRIS register value for each PWM output must be configured appropriately.
2: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.
© 2009 Microchip Technology Inc.
DS39932C-page 249
PIC18F46J11 FAMILY
TABLE 17-4:
EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES
ECCP Mode
PxM<1:0>
PxA
PxB
PxC
PxD
Single
00
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Half-Bridge
10
Yes
Yes
No
No
Full-Bridge, Forward
01
Yes
Yes
Yes
Yes
Full-Bridge, Reverse
11
Yes
Yes
Yes
Yes
Note 1:
Outputs are enabled by pulse steering in Single mode (see Register 17-4).
FIGURE 17-6:
EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS
(ACTIVE-HIGH STATE)
PxM<1:0>
Signal
0
PR2 + 1
Pulse Width
Period
00
(Single Output)
PxA Modulated
Delay(1)
Delay(1)
PxA Modulated
10
(Half-Bridge)
PxB Modulated
PxA Active
01
(Full-Bridge,
Forward)
PxB Inactive
PxC Inactive
PxD Modulated
PxA Inactive
11
(Full-Bridge,
Reverse)
PxB Modulated
PxC Active
PxD Inactive
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (ECCPxDEL<6:0>)
Note 1: Dead-band delay is programmed using the ECCPxDEL register (Section 17.5.6 “Programmable Dead-Band
Delay Mode”).
DS39932C-page 250
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
FIGURE 17-7:
EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
PxM<1:0>
Signal
PR2 + 1
Pulse
Width
0
Period
00
(Single Output)
PxA Modulated
PxA Modulated
10
(Half-Bridge)
Delay(1)
Delay(1)
PxB Modulated
PxA Active
01
(Full-Bridge,
Forward)
PxB Inactive
PxC Inactive
PxD Modulated
PxA Inactive
11
(Full-Bridge,
Reverse)
PxB Modulated
PxC Active
PxD Inactive
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (ECCPxDEL<6:0>)
Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 17.5.6 “Programmable Dead-Band
Delay Mode”).
© 2009 Microchip Technology Inc.
DS39932C-page 251
PIC18F46J11 FAMILY
17.5.1
HALF-BRIDGE MODE
In Half-Bridge mode, two pins are used as outputs to
drive push-pull loads. The PWM output signal is output
on the PxA pin, while the complementary PWM output
signal is output on the PxB pin (see Figure 17-8). This
mode can be used for half-bridge applications, as
shown in Figure 17-9, or for full-bridge applications,
where four power switches are being modulated with
two PWM signals.
Since the PxA and PxB outputs are multiplexed with the
PORT data latches, the associated TRIS bits must be
cleared to configure PxA and PxB as outputs.
FIGURE 17-8:
Period
Period
Pulse Width
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in
half-bridge power devices. The value of the PxDC<6:0>
bits of the ECCPxDEL register sets the number of
instruction cycles before the output is driven active. If the
value is greater than the duty cycle, the corresponding
output remains inactive during the entire cycle. See
Section 17.5.6 “Programmable Dead-Band Delay
Mode” for more details of the dead-band delay
operations.
PxA(2)
td
td
PxB(2)
(1)
(1)
(1)
td = Dead-Band Delay
Note 1:
At this time, the TMR2 register is equal to the
PR2 register.
2:
FIGURE 17-9:
EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
Output signals are shown as active-high.
EXAMPLE OF HALF-BRIDGE APPLICATIONS
Standard Half-Bridge Circuit (“Push-Pull”)
FET
Driver
+
PxA
Load
FET
Driver
+
PxB
-
Half-Bridge Output Driving a Full-Bridge Circuit
V+
FET
Driver
FET
Driver
PxA
FET
Driver
Load
FET
Driver
PxB
DS39932C-page 252
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
17.5.2
FULL-BRIDGE MODE
In the Reverse mode, the PxC pin is driven to its active
state, the PxB pin is modulated, while the PxA and PxD
pins will be driven to their inactive state as provided
Figure 17-11.
In Full-Bridge mode, all four pins are used as outputs.
An example of a full-bridge application is provided in
Figure 17-10.
The PxA, PxB, PxC and PxD outputs are multiplexed
with the PORT data latches. The associated TRIS bits
must be cleared to configure the PxA, PxB, PxC and
PxD pins as outputs.
In the Forward mode, the PxA pin is driven to its active
state, the PxD pin is modulated, while the PxB and PxC
pins will be driven to their inactive state as provided in
Figure 17-11.
FIGURE 17-10:
EXAMPLE OF FULL-BRIDGE APPLICATION
V+
FET
Driver
QC
QA
FET
Driver
PxA
Load
PxB
FET
Driver
PxC
FET
Driver
QD
QB
VPxD
© 2009 Microchip Technology Inc.
DS39932C-page 253
PIC18F46J11 FAMILY
FIGURE 17-11:
EXAMPLE OF FULL-BRIDGE PWM OUTPUT
Forward Mode
Period
PxA
(2)
Pulse Width
PxB(2)
PxC(2)
PxD(2)
(1)
(1)
Reverse Mode
Period
Pulse Width
PxA(2)
PxB(2)
PxC(2)
PxD(2)
(1)
Note 1:
2:
(1)
At this time, the TMR2 register is equal to the PR2 register.
The output signal is shown as active-high.
DS39932C-page 254
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
17.5.2.1
Direction Change in Full-Bridge
Mode
In the Full-Bridge mode, the PxM1 bit in the CCPxCON
register allows users to control the forward/reverse
direction. When the application firmware changes this
direction control bit, the module will change to the new
direction on the next PWM cycle.
A direction change is initiated in software by changing
the PxM1 bit of the CCPxCON register. The following
sequence occurs prior to the end of the current PWM
period:
• The modulated outputs (PxB and PxD) are placed
in their inactive state.
• The associated unmodulated outputs (PxA and
PxC) are switched to drive in the opposite
direction.
• PWM modulation resumes at the beginning of the
next period.
See Figure 17-12 for an illustration of this sequence.
The Full-Bridge mode does not provide a dead-band
delay. As one output is modulated at a time, a
dead-band delay is generally not required. There is a
situation where a dead-band delay is required. This
situation occurs when both of the following conditions
are true:
FIGURE 17-12:
1.
2.
The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
The turn-off time of the power switch, including
the power device and driver circuit, is greater
than the turn-on time.
Figure 17-13 shows an example of the PWM direction
changing from forward to reverse, at a near 100% duty
cycle. In this example, at time, t1, the PxA and PxD
outputs become inactive, while the PxC output
becomes active. Since the turn-off time of the power
devices is longer than the turn-on time, a shoot-through
current will flow through power devices, QC and QD
(see Figure 17-10), for the duration of ‘t’. The same
phenomenon will occur to power devices, QA and QB,
for PWM direction change from reverse to forward.
If changing PWM direction at high duty cycle is required
for an application, two possible solutions for eliminating
the shoot-through current are:
1.
2.
Reduce PWM duty cycle for one PWM period
before changing directions.
Use switch drivers that can drive the switches off
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
EXAMPLE OF PWM DIRECTION CHANGE
Period(1)
Signal
Period
PxA (Active-High)
PxB (Active-High)
Pulse Width
PxC (Active-High)
(2)
PxD (Active-High)
Pulse Width
Note 1:
2:
The direction bit, PxM1 of the CCPxCON register, is written any time during the PWM cycle.
When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The
modulated PxB and PxD signals are inactive at this time. The length of this time is:
(1/FOSC) • TMR2 Prescale Value
© 2009 Microchip Technology Inc.
DS39932C-page 255
PIC18F46J11 FAMILY
FIGURE 17-13:
EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
Forward Period
t1
Reverse Period
PxA
PxB
PW
PxC
PxD
PW
TON
External Switch C
TOFF
External Switch D
Potential
Shoot-Through Current
Note 1:
17.5.3
All signals are shown as active-high.
2:
TON is the turn-on delay of power switch QC and its driver.
3:
TOFF is the turn-off delay of power switch QD and its driver.
START-UP CONSIDERATIONS
When any PWM mode is used, the application
hardware must use the proper external pull-up and/or
pull-down resistors on the PWM output pins.
Note:
T = TOFF – TON
When the microcontroller is released from
Reset, all of the I/O pins are in the
high-impedance state. The external
circuits must keep the power switch
devices in the OFF state until the microcontroller drives the I/O pins with the
proper signal levels or activates the PWM
output(s).
The CCPxM<1:0> bits of the CCPxCON register allow
the user to choose whether the PWM output signals are
active-high or active-low for each pair of PWM output
pins (PxA/PxC and PxB/PxD). The PWM output
DS39932C-page 256
polarities must be selected before the PWM pin output
drivers are enabled. Changing the polarity configuration while the PWM pin output drivers are enabled is
not recommended since it may result in damage to the
application circuits.
The PxA, PxB, PxC and PxD output latches may not be
in the proper states when the PWM module is
initialized. Enabling the PWM pin output drivers at the
same time as the Enhanced PWM modes may cause
damage to the application circuit. The Enhanced PWM
modes must be enabled in the proper Output mode and
complete a full PWM cycle before enabling the PWM
pin output drivers. The completion of a full PWM cycle
is indicated by the TMR2IF or TMR4IF bit of the PIR1
or PIR3 register being set as the second PWM period
begins.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
17.5.4
ENHANCED PWM
AUTO-SHUTDOWN MODE
The PWM mode supports an Auto-Shutdown mode that
will disable the PWM outputs when an external
shutdown event occurs. Auto-Shutdown mode places
the PWM output pins into a predetermined state. This
mode is used to help prevent the PWM from damaging
the application.
The auto-shutdown sources are selected using the
ECCPxAS<2:0> bits of the ECCPAS register. A
shutdown event may be generated by:
• A logic ‘0’ on the pin that is assigned the FLT0
input function
• Comparator C1
• Comparator C2
• Setting the ECCPxASE bit in firmware
REGISTER 17-2:
A shutdown condition is indicated by the ECCPxASE
(Auto-Shutdown Event Status) bit of the ECCPxAS
register. If the bit is a ‘0’, the PWM pins are operating
normally. If the bit is a ‘1’, the PWM outputs are in the
shutdown state.
When a shutdown event occurs, two things happen:
The ECCPxASE bit is set to ‘1’. The ECCPxASE will
remain set until cleared in firmware or an auto-restart
occurs (see Section 17.5.5 “Auto-Restart Mode”).
The enabled PWM pins are asynchronously placed in
their shutdown states. The PWM output pins are
grouped into pairs [PxA/PxC] and [PxB/PxD]. The state
of each pin pair is determined by the PSSxAC and
PSSxBD bits of the ECCPxAS register. Each pin pair
may be placed into one of three states:
• Drive logic ‘1’
• Drive logic ‘0’
• Tri-state (high-impedance)
ECCPxAS: ECCPx AUTO-SHUTDOWN CONTROL REGISTER (ACCESS FBEh/FB8h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ECCPxASE
ECCPxAS2
ECCPxAS1
ECCPxAS0
PSSxAC1
PSSxAC0
PSSxBD1
PSSxBD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
ECCPxASE: ECCP Auto-Shutdown Event Status bit
1 = A shutdown event has occurred; ECCP outputs are in a shutdown state
0 = ECCP outputs are operating
bit 6-4
ECCPxAS<2:0>: ECCP Auto-Shutdown Source Select bits
000 = Auto-shutdown is disabled
001 = Comparator C1OUT output is high
010 = Comparator C2OUT output is high
011 = Either Comparator C1OUT or C2OUT is high
100 = VIL on FLT0 pin
101 = VIL on FLT0 pin or Comparator C1OUT output is high
110 = VIL on FLT0 pin or Comparator C2OUT output is high
111 = VIL on FLT0 pin or Comparator C1OUT or Comparator C2OUT is high
bit 3-2
PSSxAC<1:0>: Pins PxA and PxC Shutdown State Control bits
00 = Drive pins PxA and PxC to ‘0’
01 = Drive pins PxA and PxC to ‘1’
1x = Pins PxA and PxC tri-state
bit 1-0
PSSxBD<1:0>: Pins PxB and PxD Shutdown State Control bits
00 = Drive pins PxB and PxD to ‘0’
01 = Drive pins PxB and PxD to ‘1’
1x = Pins PxB and PxD tri-state
Note 1: The auto-shutdown condition is a level-based signal, not an edge-based signal. As long as the level is
present, the auto-shutdown will persist.
2: Writing to the ECCPxASE bit is disabled while an auto-shutdown condition persists.
3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or
auto-restart), the PWM signal will always restart at the beginning of the next PWM period.
© 2009 Microchip Technology Inc.
DS39932C-page 257
PIC18F46J11 FAMILY
FIGURE 17-14:
PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PxRSEN = 0)
PWM Period
Shutdown Event
ECCPxASE bit
PWM Activity
Normal PWM
Start of
PWM Period
17.5.5
Shutdown
Event Occurs
AUTO-RESTART MODE
The Enhanced PWM can be configured to automatically
restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by
setting the PxRSEN bit in the ECCPxDEL register.
Shutdown
Event Clears
ECCPxASE
Cleared by
Firmware
PWM
Resumes
The module will wait until the next PWM period begins,
however, before re-enabling the output pin. This behavior allows the auto-shutdown with auto-restart features
to be used in applications based on current mode PWM
control.
If auto-restart is enabled, the ECCPxASE bit will
remain set as long as the auto-shutdown condition is
active. When the auto-shutdown condition is removed,
the ECCPxASE bit will be cleared via hardware and
normal operation will resume.
FIGURE 17-15:
PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PxRSEN = 1)
PWM Period
Shutdown Event
ECCPxASE bit
PWM Activity
Normal PWM
Start of
PWM Period
DS39932C-page 258
Shutdown
Event Occurs
Shutdown
Event Clears
PWM
Resumes
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
17.5.6
PROGRAMMABLE DEAD-BAND
DELAY MODE
FIGURE 17-16:
In half-bridge applications, where all power switches
are modulated at the PWM frequency, the power
switches normally require more time to turn off than to
turn on. If both the upper and lower power switches are
switched at the same time (one turned on and the other
turned off), both switches may be on for a short period
until one switch completely turns off. During this brief
interval, a very high current (shoot-through current) will
flow through both power switches, shorting the bridge
supply. To avoid this potentially destructive
shoot-through current from flowing during switching,
turning on either of the power switches is normally
delayed to allow the other switch to completely turn off.
In Half-Bridge mode, a digitally programmable
dead-band delay is available to avoid shoot-through
current from destroying the bridge power switches. The
delay occurs at the signal transition from the non-active
state to the active state. See Figure 17-16 for
illustration. The lower seven bits of the associated
ECCPxDEL register (Register 17-3) sets the delay
period in terms of microcontroller instruction cycles
(TCY or 4 TOSC).
FIGURE 17-17:
EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
Period
Period
Pulse Width
PxA(2)
td
td
PxB(2)
(1)
(1)
(1)
td = Dead-Band Delay
Note 1:
2:
At this time, the TMR2 register is equal to the
PR2 register.
Output signals are shown as active-high.
EXAMPLE OF HALF-BRIDGE APPLICATIONS
V+
Standard Half-Bridge Circuit (“Push-Pull”)
FET
Driver
+
V
-
PxA
Load
FET
Driver
+
V
-
PxB
V-
© 2009 Microchip Technology Inc.
DS39932C-page 259
PIC18F46J11 FAMILY
REGISTER 17-3:
ECCPxDEL: ENHANCED PWM CONTROL REGISTER (ACCESS FBDh/FB7h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PxRSEN
PxDC6
PxDC5
PxDC4
PxDC3
PxDC2
PxDC1
PxDC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PxRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPxASE bit clears automatically once the shutdown event goes
away; the PWM restarts automatically
0 = Upon auto-shutdown, ECCPxASE must be cleared by software to restart the PWM
bit 6-0
PxDC<6:0>: PWM Delay Count bits
PxDCn = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal
should transition active and the actual time it transitions active.
17.5.7
PULSE STEERING MODE
In Single Output mode, pulse steering allows any of the
PWM pins to be the modulated signal. Additionally, the
same PWM signal can simultaneously be available on
multiple pins.
Once the Single Output mode is selected
(CCPxM<3:2> = 11 and PxM<1:0> = 00 of the
CCPxCON register), the user firmware can bring out
the same PWM signal to one, two, three or four output
pins by setting the appropriate STR<D:A> bits of the
PSTRxCON register, as provided in Table 17-4.
Note:
While the PWM Steering mode is active, the
CCPxM<1:0> bits of the CCPxCON register select the
PWM output polarity for the Px<D:A> pins.
The PWM auto-shutdown operation also applies to
PWM Steering mode as described in Section 17.5.4
“Enhanced PWM Auto-shutdown mode”. An
auto-shutdown event will only affect pins that have
PWM outputs enabled.
The associated TRIS bits must be set to
output (‘0’) to enable the pin output driver
in order to see the PWM signal on the pin.
DS39932C-page 260
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 17-4:
PSTRxCON: PULSE STEERING CONTROL (ACCESS FBFh/FB9h)(1)
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
CMPL1
CMPL0
—
STRSYNC
STRD
STRC
STRB
STRA
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
CMPL<1:0>: Complementary Mode Output Assignment Steering Sync bits
1 = Modulated output pin toggles between PxA and PxB for each period
0 = Complementary output assignment disabled; STRD:STRA bits used to determine Steering mode
bit 5
Unimplemented: Read as ‘0’
bit 4
STRSYNC: Steering Sync bit
1 = Output steering update occurs on next PWM period
0 = Output steering update occurs at the beginning of the instruction cycle boundary
bit 3
STRD: Steering Enable bit D
1 = PxD pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxD pin is assigned to port pin
bit 2
STRC: Steering Enable bit C
1 = PxC pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxC pin is assigned to port pin
bit 1
STRB: Steering Enable bit B
1 = PxB pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxB pin is assigned to port pin
bit 0
STRA: Steering Enable bit A
1 = PxA pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxA pin is assigned to port pin
Note 1:
The PWM Steering mode is available only when the CCPxCON register bits, CCPxM<3:2> = 11 and
PxM<1:0> = 00.
© 2009 Microchip Technology Inc.
DS39932C-page 261
PIC18F46J11 FAMILY
FIGURE 17-18:
SIMPLIFIED STEERING
BLOCK DIAGRAM
17.5.7.1
The STRSYNC bit of the PSTRxCON register gives the
user two selections of when the steering event will
happen. When the STRSYNC bit is ‘0’, the steering
event will happen at the end of the instruction that
writes to the PSTRxCON register. In this case, the output signal at the Px<D:A> pins may be an incomplete
PWM waveform. This operation is useful when the user
firmware needs to immediately remove a PWM signal
from the pin.
STRA
PxA Signal
CCPxM1
PORT Data
RPn pin
1
0
TRIS
STRB
CCPxM0
1
PORT Data
0
RPn pin
CCPxM1
PORT Data
PORT Data
Note 1:
Figures 17-19 and 17-20 illustrate the timing diagrams
of the PWM steering depending on the STRSYNC
setting.
RPn pin
1
0
TRIS
STRD
CCPxM0
When the STRSYNC bit is ‘1’, the effective steering
update will happen at the beginning of the next PWM
period. In this case, steering on/off the PWM output will
always produce a complete PWM waveform.
TRIS
STRC
Steering Synchronization
RPn pin
1
0
TRIS
Port outputs are configured as displayed when
the CCPxCON register bits, PxM<1:0> = 00
and CCP1M<3:2> = 11.
Single PWM output requires setting at least
one of the STRx bits.
2:
FIGURE 17-19:
EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0)
PWM Period
PWM
STRn
P1<D:A>
PORT Data
PORT Data
P1n = PWM
FIGURE 17-20:
EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1)
PWM
STRn
P1<D:A>
PORT Data
PORT Data
P1n = PWM
DS39932C-page 262
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
17.5.8
OPERATION IN POWER-MANAGED
MODES
the PIR2 register will be set. The ECCPx will then be
clocked from the internal oscillator clock source, which
may have a different clock frequency than the primary
clock.
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the ECCPx pin is driving a value, it will continue to drive that value. When the device wakes up, it
will continue from this state. If Two-Speed Start-ups are
enabled, the initial start-up frequency from HFINTOSC
and the postscaler may not be stable immediately.
17.5.9
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the ECCP registers to their
Reset states.
This forces the ECCP module to reset to a state
compatible with previous, non-enhanced ECCP
modules used on other PIC18 and PIC16 devices.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCPx module without change.
17.5.8.1
EFFECTS OF A RESET
Operation with Fail-Safe
Clock Monitor (FSCM)
If the Fail-Safe Clock Monitor (FSCM) is enabled, a
clock failure will force the device into the
power-managed RC_RUN mode and the OSCFIF bit of
TABLE 17-5:
Name
INTCON
REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page:
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RABIE
TMR0IF
INT0IF
RABIF
63
IPEN
SBOREN
—
RI
TO
PD
POR
BOR
64
PIR1
PMPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
65
PIE1
PMPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
65
IPR1
PMPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
65
PIR2
OSCFIF
CM2IF
CM1IF
—
BCL1IF
LVDIF
TMR3IF
CCP2IF
65
PIE2
OSCFIE
CM2IE
CM1IE
—
BCL1IE
LVDIE
TMR3IE
CCP2IE
65
IPR2
OSCFIP
CM2IP
CM1IP
—
BCL1IP
LVDIP
TMR3IP
CCP2IP
65
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
66
RCON
TRISC
TMR1L
Timer1 Register Low Byte
64
TMR1H
Timer1 Register High Byte
64
TCLKCON
T1CON
TMR2
T2CON
—
—
—
T1RUN
—
—
T3CCP2
T3CCP1
87
TMR1CS1
TMR1CS0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
RD16
TMR1ON
64
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
64
Timer2 Register
—
64
PR2
Timer2 Period Register
64
TMR3L
Timer3 Register Low Byte
67
TMR3H
Timer3 Register High Byte
67
T3CON
TMR3CS1
TMR3CS0
T3CKPS1
T3CKPS0
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
CCPR1H
Capture/Compare/PWM Register 1 High Byte
CCP1CON
ECCP1AS
ECCP1DEL
Legend:
Note 1:
P1M1
P1M0
DC1B1
DC1B0
ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0
P1RSEN
P1DC6
P1DC5
P1DC4
—
T3SYNC
RD16
TMR3ON
67
65
65
CCP1M3
CCP1M2
CCP1M0
65
PSS1AC1
PSS1AC0 PSS1BD1 PSS1BD0
64
P1DC3
P1DC2
CCP1M1
P1DC1
P1DC0
65
— = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
These bits are only available on 44-pin devices.
© 2009 Microchip Technology Inc.
DS39932C-page 263
PIC18F46J11 FAMILY
NOTES:
DS39932C-page 264
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
18.0
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices include serial EEPROMs, shift registers,
display drivers and A/D Converters.
18.1
Master SSP (MSSP) Module
Overview
The MSSP module can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C™)
- Full Master mode
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
• Master mode
• Multi-Master mode
• Slave mode with 5-bit and 7-bit address masking
(with address masking for both 10-bit and 7-bit
addressing)
All of the MSSP1 module-related SPI and I2C I/O
functions are hard-mapped to specific I/O pins.
For MSSP2 functions:
• SPI I/O functions (SDO2, SDI2, SCK2 and SS2)
are all routed through the Peripheral Pin Select
(PPS) module.
These functions may be configured to use any of
the RPn remappable pins, as described in
Section 9.7 “Peripheral Pin Select (PPS)”.
• I2C functions (SCL2 and SDA2) have fixed pin
locations.
On all PIC18F46J11 family devices, the SPI DMA capability can only be used in conjunction with MSSP2. The
SPI DMA feature is described in Section 18.4 “SPI
DMA Module”.
Note:
Throughout
this
section,
generic
references to an MSSP module in any of its
operating modes may be interpreted as
being equally applicable to MSSP1 or
MSSP2. Register names and module I/O
signals use the generic designator ‘x’ to
indicate the use of a numeral to distinguish
a particular module when required. Control
bit names are not individuated.
All members of the PIC18F46J11 family have two
MSSP modules, designated as MSSP1 and MSSP2.
The modules operate independently:
• PIC18F4XJ11 devices – Both modules can be
configured for either I2C or SPI communication
• PIC18F2XJ11 devices:
- MSSP1 can be used for either I2C or SPI
communication
- MSSP2 can be used only for SPI
communication
© 2009 Microchip Technology Inc.
DS39932C-page 265
PIC18F46J11 FAMILY
18.2
Control Registers
FIGURE 18-1:
Each MSSP module has three associated control
registers. These include a status register (SSPxSTAT)
and two control registers (SSPxCON1 and SSPxCON2).
The use of these registers and their individual Configuration bits differ significantly depending on whether the
MSSP module is operated in SPI or I2C mode.
Additional details are provided under the individual
sections.
Note:
18.3
In devices with more than one MSSP
module, it is very important to pay close
attention to the SSPxCON register names.
SSP1CON1 and SSP1CON2 control
different operational aspects of the same
module,
while
SSP1CON1
and
SSP2CON1 control the same features for
two different modules.
Internal
Data Bus
Read
SDIx
SSPxSR reg
SDOx
SSx
• Serial Data Out (SDOx) –
RC7/RX1/DT1/SDO1/RP18 or
SDO2/Remappable
• Serial Data In (SDIx) –
RB5/KBI1/SDI1/SDA1/RP8 or SDI2/Remappable
• Serial Clock (SCKx) –
RB4/KBI0/SCK1/SCL1/RP7 or
SCK2/Remappable
Shift
Clock
bit 0
SSx Control
Enable
Edge
Select
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported.
To accomplish communication, typically three pins are
used:
Write
SSPxBUF reg
SPI Mode
When MSSP2 is used in SPI mode, it can optionally be
configured to work with the SPI DMA submodule
described in Section 18.4 “SPI DMA Module”.
MSSPx BLOCK DIAGRAM
(SPI MODE)
2
Clock Select
SCKx
SSPM<3:0>
SMP:CKE 4
(TMR2 Output
2
2
)
Edge
Select
Prescaler TOSC
4, 16, 64
Data to TXx/RXx in SSPxSR
TRIS bit
Note:
Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list of
multiplexed functions.
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SSx) – RA5/AN4/SS1/
HLVDIN/RCV/RP2 or SS2/Remappable
Figure 18-1 depicts the block diagram of the MSSP
module when operating in SPI mode.
DS39932C-page 266
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
18.3.1
REGISTERS
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data
bytes are written to or read from.
Each MSSP module has four registers for SPI mode
operation. These are:
In receive operations, SSPxSR and SSPxBUF
together create a double-buffered receiver. When
SSPxSR receives a complete byte, it is transferred to
SSPxBUF and the SSPxIF interrupt is set.
• MSSPx Control Register 1 (SSPxCON1)
• MSSPx Status Register (SSPxSTAT)
• Serial Receive/Transmit Buffer Register
(SSPxBUF)
• MSSPx Shift Register (SSPxSR) – Not directly
accessible
During transmission, the SSPxBUF is not
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
SSPxCON1 and SSPxSTAT are the control and status
registers in SPI mode operation. The SSPxCON1
register is readable and writable. The lower six bits of
the SSPxSTAT are read-only. The upper two bits of the
SSPxSTAT are read/write.
REGISTER 18-1:
R/W-1
SMP
SSPxSTAT: MSSPx STATUS REGISTER – SPI MODE (ACCESS FC7h/F73h)
R/W-1
R-1
R-1
R-1
R-1
R-1
R-1
(1)
D/A
P
S
R/W
UA
BF
CKE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6
CKE: SPI Clock Select bit(1)
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
bit 5
D/A: Data/Address bit
Used in I2C™ mode only.
bit 4
P: Stop bit
Used in I2C mode only; this bit is cleared when the MSSP module is disabled, SSPEN is cleared.
bit 3
S: Start bit
Used in I2C mode only.
bit 2
R/W: Read/Write Information bit
Used in I2C mode only.
bit 1
UA: Update Address bit
Used in I2C mode only.
bit 0
BF: Buffer Full Status bit
1 = Receive complete, SSPxBUF is full
0 = Receive not complete, SSPxBUF is empty
Note 1:
Polarity of clock state is set by the CKP bit (SSPxCON1<4>).
© 2009 Microchip Technology Inc.
DS39932C-page 267
PIC18F46J11 FAMILY
REGISTER 18-2:
SSPxCON1: MSSPx CONTROL REGISTER 1 – SPI MODE (ACCESS FC6H/F72h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV(1)
SSPEN(2)
CKP
SSPM3(3)
SSPM2(3)
SSPM1(3)
SSPM0(3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
WCOL: Write Collision Detect bit
1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
bit 6
SSPOV: Receive Overflow Indicator bit(1)
SPI Slave mode:
1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software).
0 = No overflow
bit 5
SSPEN: Master Synchronous Serial Port Enable bit(2)
1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
bit 3-0
SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(3)
0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin
0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note 1:
2:
3:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPxBUF register.
When enabled, this pin must be properly configured as input or output.
Bit combinations not specifically listed here, are either reserved or implemented in I2C™ mode only.
DS39932C-page 268
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
18.3.2
OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
These control bits allow the following to be specified:
•
•
•
•
Master mode (SCKx is the clock output)
Slave mode (SCKx is the clock input)
Clock Polarity (Idle state of SCKx)
Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCKx)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The Buffer Full bit, BF (SSPxSTAT<0>), indicates when
SSPxBUF has been loaded with the received data
(transmission is complete). When the SSPxBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. If the interrupt method is not going to be
used, then software polling can be done to ensure that a
write collision does not occur.
Example 18-1 provides the loading of the SSPxBUF
(SSPxSR) for data transmission.
The SSPxSR is not directly readable or writable and
can only be accessed by addressing the SSPxBUF
register. Additionally, the SSPxSTAT register indicates
the various status conditions.
Each MSSP module consists of a transmit/receive shift
register (SSPxSR) and a buffer register (SSPxBUF).
The SSPxSR shifts the data in and out of the device,
MSb first. The SSPxBUF holds the data that was written
to the SSPxSR until the received data is ready. Once the
8 bits of data have been received, that byte is moved to
the SSPxBUF register. Then, the Buffer Full (BF) detect
bit (SSPxSTAT<0>) and the interrupt flag bit, SSPxIF,
are set. This double-buffering of the received data
(SSPxBUF) allows the next byte to start reception before
reading the data that was just received.
18.3.3
Any write to the SSPxBUF register during transmission/reception of data will be ignored and the Write
Collision Detect bit, WCOL (SSPxCON1<7>), will be set.
User software must clear the WCOL bit so that it can be
determined if the following write(s) to the SSPxBUF
register completed successfully.
The open-drain output option is controlled by the
SPI2OD and SPI1OD bits (ODCON3<1:0>). Setting an
SPIxOD bit configures both SDOx and SCKx pins for the
corresponding open-drain operation.
Note:
The drivers for the SDOx output and SCKx clock pins
can be optionally configured as open-drain outputs.
This feature allows the voltage level on the pin to be
pulled to a higher level through an external pull-up
resistor, provided the SDOx or SCKx pin is not multiplexed with an ANx analog function. This allows the
output to communicate with external circuits without the
need for additional level shifters. For more information,
see Section 9.1.4 “Open-Drain Outputs”.
When the application software is expecting
to receive valid data, the SSPxBUF should
be read before the next byte of transfer
data is written to the SSPxBUF. Application
software should follow this process even
when the current contents of SSPxBUF
are not important.
EXAMPLE 18-1:
LOOP
OPEN-DRAIN OUTPUT OPTION
LOADING THE SSP1BUF (SSP1SR) REGISTER
BTFSS
BRA
MOVF
SSP1STAT, BF
LOOP
SSP1BUF, W
;Has data been received (transmit complete)?
;No
;WREG reg = contents of SSP1BUF
MOVWF
RXDATA
;Save in user RAM, if data is meaningful
MOVF
MOVWF
TXDATA, W
SSP1BUF
;W reg = contents of TXDATA
;New data to xmit
© 2009 Microchip Technology Inc.
DS39932C-page 269
PIC18F46J11 FAMILY
18.3.4
ENABLING SPI I/O
To enable the serial port, MSSP Enable bit, SSPEN
(SSPxCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the
SSPxCON1 registers and then set the SSPEN bit. This
configures the SDIx, SDOx, SCKx and SSx pins as
serial port pins. For the pins to behave as the serial port
function, the appropriate TRIS bits, ANCON/PCFG bits
and Peripheral Pin Select registers (if using MSSP2)
should be correctly initialized prior to setting the
SSPEN bit.
Any MSSP1 serial port function that is not desired may
be overridden by programming the corresponding Data
Direction (TRIS) register to the opposite value. If
individual MSSP2 serial port functions will not be used,
they may be left unmapped.
Note:
A typical SPI serial port initialization process follows:
• Initialize ODCON3 register (optional open-drain
output control)
• Initialize remappable pin functions (if using
MSSP2, see Section 9.7 “Peripheral Pin Select
(PPS)”)
• Initialize SCKx LAT value to desired Idle SCK
level (if master device)
• Initialize SCKx ANCON/PCFG bit (if Slave mode
and multiplexed with ANx function)
• Initialize SCKx TRIS bit as output (Master mode)
or input (Slave mode)
• Initialize SDIx ANCON/PCFG bit (if SDIx is
multiplexed with ANx function)
• Initialize SDIx TRIS bit
• Initialize SSx ANCON/PCFG bit (if Slave mode
and multiplexed with ANx function)
• Initialize SSx TRIS bit (Slave modes)
• Initialize SDOx TRIS bit
• Initialize SSPxSTAT register
• Initialize SSPxCON1 register
• Set SSPEN bit to enable the module
FIGURE 18-2:
18.3.5
When MSSP2 is used in SPI Master
mode, the SCK2 function must be configured as both an output and input in the
PPS module. SCK2 must be initialized as
an output pin (by writing 0x0A to one of the
RPORx registers). Additionally, SCK2IN
must also be mapped to the same pin, by
initializing the RPINR22 register. Failure to
initialize SCK2/SCK2IN as both output
and input will prevent the module from
receiving data on the SDI2 pin, as the
module uses the SCK2IN signal to latch
the received data.
TYPICAL CONNECTION
Figure 18-2 illustrates a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCKx signal.
Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time. Whether
the data is meaningful (or dummy data) depends on the
application software. This leads to three scenarios for
data transmission:
• Master sends valid data – Slave sends dummy
data
• Master sends valid data – Slave sends valid data
• Master sends dummy data – Slave sends valid
data
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xxb
SPI Slave SSPM<3:0> = 010xb
SDOx
SDIx
Serial Input Buffer
(SSPxBUF)
SDIx
Shift Register
(SSPxSR)
MSb
Serial Input Buffer
(SSPxBUF)
LSb
DS39932C-page 270
Shift Register
(SSPxSR)
MSb
SCKx
PROCESSOR 1
SDOx
Serial Clock
LSb
SCKx
PROCESSOR 2
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
18.3.6
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCKx. The master determines
when the slave (Processor 2, Figure 18-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPxBUF register is written to. If the SPI
is only going to receive, the SDOx output could be disabled (programmed as an input). The SSPxSR register
will continue to shift in the signal present on the SDIx
pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPxBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
The CKP is selected by appropriately programming the
CKP bit (SSPxCON1<4>). This then, would give
waveforms for SPI communication as illustrated in
Figure 18-3, Figure 18-5 and Figure 18-6, where the
FIGURE 18-3:
Most Significant Byte (MSB) is transmitted first. In
Master mode, the SPI clock rate (bit rate) is
user-programmable to be one of the following:
•
•
•
•
FOSC/4 (or TCY)
FOSC/16 (or 4 • TCY)
FOSC/64 (or 16 • TCY)
Timer2 output/2
When using the Timer2 output/2 option, the Period
Register 2 (PR2) can be used to determine the SPI bit
rate. However, only PR2 values of 0x01 to 0xFF are
valid in this mode.
Figure 18-3 illustrates the waveforms for Master mode.
When the CKE bit is set, the SDOx data is valid before
there is a clock edge on SCKx. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPxBUF is loaded with the received
data is shown.
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPxBUF
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
4 Clock
Modes
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
SDOx
(CKE = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDOx
(CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDIx
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDIx
(SMP = 1)
bit 7
bit 0
Input
Sample
(SMP = 1)
SSPxIF
SSPxSR to
SSPxBUF
© 2009 Microchip Technology Inc.
Next Q4 Cycle
after Q2↓
DS39932C-page 271
PIC18F46J11 FAMILY
18.3.7
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCKx. When the
last bit is latched, the SSPxIF interrupt flag bit is set.
transmitted byte and becomes a floating output.
External pull-up/pull-down resistors may be desirable
depending on the application.
While in Slave mode, the external clock is supplied by
the external clock source on the SCKx pin. This
external clock must meet the minimum high and low
times as specified in the electrical specifications.
Note 1: When the SPI is in Slave mode with
pin
control
enabled
the
SSx
(SSPxCON1<3:0> = 0100), the SPI
module will reset if the SSx pin is set to
VDD.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device can be
configured to wake-up from Sleep.
2: If the SPI is used in Slave mode with CKE
set, then the SSx pin control must be
enabled.
18.3.8
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SSx pin to
a high level or clearing the SSPEN bit.
SLAVE SELECT
SYNCHRONIZATION
The SSx pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with the SSx pin control
enabled (SSPxCON1<3:0> = 04h). When the SSx pin
is low, transmission and reception are enabled and the
SDOx pin is driven. When the SSx pin goes high, the
SDOx pin is no longer driven, even if in the middle of a
FIGURE 18-4:
To emulate two-wire communication, the SDOx pin can
be connected to the SDIx pin. When the SPI needs to
operate as a receiver, the SDOx pin can be configured
as an input. This disables transmissions from the
SDOx. The SDIx can always be left as an input (SDIx
function) since it cannot create a bus conflict.
SLAVE SYNCHRONIZATION WAVEFORM
SSx
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
SDOx
SDIx
(SMP = 0)
bit 7
bit 6
bit 7
bit 0
bit 0
bit 7
bit 7
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
DS39932C-page 272
Next Q4 Cycle
after Q2↓
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
FIGURE 18-5:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SSx
Optional
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
SDOx
bit 7
SDIx
(SMP = 0)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPxSR to
SSPxBUF
FIGURE 18-6:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SSx
Not Optional
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
Write to
SSPxBUF
SDOx
bit 7
SDIx
(SMP = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
© 2009 Microchip Technology Inc.
Next Q4 Cycle
after Q2↓
DS39932C-page 273
PIC18F46J11 FAMILY
18.3.9
OPERATION IN POWER-MANAGED
MODES
In SPI Master mode, module clocks may be operating
at a different speed than when in full-power mode. In
the case of Sleep mode, all clocks are halted.
18.3.11
BUS MODE COMPATIBILITY
Table 18-1 provides the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
In Idle modes, a clock is provided to the peripherals.
That clock can be from the primary clock source, the
secondary clock (Timer1 oscillator) or the INTOSC
source. See Section 2.3 “Clock Sources and
Oscillator Switching” for additional information.
TABLE 18-1:
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP interrupts are enabled, they can wake the
controller from Sleep mode, or one of the Idle modes,
when the master completes sending data. If an exit
from Sleep or Idle mode is not desired, MSSP
interrupts should be disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the device wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI
Transmit/Receive Shift register. When all 8 bits have
been received, the MSSP interrupt flag bit will be set,
and if enabled, will wake the device.
18.3.10
EFFECTS OF A RESET
SPI BUS MODES
Control Bits State
Standard SPI Mode
Terminology
CKP
CKE
0, 0
0
1
0, 1
0
0
1, 0
1
1
1, 1
1
0
There is also an SMP bit, which controls when the data
is sampled.
18.3.12
SPI CLOCK SPEED AND MODULE
INTERACTIONS
Because MSSP1 and MSSP2 are independent
modules, they can operate simultaneously at different
data rates. Setting the SSPM<3:0> bits of the
SSPxCON1 register determines the rate for the
corresponding module.
An exception is when both modules use Timer2 as a
time base in Master mode. In this instance, any
changes to the Timer2 module’s operation will affect
both MSSP modules equally. If different bit rates are
required for each module, the user should select one of
the other three time base options for one of the
modules.
A Reset disables the MSSP module and terminates the
current transfer.
DS39932C-page 274
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 18-2:
Name
INTCON
REGISTERS ASSOCIATED WITH SPI OPERATION
Bit 7
Bit 6
Bit 5
GIE/GIEH PEIE/GIEL TMR0IE
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
63
PIR1
PMPIF
(2)
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
65
PIE1
PMPIE(2)
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
65
IPR1
PMPIP(2)
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
65
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CTMUIF
TMR3GIF
RTCCIF
65
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CTMUIE
TMR3GIE
RTCCIE
65
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CTMUIP
TMR3GIP
RTCCIP
65
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
66
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
66
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
66
TRISD
SSP1BUF
MSSP1 Receive Buffer/Transmit Register
64
SSPxCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
64
SSPxSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
64
—
—
SPI2OD
SPI1OD
68
SSP2BUF
ODCON3(1)
MSSP2 Receive Buffer/Transmit Register
—
—
—
—
67
Legend: Shaded cells are not used by the MSSP module in SPI mode.
Note 1: Configuration SFR overlaps with default SFR at this address; available only when WDTCON<4> = 1.
2: These bits are only available on 44-pin devices.
© 2009 Microchip Technology Inc.
DS39932C-page 275
PIC18F46J11 FAMILY
18.4
SPI DMA Module
The SPI DMA module contains control logic to allow the
MSSP2 module to perform SPI direct memory access
transfers. This enables the module to quickly transmit
or receive large amounts of data with relatively little
CPU intervention. When the SPI DMA module is used,
MSSP2 can directly read and write to general purpose
SRAM. When the SPI DMA module is not enabled,
MSSP2 functions normally, but without DMA capability.
The SPI DMA module is composed of control logic, a
Destination Receive Address Pointer, a Transmit
Source Address Pointer, an interrupt manager and a
Byte Count register for setting the size of each DMA
transfer. The DMA module may be used with all SPI
Master and Slave modes, and supports both
half-duplex and full-duplex transfers.
18.4.1
I/O PIN CONSIDERATIONS
When enabled, the SPI DMA module uses the MSSP2
module. All SPI related input and output signals related
to MSSP2 are routed through the Peripheral Pin Select
module. The appropriate initialization procedure as
described in Section 18.4.6 “Using the SPI DMA
Module” will need to be followed prior to using the SPI
DMA module. The output pins assigned to the SDO2
and SCK2 functions can optionally be configured as
open-drain outputs, such as for level shifting operations
mentioned in the same section.
18.4.2
RAM TO RAM COPY OPERATIONS
Although the SPI DMA module is primarily intended to
be used for SPI communication purposes, the module
can also be used to perform RAM to RAM copy operations. To do this, configure the module for Full-Duplex
Master mode operation, but assign the SDO2 output
and SDI2 input functions onto the same RPn pin in the
PPS module. This will allow the module to operate in
Loopback mode, providing RAM copy capability.
18.4.3
IDLE AND SLEEP
CONSIDERATIONS
The SPI DMA module remains fully functional when the
microcontroller is in Idle mode.
During normal sleep, the SPI DMA module is not functional and should not be used. To avoid corrupting a
transfer, user firmware should be careful to make
certain that pending DMA operations are complete by
polling the DMAEN bit in the DMACON1 register prior
to putting the microcontroller into Sleep.
DS39932C-page 276
In SPI Slave modes, the MSSP2 module is capable of
transmitting and/or receiving one byte of data while in
Sleep mode. This allows the SSP2IF flag in the PIR3
register to be used as a wake-up source. When the
DMAEN bit is cleared, the SPI DMA module is
effectively disabled, and the MSSP2 module functions
normally, but without DMA capabilities. If the DMAEN
bit is clear prior to entering Sleep, it is still possible to
use the SSP2IF as a wake-up source without any data
loss.
Neither MSSP2 nor the SPI DMA module will provide
any functionality in Deep Sleep. Upon exiting from
Deep Sleep, all of the I/O pins, MSSP2 and SPI DMA
related registers will need to be fully reinitialized before
the SPI DMA module can be used again.
18.4.4
REGISTERS
The SPI DMA engine is enabled and controlled by the
following Special Function Registers:
• DMACON1
• DMACON2
• TXADDRH
• TXADDRL
• RXADDRH
• RXADDRL
• DMABCH
• DMABCL
18.4.4.1
DMACON1
The DMACON1 register is used to select the main
operating mode of the SPI DMA module. The SSCON1
and SSCON0 bits are used to control the slave select
pin.
When MSSP2 is used in SPI Master mode with the SPI
DMA module, SSDMA can be controlled by the DMA
module as an output pin. If MSSP2 will be used to communicate with an SPI slave device that needs the SS
pin to be toggled periodically, the SPI DMA hardware
can automatically be used to deassert SS between
each byte, every two bytes or every four bytes.
Alternatively, user firmware can manually generate
slave select signals with normal general purpose I/O
pins, if required by the slave device(s).
When the TXINC bit is set, the TXADDR register will
automatically increment after each transmitted byte.
Automatic transmit address increment can be disabled
by clearing the TXINC bit. If the automatic transmit
address increment is disabled, each byte which is output on SDO2, will be the same (the contents of the
SRAM pointed to by the TXADDR register) for the
entire DMA transaction.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
When the RXINC bit is set, the RXADDR register will
automatically increment after each received byte. Automatic receive address increment can be disabled by
clearing the RXINC bit. If RXINC is disabled in
Full-Duplex or Half-Duplex Receive modes, all incoming data bytes on SDI2 will overwrite the same memory
location pointed to by the RXADDR register. After the
SPI DMA transaction has completed, the last received
byte will reside in the memory location pointed to by the
RXADDR register.
The SPI DMA module can be used for either half-duplex
receive only communication, half-duplex transmit only
communication or full-duplex simultaneous transmit and
receive operations. All modes are available for both SPI
master and SPI slave configurations. The DUPLEX0
and DUPLEX1 bits can be used to select the desired
operating mode.
The behavior of the DLYINTEN bit varies greatly
depending on the SPI operating mode. For example
behavior for each of the modes, see Figure 18-3
through Figure 18-6.
SPI Slave mode, DLYINTEN = 1: In this mode, an
SSP2IF interrupt will be generated during a transfer if
the time between successful byte transmission events
is longer than the value set by the DLYCYC<3:0> bits
in the DMACON2 register. This interrupt allows slave
firmware to know that the master device is taking an
unusually large amount of time between byte transmissions. For example, this information may be useful for
implementing application-defined communication
protocols involving time-outs if the bus remains Idle for
too long. When DLYINTEN = 1, the DLYLVL<3:0>
interrupts occur normally according to the selected
setting.
SPI Slave mode, DLYINTEN = 0: In this mode, the
time-out based interrupt is disabled. No additional
SSP2IF interrupt events will be generated by the SPI
DMA module, other than those indicated by the
INTLVL<3:0> bits in the DMACON2 register. In this
mode, always set DLYCYC<3:0> = 0000.
© 2009 Microchip Technology Inc.
SPI Master mode, DLYINTEN = 0: The DLYCYC<3:0>
bits in the DMACON2 register determine the amount of
additional inter-byte delay, which is added by the SPI
DMA module during a transfer. The Master mode SS2
output feature may be used.
SPI Master mode, DLYINTEN = 1: The amount of
hardware overhead is slightly reduced in this mode,
and the minimum inter-byte delay is 8 TCY for FOSC/4,
9 TCY for FOSC/16 and 15 TCY for FOSC/64. This mode
can potentially be used to obtain slightly higher
effective SPI bandwidth. In this mode, the SS2 control
feature cannot be used, and should always be disabled
(DMACON1<7:6> = 00). Additionally, the interrupt
generating hardware (used in Slave mode) remains
active. To avoid extraneous SSP2IF interrupt events,
set the DMACON2 delay bits, DLYCYC<3:0> = 1111,
and ensure that the SPI serial clock rate is no slower
than FOSC/64.
In SPI Master modes, the DMAEN bit is used to enable
the SPI DMA module and to initiate an SPI DMA transaction. After user firmware sets the DMAEN bit, the
DMA hardware will begin transmitting and/or receiving
data bytes according to the configuration used. In SPI
Slave modes, setting the DMAEN bit will finish the
initialization steps needed to prepare the SPI DMA
module for communication (which must still be initiated
by the master device).
To avoid possible data corruption, once the DMAEN bit
is set, user firmware should not attempt to modify any
of the MSSP2 or SPI DMA related registers, with the
exception of the INTLVL bits in the DMACON2 register.
If user firmware wants to halt an ongoing DMA transaction, the DMAEN bit can be manually cleared by the
firmware. Clearing the DMAEN bit while a byte is
currently being transmitted will not immediately halt the
byte in progress. Instead, any byte currently in
progress will be completed before the MSSP2 and SPI
DMA modules go back to their Idle conditions. If user
firmware clears the DMAEN bit, the TXADDR,
RXADDR and DMABC registers will no longer update,
and the DMA module will no longer make any
additional read or writes to SRAM; therefore, state
information can be lost.
DS39932C-page 277
PIC18F46J11 FAMILY
REGISTER 18-3:
DMACON1: DMA CONTROL REGISTER 1 (ACCESS F88h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSCON1
SSCON0
TXINC
RXINC
DUPLEX1
DUPLEX0
DLYINTEN
DMAEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
SSCON<1:0>: SSDMA Output Control bits (Master modes only)
11 = SSDMA is asserted for the duration of 4 bytes; DLYINTEN is always reset low
01 = SSDMA is asserted for the duration of 2 bytes; DLYINTEN is always reset low
10 = SSDMA is asserted for the duration of 1 byte; DLYINTEN is always reset low
00 = SSDMA is not controlled by the DMA module; DLYINTEN bit is software programmable
bit 5
TXINC: Transmit Address Increment Enable bit
Allows the transmit address to increment as the transfer progresses.
1 = The transmit address is to be incremented from the initial value of TXADDR<11:0>
0 = The transmit address is always set to the initial value of TXADDR<11:0>
bit 4
RXINC: Receive Address Increment Enable bit
Allows the receive address to increment as the transfer progresses.
1 = The received address is to be incremented from the intial value of RXADDR<11:0>
0 = The received address is always set to the initial value of RXADDR<11:0>
bit 3-2
DUPLEX<1:0>: Transmit/Receive Operating Mode Select bits
10 = SPI DMA operates in Full-Duplex mode, data is simultaneously transmitted and received
01 = DMA operates in Half-Duplex mode, data is transmitted only
00 = DMA operates in Half-Duplex mode, data is received only
bit 1
DLYINTEN: Delay Interrupt Enable bit
Enables the interrupt to be invoked after the number of SCK cycles specified in DLYCYC<2:0> has
elapsed from the latest completed transfer.
1 = The interrupt is enabled, SSCON<1:0> must be set to ‘00’
0 = The interrupt is disabled
bit 0
DMAEN: DMA Operation Start/Stop bit
This bit is set by the users’ software to start the DMA operation. It is reset back to zero by the DMA
engine when the DMA operation is completed or aborted.
1 = DMA is in session
0 = DMA is not in session
DS39932C-page 278
© 2009 Microchip Technology Inc.
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18.4.4.2
DMACON2
The DMACON2 register contains control bits for
controlling interrupt generation and inter-byte delay
behavior. The INTLVL<3:0> bits are used to select when
an SSP2IF interrupt should be generated.The function
of the DLYCYC<3:0> bits depends on the SPI operating
mode (Master/Slave), as well as the DLYINTEN setting.
In SPI Master mode, the DLYCYC<3:0> bits can be used
REGISTER 18-4:
to control how much time the module will Idle between
bytes in a transfer. By default, the hardware requires a
minimum delay of: 8 TCY for FOSC/4, 9 TCY for FOSC/16
and 15 TCY for FOSC/64. Additional delays can be
added with the DLYCYC bits. In SPI Slave modes, the
DLYCYC<3:0> bits may optionally be used to trigger an
additional time-out based interrupt.
DMACON2: DMA CONTROL REGISTER 2 (ACCESS F86h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DLYCYC3
DLYCYC2
DLYCYC1
DLYCYC0
INTLVL3
INTLVL2
INTLVL1
INTLVL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
x = Bit is unknown
DLYCYC<3:0>: Delay Cycle Selection bits
When DLYINTEN = 0, these bits specify the additional delay (above the base overhead of the
hardware) in number of TCY cycles before the SSP2BUF register is written again for the next transfer.
When DLYINTEN = 1, these bits specify the additional delay in number of TCY cycles from the latest
completed transfer before an interrupt to the CPU is invoked. In this case, the delay before the
SSP2BUF register is written again is 1 TCY + (base overhead of hardware).
1111 = Delay time in number of instruction cycles is 2,048 cycles
1110 = Delay time in number of instruction cycles is 1,024 cycles
1101 = Delay time in number of instruction cycles is 896 cycles
1100 = Delay time in number of instruction cycles is 768 cycles
1011 = Delay time in number of instruction cycles is 640 cycles
1010 = Delay time in number of instruction cycles is 512 cycles
1001 = Delay time in number of instruction cycles is 384 cycles
1000 = Delay time in number of instruction cycles is 256 cycles
0111 = Delay time in number of instruction cycles is 128 cycles
0110 = Delay time in number of instruction cycles is 64 cycles
0101 = Delay time in number of instruction cycles is 32 cycles
0100 = Delay time in number of instruction cycles is 16 cycles
0011 = Delay time in number of instruction cycles is 8 cycles
0010 = Delay time in number of instruction cycles is 4 cycles
0001 = Delay time in number of instruction cycles is 2 cycles
0000 = Delay time in number of instruction cycles is 1 cycle
© 2009 Microchip Technology Inc.
DS39932C-page 279
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REGISTER 18-4:
bit 3-0
DMACON2: DMA CONTROL REGISTER 2 (ACCESS F86h) (CONTINUED)
INTLVL<3:0>: Watermark Interrupt Enable bits
These bits specify the amount of remaining data yet to be transferred (transmitted and/or received)
upon which an interrupt is generated.
1111 = Amount of remaining data to be transferred is 576 bytes
1110 = Amount of remaining data to be transferred is 512 bytes
1101 = Amount of remaining data to be transferred is 448 bytes
1100 = Amount of remaining data to be transferred is 384 bytes
1011 = Amount of remaining data to be transferred is 320 bytes
1010 = Amount of remaining data to be transferred is 256 bytes
1001 = Amount of remaining data to be transferred is 192 bytes
1000 = Amount of remaining data to be transferred is 128 bytes
0111 = Amount of remaining data to be transferred is 67 bytes
0110 = Amount of remaining data to be transferred is 32 bytes
0101 = Amount of remaining data to be transferred is 16 bytes
0100 = Amount of remaining data to be transferred is 8 bytes
0011 = Amount of remaining data to be transferred is 4 bytes
0010 = Amount of remaining data to be transferred is 2 bytes
0001 = Amount of remaining data to be transferred is 1 byte
0000 = Transfer complete
DS39932C-page 280
© 2009 Microchip Technology Inc.
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18.4.4.3
DMABCH and DMABCL
The DMABCH and DMABCL register pair forms a 10-bit
Byte Count register, which is used by the SPI DMA
module to send/receive up to 1,024 bytes for each DMA
transaction. When the DMA module is actively running
(DMAEN = 1), the DMA Byte Count register decrements
after each byte is transmitted/received. The DMA transaction will halt and the DMAEN bit will be automatically
cleared by hardware after the last byte has completed.
After a DMA transaction is complete, the DMABC
register will read 0x000.
Prior to initiating a DMA transaction by setting the
DMAEN bit, user firmware should load the appropriate
value into the DMABCH/DMABCL registers. The
DMABC is a “base zero” counter, so the actual number
of bytes which will be transmitted follows in
Equation 18-1.
For example, if user firmware wants to transmit 7 bytes
in one transaction, DMABC should be loaded with
006h. Similarly, if user firmware wishes to transmit
1,024 bytes, DMABC should be loaded with 3FFh.
EQUATION 18-1:
BYTES TRANSMITTED
FOR A GIVEN DMABC
Bytes XMIT ≡ ( DMABC + 1 )
18.4.4.4
18.4.5
The SPI DMA module can read from and transmit data
from all general purpose memory on the device. The SPI
DMA module cannot be used to read from the Special
Function Registers (SFRs) contained in banks 14 and
15.
RXADDRH and RXADDRL
INTERRUPTS
The SPI DMA module alters the behavior of the SSP2IF
interrupt flag. In normal/non-DMA modes, the SSP2IF is
set once after every single byte is transmitted/received
through the MSSP2 module. When MSSP2 is used with
the SPI DMA module, the SSP2IF interrupt flag will be
set according to the user-selected INTLVL<3:0> value
specified in the DMACON2 register. The SSP2IF interrupt condition will also be generated once the SPI DMA
transaction has fully completed, and the DMAEN bit has
been cleared by hardware.
The SSP2IF flag becomes set once the DMA byte count
value indicates that the specified INTLVL has been
reached. For example, if DMACON2<3:0> = 0101
(16 bytes remaining), the SSP2IF interrupt flag will
become set once DMABC reaches 00Fh. If user
firmware then clears the SSP2IF interrupt flag, the flag
will not be set again by the hardware until after all bytes
have been fully transmitted and the DMA transaction is
complete.
Note:
TXADDRH and TXADDRL
The TXADDRH and TXADDRL registers pair together
to form a 12-bit Transmit Source Address Pointer
register. In modes that use TXADDR (Full-Duplex and
Half-Duplex Transmit), the TXADDR will be incremented after each byte is transmitted. Transmitted data
bytes will be taken from the memory location pointed to
by the TXADDR register. The contents of the memory
locations pointed to by TXADDR will not be modified by
the DMA module during a transmission.
18.4.4.5
The SPI DMA module can write received data to all
general purpose memory on the device. The SPI DMA
module cannot be used to modify the Special Function
Registers contained in banks 14 and 15.
User firmware may modify the INTLVL bits
while a DMA transaction is in progress
(DMAEN = 1). If an INTLVL value is
selected which is higher than the actual
remaining number of bytes (indicated by
DMABC + 1), the SSP2IF interrupt flag
will immediately become set.
For example, if DMABC = 00Fh (implying 16 bytes are
remaining) and user firmware writes ‘1111’ to
INTLVL<3:0> (interrupt when 576 bytes remaining),
the SSP2IF interrupt flag will immediately become set.
If user firmware clears this interrupt flag, a new interrupt condition will not be generated until either: user
firmware again writes INTLVL with an interrupt level
higher than the actual remaining level, or the DMA
transaction completes and the DMAEN bit is cleared.
Note:
If the INTLVL bits are modified while a
DMA transaction is in progress, care
should be taken to avoid inadvertently
changing the DLYCYC<3:0> value.
The RXADDRH and RXADDRL register pair together
to form a 12-bit Receive Destination Address Pointer.
In modes that use RXADDR (Full-Duplex and
Half-Duplex Receive), the RXADDR register will be
incremented after each byte is received. Received data
bytes will be stored at the memory location pointed to
by the RXADDR register.
© 2009 Microchip Technology Inc.
DS39932C-page 281
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18.4.6
USING THE SPI DMA MODULE
The following steps would typically be taken to enable
and use the SPI DMA module:
1.
2.
3.
Configure the I/O pins, which will be used by
MSSP2.
a) Assign SCK2, SDO2, SDI2 and SS2 to RPn
pins as appropriate for the SPI mode which
will be used. Only functions which will be
used need to be assigned to a pin.
b) Initialize the associated LATx registers for
the desired Idle SPI bus state.
c) If Open-Drain Output mode on SDO2 and
SCK2 (Master mode) is desired, set
ODCON3<1>.
d) Configure corresponding TRISx bits for
each I/O pin used
Configure and enable MSSP2 for the desired
SPI operating mode.
a) Select the desired operating mode (Master
or Slave, SPI Mode 0, 1, 2 and 3) and
configure the module by writing to the
SSP2STAT and SSP2CON1 registers.
b) Enable MSSP2 by setting SSP2CON1<5> = 1.
Configure the SPI DMA engine.
a) Select the desired operating mode by
writing the appropriate values to
DMACON2 and DMACON1.
b) Initialize the TXADDRH/TXADDRL Pointer
(Full-Duplex or Half-Duplex Transmit Only
mode).
c) Initialize the RXADDRH/RXADDRL Pointer
(Full-Duplex or Half-Duplex Receive Only
mode).
d) Initialize the DMABCH/DMABCL Byte Count
register with the number of bytes to be
transferred in the next SPI DMA operation.
e) Set the DMAEN bit (DMACON1<0>).
4.
Detect the SSP2IF interrupt condition (PIR3<7).
a) If the interrupt was configured to occur at
the completion of the SPI DMA transaction,
the DMAEN bit (DMACON1<0>) will be
clear. User firmware may prepare the
module for another transaction by repeating
steps 3.b through 3.e.
b) If the interrupt was configured to occur prior
to the completion of the SPI DMA transaction, the DMAEN bit may still be set,
indicating the transaction is still in progress.
User firmware would typically use this interrupt condition to begin preparing new data
for the next DMA transaction. Firmware
should not repeat steps 3.b. through 3.e.
until the DMAEN bit is cleared by the
hardware, indicating the transaction is
complete.
Example 18-2 provides example code demonstrating
the initialization process and the steps needed to use
the SPI DMA module to perform a 512-byte
Full-Duplex, Master mode transfer.
In SPI Master modes, this will initiate a DMA
transaction. In SPI Slave modes, this will
complete the initialization process, and the
module will now be ready to begin receiving
and/or transmitting data to the master
device once the master starts the
transaction.
DS39932C-page 282
© 2009 Microchip Technology Inc.
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EXAMPLE 18-2:
512-BYTE SPI MASTER MODE Init AND TRANSFER
;For this example, let's use RP5(RB2) for SCK2,
;RP4(RB1) for SDO2, and RP3(RB0) for SDI2
;Let’s use SPI master mode, CKE = 0, CKP = 0,
;without using slave select signalling.
InitSPIPins:
movlb
bcf
bcf
bcf
bcf
bcf
bsf
0x0F
ODCON3, SPI2OD
;Select bank 15, for access to ODCON3 register
;Let’s not use open drain outputs in this example
LATB, RB2
LATB, RB1
TRISB, RB1
TRISB, RB2
TRISB, RB0
;Initialize our (to be) SCK2
;Initialize our (to be) SDO2
;Make SDO2 output, and drive
;Make SCK2 output, and drive
;SDI2 is an input, make sure
pin low (idle).
pin to an idle state
low
low (idle state)
it is tri-stated
;Now we should unlock the PPS registers, so we can
;assign the MSSP2 functions to our desired I/O pins.
movlb
bcf
0x0E
INTCON, GIE
movlw
movwf
movlw
movwf
bcf
bsf
0x55
EECON2
0xAA
EECON2
PPSCON, IOLOCK
INTCON, GIE
;We may now write to RPINRx and RPORx registers
;May now turn back on interrupts if desired
movlw
movwf
0x03
RPINR21
;0x0A is SCK2 output signal
;Assign the SDI2 function to pin RP3
movlw
movwf
movlw
0x0A
RPOR4
0x04
RPINR22
0x09
RPOR5
PPSCON, IOLOCK
0x0F
;Let’s assign SCK2 output to pin RP4
;RPOR4 maps output signals to RP4 pin
;SCK2 also needs to be configured as an input on the
same pin
;SCK2 input function taken from RP4 pin
;0x09 is SDO2 output
;Assign SDO2 output signal to the RP5 (RB2) pin
;Lock the PPS registers to prevent changes
;Done with PPS registers, bank 15 has other SFRs
InitMSSP2:
clrf
movlw
movwf
bsf
SSP2STAT
b'00000000'
SSP2CON1
SSP2CON1, SSPEN
;CKE = 0, SMP = 0 (sampled at middle of bit)
;CKP = 0, SPI Master mode, Fosc/4
;MSSP2 initialized
;Enable the MSSP2 module
InitSPIDMA:
movlw
movwf
movlw
movwf
b'00111110'
DMACON1
b'11110000'
DMACON2
;Full duplex, RX/TXINC enabled, no SSCON
;DLYINTEN is set, so DLYCYC3:DLYCYC0 = 1111
;Minimum delay between bytes, interrupt
;only once when the transaction is complete
movwf
movlw
movwf
bsf
movlb
© 2009 Microchip Technology Inc.
;Select bank 14 for access to PPS registers
;I/O Pin unlock sequence will not work if CPU
;services an interrupt during the sequence
;Unlock sequence consists of writing 0x55
;and 0xAA to the EECON2 register.
DS39932C-page 283
PIC18F46J11 FAMILY
EXAMPLE 18-2:
512-BYTE SPI MASTER MODE Init AND TRANSFER (CONTINUED)
;Somewhere else in our project, lets assume we have
;allocated some RAM for use as SPI receive and
;transmit buffers.
;
;DestBuf
;
;SrcBuf
;
udata
res
0x500
0x200
res
0x200
PrepareTransfer:
movlw
HIGH(DestBuf)
movwf
RXADDRH
movlw
LOW(DestBuf)
movwf
RXADDRL
;Let’s reserve 0x500-0x6FF for use as our SPI
;receive data buffer in this example
;Lets reserve 0x700-0x8FF for use as our SPI
;transmit data buffer in this example
;Get high byte of DestBuf address (0x05)
;Load upper four bits of the RXADDR register
;Get low byte of the DestBuf address (0x00)
;Load lower eight bits of the RXADDR register
movlw
movwf
movlw
movwf
HIGH(SrcBuf)
TXADDRH
LOW(SrcBuf)
TXADDRL
;Get high byte of SrcBuf address (0x07)
;Load upper four bits of the TXADDR register
;Get low byte of the SrcBuf address (0x00)
;Load lower eight bits of the TXADDR register
movlw
movwf
movlw
movwf
0x01
DMABCH
0xFF
DMABCL
;Lets move 0x200 (512) bytes in one DMA xfer
;Load the upper two bits of DMABC register
;Actual bytes transferred is (DMABC + 1), so
;we load 0x01FF into DMABC to xfer 0x200 bytes
DMACON1, DMAEN
;The SPI DMA module will now begin transferring
;the data taken from SrcBuf, and will store
;received bytes into DestBuf.
BeginXfer:
bsf
;Execute whatever
;CPU is now free to do whatever it wants to
;and the DMA operation will continue without
;intervention, until it completes.
;When the transfer is complete, the SSP2IF flag in
;the PIR3 register will become set, and the DMAEN bit
;is automatically cleared by the hardware.
;The DestBuf (0x500-0x7FF) will contain the received
;data. To start another transfer, firmware will need
;to reinitialize RXADDR, TXADDR, DMABC and then
;set the DMAEN bit.
DS39932C-page 284
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18.5
I2C Mode
18.5.1
The MSSP module in I2C mode fully implements all
master and slave functions (including general call
support), and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications and 7-bit and 10-bit addressing.
Two pins are used for data transfer:
• Serial Clock (SCLx) –
RB4/PMA1/KBI0/SCK1/SCL1/RP7 or
RD0/PMD0/SCL2
• Serial Data (SDAx) –
RB5/PMA0/KBI1/SDI1/SDA1/RP8 or
RD1/PMD1/SDA2
The user must configure these pins as inputs by setting
the associated TRIS bits.
FIGURE 18-7:
MSSPx BLOCK DIAGRAM
(I2C™ MODE)
Internal
Data Bus
Read
Write
SSPxBUF reg
SCLx
Shift
Clock
SSPxSR reg
SDAx
MSb
LSb
Match Detect
Addr Match
Address Mask
Note:
The MSSP module has six registers for I2C operation.
These are:
•
•
•
•
MSSPx Control Register 1 (SSPxCON1)
MSSPx Control Register 2 (SSPxCON2)
MSSPx Status Register (SSPxSTAT)
Serial Receive/Transmit Buffer Register
(SSPxBUF)
• MSSPx Shift Register (SSPxSR) – Not directly
accessible
• MSSPx Address Register (SSPxADD)
• MSSPx 7-Bit Address Mask Register (SSPxMSK)
SSPxCON1, SSPxCON2 and SSPxSTAT are the
control and status registers in I2C mode operation. The
SSPxCON1 and SSPxCON2 registers are readable and
writable. The lower six bits of the SSPxSTAT are
read-only. The upper two bits of the SSPxSTAT are
read/write.
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data
bytes are written to or read from.
SSPxADD contains the slave device address when the
MSSP is configured in I2C Slave mode. When the
MSSP is configured in Master mode, the lower seven
bits of SSPxADD act as the Baud Rate Generator
(BRG) reload value.
SSPxMSK holds the slave address mask value when
the module is configured for 7-Bit Address Masking
mode. While it is a separate register, it shares the same
SFR address as SSPxADD; it is only accessible when
the SSPM<3:0> bits are specifically set to permit
access. Additional details are provided in
Section 18.5.3.4 “7-Bit Address Masking Mode”.
In receive operations, SSPxSR and SSPxBUF
together, create a double-buffered receiver. When
SSPxSR receives a complete byte, it is transferred to
SSPxBUF and the SSPxIF interrupt is set.
SSPxADD reg
Start and
Stop bit Detect
REGISTERS
Set, Reset
S, P bits
(SSPxSTAT reg)
During transmission, the SSPxBUF is not
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list of
multiplexed functions.
© 2009 Microchip Technology Inc.
DS39932C-page 285
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REGISTER 18-5:
R/W-1
SSPxSTAT: MSSPx STATUS REGISTER – I2C™ MODE (ACCESS FC7h/F73h)
R/W-1
SMP
CKE
R-1
R-1
R-1
D/A
(1)
(1)
P
S
R-1
R/W
(2,3)
R-1
R-1
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
bit 6
CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
bit 5
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4
P: Stop bit(1)
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
bit 3
S: Start bit(1)
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
bit 2
R/W: Read/Write Information bit(2,3)
In Slave mode:
1 = Read
0 = Write
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
bit 1
UA: Update Address bit (10-Bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPxADD register
0 = Address does not need to be updated
bit 0
BF: Buffer Full Status bit
In Transmit mode:
1 = SSPxBUF is full
0 = SSPxBUF is empty
In Receive mode:
1 = SSPxBUF is full (does not include the ACK and Stop bits)
0 = SSPxBUF is empty (does not include the ACK and Stop bits)
Note 1:
2:
3:
This bit is cleared on Reset and when SSPEN is cleared.
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or not ACK bit.
ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Active mode.
DS39932C-page 286
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REGISTER 18-6:
R/W-0
SSPxCON1: MSSPx CONTROL REGISTER 1 – I2C™ MODE (ACCESS FC6h/F72h)
R/W-0
WCOL
R/W-0
SSPOV
SSPEN
(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CKP
SSPM3(2)
SSPM2(2)
SSPM1(2)
SSPM0(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a
transmission to be started (must be cleared in software)
0 = No collision
In Slave Transmit mode:
1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in
software)
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5
SSPEN: Master Synchronous Serial Port Enable bit(1)
1 = Enables the serial port and configures the SDAx and SCLx pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4
CKP: SCKx Release Control bit
In Slave mode:
1 = Releases clock
0 = Holds clock low (clock stretch); used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0
SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(2)
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011 = I2C Firmware Controlled Master mode (slave Idle)
1001 = Load SSPxMSK register at SSPxADD SFR address(3,4)
1000 = I2C Master mode, clock = FOSC/(4 * (SSPxADD + 1))
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
Note 1:
2:
3:
4:
When enabled, the SDAx and SCLx pins must be configured as inputs.
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
When SSPM<3:0> = 1001, any reads or writes to the SSPxADD SFR address actually accesses the
SSPxMSK register.
This mode is only available when 7-Bit Address Masking mode is selected (MSSPMSK Configuration bit is ‘1’).
© 2009 Microchip Technology Inc.
DS39932C-page 287
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REGISTER 18-7:
SSPxCON2: MSSPx CONTROL REGISTER 2 –I2C™ MASTER MODE
(ACCESS FC5h/F71h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCEN(3)
ACKSTAT
ACKDT(1)
ACKEN(2)
RCEN(2)
PEN(2)
RSEN(2)
SEN(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GCEN: General Call Enable bit (Slave mode only)(3)
1 = Enable interrupt when a general call address (0000h) is received in the SSPxSR
0 = General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5
ACKDT: Acknowledge Data bit (Master Receive mode only)(1)
1 = Not Acknowledge
0 = Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit(2)
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit;
automatically cleared by hardware
0 = Acknowledge sequence Idle
bit 3
RCEN: Receive Enable bit (Master Receive mode only)(2)
1 = Enables Receive mode for I2C
0 = Receive Idle
bit 2
PEN: Stop Condition Enable bit(2)
1 = Initiates Stop condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Stop condition Idle
bit 1
RSEN: Repeated Start Condition Enable bit(2)
1 = Initiates Repeated Start condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Repeated Start condition Idle
bit 0
SEN: Start Condition Enable bit(2)
1 = Initiates Start condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Start condition Idle
Note 1:
2:
3:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written
(or writes to the SSPxBUF are disabled).
This bit is not implemented in I2C Master mode.
DS39932C-page 288
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 18-8:
SSPxCON2: MSSPx CONTROL REGISTER 2 – I2C™ SLAVE MODE
(ACCESS FC5h/F71h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCEN
ACKSTAT(2)
ADMSK5
ADMSK4
ADMSK3
ADMSK2
ADMSK1
SEN(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GCEN: General Call Enable bit (Slave mode only)
1 = Enables interrupt when a general call address (0000h) is received in the SSPxSR
0 = General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit(2)
Unused in Slave mode.
bit 5-2
ADMSK<5:2>: Slave Address Mask Select bits (5-Bit Address Masking)
1 = Masking of corresponding bits of SSPxADD enabled
0 = Masking of corresponding bits of SSPxADD disabled
bit 1
ADMSK1: Slave Address Least Significant bit(s) Mask Select bit
In 7-Bit Addressing mode:
1 = Masking of SSPxADD<1> only enabled
0 = Masking of SSPxADD<1> only disabled
In 10-Bit Addressing mode:
1 = Masking of SSPxADD<1:0> enabled
0 = Masking of SSPxADD<1:0> disabled
bit 0
SEN: Start Condition Enable/Stretch Enable bit(1)
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1:
2:
If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written
(or writes to the SSPxBUF are disabled).
This bit is unimplemented in I2C Slave mode.
REGISTER 18-9:
SSPxMSK: I2C™ SLAVE ADDRESS MASK REGISTER – 7-BIT MASKING MODE
(ACCESS FC8h/F74h)(1)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
MSK<7:0>: Slave Address Mask Select bits
1 = Masking of corresponding bit of SSPxADD enabled
0 = Masking of corresponding bit of SSPxADD disabled
Note 1:
2:
This register shares the same SFR address as SSPxADD and is only addressable in select MSSP
operating modes. See Section 18.5.3.4 “7-Bit Address Masking Mode” for more details.
MSK0 is not used as a mask bit in 7-bit addressing.
© 2009 Microchip Technology Inc.
DS39932C-page 289
PIC18F46J11 FAMILY
18.5.2
OPERATION
The MSSP module functions are enabled by setting the
MSSP Enable bit, SSPEN (SSPxCON1<5>).
The SSPxCON1 register allows control of the I2C
operation. Four mode selection bits (SSPxCON1<3:0>)
allow one of the following I2C modes to be selected:
2
The SCLx clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter 100 and
parameter 101.
18.5.3.1
Addressing
I C Master mode, clock
I2C Slave mode (7-bit address)
I2C Slave mode (10-bit address)
I2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
• I2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
• I2C Firmware Controlled Master mode, slave is
Idle
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPxSR register. All
incoming bits are sampled with the rising edge of the
clock (SCLx) line. The value of register, SSPxSR<7:1>,
is compared to the value of the SSPxADD register. The
address is compared on the falling edge of the eighth
clock (SCLx) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
Selection of any I2C mode with the SSPEN bit set
forces the SCLx and SDAx pins to be open-drain,
provided these pins are programmed as inputs by
setting the appropriate TRISB or TRISD bits. To ensure
proper operation of the module, pull-up resistors must
be provided externally to the SCLx and SDAx pins.
2.
3.
4.
•
•
•
•
18.5.3
SLAVE MODE
In Slave mode, the SCLx and SDAx pins must be
configured as inputs (TRISB<5:4> set). The MSSP
module will override the input state with the output data
when required (slave-transmitter).
The I2C Slave mode hardware will always generate an
interrupt on an address match. Address masking will
allow the hardware to generate an interrupt for more
than one address (up to 31 in 7-bit addressing and up
to 63 in 10-bit addressing). Through the mode select
bits, the user can also choose to interrupt on Start and
Stop bits.
1.
In 10-Bit Addressing mode, two address bytes need to
be received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPxSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address, the first byte would equal
‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two
MSbs of the address. The sequence of events for 10-bit
addressing is as follows, with steps 7 through 9 for the
slave-transmitter:
1.
When an address is matched, or the data transfer after
an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse
and load the SSPxBUF register with the received value
currently in the SSPxSR register.
2.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
4.
• The Buffer Full bit, BF (SSPxSTAT<0>), was set
before the transfer was received.
• The overflow bit, SSPOV (SSPxCON1<6>), was
set before the transfer was received.
In this case, the SSPxSR register value is not loaded
into the SSPxBUF, but bit, SSPxIF, is set. The BF bit is
cleared by reading the SSPxBUF register, while bit,
SSPOV, is cleared through software.
DS39932C-page 290
The SSPxSR register value is loaded into the
SSPxBUF register.
The Buffer Full bit, BF, is set.
An ACK pulse is generated.
The MSSPx Interrupt Flag bit, SSPxIF, is set
(and interrupt is generated, if enabled) on the
falling edge of the ninth SCLx pulse.
3.
5.
6.
7.
8.
9.
Receive first (high) byte of address (bits,
SSPxIF, BF and UA, are set on address match).
Update the SSPxADD register with second (low)
byte of address (clears bit, UA, and releases the
SCLx line).
Read the SSPxBUF register (clears bit, BF) and
clear flag bit, SSPxIF.
Receive second (low) byte of address (bits,
SSPxIF, BF and UA, are set).
Update the SSPxADD register with the first
(high) byte of address. If match releases SCLx
line, this will clear bit, UA.
Read the SSPxBUF register (clears bit, BF) and
clear flag bit, SSPxIF.
Receive Repeated Start condition.
Receive first (high) byte of address (bits,
SSPxIF and BF, are set).
Read the SSPxBUF register (clears bit, BF) and
clear flag bit, SSPxIF.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
18.5.3.2
Address Masking Modes
Masking an address bit causes that bit to become a
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an interrupt. It is possible to mask more than one address bit at
a time, which greatly expands the number of addresses
Acknowledged.
The I2C slave behaves the same way, whether address
masking is used or not. However, when address masking is used, the I2C slave can Acknowledge multiple
addresses and cause interrupts. When this occurs, it is
necessary to determine which address caused the
interrupt by checking SSPxBUF.
The PIC18F46J11 family of devices is capable of using
two different Address Masking modes in I2C slave
operation: 5-Bit Address Masking and 7-Bit Address
Masking. The Masking mode is selected at device
configuration using the MSSPMSK Configuration bit.
The default device configuration is 7-Bit Address
Masking.
Both Masking modes, in turn, support address masking
of 7-bit and 10-bit addresses. The combination of
Masking modes and addresses provide different
ranges of Acknowledgable addresses for each
combination.
While both Masking modes function in roughly the
same manner, the way they use address masks is
different.
18.5.3.3
5-Bit Address Masking Mode
As the name implies, 5-Bit Address Masking mode uses
an address mask of up to five bits to create a range of
addresses to be Acknowledged, using bits 5 through 1 of
EXAMPLE 18-3:
the incoming address. This allows the module to
Acknowledge up to 31 addresses when using 7-bit
addressing, or 63 addresses with 10-bit addressing (see
Example 18-3). This Masking mode is selected when
the MSSPMSK Configuration bit is programmed (‘0’).
The address mask in this mode is stored in the
SSPxCON2 register, which stops functioning as a control
register in I2C Slave mode (Register 18-8). In 7-Bit
Address Masking mode, address mask bits,
ADMSK<5:1>
(SSPxCON2<5:1>),
mask
the
corresponding address bits in the SSPxADD register. For
any ADMSK bits that are set (ADMSK<n> = 1), the corresponding address bit is ignored (SSPxADD<n> = x).
For the module to issue an address Acknowledge, it is
sufficient to match only on addresses that do not have an
active address mask.
In 10-Bit Address Masking mode, bits, ADMSK<5:2>,
mask the corresponding address bits in the SSPxADD
register. In addition, ADMSK1 simultaneously masks
the two LSbs of the address (SSPxADD<1:0>). For any
ADMSK bits that are active (ADMSK<n> = 1), the corresponding address bit is ignored (SPxADD<n> = x).
Also note, that although in 10-Bit Address Masking
mode, the upper address bits reuse part of the
SSPxADD register bits. The address mask bits do not
interact with those bits; they only affect the lower
address bits.
Note 1: ADMSK1 masks the two Least Significant
bits of the address.
2: The two MSbs of the address are not
affected by address masking.
ADDRESS MASKING EXAMPLES IN 5-BIT MASKING MODE
7-Bit Addressing:
SSPxADD<7:1>= A0h (1010000) (SSPxADD<0> is assumed to be ‘0’)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh
10-Bit Addressing:
SSPxADD<7:0> = A0h (10100000) (The two MSbs of the address are ignored in this example, since
they are not affected by masking)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh,
AEh, AFh
© 2009 Microchip Technology Inc.
DS39932C-page 291
PIC18F46J11 FAMILY
18.5.3.4
7-Bit Address Masking Mode
Unlike 5-Bit Address Masking mode, 7-Bit Address
Masking mode uses a mask of up to eight bits (in 10-bit
addressing) to define a range of addresses than can be
Acknowledged, using the lowest bits of the incoming
address. This allows the module to Acknowledge up to
127 different addresses with 7-bit addressing, or
255 with 10-bit addressing (see Example 18-4). This
mode is the default configuration of the module, and is
selected when MSSPMSK is unprogrammed (‘1’).
The address mask for 7-Bit Address Masking mode is
stored in the SSPxMSK register, instead of the
SSPxCON2 register. SSPxMSK is a separate hardware register within the module, but it is not directly
addressable. Instead, it shares an address in the SFR
space with the SSPxADD register. To access the
SSPxMSK register, it is necessary to select MSSP
mode, ‘1001’ (SSPCON1<3:0> = 1001), and then read
or write to the location of SSPxADD.
To use 7-Bit Address Masking mode, it is necessary to
initialize SSPxMSK with a value before selecting the
I2C Slave Addressing mode. Thus, the required
sequence of events is:
1.
2.
3.
Setting or clearing mask bits in SSPxMSK behaves in
the opposite manner of the ADMSK bits in 5-Bit
Address Masking mode. That is, clearing a bit in
SSPxMSK causes the corresponding address bit to be
masked; setting the bit requires a match in that
position. SSPxMSK resets to all ‘1’s upon any Reset
condition and, therefore, has no effect on the standard
MSSP operation until written with a mask value.
With 7-Bit Address Masking mode, SSPxMSK<7:1>
bits mask the corresponding address bits in the
SSPxADD register. For any SSPxMSK bits that are
active
(SSPxMSK<n> = 0),
the
corresponding
SSPxADD address bit is ignored (SSPxADD<n> = x).
For the module to issue an address Acknowledge, it is
sufficient to match only on addresses that do not have
an active address mask.
With 10-Bit Address Masking mode, SSPxMSK<7:0>
bits mask the corresponding address bits in the
SSPxADD register. For any SSPxMSK bits that are
active (= 0), the corresponding SSPxADD address bit
is ignored (SSPxADD<n> = x).
Note:
The two MSbs of the address are not
affected by address masking.
Select
SSPxMSK
Access
mode
(SSPxCON2<3:0> = 1001).
Write the mask value to the appropriate
SSPxADD register address (FC8h for MSSP1,
F6Eh for MSSP2).
Set the appropriate I2C Slave mode
(SSPxCON2<3:0> = 0111 for 10-bit addressing,
0110 for 7-bit addressing).
EXAMPLE 18-4:
ADDRESS MASKING EXAMPLES IN 7-BIT MASKING MODE
7-Bit Addressing:
SSPxADD<7:1>= 1010 000
SSPxMSK<7:1>= 1111 001
Addresses Acknowledged = A8h, A6h, A4h, A0h
10-Bit Addressing:
SSPxADD<7:0> = 1010 0000 (The two MSbs are ignored in this example since they are not affected)
SSPxMSK<5:1> = 1111 0
Addresses Acknowledged = A8h, A6h, A4h, A0h
DS39932C-page 292
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
18.5.3.5
Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPxSTAT
register is cleared. The received address is loaded into
the SSPxBUF register and the SDAx line is held low
(ACK).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit, BF (SSPxSTAT<0>),
is set or bit, SSPOV (SSPxCON1<6>), is set.
An MSSP interrupt is generated for each data transfer
byte. The interrupt flag bit, SSPxIF, must be cleared in
software. The SSPxSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPxCON2<0> = 1), SCLx will be
held low (clock stretch) following each data transfer.
The clock must be released by setting bit, CKP
(SSPxCON1<4>). See Section 18.5.4 “Clock
Stretching” for more details.
18.5.3.6
Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPxSTAT register is set. The received address is
loaded into the SSPxBUF register. The ACK pulse will
be sent on the ninth bit and pin SCLx is held low regardless of SEN (see Section 18.5.4 “Clock Stretching”
for more details). By stretching the clock, the master
will be unable to assert another clock pulse until the
slave is done preparing the transmit data. The transmit
data must be loaded into the SSPxBUF register, which
also loads the SSPxSR register. Then, the SCLx pin
should be enabled by setting bit, CKP
(SSPxCON1<4>). The eight data bits are shifted out on
the falling edge of the SCLx input. This ensures that the
SDAx signal is valid during the SCLx high time
(Figure 18-10).
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCLx input pulse. If the
SDAx line is high (not ACK), then the data transfer is
complete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets the SSPxSTAT
register) and the slave monitors for another occurrence
of the Start bit. If the SDAx line was low (ACK), the next
transmit data must be loaded into the SSPxBUF
register. Again, the SCLx pin must be enabled by
setting bit, CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPxIF bit must be cleared in software and
the SSPxSTAT register is used to determine the status
of the byte. The SSPxIF bit is set on the falling edge of
the ninth clock pulse.
© 2009 Microchip Technology Inc.
DS39932C-page 293
DS39932C-page 294
2
A6
3
4
A4
5
A3
Receiving Address
A5
6
A2
(CKP does not reset to ‘0’ when SEN = 0)
CKP (SSPxCON1<4>)
SSPOV (SSPxCON1<6>)
BF (SSPxSTAT<0>)
SSPxIF (PIR1<3> or PIR3<7>)
1
SCLx
S
A7
7
A1
8
9
ACK
R/W = 0
1
D7
3
4
D4
5
D3
Receiving Data
D5
Cleared in software
SSPxBUF is read
2
D6
6
D2
7
D1
8
D0
9
ACK
1
D7
2
D6
3
4
D4
5
D3
Receiving Data
D5
6
D2
7
D1
8
D0
Bus master
terminates
transfer
P
SSPOV is set
because SSPxBUF is
still full. ACK is not sent.
9
ACK
FIGURE 18-8:
SDAx
PIC18F46J11 FAMILY
I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
© 2009 Microchip Technology Inc.
© 2009 Microchip Technology Inc.
2
A6
2:
Note 1:
3
A5
4
X
5
A3
6
X
7
X
8
9
ACK
R/W = 0
1
D7
3
D5
4
D4
6
D2
7
D1
8
D0
9
ACK
1
D7
In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt.
5
D3
Receiving Data
Cleared in software
SSPxBUF is read
2
D6
x = Don’t care (i.e., address bit can either be a ‘1’ or a ‘0’).
(CKP does not reset to ‘0’ when SEN = 0)
CKP (SSPxCON1<4>)
SSPOV (SSPxCON1<6>)
BF (SSPxSTAT<0>)
SSPxIF (PIR1<3> or PIR3<7>)
1
SCLx
S
A7
Receiving Address
2
D6
3
D5
4
D4
5
D3
Receiving Data
6
D2
7
D1
8
D0
Bus master
terminates
transfer
P
SSPOV is set
because SSPxBUF is
still full. ACK is not sent.
9
ACK
FIGURE 18-9:
SDAx
PIC18F46J11 FAMILY
I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011
(RECEPTION, 7-BIT ADDRESS)
DS39932C-page 295
DS39932C-page 296
CKP
2
A6
Data in
sampled
1
BF (SSPSTAT<0>)
SSPIF (PIR1<3>)
S
A7
3
4
A4
5
A3
6
A2
Receiving Address
A5
7
A1
8
R/W = 1
9
ACK
4
5
D3
6
D2
Transmitting Data
D4
Cleared in software
3
D5
SSPBUF is written in software
2
D6
CKP is set in software
Clear by reading
SCL held low
while CPU
responds to SSPIF
1
D7
7
8
D0
9
ACK
From SSPIF ISR
D1
1
D7
4
D4
5
D3
6
D2
CKP is set in software
7
8
D0
9
ACK
From SSPIF ISR
D1
Transmitting Data
Cleared in software
3
D5
SSPBUF is written in software
2
D6
P
FIGURE 18-10:
SCL
SDA
PIC18F46J11 FAMILY
I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
© 2009 Microchip Technology Inc.
© 2009 Microchip Technology Inc.
2
1
3
1
5
0
7
A8
8
UA is set indicating that
the SSPxADD needs to be
updated
SSPxBUF is written with
contents of SSPxSR
6
A9
9
A7
2
X
4
5
A3
6
A2
UA is set indicating that
SSPxADD needs to be
updated
Cleared by hardware
when SSPxADD is updated
with low byte of address
7
X
Cleared in software
3
A5
Dummy read of SSPxBUF
to clear BF flag
1
A6
Receive Second Byte of Address
4
5
6
Cleared in software
3
7
Cleared by hardware when
SSPxADD is updated with high
byte of address
2
D3 D2
8
9
1
Note that the Most Significant bits of the address are not affected by the bit masking.
1
D6 D5 D4
2
4
5
6
Cleared in software
3
D3 D2
Receive Data Byte
D1 D0 ACK D7 D6 D5 D4
In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X.X will be Acknowledged and cause an interrupt.
9
D7
Receive Data Byte
3:
8
X
ACK
2:
x = Don’t care (i.e., address bit can either be a ‘1’ or a ‘0’).
(CKP does not reset to ‘0’ when SEN = 0)
CKP (SSPxCON1<4>)
UA (SSPxSTAT<1>)
SSPOV (SSPxCON1<6>)
BF (SSPxSTAT<0>)
Note 1:
4
1
Cleared in software
SSPxIF (PIR1<3> or PIR3<7>)
1
SCLx
S
1
ACK
R/W = 0
Clock is held low until
update of SSPxADD has
taken place
7
8
D1 D0
9
P
Bus master
terminates
transfer
SSPOV is set
because SSPxBUF is
still full. ACK is not sent.
ACK
FIGURE 18-11:
SDAx
Receive First Byte of Address
Clock is held low until
update of SSPxADD has
taken place
PIC18F46J11 FAMILY
I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001
(RECEPTION, 10-BIT ADDRESS)
DS39932C-page 297
DS39932C-page 298
2
1
3
1
4
1
5
0
7
A8
8
UA is set indicating that
the SSPxADD needs to be
updated
SSPxBUF is written with
contents of SSPxSR
6
A9
9
(CKP does not reset to ‘0’ when SEN = 0)
CKP (SSPxCON1<4>)
UA (SSPxSTAT<1>)
SSPOV (SSPxCON1<6>)
BF (SSPxSTAT<0>)
Cleared in software
SSPxIF (PIR1<3> or PIR3<7>)
1
SCLx
S
1
ACK
R/W = 0
A7
2
4
A4
5
A3
6
A2
8
9
A0 ACK
UA is set indicating that
SSPxADD needs to be
updated
Cleared by hardware
when SSPxADD is updated
with low byte of address
7
A1
Cleared in software
3
A5
Dummy read of SSPxBUF
to clear BF flag
1
A6
Receive Second Byte of Address
1
D7
4
5
6
Cleared in software
3
D3 D2
7
8
9
1
2
4
5
6
Cleared in software
3
D3 D2
Receive Data Byte
D1 D0 ACK D7 D6 D5 D4
Cleared by hardware when
SSPxADD is updated with high
byte of address
2
D6 D5 D4
Receive Data Byte
Clock is held low until
update of SSPxADD has
taken place
7
8
D1 D0
9
P
Bus master
terminates
transfer
SSPOV is set
because SSPxBUF is
still full. ACK is not sent.
ACK
FIGURE 18-12:
SDAx
Receive First Byte of Address
Clock is held low until
update of SSPxADD has
taken place
PIC18F46J11 FAMILY
I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
© 2009 Microchip Technology Inc.
© 2009 Microchip Technology Inc.
2
3
1
4
1
CKP (SSPxCON1<4>)
UA (SSPxSTAT<1>)
BF (SSPxSTAT<0>)
5
0
6
7
A9 A8
8
UA is set indicating that
the SSPxADD needs to be
updated
SSPxBUF is written with
contents of SSPxSR
SSPxIF (PIR1<3> or PIR3<7>)
1
S
SCLx
1
Receive First Byte of Address
1
9
ACK
1
3
4
5
Cleared in software
2
7
UA is set indicating that
SSPxADD needs to be
updated
8
A0
Cleared by hardware when
SSPxADD is updated with low
byte of address
6
A6 A5 A4 A3 A2 A1
Receive Second Byte of Address
Dummy read of SSPxBUF
to clear BF flag
A7
9
ACK
2
3
1
4
1
Cleared in software
1
1
5
0
6
8
9
ACK
R/W = 1
1
2
4
5
6
CKP is set in software
9
P
Completion of
data transmission
clears BF flag
8
ACK
Bus master
terminates
transfer
CKP is automatically cleared in hardware, holding SCLx low
7
D4 D3 D2 D1 D0
Cleared in software
3
D7 D6 D5
Transmitting Data Byte
Clock is held low until
CKP is set to ‘1’
Write of SSPxBUF
BF flag is clear
initiates transmit
at the end of the
third address sequence
7
A9 A8
Cleared by hardware when
SSPxADD is updated with high
byte of address.
Dummy read of SSPxBUF
to clear BF flag
Sr
1
Receive First Byte of Address
Clock is held low until
update of SSPxADD has
taken place
FIGURE 18-13:
SDAx
R/W = 0
Clock is held low until
update of SSPxADD has
taken place
PIC18F46J11 FAMILY
I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
DS39932C-page 299
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18.5.4
CLOCK STRETCHING
Both 7-Bit and 10-Bit Slave modes implement
automatic clock stretching during a transmit sequence.
The SEN bit (SSPxCON2<0>) allows clock stretching
to be enabled during receives. Setting SEN will cause
the SCLx pin to be held low at the end of each data
receive sequence.
18.5.4.1
Clock Stretching for 7-Bit Slave
Receive Mode (SEN = 1)
In 7-Bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence, if the BF
bit is set, the CKP bit in the SSPxCON1 register is
automatically cleared, forcing the SCLx output to be
held low. The CKP bit being cleared to ‘0’ will assert
the SCLx line low. The CKP bit must be set in the
user’s ISR before reception is allowed to continue. By
holding the SCLx line low, the user has time to service
the ISR and read the contents of the SSPxBUF before
the master device can initiate another receive
sequence. This will prevent buffer overruns from
occurring (see Figure 18-15).
Note 1: If the user reads the contents of the
SSPxBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
18.5.4.2
18.5.4.3
Clock Stretching for 7-Bit Slave
Transmit Mode
The 7-Bit Slave Transmit mode implements clock
stretching by clearing the CKP bit after the falling edge
of the ninth clock if the BF bit is clear. This occurs
regardless of the state of the SEN bit.
The user’s Interrupt Service Routine (ISR) must set
the CKP bit before transmission is allowed to continue.
By holding the SCLx line low, the user has time to
service the ISR and load the contents of the SSPxBUF
before the master device can initiate another transmit
sequence (see Figure 18-10).
Note 1: If the user loads the contents of
SSPxBUF, setting the BF bit before the
falling edge of the ninth clock, the CKP bit
will not be cleared and clock stretching
will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit.
18.5.4.4
Clock Stretching for 10-Bit Slave
Transmit Mode
In 10-Bit Slave Transmit mode, clock stretching is
controlled during the first two address sequences by
the state of the UA bit, just as it is in 10-Bit Slave
Receive mode. The first two addresses are followed
by a third address sequence, which contains the
high-order bits of the 10-bit address and the R/W bit
set to ‘1’. After the third address sequence is
performed, the UA bit is not set, the module is now
configured in Transmit mode and clock stretching is
controlled by the BF flag as in 7-Bit Slave Transmit
mode (see Figure 18-13).
Clock Stretching for 10-Bit Slave
Receive Mode (SEN = 1)
In 10-Bit Slave Receive mode, during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPxADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
Note:
If the user polls the UA bit and clears it by
updating the SSPxADD register before the
falling edge of the ninth clock occurs, and
if the user has not cleared the BF bit by
reading the SSPxBUF register before that
time, then the CKP bit will still NOT be
asserted low. Clock stretching on the basis
of the state of the BF bit only occurs during
a data sequence, not an address
sequence.
DS39932C-page 300
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
18.5.4.5
Clock Synchronization and CKP bit
When the CKP bit is cleared, the SCLx output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCLx output low until the SCLx output is already
sampled low. Therefore, the CKP bit will not assert the
SCLx line until an external I2C master device has
FIGURE 18-14:
already asserted the SCLx line. The SCLx output will
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCLx. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCLx (see
Figure 18-14).
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDAx
DX – 1
DX
SCLx
CKP
Master device
asserts clock
Master device
deasserts clock
WR
SSPxCON1
© 2009 Microchip Technology Inc.
DS39932C-page 301
DS39932C-page 302
2
A6
CKP (SSPxCON1<4>)
SSPOV (SSPxCON1<6>)
BF (SSPxSTAT<0>)
SSPxIF (PIR1<3> or PIR3<7>)
1
SCLx
S
A7
3
4
A4
5
A3
6
A2
Receiving Address
A5
7
A1
8
9
ACK
R/W = 0
3
4
D4
5
D3
Receiving Data
D5
Cleared in software
2
D6
If BF is cleared
prior to the falling
edge of the 9th clock,
CKP will not be reset
to ‘0’ and no clock
stretching will occur
SSPxBUF is read
1
D7
6
D2
7
D1
9
ACK
1
D7
BF is set after falling
edge of the 9th clock,
CKP is reset to ‘0’ and
clock stretching occurs
8
D0
3
4
D4
5
D3
Receiving Data
D5
CKP
written
to ‘1’ in
software
2
D6
Clock is held low until
CKP is set to ‘1’
6
D2
7
D1
8
D0
Bus master
terminates
transfer
P
SSPOV is set
because SSPxBUF is
still full. ACK is not sent.
9
ACK
Clock is not held low
because ACK = 1
FIGURE 18-15:
SDAx
Clock is not held low
because buffer full bit is
clear prior to falling edge
of 9th clock
PIC18F46J11 FAMILY
I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
© 2009 Microchip Technology Inc.
© 2009 Microchip Technology Inc.
2
1
3
1
4
1
5
0
CKP (SSPxCON1<4>)
UA (SSPxSTAT<1>)
SSPOV (SSPxCON1<6>)
BF (SSPxSTAT<0>)
6
7
A9 A8
8
UA is set indicating that
the SSPxADD needs to be
updated
SSPxBUF is written with
contents of SSPxSR
Cleared in software
SSPxIF (PIR1<3> or PIR3<7>)
1
SCLx
S
1
9
ACK
R/W = 0
A7
2
4
A4
5
A3
6
A2
Cleared in software
3
A5
7
A1
8
A0
Note: An update of the SSPxADD
register before the falling
edge of the ninth clock will
have no effect on UA and
UA will remain set.
UA is set indicating that
SSPxADD needs to be
updated
Cleared by hardware when
SSPxADD is updated with low
byte of address after falling edge
of ninth clock
Dummy read of SSPxBUF
to clear BF flag
1
A6
Receive Second Byte of Address
9
ACK
2
4
5
6
Cleared in software
3
D3 D2
7
8
1
4
5
6
Cleared in software
3
CKP written to ‘1’
in software
2
D3 D2
Receive Data Byte
D7 D6 D5 D4
Note: An update of the SSPxADD register before
the falling edge of the ninth clock will have no
effect on UA and UA will remain set.
9
ACK
Clock is held low until
CKP is set to ‘1’
D1 D0
Cleared by hardware when
SSPxADD is updated with high
byte of address after falling edge
of ninth clock
Dummy read of SSPxBUF
to clear BF flag
1
D7 D6 D5 D4
Receive Data Byte
Clock is held low until
update of SSPxADD has
taken place
7
8
9
Bus master
terminates
transfer
P
SSPOV is set
because SSPxBUF is
still full. ACK is not sent.
D1 D0
ACK
Clock is not held low
because ACK = 1
FIGURE 18-16:
SDAx
Receive First Byte of Address
Clock is held low until
update of SSPxADD has
taken place
PIC18F46J11 FAMILY
I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)
DS39932C-page 303
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18.5.5
GENERAL CALL ADDRESS
SUPPORT
If the general call address matches, the SSPxSR is
transferred to the SSPxBUF, the BF flag bit is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit), the
SSPxIF interrupt flag bit is set.
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
When the interrupt is serviced, the source for the
interrupt can be checked by reading the contents of the
SSPxBUF. The value can be used to determine if the
address was device-specific or a general call address.
In 10-bit mode, the SSPxADD is required to be updated
for the second half of the address to match and the UA
bit is set (SSPxSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-Bit Addressing mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 18-17).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the
General Call Enable bit, GCEN, is enabled
(SSPxCON2<7> set). Following a Start bit detect, 8 bits
are shifted into the SSPxSR and the address is
compared against the SSPxADD. It is also compared to
the general call address and fixed in hardware.
FIGURE 18-17:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7-BIT OR 10-BIT ADDRESSING MODE)
Address is compared to General Call Address
after ACK, set interrupt
SCLx
S
1
2
3
4
5
Receiving Data
R/W = 0
General Call Address
SDAx
ACK D7
6
7
8
9
1
ACK
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
9
SSPxIF
BF (SSPxSTAT<0>)
Cleared in software
SSPxBUF is read
SSPOV (SSPxCON1<6>)
‘0’
GCEN (SSPxCON2<7>)
‘1’
18.5.6
MASTER MODE
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPxCON1 and by setting
the SSPEN bit. In Master mode, the SCLx and SDAx
lines are manipulated by the MSSP hardware if the
TRIS bits are set.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop conditions. The Start (S) and Stop (P) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I2C bus may be taken when the Stop bit is set, or
the bus is Idle, with both the Start and Stop bits clear.
Once Master mode is enabled, the user has six
options.
1.
2.
3.
4.
5.
6.
Assert a Start condition on SDAx and SCLx.
Assert a Repeated Start condition on SDAx and
SCLx.
Write to the SSPxBUF register initiating
transmission of data/address.
Configure the I2C port to receive data.
Generate an Acknowledge condition at the end
of a received byte of data.
Generate a Stop condition on SDAx and SCLx.
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
DS39932C-page 304
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
The following events will cause the MSSP Interrupt
Flag bit, SSPxIF, to be set (and MSSP interrupt, if
enabled):
The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register to
initiate transmission before the Start
condition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPxBUF did not occur.
FIGURE 18-18:
•
•
•
•
•
Start condition
Stop condition
Data transfer byte transmitted/received
Acknowledge transmitted
Repeated Start
MSSPx BLOCK DIAGRAM (I2C™ MASTER MODE)
SSPM<3:0>
SSPxADD<6:0>
Internal
Data Bus
Read
Write
SSPxBUF
SDAx
Baud
Rate
Generator
Shift
Clock
SDAx In
SCLx In
Bus Collision
18.5.6.1
Start bit, Stop bit,
Acknowledge
Generate
Start bit Detect
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
End of XMIT/RCV
I2C Master Mode Operation
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDAx while SCLx outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. S and P conditions
are output to indicate the beginning and the end of a
serial transfer.
© 2009 Microchip Technology Inc.
LSb
Clock Cntl
SCLx
Receive Enable
SSPxSR
MSb
Clock Arbitrate/WCOL Detect
(hold off clock source)
Note:
Set/Reset S, P (SSPxSTAT), WCOL (SSPxCON1)
Set SSPxIF, BCLxIF
Reset ACKSTAT, PEN (SSPxCON2)
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address, followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDAx, while SCLx outputs
the serial clock. Serial data is received 8 bits at a time.
After each byte is received, an Acknowledge bit is
transmitted. S and P conditions indicate the beginning
and end of transmission.
The BRG, used for the SPI mode operation, is used to
set the SCLx clock frequency for either 100 kHz,
400 kHz or 1 MHz I2C operation. See Section 18.5.7
“Baud Rate” for more details.
DS39932C-page 305
PIC18F46J11 FAMILY
A typical transmit sequence would go as follows:
1.
The user generates a Start condition by setting
the Start Enable bit, SEN (SSPxCON2<0>).
2. SSPxIF is set. The MSSP module will wait for
the required start time before any other
operation takes place.
3. The user loads the SSPxBUF with the slave
address to transmit.
4. Address is shifted out of the SDAx pin until all
8 bits are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPxCON2 register (SSPxCON2<6>).
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
7. The user loads the SSPxBUF with 8 bits of data.
8. Data is shifted out the SDAx pin until all 8 bits
are transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPxCON2 register (SSPxCON2<6>).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
11. The user generates a Stop condition by setting
the Stop Enable bit, PEN (SSPxCON2<2>).
12. Interrupt is generated once the Stop condition is
complete.
DS39932C-page 306
18.5.7
BAUD RATE
2
In I C Master mode, the BRG reload value is placed in
the lower seven bits of the SSPxADD register
(Figure 18-19). When a write occurs to SSPxBUF, the
Baud Rate Generator will automatically begin counting.
The BRG counts down to 0 and stops until another
reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and
Q4 clocks. In I2C Master mode, the BRG is reloaded
automatically.
Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCLx pin
will remain in its last state.
Table 18-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
18.5.7.1
Baud Rate and Module
Interdependence
Because this mode derives its basic clock source from
the system clock, any changes to the clock will affect
both modules in the same proportion. It may be
possible to change one or both baud rates back to a
previous value by changing the BRG reload value.
Because MSSP1 and MSSP2 are independent, they
can operate simultaneously in I2C Master mode at
different baud rates. This is done by using different
BRG reload values for each module.
FIGURE 18-19:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
SSPM<3:0>
Reload
SCLx
Control
SSPxADD<6:0>
Reload
BRG Down Counter
CLKO
TABLE 18-3:
FOSC/4
I2C™ CLOCK RATE w/BRG
FOSC
FCY
FCY * 2
BRG Value
FSCL
(2 Rollovers of BRG)
40 MHz
10 MHz
20 MHz
18h
400 kHz(1)
40 MHz
10 MHz
20 MHz
1Fh
312.5 kHz
40 MHz
10 MHz
20 MHz
63h
100 kHz
16 MHz
4 MHz
8 MHz
09h
400 kHz(1)
16 MHz
4 MHz
8 MHz
0Ch
308 kHz
16 MHz
4 MHz
8 MHz
27h
100 kHz
4 MHz
1 MHz
2 MHz
02h
333 kHz(1)
4 MHz
1 MHz
2 MHz
09h
100 kHz
1 MHz
2 MHz
00h
1 MHz(1)
4 MHz
Note 1:
I2C
I2C
The
interface does not conform to the 400 kHz
specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
© 2009 Microchip Technology Inc.
DS39932C-page 307
PIC18F46J11 FAMILY
18.5.7.2
Clock Arbitration
sampled high. When the SCLx pin is sampled high, the
BRG is reloaded with the contents of SSPxADD<6:0>
and begins counting. This ensures that the SCLx high
time will always be at least one BRG rollover count in
the event that the clock is held low by an external
device (Figure 18-20).
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCLx pin (SCLx allowed to float high).
When the SCLx pin is allowed to float high, the BRG is
suspended from counting until the SCLx pin is actually
FIGURE 18-20:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDAx
DX
DX – 1
SCLx allowed to transition high
SCLx deasserted but slave holds
SCLx low (clock arbitration)
SCLx
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCLx is sampled high, reload takes
place and BRG starts its count
BRG
Reload
I2C MASTER MODE START
CONDITION TIMING
Note:
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPxCON2<0>). If the SDAx and
SCLx pins are sampled high, the BRG is reloaded with
the contents of SSPxADD<6:0> and starts its count. If
SCLx and SDAx are both sampled high when the Baud
Rate Generator times out (TBRG), the SDAx pin is
driven low. The action of the SDAx being driven low
while SCLx is high is the Start condition and causes the
Start bit (SSPxSTAT<3>) to be set. Following this, the
BRG is reloaded with the contents of SSPxADD<6:0>
and resumes its count. When the BRG times out
(TBRG), the SEN bit (SSPxCON2<0>) will be
automatically cleared by hardware. The BRG is
suspended, leaving the SDAx line held low and the Start
condition is complete.
18.5.8.1
18.5.8
FIGURE 18-21:
If, at the beginning of the Start condition, the
SDAx and SCLx pins are already sampled
low or if during the Start condition, the SCLx
line is sampled low, before the SDAx line is
driven low, a bus collision occurs, the Bus
Collision Interrupt Flag, BCLxIF, is set, the
Start condition is aborted and the I2C
module is reset into its Idle state.
WCOL Status Flag
If the user writes the SSPxBUF when a Start sequence
is in progress, the WCOL bit is set and the contents of
the buffer are unchanged (the write does not occur).
Note:
Because queueing of events is not
allowed, writing to the lower five bits of
SSPxCON2 is disabled until the Start
condition is complete.
FIRST START BIT TIMING
Write to SEN bit occurs here
Set S bit (SSPxSTAT<3>)
SDAx = 1,
SCLx = 1
TBRG
At completion of Start bit,
hardware clears SEN bit
and sets SSPxIF bit
TBRG
Write to SSPxBUF occurs here
1st bit
SDAx
2nd bit
TBRG
SCLx
TBRG
S
DS39932C-page 308
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
18.5.9
I2C MASTER MODE REPEATED
START CONDITION TIMING
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
A Repeated Start condition occurs when the RSEN bit
(SSPxCON2<1>) is programmed high and the I2C logic
module is in the Idle state. When the RSEN bit is set,
the SCLx pin is asserted low. When the SCLx pin is
sampled low, the BRG is loaded with the contents of
SSPxADD<5:0> and begins counting. The SDAx pin is
released (brought high) for one BRG count (TBRG).
When the BRG times out, and if SDAx is sampled high,
the SCLx pin will be deasserted (brought high). When
SCLx is sampled high, the BRG is reloaded with the
contents of SSPxADD<6:0> and begins counting.
SDAx and SCLx must be sampled high for one TBRG.
This action is then followed by assertion of the SDAx
pin (SDAx = 0) for one TBRG while SCLx is high.
Following this, the RSEN bit (SSPxCON2<1>) will be
automatically cleared and the BRG will not be
reloaded, leaving the SDAx pin held low. As soon as a
Start condition is detected on the SDAx and SCLx pins,
the Start bit (SSPxSTAT<3>) will be set. The SSPxIF bit
will not be set until the BRG has timed out.
2: A bus collision during the Repeated Start
condition occurs if:
• SDAx is sampled low when SCLx
goes from low-to-high.
• SCLx goes low before SDAx is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Immediately following the SSPxIF bit getting set, the
user may write the SSPxBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional 8 bits
of address (10-bit mode) or 8 bits of data (7-bit mode).
18.5.9.1
If the user writes the SSPxBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write does
not occur).
Note:
FIGURE 18-22:
WCOL Status Flag
Because queueing of events is not
allowed, writing of the lower five bits of
SSPxCON2 is disabled until the Repeated
Start condition is complete.
REPEATED START CONDITION WAVEFORM
S bit set by hardware
Write to SSPxCON2 occurs here: SDAx = 1,
SCLx (no change).
SDAx = 1,
SCLx = 1
TBRG
TBRG
At completion of Start bit,
hardware clears RSEN bit
and sets SSPxIF
TBRG
1st bit
SDAx
RSEN bit set by hardware
on falling edge of ninth clock,
end of XMIT
Write to SSPxBUF occurs here
TBRG
SCLx
TBRG
Sr = Repeated Start
© 2009 Microchip Technology Inc.
DS39932C-page 309
PIC18F46J11 FAMILY
18.5.10
I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address, is accomplished by
simply writing a value to the SSPxBUF register. This
action will set the Buffer Full flag bit, BF, and allow the
BRG to begin counting and start the next transmission.
Each bit of address/data will be shifted out onto the
SDAx pin after the falling edge of SCLx is asserted (see
data hold time specification parameter 106). SCLx is
held low for one BRG rollover count (TBRG). Data
should be valid before SCLx is released high (see data
setup time specification parameter 107). When the
SCLx pin is released high, it is held that way for TBRG.
The data on the SDAx pin must remain stable for that
duration and some hold time after the next falling edge
of SCLx. After the eighth bit is shifted out (the falling
edge of the eighth clock), the BF flag is cleared and the
master releases SDAx. This allows the slave device
being addressed to respond with an ACK bit during the
ninth bit time if an address match occurred, or if data
was received properly. The status of ACK is written into
the ACKDT bit on the falling edge of the ninth clock.
If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared; if not, the bit is
set. After the ninth clock, the SSPxIF bit is set and the
master clock (BRG) is suspended until the next data
byte is loaded into the SSPxBUF, leaving SCLx low and
SDAx unchanged (Figure 18-23).
After the write to the SSPxBUF, each bit of the address
will be shifted out on the falling edge of SCLx until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
deassert the SDAx pin, allowing the slave to respond
with an Acknowledge. On the falling edge of the ninth
clock, the master will sample the SDAx pin to see if the
address was recognized by a slave. The status of the
ACK bit is loaded into the ACKSTAT status bit
(SSPxCON2<6>). Following the falling edge of the
ninth clock transmission of the address, the SSPxIF
flag is set, the BF flag is cleared and the BRG is turned
off until another write to the SSPxBUF takes place,
holding SCLx low and allowing SDAx to float.
18.5.10.1
BF Status Flag
In Transmit mode, the BF bit (SSPxSTAT<0>) is set
when the CPU writes to SSPxBUF and is cleared when
all eight bits are shifted out.
18.5.10.2
The user should verify that the WCOL bit is clear after
each write to SSPxBUF to ensure the transfer is correct.
In all cases, WCOL must be cleared in software.
18.5.10.3
ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPxCON2<6>)
is cleared when the slave has sent an Acknowledge
(ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
18.5.11
I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPxCON2<3>).
Note:
The MSSP module must be in an inactive
state before the RCEN bit is set or the
RCEN bit will be disregarded.
The BRG begins counting and on each rollover, the
state of the SCLx pin changes (high-to-low/low-to-high)
and data is shifted into the SSPxSR. After the falling
edge of the eighth clock, the receive enable flag is
automatically cleared, the contents of the SSPxSR are
loaded into the SSPxBUF, the BF flag bit is set, the
SSPxIF flag bit is set and the BRG is suspended from
counting, holding SCLx low. The MSSP is now in Idle
state awaiting the next command. When the buffer is
read by the CPU, the BF flag bit is automatically
cleared. The user can then send an Acknowledge bit at
the end of reception by setting the Acknowledge
Sequence Enable bit, ACKEN (SSPxCON2<4>).
18.5.11.1
BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPxBUF from SSPxSR. It
is cleared when the SSPxBUF register is read.
18.5.11.2
SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPxSR and the BF flag bit is
already set from a previous reception.
18.5.11.3
WCOL Status Flag
If users write the SSPxBUF when a receive is already
in progress (i.e., SSPxSR is still shifting in a data byte),
the WCOL bit is set and the contents of the buffer are
unchanged (the write does not occur).
WCOL Status Flag
If the user writes the SSPxBUF when a transmit is
already in progress (i.e., SSPxSR is still shifting out a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur) after
2 TCY after the SSPxBUF write. If SSPxBUF is rewritten
within 2 TCY, the WCOL bit is set and SSPxBUF is
updated. This may result in a corrupted transfer.
DS39932C-page 310
© 2009 Microchip Technology Inc.
© 2009 Microchip Technology Inc.
S
R/W
PEN
SEN
BF (SSPxSTAT<0>)
SSPxIF
SCLx
SDAx
A6
A5
A4
A3
A2
A1
3
4
5
Cleared in software
2
6
7
8
After Start condition, SEN cleared by hardware
SSPxBUF written
1
9
D7
1
SCLx held low
while CPU
responds to SSPxIF
ACK = 0
R/W = 0
SSPxBUF written with 7-bit address and R/W,
start transmit
A7
Transmit Address to Slave
3
D5
4
D4
5
D3
6
D2
7
D1
8
D0
SSPxBUF is written in software
Cleared in software service routine
from MSSP interrupt
2
D6
Transmitting Data or Second Half
of 10-bit Address
P
ACKSTAT in
SSPxCON2 = 1
Cleared in software
9
ACK
From slave, clear ACKSTAT bit (SSPxCON2<6>)
FIGURE 18-23:
SEN = 0
Write SSPxCON2<0> (SEN = 1),
Start condition begins
PIC18F46J11 FAMILY
I 2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7-BIT OR 10-BIT ADDRESS)
DS39932C-page 311
DS39932C-page 312
S
ACKEN
SSPOV
BF
(SSPxSTAT<0>)
SDAx = 0, SCLx = 1,
while CPU
responds to SSPxIF
SSPxIF
SCLx
SDAx
1
A7
2
4
5
6
Cleared in software
3
A6 A5 A4 A3 A2
Transmit Address to Slave
7
A1
8
9
R/W = 0
ACK
2
3
5
6
7
8
D0
9
ACK
2
3
4
5
6
7
Cleared in software
Set SSPxIF interrupt
at end of Acknowledge
sequence
Data shifted in on falling edge of CLK
1
Cleared in
software
Set SSPxIF at end
of receive
9
ACK is not sent
ACK
Bus master
terminates
transfer
Set P bit
(SSPxSTAT<4>)
and SSPxIF
Set SSPxIF interrupt
at end of Acknowledge
sequence
P
PEN bit = 1
written here
SSPOV is set because
SSPxBUF is still full
8
D0
RCEN cleared
automatically
Set ACKEN, start Acknowledge sequence,
SDAx = ACKDT = 1
D7 D6 D5 D4 D3 D2 D1
Receiving Data from Slave
RCEN = 1, start
next receive
ACK from master,
SDAx = ACKDT = 0
Last bit is shifted into SSPxSR and
contents are unloaded into SSPxBUF
Cleared in software
Set SSPxIF interrupt
at end of receive
4
Cleared in software
1
D7 D6 D5 D4 D3 D2 D1
Receiving Data from Slave
RCEN cleared
automatically
Master configured as a receiver
by programming SSPxCON2<3> (RCEN = 1)
FIGURE 18-24:
SEN = 0
Write to SSPxBUF occurs here,
ACK from Slave
start XMIT
Write to SSPxCON2<0> (SEN = 1),
begin Start condition
Write to SSPxCON2<4>
to start Acknowledge sequence,
SDAx = ACKDT (SSPxCON2<5>) = 0
PIC18F46J11 FAMILY
I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
18.5.12
ACKNOWLEDGE SEQUENCE
TIMING
18.5.13
A Stop bit is asserted on the SDAx pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPxCON2<2>). At the end of a
receive/transmit, the SCLx line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDAx line low. When the
SDAx line is sampled low, the BRG is reloaded and
counts down to 0. When the BRG times out, the SCLx
pin will be brought high and one Baud Rate Generator
rollover count (TBRG) later, the SDAx pin will be deasserted. When the SDAx pin is sampled high while SCLx
is high, the Stop bit (SSPxSTAT<4>) is set. A TBRG
later, the PEN bit is cleared and the SSPxIF bit is set
(Figure 18-26).
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPxCON2<4>). When this bit is set, the SCLx pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDAx pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The BRG
then counts for one rollover period (TBRG) and the SCLx
pin is deasserted (pulled high). When the SCLx pin is
sampled high (clock arbitration), the BRG counts for
TBRG; the SCLx pin is then pulled low. Following this, the
ACKEN bit is automatically cleared, the BRG is turned
off and the MSSP module then goes into an inactive
state (Figure 18-25).
18.5.12.1
18.5.13.1
WCOL Status Flag
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
WCOL Status Flag
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 18-25:
STOP CONDITION TIMING
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPxCON2,
ACKEN = 1, ACKDT = 0
ACKEN automatically cleared
TBRG
TBRG
SDAx
D0
SCLx
8
ACK
9
SSPxIF
SSPxIF set at
the end of receive
Note:
Cleared in
software
TBRG = one Baud Rate Generator period.
FIGURE 18-26:
Cleared in
software
SSPxIF set at the end
of Acknowledge sequence
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG
after SDAx sampled high. P bit (SSPxSTAT<4>) is set
Write to SSPxCON2,
set PEN
PEN bit (SSPxCON2<2>) is cleared by
hardware and the SSPxIF bit is set
Falling edge of
9th clock
TBRG
SCLx
SDAx
ACK
P
TBRG
TBRG
TBRG
SCLx brought high after TBRG
SDAx asserted low before rising edge of clock
to set up Stop condition
Note:
TBRG = one Baud Rate Generator period.
© 2009 Microchip Technology Inc.
DS39932C-page 313
PIC18F46J11 FAMILY
18.5.14
SLEEP OPERATION
2
While in Sleep mode, the I C module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
18.5.15
EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
18.5.16
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Start and
Stop bits are cleared from a Reset or when the MSSP
module is disabled. Control of the I2C bus may be taken
when the P bit (SSPxSTAT<4>) is set, or the bus is Idle,
with both the Start and Stop bits clear. When the bus is
busy, enabling the MSSP interrupt will generate the
interrupt when the Stop condition occurs.
In multi-master operation, the SDAx line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed in
hardware with the result placed in the BCLxIF bit.
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
18.5.17
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDAx and SCLx lines are deasserted and
the SSPxBUF can be written to. When the user services
the bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condition
was in progress when the bus collision occurred, the condition is aborted, the SDAx and SCLx lines are
deasserted and the respective control bits in the
SSPxCON2 register are cleared. When the user services
the bus collision Interrupt Service Routine (ISR), and if
the I2C bus is free, the user can resume communication
by asserting a Start condition.
The master will continue to monitor the SDAx and SCLx
pins. If a Stop condition occurs, the SSPxIF bit will be set.
A write to the SSPxBUF will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
The states where arbitration can be lost are:
•
•
•
•
•
puts a ‘1’ on SDAx, by letting SDAx float high and
another master asserts a ‘0’. When the SCLx pin floats
high, data should be stable. If the expected data on
SDAx is a ‘1’ and the data sampled on the SDAx pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLxIF, and reset the
I2C port to its Idle state (Figure 18-27).
MULTI -MASTER
COMMUNICATION, BUS COLLISION
AND BUS ARBITRATION
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus
can be taken when the Stop bit is set in the SSPxSTAT
register, or the bus is Idle and the Start and Stop bits
are cleared.
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the
SDAx pin, arbitration takes place when the master out-
FIGURE 18-27:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes
while SCLx = 0
SDAx line pulled low
by another source
SDAx released
by master
Sample SDAx. While SCLx is high,
data doesn’t match what is driven
by the master;
bus collision has occurred
SDAx
SCLx
Set bus collision
interrupt (BCLxIF)
BCLxIF
DS39932C-page 314
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
18.5.17.1
Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a)
b)
SDAx or SCLx is sampled low at the beginning
of the Start condition (Figure 18-28).
SCLx is sampled low before SDAx is asserted
low (Figure 18-29).
During a Start condition, both the SDAx and the SCLx
pins are monitored.
If the SDAx pin is sampled low during this count, the
BRG is reset and the SDAx line is asserted early
(Figure 18-30). If, however, a ‘1’ is sampled on the
SDAx pin, the SDAx pin is asserted low at the end of
the BRG count. The BRG is then reloaded and counts
down to 0. If the SCLx pin is sampled as ‘0’ during this
time, a bus collision does not occur. At the end of the
BRG count, the SCLx pin is asserted low.
Note:
If the SDAx pin is already low, or the SCLx pin is
already low, then all of the following occur:
• The Start condition is aborted
• The BCLxIF flag is set
• The MSSP module is reset to its inactive state
(Figure 18-28)
The Start condition begins with the SDAx and SCLx
pins deasserted. When the SDAx pin is sampled high,
the BRG is loaded from SSPxADD<6:0> and counts
down to 0. If the SCLx pin is sampled low while SDAx
is high, a bus collision occurs because it is assumed
that another master is attempting to drive a data ‘1’
during the Start condition.
FIGURE 18-28:
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDAx before the other.
This condition does not cause a bus collision because the two masters must be
allowed to arbitrate the first address
following the Start condition. If the address
is the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
BUS COLLISION DURING START CONDITION (SDAx ONLY)
SDAx goes low before the SEN bit is set.
Set BCLxIF,
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
SDAx
SCLx
Set SEN, enable Start
condition if SDAx = 1, SCLx = 1
SEN cleared automatically because of bus collision.
MSSPx module reset into Idle state.
SEN
BCLxIF
SDAx sampled low before
Start condition. Set BCLxIF.
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
SSPxIF and BCLxIF are
cleared in software
S
SSPxIF
SSPxIF and BCLxIF are
cleared in software
© 2009 Microchip Technology Inc.
DS39932C-page 315
PIC18F46J11 FAMILY
FIGURE 18-29:
BUS COLLISION DURING START CONDITION (SCLx = 0)
SDAx = 0, SCLx = 1
TBRG
TBRG
SDAx
Set SEN, enable Start
sequence if SDAx = 1, SCLx = 1
SCLx
SCLx = 0 before SDAx = 0,
bus collision occurs. Set BCLxIF.
SEN
SCLx = 0 before BRG time-out,
bus collision occurs. Set BCLxIF.
BCLxIF
Interrupt cleared
in software
S
‘0’
‘0’
SSPxIF
‘0’
‘0’
FIGURE 18-30:
BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION
SDAx = 0, SCLx = 1
Set S
Less than TBRG
SDAx
SCLx
TBRG
SDAx pulled low by other master.
Reset BRG and assert SDAx.
S
SCLx pulled low after BRG
time-out
SEN
BCLxIF
Set SSPxIF
Set SEN, enable Start
sequence if SDAx = 1, SCLx = 1
‘0’
S
SSPxIF
SDAx = 0, SCLx = 1,
set SSPxIF
DS39932C-page 316
Interrupts cleared
in software
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
18.5.17.2
Bus Collision During a Repeated
Start Condition
If SDAx is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, see
Figure 18-31). If SDAx is sampled high, the BRG is
reloaded and begins counting. If SDAx goes from
high-to-low before the BRG times out, no bus collision
occurs because no two masters can assert SDAx at
exactly the same time.
During a Repeated Start condition, a bus collision
occurs if:
a)
b)
A low level is sampled on SDAx when SCLx
goes from a low level to a high level.
SCLx goes low before SDAx is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
If SCLx goes from high-to-low before the BRG times
out and SDAx has not already been asserted, a bus
collision occurs. In this case, another master is
attempting to transmit a data ‘1’ during the Repeated
Start condition (see Figure 18-32).
When the user deasserts SDAx and the pin is allowed
to float high, the BRG is loaded with SSPxADD<6:0>
and counts down to 0. The SCLx pin is then deasserted
and when sampled high, the SDAx pin is sampled.
FIGURE 18-31:
If, at the end of the BRG time-out, both SCLx and SDAx
are still high, the SDAx pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCLx pin, the SCLx pin is
driven low and the Repeated Start condition is complete.
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDAx
SCLx
Sample SDAx when SCLx goes high.
If SDAx = 0, set BCLxIF and release SDAx and SCLx.
RSEN
BCLxIF
Cleared in software
S
‘0’
SSPxIF
‘0’
FIGURE 18-32:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDAx
SCLx
BCLxIF
SCLx goes low before SDAx,
set BCLxIF. Release SDAx and SCLx.
Interrupt cleared
in software
RSEN
S
‘0’
SSPxIF
© 2009 Microchip Technology Inc.
DS39932C-page 317
PIC18F46J11 FAMILY
18.5.17.3
Bus Collision During a Stop
Condition
The Stop condition begins with SDAx asserted low.
When SDAx is sampled low, the SCLx pin is allowed to
float. When the pin is sampled high (clock arbitration),
the BRG is loaded with SSPxADD<6:0> and counts
down to 0. After the BRG times out, SDAx is sampled. If
SDAx is sampled low, a bus collision has occurred. This
is due to another master attempting to drive a data ‘0’
(Figure 18-33). If the SCLx pin is sampled low before
SDAx is allowed to float high, a bus collision occurs. This
is another case of another master attempting to drive a
data ‘0’ (Figure 18-34).
Bus collision occurs during a Stop condition if:
a)
b)
After the SDAx pin has been deasserted and
allowed to float high, SDAx is sampled low after
the BRG has timed out.
After the SCLx pin is deasserted, SCLx is
sampled low before SDAx goes high.
FIGURE 18-33:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG
TBRG
SDAx sampled
low after TBRG,
set BCLxIF
TBRG
SDAx
SDAx asserted low
SCLx
PEN
BCLxIF
P
‘0’
SSPxIF
‘0’
FIGURE 18-34:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDAx
Assert SDAx
SCLx
SCLx goes low before SDAx goes high,
set BCLxIF
PEN
BCLxIF
P
‘0’
SSPxIF
‘0’
DS39932C-page 318
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 18-4:
Name
REGISTERS ASSOCIATED WITH I2C™ OPERATION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
63
PIR1
PMPIF(3)
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
65
PIE1
PMPIE(3)
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
65
IPR1
PMPIP
(3)
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
65
PIR2
OSCFIF
CM2IF
CM1IF
—
BCL1IF
LVDIF
TMR3IF
CCP2IF
65
PIE2
OSCFIE
CM2IE
CM1IE
—
BCL1IE
LVDIE
TMR3IE
CCP2IE
65
IPR2
OSCFIP
CM2IP
CM1IP
—
BCL1IP
LVDIP
TMR3IP
CCP2IP
65
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CTMUIF
TMR3GIF
RTCIF
65
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CTMUIE
TMR3GIE
RTCIE
65
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CTMUIP
TMR3GIP
RTCIP
65
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
66
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
66
SSP1BUF
MSSP1 Receive Buffer/Transmit Register
SSPxADD
MSSP1 Address Register (I2C™ Slave mode), MSSP1 Baud Rate Reload Register (I2C Master mode)
64
64, 67
SSPxMSK(1)
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
64, 67
SSPxCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
64, 67
SSPxCON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
64, 67
GCEN
SSPxSTAT
SMP
(2)
ACKSTAT ADMSK5
CKE
(2)
ADMSK4
D/A
P
(2)
ADMSK3
S
(2)
ADMSK2
R/W
(2)
ADMSK1
UA
SEN
BF
64, 67
SSP2BUF
MSSP2 Receive Buffer/Transmit Register
67
SSP2ADD
MSSP2 Address Register (I2C Slave mode), MSSP2 Baud Rate Reload Register (I2C Master mode)
67
Legend:
Note 1:
2:
3:
— = unimplemented, read as ‘0’. Shaded cells are not used by the MSSPx module in I2C™ mode.
SSPxMSK shares the same address in SFR space as SSPxADD, but is only accessible in certain I2C Slave mode
operations in 7-Bit Masking mode. See Section 18.5.3.4 “7-Bit Address Masking Mode” for more details.
Alternate bit definitions for use in I2C Slave mode operations only.
These bits are only available on 44-pin devices.
© 2009 Microchip Technology Inc.
DS39932C-page 319
PIC18F46J11 FAMILY
NOTES:
DS39932C-page 320
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
19.0
ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is one of two
serial I/O modules. (Generically, the EUSART is also
known as a Serial Communications Interface or SCI.)
The EUSART can be configured as a full-duplex
asynchronous system that can communicate with
peripheral devices, such as CRT terminals and
personal computers. It can also be configured as a
half-duplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs and so on.
The Enhanced USART module implements additional
features, including automatic baud rate detection and
calibration, automatic wake-up on Sync Break reception and 12-bit Break character transmit. These make it
ideally suited for use in Local Interconnect Network bus
(LIN bus) systems.
All members of the PIC18F46J11 family are equipped
with two independent EUSART modules, referred to as
EUSART1 and EUSART2. They can be configured in
the following modes:
• Asynchronous (full-duplex) with:
- Auto-wake-up on character reception
- Auto-baud calibration
- 12-bit Break character transmission
• Synchronous – Master (half-duplex) with
selectable clock polarity
• Synchronous – Slave (half-duplex) with selectable
clock polarity
The pins of EUSART1 and EUSART2 are multiplexed
with the functions of PORTC (RC6/PMA5/TX1/CK1/RP17
and RC7/PMA4/RX1/DT1/SDO1/RP18) and remapped
(RPn1/TX2/CK2 and RPn2/RX2/DT2), respectively. In
order to configure these pins as an EUSART:
• For EUSART1:
- SPEN bit (RCSTA1<7>) must be set (= 1)
- TRISC<7> bit must be set (= 1)
- TRISC<6> bit must be cleared (= 0) for
Asynchronous and Synchronous Master
modes
- TRISC<6> bit must be set (= 1) for
Synchronous Slave mode
• For EUSART2:
- SPEN bit (RCSTA2<7>) must be set (= 1)
- TRIS bit for RPn2/RX2/DT2 = 1
- TRIS bit for RPn1/TX2/CK2 = 0 for
Asynchronous and Synchronous Master
modes
- TRISC<6> bit must be set (= 1) for
Synchronous Slave mode
Note:
The EUSART control will automatically
reconfigure the pin from input to output as
needed.
The TXx/CKx I/O pins have an optional open-drain
output capability. By default, when this pin is used by
the EUSART as an output, it will function as a standard
push-pull CMOS output. The TXx/CKx I/O pins’
open-drain, output feature can be enabled by setting
the corresponding UxOD bit in the ODCON2 register.
For more details, see Section 18.3.3 “Open-Drain
Output Option”.
The operation of each Enhanced USART module is
controlled through three registers:
• Transmit Status and Control (TXSTAx)
• Receive Status and Control (RCSTAx)
• Baud Rate Control (BAUDCONx)
These are covered in detail in Register 19-1,
Register 19-2 and Register 19-3, respectively.
Note:
© 2009 Microchip Technology Inc.
Throughout this section, references to
register and bit names that may be associated with a specific EUSART module are
referred to generically by the use of ‘x’ in
place of the specific module number.
Thus, “RCSTAx” might refer to the
Receive Status register for either
EUSART1 or EUSART2.
DS39932C-page 321
PIC18F46J11 FAMILY
REGISTER 19-1:
TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER (ACCESS FADh/FA8h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-1
R/W-0
CSRC
TX9
TXEN(1)
SYNC
SENDB
BRGH
TRMT
TX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6
TX9: 9-Bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5
TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4
SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3
SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care.
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode.
bit 1
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0
TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1:
SREN/CREN overrides TXEN in Sync mode.
DS39932C-page 322
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 19-2:
RCSTAx: RECEIVE STATUS AND CONTROL REGISTER (ACCESS FACh/F9Ch)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-x
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6
RX9: 9-Bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-Bit (RX9 = 1):
1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 9-Bit (RX9 = 0):
Don’t care.
bit 2
FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREGx register and receiving next valid byte)
0 = No framing error
bit 1
OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0
RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
© 2009 Microchip Technology Inc.
DS39932C-page 323
PIC18F46J11 FAMILY
REGISTER 19-3:
BAUDCONx: BAUD RATE CONTROL REGISTER (ACCESS F7Eh/F7Ch)
R/W-0
R-1
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
ABDOVF
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
ABDOVF: Auto-Baud Acquisition Rollover Status bit
1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software)
0 = No BRG rollover has occurred
bit 6
RCIDL: Receive Operation Idle Status bit
1 = Receive operation is Idle
0 = Receive operation is active
bit 5
RXDTP: Data/Receive Polarity Select bit
Asynchronous mode:
1 = Receive data (RXx) is inverted (active-low)
0 = Receive data (RXx) is not inverted (active-high)
Synchronous mode:
1 = Data (DTx) is inverted (active-low)
0 = Data (DTx) is not inverted (active-high)
bit 4
TXCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
1 = Idle state for transmit (TXx) is a low level
0 = Idle state for transmit (TXx) is a high level
Synchronous mode:
1 = Idle state for clock (CKx) is a high level
0 = Idle state for clock (CKx) is a low level
bit 3
BRG16: 16-Bit Baud Rate Register Enable bit
1 = 16-bit Baud Rate Generator – SPBRGHx and SPBRGx
0 = 8-bit Baud Rate Generator – SPBRGx only (Compatible mode), SPBRGHx value ignored
bit 2
Unimplemented: Read as ‘0’
bit 1
WUE: Wake-up Enable bit
Asynchronous mode:
1 = EUSART will continue to sample the RXx pin – interrupt generated on falling edge; bit cleared in
hardware on following rising edge
0 = RXx pin not monitored or rising edge detected
Synchronous mode:
Unused in this mode.
bit 0
ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Enable baud rate measurement on the next character; requires reception of a Sync field (55h);
cleared in hardware upon completion
0 = Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode.
DS39932C-page 324
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
19.1
Baud Rate Generator (BRG)
The BRG is a dedicated, 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>)
selects 16-bit mode.
Writing a new value to the SPBRGHx:SPBRGx
registers causes the BRG timer to be reset (or cleared).
This ensures the BRG does not wait for a timer
overflow before outputting the new baud rate.
19.1.1
OPERATION IN POWER-MANAGED
MODES
The SPBRGHx:SPBRGx register pair controls the period
of a free-running timer. In Asynchronous mode, bits,
BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>),
also control the baud rate. In Synchronous mode, BRGH
is ignored.
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRGx register pair.
Table 19-1 provides the formula for computation of the
baud rate for different EUSART modes, which only apply
in Master mode (internally generated clock).
19.1.2
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGHx:SPBRGx registers can
be calculated using the formulas in Table 19-1. From
this, the error in baud rate can be determined. An
example calculation is provided in Example 19-1.
Typical baud rates and error values for the various
Asynchronous modes are provided in Table 19-2. It
may be advantageous to use the high baud rate
(BRGH = 1) or the 16-bit BRG to reduce the baud rate
error, or achieve a slow baud rate for a fast oscillator
frequency.
TABLE 19-1:
SAMPLING
The
data
on
the
RXx
pin
(either
RC7/PMA4/RX1/DT1/SDO1/RP18 or RPn2/RX2/DT2)
is sampled three times by a majority detect circuit to
determine if a high or a low level is present at the RXx
pin.
BAUD RATE FORMULAS
Configuration Bits
BRG/EUSART Mode
Baud Rate Formula
8-bit/Asynchronous
FOSC/[64 (n + 1)]
SYNC
BRG16
BRGH
0
0
0
0
0
1
8-bit/Asynchronous
0
1
0
16-bit/Asynchronous
0
1
1
16-bit/Asynchronous
1
0
x
8-bit/Synchronous
1
1
x
16-bit/Synchronous
FOSC/[16 (n + 1)]
FOSC/[4 (n + 1)]
Legend: x = Don’t care, n = value of SPBRGHx:SPBRGx register pair
© 2009 Microchip Technology Inc.
DS39932C-page 325
PIC18F46J11 FAMILY
EXAMPLE 19-1:
CALCULATING BAUD RATE ERROR
For a device with Fosc of 16 MHz, desired baud rate of 9600, Asynchronous mode, and
8-bit BRG:
Desired Baud Rate = Fosc/(64 ([SPBRGHx:SPBRGx] + 1))
Solving for SPBRGHx:SPBRGx:
X = ((Fosc/Desired Baud Rate)/64) – 1
= ((16000000/9600)/64) – 1
= [25.042] = 25
Calculated Baud Rate=16000000/(64 (25 + 1))
= 9615
Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%
TABLE 19-2:
Name
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
TXSTAx
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
65
RCSTAx
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
65
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN
66
BAUDCONx ABDOVF
SPBRGHx
EUSARTx Baud Rate Generator Register High Byte
66
SPBRGx
EUSARTx Baud Rate Generator Register Low Byte
65
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
DS39932C-page 326
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 19-3:
BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
Actual
Rate
(K)
FOSC = 10.000 MHz
Actual
Rate
(K)
FOSC = 8.000 MHz
Actual
Rate
(K)
Actual
Rate
(K)
%
Error
0.3
—
—
—
—
—
—
—
—
—
—
—
—
1.2
—
—
—
1.221
1.73
255
1.202
0.16
129
1.201
-0.16
103
2.4
2.441
1.73
255
2.404
0.16
129
2.404
0.16
64
2.403
-0.16
51
9.6
9.615
0.16
64
9.766
1.73
31
9.766
1.73
15
9.615
-0.16
12
19.2
19.531
1.73
31
19.531
1.73
15
19.531
1.73
7
—
—
—
57.6
56.818
-1.36
10
62.500
8.51
4
52.083
-9.58
2
—
—
—
115.2
125.000
8.51
4
104.167
-9.58
2
78.125
-32.18
1
—
—
—
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
(decimal)
Actual
Rate
(K)
0.16
207
0.300
-0.16
103
0.300
-0.16
51
0.16
51
1.201
-0.16
25
1.201
-0.16
12
2.404
0.16
25
2.403
-0.16
12
—
—
—
9.6
8.929
-6.99
6
—
—
—
—
—
—
19.2
20.833
8.51
2
—
—
—
—
—
—
57.6
62.500
8.51
0
—
—
—
—
—
—
115.2
62.500
-45.75
0
—
—
—
—
—
—
Actual
Rate
(K)
%
Error
0.3
0.300
1.2
1.202
2.4
SPBRG
value
%
Error
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
SPBRG
value
(decimal)
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
(decimal)
Actual
Rate
(K)
%
Error
—
—
—
—
—
—
—
—
—
9.6
9.766
1.73
19.2
19.231
57.6
58.140
115.2
113.636
FOSC = 10.000 MHz
(decimal)
Actual
Rate
(K)
%
Error
—
—
—
—
—
—
—
—
—
255
9.615
0.16
0.16
129
19.231
0.94
42
56.818
-1.36
21
113.636
-1.36
Actual
Rate
(K)
%
Error
0.3
—
1.2
—
2.4
SPBRG
value
FOSC = 8.000 MHz
(decimal)
Actual
Rate
(K)
%
Error
—
—
—
—
—
—
—
—
—
2.441
1.73
255
2.403
-0.16
207
129
9.615
0.16
64
9615.
-0.16
51
0.16
64
19.531
1.73
31
19.230
-0.16
25
-1.36
21
56.818
-1.36
10
55.555
3.55
8
10
125.000
8.51
4
—
—
—
SPBRG
value
SPBRG
value
SPBRG
value
(decimal)
—
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)
FOSC = 4.000 MHz
Actual
Rate
(K)
%
Error
FOSC = 2.000 MHz
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3
—
—
—
—
—
—
0.300
-0.16
207
1.2
1.202
0.16
207
1.201
-0.16
103
1.201
-0.16
51
2.4
2.404
0.16
103
2.403
-0.16
51
2.403
-0.16
25
9.6
9.615
0.16
25
9.615
-0.16
12
—
—
—
19.2
19.231
0.16
12
—
—
—
—
—
—
57.6
62.500
8.51
3
—
—
—
—
—
—
115.2
125.000
8.51
1
—
—
—
—
—
—
© 2009 Microchip Technology Inc.
DS39932C-page 327
PIC18F46J11 FAMILY
TABLE 19-3:
BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
(K)
FOSC = 40.000 MHz
Actual
Rate
(K)
%
Error
FOSC = 20.000 MHz
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
FOSC = 10.000 MHz
(decimal)
Actual
Rate
(K)
SPBRG
value
%
Error
FOSC = 8.000 MHz
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
SPBRG
value
(decimal)
0.3
0.300
0.00
8332
0.300
0.02
4165
0.300
0.02
2082
0.300
-0.04
1.2
1.200
0.02
2082
1.200
-0.03
1041
1.200
-0.03
520
1.201
-0.16
1665
415
2.4
2.402
0.06
1040
2.399
-0.03
520
2.404
0.16
259
2.403
-0.16
207
9.6
9.615
0.16
259
9.615
0.16
129
9.615
0.16
64
9.615
-0.16
51
19.2
19.231
0.16
129
19.231
0.16
64
19.531
1.73
31
19.230
-0.16
25
57.6
58.140
0.94
42
56.818
-1.36
21
56.818
-1.36
10
55.555
3.55
8
115.2
113.636
-1.36
21
113.636
-1.36
10
125.000
8.51
4
—
—
—
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
(decimal)
Actual
Rate
(K)
%
Error
0.04
832
0.300
0.16
207
1.201
2.404
0.16
103
9.6
9.615
0.16
19.2
19.231
57.6
62.500
115.2
125.000
FOSC = 1.000 MHz
(decimal)
Actual
Rate
(K)
%
Error
-0.16
415
0.300
-0.16
-0.16
103
1.201
-0.16
51
2.403
-0.16
51
2.403
-0.16
25
25
9.615
-0.16
12
—
—
—
0.16
12
—
—
—
—
—
—
8.51
3
—
—
—
—
—
—
8.51
1
—
—
—
—
—
—
Actual
Rate
(K)
%
Error
0.3
0.300
1.2
1.202
2.4
SPBRG
value
SPBRG
value
SPBRG
value
(decimal)
207
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
(decimal)
Actual
Rate
(K)
%
Error
0.00
33332
0.300
0.00
8332
1.200
0.02
4165
Actual
Rate
(K)
%
Error
0.3
0.300
1.2
1.200
2.4
2.400
SPBRG
value
FOSC = 10.000 MHz
(decimal)
Actual
Rate
(K)
%
Error
0.00
16665
0.300
0.02
4165
1.200
2.400
0.02
2082
2.402
SPBRG
value
FOSC = 8.000 MHz
(decimal)
Actual
Rate
(K)
%
Error
0.00
8332
0.300
-0.01
6665
0.02
2082
1.200
-0.04
1665
0.06
1040
2.400
-0.04
832
SPBRG
value
SPBRG
value
(decimal)
9.6
9.606
0.06
1040
9.596
-0.03
520
9.615
0.16
259
9.615
-0.16
207
19.2
19.193
-0.03
520
19.231
0.16
259
19.231
0.16
129
19.230
-0.16
103
57.6
57.803
0.35
172
57.471
-0.22
86
58.140
0.94
42
57.142
0.79
34
115.2
114.943
-0.22
86
116.279
0.94
42
113.636
-1.36
21
117.647
-2.12
16
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
BAUD
RATE
(K)
0.3
1.2
FOSC = 4.000 MHz
Actual
Rate
(K)
%
Error
0.300
1.200
0.01
0.04
FOSC = 2.000 MHz
(decimal)
Actual
Rate
(K)
%
Error
3332
832
0.300
1.201
-0.04
-0.16
SPBRG
value
FOSC = 1.000 MHz
(decimal)
Actual
Rate
(K)
%
Error
1665
415
0.300
1.201
-0.04
-0.16
832
207
103
SPBRG
value
SPBRG
value
(decimal)
2.4
2.404
0.16
415
2.403
-0.16
207
2.403
-0.16
9.6
9.615
0.16
103
9.615
-0.16
51
9.615
-0.16
25
19.2
19.231
0.16
51
19.230
-0.16
25
19.230
-0.16
12
57.6
58.824
2.12
16
55.555
3.55
8
—
—
—
115.2
111.111
-3.55
8
—
—
—
—
—
—
DS39932C-page 328
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
19.1.3
AUTO-BAUD RATE DETECT
The Enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
Note 1: If the WUE bit is set with the ABDEN bit,
Auto-Baud Rate Detection will occur on
the byte following the Break character.
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible
due to bit error rates. Overall system timing and communication baud rates must
be taken into consideration when using the
Auto-Baud Rate Detection feature.
The automatic baud rate measurement sequence
(Figure 19-1) begins whenever a Start bit is received
and the ABDEN bit is set. The calculation is
self-averaging.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RXx signal, the RXx signal is timing the BRG.
In ABD mode, the internal BRG is used as a counter to
time the bit period of the incoming serial byte stream.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The ABD must receive
a byte with the value, 55h (ASCII “U”, which is also the
LIN bus Sync character), in order to calculate the proper
bit rate. The measurement is taken over both a low and
high bit time in order to minimize any effects caused by
asymmetry of the incoming signal. After a Start bit, the
SPBRGx begins counting up, using the preselected
clock source on the first rising edge of RXx. After eight
bits on the RXx pin or the fifth rising edge, an accumulated value totalling the proper BRG period is left in the
SPBRGHx:SPBRGx register pair. Once the 5th edge is
seen (this should correspond to the Stop bit), the
ABDEN bit is automatically cleared.
If a rollover of the BRG occurs (an overflow from FFFFh
to 0000h), the event is trapped by the ABDOVF status
bit (BAUDCONx<7>). It is set in hardware by BRG rollovers and can be set or cleared by the user in software.
ABD mode remains active after rollover events and the
ABDEN bit remains set (Figure 19-2).
TABLE 19-4:
BRG COUNTER
CLOCK RATES
BRG16
BRGH
BRG Counter Clock
0
0
FOSC/512
0
1
FOSC/128
1
0
FOSC/128
1
FOSC/32
1
Note:
19.1.3.1
During the ABD sequence, SPBRGx and
SPBRGHx are both used as a 16-bit
counter, independent of BRG16 setting.
ABD and EUSART Transmission
Since the BRG clock is reversed during ABD acquisition, the EUSART transmitter cannot be used during
ABD. This means that whenever the ABDEN bit is set,
TXREGx cannot be written to. Users should also
ensure that ABDEN does not become set during a
transmit sequence. Failing to do this may result in
unpredictable EUSART operation.
While calibrating the baud rate period, the BRG
registers are clocked at 1/8th the preconfigured clock
rate. Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRGx and SPBRGHx will be used
as a 16-bit counter. This allows the user to verify that
no carry occurred for 8-bit modes by checking for 00h
in the SPBRGHx register.
Refer to Table 19-4 for counter clock rates to the BRG.
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCxIF interrupt is set
once the fifth rising edge on RXx is detected. The value
in the RCREGx needs to be read to clear the RCxIF
interrupt. The contents of RCREGx should be
discarded.
© 2009 Microchip Technology Inc.
DS39932C-page 329
PIC18F46J11 FAMILY
FIGURE 19-1:
BRG Value
AUTOMATIC BAUD RATE CALCULATION
XXXXh
RXx pin
0000h
001Ch
Start
Edge #1
Bit 1
Bit 0
Edge #2
Bit 3
Bit 2
Edge #3
Bit 5
Bit 4
Edge #4
Bit 7
Bit 6
Edge #5
Stop Bit
BRG Clock
Auto-Cleared
Set by User
ABDEN bit
RCxIF bit
(Interrupt)
Read
RCREGx
SPBRGx
XXXXh
1Ch
SPBRGHx
XXXXh
00h
Note:
The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
FIGURE 19-2:
BRG OVERFLOW SEQUENCE
BRG Clock
ABDEN bit
RXx pin
Start
Bit 0
ABDOVF bit
FFFFh
BRG Value
DS39932C-page 330
XXXXh
0000h
0000h
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
19.2
EUSART Asynchronous Mode
Once the TXREGx register transfers the data to the TSR
register (occurs in one TCY), the TXREGx register is
empty and the TXxIF flag bit is set. This interrupt can be
enabled or disabled by setting or clearing the interrupt
enable bit, TXxIE. TXxIF will be set regardless of the
state of TXxIE; it cannot be cleared in software. TXxIF is
also not cleared immediately upon loading TXREGx, but
becomes valid in the second instruction cycle following
the load instruction. Polling TXxIF immediately following
a load of TXREGx will return invalid results.
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTAx<4>). In this mode, the
EUSART uses standard Non-Return-to-Zero (NRZ)
format (one Start bit, eight or nine data bits and one Stop
bit). The most common data format is 8 bits. An on-chip
dedicated 8-bit/16-bit BRG can be used to derive
standard baud rate frequencies from the oscillator.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent but use the same data format and baud
rate. The BRG produces a clock, either x16 or x64 of the
bit shift rate, depending on the BRGH and BRG16 bits
(TXSTAx<2> and BAUDCONx<3>). Parity is not
supported by the hardware but can be implemented in
software and stored as the ninth data bit.
While TXxIF indicates the status of the TXREGx
register; another bit, TRMT (TXSTAx<1>), shows the
status of the TSR register. TRMT is a read-only bit,
which is set when the TSR register is empty. No interrupt logic is tied to this bit so the user has to poll this bit
in order to determine if the TSR register is empty.
When operating in Asynchronous mode, the EUSART
module consists of the following important elements:
•
•
•
•
•
•
•
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
Auto-Wake-up on Sync Break Character
12-Bit Break Character Transmit
Auto-Baud Rate Detection
19.2.1
2: Flag bit, TXxIF, is set when enable bit,
TXEN, is set.
To set up an Asynchronous Transmission:
1.
2.
EUSART ASYNCHRONOUS
TRANSMITTER
3.
4.
Figure 19-3 displays the EUSART transmitter block
diagram.
5.
The heart of the transmitter is the Transmit (Serial) Shift
Register (TSR). The Shift register obtains its data from
the Read/Write Transmit Buffer register, TXREGx. The
TXREGx register is loaded with data in software. The
TSR register is not loaded until the Stop bit has been
transmitted from the previous load. As soon as the Stop
bit is transmitted, the TSR is loaded with new data from
the TXREGx register (if available).
FIGURE 19-3:
6.
7.
8.
Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
If interrupts are desired, set enable bit, TXxIE.
If 9-bit transmission is desired, set transmit bit,
TX9. Can be used as address/data bit.
Enable the transmission by setting bit, TXEN,
which will also set bit, TXxIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
Load data to the TXREGx register (starts
transmission).
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXxIF
TXREGx Register
TXxIE
8
MSb
(8)
LSb
• • •
Pin Buffer
and Control
0
TSR Register
TXx pin
Interrupt
TXEN
Baud Rate CLK
TRMT
BRG16
SPBRGHx SPBRGx
Baud Rate Generator
© 2009 Microchip Technology Inc.
SPEN
TX9
TX9D
DS39932C-page 331
PIC18F46J11 FAMILY
FIGURE 19-4:
ASYNCHRONOUS TRANSMISSION
Write to TXREGx
Word 1
BRG Output
(Shift Clock)
TXx (pin)
Start bit
bit 0
bit 1
bit 7/8
Stop bit
Word 1
TXxIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 19-5:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREGx
Word 2
Word 1
BRG Output
(Shift Clock)
TXx (pin)
Start bit
bit 1
1 TCY
TXxIF bit
(Interrupt Reg. Flag)
bit 7/8
Stop bit
Start bit
bit 0
Word 2
Word 1
1 TCY
Word 1
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note:
bit 0
Word 2
Transmit Shift Reg.
This timing diagram shows two consecutive transmissions.
TABLE 19-5:
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
63
INTCON
GIE/GIEH PEIE/GIEL
PIR1
PMPIF(1)
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
65
PIE1
PMPIE(1)
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
65
IPR1
PMPIP(1)
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
65
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CTMUIF
TMR3GIF
RTCCIF
65
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CTMUIE TMR3GIE
RTCCIE
65
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CTMUIP TMR3GIP
RTCCIP
65
SPEN
RX9
SREN
CREN
ADDEN
RX9D
65
RCSTAx
TXREGx
TXSTAx
FERR
OERR
EUSARTx Transmit Register
65
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
65
BAUDCONx
ABDOVF
RCIDL
RXDTP
TXDTP
BRG16
—
WUE
ABDEN
66
SPBRGHx
EUSARTx Baud Rate Generator Register High Byte
66
SPBRGx
EUSARTx Baud Rate Generator Register Low Byte
65
ODCON2
—
—
—
—
U2OD
U1OD
68
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: These bits are only available on 44-pin devices.
DS39932C-page 332
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
19.2.2
EUSART ASYNCHRONOUS
RECEIVER
19.2.3
The receiver block diagram is displayed in Figure 19-6.
The data is received on the RXx pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at FOSC. This mode would typically be used
in RS-232 systems.
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCxIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
7. The RCxIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCxIE and GIE bits are set.
8. Read the RCSTAx register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
9. Read RCREGx to determine if the device is
being addressed.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
To set up an Asynchronous Reception:
1.
Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
3. If interrupts are desired, set enable bit, RCxIE.
4. If 9-bit reception is desired, set bit, RX9.
5. Enable the reception by setting bit, CREN.
6. Flag bit, RCxIF, will be set when reception is
complete and an interrupt will be generated if
enable bit, RCxIE, was set.
7. Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREGx register.
9. If any error occurred, clear the error by clearing
enable bit, CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 19-6:
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
EUSARTx RECEIVE BLOCK DIAGRAM
CREN
OERR
FERR
x64 Baud Rate CLK
BRG16
SPBRGHx
SPBRGx
Baud Rate Generator
÷ 64
or
÷ 16
or
÷4
RSR Register
MSb
Stop
(8)
7
• • •
1
LSb
0
Start
RX9
Pin Buffer
and Control
Data
Recovery
RXx
RX9D
RCREGx Register
FIFO
SPEN
8
Interrupt
RCxIF
Data Bus
RCxIE
© 2009 Microchip Technology Inc.
DS39932C-page 333
PIC18F46J11 FAMILY
FIGURE 19-7:
ASYNCHRONOUS RECEPTION
Start
bit
RXx (pin)
bit 0
bit 7/8 Stop
bit
bit 1
Rcv Shift Reg
Rcv Buffer Reg
Start
bit
bit 0
Stop
bit
Start
bit
bit 7/8
Stop
bit
Word 2
RCREGx
Word 1
RCREGx
Read Rcv
Buffer Reg
RCREGx
bit 7/8
RCxIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after
the third word causing the OERR (Overrun) bit to be set.
TABLE 19-6:
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
63
INTCON
GIE/GIEH PEIE/GIEL
PIR1
PMPIF(1)
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
65
PIE1
PMPIE(1)
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
65
IPR1
PMPIP(1)
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
65
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CTMUIF TMR3GIF
RTCCIF
65
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CTMUIE TMR3GIE
RTCCIE
65
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CTMUIP TMR3GIP
RTCCIP
65
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
65
RCSTAx
RCREGx
TXSTAx
EUSARTx Receive Register
CSRC
BAUDCONx ABDOVF
65
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
65
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN
66
SPBRGHx
EUSARTx Baud Rate Generator Register High Byte
66
SPBRGx
EUSARTx Baud Rate Generator Register Low Byte
65
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: These bits are only available on 44-pin devices.
19.2.4
AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the BRG is inactive and a
proper byte reception cannot be performed. The
auto-wake-up feature allows the controller to wake-up
due to activity on the RXx/DTx line while the EUSART
is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCONx<1>). Once set, the typical
receive sequence on RXx/DTx is disabled and the
DS39932C-page 334
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on
the RXx/DTx line. (This coincides with the start of a
Sync Break or a Wake-up Signal character for the LIN
protocol.)
Following a wake-up event, the module generates an
RCxIF interrupt. The interrupt is generated synchronously to the Q clocks in normal operating modes
(Figure 19-8) and asynchronously if the device is in
Sleep mode (Figure 19-9). The interrupt condition is
cleared by reading the RCREGx register.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
19.2.4.2
The WUE bit is automatically cleared once a
low-to-high transition is observed on the RXx line
following the wake-up event. At this point, the EUSART
module is in Idle mode and returns to normal operation.
This signals to the user that the Sync Break event is
over.
19.2.4.1
The timing of WUE and RCxIF events may cause some
confusion when it comes to determining the validity of
received data. As noted, setting the WUE bit places the
EUSART in an Idle mode. The wake-up event causes a
receive interrupt by setting the RCxIF bit. The WUE bit
is cleared after this when a rising edge is seen on
RXx/DTx. The interrupt condition is then cleared by
reading the RCREGx register. Ordinarily, the data in
RCREGx will be dummy data and should be discarded.
Special Considerations Using
Auto-Wake-up
Since auto-wake-up functions by sensing rising edge
transitions on RXx/DTx, information with any state
changes before the Stop bit may signal a false
End-Of-Character (EOC) and cause data or framing
errors. To work properly, therefore, the initial character
in the transmission must be all ‘0’s. This can be 00h
(8 bytes) for standard RS-232 devices or 000h
(12 bits) for LIN bus.
The fact that the WUE bit has been cleared (or is still
set) and the RCxIF flag is set should not be used as an
indicator of the integrity of the data in RCREGx. Users
should consider implementing a parallel method in
firmware to verify received data integrity.
To assure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process. If
a receive operation is not occurring, the WUE bit may
then be set just prior to entering the Sleep mode.
Oscillator start-up time must also be considered,
especially in applications using oscillators with
longer start-up intervals (i.e., HS or HSPLL mode).
The Sync Break (or Wake-up Signal) character must
be of sufficient length and be followed by a sufficient
interval to allow enough time for the selected
oscillator to start and provide proper initialization of
the EUSART.
FIGURE 19-8:
Special Considerations Using the
WUE Bit
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user
WUE bit(1)
Auto-Cleared
RXx/DTx Line
RCxIF
Cleared due to user read of RCREGx
Note 1: The EUSART remains in Idle while the WUE bit is set.
FIGURE 19-9:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit(2)
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Bit set by user
Auto-Cleared
RXx/DTx Line
Note 1
RCxIF
SLEEP Command Executed
Note 1:
2:
Sleep Ends
Cleared due to user read of RCREGx
If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the
oscillator is ready. This sequence should not depend on the presence of Q clocks.
The EUSART remains in Idle while the WUE bit is set.
© 2009 Microchip Technology Inc.
DS39932C-page 335
PIC18F46J11 FAMILY
19.2.5
BREAK CHARACTER SEQUENCE
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. The Break character transmit
consists of a Start bit, followed by twelve ‘0’ bits and a
Stop bit. The Frame Break character is sent whenever
the SENDB and TXEN bits (TXSTAx<3> and
TXSTAx<5>) are set while the Transmit Shift Register
is loaded with data.
Note that the value of data written to TXREGx will be
ignored and all ‘0’s will be transmitted.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
Note that the data value written to the TXREGx for the
Break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal transmission. See Figure 19-10 for the timing of the Break
character sequence.
19.2.5.1
Break and Sync Transmit Sequence
The following sequence will send a message frame
header made up of a Break, followed by an Auto-Baud
Sync byte. This sequence is typical of a LIN bus master.
1.
2.
3.
4.
5.
Configure the EUSART for the desired mode.
Set the TXEN and SENDB bits to set up the
Break character.
Load the TXREGx with a dummy character to
initiate transmission (the value is ignored).
Write ‘55h’ to TXREGx to load the Sync
character into the transmit FIFO buffer.
After the Break has been sent, the SENDB bit is
reset by hardware. The Sync character now
transmits in the preconfigured mode.
When the TXREGx becomes empty, as indicated by the
TXxIF, the next data byte can be written to TXREGx.
19.2.6
RECEIVING A BREAK CHARACTER
The Enhanced USART module can receive a Break
character in two ways.
The first method forces configuration of the baud rate
at a frequency of 9/13 the typical speed. This allows for
the Stop bit transition to be at the correct sampling
location (13 bits for Break versus Start bit and 8 data
bits for typical data).
The second method uses the auto-wake-up feature
described in Section 19.2.4 “Auto-Wake-up on Sync
Break Character”. By enabling this feature, the
EUSART will sample the next two transitions on
RXx/DTx, cause an RCxIF interrupt and receive the
next data byte followed by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detect
feature. For both methods, the user can set the ABDEN
bit once the TXxIF interrupt is observed.
FIGURE 19-10:
Write to TXREGx
SEND BREAK CHARACTER SEQUENCE
Dummy Write
BRG Output
(Shift Clock)
TXx (pin)
Start Bit
Bit 0
Bit 1
Bit 11
Stop Bit
Break
TXxIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB sampled here
Auto-Cleared
SENDB bit
(Transmit Shift
Reg. Empty Flag)
DS39932C-page 336
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
19.3
EUSART Synchronous Master
Mode
Once the TXREGx register transfers the data to the
TSR register (occurs in one TCY), the TXREGx is empty
and the TXxIF flag bit is set. The interrupt can be
enabled or disabled by setting or clearing the interrupt
enable bit, TXxIE. TXxIF is set regardless of the state
of enable bit, TXxIE; it cannot be cleared in software. It
will reset only when new data is loaded into the
TXREGx register.
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTAx<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit,
SYNC (TXSTAx<4>). In addition, enable bit, SPEN
(RCSTAx<7>), is set in order to configure the TXx and
RXx pins to CKx (clock) and DTx (data) lines,
respectively.
While flag bit, TXxIF, indicates the status of the TXREGx
register, another bit, TRMT (TXSTAx<1>), shows the
status of the TSR register. TRMT is a read-only bit which
is set when the TSR is empty. No interrupt logic is tied to
this bit, so the user must poll this bit in order to determine
if the TSR register is empty. The TSR is not mapped in
data memory so it is not available to the user.
The Master mode indicates that the processor transmits the master clock on the CKx line. Clock polarity is
selected with the TXCKP bit (BAUDCONx<4>). Setting
TXCKP sets the Idle state on CKx as high, while clearing the bit sets the Idle state as low. This option is
provided to support Microwire devices with this module.
19.3.1
To set up a Synchronous Master Transmission:
1.
EUSART SYNCHRONOUS MASTER
TRANSMISSION
2.
The EUSART transmitter block diagram is shown in
Figure 19-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREGx. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREGx (if available).
FIGURE 19-11:
3.
4.
5.
6.
7.
8.
Initialize the SPBRGHx:SPBRGx registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the required baud
rate.
Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
If interrupts are desired, set enable bit, TXxIE.
If 9-bit transmission is required, set bit, TX9.
Enable the transmission by setting bit, TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
Start transmission by loading data to the
TXREGx register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1/
SDO1/RP18
bit 0
RC6/TX1/CK1/RP17 pin
(TXCKP = 0)
bit 1
Word 1
bit 2
Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 7
bit 0
bit 1
bit 7
Word 2
RC6/TX1/CK1 pin
(TXCKP = 1)
Write to
TXREG1 Reg
Write Word 1
Write Word 2
TX1IF bit
(Interrupt Flag)
TRMT bit
TXEN bit
‘1’
‘1’
Note: Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words. This example is equally applicable to
EUSART2 (RPn1/TX2/CK2 and RPn2/RX2/DT2).
© 2009 Microchip Technology Inc.
DS39932C-page 337
PIC18F46J11 FAMILY
FIGURE 19-12:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
bit 0
RC7/RX1/DT1/
SDO1/RP18 pin
bit 2
bit 1
bit 6
bit 7
RC6/TX1/CK1/RP17 pin
Write to
TXREG1 reg
TX1IF bit
TRMT bit
TXEN bit
Note: This example is equally applicable to EUSART2 (RPn1/TX2/CK2 and RPn2/RX2/DT2).
TABLE 19-7:
Name
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
63
PIR1
PMPIF(1)
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
65
PIE1
PMPIE(1)
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
65
IPR1
PMPIP(1)
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
65
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CTMUIF TMR3GIF
RTCCIF
65
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CTMUIE TMR3GIE RTCCIE
65
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CTMUIP TMR3GIP RTCCIP
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
RCSTAx
TXREGx
TXSTAx
EUSARTx Transmit Register
CSRC
BAUDCONx ABDOVF
65
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN
SPBRGHx
EUSARTx Baud Rate Generator Register High Byte
SPBRGx
EUSARTx Baud Rate Generator Register Low Byte
ODCON2
—
—
—
65
65
—
65
66
66
65
U2OD
U1OD
68
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: These pins are only available on 44-pin devices.
DS39932C-page 338
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
19.3.2
EUSART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTAx<5>) or the Continuous Receive
Enable bit, CREN (RCSTAx<4>). Data is sampled on
the RXx pin on the falling edge of the clock.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1.
2.
Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRG16 bit, as required, to achieve the desired
baud rate.
Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
FIGURE 19-13:
3.
4.
5.
6.
Ensure bits, CREN and SREN, are clear.
If interrupts are desired, set enable bit, RCxIE.
If 9-bit reception is desired, set bit, RX9.
If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
7. Interrupt flag bit, RCxIF, will be set when
reception is complete and an interrupt will be
generated if the enable bit, RCxIE, was set.
8. Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREGx register.
10. If any error occurred, clear the error by clearing
bit, CREN.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1/
SDO1/RP18 pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RC6/TX1/CK1/RP17
pin (TXCKP = 0)
RC6/TX1/CK1/RP17
pin (TXCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ‘0’
‘0’
RC1IF bit
(Interrupt)
Read
RCREG1
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. This example is equally applicable
to EUSART2 (RPn1/TX2/CK2 and RPn2/RX2/DT2).
© 2009 Microchip Technology Inc.
DS39932C-page 339
PIC18F46J11 FAMILY
TABLE 19-8:
Name
INTCON
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7
Bit 6
Bit 5
GIE/GIEH PEIE/GIEL TMR0IE
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
63
PIR1
PMPIF
(1)
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
65
PIE1
PMPIE(1)
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
65
IPR1
PMPIP(1)
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
65
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CTMUIF TMR3GIF RTCCIF
65
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CTMUIE TMR3GIE RTCCIE
65
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CTMUIP TMR3GIP RTCCIP
65
SPEN
RX9
SREN
CREN
ADDEN
RCSTAx
RCREGx
TXSTAx
FERR
OERR
RX9D
EUSARTx Receive Register
CSRC
BAUDCONx ABDOVF
65
65
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
65
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN
66
SPBRGHx
EUSARTx Baud Rate Generator Register High Byte
66
SPBRGx
EUSARTx Baud Rate Generator Register Low Byte
65
ODCON2
—
—
—
—
U2OD
U1OD
68
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: These pins are only available on 44-pin devices.
DS39932C-page 340
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
19.4
EUSART Synchronous Slave
Mode
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTAx<7>). This mode differs from the
Synchronous Master mode in that the shift clock is supplied externally at the CKx pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any low-power mode.
19.4.1
EUSART SYNCHRONOUS SLAVE
TRANSMISSION
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode.
7.
If two words are written to the TXREGx and then the
SLEEP instruction is executed, the following will occur:
8.
a)
b)
c)
d)
e)
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in the TXREGx
register.
Flag bit, TXxIF, will not be set.
When the first word has been shifted out of TSR,
the TXREGx register will transfer the second
word to the TSR and flag bit, TXxIF, will now be
set.
If enable bit, TXxIE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
© 2009 Microchip Technology Inc.
Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
Clear bits, CREN and SREN.
If interrupts are desired, set enable bit, TXxIE.
If 9-bit transmission is desired, set bit, TX9.
Enable the transmission by setting enable bit,
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
Start transmission by loading data to the
TXREGx register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
DS39932C-page 341
PIC18F46J11 FAMILY
TABLE 19-9:
Name
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
63
PIR1
PMPIF(1)
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
65
PIE1
PMPIE(1)
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
65
IPR1
(1)
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
65
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CTMUIF
TMR3GIF
RTCCIF
65
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CTMUIE TMR3GIE
RTCCIE
65
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CTMUIP TMR3GIP
RTCCIP
65
CREN
ADDEN
RX9D
65
RCSTAx
TXREGx
TXSTAx
PMPIP
SPEN
RX9
SREN
FERR
OERR
EUSARTx Transmit Register
CSRC
BAUDCONx ABDOVF
65
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
65
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN
66
SPBRGHx
EUSARTx Baud Rate Generator Register High Byte
66
SPBRGx
EUSARTx Baud Rate Generator Register Low Byte
65
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1: These pins are only available on 44-pin devices.
DS39932C-page 342
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
19.4.2
EUSART SYNCHRONOUS SLAVE
RECEPTION
To set up a Synchronous Slave Reception:
1.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep, or any
Idle mode and bit, SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREGx register. If the RCxIE enable bit is set, the
interrupt generated will wake the chip from the
low-power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
2.
3.
4.
5.
6.
7.
8.
9.
Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
If interrupts are desired, set enable bit, RCxIE.
If 9-bit reception is desired, set bit, RX9.
To enable reception, set enable bit, CREN.
Flag bit, RCxIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCxIE, was set.
Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREGx register.
If any error occurred, clear the error by clearing
bit, CREN.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 19-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
63
PIR1
PMPIF(1)
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
65
PIE1
PMPIE(1)
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
65
IPR1
PMPIP(1)
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
65
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CTMUIF
TMR3GIF
RTCCIF
65
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CTMUIE TMR3GIE
RTCCIE
65
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CTMUIP TMR3GIP
RTCCIP
65
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
65
RCSTAx
RCREGx
TXSTAx
EUSARTx Receive Register
CSRC
BAUDCONx ABDOVF
65
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
65
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN
66
SPBRGHx
EUSARTx Baud Rate Generator Register High Byte
66
SPBRGx
EUSARTx Baud Rate Generator Register Low Byte
65
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1: These pins are only available on 44-pin devices.
© 2009 Microchip Technology Inc.
DS39932C-page 343
PIC18F46J11 FAMILY
NOTES:
DS39932C-page 344
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
20.0
10-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) Converter module has
10 inputs for the 28-pin devices and 13 for the 44-pin
devices. Additionally, two internal channels are
available for sampling the VDDCORE and VBG absolute
reference voltage. This module allows conversion of an
analog input signal to a corresponding 10-bit digital
number.
The module has six registers:
• A/D Control Register 0 (ADCON0)
REGISTER 20-1:
•
•
•
•
A/D Control Register 1 (ADCON1)
A/D Port Configuration Register 2 (ANCON0)
A/D Port Configuration Register 1 (ANCON1)
A/D Result Registers (ADRESH and ADRESL)
The ADCON0 register, in Register 20-1, controls the
operation of the A/D module. The ADCON1 register, in
Register 20-2, configures the A/D clock source,
programmed acquisition time and justification.
The ANCON0 and ANCON1 registers, in Register 20-3
and Register 20-4, configure the functions of the port
pins.
ADCON0: A/D CONTROL REGISTER 0 (ACCESS FC2h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VCFG1
VCFG0
CHS3(2)
CHS2(2)
CHS1(2)
CHS0(2)
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
VCFG1: Voltage Reference Configuration bit (VREF- source)
1 = VREF- (AN2)
0 = AVSS
bit 6
VCFG0: Voltage Reference Configuration bit (VREF+ source)
1 = VREF+ (AN3)
0 = AVDD
bit 5-2
CHS<3:0>: Analog Channel Select bits(2)
0000 = Channel 00 (AN0)
0001 = Channel 01 (AN1)
0010 = Channel 02 (AN2)
0011 = Channel 03 (AN3)
0100 = Channel 04 (AN4)
0101 = Channel 05 (AN5)(1)
0110 = Channel 06 (AN6)(1)
0111 = Channel 07 (AN7)(1)
1000 = Channel 08 (AN8)
1001 = Channel 09 (AN9)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
1100 = Channel 12 (AN12)
1101 = (Reserved)
1110 = VDDCORE
1111 = VBG Absolute Reference (~1.2V)(3)
bit 1
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress
0 = A/D Idle
bit 0
ADON: A/D On bit
1 = A/D Converter module is enabled
0 = A/D Converter module is disabled
Note 1:
2:
3:
x = Bit is unknown
These channels are not implemented on 28-pin devices.
Performing a conversion on unimplemented channels will return random values.
For best accuracy, the band gap reference circuit should be enabled (ANCON1<7> = 1) at least 10 ms
before performing a conversion on this channel.
© 2009 Microchip Technology Inc.
DS39932C-page 345
PIC18F46J11 FAMILY
REGISTER 20-2:
ADCON1: A/D CONTROL REGISTER 1 (ACCESS FC1h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
ADCAL
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
bit 6
ADCAL: A/D Calibration bit
1 = Calibration is performed on next A/D conversion
0 = Normal A/D Converter operation
bit 5-3
ACQT<2:0>: A/D Acquisition Time Select bits
111 = 20 TAD
110 = 16 TAD
101 = 12 TAD
100 = 8 TAD
011 = 6 TAD
010 = 4 TAD
001 = 2 TAD
000 = 0 TAD
bit 2-0
ADCS<2:0>: A/D Conversion Clock Select bits
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock derived from A/D RC oscillator)(1)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
Note 1:
x = Bit is unknown
If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
DS39932C-page 346
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
The ANCON0 and ANCON1 registers are used to
configure the operation of the I/O pin associated with
each analog channel. Setting any one of the PCFG bits
configures the corresponding pin to operate as a digital
only I/O. Clearing a bit configures the pin to operate as
an analog input for either the A/D Converter or the
comparator module; all digital peripherals are disabled
and digital inputs read as ‘0’. As a rule, I/O pins that are
multiplexed with analog inputs default to analog
operation on device Resets.
request that the band gap reference circuit should be
enabled. For best accuracy, firmware should allow a
settling time of at least 10 ms prior to performing the first
acquisition on this channel after enabling the band gap
reference.
The reference circuit may already have been turned on
if some other hardware module (such as the on-chip
voltage regulator, comparators or HLVD) has already
requested it. In this case, the initial turn-on settling time
may have already elapsed and firmware does not need
to wait as long before measuring VBG. Once the acquisition is complete, firmware may clear the VBGEN bit,
which will save a small amount of power if no other
modules are still requesting the VBG reference.
In order to correctly perform A/D conversions on the VBG
band gap reference (ADCON0<5:2> = 1111), the reference circuit must be powered on first. The VBGEN bit in
the ANCON1 register allows the firmware to manually
REGISTER 20-3:
ANCON0: A/D PORT CONFIGURATION REGISTER 2 (BANKED F48h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG7(1)
PCFG6(1)
PCFG5(1)
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
x = Bit is unknown
PCFG<7:0>: Analog Port Configuration bits (AN<7:0>)
1 = Pin configured as a digital port
0 = Pin configured as an analog channel – digital input disabled and reads ‘0’
These bits are not implemented on 28-pin devices.
REGISTER 20-4:
ANCON1: A/D PORT CONFIGURATION REGISTER 1 (BANKED F49h)
R/W-0
r
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VBGEN
—
—
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
bit 7
bit 0
Legend:
r = Reserved
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
VBGEN: 1.2V Band Gap Reference Enable bit
1 = 1.2V band gap reference is powered on
0 = 1.2V band gap reference is turned off to save power (if no other modules are requesting it)
bit 6
Reserved: Always maintain as ‘0’ for lowest power consumption
bit 5
Unimplemented: Read as ‘0’
bit 4-0
PCFG<12:8>: Analog Port Configuration bits (AN<12:8>)
1 = Pin configured as a digital port
0 = Pin configured as an analog channel – digital input disabled and reads ‘0’
© 2009 Microchip Technology Inc.
DS39932C-page 347
PIC18F46J11 FAMILY
Each port pin associated with the A/D Converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0<1>) is
cleared and the A/D Interrupt Flag bit, ADIF, is set.
The analog reference voltage is software selectable to either the device’s positive and negative
supply voltage (AV DD and AV SS ), or the voltage
and
level
on
the
RA3/AN3/VREF +/C1INB
RA2/AN2/VREF -/CVREF /C2INB pins.
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted. The value in the
ADRESH:ADRESL register pair is not modified for a
Power-on Reset (POR). These registers will contain
unknown data after a POR.
The output of the sample and hold is the input into the
Converter, which generates the result via successive
approximation.
Figure 20-1 provides the block diagram of the A/D module.
FIGURE 20-1:
A/D BLOCK DIAGRAM
CHS<3:0>
1111
1110
1100
1011
1010
1001
1000
0111
0110
VAIN
0101
(Input Voltage)
10-Bit
A/D
Converter
0100
0011
0010
VCFG<1:0>
Reference
Voltage
0001
VDD(2)
0000
VBG
VDDCORE/VCAP
AN12
AN11
AN10
AN9
AN8
AN7(1)
AN6(1)
AN5(1)
AN4
AN3
AN2
AN1
AN0
VREF+
VREFVSS(2)
Note 1: Channels AN5, AN6 and AN7 are not available on 28-pin devices.
2: I/O pins have diode protection to VDD and VSS.
DS39932C-page 348
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 20.1
“A/D Acquisition Requirements”. After this acquisition time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
2.
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time (if required).
Start conversion:
• Set GO/DONE bit (ADCON0<1>)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
3.
4.
5.
The following steps should be followed to do an A/D
conversion:
1.
Configure the A/D module:
• Configure the required ADC pins as analog
pins using ANCON0, ANCON1
• Set voltage reference using ADCON0
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON1)
• Select A/D conversion clock (ADCON1)
• Turn on A/D module (ADCON0)
FIGURE 20-2:
OR
• Waiting for the A/D interrupt
Read A/D Result registers (ADRESH:ADRESL);
clear bit, ADIF, if required.
For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before next acquisition starts.
6.
7.
ANALOG INPUT MODEL
VDD
RS
VAIN
ANx
CPIN
5 pF
Sampling
Switch
VT = 0.6V
RIC ≤ 1k
VT = 0.6V
SS
RSS
ILEAKAGE
±100 nA
CHOLD = 25 pF
VSS
Legend: CPIN
= Input Capacitance
VT
= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to
various junctions
= Interconnect Resistance
RIC
= Sampling Switch
SS
= Sample/Hold Capacitance (from DAC)
CHOLD
RSS
= Sampling Switch Resistance
© 2009 Microchip Technology Inc.
VDD
1
2
3
4
Sampling Switch (kΩ)
DS39932C-page 349
PIC18F46J11 FAMILY
20.1
A/D Acquisition Requirements
For the A/D Converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is illustrated in Figure 20-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 10 kΩ. After the analog input channel is
selected (changed), the channel must be sampled for
at least the minimum acquisition time before starting a
conversion.
Note:
CHOLD
Rs
Conversion Error
VDD
Temperature
=
=
≤
=
=
25 pF
2.5 kΩ
1/2 LSb
3V → Rss = 2 kΩ
85°C (system max.)
ACQUISITION TIME
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
=
TAMP + TC + TCOFF
EQUATION 20-2:
VHOLD
or
TC
Equation 20-3 provides the calculation of the minimum
required acquisition time, TACQ. This calculation is
based on the following application system
assumptions:
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
EQUATION 20-1:
TACQ
To calculate the minimum acquisition time,
Equation 20-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
A/D MINIMUM CHARGING TIME
=
(VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))
=
-(CHOLD)(RIC + RSS + RS) ln(1/2048)
EQUATION 20-3:
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
=
TAMP + TC + TCOFF
TAMP
=
0.2 ms
TCOFF
=
(Temp – 25°C)(0.02 μs/°C)
(85°C – 25°C)(0.02 μs/°C)
1.2 μs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 μs.
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/2048) μs
-(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) μs
1.05 μs
TACQ
=
0.2 μs + 1.05 μs + 1.2 μs
2.45 μs
DS39932C-page 350
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
20.2
Selecting and Configuring
Automatic Acquisition Time
The ADCON1 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
When the GO/DONE bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensuring the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE bit. This occurs when the ACQT<2:0> bits
(ADCON1<5:3>) remain in their Reset state (‘000’) and
is compatible with devices that do not offer
programmable acquisition times.
If desired, the ACQT bits can be set to select a programmable acquisition time for the A/D module. When
the GO/DONE bit is set, the A/D module continues to
sample the input for the selected acquisition time, then
automatically begins a conversion. Since the acquisition time is programmed, there may be no need to wait
for an acquisition time between selecting a channel and
setting the GO/DONE bit.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
20.3
Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 11 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable.
There are seven possible options for TAD:
•
•
•
•
•
•
•
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
Internal RC Oscillator
TABLE 20-1:
TAD vs. DEVICE OPERATING
FREQUENCIES
AD Clock Source (TAD)
Operation
ADCS<2:0>
Maximum
Device
Frequency
2 TOSC
000
2.86 MHz
TOSC
100
5.71 MHz
8 TOSC
001
11.43 MHz
16 TOSC
101
22.86 MHz
32 TOSC
010
45.71 MHz
64 TOSC
110
48.0 MHz
RC(2)
011
1.00 MHz(1)
4
Note 1:
2:
20.4
The RC source has a typical TAD time of
4 μs.
For device frequencies above 1 MHz, the
device must be in Sleep mode for the
entire conversion or the A/D accuracy may
be out of specification.
Configuring Analog Port Pins
The ANCON0, ANCON1 and TRISA registers control
the operation of the A/D port pins. The port pins needed
as analog inputs must have their corresponding TRIS
bits set (input). If the TRIS bit is cleared (output), the
digital output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS<3:0> bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Pins configured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will be accurately
converted.
2: Analog levels on any pin defined as a
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible but greater than the
minimum TAD (see parameter 130 in Table 28-28 for
more information).
Table 20-1 provides the resultant TAD times derived
from the device operating frequencies and the A/D
clock source selected.
© 2009 Microchip Technology Inc.
DS39932C-page 351
PIC18F46J11 FAMILY
20.5
A/D Conversions
20.6
Figure 20-3 displays the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
An A/D conversion can be started by the Special Event
Trigger of the ECCP2 module. This requires that the
CCP2M<3:0> bits (CCP2CON<3:0>) be programmed
as ‘1011’ and that the A/D module is enabled (ADON
bit is set). When the trigger occurs, the GO/DONE bit
will be set, starting the A/D acquisition and conversion,
and the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate TACQ time is selected before
the Special Event Trigger sets the GO/DONE bit (starts
a conversion).
Figure 20-4 displays the operation of the A/D Converter
after the GO/DONE bit has been set, the ACQT<2:0>
bits are set to ‘010’ and a 4 TAD acquisition time has
been selected before the conversion starts.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D
conversion
sample.
This
means
the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can be
started. After this wait, acquisition on the selected
channel is automatically started.
Note:
Use of the ECCP2 Trigger
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 20-3:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b4
b1
b0
b6
b7
b2
b9
b8
b3
b5
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit
Next Q4: ADRESH/ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
FIGURE 20-4:
TAD Cycles
TACQT Cycles
1
2
3
Automatic
Acquisition
Time
4
1
b9
3
4
5
b8
b7
b6
6
b5
7
b4
8
9
10
11
b3
b2
b1
b0
Conversion starts
(Holding capacitor is disconnected)
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
DS39932C-page 352
2
Next Q4: ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
20.7
A/D Converter Calibration
The A/D Converter in the PIC18F46J11 family of
devices includes a self-calibration feature, which compensates for any offset generated within the module.
The calibration process is automated and is initiated by
setting the ADCAL bit (ADCON1<6>). The next time
the GO/DONE bit is set, the module will perform a
“dummy” conversion (that is, with reading none of the
input channels) and store the resulting value internally
to compensate for the offset. Thus, subsequent offsets
will be compensated.
Example 20-1 provides an example of a calibration
routine.
The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset or if there are other major changes in
operating conditions.
20.8
Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed
mode.
EXAMPLE 20-1:
BCF
BSF
BSF
BSF
CALIBRATION
BTFSC
BRA
BCF
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON1 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been completed. If desired, the device may be placed into the
corresponding power-managed Idle mode during the
conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in the Sleep mode requires the A/D RC clock
to be selected. If bits, ACQT<2:0>, are set to ‘000’ and
a conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN and
SCS bits in the OSCCON register must have already
been cleared prior to starting the conversion.
SAMPLE A/D CALIBRATION ROUTINE
ANCON0,PCFG0
ADCON0,ADON
ADCON1,ADCAL
ADCON0,GO
ADCON0,GO
CALIBRATION
ADCON1,ADCAL
© 2009 Microchip Technology Inc.
;Make Channel 0 analog
;Enable A/D module
;Enable Calibration
;Start a dummy A/D conversion
;
;Wait for the dummy conversion to finish
;
;Calibration done, turn off calibration enable
;Proceed with the actual A/D conversion
DS39932C-page 353
PIC18F46J11 FAMILY
TABLE 20-2:
Name
SUMMARY OF A/D REGISTERS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
63
PIR1
PMPIF(1)
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
65
PIE1
(1)
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
65
PMPIE
(1)
IPR1
PMPIP
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
65
PIR2
OSCFIF
CM2IF
CM1IF
—
BCL1IF
LVDIF
TMR3IF
CCP2IF
65
PIE2
OSCFIE
CM2IE
CM1IE
—
BCL1IE
LVDIE
TMR3IE
CCP2IE
65
IPR2
OSCFIP
CM2IP
CM1IP
—
BCL1IP
LVDIP
TMR3IP
CCP2IP
65
ADRESH
A/D Result Register High Byte
64
ADRESL
A/D Result Register Low Byte
64
ADCON0
ANCON0
VCFG1
VCFG0
CHS3
PCFG7(1) PCFG6(1) PCFG5(1)
CHS3
CHS1
CHS0
GO/DONE
ADON
64
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
68
ADCON1
ADFM
ADCAL
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
64
ANCON1
VBGEN
r(2)
—
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
68
CCP2CON
P2M1
P2M0
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
65
PORTA
RA7
RA6
RA5
—
RA3
RA2
RA1
RA0
66
TRISA
TRISA7
TRISA6
TRISA5
—
TRISA3
TRISA2
TRISA1
TRISA0
66
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These bits are only available on 44-pin devices.
2: Reserved. Always maintain as ‘0’ for minimum power consumption.
DS39932C-page 354
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
21.0
COMPARATOR MODULE
The analog comparator module contains two comparators that can be independently configured in a variety of
ways. The inputs can be selected from the analog inputs
and two internal voltage references. The digital outputs
are available at the pin level and can also be read
through the control register. Multiple output and interrupt
event generation is also available. Figure 21-1 provides
a generic single comparator from the module.
21.1
Registers
The CMxCON registers (Register 21-1) select the input
and output configuration for each comparator, as well
as the settings for interrupt generation.
The CMSTAT register (Register 21-2) provides the output results of the comparators. The bits in this register
are read-only.
Key features of the module are:
•
•
•
•
•
Independent comparator control
Programmable input configuration
Output to both pin and register levels
Programmable output polarity
Independent interrupt generation for each
comparator with configurable interrupt-on-change
FIGURE 21-1:
COMPARATOR SIMPLIFIED BLOCK DIAGRAM
COUTx
(CMSTAT<1:0>)
CCH<1:0>
CxINB
0
VIRV
3
Interrupt
Logic
CMxIF
EVPOL<4:3>
CREF
COE
VIN-
CxINA
0
CVREF
1
© 2009 Microchip Technology Inc.
VIN+
Cx
Polarity
Logic
CON
CPOL
CxOUT
DS39932C-page 355
PIC18F46J11 FAMILY
REGISTER 21-1:
CMxCON: COMPARATOR CONTROL x REGISTER (ACCESS FD2h/FD1h)
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
CON
COE
CPOL
EVPOL1
EVPOL0
CREF
CCH1
CCH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
CON: Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled
bit 6
COE: Comparator Output Enable bit
1 = Comparator output is present on the CxOUT pin (assigned in PPS module)
0 = Comparator output is internal only
bit 5
CPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 4-3
EVPOL<1:0>: Interrupt Polarity Select bits
11 = Interrupt generation on any change of the output(1)
10 = Interrupt generation only on high-to-low transition of the output
01 = Interrupt generation only on low-to-high transition of the output
00 = Interrupt generation is disabled
bit 2
CREF: Comparator Reference Select bit (non-inverting input)
1 = Non-inverting input connects to internal CVREF voltage
0 = Non-inverting input connects to CxINA pin
bit 1-0
CCH<1:0>: Comparator Channel Select bits
11 = Inverting input of comparator connects to VIRV
10 = For CM1CON, inverting input of comparator connects to C2INB pin; for CM2CON, reserved
01 = Reserved
00 = Inverting input of comparator connects to CxINB pin
Note 1:
The CMxIF is automatically set any time this mode is selected and must be cleared by the application after
the initial configuration.
DS39932C-page 356
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 21-2:
CMSTAT: COMPARATOR STATUS REGISTER (ACCESS F70h)
U-0
U-0
U-0
U-0
U-0
U-0
R-1
R-1
—
—
—
—
—
—
COUT2
COUT1
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1-0
COUT<2:1>: Comparator x Status bits
If CPOL = 0 (non-inverted polarity):
1 = Comparator VIN+ > VIN0 = Comparator VIN+ < VINIf CPOL = 1 (inverted polarity):
1 = Comparator VIN+ < VIN0 = Comparator VIN+ > VIN-
© 2009 Microchip Technology Inc.
x = Bit is unknown
DS39932C-page 357
PIC18F46J11 FAMILY
21.2
Comparator Operation
21.3
Comparator Response Time
A single comparator is shown in Figure 21-2, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input, VIN-, the output of the comparator is a digital low level. When the analog input at VIN+
is greater than the analog input, VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 21-2 represent
the uncertainty due to input offsets and response time.
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. The response time
of the comparator differs from the settling time of the
voltage reference. Therefore, both of these times must
be considered when determining the total response to
a comparator input change. Otherwise, the maximum
delay of the comparators should be used (see
Section 28.0 “Electrical Characteristics”).
FIGURE 21-2:
SINGLE COMPARATOR
21.4
VIN+
+
VIN-
–
Figure 21-3 provides a simplified circuit for an analog
input. Since the analog pins are connected to a digital
output, they have reverse biased diodes to VDD and
VSS. The analog input, therefore, must be between VSS
and VDD. If the input voltage deviates from this range
by more than 0.6V in either direction, one of the diodes
is forward biased and a latch-up condition may occur.
A maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
Output
VINVIN+
Output
FIGURE 21-3:
Analog Input Connection
Considerations
COMPARATOR ANALOG INPUT MODEL
VDD
VT = 0.6V
RS < 10k
Comparator
Input
AIN
CPIN
5 pF
VA
RIC
VT = 0.6V
ILEAKAGE
±100 nA
VSS
Legend:
DS39932C-page 358
CPIN
VT
ILEAKAGE
RIC
RS
VA
=
=
=
=
=
=
Input Capacitance
Threshold Voltage
Leakage Current at the pin due to various junctions
Interconnect Resistance
Source Impedance
Analog Voltage
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
21.5
Comparator Control and
Configuration
Each comparator has up to eight possible combinations of inputs: up to four external analog inputs, and
one of two internal voltage references.
Both comparators allow a selection of the signal from
pin, CxINA, or the voltage from the comparator reference (CVREF) on the non-inverting channel. This is
compared to either CxINB, CTMU or the microcontroller’s fixed internal reference voltage (VIRV, 0.6V
nominal) on the inverting channel.
Table 21-1 provides the comparator inputs and outputs
tied to fixed I/O pins.
Figure 21-4 illustrates the available comparator
configurations and their corresponding bit settings.
TABLE 21-1:
Comparator
1
2
21.5.1
The external reference is used when CREF = 0
(CMxCON<2>) and VIN+ is connected to the CxINA
pin. When external voltage references are used, the
comparator module can be configured to have the
reference sources externally. The reference signal
must be between VSS and VDD, and can be applied to
either pin of the comparator.
The comparator module also allows the selection of an
internally generated voltage reference (CVREF) from
the comparator voltage reference module. This module
is described in more detail in Section 21.0 “Comparator Module”. The reference from the comparator
voltage reference module is only available when
CREF = 1. In this mode, the internal voltage reference
is applied to the comparator’s VIN+ pin.
Note:
COMPARATOR INPUTS AND
OUTPUTS
Input or Output
I/O Pin
C1INA (VIN+)
RA0
C1INB (VIN-)
RA3
C1OUT
Remapped
RPn
C2INA(VIN+)
RA1
C2INB(VIN-)
RA2
C2OUT
Remapped
RPn
COMPARATOR ENABLE AND
INPUT SELECTION
Setting the CON bit of the CMxCON register
(CMxCON<7>) enables the comparator for operation.
Clearing the CON bit disables the comparator, resulting
in minimum current consumption.
The CCH<1:0> bits in the CMxCON register
(CMxCON<1:0>) direct either one of three analog input
pins, or the Internal Reference Voltage (VIRV), to the
comparator VIN-. Depending on the comparator operating mode, either an external or internal voltage
reference may be used. The analog signal present at
VIN- is compared to the signal at VIN+ and the digital
output of the comparator is adjusted accordingly.
© 2009 Microchip Technology Inc.
21.5.2
The comparator input pin selected by
CCH<1:0> must be configured as an input
by setting both the corresponding TRIS and
PCFG bits in the ANCON1 register.
COMPARATOR ENABLE AND
OUTPUT SELECTION
The comparator outputs are read through the CMSTAT
register. The CMSTAT<0> reads the Comparator 1 output and CMSTAT<1> reads the Comparator 2 output.
These bits are read-only.
The comparator outputs may also be directly output to
the RPn I/O pins by setting the COE bit (CMxCON<6>).
When enabled, multiplexers in the output path of the
pins switch to the output of the comparator.
By default, the comparator’s output is at logic high
whenever the voltage on VIN+ is greater than on VIN-.
The polarity of the comparator outputs can be inverted
using the CPOL bit (CMxCON<5>).
The uncertainty of each of the comparators is related to
the input offset voltage and the response time given in
the specifications, as discussed in Section 21.2
“Comparator Operation”.
DS39932C-page 359
PIC18F46J11 FAMILY
FIGURE 21-4:
COMPARATOR CONFIGURATIONS
Comparator Off
CON = 0, CREF = x, CCH<1:0> = xx
COE
VIN-
Cx
VIN+
Off (Read as ‘0’)
Comparator CxINB > CxINA Compare
CON = 1, CREF = 0, CCH<1:0> = 00
CxOUT
pin
Comparator CxINC > CxINA Compare
CON = 1, CREF = 0, CCH<1:0> = 01
COE
CxINB
CxINA
COE
VINVIN+
Cx
CxOUT
pin
Comparator CxIND > CxINA Compare
CON = 1, CREF = 0, CCH<1:0> = 10
CxINC
VIN-
CxINA
VIN+
Cx
CxOUT
pin
Comparator VIRV > CxINA Compare
CON = 1, CREF = 0, CCH<1:0> = 11
COE
CxIND
VIN-
CxINA
VIN+
Cx
COE
CxOUT
pin
Comparator CxINB > CVREF Compare
CON = 1, CREF = 1, CCH<1:0> = 00
VIRV
VIN-
CxINA
VIN+
Cx
CxOUT
pin
Comparator CxINC > CVREF Compare
CON = 1, CREF = 1, CCH<1:0> = 01
COE
CxINB
CVREF
COE
VINVIN+
Cx
CxOUT
pin
CxINC
VIN-
CVREF
VIN+
Cx
Comparator VIRV > CVREF Compare
CON = 1, CREF = 1, CCH<1:0> = 11
Comparator CxIND > CVREF Compare
CON = 1, CREF = 1, CCH<1:0> = 10
COE
CxIND
CVREF
Note:
COE
VINVIN+
Cx
CxOUT
pin
CxOUT
pin
VIRV
VIN-
CVREF
VIN+
Cx
CxOUT
pin
VIRV is the Internal Reference Voltage (see Table 28-2).
DS39932C-page 360
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
21.6
Comparator Interrupts
When EVPOL<1:0> = 11, the comparator interrupt flag
is set whenever there is a change in the output value of
either comparator. Software will need to maintain
information about the status of the output bits, as read
from CMSTAT<1:0>, to determine the actual change
that occurred. The CMxIF bits (PIR2<6:5>) are the
Comparator Interrupt Flags. The CMxIF bits must be
reset by clearing them. Since it is also possible to write
a ‘1’ to this register, a simulated interrupt may be
initiated.
The comparator interrupt flag is set whenever any of
the following occurs:
- Low-to-high transition of the comparator
output
- High-to-low transition of the comparator
output
- Any change in the comparator output
The comparator interrupt selection is done by the
EVPOL<1:0> bits in the CMxCON register
(CMxCON<4:3>).
Table 21-2 provides the interrupt generation
corresponding to comparator input voltages and
EVPOL bit settings.
In order to provide maximum flexibility, the output of the
comparator may be inverted using the CPOL bit in the
CMxCON register (CMxCON<5>). This is functionally
identical to reversing the inverting and non-inverting
inputs of the comparator for a particular mode.
Both the CMxIE bits (PIE2<6:5>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit (INTCON<7>) must also be set.
If any of these bits are clear, the interrupt is not
enabled, though the CMxIF bits will still be set if an
interrupt condition occurs.
An interrupt is generated on the low-to-high or high-tolow transition of the comparator output. This mode of
interrupt generation is dependent on EVPOL<1:0> in
the CMxCON register. When EVPOL<1:0> = 01 or 10,
the interrupt is generated on a low-to-high or high-tolow transition of the comparator output. Once the
interrupt is generated, it is required to clear the interrupt
flag by software.
TABLE 21-2:
CPOL
Figure 21-1 provides a simplified diagram of the
interrupt section.
COMPARATOR INTERRUPT GENERATION
EVPOL<1:0>
00
01
0
10
11
00
01
1
10
11
© 2009 Microchip Technology Inc.
Comparator
Input Change
COUTx Transition
Interrupt
Generated
VIN+ > VIN-
Low-to-High
No
VIN+ < VIN-
High-to-Low
No
VIN+ > VIN-
Low-to-High
Yes
No
VIN+ < VIN-
High-to-Low
VIN+ > VIN-
Low-to-High
No
VIN+
< VIN-
High-to-Low
Yes
VIN+ > VIN-
Low-to-High
Yes
VIN+ < VIN-
High-to-Low
Yes
VIN+ > VIN-
High-to-Low
No
VIN+ < VIN-
Low-to-High
No
VIN+ > VIN-
High-to-Low
No
VIN+ < VIN-
Low-to-High
Yes
VIN+ > VIN-
High-to-Low
Yes
VIN+ < VIN-
Low-to-High
No
VIN+ > VIN-
High-to-Low
Yes
VIN+ < VIN-
Low-to-High
Yes
DS39932C-page 361
PIC18F46J11 FAMILY
21.7
Comparator Operation During
Sleep
21.8
A device Reset forces the CMxCON registers to their
Reset state. This forces both comparators and the
voltage reference to the OFF state.
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional if enabled. This interrupt will
wake-up the device from Sleep mode when enabled.
Each operational comparator will consume additional
current. To minimize power consumption while in Sleep
mode, turn off the comparators (CON = 0) before
entering Sleep. If the device wakes up from Sleep, the
contents of the CMxCON register are not affected.
TABLE 21-3:
Name
INTCON
Effects of a Reset
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Bit 7
Bit 6
GIE/GIEH PEIE/GIEL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
63
PIR2
OSCFIF
CM2IF
CM1IF
—
BCL1IF
LVDIF
TMR3IF
CCP2IF
65
PIE2
OSCFIE
CM2IE
CM1IE
—
BCL1IE
LVDIE
TMR3IE
CCP2IE
65
IPR2
OSCFIP
CM2IP
CM1IP
—
BCL1IP
LVDIP
TMR3IP
CCP2IP
65
CMxCON
CVRCON(1)
CON
COE
CPOL
EVPOL1
EVPOL0
CREF
CCH1
CCH0
64
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
68
67
CMSTAT
—
—
—
—
—
—
COUT2
COUT1
ANCON0
PCFG7(1)
PCFG6(1)
PCFG5(1)
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
68
PORTA
RA7
RA6
RA5
—
RA3
RA2
RA1
RA0
66
TRISA
TRISA7
TRISA6
TRISA5
—
TRISA3
TRISA2
TRISA1
TRISA0
66
Legend: — = unimplemented, read as ‘0’, r = reserved. Shaded cells are not related to comparator operation.
Note 1: These bits and/or registers are not implemented on 28-pin devices.
DS39932C-page 362
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
22.0
COMPARATOR VOLTAGE
REFERENCE MODULE
The comparator voltage reference is a 16-tap resistor
ladder network that provides a selectable reference
voltage. Although its primary purpose is to provide a
reference for the analog comparators, it may also be
used independently of them.
FIGURE 22-1:
Figure 22-1 provides a block diagram of the module.
The resistor ladder is segmented to provide two ranges
of CVREF values and has a power-down function to
conserve power when the reference is not being used.
The module’s supply reference can be provided from
either device VDD/VSS or an external voltage reference.
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VREF+
VDD
CVRSS = 1
8R
CVRSS = 0
CVR<3:0>
R
CVREN
R
R
16-to-1 MUX
R
16 Steps
R
CVREF
R
R
CVRR
VREF-
8R
CVRSS = 1
CVRSS = 0
© 2009 Microchip Technology Inc.
DS39932C-page 363
PIC18F46J11 FAMILY
22.1
Configuring the Comparator
Voltage Reference
The comparator voltage reference module is controlled
through the CVRCON register (Register 22-1). The
comparator voltage reference provides two ranges of
output voltage, each with 16 distinct levels. The range
to be used is selected by the CVRR bit (CVRCON<5>).
The primary difference between the ranges is the size
of the steps selected by the CVREF Selection bits
(CVR<3:0>), with one range offering finer resolution.
The equations used to calculate the output of the
comparator voltage reference are as follows:
EQUATION 22-1:
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF- that are multiplexed with RA2 and RA3. The
voltage source is selected by the CVRSS bit
(CVRCON<4>).
The settling time of the comparator voltage reference
must be considered when changing the CVREF
output (see Table 28-4 in Section 28.0 “Electrical
Characteristics”).
CALCULATING OUTPUT
OF THE COMPARATOR
VOLTAGE REFERENCE
When CVRR = 1 and CVRSS = 0:
CVREF = ((CVR<3:0>)/24) x (CVRSRC)
When CVRR = 0 and CVRSS = 0:
CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) x (CVRSRC)
When CVRR = 1 and CVRSS = 1:
CVREF = ((CVR<3:0>)/24) x (CVRSRC) + VREFWhen CVRR = 0 and CVRSS = 1:
CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) x (CVRSRC) +VREF-)
REGISTER 22-1:
CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
(BANKED F53h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CVREN
CVROE(1)
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
CVREN: Comparator Voltage Reference Enable bit
1 = CVREF circuit powered on
0 = CVREF circuit powered down
bit 6
CVROE: Comparator VREF Output Enable bit(1)
1 = CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF/C2INB pin
0 = CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF/C2INB pin
bit 5
CVRR: Comparator VREF Range Selection bit
1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range)
0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range)
bit 4
CVRSS: Comparator VREF Source Selection bit
1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-)
0 = Comparator reference source, CVRSRC = AVDD – AVSS
bit 3-0
CVR<3:0>: Comparator VREF Value Selection bits (0 ≤ (CVR<3:0>) ≤ 15)
When CVRR = 1:
CVREF = ((CVR<3:0>)/24) • (CVRSRC)
When CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) • (CVRSRC)
Note 1:
CVROE overrides the TRIS bit setting.
DS39932C-page 364
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
22.2
Voltage Reference Accuracy/Error
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(see Figure 22-1) keep CVREF from approaching the
reference source rails. The voltage reference is derived
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 28.0 “Electrical Characteristics”.
22.3
Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RA2 pin if the
CVROE bit is set. Enabling the voltage reference output onto RA2 when it is configured as a digital input will
increase current consumption. Connecting RA2 as a
digital output with CVRSS enabled will also increase
current consumption.
FIGURE 22-2:
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage
reference output for external connections to VREF. See
Figure 22-2 for an example buffering technique.
22.4
Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
22.5
Effects of a Reset
A device Reset disables the voltage reference by
clearing bit, CVREN (CVRCON<7>). This Reset also
disconnects the reference from the RA2 pin by clearing
bit, CVROE (CVRCON<6>) and selects the high-voltage
range by clearing bit, CVRR (CVRCON<5>). The CVR
value select bits are also cleared.
COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC18F46J11
CVREF
Module
R(1)
Voltage
Reference
Output
Impedance
Note 1:
TABLE 22-1:
+
–
RA2
CVREF Output
R is dependent upon the Comparator Voltage Reference Configuration bits, CVRCON<5> and CVRCON<3:0>.
REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
CVRCON
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
68
CM1CON
CON
COE
CPOL
EVPOL1
EVPOL0
CREF
CCH1
CCH0
64
CM2CON
CON
COE
CPOL
EVPOL1
EVPOL0
CREF
CCH1
CCH0
64
TRISA7
TRISA6
TRISA5
Name
TRISA
ANCON0
ANCON1
PCFG7(1) PCFG6(1) PCFG5(1)
VBGEN
r
—
—
TRISA3
TRISA2
TRISA1
TRISA0
66
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
68
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
68
Legend: — = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used with the comparator voltage
reference.
Note 1: These bits are only available on 44-pin devices.
© 2009 Microchip Technology Inc.
DS39932C-page 365
PIC18F46J11 FAMILY
NOTES:
DS39932C-page 366
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
23.0
HIGH/LOW VOLTAGE DETECT
(HLVD)
PIC18F46J11 family devices (including PIC18LF46J11
family devices) have a High/Low Voltage Detect
(HLVD) module for monitoring the absolute voltage on
VDD or the HLVDIN pin. This is a programmable circuit
that allows the user to specify both a device voltage trip
point and the direction of change from that point.
The High/Low-Voltage Detect Control register
(Register 23-1) completely controls the operation of the
HLVD module. This allows the circuitry to be “turned
off” by the user under software control, which
minimizes the current consumption for the device.
Figure 23-1 provides a block diagram for the HLVD
module.
If the module detects an excursion past the trip point in
that direction, an interrupt flag is set. If the interrupt is
enabled, the program execution will branch to the interrupt vector address and the software can then respond
to the interrupt.
REGISTER 23-1:
R/W-0
HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER (ACCESS F85h)
R-0
VDIRMAG
BGVST
R-0
IRVST
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HLVDEN
HLVDL3(1)
HLVDL2(1)
HLVDL1(1)
HLVDL0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
VDIRMAG: Voltage Direction Magnitude Select bit
1 = Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>)
0 = Event occurs when voltage equals or falls below trip point (HLVDL<3:0>)
bit 6
BGVST: Band Gap Reference Voltages Stable Status Flag bit
1 = Indicates internal band gap voltage references is stable
0 = Indicates internal band gap voltage reference is not stable
bit 5
IRVST: Internal Reference Voltage Stable Flag bit
1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range
0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage
range and the HLVD interrupt should not be enabled
bit 4
HLVDEN: High/Low-Voltage Detect Power Enable bit
1 = HLVD enabled
0 = HLVD disabled
bit 3-0
HLVDL<3:0>: Voltage Detection Limit bits(1)
1111 = External analog input is used (input comes from the HLVDIN pin)
1110 = Maximum setting
.
.
.
0000 = Minimum setting
Note 1:
See Table 28-7 in Section 28.0 “Electrical Characteristics” for specifications.
The module is enabled by setting the HLVDEN bit.
Each time the module is enabled, the circuitry requires
some time to stabilize. The IRVST bit is a read-only bit
that indicates when the circuit is stable. The module
can generate an interrupt only after the circuit is stable
and IRVST is set.
© 2009 Microchip Technology Inc.
The VDIRMAG bit determines the overall operation of
the module. When VDIRMAG is cleared, the module
monitors for drops in VDD below a predetermined set
point. When the bit is set, the module monitors for rises
in VDD above the set point.
DS39932C-page 367
PIC18F46J11 FAMILY
23.1
Operation
The trip point voltage is software programmable to any
one of 16 values. The trip point is selected by
programming the HLVDL<3:0> bits (HLVDCON<3:0>).
When the HLVD module is enabled, a comparator uses
an internally generated reference voltage as the set
point. The set point is compared with the trip point,
where each node in the resistor divider represents a
trip point voltage. The “trip point” voltage is the voltage
level at which the device detects a high or low-voltage
event, depending on the configuration of the module.
Additionally, the HLVD module allows the user to
supply the trip voltage to the module from an external
source. This mode is enabled when bits, HLVDL<3:0>,
are set to ‘1111’. In this state, the comparator input is
multiplexed from the external input pin, HLVDIN. This
gives users flexibility because it allows them to
configure the HLVD interrupt to occur at any voltage in
the valid operating range.
When the supply voltage is equal to the trip point, the
voltage tapped off of the resistor array is equal to the
internal reference voltage generated by the voltage
reference module. The comparator then generates an
interrupt signal by setting the LVDIF bit.
FIGURE 23-1:
HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT)
Externally Generated
Trip Point
VDD
VDD
HLVDL<3:0>
HLVDCON
Register
HLVDEN
16-to-1 MUX
HLVDIN
VDIRMAG
Set
LVDIF
HLVDEN
Internal Voltage
Reference
1.2V Typical
DS39932C-page 368
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
23.2
HLVD Setup
To set up the HLVD module:
1.
2.
3.
4.
5.
6.
Disable the module by clearing the HLVDEN bit
(HLVDCON<4>).
Write the value to the HLVDL<3:0> bits that
selects the desired HLVD trip point.
Set the VDIRMAG bit to detect one of the
following:
• High voltage (VDIRMAG = 1)
• Low voltage (VDIRMAG = 0)
Enable the HLVD module by setting the
HLVDEN bit.
Clear the HLVD Interrupt Flag, LVDIF
(PIR2<2>), which may have been set from a
previous interrupt.
If interrupts are desired, enable the HLVD
interrupt by setting the HLVDIE and GIE/GIEH
bits (PIE2<2> and INTCON<7>).
23.4
HLVD Start-up Time
The internal reference voltage of the HLVD module,
specified in electrical specification parameter D420
(see Table 28-7 in Section 28.0 “Electrical Characteristics”), may be used by other internal circuitry,
such as the Programmable Brown-out Reset (BOR).
If the HLVD or other circuits using the voltage reference
are disabled to lower the device’s current consumption,
the reference voltage circuit will require time to become
stable before a low or high-voltage condition can be
reliably detected. This start-up time, TIRVST, is an
interval that is independent of device clock speed. It is
specified in electrical specification parameter 36
(Table 28-13).
The HLVD interrupt flag is not enabled until TIRVST has
expired and a stable reference voltage is reached. For
this reason, brief excursions beyond the set point may
not be detected during this interval. Refer to Figure 23-2
or Figure 23-3.
An interrupt will not be generated until the
IRVST bit is set.
23.3
Current Consumption
When the module is enabled, the HLVD comparator
and voltage divider are enabled and will consume static
current. The total current consumption, when enabled,
is specified in electrical specification parameter D022B
(ΔIHLVD) (Section 28.2 “DC Characteristics: PowerDown and Supply Current PIC18F46J50 Family
(Industrial)”).
Depending on the application, the HLVD module does
not need to operate constantly. To decrease the current
requirements, the HLVD circuitry may only need to be
enabled for short periods where the voltage is checked.
After doing the check, the HLVD module may be
disabled.
© 2009 Microchip Technology Inc.
DS39932C-page 369
PIC18F46J11 FAMILY
FIGURE 23-2:
LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0)
CASE 1:
LVDIF may not be set
VDD
VHLVD
LVDIF
Enable HLVD
TIRVST
IRVST
Internal Reference is stable
LVDIF cleared in software
CASE 2:
VDD
VHLVD
LVDIF
Enable HLVD
TIRVST
IRVST
Internal Reference is stable
LVDIF cleared in software
LVDIF cleared in software,
LVDIF remains set since HLVD condition still exists
DS39932C-page 370
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
FIGURE 23-3:
HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1)
CASE 1:
LVDIF may not be set
VHLVD
VDD
LVDIF
Enable HLVD
TIRVST
IRVST
LVDIF cleared in software
Internal Reference is stable
CASE 2:
VHLVD
VDD
LVDIF
Enable HLVD
TIRVST
IRVST
Internal Reference is stable
LVDIF cleared in software
LVDIF cleared in software,
LVDIF remains set since HLVD condition still exists
23.5
Applications
FIGURE 23-4:
In many applications, it is desirable to have the ability to
detect a drop below, or rise above, a particular threshold.
For general battery applications, Figure 23-4 provides a
possible voltage curve.
VA
VB
Voltage
Over time, the device voltage decreases. When the
device voltage reaches voltage, VA, the HLVD logic
generates an interrupt at time, TA. The interrupt could
cause the execution of an ISR, which would allow the
application to perform “housekeeping tasks” and
perform a controlled shutdown before the device
voltage exits the valid operating range at TB.
TYPICAL HIGH/
LOW-VOLTAGE DETECT
APPLICATION
The HLVD, thus, would give the application a time
window, represented by the difference between TA and
TB, to safely exit.
Time
TA
TB
Legend: VA = HLVD trip point
VB = Minimum valid device
operating voltage
© 2009 Microchip Technology Inc.
DS39932C-page 371
PIC18F46J11 FAMILY
23.6
Operation During Sleep
23.7
When enabled, the HLVD circuitry continues to operate
during Sleep. If the device voltage crosses the trip
point, the LVDIF bit will be set and the device will wakeup from Sleep. Device execution will continue from the
interrupt vector address if interrupts have been globally
enabled.
TABLE 23-1:
Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the HLVD module to be turned off.
REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
HLVDCON
VDIRMAG
BGVST
IRVST
HLVDEN
HLVDL3
HLVDL2
HLVDL1
HLVDL0
66
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
63
PIR2
OSCFIF
CM1IF
CM2IF
—
BCLIF
LVDIF
TMR3IF
CCP2IF
65
PIE2
OSCFIE
CM1IE
CM2IE
—
BCLIE
LVDIE
TMR3IE
CCP2IE
65
IPR2
OSCFIP
CM1IP
CM2IP
—
BCLIP
LVDIP
TMR3IP
CCP2IP
65
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module.
DS39932C-page 372
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
24.0
CHARGE TIME
MEASUREMENT UNIT (CTMU)
•
•
•
•
Control of response to edges
Time measurement resolution of 1 nanosecond
High precision time measurement
Time delay of external or internal signal
asynchronous to system clock
• Accurate current source suitable for capacitive
measurement
The Charge Time Measurement Unit (CTMU) is a
flexible analog module that provides accurate differential time measurement between pulse sources, as well
as asynchronous pulse generation. By working with
other on-chip analog modules, the CTMU can be used
to precisely measure time, measure capacitance,
measure relative changes in capacitance or generate
output pulses with a specific time delay. The CTMU is
ideal for interfacing with capacitive-based sensors.
The CTMU works in conjunction with the A/D Converter
to provide up to 13 channels for time or charge
measurement, depending on the specific device and
the number of A/D channels available. When configured for time delay, the CTMU is connected to one of
the analog comparators. The level-sensitive input edge
sources can be selected from four sources: two
external inputs or ECCP1/ECCP2 Special Event
Triggers.
The module includes the following key features:
• Up to 13 channels available for capacitive or time
measurement input
• On-chip precision current source
• Four-edge input trigger sources
• Polarity control for each edge source
• Control of edge sequence
FIGURE 24-1:
Figure 24-1 provides a block diagram of the CTMU.
CTMU BLOCK DIAGRAM
CTMUCON
EDGEN
EDGSEQEN
EDG1SELx
EDG1POL
EDG2SELx
EDG2POL
CTEDG1
CTEDG2
CTMUICON
ITRIM<5:0>
IRNG<1:0>
EDG1STAT
EDG2STAT
Edge
Control
Logic
TGEN
IDISSEN
Current Source
Current
Control
ECCP2
CTMU
Control
Logic
Pulse
Generator
ECCP1
A/D Converter
CTPLS
Comparator 2
Input
Comparator 2 Output
© 2009 Microchip Technology Inc.
DS39932C-page 373
PIC18F46J11 FAMILY
24.1
CTMU Operation
The CTMU works by using a fixed current source to
charge a circuit. The type of circuit depends on the type
of measurement being made. In the case of charge
measurement, the current is fixed, and the amount of
time the current is applied to the circuit is fixed. The
amount of voltage read by the A/D is then a measurement of the capacitance of the circuit. In the case of
time measurement, the current, as well as the capacitance of the circuit, is fixed. In this case, the voltage
read by the A/D is then representative of the amount of
time elapsed from the time the current source starts
and stops charging the circuit.
If the CTMU is being used as a time delay, both
capacitance and current source are fixed, as well as the
voltage supplied to the comparator circuit. The delay of
a signal is determined by the amount of time it takes the
voltage to charge to the comparator threshold voltage.
24.1.1
THEORY OF OPERATION
The operation of the CTMU is based on the equation
for charge:
dV
C = I ⋅ ------dT
More simply, the amount of charge measured in
coulombs in a circuit is defined as current in amperes
(I) multiplied by the amount of time in seconds that the
current flows (t). Charge is also defined as the
capacitance in farads (C) multiplied by the voltage of
the circuit (V). It follows that:
I ⋅ t = C ⋅ V.
The CTMU module provides a constant, known current
source. The A/D Converter is used to measure (V) in
the equation, leaving two unknowns: capacitance (C)
and time (t). The above equation can be used to calculate capacitance or time, by either the relationship
using the known fixed capacitance of the circuit:
t = (C ⋅ V) ⁄ I
or by:
C = (I ⋅ t) ⁄ V
using a fixed time that the current source is applied to
the circuit.
24.1.2
CURRENT SOURCE
At the heart of the CTMU is a precision current source,
designed to provide a constant reference for measurements. The level of current is user-selectable across
three ranges or a total of two orders of magnitude, with
the ability to trim the output in ±2% increments
(nominal). The current range is selected by the
IRNG<1:0> bits (CTMUICON<9:8>), with a value of
‘00’ representing the lowest range.
DS39932C-page 374
Current trim is provided by the ITRIM<5:0> bits
(CTMUICON<7:2>). These six bits allow trimming of
the current source in steps of approximately 2% per
step. Note that half of the range adjusts the current
source positively and the other half reduces the current
source. A value of ‘000000’ is the neutral position (no
change). A value of ‘100000’ is the maximum negative
adjustment (approximately -62%) and ‘011111’ is the
maximum positive adjustment (approximately +62%).
24.1.3
EDGE SELECTION AND CONTROL
CTMU measurements are controlled by edge events
occurring on the module’s two input channels. Each
channel, referred to as Edge 1 and Edge 2, can be configured to receive input pulses from one of the edge
input pins (CTEDG1 and CTEDG2) or ECCPx Special
Event Triggers. The input channels are level-sensitive,
responding to the instantaneous level on the channel
rather than a transition between levels. The inputs are
selected using the EDG1SEL and EDG2SEL bit pairs
(CTMUCONL<3:2 and 6:5>).
In addition to source, each channel can be configured for
event polarity using the EDGE2POL and EDGE1POL
bits (CTMUCONL<7,4>). The input channels can also
be filtered for an edge event sequence (Edge 1 occurring before Edge 2) by setting the EDGSEQEN bit
(CTMUCONH<2>).
24.1.4
EDGE STATUS
The CTMUCON register also contains two status bits:
EDG2STAT and EDG1STAT (CTMUCONL<1:0>).
Their primary function is to show if an edge response
has occurred on the corresponding channel. The
CTMU automatically sets a particular bit when an edge
response is detected on its channel. The level-sensitive
nature of the input channels also means that the status
bits become set immediately if the channel’s configuration is changed and is the same as the channel’s
current state.
The module uses the edge status bits to control the current source output to external analog modules (such as
the A/D Converter). Current is only supplied to external
modules when only one (but not both) of the status bits
is set, and shuts current off when both bits are either
set or cleared. This allows the CTMU to measure current only during the interval between edges. After both
status bits are set, it is necessary to clear them before
another measurement is taken. Both bits should be
cleared simultaneously, if possible, to avoid re-enabling
the CTMU current source.
In addition to being set by the CTMU hardware, the
edge status bits can also be set by software. This is
also the user’s application to manually enable or
disable the current source. Setting either one (but not
both) of the bits enables the current source. Setting or
clearing both bits at once disables the source.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
24.1.5
INTERRUPTS
The CTMU sets its interrupt flag (PIR3<2>) whenever
the current source is enabled, then disabled. An interrupt is generated only if the corresponding interrupt
enable bit (PIE3<2>) is also set. If edge sequencing is
not enabled (i.e., Edge 1 must occur before Edge 2), it
is necessary to monitor the edge status bits and
determine which edge occurred last and caused the
interrupt.
24.2
CTMU Module Initialization
The following sequence is a general guideline used to
initialize the CTMU module:
1.
Select the current source range using the IRNG
bits (CTMUICON<1:0>).
2. Adjust the current source trim using the ITRIM
bits (CTMUICON<7:2>).
3. Configure the edge input sources for Edge 1 and
Edge 2 by setting the EDG1SEL and EDG2SEL
bits (CTMUCONL<3:2 and 6:5>).
4. Configure the input polarities for the edge inputs
using the EDG1POL and EDG2POL bits
(CTMUCONL<4,7>). The default configuration
is for negative edge polarity (high-to-low
transitions).
5. Enable edge sequencing using the EDGSEQEN
bit (CTMUCONH<2>). By default, edge
sequencing is disabled.
6. Select the operating mode (Measurement or
Time Delay) with the TGEN bit. The default
mode is Time/Capacitance Measurement.
7. Discharge the connected circuit by setting the
IDISSEN bit (CTMUCONH<1>); after waiting a
sufficient time for the circuit to discharge, clear
IDISSEN.
8. Disable the module by clearing the CTMUEN bit
(CTMUCONH<7>).
9. Enable the module by setting the CTMUEN bit.
10. Clear the Edge Status bits: EDG2STAT and
EDG1STAT (CTMUCONL<1:0>).
11. Enable both edge inputs by setting the EDGEN
bit (CTMUCONH<3>).
Depending on the type of measurement or pulse
generation being performed, one or more additional
modules may also need to be initialized and configured
with the CTMU module:
• Edge Source Generation: In addition to the
external edge input pins, both Timer1 and the
Output Compare/PWM1 module can be used as
edge sources for the CTMU.
• Capacitance or Time Measurement: The CTMU
module uses the A/D Converter to measure the
voltage across a capacitor that is connected to one
of the analog input channels.
• Pulse Generation: When generating system clock
independent output pulses, the CTMU module
uses Comparator 2 and the associated
comparator voltage reference.
24.3
The CTMU requires calibration for precise measurements of capacitance and time, as well as for accurate
time delay. If the application only requires measurement
of a relative change in capacitance or time, calibration is
usually not necessary. An example of this type of application would include a capacitive touch switch, in which
the touch circuit has a baseline capacitance, and the
added capacitance of the human body changes the
overall capacitance of a circuit.
If actual capacitance or time measurement is required,
two hardware calibrations must take place: the current
source needs calibration to set it to a precise current,
and the circuit being measured needs calibration to
measure and/or nullify all other capacitance other than
that to be measured.
24.3.1
CURRENT SOURCE CALIBRATION
The current source on board the CTMU module has a
range of ±60% nominal for each of three current
ranges. Therefore, for precise measurements, it is
possible to measure and adjust this current source by
placing a high precision resistor, RCAL, onto an unused
analog channel. An example circuit is shown in
Figure 24-2. The current source measurement is
performed using the following steps:
1.
2.
3.
4.
5.
6.
© 2009 Microchip Technology Inc.
Calibrating the CTMU Module
Initialize the A/D Converter.
Initialize the CTMU.
Enable the current source by setting EDG1STAT
(CTMUCONL<0>).
Issue settling time delay.
Perform A/D conversion.
Calculate the current source current using
I = V/ RCAL, where RCAL is a high precision
resistance and V is measured by performing an
A/D conversion.
DS39932C-page 375
PIC18F46J11 FAMILY
The CTMU current source may be trimmed with the
trim bits in CTMUICON using an iterative process to get
an exact desired current. Alternatively, the nominal
value without adjustment may be used; it may be
stored by the software for use in all subsequent
capacitive or time measurements.
To calculate the value for RCAL, the nominal current
must be chosen, and then the resistance can be
calculated. For example, if the A/D Converter reference
voltage is 3.3V, use 70% of full scale, or 2.31V as the
desired approximate voltage to be read by the A/D
Converter. If the range of the CTMU current source is
selected to be 0.55 μA, the resistor value needed is calculated as RCAL = 2.31V/0.55 μA, for a value of 4.2 MΩ.
Similarly, if the current source is chosen to be 5.5 μA,
RCAL would be 420,000Ω, and 42,000Ω if the current
source is set to 55 μA.
FIGURE 24-2:
A value of 70% of full-scale voltage is chosen to make
sure that the A/D Converter was in a range that is well
above the noise floor. Keep in mind that if an exact current is chosen, that is to incorporate the trimming bits
from CTMUICON, the resistor value of RCAL may need
to be adjusted accordingly. RCAL may also be adjusted
to allow for available resistor values. RCAL should be of
the highest precision available, keeping in mind the
amount of precision needed for the circuit that the
CTMU will be used to measure. A recommended
minimum would be 0.1% tolerance.
The following examples show one typical method for
performing a CTMU current calibration. Example 24-1
demonstrates how to initialize the A/D Converter and
the CTMU; this routine is typical for applications using
both modules. Example 24-2 demonstrates one
method for the actual calibration routine.
CTMU CURRENT SOURCE
CALIBRATION CIRCUIT
PIC18F46J11 Device
Current Source
CTMU
A/D Converter
ANx
RCAL
DS39932C-page 376
A/D
MUX
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
EXAMPLE 24-1:
SETUP FOR CTMU CALIBRATION ROUTINES
#include "p18cxxx.h"
/**************************************************************************/
/*Setup CTMU *****************************************************************/
/**************************************************************************/
void setup(void)
{ //CTMUCON - CTMU Control register
CTMUCONH = 0x00;
//make sure CTMU is disabled
CTMUCONL = 0x90;
//CTMU continues to run when emulator is stopped,CTMU continues
//to run in idle mode,Time Generation mode disabled, Edges are blocked
//No edge sequence order, Analog current source not grounded, trigger
//output disabled, Edge2 polarity = positive level, Edge2 source =
//source 0, Edge1 polarity = positive level, Edge1 source = source 0,
//CTMUICON - CTMU Current Control Register
CTMUICON = 0x01;
//0.55uA, Nominal - No Adjustment
/**************************************************************************/
//Setup AD converter;
/**************************************************************************/
TRISA=0x04;
//set channel 2 as an input
// Configured AN2 as an analog channel
// ANCON0
ANCON0 = 0XFB;
// ANCON1
ANCON1 = 0X1F;
// ADCON1
ADCON1bits.ADFM=1;
ADCON1bits.ADCAL=0;
ADCON1bits.ACQT=1;
ADCON1bits.ADCS=2;
//
//
//
//
ANCON1bits.VBGEN=1;
// Turn on the Bandgap needed for Rev A0 parts
// ADCON0
ADCON0bits.VCFG0 =0;
ADCON0bits.VCFG1 =0;
ADCON0bits.CHS=2;
// Vref+ = AVdd
// Vref- = AVss
// Select ADC channel
ADCON0bits.ADON=1;
// Turn on ADC
Resulst format 1= Right justified
Normal A/D conversion operation
Acquition time 7 = 20TAD 2 = 4TAD 1=2TAD
Clock conversion bits 6= FOSC/64 2=FOSC/32
}
© 2009 Microchip Technology Inc.
DS39932C-page 377
PIC18F46J11 FAMILY
EXAMPLE 24-2:
CURRENT CALIBRATION ROUTINE
#include "p18cxxx.h"
#define COUNT 500
#define DELAY for(i=0;i<COUNT;i++)
#define RCAL .027
#define ADSCALE 1023
#define ADREF 3.3
int main(void)
{
int i;
int j = 0;
unsigned int Vread = 0;
double VTot = 0;
float Vavg=0, Vcal=0, CTMUISrc = 0;
//@ 8MHz = 125uS.
//R value is 4200000 (4.2M)
//scaled so that result is in
//1/100th of uA
//for unsigned conversion 10 sig bits
//Vdd connected to A/D Vr+
//index for loop
//float values stored for calcs
//assume CTMU and A/D have been setup correctly
//see Example 25-1 for CTMU & A/D setup
setup();
CTMUCONHbits.CTMUEN = 1;
CTMUCONLbits.EDG1STAT = 0;
CTMUCONLbits.EDG2STAT = 0;
for(j=0;j<10;j++)
{
CTMUCONHbits.IDISSEN = 1;
DELAY;
CTMUCONHbits.IDISSEN = 0;
CTMUCONLbits.EDG1STAT = 1;
//Enable the CTMU
// Set Edge status bits to zero
//drain charge on the circuit
//wait 125us
//end drain of circuit
DELAY;
CTMUCONLbits.EDG1STAT = 0;
//Begin charging the circuit
//using CTMU current source
//wait for 125us
//Stop charging circuit
PIR1bits.ADIF = 0;
ADCON0bits.GO=1;
while(!PIR1bits.ADIF);
//make sure A/D Int not set
//and begin A/D conv.
//Wait for A/D convert complete
Vread = ADRES;
PIR1bits.ADIF = 0;
VTot += Vread;
//Get the value from the A/D
//Clear A/D Interrupt Flag
//Add the reading to the total
}
Vavg = (float)(VTot/10.000);
Vcal = (float)(Vavg/ADSCALE*ADREF);
CTMUISrc = Vcal/RCAL;
//Average of 10 readings
//CTMUISrc is in 1/100ths of uA
}
DS39932C-page 378
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
24.3.2
CAPACITANCE CALIBRATION
There is a small amount of capacitance from the internal A/D Converter sample capacitor as well as stray
capacitance from the circuit board traces and pads that
affect the precision of capacitance measurements. A
measurement of the stray capacitance can be taken by
making sure the desired capacitance to be measured
has been removed. The measurement is then
performed using the following steps:
1.
2.
3.
4.
5.
6.
Initialize the A/D Converter and the CTMU.
Set EDG1STAT (= 1).
Wait for a fixed delay of time t.
Clear EDG1STAT.
Perform an A/D conversion.
Calculate the stray and A/D sample capacitances:
An iterative process may need to be used to adjust the
time, t, that the circuit is charged to obtain a reasonable
voltage reading from the A/D Converter. The value of t
may be determined by setting COFFSET to a theoretical
value, then solving for t. For example, if CSTRAY is
theoretically calculated to be 11 pF, and V is expected
to be 70% of VDD, or 2.31V, then t would be:
(4 pF + 11 pF) • 2.31V/0.55 μA
or 63 μs.
See Example 24-3 for a typical routine for CTMU
capacitance calibration.
C OFFSET = C STRAY + CAD = ( I ⋅ t ) ⁄ V
where I is known from the current source measurement
step, t is a fixed delay and V is measured by performing
an A/D conversion.
This measured value is then stored and used for
calculations of time measurement or subtracted for
capacitance measurement. For calibration, it is
expected that the capacitance of CSTRAY + CAD is
approximately known. CAD is approximately 4 pF.
© 2009 Microchip Technology Inc.
DS39932C-page 379
PIC18F46J11 FAMILY
EXAMPLE 24-3:
CAPACITANCE CALIBRATION ROUTINE
#include "p18cxxx.h"
#define
#define
#define
#define
bits
#define
#define
COUNT 25
ETIME COUNT*2.5
DELAY for(i=0;i<COUNT;i++)
ADSCALE 1023
//@ 8MHz INTFRC = 62.5 us.
//time in uS
ADREF 3.3
RCAL .027
//Vdd connected to A/D Vr+
//R value is 4200000 (4.2M)
//scaled so that result is in
//1/100th of uA
//for unsigned conversion 10 sig
int main(void)
{
int i;
int j = 0;
//index for loop
unsigned int Vread = 0;
float CTMUISrc, CTMUCap, Vavg, VTot, Vcal;
//assume CTMU and A/D have been setup correctly
//see Example 25-1 for CTMU & A/D setup
setup();
CTMUCONHbits.CTMUEN = 1;
CTMUCONLbits.EDG1STAT = 0;
CTMUCONLbits.EDG2STAT = 0;
for(j=0;j<10;j++)
{
CTMUCONHbits.IDISSEN = 1;
DELAY;
CTMUCONHbits.IDISSEN = 0;
CTMUCONLbits.EDG1STAT = 1;
//Enable the CTMU
// Set Edge status bits to zero
//drain charge on the circuit
//wait 125us
//end drain of circuit
DELAY;
CTMUCONLbits.EDG1STAT = 0;
//Begin charging the circuit
//using CTMU current source
//wait for 125us
//Stop charging circuit
PIR1bits.ADIF = 0;
ADCON0bits.GO=1;
while(!PIR1bits.ADIF);
//make sure A/D Int not set
//and begin A/D conv.
//Wait for A/D convert complete
Vread = ADRES;
PIR1bits.ADIF = 0;
VTot += Vread;
//Get the value from the A/D
//Clear A/D Interrupt Flag
//Add the reading to the total
}
Vavg = (float)(VTot/10.000);
Vcal = (float)(Vavg/ADSCALE*ADREF);
CTMUISrc = Vcal/RCAL;
CTMUCap = (CTMUISrc*ETIME/Vcal)/100;
//Average of 10 readings
//CTMUISrc is in 1/100ths of uA
}
DS39932C-page 380
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
24.4
Measuring Capacitance with the
CTMU
There are two separate methods of measuring capacitance with the CTMU. The first is the absolute method,
in which the actual capacitance value is desired. The
second is the relative method, in which the actual
capacitance is not needed, rather an indication of a
change in capacitance is required.
24.4.1
ABSOLUTE CAPACITANCE
MEASUREMENT
For absolute capacitance measurements, both the
current and capacitance calibration steps found in
Section 24.3 “Calibrating the CTMU Module”
should be followed. Capacitance measurements are
then performed using the following steps:
1.
2.
3.
4.
5.
6.
7.
8.
Initialize the A/D Converter.
Initialize the CTMU.
Set EDG1STAT.
Wait for a fixed delay, T.
Clear EDG1STAT.
Perform an A/D conversion.
Calculate the total capacitance, CTOTAL = (I * T)/V,
where I is known from the current source
measurement step (see Section 24.3.1 “Current
Source Calibration”), T is a fixed delay and V is
measured by performing an A/D conversion.
Subtract the stray and A/D capacitance
(COFFSET from Section 24.3.2 “Capacitance
Calibration”) from CTOTAL to determine the
measured capacitance.
© 2009 Microchip Technology Inc.
24.4.2
RELATIVE CHARGE
MEASUREMENT
An application may not require precise capacitance
measurements. For example, when detecting a valid
press of a capacitance-based switch, detecting a relative change of capacitance is of interest. In this type of
application, when the switch is open (or not touched),
the total capacitance is the capacitance of the combination of the board traces, the A/D Converter, etc. A larger
voltage will be measured by the A/D Converter. When
the switch is closed (or is touched), the total
capacitance is larger due to the addition of the
capacitance of the human body to the above listed
capacitances, and a smaller voltage will be measured
by the A/D Converter.
Detecting capacitance changes is easily accomplished
with the CTMU using these steps:
1.
2.
3.
4.
5.
Initialize the A/D Converter and the CTMU.
Set EDG1STAT.
Wait for a fixed delay.
Clear EDG1STAT.
Perform an A/D conversion.
The voltage measured by performing the A/D conversion is an indication of the relative capacitance. Note
that in this case, no calibration of the current source or
circuit capacitance measurement is needed. See
Example 24-4 for a sample software routine for a
capacitive touch switch.
DS39932C-page 381
PIC18F46J11 FAMILY
EXAMPLE 24-4:
ROUTINE FOR CAPACITIVE TOUCH SWITCH
#include "p18cxxx.h"
#define
#define
#define
#define
COUNT 500
DELAY for(i=0;i<COUNT;i++)
OPENSW 1000
TRIP 300
#define HYST 65
//@ 8MHz = 125uS.
//Un-pressed switch value
//Difference between pressed
//and un-pressed switch
//amount to change
//from pressed to un-pressed
#define PRESSED 1
#define UNPRESSED 0
int main(void)
{
unsigned int Vread;
unsigned int switchState;
int i;
//storage for reading
//assume CTMU and A/D have been setup correctly
//see Example 25-1 for CTMU & A/D setup
setup();
CTMUCONHbits.CTMUEN = 1;
CTMUCONLbits.EDG1STAT = 0;
CTMUCONLbits.EDG2STAT = 0;
CTMUCONHbits.IDISSEN = 1;
DELAY;
CTMUCONHbits.IDISSEN = 0;
// Enable the CTMU
// Set Edge status bits to zero
CTMUCONLbits.EDG1STAT = 1;
DELAY;
CTMUCONLbits.EDG1STAT = 0;
//Begin charging the circuit
//using CTMU current source
//wait for 125us
//Stop charging circuit
PIR1bits.ADIF = 0;
ADCON0bits.GO=1;
while(!PIR1bits.ADIF);
//make sure A/D Int not set
//and begin A/D conv.
//Wait for A/D convert complete
Vread = ADRES;
//Get the value from the A/D
//drain charge on the circuit
//wait 125us
//end drain of circuit
if(Vread < OPENSW - TRIP)
{
switchState = PRESSED;
}
else if(Vread > OPENSW - TRIP + HYST)
{
switchState = UNPRESSED;
}
}
DS39932C-page 382
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
24.5
Measuring Time with the CTMU
Module
It is assumed that the time measured is small enough
that the capacitance, COFFSET, provides a valid voltage
to the A/D Converter. For the smallest time measurement, always set the A/D Channel Select register
(AD1CHS) to an unused A/D channel; the corresponding pin for which is not connected to any circuit board
trace. This minimizes added stray capacitance, keeping the total circuit capacitance close to that of the A/D
Converter itself (4-5 pF). To measure longer time
intervals, an external capacitor may be connected to an
A/D channel and this channel selected when making a
time measurement.
Time can be precisely measured after the ratio (C/I) is
measured from the current and capacitance calibration
step by following these steps:
1.
2.
3.
4.
5.
Initialize the A/D Converter and the CTMU.
Set EDG1STAT.
Set EDG2STAT.
Perform an A/D conversion.
Calculate the time between edges as T = (C/I) * V,
where I is calculated in the current calibration step
(Section 24.3.1 “Current Source Calibration”),
C is calculated in the capacitance calibration step
(Section 24.3.2 “Capacitance Calibration”) and
V is measured by performing the A/D conversion.
FIGURE 24-3:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME
MEASUREMENT
PIC18F46J11 Device
CTMU
CTEDG1
EDG1
CTEDG2
EDG2
Current Source
Output Pulse
ANX
A/D Converter
CAD
RPR
© 2009 Microchip Technology Inc.
DS39932C-page 383
PIC18F46J11 FAMILY
24.6
Creating a Delay with the CTMU
Module
An example use of this feature is for interfacing with
variable capacitive-based sensors, such as a humidity
sensor. As the humidity varies, the pulse width output
on CTPLS will vary. The CTPLS output pin can be connected to an input capture pin and the varying pulse
width is measured to determine the humidity in the
application.
A unique feature on board the CTMU module is its
ability to generate system clock independent output
pulses based on an external capacitor value. This is
accomplished using the internal comparator voltage
reference module, Comparator 2 input pin and an
external capacitor. The pulse is output onto the CTPLS
pin. To enable this mode, set the TGEN bit.
Follow these steps to use this feature:
1.
2.
3.
See Figure 24-4 for an example circuit. CPULSE is
chosen by the user to determine the output pulse width
on CTPLS. The pulse width is calculated by
T = (CPULSE /I)*V, where I is known from the current
source measurement step (Section 24.3.1 “Current
Source Calibration”) and V is the internal reference
voltage (CVREF).
FIGURE 24-4:
4.
5.
Initialize Comparator 2.
Initialize the comparator voltage reference.
Initialize the CTMU and enable time delay
generation by setting the TGEN bit.
Set EDG1STAT.
When CPULSE charges to the value of the voltage
reference trip point, an output pulse is generated
on CTPLS.
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE
DELAY GENERATION
PIC18F46J11 Device
CTEDG1
EDG1
CTMU
CTPLS
Current Source
Comparator
C2INB
CPULSE
24.7
24.7.1
C2
CVREF
Operation During Sleep/Idle
Modes
SLEEP MODE AND DEEP SLEEP
MODES
When the device enters any Sleep mode, the CTMU
module current source is always disabled. If the CTMU
is performing an operation that depends on the current
source when Sleep mode is invoked, the operation may
not terminate correctly. Capacitance and time
measurements may return erroneous values.
24.7.2
IDLE MODE
The behavior of the CTMU in Idle mode is determined
by the CTMUSIDL bit (CTMUCONH<5>). If CTMUSIDL
is cleared, the module will continue to operate in Idle
mode. If CTMUSIDL is set, the module’s current source
is disabled when the device enters Idle mode. If the
DS39932C-page 384
module is performing an operation when Idle mode is
invoked, in this case, the results will be similar to those
with Sleep mode.
24.8
Effects of a Reset on CTMU
Upon Reset, all registers of the CTMU are cleared. This
leaves the CTMU module disabled, its current source is
turned off and all configuration options return to their
default settings. The module needs to be re-initialized
following any Reset.
If the CTMU is in the process of taking a measurement at
the time of Reset, the measurement will be lost. A partial
charge may exist on the circuit that was being measured,
and should be properly discharged before the CTMU
makes subsequent attempts to make a measurement.
The circuit is discharged by setting and then clearing the
IDISSEN bit (CTMUCONH<1>) while the A/D Converter
is connected to the appropriate channel.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
24.9
Registers
The CTMUCONH and CTMUCONL registers
(Register 24-1 and Register 24-2) contain control bits
for configuring the CTMU module edge source selection, edge source polarity selection, edge sequencing,
A/D trigger, analog circuit capacitor discharge and
enables. The CTMUICON register (Register 24-3) has
bits for selecting the current source range and current
source trim.
There are three control registers for the CTMU:
• CTMUCONH
• CTMUCONL
• CTMUICON
REGISTER 24-1:
CTMUCONH: CTMU CONTROL REGISTER HIGH (ACCESS FB3h)
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
CTMUEN
—
CTMUSIDL
TGEN
EDGEN
EDGSEQEN
IDISSEN
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
CTMUEN: CTMU Enable bit
1 = Module is enabled
0 = Module is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5
CTMUSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 4
TGEN: Time Generation Enable bit
1 = Enables edge delay generation
0 = Disables edge delay generation
bit 3
EDGEN: Edge Enable bit
1 = Edges are not blocked
0 = Edges are blocked
bit 2
EDGSEQEN: Edge Sequence Enable bit
1 = Edge 1 event must occur before Edge 2 event can occur
0 = No edge sequence is needed
bit 1
IDISSEN: Analog Current Source Control bit
1 = Analog current source output is grounded
0 = Analog current source output is not grounded
bit 0
Reserved: Write as ‘0’
© 2009 Microchip Technology Inc.
x = Bit is unknown
DS39932C-page 385
PIC18F46J11 FAMILY
REGISTER 24-2:
CTMUCONL: CTMU CONTROL REGISTER LOW (ACCESS FB2h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EDG2POL
EDG2SEL1
EDG2SEL0
EDG1POL
EDG1SEL1
EDG1SEL0
EDG2STAT
EDG1STAT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
EDG2POL: Edge 2 Polarity Select bit
1 = Edge 2 programmed for a positive edge response
0 = Edge 2 programmed for a negative edge response
bit 6-5
EDG2SEL<1:0>: Edge 2 Source Select bits
11 = CTEDG1 pin
10 = CTEDG2 pin
01 = ECCP1 Special Event Trigger
00 = ECCP2 Special Event Trigger
bit 4
EDG1POL: Edge 1 Polarity Select bit
1 = Edge 1 programmed for a positive edge response
0 = Edge 1 programmed for a negative edge response
bit 3-2
EDG1SEL<1:0>: Edge 1 Source Select bits
11 = CTEDG1 pin
10 = CTEDG2 pin
01 = ECCP1 Special Event Trigger
00 = ECCP2 Special Event Trigger
bit 1
EDG2STAT: Edge 2 Status bit
1 = Edge 2 event has occurred
0 = Edge 2 event has not occurred
bit 0
EDG1STAT: Edge 1 Status bit
1 = Edge 1 event has occurred
0 = Edge 1 event has not occurred
DS39932C-page 386
x = Bit is unknown
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 24-3:
CTMUICON: CTMU CURRENT CONTROL REGISTER (ACCESS FB1h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ITRIM5
ITRIM4
ITRIM3
ITRIM2
ITRIM1
ITRIM0
IRNG1
IRNG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
ITRIM<5:0>: Current Source Trim bits
011111 = Maximum positive change from nominal current
011110
.
.
.
000001 = Minimum positive change from nominal current
000000 = Nominal current output specified by IRNG<1:0>
111111 = Minimum negative change from nominal current
.
.
.
100010
100001 = Maximum negative change from nominal current
bit 1-0
IRNG<1:0>: Current Source Range Select bits
11 = 100 × Base current
10 = 10 × Base current
01 = Base current level (0.55 μA nominal)
00 = Current source disabled
TABLE 24-1:
REGISTERS ASSOCIATED WITH CTMU MODULE
Name
Bit 7
CTMUCONH
CTMUEN
CTMUCONL EDG2POL
CTMUICON
Legend:
x = Bit is unknown
ITRIM5
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page:
EDGSEQEN
IDISSEN
—
65
—
CTMUSIDL
TGEN
EDGEN
EDG2SEL1
EDG2SEL0
EDG1POL
EDG1SEL1
ITRIM4
ITRIM3
ITRIM2
ITRIM1
EDG1SEL0 EDG2STAT EDG1STAT
ITRIM0
IRNG1
IRNG0
65
65
— = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
© 2009 Microchip Technology Inc.
DS39932C-page 387
PIC18F46J11 FAMILY
NOTES:
DS39932C-page 388
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
25.0
SPECIAL FEATURES OF THE
CPU
PIC18F46J11 family devices include several features
intended to maximize reliability and minimize cost
through elimination of external components. These are:
• Oscillator Selection
• Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor (FSCM)
• Two-Speed Start-up
• Code Protection
• In-Circuit Serial Programming (ICSP)
25.1.1
CONSIDERATIONS FOR
CONFIGURING THE PIC18F46J11
FAMILY DEVICES
Unlike some previous PIC18 microcontrollers, devices
of the PIC18F46J11 family do not use persistent memory registers to store configuration information. The
Configuration
registers,
CONFIG1L
through
CONFIG4H, are implemented as volatile memory.
Immediately after power-up, or after a device Reset,
the microcontroller hardware automatically loads the
CONFIG1L through CONFIG4L registers with configuration data stored in nonvolatile Flash program
memory. The last four words of Flash program memory,
known as the Flash Configuration Words (FCW), are
used to store the configuration data.
Table 25-1 provides the Flash program memory, which
will be loaded into the corresponding Configuration
register.
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 2.0
“Oscillator Configurations”.
When creating applications for these devices, users
should always specifically allocate the location of the
FCW for configuration data. This is to make certain that
program code is not stored in this address when the
code is compiled.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet. In
addition to their Power-up and Oscillator Start-up
Timers provided for Resets, the PIC18F46J11 family of
devices have a configurable Watchdog Timer (WDT),
which is controlled in software.
The four Most Significant bits (MSb) of the FCW corresponding to CONFIG1H, CONFIG2H, CONFIG3H and
CONFIG4H should always be programmed to ‘1111’.
This makes these FCWs appear to be NOP instructions
in the remote event that their locations are ever
executed by accident.
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure.
Two-Speed Start-up enables code to be executed
almost immediately on start-up, while the primary clock
source completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
25.1
To prevent inadvertent configuration changes during
code execution, the Configuration registers,
CONFIG1L through CONFIG4L, are loaded only once
per power-up or Reset cycle. User’s firmware can still
change the configuration by using self-reprogramming
to modify the contents of the FCW.
Modifying the FCW will not change the active contents
being used in the CONFIG1L through CONFIG4H
registers until after the device is reset.
Configuration Bits
The Configuration bits can be programmed to select
various device configurations. The configuration data is
stored in the last four words of Flash program memory;
Figure 5-1 depicts this. The configuration data gets
loaded into the volatile Configuration registers,
CONFIG1L through CONFIG4H, which are readable
and mapped to program memory starting at location
300000h.
Table 25-2 provides a complete list. A detailed explanation of the various bit functions is provided in
Register 25-1 through Register 25-6.
© 2009 Microchip Technology Inc.
DS39932C-page 389
PIC18F46J11 FAMILY
TABLE 25-1:
MAPPING OF THE FLASH CONFIGURATION WORDS TO THE CONFIGURATION
REGISTERS
Configuration Register
(Volatile)
Configuration Register
Address
Flash Configuration Byte Address
300000h
XXXF8h
CONFIG1L
CONFIG1H
300001h
XXXF9h
CONFIG2L
300002h
XXXFAh
CONFIG2H
300003h
XXXFBh
CONFIG3L
300004h
XXXFCh
CONFIG3H
300005h
XXXFDh
CONFIG4L
300006h
XXXFEh
CONFIG4H
300007h
XXXFFh
TABLE 25-2:
CONFIGURATION BITS AND DEVICE IDs
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default/
Unprog.
Value(1)
300000h CONFIG1L
DEBUG
XINST
STVREN
—
—
—
—
WDTEN
111- ---1
300001h CONFIG1H
—(2)
—(2)
—(2)
—(2)
—
CP0
—
—
1111 -1--
300002h CONFIG2L
IESO
FCMEN
—
LPT1OSC
T1DIG
FOSC2
FOSC1
FOSC0
11-1 1111
300003h CONFIG2H
—(2)
—(2)
—(2)
—(2)
WDTPS3
WDTPS2
WDTPS1
WDTPS0
1111 1111
300004h CONFIG3L DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 DSWDTEN DSBOREN RTCOSC DSWDTOSC 1111 1111
300005h CONFIG3H
—(2)
—(2)
—(2)
—(2)
MSSPMSK
—
—
IOL1WAY
1111 1--1
300006h CONFIG4L
WPCFG
WPEND
WPFP5
WPFP4
WPFP3
WPFP2
WPFP1
WPFP0
1111 1111
300007h CONFIG4H
—(2)
—(2)
—(2)
—(2)
—
—
—
WPDIS
3FFFFEh DEVID1
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
xxx0 0000(3)
3FFFFFh DEVID2
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
0100 00xx(3)
Legend:
Note 1:
2:
3:
1111 ---1
x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset states, the
configuration bytes maintain their previously programmed states.
The value of these bits in program memory should always be programmed to ‘1’. This ensures that the location is executed as a NOP if it
is accidentally executed.
See Register 25-9 and Register 25-10 for DEVID values. These registers are read-only and cannot be programmed by the user.
DS39932C-page 390
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 25-1:
CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
R/WO-1
R/WO-1
R/WO-1
U-0
U-1
U-1
U-1
R/WO-1
DEBUG
XINST
STVREN
—
—
—
—
WDTEN
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
-n = Value at Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
DEBUG: Background Debugger Enable bit
1 = Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
bit 6
XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled
bit 5
STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Reset on stack overflow/underflow enabled
0 = Reset on stack overflow/underflow disabled
bit 4-1
Unimplemented: Read as ‘0’
bit 0
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on SWDTEN bit)
© 2009 Microchip Technology Inc.
DS39932C-page 391
PIC18F46J11 FAMILY
REGISTER 25-2:
CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
U-1
U-1
U-1
U-1
U-0
R/WO-1
U-0
U-0
—
—
—
—
—
CP0
—
—
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
-n = Value at Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
Unimplemented: Program the corresponding Flash Configuration bit to ‘1’
bit 3
Unimplemented: Maintain as ‘0’
bit 2
CP0: Code Protection bit
1 = Program memory is not code-protected
0 = Program memory is code-protected
bit 1-0
Unimplemented: Maintain as ‘0’
DS39932C-page 392
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 25-3:
R/WO-1
IESO
CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
R/WO-1
U-0
R/WO-1
R/WO-1
R/WO-1
R/WO-1
R/WO-1
FCMEN
—
LPT1OSC
T1DIG
FOSC2
FOSC1
FOSC0
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
-n = Value at Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit
1 = Two-Speed Start-up enabled
0 = Two-Speed Start-up disabled
bit 6
FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor enabled
0 = Fail-Safe Clock Monitor disabled
bit 5
Unimplemented: Read as ‘0’
bit 4
LPT1OSC: Low-Power Timer1 Oscillator Enable bit
1 = Timer1 oscillator configured for high-power operation
0 = Timer1 oscillator configured for low-power operation
bit 3
T1DIG: Secondary Clock Source T1OSCEN Enforcement bit
1 = Secondary oscillator clock source may be selected (OSCCON<1:0> = 01) regardless of the
T1OSCEN (T1CON<3>) state
0 = Secondary oscillator clock source may not be selected unless T1CON<3> = 1
bit 2-0
FOSC<2:0>: Oscillator Selection bits
111 = ECPLL oscillator with PLL software controlled, CLKO on RA6
110 = EC oscillator with CLKO on RA6
101 = HSPLL oscillator with PLL software controlled
100 = HS oscillator
011 = INTOSCPLLO, internal oscillator with PLL software controlled, CLKO on RA6, port function on
RA7
010 = INTOSCPLL, internal oscillator with PLL software controlled, port function on RA6 and RA7
001 = INTOSCO internal oscillator block (INTRC/INTOSC) with CLKO on RA6, port function on RA7
000 = INTOSC internal oscillator block (INTRC/INTOSC), port function on RA6 and RA7
© 2009 Microchip Technology Inc.
DS39932C-page 393
PIC18F46J11 FAMILY
REGISTER 25-4:
CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-1
U-1
U-1
U-1
R/WO-1
R/WO-1
R/WO-1
R/WO-1
—
—
—
—
WDTPS3
WDTPS2
WDTPS1
WDTPS0
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
-n = Value at Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
Unimplemented: Program the corresponding Flash Configuration bit to ‘1’
bit 3-0
WDTPS<3:0>: Watchdog Timer Postscale Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
DS39932C-page 394
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 25-5:
R/WO-1
CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)
R/WO-1
(1)
DSWDTPS3
R/WO-1
R/WO-1
R/WO-1
R/WO-1
R/WO-1
R/WO-1
DSWDTPS2(1) DSWDTPS1(1) DSWDTPS0(1) DSWDTEN(1) DSBOREN(1) RTCOSC DSWDTOSC(1)
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
-n = Value at Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
DSWDTPS<3:0>: Deep Sleep Watchdog Timer Postscale Select bits(1)
The DSWDT prescaler is 32. This creates an approximate base time unit of 1 ms.
1111 = 1:2,147,483,648 (25.7 days)
1110 = 1:536,870,912 (6.4 days)
1101 = 1:134,217,728 (38.5 hours)
1100 = 1:33,554,432 (9.6 hours)
1011 = 1:8,388,608 (2.4 hours)
1010 = 1:2,097,152 (36 minutes)
1001 = 1:524,288 (9 minutes)
1000 = 1:131,072 (135 seconds)
0111 = 1:32,768 (34 seconds)
0110 = 1:8,192 (8.5 seconds)
0101 = 1:2,048 (2.1 seconds)
0100 = 1:512 (528 ms)
0011 = 1:128 (132 ms)
0010 = 1:32 (33 ms)
0001 = 1:8 (8.3 ms)
0000 = 1:2 (2.1 ms)
bit 3
DSWDTEN: Deep Sleep Watchdog Timer Enable bit(1)
1 = DSWDT enabled
0 = DSWDT disabled
bit 2
DSBOREN: Deep Sleep BOR Enable bit(1)
1 = BOR enabled in Deep Sleep (when using PIC18FXXJXX device)
0 = BOR disabled in Deep Sleep (does not affect operation in non Deep Sleep modes)
bit 1
RTCOSC: RTCC Reference Clock Select bit
1 = RTCC uses T1OSC/T1CKI as reference clock
0 = RTCC uses INTRC as reference clock
bit 0
DSWDTOSC: DSWDT Reference Clock Select bit(1)
1 = DSWDT uses INTRC as reference clock
0 = DSWDT uses T1OSC/T1CKI as reference clock
Note 1:
Deep Sleep bits are not available on “LF” devices.
© 2009 Microchip Technology Inc.
DS39932C-page 395
PIC18F46J11 FAMILY
REGISTER 25-6:
CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
U-1
U-1
U-1
U-1
R/WO-1
U-0
U-0
R/WO-1
—
—
—
—
MSSPMSK
—
—
IOL1WAY
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
-n = Value at Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
Unimplemented: Program the corresponding Flash Configuration bit to ‘1’
bit 3
MSSPMSK: MSSP 7-Bit Address Masking Mode Enable bit
1 = 7-Bit Address Masking mode enabled
0 = 5-Bit Address Masking mode enabled
bit 2-1
Unimplemented: Read as ‘0’
bit 0
IOL1WAY: IOLOCK One-Way Set Enable bit
1 = IOLOCK bit (PPSCON<0>) can be set once, provided the unlock sequence has been completed.
Once set, the Peripheral Pin Select registers cannot be written to a second time.
0 = IOLOCK bit (PPSCON<0>) can be set and cleared as needed, provided the unlock sequence has
been completed
REGISTER 25-7:
R/WO-1
WPCFG
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/WO-1
R/WO-1
R/WO-1
R/WO-1
R/WO-1
R/WO-1
R/WO-1
WPEND
WPFP5(2)
WPFP4(3)
WPFP3
WPFP2
WPFP1
WPFP0
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
-n = Value at Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
WPCFG: Write/Erase Protect Configuration Region Select bit (valid when WPDIS = 0)
1 = Configuration Words page is not erase/write-protected, regardless of WPEND and WPFP<5:0>
settings(1)
0 = Configuration Words page is erase/write-protected, regardless of WPEND and WPFP<5:0>(1)
bit 6
WPEND: Write/Erase Protect Region Select bit (valid when WPDIS = 0)
1 = Flash pages WPFP<5:0> to (Configuration Words page) are write/erase protected
0 = Flash pages 0 to WPFP<5:0> are erase/write-protected
bit 5-0
WPFP<5:0>: Write/Erase Protect Page Start/End Location bits(2,3)
Used with WPEND bit to define which pages in Flash will be erase/write-protected.
Note 1:
2:
3:
The “Configuration Words page” contains the FCWs and is the last page of implemented Flash memory on
a given device. Each page consists of 1,024 bytes. For example, on a device with 64 Kbytes of Flash, the
first page is 0 and the last page (Configuration Words page) is 63 (3Fh).
Not available on 32K devices.
Not available on 32K and 16K devices.
DS39932C-page 396
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
REGISTER 25-8:
CONFIG4H: CONFIGURATION REGISTER 4 HIGH (BYTE ADDRESS 300007h)
U-1
U-1
U-1
U-1
U-0
U-0
U-0
R/WO-1
—
—
—
—
—
—
—
WPDIS
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
-n = Value at Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
Unimplemented: Program the corresponding Flash Configuration bit to ‘1’
bit 3-1
Unimplemented: Read as ‘0’
bit 0
WPDIS: Write-Protect Disable bit
1 = WPFP<5:0>, WPEND and WPCFG bits ignored; all Flash memory may be erased or written
0 = WPFP<5:0>, WPEND and WPCFG bits enabled; erase/write-protect active for the selected
region(s)
REGISTER 25-9:
DEVID1: DEVICE ID REGISTER 1 FOR PIC18F46J11 FAMILY DEVICES
(BYTE ADDRESS 3FFFFEh)
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
DEV<2:0>: Device ID bits
These bits are used with DEV<10:3> bits in Device ID Register 2 to identify the part number. See
Register 25-10.
bit 4-0
REV<4:0>: Revision ID bits
These bits are used to indicate the device revision.
© 2009 Microchip Technology Inc.
DS39932C-page 397
PIC18F46J11 FAMILY
REGISTER 25-10: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F46J11 FAMILY DEVICES
(BYTE ADDRESS 3FFFFFh)
R
R
R
R
R
R
R
R
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
DEV<10:3>: Device ID bits
These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number.
DS39932C-page 398
DEV<10:3>
(DEVID2<7:0>)
DEV<2:0>
(DEVID2<7:5>)
Device
0100 1110
001
PIC18F46J11
0100 1110
000
PIC18F45J11
0100 1101
111
PIC18F44J11
0100 1101
110
PIC18F26J11
0100 1101
101
PIC18F25J11
0100 1101
100
PIC18F24J11
0100 1110
111
PIC18LF46J11
0100 1110
110
PIC18LF45J11
0100 1110
101
PIC18LF44J11
0100 1110
100
PIC18LF26J11
0100 1110
011
PIC18LF25J11
0100 1110
010
PIC18LF24J11
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
25.2
Watchdog Timer (WDT)
PIC18F46J11 family devices have both a conventional
WDT circuit and a dedicated, Deep Sleep capable
Watchdog Timer. When enabled, the conventional
WDT operates in normal Run, Idle and Sleep modes.
This data sheet section describes the conventional
WDT circuit.
The dedicated, Deep Sleep capable WDT can only be
enabled in Deep Sleep mode. This timer is described in
Section 3.6.4 “Deep Sleep Watchdog Timer
(DSWDT)”.
The conventional WDT is driven by the INTRC oscillator. When the WDT is enabled, the clock source is also
enabled. The nominal WDT period is 4 ms and has the
same stability as the INTRC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by the WDTPS bits
in Configuration Register 2H. Available periods range
from about 4 ms to 135 seconds (2.25 minutes
depending on voltage, temperature and WDT
postscaler). The WDT and postscaler are cleared
FIGURE 25-1:
whenever a SLEEP or CLRWDT instruction is executed,
or a clock failure (primary or Timer1 oscillator) has
occurred.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
25.2.1
CONTROL REGISTER
The WDTCON register (Register 25-11) is a readable
and writable register. The SWDTEN bit enables or disables WDT operation. This allows software to override
the WDTEN Configuration bit and enable the WDT only
if it has been disabled by the Configuration bit.
LVDSTAT is a read-only status bit that is continuously
updated and provides information about the current
level of VDDCORE. This bit is only valid when the on-chip
voltage regulator is enabled.
WDT BLOCK DIAGRAM
SWDTEN
Enable WDT
INTRC Control
WDT Counter
INTRC Oscillator
Wake-up from
Power-Managed
Modes
÷128
CLRWDT
All Device Resets
Programmable Postscaler
1:1 to 1:32,768
Reset
WDT
Reset
WDT
WDTPS<3:0>
4
Sleep
© 2009 Microchip Technology Inc.
DS39932C-page 399
PIC18F46J11 FAMILY
REGISTER 25-11: WDTCON: WATCHDOG TIMER CONTROL REGISTER (ACCESS FC0h)
R/W-1
R-x
REGSLP(2)
LVDSTAT(2)
R-x
ULPLVL
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
DS(2)
ULPEN
ULPSINK
SWDTEN(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
REGSLP: Voltage Regulator Low-Power Operation Enable bit(2)
1 = On-chip regulator enters low-power operation when device enters Sleep mode
0 = On-chip regulator is active even in Sleep mode
bit 6
LVDSTAT: Low-Voltage Detect Status bit(2)
1 = VDDCORE > 2.45V nominal
0 = VDDCORE < 2.45V nominal
bit 5
ULPLVL: Ultra Low-Power Wake-up Output bit (not valid unless ULPEN = 1)
1 = Voltage on RA0 > ~0.5V
0 = Voltage on RA0 < ~0.5V
bit 4
Unimplemented: Read as ‘0’
bit 3
DS: Deep Sleep Wake-up Status bit (used in conjunction with RCON, POR and BOR bits to determine
Reset source)(2)
1 = If the last exit from POR was caused by a normal wake-up from Deep Sleep
0 = If the last exit from POR was a result of hard cycling VDD, or if the Deep Sleep BOR was enabled
and detected, a (VDD < VDSBOR) and (VDD < VPOR) condition
bit 2
ULPEN: Ultra Low-Power Wake-up Module Enable bit
1 = Ultra Low-Power Wake-up module is enabled; ULPLVL bit indicates comparator output
0 = Ultra Low-Power Wake-up module is disabled
bit 1
ULPSINK: Ultra Low-Power Wake-up Current Sink Enable bit
1 = Ultra Low-Power Wake-up current sink is enabled (if ULPEN = 1)
0 = Ultra Low-Power Wake-up current sink is disabled
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit(1)
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Note 1:
2:
This bit has no effect if the Configuration bit, WDTEN, is enabled.
Not available on devices where the on-chip voltage regulator is disabled (“LF” devices).
TABLE 25-3:
Name
RCON
WDTCON
SUMMARY OF WATCHDOG TIMER REGISTERS
Bit 7
Bit 6
Bit 5
Bit 4
IPEN
—
CM
RI
TO
—
DS
REGSLP LVDSTAT ULPLVL
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
PD
POR
BOR
64
ULPEN ULPSINK SWDTEN
64
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
DS39932C-page 400
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
25.3
On-Chip Voltage Regulator
Note 1: The on-chip voltage regulator is only
available in parts designated with an “F”,
such as PIC18F25J11. The on-chip
regulator is disabled on devices with “LF”
in their part number.
2: The VDDCORE/VCAP pin must never be left
floating. On “F” devices, it must be connected to a capacitor, of size CEFC, to
ground. On “LF” devices, VDDCORE/VCAP
must be connected to a power supply
source between 2.0V and 2.7V.
The digital core logic of the PIC18F46J11 family
devices is designed on an advanced manufacturing
process, which requires 2.0V to 2.7V. The digital core
logic obtains power from the VDDCORE/VCAP power
supply pin.
However, in many applications it may be inconvenient
to run the I/O pins at the same core logic voltage, as it
would restrict the ability of the device to interface with
other, higher voltage devices, such as those run at a
nominal 3.3V. Therefore, all PIC18F46J11 family
devices implement a dual power supply rail topology.
The core logic obtains power from the VDDCORE/VCAP
pin, while the general purpose I/O pins obtain power
from the VDD pin of the microcontroller, which may be
supplied with a voltage between 2.15V to 3.6V (“F”
devices) or 2.0V to 3.6V (“LF” devices).
This dual supply topology allows the microcontroller to
interface with standard 3.3V logic devices, while
running the core logic at a lower voltage of nominally
2.5V.
In order to make the microcontroller more convenient to
use, an integrated 2.5V low dropout, low quiescent
current linear regulator has been integrated on the die
inside PIC18F46J11 family devices. This regulator is
designed specifically to supply the core logic of the
device. It allows PIC18F46J11 family devices to
effectively run from a single power supply rail, without
the need for external regulators.
The on-chip voltage regulator is always enabled on “F”
devices. The VDDCORE/VCAP pin serves simultaneously
as the regulator output pin and the core logic supply
power input pin. A capacitor should be connected to the
VDDCORE/VCAP pin to ground and is necessary for regulator stability. For example connections for PIC18F and
PIC18LF devices, see Figure 25-2.
© 2009 Microchip Technology Inc.
On “LF” devices, the on-chip regulator is always
disabled. This allows the device to save a small amount
of quiescent current consumption, which may be
advantageous in some types of applications, such as
those which will entirely be running at a nominal 2.5V.
On PIC18LF46J11 family devices, the VDDCORE/VCAP
pin still serves as the core logic power supply input pin,
and therefore, must be connected to a 2.0V to 2.7V
supply rail at the application circuit board level. On
these devices, the I/O pins may still optionally be supplied with a voltage between 2.0V to 3.6V, provided that
VDD is always greater than, or equal to,
VDDCORE/VCAP. For example connections for PIC18F
and PIC18LF devices, see Figure 25-2.
Note:
In parts designated with an “LF”, such as
PIC18LF46J11, VDDCORE must never
exceed VDD.
The specifications for core voltage and capacitance are
listed in Section 28.3 “DC Characteristics:
PIC18F46J50 Family (Industrial)”.
25.3.1
VOLTAGE REGULATOR TRACKING
MODE AND LOW-VOLTAGE
DETECTION
When it is enabled, the on-chip regulator provides a constant voltage of 2.5V nominal to the digital core logic.
The regulator can provide this level from a VDD of about
2.5V, all the way up to the device’s VDDMAX. It does not
have the capability to boost VDD levels below 2.5V.
When the VDD supply input voltage drops too low to
regulate to 2.5V, the regulator enters Tracking mode. In
Tracking mode, the regulator output follows VDD, with a
typical voltage drop of 100 mV or less.
The on-chip regulator includes a simple, Low-Voltage
Detect (LVD) circuit. This circuit is separate and independent of the High/Low-Voltage Detect (HLVD) module
described in Section 23.0 “High/Low Voltage Detect
(HLVD)”. The on-chip regulator LVD circuit continuously
monitors the VDDCORE voltage level and updates the
LVDSTAT bit in the WDTCON register. The LVD detect
threshold is set slightly below the normal regulation set
point of the on-chip regulator.
Application firmware may optionally poll the LVDSTAT
bit to determine when it is safe to run at the maximum
rated frequency, so as not to inadvertently violate the
voltage versus frequency requirements provided by
Figure 28-1.
The VDDCORE monitoring LVD circuit is only active
when the on-chip regulator is enabled. On “LF”
devices, the Analog-to-Digital Converter and the HLVD
module can still be used to provide firmware with VDD
and VDDCORE voltage level information.
DS39932C-page 401
PIC18F46J11 FAMILY
FIGURE 25-2:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
PIC18FXXJ11 Devices (Regulator Enabled):
3.3V
PIC18FXXJ11
VDD
VDDCORE/VCAP
CEFC
VSS
PIC18LFXXJ11 Devices (Regulator Disabled):
2.5V
PIC18LFXXJ11
VDD
VDDCORE/VCAP
VSS
OR
2.5V
3.3V
PIC18LFXXJ11
VDD
VDDCORE/VCAP
VSS
25.3.2
ON-CHIP REGULATOR AND BOR
When the on-chip regulator is enabled, PIC18F46J11
family devices also have a simple brown-out capability.
If the voltage supplied to the regulator is inadequate to
maintain a minimum output level; the regulator Reset
circuitry will generate a Brown-out Reset (BOR). This
event is captured by the BOR flag bit (RCON<0>).
The operation of the BOR is described in more detail in
Section 4.4 “Brown-out Reset (BOR)” and
Section 4.4.1 “Detecting BOR”. The brown-out voltage
levels are specific in Section 28.1 “DC Characteristics:
Supply Voltage PIC18F46J11 Family (Industrial)”.
25.3.3
POWER-UP REQUIREMENTS
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, VDDCORE should not
exceed VDD by 0.3 volts.
25.3.4
OPERATION IN SLEEP MODE
When enabled, the on-chip regulator always consumes
a small incremental amount of current over IDD. This
includes when the device is in Sleep mode, even
though the core digital logic does not require much
power. To provide additional savings in applications
where power resources are critical, the regulator can
be configured to automatically enter a lower quiescent
draw standby mode whenever the device goes into
Sleep mode. This feature is controlled by the REGSLP
bit (WDTCON<7>, Register 25-11). If this bit is set
upon entry into Sleep mode, the regulator will transition
into a lower power state. In this state, the regulator still
provides a regulated output voltage necessary to
maintain SRAM state information, but consumes less
quiescent current.
Substantial Sleep mode power savings can be
obtained by setting the REGSLP bit, but device
wake-up time will increase in order to insure the
regulator has enough time to stabilize.
DS39932C-page 402
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
25.4
Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the
latency period, from oscillator start-up to code execution, by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
Configuration bit.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the internal oscillator block as the clock source, following the
time-out of the Power-up Timer after a Power-on Reset
is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
Two-Speed Start-up should be enabled only if the
primary oscillator mode is HS or HSPLL
(Crystal-Based) modes. Since the EC and ECPLL
modes do not require an Oscillator Start-up Timer
(OST) delay, Two-Speed Start-up should be disabled.
In all other power-managed modes, Two-Speed
Start-up is not used. The device will be clocked by the
currently selected clock source until the primary clock
source becomes available. The setting of the IESO bit
is ignored.
FIGURE 25-3:
TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL)
Q1
Q2
Q3
Q4
Q2 Q3 Q4 Q1 Q2 Q3
Q1
INTRC
OSC1
TOST(1)
TPLL(1)
1
PLL Clock
Output
2
n-1 n
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake from Interrupt Event
PC + 4
PC + 2
PC + 6
OSTS bit Set
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
25.4.1
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
While using the INTRC oscillator in Two-Speed
Start-up, the device still obeys the normal command
sequences for entering power-managed modes,
including serial SLEEP instructions (refer to
Section 3.1.4 “Multiple Sleep Commands”). In
practice, this means that user code can change the
SCS<1:0> bit settings or issue SLEEP instructions
before the OST times out. This would allow an application to briefly wake-up, perform routine “housekeeping”
tasks and return to Sleep before the device starts to
operate from the primary oscillator.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator block is providing the clock during
wake-up from Reset or Sleep mode.
© 2009 Microchip Technology Inc.
25.5
Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the
microcontroller to continue operation in the event of an
external oscillator failure by automatically switching the
device clock to the internal oscillator block. The FSCM
function is enabled by setting the FCMEN Configuration
bit.
When FSCM is enabled, the INTRC oscillator runs at
all times to monitor clocks to peripherals and provide a
backup clock in the event of a clock failure. Clock
monitoring (shown in Figure 25-4) is accomplished by
creating a sample clock signal, which is the INTRC output divided by 64. This allows ample time between
FSCM sample clocks for a peripheral clock edge to
occur. The peripheral device clock and the sample
clock are presented as inputs to the clock monitor latch.
The clock monitor is set on the falling edge of the
device clock source but cleared on the rising edge of
the sample clock.
DS39932C-page 403
PIC18F46J11 FAMILY
FIGURE 25-4:
FSCM BLOCK DIAGRAM
Clock Monitor
Latch
(edge-triggered)
Peripheral
Clock
INTRC
Source
(32 μs)
÷ 64
S
Q
C
Q
The FSCM will detect failures of the primary or secondary
clock sources only. If the internal oscillator block fails, no
failure would be detected, nor would any action be
possible.
488 Hz
(2.048 ms)
Clock
Failure
Detected
Clock failure is tested for on the falling edge of the
sample clock. If a sample clock falling edge occurs
while the clock monitor is still set, and a clock failure
has been detected (Figure 25-5), the following results:
• The FSCM generates an oscillator fail interrupt by
setting bit, OSCFIF (PIR2<7>);
• The device clock source is switched to the internal
oscillator block (OSCCON is not updated to show
the current clock source – this is the Fail-safe
condition); and
• The WDT is reset.
During switchover, the postscaler frequency from the
internal oscillator block may not be sufficiently stable
for timing-sensitive applications. In these cases, it may
FIGURE 25-5:
be desirable to select another clock configuration and
enter an alternate power-managed mode. This can be
done to attempt a partial recovery or execute a
controlled shutdown. See Section 3.1.4 “Multiple
Sleep Commands” and Section 25.4.1 “Special
Considerations for Using Two-Speed Start-up” for
more details.
25.5.1
FSCM AND THE WATCHDOG TIMER
Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with a
separate divider and counter, disabling the WDT has
no effect on the operation of the INTRC oscillator when
the FSCM is enabled.
As already noted, the clock source is switched to the
INTRC clock when a clock failure is detected; this may
mean a substantial change in the speed of code execution. If the WDT is enabled with a small prescale value,
a decrease in clock speed allows a WDT time-out to
occur and a subsequent device Reset. For this reason,
Fail-Safe Clock Monitor events also reset the WDT and
postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood
of an erroneous time-out.
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
Device
Clock
Output
Clock Monitor
Output (Q)
Failure
Detected
OSCFIF
Clock Monitor Test
Note:
Clock Monitor Test
Clock Monitor Test
The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
DS39932C-page 404
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
25.5.2
EXITING FAIL-SAFE OPERATION
The Fail-Safe Clock Monitor condition is terminated by
either a device Reset or by entering a power-managed
mode. On Reset, the controller starts the primary clock
source specified in Configuration Register 2H (with any
required start-up delays that are required for the oscillator mode, such as OST or PLL timer). The INTRC
oscillator provides the device clock until the primary
clock source becomes ready (similar to a Two-Speed
Start-up). The clock source is then switched to the
primary clock (indicated by the OSTS bit in the
OSCCON register becoming set). The FSCM then
resumes monitoring the peripheral clock.
The primary clock source may never become ready
during start-up. In this case, operation is clocked by the
INTRC oscillator. The OSCCON register will remain in
its Reset state until a power-managed mode is entered.
25.5.3
FSCM INTERRUPTS IN
POWER-MANAGED MODES
By entering a power-managed mode, the clock
multiplexer selects the clock source selected by the
OSCCON register. FSCM of the power-managed clock
source resumes in the power-managed mode.
If an oscillator failure occurs during power-managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1), code execution will be clocked
by the INTRC multiplexer. An automatic transition back
to the failed clock source will not occur.
If the interrupt is disabled, subsequent interrupts while
in Idle mode will cause the CPU to begin executing
instructions while being clocked by the INTRC source.
25.5.4
POR OR WAKE-UP FROM SLEEP
The FSCM is designed to detect oscillator failure at any
point after the device has exited Power-on Reset (POR)
or low-power Sleep mode. When the primary device
clock is either the EC or INTRC modes, monitoring can
begin immediately following these events.
For HS or HSPLL modes, the situation is somewhat
different. Since the oscillator may require a start-up
time considerably longer than the FSCM sample clock
time, a false clock failure may be detected. To prevent
this, the internal oscillator block is automatically configured as the device clock and functions until the primary
clock is stable (the OST and PLL timers have timed
© 2009 Microchip Technology Inc.
out). This is identical to Two-Speed Start-up mode.
Once the primary clock is stable, the INTRC returns to
its role as the FSCM source.
Note:
The same logic that prevents false
oscillator failure interrupts on POR, or
wake-up from Sleep, will also prevent the
detection of the oscillator’s failure to start
at all following these events. This can be
avoided by monitoring the OSTS bit and
using a timing routine to determine if the
oscillator is taking too long to start. Even
so, no oscillator failure interrupt will be
flagged.
As noted in Section 25.4.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible to
select another clock configuration and enter an alternate
power-managed mode while waiting for the primary
clock to become stable. When the new power-managed
mode is selected, the primary clock is disabled.
25.6
Program Verification and Code
Protection
For all devices in the PIC18F46J11 family of devices,
the on-chip program memory space is treated as a
single block. Code protection for this block is controlled
by one Configuration bit, CP0. This bit inhibits external
reads and writes to the program memory space. It has
no direct effect in normal execution mode.
25.6.1
CONFIGURATION REGISTER
PROTECTION
The Configuration registers are protected against
untoward changes or reads in two ways. The primary
protection is the write-once feature of the Configuration
bits, which prevents reconfiguration once the bit has
been programmed during a power cycle. To safeguard
against unpredictable events, Configuration bit
changes resulting from individual cell level disruptions
(such as ESD events) will cause a parity error and
trigger a device Reset. This is seen by the user as a
Configuration Mismatch (CM) Reset.
The data for the Configuration registers is derived from
the FCW in program memory. When the CP0 bit is set,
the source data for device configuration is also
protected as a consequence.
DS39932C-page 405
PIC18F46J11 FAMILY
25.7
In-Circuit Serial Programming
(ICSP)
PIC18F46J11 family microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
DS39932C-page 406
25.8
In-Circuit Debugger
When the DEBUG Configuration bit is programmed to
a ‘0’, the In-Circuit Debugger functionality is enabled.
This function allows simple debugging functions when
used with MPLAB® IDE. When the microcontroller has
this feature enabled, some resources are not available
for general use.
Table 25-4 lists the resources required by the
background debugger.
TABLE 25-4:
DEBUGGER RESOURCES
I/O pins:
RB6, RB7
Stack:
2 levels
Program Memory:
512 bytes
Data Memory:
10 bytes
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
26.0
INSTRUCTION SET SUMMARY
The PIC18F46J11 family of devices incorporates the
standard set of 75 PIC18 core instructions, and an
extended set of eight new instructions for the optimization of code that is recursive or that utilizes a software
stack. The extended set is discussed later in this
section.
26.1
Standard Instruction Set
The standard PIC18 instruction set adds many
enhancements to the previous PIC® MCU instruction
sets, while maintaining an easy migration from these
PIC MCU instruction sets. Most instructions are a
single program memory word (16 bits), but there are
four instructions that require two program memory
locations.
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
•
•
•
•
Byte-oriented operations
Bit-oriented operations
Literal operations
Control operations
The PIC18 instruction set summary in Table 26-2 lists
the byte-oriented, bit-oriented, literal and control
operations.
Table 26-1 provides the opcode field descriptions.
Most Byte-oriented instructions have three operands:
1.
2.
3.
The file register (specified by ‘f’)
The destination of the result (specified by ‘d’)
The accessed memory (specified by ‘a’)
The file register designator, ‘f’, specifies which file
register is to be used by the instruction. The destination
designator, ‘d’, specifies where the result of the
operation is to be placed. If ‘d’ is ‘0’, the result is placed
in the WREG register. If ‘d’ is ‘1’, the result is placed in
the file register specified in the instruction.
All Bit-oriented instructions have three operands:
1.
2.
3.
The file register (specified by ‘f’)
The bit in the file register (specified by ‘b’)
The accessed memory (specified by ‘a’)
The Literal instructions may use some of the following
operands:
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
• No operand required (specified by ‘—’)
The Control instructions may use some of the
following operands:
• A program memory address (specified by ‘n’)
• The mode of the CALL or RETURN instructions
(specified by ‘s’)
• The mode of the table read and table write
instructions (specified by ‘m’)
• No operand required (specified by ‘—’)
All instructions are a single word, except for four
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the 4 MSbs are ‘1’s. If
this second word is executed as an instruction (by
itself), it will execute as a NOP.
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
Program Counter (PC) is changed as a result of the
instruction. In these cases, the execution takes two
instruction cycles with the additional instruction
cycle(s) executed as a NOP.
The double-word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 μs. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 μs.
Two-word branch instructions (if true) would take 3 μs.
Figure 26-1 provides the general formats that the
instructions can have. All examples use the convention
‘nnh’ to represent a hexadecimal number.
The instruction set summary, provided in Table 26-2,
lists the standard instructions recognized by the
Microchip MPASMTM Assembler.
Section 26.1.1 “Standard Instruction Set” provides
a description of each instruction.
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register designator, ‘f’, represents the number of the file in which the
bit is located.
© 2009 Microchip Technology Inc.
DS39932C-page 407
PIC18F46J11 FAMILY
TABLE 26-1:
OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit:
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb
Bit address within an 8-bit file register (0 to 7)
BSR
Bank Select Register. Used to select the current RAM bank
C, DC, Z, OV, N
ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative
d
Destination select bit:
d = 0: store result in WREG
d = 1: store result in file register f
dest
Destination: either the WREG register or the specified register file location
f
8-bit register file address (00h to FFh), or 2-bit FSR designator (0h to 3h)
fs
12-bit register file address (000h to FFFh). This is the source address
fd
12-bit register file address (000h to FFFh). This is the destination address
GIE
Global Interrupt Enable bit
k
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value)
label
Label name
mm
The mode of the TBLPTR register for the table read and table write instructions
Used only with table read and table write instructions
*
No Change to register (such as TBLPTR with table reads and writes)
*+
Post-Increment register (such as TBLPTR with table reads and writes)
*-
Post-Decrement register (such as TBLPTR with table reads and writes)
+*
Pre-Increment register (such as TBLPTR with table reads and writes)
n
The relative address (2’s complement number) for relative branch instructions or the direct address for
Call/Branch and Return instructions
PC
Program Counter
PCL
Program Counter Low Byte
PCH
Program Counter High Byte
PCLATH
Program Counter High Byte Latch
PCLATU
Program Counter Upper Byte Latch
PD
Power-Down bit
PRODH
Product of Multiply High Byte
PRODL
Product of Multiply Low Byte
s
Fast Call/Return mode select bit:
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
TBLPTR
21-Bit Table Pointer (points to a program memory location)
TABLAT
8-Bit Table Latch
TO
Time-out bit
TOS
Top-of-Stack
u
Unused or Unchanged
WDT
Watchdog Timer
WREG
Working register (accumulator)
x
Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0; it is the recommended form of use for
compatibility with all Microchip software tools
zs
7-bit offset value for Indirect Addressing of register files (source)
7-bit offset value for Indirect Addressing of register files (destination)
zd
{
}
Optional argument
[text]
Indicates Indexed Addressing
(text)
The contents of text
[expr]<n>
Specifies bit n of the register indicated by the pointer, expr
→
Assigned to
< >
Register bit field
∈
In the set of
italics
User-defined term (font is Courier New)
DS39932C-page 408
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
EXAMPLE 26-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15
10
9
OPCODE
Example Instruction
8 7
d
0
a
ADDWF MYREG, W, B
f (FILE #)
d = 0 for result destination to be WREG register
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
OPCODE
15
0
f (Source FILE #)
12 11
MOVFF MYREG1, MYREG2
0
f (Destination FILE #)
1111
f = 12-bit file register address
Bit-oriented file register operations
15
12 11
9 8 7
0
OPCODE b (BIT #) a
BSF MYREG, bit, B
f (FILE #)
b = 3-bit position of bit in file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
Literal operations
15
8
7
0
OPCODE
MOVLW 7Fh
k (literal)
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15
8 7
0
OPCODE
15
n<7:0> (literal)
12 11
GOTO Label
0
n<19:8> (literal)
1111
n = 20-bit immediate value
15
8 7
OPCODE
15
S
0
CALL MYFUNC
n<7:0> (literal)
12 11
0
n<19:8> (literal)
1111
S = Fast bit
15
11 10
OPCODE
15
0
8 7
OPCODE
© 2009 Microchip Technology Inc.
BRA MYFUNC
n<10:0> (literal)
0
n<7:0> (literal)
BC MYFUNC
DS39932C-page 409
PIC18F46J11 FAMILY
TABLE 26-2:
PIC18F46J11 FAMILY INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
16-Bit Instruction Word
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
fs, fd
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
SUBWF
SUBWFB
f, d, a
f, d, a
SWAPF
TSTFSZ
XORWF
f, d, a
f, a
f, d, a
Note 1:
2:
3:
4:
Add WREG and f
Add WREG and Carry bit to f
AND WREG with f
Clear f
Complement f
Compare f with WREG, Skip =
Compare f with WREG, Skip >
Compare f with WREG, Skip <
Decrement f
Decrement f, Skip if 0
Decrement f, Skip if Not 0
Increment f
Increment f, Skip if 0
Increment f, Skip if Not 0
Inclusive OR WREG with f
Move f
1st word
Move fs (source) to
fd (destination) 2nd word
Move WREG to f
Multiply WREG with f
Negate f
Rotate Left f through Carry
Rotate Left f (No Carry)
Rotate Right f through Carry
Rotate Right f (No Carry)
Set f
Subtract f from WREG with
Borrow
Subtract WREG from f
Subtract WREG from f with
Borrow
Swap Nibbles in f
Test f, Skip if 0
Exclusive OR WREG with f
1
1
1
1
1
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1
2
C, DC, Z, OV, N
C, DC, Z, OV, N
Z, N
Z
Z, N
None
None
None
C, DC, Z, OV, N
None
None
C, DC, Z, OV, N
None
None
Z, N
Z, N
None
1, 2
1, 2
1,2
2
1, 2
4
4
1, 2
1, 2, 3, 4
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1, 2
1
1
1
1
1
1
1
1
1
1
0010
0010
0001
0110
0001
0110
0110
0110
0000
0010
0100
0010
0011
0100
0001
0101
1100
1111
0110
0000
0110
0011
0100
0011
0100
0110
0101
01da
00da
01da
101a
11da
001a
010a
000a
01da
11da
11da
10da
11da
10da
00da
00da
ffff
ffff
111a
001a
110a
01da
01da
00da
00da
100a
01da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
1
1
0101
0101
11da
10da
ffff
ffff
ffff C, DC, Z, OV, N
ffff C, DC, Z, OV, N
1, 2
1
1 (2 or 3)
1
0011
0110
0001
10da
011a
10da
ffff
ffff
ffff
ffff None
ffff None
ffff Z, N
4
1, 2
None
None
C, DC, Z, OV, N
C, Z, N
Z, N
C, Z, N
Z, N
None
C, DC, Z, OV, N
1, 2
1, 2
1, 2
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
DS39932C-page 410
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 26-2:
PIC18F46J11 FAMILY INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
Description
Cycles
16-Bit Instruction Word
MSb
LSb
Status
Affected
Notes
BIT-ORIENTED OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a
f, b, a
f, b, a
f, b, a
f, b, a
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f
1
1
1 (2 or 3)
1 (2 or 3)
1
1001
1000
1011
1010
0111
bbba
bbba
bbba
bbba
bbba
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
None
None
None
None
None
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
2
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
None
None
None
None
None
None
None
None
None
None
1
1
1
1
2
1
2
1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
2
2
1
0000
0000
0000
1100
0000
0000
kkkk
0001
0000
1, 2
1, 2
3, 4
3, 4
1, 2
CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
n
n
n
n
n
n
n
n
n
n, s
CLRWDT
DAW
GOTO
—
—
n
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
s
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call Subroutine
1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to Address
1st word
2nd word
No Operation
No Operation
Pop Top of Return Stack (TOS)
Push Top of Return Stack (TOS)
Relative Call
Software Device Reset
Return from Interrupt Enable
RETLW
RETURN
SLEEP
k
s
—
Return with Literal in WREG
Return from Subroutine
Go into Standby mode
Note 1:
2:
3:
4:
1
1
2
TO, PD
C
None
None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
kkkk None
001s None
0011 TO, PD
4
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
© 2009 Microchip Technology Inc.
DS39932C-page 411
PIC18F46J11 FAMILY
TABLE 26-2:
PIC18F46J11 FAMILY INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
Description
Cycles
16-Bit Instruction Word
MSb
LSb
Status
Affected
Notes
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
Add Literal and WREG
AND Literal with WREG
Inclusive OR Literal with WREG
Move Literal (12-bit) 2nd word
to FSR(f)
1st word
Move Literal to BSR<3:0>
Move Literal to WREG
Multiply Literal with WREG
Return with Literal in WREG
Subtract WREG from Literal
Exclusive OR Literal with WREG
1
1
1
2
1
1
1
2
1
1
0000
0000
0000
1110
1111
0000
0000
0000
0000
0000
0000
1111
1011
1001
1110
0000
0001
1110
1101
1100
1000
1010
kkkk
kkkk
kkkk
00ff
kkkk
0000
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z, OV, N
Z, N
Z, N
None
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
1001
1010
1011
1100
1101
1110
1111
None
None
None
None
None
None
None
None
None
None
None
None
C, DC, Z, OV, N
Z, N
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD*
TBLRD*+
TBLRD*TBLRD+*
TBLWT*
TBLWT*+
TBLWT*TBLWT+*
Note 1:
2:
3:
4:
Table Read
Table Read with Post-Increment
Table Read with Post-Decrement
Table Read with Pre-Increment
Table Write
Table Write with Post-Increment
Table Write with Post-Decrement
Table Write with Pre-Increment
2
2
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
DS39932C-page 412
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
26.1.1
STANDARD INSTRUCTION SET
ADDLW
ADD Literal to W
ADDWF
ADD W to f
Syntax:
ADDLW
Syntax:
ADDWF
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) + (f) → dest
Status Affected:
N, OV, C, DC, Z
k
Operands:
0 ≤ k ≤ 255
Operation:
(W) + k → W
Status Affected:
N, OV, C, DC, Z
Encoding:
0000
1111
kkkk
kkkk
Description:
The contents of W are added to the
8-bit literal ‘k’ and the result is placed in
W.
Words:
1
Cycles:
1
Encoding:
0010
Description:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
Example:
ADDLW
01da
ffff
ffff
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
15h
Before Instruction
W
= 10h
After Instruction
W =
25h
f {,d {,a}}
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWF
Before Instruction
W
=
REG
=
After Instruction
W
=
REG
=
Note:
REG, 0, 0
17h
0C2h
0D9h
0C2h
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
© 2009 Microchip Technology Inc.
DS39932C-page 413
PIC18F46J11 FAMILY
ADDWFC
ADD W and Carry bit to f
ANDLW
AND Literal with W
Syntax:
ADDWFC
Syntax:
ANDLW
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
f {,d {,a}}
Operation:
(W) + (f) + (C) → dest
Status Affected:
N,OV, C, DC, Z
Encoding:
0010
Description:
00da
ffff
Add W, the Carry flag and data memory
location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Operands:
0 ≤ k ≤ 255
Operation:
(W) .AND. k → W
Status Affected:
N, Z
Encoding:
ffff
k
0000
1011
kkkk
kkkk
Description:
The contents of W are ANDed with the
8-bit literal ‘k’. The result is placed in
W.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’
Process
Data
Write to
W
Example:
ANDLW
Before Instruction
W
=
After Instruction
W
=
05Fh
A3h
03h
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWFC
Before Instruction
Carry bit =
REG
=
W
=
After Instruction
Carry bit =
REG
=
W
=
DS39932C-page 414
REG, 0, 1
1
02h
4Dh
0
02h
50h
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
ANDWF
AND W with f
BC
Branch if Carry
Syntax:
ANDWF
Syntax:
BC
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
f {,d {,a}}
Operation:
(W) .AND. (f) → dest
Status Affected:
N, Z
Encoding:
0001
Description:
Operands:
-128 ≤ n ≤ 127
Operation:
if Carry bit is ‘1’,
(PC) + 2 + 2n → PC
Status Affected:
None
Encoding:
01da
ffff
ffff
1110
Description:
The contents of W are ANDed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ANDWF
Before Instruction
W
=
REG
=
After Instruction
W
=
REG
=
REG, 0, 0
17h
C2h
02h
C2h
© 2009 Microchip Technology Inc.
0010
nnnn
nnnn
If the Carry bit is ’1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
n
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
Before Instruction
PC
After Instruction
If Carry
PC
If Carry
PC
BC
5
=
address (HERE)
=
=
=
=
1;
address (HERE + 12)
0;
address (HERE + 2)
DS39932C-page 415
PIC18F46J11 FAMILY
BCF
Bit Clear f
BN
Branch if Negative
Syntax:
BCF
Syntax:
BN
Operands:
0 ≤ f ≤ 255
0≤b≤7
a ∈ [0,1]
f, b {,a}
Operation:
0 → f<b>
Status Affected:
None
Encoding:
1001
Description:
Operands:
-128 ≤ n ≤ 127
Operation:
if Negative bit is ‘1’,
(PC) + 2 + 2n → PC
Status Affected:
None
Encoding:
bbba
ffff
ffff
1110
Description:
Bit ‘b’ in register ‘f’ is cleared.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
BCF
Before Instruction
FLAG_REG = C7h
After Instruction
FLAG_REG = 47h
DS39932C-page 416
FLAG_REG,
7, 0
0110
nnnn
nnnn
If the Negative bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
Q Cycle Activity:
Decode
n
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
Before Instruction
PC
After Instruction
If Negative
PC
If Negative
PC
BN
Jump
=
address (HERE)
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
BNC
Branch if Not Carry
BNN
Branch if Not Negative
Syntax:
BNC
Syntax:
BNN
n
n
Operands:
-128 ≤ n ≤ 127
Operands:
-128 ≤ n ≤ 127
Operation:
if Carry bit is ‘0’,
(PC) + 2 + 2n → PC
Operation:
if Negative bit is ‘0’,
(PC) + 2 + 2n → PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
Description:
0011
nnnn
nnnn
If the Carry bit is ‘0’, then the program
will branch.
Encoding:
1110
Description:
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
nnnn
nnnn
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
1
Words:
1
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
0111
If the Negative bit is ‘0’, then the
program will branch.
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
If No Jump:
Example:
If No Jump:
HERE
Before Instruction
PC
After Instruction
If Carry
PC
If Carry
PC
BNC
Jump
=
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
© 2009 Microchip Technology Inc.
Example:
HERE
Before Instruction
PC
After Instruction
If Negative
PC
If Negative
PC
BNN
Jump
=
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
DS39932C-page 417
PIC18F46J11 FAMILY
BNOV
Branch if Not Overflow
BNZ
Branch if Not Zero
Syntax:
BNOV
Syntax:
BNZ
n
n
Operands:
-128 ≤ n ≤ 127
Operands:
-128 ≤ n ≤ 127
Operation:
if Overflow bit is ‘0’,
(PC) + 2 + 2n → PC
Operation:
if Zero bit is ‘0’,
(PC) + 2 + 2n → PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
Description:
0101
nnnn
nnnn
If the Overflow bit is ‘0’, then the
program will branch.
Encoding:
1110
Description:
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
nnnn
nnnn
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
1
Words:
1
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
0001
If the Zero bit is ‘0’, then the program
will branch.
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
If No Jump:
If No Jump:
Example:
HERE
Before Instruction
PC
After Instruction
If Overflow
PC
If Overflow
PC
DS39932C-page 418
BNOV Jump
=
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
Example:
HERE
Before Instruction
PC
After Instruction
If Zero
PC
If Zero
PC
BNZ
Jump
=
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
BRA
Unconditional Branch
BSF
Bit Set f
Syntax:
BRA
Syntax:
BSF
Operands:
-1024 ≤ n ≤ 1023
Operands:
Operation:
(PC) + 2 + 2n → PC
Status Affected:
None
0 ≤ f ≤ 255
0≤b≤7
a ∈ [0,1]
Operation:
1 → f<b>
Status Affected:
None
Encoding:
n
1101
Description:
0nnn
nnnn
nnnn
Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Words:
1
Cycles:
2
Encoding:
1000
Description:
Q1
Q2
Q3
Q4
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
Example:
HERE
Before Instruction
PC
After Instruction
PC
BRA
Jump
=
address (HERE)
=
address (Jump)
ffff
ffff
Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
BSF
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
© 2009 Microchip Technology Inc.
bbba
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Q Cycle Activity:
Decode
f, b {,a}
FLAG_REG, 7, 1
=
0Ah
=
8Ah
DS39932C-page 419
PIC18F46J11 FAMILY
BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
BTFSC f, b {,a}
Syntax:
BTFSS f, b {,a}
Operands:
0 ≤ f ≤ 255
0≤b≤7
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
0≤b<7
a ∈ [0,1]
Operation:
skip if (f<b>) = 0
Operation:
skip if (f<b>) = 1
Status Affected:
None
Status Affected:
None
Encoding:
1011
Description:
bbba
ffff
ffff
If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped. If bit ‘b’ is ‘0’,
then the next instruction fetched during
the current instruction execution is discarded and a NOP is executed instead,
making this a two-cycle instruction.
Encoding:
1010
Description:
bbba
ffff
ffff
If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘1’,
then the next instruction fetched during
the current instruction execution is discarded and a NOP is executed instead,
making this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Words:
1
Cycles:
1(2)
Note:
Cycles:
1(2)
Note:
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
Decode
Read
register ‘f’
Process
Data
No
operation
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
If skip:
If skip:
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
FALSE
TRUE
Before Instruction
PC
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
DS39932C-page 420
BTFSC
:
:
FLAG, 1, 0
=
address (HERE)
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
Example:
HERE
FALSE
TRUE
Before Instruction
PC
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
BTFSS
:
:
FLAG, 1, 0
=
address (HERE)
=
=
=
=
0;
address (FALSE)
1;
address (TRUE)
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
BTG f, b {,a}
Syntax:
BOV
Operands:
0 ≤ f ≤ 255
0≤b<7
a ∈ [0,1]
Operands:
-128 ≤ n ≤ 127
Operation:
if Overflow bit is ‘1’,
(PC) + 2 + 2n → PC
Status Affected:
None
Operation:
(f<b>) → f<b>
Status Affected:
None
Encoding:
0111
Description:
Encoding:
bbba
ffff
ffff
1110
Description:
Bit ‘b’ in data memory location ‘f’ is
inverted.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
BTG
PORTC,
© 2009 Microchip Technology Inc.
Words:
1
Cycles:
nnnn
nnnn
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
4, 0
Before Instruction:
PORTC =
0111 0101 [75h]
After Instruction:
PORTC =
0110 0101 [65h]
0100
If the Overflow bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
n
Example:
HERE
Before Instruction
PC
After Instruction
If Overflow
PC
If Overflow
PC
BOV
Jump
=
address (HERE)
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
DS39932C-page 421
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BZ
Branch if Zero
CALL
Subroutine Call
Syntax:
BZ
Syntax:
CALL k {,s}
n
Operands:
-128 ≤ n ≤ 127
Operands:
Operation:
if Zero bit is ‘1’,
(PC) + 2 + 2n → PC
0 ≤ k ≤ 1048575
s ∈ [0,1]
Operation:
Status Affected:
None
(PC) + 4 → TOS,
k → PC<20:1>;
if s = 1,
(W) → WS,
(STATUS) → STATUSS,
(BSR) → BSRS
Status Affected:
None
Encoding:
1110
Description:
0000
nnnn
nnnn
If the Zero bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
1
Cycles:
1(2)
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Q1
Q2
Q3
Q4
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
If No Jump:
Example:
HERE
Before Instruction
PC
After Instruction
If Zero
PC
If Zero
PC
DS39932C-page 422
BZ
Jump
=
address (HERE)
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
k7kkk
kkkk
110s
k19kkk
kkkk0
kkkk8
Description:
Subroutine call of entire 2-Mbyte
memory range. First, return address
(PC + 4) is pushed onto the return
stack. If ‘s’ = 1, the W, STATUS and
BSR
registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0, no
update occurs (default). Then, the
20-bit value ‘k’ is loaded into
PC<20:1>. CALL is a two-cycle
instruction.
Words:
2
Cycles:
2
Q Cycle Activity:
If Jump:
Decode
1110
1111
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’<7:0>,
Push PC to
stack
Read literal
’k’<19:8>,
Write to PC
No
operation
No
operation
No
operation
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
PC
=
TOS
=
WS
=
BSRS
=
STATUSS =
CALL
THERE,1
address (HERE)
address (THERE)
address (HERE + 4)
W
BSR
STATUS
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
CLRF
Clear f
Syntax:
CLRF
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
f {,a}
Operation:
000h → f,
1→Z
Status Affected:
Z
Encoding:
0110
Description:
101a
ffff
ffff
Clears the contents of the specified
register.
CLRWDT
Clear Watchdog Timer
Syntax:
CLRWDT
Operands:
None
Operation:
000h → WDT,
000h → WDT postscaler,
1 → TO,
1 → PD
Status Affected:
TO, PD
Encoding:
0000
Words:
1
Cycles:
1
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
CLRF
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
FLAG_REG,1
=
5Ah
=
00h
© 2009 Microchip Technology Inc.
0100
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
No
operation
Example:
Q Cycle Activity:
0000
CLRWDT instruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits, TO
and PD, are set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
0000
Description:
CLRWDT
Before Instruction
WDT Counter
After Instruction
WDT Counter
WDT Postscaler
TO
PD
=
?
=
=
=
=
00h
0
1
1
DS39932C-page 423
PIC18F46J11 FAMILY
COMF
Complement f
CPFSEQ
Compare f with W, Skip if f = W
Syntax:
COMF
Syntax:
CPFSEQ
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) – (W),
skip if (f) = (W)
(unsigned comparison)
Status Affected:
None
f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
f → dest
Status Affected:
N, Z
Encoding:
0001
Description:
11da
ffff
ffff
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
Encoding:
Description:
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Read
register ‘f’
Example:
COMF
Before Instruction
REG
=
After Instruction
REG
=
W
=
13h
13h
ECh
Q3
Process
Data
REG, 0, 0
ffff
ffff
Compares the contents of data memory location ‘f’ to the contents of W by
performing an unsigned subtraction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q4
Words:
1
Write to
destination
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Decode
Q2
Read
register ‘f’
Q3
Process
Data
Q4
No
operation
If skip:
Q1
Q2
Q3
No
No
No
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
No
No
operation
operation
operation
No
No
No
operation
operation
operation
Example:
HERE
NEQUAL
EQUAL
Before Instruction
PC Address
W
REG
After Instruction
If REG
PC
If REG
PC
DS39932C-page 424
001a
If ‘f’ = W, then the fetched instruction is
discarded and a NOP is executed
instead, making this a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words:
0110
f {,a}
Q4
No
operation
Q4
No
operation
No
operation
CPFSEQ REG, 0
:
:
=
=
=
HERE
?
?
=
=
≠
=
W;
Address (EQUAL)
W;
Address (NEQUAL)
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
CPFSGT
Compare f with W, Skip if f > W
CPFSLT
Compare f with W, Skip if f < W
Syntax:
CPFSGT
Syntax:
CPFSLT
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) – (W),
skip if (f) > (W)
(unsigned comparison)
Operation:
(f) – (W),
skip if (f) < (W)
(unsigned comparison)
Status Affected:
None
Status Affected:
None
Encoding:
Description:
0110
f {,a}
010a
ffff
ffff
Compares the contents of data memory location ‘f’ to the contents of the W
by performing an unsigned subtraction.
Encoding:
0110
Description:
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
Words:
1
Cycles:
1(2)
Note:
Q Cycle Activity:
Q1
Decode
3 cycles if skip and followed
by a 2-word instruction.
Q2
Read
register ‘f’
Q3
Process
Data
Q4
No
operation
Q1
Q2
Q3
No
No
No
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
No
No
operation
operation
operation
No
No
No
operation
operation
operation
Q4
No
operation
Example:
HERE
NGREATER
GREATER
Before Instruction
PC
W
After Instruction
If REG
PC
If REG
PC
CPFSGT REG, 0
:
:
=
=
Address (HERE)
?
>
=
≤
=
W;
Address (GREATER)
W;
Address (NGREATER)
© 2009 Microchip Technology Inc.
ffff
ffff
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
If skip:
Q4
No
operation
No
operation
000a
Compares the contents of data memory location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
f {,a}
Example:
HERE
NLESS
LESS
Before Instruction
PC
W
After Instruction
If REG
PC
If REG
PC
CPFSLT REG, 1
:
:
=
=
Address (HERE)
?
<
=
≥
=
W;
Address (LESS)
W;
Address (NLESS)
DS39932C-page 425
PIC18F46J11 FAMILY
DAW
Decimal Adjust W Register
DECF
Decrement f
Syntax:
DAW
Syntax:
DECF f {,d {,a}}
Operands:
None
Operands:
Operation:
If [W<3:0> > 9] or [DC = 1] then,
(W<3:0>) + 6 → W<3:0>;
else,
(W<3:0>) → W<3:0>
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest
Status Affected:
C, DC, N, OV, Z
Encoding:
If [W<7:4> > 9] or [C = 1] then,
(W<7:4>) + 6 → W<7:4>,
C = 1;
else,
(W<7:4>) → W<7:4>
Status Affected:
0000
Description:
C
Encoding:
0000
0000
0000
DAW adjusts the eight-bit value in W,
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register W
Process
Data
Write
W
Example 1:
DAW
Before Instruction
W
=
C
=
DC
=
After Instruction
W
=
C
=
DC
=
A5h
0
0
05h
1
0
Example 2:
Before Instruction
W
=
C
=
DC
=
After Instruction
W
=
C
=
DC
=
DS39932C-page 426
ffff
ffff
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
0111
Description:
01da
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
DECF
Before Instruction
CNT
=
Z
=
After Instruction
CNT
=
Z
=
CNT,
1, 0
01h
0
00h
1
CEh
0
0
34h
1
0
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
DECFSZ
Decrement f, Skip if 0
DCFSNZ
Decrement f, Skip if not 0
Syntax:
DECFSZ f {,d {,a}}
Syntax:
DCFSNZ
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest,
skip if result = 0
Operation:
(f) – 1 → dest,
skip if result ≠ 0
Status Affected:
None
Status Affected:
None
Encoding:
0010
Description:
11da
ffff
ffff
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Encoding:
0100
Description:
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Words:
1
Cycles:
1(2)
Note:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
DECFSZ
GOTO
CNT, 1, 1
LOOP
Example:
HERE
CONTINUE
Before Instruction
PC
=
After Instruction
CNT
=
If CNT
=
PC =
If CNT
≠
PC =
Address (HERE)
CNT – 1
0;
Address (CONTINUE)
0;
Address (HERE + 2)
© 2009 Microchip Technology Inc.
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
If skip and followed by 2-word instruction:
ffff
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Decode
ffff
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
11da
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words:
f {,d {,a}}
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
ZERO
NZERO
Before Instruction
TEMP
After Instruction
TEMP
If TEMP
PC
If TEMP
PC
DCFSNZ
:
:
TEMP, 1, 0
=
?
=
=
=
≠
=
TEMP – 1,
0;
Address (ZERO)
0;
Address (NZERO)
DS39932C-page 427
PIC18F46J11 FAMILY
GOTO
Unconditional Branch
INCF
Increment f
Syntax:
GOTO k
Syntax:
INCF
Operands:
0 ≤ k ≤ 1048575
Operands:
Operation:
k → PC<20:1>
Status Affected:
None
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest
Status Affected:
C, DC, N, OV, Z
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
1111
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Description:
GOTO allows an unconditional branch
anywhere within entire 2-Mbyte memory range. The 20-bit value ‘k’ is loaded
into PC<20:1>. GOTO is always a
two-cycle instruction.
Words:
2
Cycles:
2
Encoding:
0010
Description:
Q1
Q2
Q3
Q4
Read literal
‘k’<7:0>,
No
operation
Read literal
‘k’<19:8>,
Write to PC
No
operation
No
operation
No
operation
No
operation
Example:
GOTO THERE
After Instruction
PC =
Address (THERE)
ffff
ffff
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
INCF
Before Instruction
CNT
=
Z
=
C
=
DC
=
After Instruction
CNT
=
Z
=
C
=
DC
=
DS39932C-page 428
10da
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Q Cycle Activity:
Decode
f {,d {,a}}
CNT, 1, 0
FFh
0
?
?
00h
1
1
1
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
INCFSZ
Increment f, Skip if 0
INFSNZ
Syntax:
INCFSZ
Syntax:
INFSNZ
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
f {,d {,a}}
Increment f, Skip if not 0
f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
(f) + 1 → dest,
skip if result = 0
Operation:
(f) + 1 → dest,
skip if result ≠ 0
Status Affected:
None
Status Affected:
None
Encoding:
0011
Description:
11da
ffff
ffff
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’. (default)
Encoding:
0100
Description:
10da
ffff
ffff
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Words:
1
Cycles:
1(2)
Note:
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
If skip:
If skip:
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NZERO
ZERO
Before Instruction
PC
=
After Instruction
CNT
=
If CNT
=
PC
=
If CNT
≠
PC
=
INCFSZ
:
:
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
© 2009 Microchip Technology Inc.
CNT, 1, 0
Example:
HERE
ZERO
NZERO
Before Instruction
PC
=
After Instruction
REG
=
If REG
≠
PC
=
If REG
=
PC
=
INFSNZ
REG, 1, 0
Address (HERE)
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
DS39932C-page 429
PIC18F46J11 FAMILY
IORLW
Inclusive OR Literal with W
IORWF
Inclusive OR W with f
Syntax:
IORLW k
Syntax:
IORWF
Operands:
0 ≤ k ≤ 255
Operands:
Operation:
(W) .OR. k → W
Status Affected:
N, Z
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .OR. (f) → dest
Status Affected:
N, Z
Encoding:
0000
1001
kkkk
kkkk
Description:
The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed
in W.
Words:
1
Cycles:
1
Encoding:
0001
Description:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
Example:
IORLW
Before Instruction
W
=
After Instruction
W
=
00da
ffff
ffff
Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
35h
9Ah
BFh
f {,d {,a}}
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
IORWF
Before Instruction
RESULT =
W
=
After Instruction
RESULT =
W
=
DS39932C-page 430
RESULT, 0, 1
13h
91h
13h
93h
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
LFSR
Load FSR
MOVF
Move f
Syntax:
LFSR f, k
Syntax:
MOVF
Operands:
0≤f≤2
0 ≤ k ≤ 4095
Operands:
Operation:
k → FSRf
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Status Affected:
None
Operation:
f → dest
Status Affected:
N, Z
Encoding:
1110
1111
1110
0000
00ff
k7kkk
k11kkk
kkkk
Description:
The 12-bit literal ‘k’ is loaded into the
file select register pointed to by ‘f’.
Words:
2
Cycles:
2
Encoding:
0101
Description:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’ MSB
Process
Data
Write
literal ‘k’
MSB to
FSRfH
Decode
Read literal
‘k’ LSB
Process
Data
Write literal
‘k’ to FSRfL
Example:
After Instruction
FSR2H
FSR2L
03h
ABh
00da
ffff
ffff
The contents of register ‘f’ are moved
to a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
LFSR 2, 3ABh
=
=
f {,d {,a}}
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
W
Example:
MOVF
Before Instruction
REG
W
After Instruction
REG
W
© 2009 Microchip Technology Inc.
REG, 0, 0
=
=
22h
FFh
=
=
22h
22h
DS39932C-page 431
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MOVFF
Move f to f
MOVLB
Move Literal to Low Nibble in BSR
Syntax:
MOVFF fs,fd
Syntax:
MOVLW k
Operands:
0 ≤ fs ≤ 4095
0 ≤ fd ≤ 4095
Operands:
0 ≤ k ≤ 255
Operation:
k → BSR
Status Affected:
None
Operation:
(fs) → fd
Status Affected:
None
Encoding:
1st word (source)
2nd word (destin.)
Encoding:
1100
1111
Description:
ffff
ffff
ffff
ffff
ffffs
ffffd
The contents of source register ‘fs’ are
moved to destination register ‘fd’.
Location of source ‘fs’ can be anywhere
in the 4096-byte data space (000h to
FFFh) and location of destination ‘fd’
can also be anywhere from 000h to
FFFh.
Either source or destination can be W
(a useful special situation).
MOVFF is particularly useful for
transferring a data memory location to
a peripheral register (such as the
transmit buffer or an I/O port).
The MOVFF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register
Words:
2
Cycles:
2
0000
0001
kkkk
kkkk
Description:
The eight-bit literal ‘k’ is loaded into the
Bank Select Register (BSR). The value
of BSR<7:4> always remains ‘0’
regardless of the value of k7:k4.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write literal
‘k’ to BSR
MOVLB
5
Example:
Before Instruction
BSR Register =
After Instruction
BSR Register =
02h
05h
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
No dummy
read
Example:
MOVFF
Before Instruction
REG1
REG2
After Instruction
REG1
REG2
DS39932C-page 432
REG1, REG2
=
=
33h
11h
=
=
33h
33h
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
MOVLW
Move Literal to W
MOVWF
Move W to f
Syntax:
MOVLW k
Syntax:
MOVWF
Operands:
0 ≤ k ≤ 255
Operands:
Operation:
k→W
0 ≤ f ≤ 255
a ∈ [0,1]
Status Affected:
None
Encoding:
0000
Description:
1110
kkkk
kkkk
The eight-bit literal ‘k’ is loaded into W.
Words:
1
Cycles:
1
Operation:
(W) → f
Status Affected:
None
Encoding:
0110
Description:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
Example:
After Instruction
W
=
MOVLW
f {,a}
111a
ffff
ffff
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
5Ah
5Ah
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
MOVWF
Before Instruction
W
=
REG
=
After Instruction
W
=
REG
=
© 2009 Microchip Technology Inc.
REG, 0
4Fh
FFh
4Fh
4Fh
DS39932C-page 433
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MULLW
Multiply Literal with W
MULWF
Multiply W with f
Syntax:
MULLW
Syntax:
MULWF
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(W) x (f) → PRODH:PRODL
Status Affected:
None
k
Operands:
0 ≤ k ≤ 255
Operation:
(W) x k → PRODH:PRODL
Status Affected:
None
Encoding:
0000
Description:
1101
kkkk
kkkk
An unsigned multiplication is carried
out between the contents of W and the
8-bit literal ‘k’. The 16-bit result is
placed in PRODH:PRODL register pair.
PRODH contains the high byte.
Encoding:
0000
Description:
W is unchanged.
None of the Status flags are affected.
1
Cycles:
1
Q1
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write
registers
PRODH:
PRODL
MULLW
=
=
=
=
=
=
0C4h
E2h
?
?
E2h
ADh
08h
If ‘a’ is ‘0’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
registers
PRODH:
PRODL
Example:
Before Instruction
W
REG
PRODH
PRODL
After Instruction
W
REG
PRODH
PRODL
DS39932C-page 434
ffff
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Decode
Before Instruction
W
PRODH
PRODL
After Instruction
W
PRODH
PRODL
ffff
Note that neither Overflow nor Carry is
possible in this operation. A Zero result is
possible but not detected.
Q Cycle Activity:
Example:
001a
An unsigned multiplication is carried out
between the contents of W and the
register file location ‘f’. The 16-bit result is
stored in the PRODH:PRODL register
pair. PRODH contains the high byte. Both
W and ‘f’ are unchanged.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result
is possible but not detected.
Words:
f {,a}
MULWF
REG, 1
=
=
=
=
C4h
B5h
?
?
=
=
=
=
C4h
B5h
8Ah
94h
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
NEGF
Negate f
Syntax:
NEGF
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
f {,a}
Operation:
(f) + 1 → f
Status Affected:
N, OV, C, DC, Z
Encoding:
0110
Description:
110a
ffff
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
Syntax:
NOP
Operands:
None
Operation:
No operation
Status Affected:
None
0000
1111
ffff
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Cycles:
No Operation
Encoding:
Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’.
Words:
NOP
0000
xxxx
Description:
No operation.
Words:
1
Cycles:
1
0000
xxxx
0000
xxxx
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
Example:
None.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
NEGF
Before Instruction
REG
=
After Instruction
REG
=
REG, 1
0011 1010 [3Ah]
1100 0110 [C6h]
© 2009 Microchip Technology Inc.
DS39932C-page 435
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POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
Syntax:
POP
Syntax:
PUSH
Operands:
None
Operands:
None
Operation:
(TOS) → bit bucket
Operation:
(PC + 2) → TOS
Status Affected:
None
Status Affected:
None
Encoding:
0000
0000
0000
0110
Encoding:
0000
0000
0000
0101
Description:
The TOS value is pulled off the return
stack and is discarded. The TOS value
then becomes the previous value that
was pushed onto the return stack.
This instruction is provided to enable
the user to properly manage the return
stack to incorporate a software stack.
Description:
The PC + 2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implementing a
software stack by modifying TOS and
then pushing it onto the return stack.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Q Cycle Activity:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
POP TOS
value
No
operation
POP
GOTO
NEW
Example:
Q2
Q3
Q4
PUSH
PC + 2 onto
return stack
No
operation
No
operation
Example:
Before Instruction
TOS
Stack (1 level down)
=
=
0031A2h
014332h
After Instruction
TOS
PC
=
=
014332h
NEW
DS39932C-page 436
Q1
Decode
PUSH
Before Instruction
TOS
PC
=
=
345Ah
0124h
After Instruction
PC
TOS
Stack (1 level down)
=
=
=
0126h
0126h
345Ah
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
RCALL
Relative Call
RESET
Reset
Syntax:
RCALL
Syntax:
RESET
n
Operands:
-1024 ≤ n ≤ 1023
Operands:
None
Operation:
(PC) + 2 → TOS,
(PC) + 2 + 2n → PC
Operation:
Reset all registers and flags that are
affected by a MCLR Reset.
Status Affected:
None
Status Affected:
All
Encoding:
1101
Description:
1nnn
nnnn
nnnn
Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto the
stack. Then, add the 2’s complement
number ‘2n’ to the PC. Since the PC
will have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Words:
1
Cycles:
2
Encoding:
0000
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
1111
1111
This instruction provides a way to
execute a MCLR Reset in software.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
reset
No
operation
No
operation
Example:
Q Cycle Activity:
0000
Description:
After Instruction
Registers =
Flags*
=
RESET
Reset Value
Reset Value
PUSH PC
to stack
No
operation
Example:
No
operation
HERE
RCALL Jump
Before Instruction
PC =
Address (HERE)
After Instruction
PC =
Address (Jump)
TOS =
Address (HERE + 2)
© 2009 Microchip Technology Inc.
DS39932C-page 437
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RETFIE
Return from Interrupt
RETLW
Return Literal to W
Syntax:
RETFIE {s}
Syntax:
RETLW k
Operands:
s ∈ [0,1]
Operands:
0 ≤ k ≤ 255
Operation:
(TOS) → PC,
1 → GIE/GIEH or PEIE/GIEL;
if s = 1,
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
Operation:
k → W,
(TOS) → PC,
PCLATU, PCLATH are unchanged
Status Affected:
None
Status Affected:
0000
0000
Description:
0000
0001
Words:
1
Cycles:
2
Q Cycle Activity:
kkkk
kkkk
W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from
the top of the stack (the return
address). The high address latch
(PCLATH) remains unchanged.
Words:
1
Cycles:
2
000s
Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low-priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers WS,
STATUSS and BSRS are loaded into
their corresponding registers W,
STATUS and BSR. If ‘s’ = 0, no update
of these registers occurs (default).
1100
Description:
GIE/GIEH, PEIE/GIEL.
Encoding:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
POP PC
from stack,
write to W
No
operation
No
operation
No
operation
No
operation
Example:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
POP PC
from stack
Set GIEH or
GIEL
No
operation
Encoding:
No
operation
Example:
RETFIE
After Interrupt
PC
W
BSR
STATUS
GIE/GIEH, PEIE/GIEL
DS39932C-page 438
No
operation
No
operation
1
=
=
=
=
=
TOS
WS
BSRS
STATUSS
1
CALL TABLE ;
;
;
;
:
TABLE
ADDWF PCL ;
RETLW k0
;
RETLW k1
;
:
:
RETLW kn
;
Before Instruction
W
=
After Instruction
W
=
W contains table
offset value
W now has
table value
W = offset
Begin table
End of table
07h
value of kn
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
RETURN {s}
Syntax:
RLCF
Operands:
s ∈ [0,1]
Operands:
Operation:
(TOS) → PC;
if s = 1,
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<n>) → dest<n + 1>,
(f<7>) → C,
(C) → dest<0>
Status Affected:
C, N, Z
Status Affected:
None
Encoding:
0000
Description:
Encoding:
0000
0001
001s
0011
Description:
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’= 1, the contents of the shadow
registers WS, STATUSS and BSRS are
loaded into their corresponding
registers W, STATUS and BSR. If
‘s’ = 0, no update of these registers
occurs (default).
Words:
1
Cycles:
2
Q1
Q2
Q3
Q4
No
operation
Process
Data
POP PC
from stack
No
operation
No
operation
No
operation
No
operation
01da
ffff
ffff
The contents of register ‘f’ are rotated
one bit to the left through the Carry flag.
If ‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in register
‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Decode
f {,d {,a}}
register f
C
Words:
1
Cycles:
1
Q Cycle Activity:
Example:
RETURN
After Instruction:
PC = TOS
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
Before Instruction
REG
=
C
=
After Instruction
REG
=
W
=
C
=
© 2009 Microchip Technology Inc.
RLCF
REG, 0, 0
1110 0110
0
1110 0110
1100 1100
1
DS39932C-page 439
PIC18F46J11 FAMILY
RLNCF
Rotate Left f (No Carry)
RRCF
Rotate Right f through Carry
Syntax:
RLNCF
Syntax:
RRCF
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<n>) → dest<n + 1>,
(f<7>) → dest<0>
Operation:
Status Affected:
N, Z
(f<n>) → dest<n – 1>,
(f<0>) → C,
(C) → dest<7>
Status Affected:
C, N, Z
Encoding:
0100
Description:
f {,d {,a}}
01da
ffff
ffff
The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
Encoding:
0011
Description:
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used to
select the GPR bank (default).
Cycles:
1
Q1
Decode
Q2
Read
register ‘f’
Example:
RLNCF
Before Instruction
REG
=
After Instruction
REG
=
DS39932C-page 440
Q3
Process
Data
Q4
Write to
destination
Words:
1
Cycles:
register f
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
REG, 1, 0
1010 1011
0101 0111
ffff
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
W. If ‘d’ is ‘1’, the result is placed back
in register ‘f’ (default).
C
Q Cycle Activity:
ffff
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
register f
1
00da
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
f {,d {,a}}
Example:
RRCF
Before Instruction
REG
=
C
=
After Instruction
REG
=
W
=
C
=
REG, 0, 0
1110 0110
0
1110 0110
0111 0011
0
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
RRNCF
Rotate Right f (No Carry)
SETF
Set f
Syntax:
RRNCF
Syntax:
SETF
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f<n>) → dest<n – 1>,
(f<0>) → dest<7>
Status Affected:
N, Z
Encoding:
0100
Description:
f {,d {,a}}
00da
Operation:
FFh → f
Status Affected:
None
Encoding:
ffff
ffff
0110
Description:
The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
register f
Words:
1
Cycles:
1
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
RRNCF
Before Instruction
REG
=
After Instruction
REG
=
Example 2:
ffff
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
SETF
Before Instruction
REG
After Instruction
REG
REG,1
=
5Ah
=
FFh
REG, 1, 0
1101 0111
1110 1011
RRNCF
Before Instruction
W
=
REG
=
After Instruction
W
=
REG
=
ffff
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
Q Cycle Activity:
100a
The contents of the specified register
are set to FFh.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If
‘a’ is ‘1’, then the bank will be selected
as per the BSR value (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
f {,a}
REG, 0, 0
?
1101 0111
1110 1011
1101 0111
© 2009 Microchip Technology Inc.
DS39932C-page 441
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SLEEP
Enter Sleep Mode
SUBFWB
Subtract f from W with Borrow
Syntax:
SLEEP
Syntax:
SUBFWB
Operands:
None
Operands:
Operation:
00h → WDT,
0 → WDT postscaler,
1 → TO,
0 → PD
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) – (f) – (C) → dest
Status Affected:
N, OV, C, DC, Z
Status Affected:
TO, PD
Encoding:
0000
Encoding:
0000
0000
0011
0101
Description:
The Power-Down status bit (PD) is
cleared. The Time-out status bit (TO)
is set. The Watchdog Timer and its
postscaler are cleared.
Description:
1
Cycles:
1
Q1
Q2
Q3
Q4
No
operation
Process
Data
Go to
Sleep
Example:
SLEEP
Before Instruction
TO =
?
?
PD =
After Instruction
1†
TO =
0
PD =
† If WDT causes wake-up, this bit is cleared.
DS39932C-page 442
ffff
ffff
Subtract register ‘f’ and Carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is stored in
W. If ‘d’ is ‘1’, the result is stored in
register ‘f’ (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Decode
01da
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
The processor is put into Sleep mode
with the oscillator stopped.
Words:
f {,d {,a}}
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
SUBFWB
REG, 1, 0
Before Instruction
REG
=
3
W
=
2
C
=
1
After Instruction
REG
=
FF
W
=
2
C
=
0
Z
=
0
N
=
1 ; result is negative
Example 2:
SUBFWB
REG, 0, 0
Before Instruction
REG
=
2
W
=
5
C
=
1
After Instruction
REG
=
2
W
=
3
C
=
1
Z
=
0
N
=
0 ; result is positive
SUBFWB
REG, 1, 0
Example 3:
Before Instruction
REG
=
1
W
=
2
C
=
0
After Instruction
REG
=
0
W
=
2
C
=
1
Z
=
1 ; result is zero
N
=
0
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
SUBLW
Subtract W from Literal
SUBWF
Subtract W from f
Syntax:
SUBLW k
Syntax:
SUBWF
Operands:
0 ≤ k ≤ 255
Operands:
Operation:
k – (W) → W
Status Affected:
N, OV, C, DC, Z
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (W) → dest
Status Affected:
N, OV, C, DC, Z
Encoding:
0000
1000
kkkk
kkkk
Description:
W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.
Words:
1
Cycles:
1
Encoding:
0101
Description:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
Example 1:
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
Example 2:
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
Example 3:
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
SUBLW
SUBLW
; result is positive
02h
?
00h
1
1
0
SUBLW
; result is zero
02h
03h
?
FFh
0
0
1
; (2’s complement)
; result is negative
ffff
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the result
is stored back in register ‘f’ (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
SUBWF
REG, 1, 0
Example 1:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 2:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 3:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
© 2009 Microchip Technology Inc.
ffff
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
02h
02h
11da
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
01h
?
01h
1
0
0
f {,d {,a}}
3
2
?
1
2
1
0
0
; result is positive
SUBWF
REG, 0, 0
2
2
?
2
0
1
1
0
SUBWF
; result is zero
REG, 1, 0
1
2
?
FFh ;(2’s complement)
2
0
; result is negative
0
1
DS39932C-page 443
PIC18F46J11 FAMILY
SUBWFB
Subtract W from f with Borrow
SWAPF
Swap f
Syntax:
SUBWFB
Syntax:
SWAPF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (W) – (C) → dest
Operation:
Status Affected:
N, OV, C, DC, Z
(f<3:0>) → dest<7:4>,
(f<7:4>) → dest<3:0>
Status Affected:
None
Encoding:
0101
Description:
f {,d {,a}}
10da
ffff
ffff
Subtract W and the Carry flag (borrow)
from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
Encoding:
0011
Description:
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Read
register ‘f’
Example 1:
SUBWFB
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 2:
Q4
Write to
destination
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
REG, 1, 0
19h
0Dh
1
(0001 1001)
(0000 1101)
0Ch
0Dh
1
0
0
(0000 1011)
(0000 1101)
ffff
Example:
SWAPF
Before Instruction
REG
=
After Instruction
REG
=
REG, 1, 0
53h
35h
; result is positive
SUBWFB REG, 0, 0
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 3:
1Bh
1Ah
0
(0001 1011)
(0001 1010)
1Bh
00h
1
1
0
(0001 1011)
SUBWFB
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
C
Z
N
Q3
Process
Data
ffff
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
10da
The upper and lower nibbles of register
‘f’ are exchanged. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed in register ‘f’ (default).
=
=
=
=
DS39932C-page 444
; result is zero
REG, 1, 0
03h
0Eh
1
(0000 0011)
(0000 1101)
F5h
(1111 0100)
; [2’s comp]
(0000 1101)
0Eh
0
0
1
; result is negative
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TBLRD
Table Read
TBLRD
Table Read (Continued)
Syntax:
TBLRD ( *; *+; *-; +*)
Example 1:
TBLRD
Operands:
None
Operation:
if TBLRD *,
(Prog Mem (TBLPTR)) → TABLAT,
TBLPTR – No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) → TABLAT,
(TBLPTR) + 1 → TBLPTR;
if TBLRD *-,
(Prog Mem (TBLPTR)) → TABLAT,
(TBLPTR) – 1 → TBLPTR;
if TBLRD +*,
(TBLPTR) + 1 → TBLPTR,
(Prog Mem (TBLPTR)) → TABLAT
Before Instruction
TABLAT
TBLPTR
MEMORY(00A356h)
After Instruction
TABLAT
TBLPTR
Example 2:
Status Affected: None
Encoding:
Description:
0000
0000
0000
10nn
nn=0 *
=1 *+
=2 *=3 +*
TBLRD
Before Instruction
TABLAT
TBLPTR
MEMORY(01A357h)
MEMORY(01A358h)
After Instruction
TABLAT
TBLPTR
*+ ;
=
=
=
55h
00A356h
34h
=
=
34h
00A357h
+* ;
=
=
=
=
AAh
01A357h
12h
34h
=
=
34h
01A358h
This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory.
TBLPTR has a 2-Mbyte address range.
TBLPTR<0> = 0: Least Significant Byte of
Program Memory Word
TBLPTR<0> = 1: Most Significant Byte of
Program Memory Word
The TBLRD instruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
No
operation
No operation
(Read Program
Memory)
No
operation
No operation
(Write
TABLAT)
© 2009 Microchip Technology Inc.
DS39932C-page 445
PIC18F46J11 FAMILY
TBLWT
Table Write
TBLWT
Table Write (Continued)
Syntax:
TBLWT ( *; *+; *-; +*)
Example 1:
TBLWT *+;
Operands:
None
Operation:
if TBLWT*,
(TABLAT) → Holding Register,
TBLPTR – No Change;
if TBLWT*+,
(TABLAT) → Holding Register,
(TBLPTR) + 1 → TBLPTR;
if TBLWT*-,
(TABLAT) → Holding Register,
(TBLPTR) – 1 → TBLPTR;
if TBLWT+*,
(TBLPTR) + 1 → TBLPTR,
(TABLAT) → Holding Register
Status Affected:
Example 2:
None
Encoding:
Description:
Before Instruction
TABLAT
=
55h
TBLPTR
=
00A356h
HOLDING REGISTER
(00A356h)
=
FFh
After Instructions (table write completion)
TABLAT
=
55h
TBLPTR
=
00A357h
HOLDING REGISTER
(00A356h)
=
55h
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *=3 +*
This instruction uses the 3 LSBs of
TBLPTR to determine which of the
8 holding registers the TABLAT is written
to. The holding registers are used to
program the contents of Program Memory
(P.M.). (Refer to Section 5.0 “Memory
Organization” for additional details on
programming Flash memory.)
TBLWT +*;
Before Instruction
TABLAT
=
34h
TBLPTR
=
01389Ah
HOLDING REGISTER
(01389Ah)
=
FFh
HOLDING REGISTER
(01389Bh)
=
FFh
After Instruction (table write completion)
TABLAT
=
34h
TBLPTR
=
01389Bh
HOLDING REGISTER
(01389Ah)
=
FFh
HOLDING REGISTER
(01389Bh)
=
34h
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory.
TBLPTR has a 2-Mbyte address range.
The LSb of the TBLPTR selects which
byte of the program memory location to
access.
TBLPTR<0> = 0: Least Significant Byte
of Program Memory
Word
TBLPTR<0> = 1: Most Significant Byte of
Program Memory Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
•
•
•
•
no change
post-increment
post-decrement
pre-increment
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
No
No
No
operation operation operation
No
No
No
No
operation operation operation operation
(Write to
(Read
Holding
TABLAT)
Register)
DS39932C-page 446
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TSTFSZ
Test f, Skip if 0
XORLW
Exclusive OR Literal with W
Syntax:
TSTFSZ f {,a}
Syntax:
XORLW k
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ k ≤ 255
Operation:
(W) .XOR. k → W
Status Affected:
N, Z
Operation:
skip if f = 0
Status Affected:
None
Encoding:
Encoding:
0110
Description:
011a
ffff
ffff
If ‘f’ = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOP is executed,
making this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
0000
1010
kkkk
kkkk
Description:
The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
Example:
Before Instruction
W
=
After Instruction
W
=
XORLW
0AFh
B5h
1Ah
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NZERO
ZERO
Before Instruction
PC
After Instruction
If CNT
PC
If CNT
PC
TSTFSZ
:
:
CNT, 1
=
Address (HERE)
=
=
≠
=
00h,
Address (ZERO)
00h,
Address (NZERO)
© 2009 Microchip Technology Inc.
DS39932C-page 447
PIC18F46J11 FAMILY
XORWF
Exclusive OR W with f
Syntax:
XORWF
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .XOR. (f) → dest
Status Affected:
N, Z
Encoding:
0001
Description:
f {,d {,a}}
10da
ffff
ffff
Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in the register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
XORWF
Before Instruction
REG
=
W
=
After Instruction
REG
=
W
=
DS39932C-page 448
REG, 1, 0
AFh
B5h
1Ah
B5h
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
26.2
Extended Instruction Set
A summary of the instructions in the extended instruction set is provided in Table 26-3. Detailed descriptions
are provided in Section 26.2.2 “Extended Instruction
Set”. The opcode field descriptions in Table 26-1
(page 408) apply to both the standard and extended
PIC18 instruction sets.
In addition to the standard 75 instructions of the PIC18
instruction set, the PIC18F46J11 family of devices also
provides an optional extension to the core CPU functionality. The added features include eight additional
instructions that augment Indirect and Indexed
Addressing operations and the implementation of
Indexed Literal Offset Addressing for many of the
standard PIC18 instructions.
Note:
The additional features of the extended instruction
set are enabled by default on unprogrammed
devices. Users must properly set or clear the XINST
Configuration bit during programming to enable or
disable these features.
The instructions in the extended set can all be
classified as literal operations, which either manipulate
the File Select Registers (FSR), or use them for
Indexed Addressing. Two of the instructions, ADDFSR
and SUBFSR, each have an additional special instantiation for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution.
26.2.1
EXTENDED INSTRUCTION SYNTAX
Most of the extended instructions use indexed arguments, using one of the FSRs and some offset to specify
a source or destination register. When an argument for
an instruction serves as part of Indexed Addressing, it is
enclosed in square brackets (“[ ]”). This is done to indicate that the argument is used as an index or offset. The
MPASM™ Assembler will flag an error if it determines
that an index or offset value is not bracketed.
The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
When the extended instruction set is enabled, brackets
are also used to indicate index arguments in
byte-oriented and bit-oriented instructions. This is in
addition to other changes in their syntax. For more
details, see Section 26.2.3.1 “Extended Instruction
Syntax with Standard PIC18 Commands”.
• Dynamic allocation and deallocation of software
stack space when entering and leaving
subroutines
• Function Pointer invocation
• Software Stack Pointer manipulation
• Manipulation of variables located in a software
stack
TABLE 26-3:
The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C; the user may likely never use
these instructions directly in assembler.
The syntax for these commands is
provided as a reference for users who may
be reviewing code that has been
generated by a compiler.
Note:
In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text and going forward, optional
arguments are denoted by braces (“{ }”).
EXTENSIONS TO THE PIC18 INSTRUCTION SET
Mnemonic,
Operands
ADDFSR
ADDULNK
CALLW
MOVSF
f, k
k
MOVSS
zs, zd
PUSHL
k
SUBFSR
SUBULNK
f, k
k
zs, fd
Description
Add Literal to FSR
Add Literal to FSR2 and Return
Call Subroutine using WREG
Move zs (source) to 1st word
fd (destination) 2nd word
Move zs (source) to 1st word
zd (destination) 2nd word
Store Literal at FSR2,
Decrement FSR2
Subtract Literal from FSR
Subtract Literal from FSR2 and
Return
© 2009 Microchip Technology Inc.
Cycles
1
2
2
2
16-Bit Instruction Word
MSb
LSb
1
1110
1110
0000
1110
1111
1110
1111
1110
1000
1000
0000
1011
ffff
1011
xxxx
1010
ffkk
11kk
0001
0zzz
ffff
1zzz
xzzz
kkkk
kkkk
kkkk
0100
zzzz
ffff
zzzz
zzzz
kkkk
1
2
1110
1110
1001
1001
ffkk
11kk
kkkk
kkkk
2
Status
Affected
None
None
None
None
—
None
—
None
—
None
None
DS39932C-page 449
PIC18F46J11 FAMILY
26.2.2
EXTENDED INSTRUCTION SET
ADDFSR
Add Literal to FSR
ADDULNK
Syntax:
ADDFSR f, k
Syntax:
ADDULNK k
Operands:
0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
Operands:
0 ≤ k ≤ 63
Operation:
FSR(f) + k → FSR(f)
Status Affected:
None
Encoding:
1110
Add Literal to FSR2 and Return
FSR2 + k → FSR2,
Operation:
(TOS) → PC
Status Affected:
1000
ffkk
kkkk
Description:
The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’.
Words:
1
Cycles:
1
None
Encoding:
1110
Description:
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
FSR
Example:
03FFh
After Instruction
FSR2
=
0422h
This may be thought of as a special
case of the ADDFSR instruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
FSR
No
Operation
No
Operation
No
Operation
No
Operation
Example:
Note:
kkkk
The instruction takes two cycles to
execute; a NOP is performed during
the second cycle.
ADDFSR 2, 23h
Before Instruction
FSR2
=
11kk
The 6-bit literal ‘k’ is added to the
contents of FSR2. A RETURN is then
executed by loading the PC with the
TOS.
Q Cycle Activity:
Q1
1000
ADDULNK 23h
Before Instruction
FSR2
=
PC
=
03FFh
0100h
After Instruction
FSR2
=
PC
=
0422h
(TOS)
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
DS39932C-page 450
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
CALLW
Subroutine Call using WREG
MOVSF
Syntax:
CALLW
Syntax:
MOVSF [zs], fd
Operands:
None
Operands:
Operation:
(PC + 2) → TOS,
(W) → PCL,
(PCLATH) → PCH,
(PCLATU) → PCU
0 ≤ zs ≤ 127
0 ≤ fd ≤ 4095
Operation:
((FSR2) + zs) → fd
Status Affected:
None
Status Affected:
None
Encoding:
0000
Description
0000
0001
0100
First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then, the
contents of PCLATH and PCLATU are
latched into PCH and PCU, respectively. The second cycle is executed as
a NOP instruction while the new next
instruction is fetched.
Move Indexed to f
Encoding:
1st word (source)
2nd word (destin.)
Description:
Unlike CALL, there is no option to
update W, STATUS or BSR.
Words:
1
Cycles:
2
Q1
Q2
Q3
Q4
Read
WREG
Push PC to
stack
No
operation
No
operation
No
operation
No
operation
No
operation
Before Instruction
PC
=
PCLATH =
PCLATU =
W
=
After Instruction
PC
=
TOS
=
PCLATH =
PCLATU =
W
=
Words:
2
Cycles:
2
Q Cycle Activity:
CALLW
Decode
address (HERE)
10h
00h
06h
001006h
address (HERE + 2)
10h
00h
06h
© 2009 Microchip Technology Inc.
zzzzs
ffffd
The contents of the source register are
moved to destination register ‘fd’. The
actual address of the source register is
determined by adding the 7-bit literal
offset ‘zs’, in the first word, to the value
of FSR2. The address of the destination register is specified by the 12-bit literal ‘fd’ in the second word. Both
addresses can be anywhere in the
4096-byte data space (000h to FFFh).
Q1
HERE
0zzz
ffff
If the resultant source address points to
an Indirect Addressing register, the
value returned will be 00h.
Decode
Example:
1011
ffff
The MOVSF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Q Cycle Activity:
Decode
1110
1111
Q2
Q3
Determine
Determine
source addr source addr
No
operation
No
operation
No dummy
read
Example:
MOVSF
Before Instruction
FSR2
Contents
of 85h
REG2
After Instruction
FSR2
Contents
of 85h
REG2
Q4
Read
source reg
Write
register ‘f’
(dest)
[05h], REG2
=
80h
=
=
33h
11h
=
80h
=
=
33h
33h
DS39932C-page 451
PIC18F46J11 FAMILY
MOVSS
Move Indexed to Indexed
PUSHL
Store Literal at FSR2, Decrement FSR2
Syntax:
MOVSS [zs], [zd]
Syntax:
PUSHL k
Operands:
0 ≤ zs ≤ 127
0 ≤ zd ≤ 127
Operands:
0 ≤ k ≤ 255
Operation:
k → (FSR2),
FSR2 – 1 → FSR2
Status Affected:
None
Operation:
((FSR2) + zs) → ((FSR2) + zd)
Status Affected:
None
Encoding:
1st word (source)
2nd word (dest.)
1110
1111
Description
1011
xxxx
1zzz
xzzz
zzzzs
zzzzd
The contents of the source register are
moved to the destination register. The
addresses of the source and destination registers are determined by adding
the 7-bit literal offsets ‘zs’ or ‘zd’,
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4096-byte data memory space
(000h to FFFh).
The MOVSS instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an Indirect Addressing register, the
value returned will be 00h. If the
resultant destination address points to
an Indirect Addressing register, the
instruction will execute as a NOP.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Decode
Decode
Q2
Q3
Determine
Determine
source addr source addr
Determine
dest addr
Example:
1110
Description:
1010
kkkk
kkkk
The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2.
FSR2 is decremented by 1 after the
operation.
This instruction allows users to push
values onto a software stack.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read ‘k’
Process
data
Write to
destination
Example:
PUSHL 08h
Before Instruction
FSR2H:FSR2L
Memory (01ECh)
=
=
01ECh
00h
After Instruction
FSR2H:FSR2L
Memory (01ECh)
=
=
01EBh
08h
Q4
Read
source reg
Write
to dest reg
MOVSS [05h], [06h]
Before Instruction
FSR2
Contents
of 85h
Contents
of 86h
After Instruction
FSR2
Contents
of 85h
Contents
of 86h
DS39932C-page 452
Determine
dest addr
Encoding:
=
80h
=
33h
=
11h
=
80h
=
33h
=
33h
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
SUBFSR
Subtract Literal from FSR
SUBULNK
Syntax:
SUBFSR f, k
Syntax:
SUBULNK k
Operands:
0 ≤ k ≤ 63
Operands:
0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
Operation:
FSR2 – k → FSR2,
Operation:
FSRf – k → FSRf
Status Affected:
None
Encoding:
1110
(TOS) → PC
Status Affected:
1001
ffkk
kkkk
Description:
The 6-bit literal ‘k’ is subtracted from
the contents of the FSR specified
by ‘f’.
Words:
1
Cycles:
1
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Before Instruction
FSR2
=
After Instruction
FSR2
=
SUBFSR 2, 23h
None
Encoding:
1110
Description:
1001
11kk
kkkk
The 6-bit literal ‘k’ is subtracted from the
contents of the FSR2. A RETURN is then
executed by loading the PC with the
TOS.
The instruction takes two cycles to
execute; a NOP is performed during the
second cycle.
Q Cycle Activity:
Example:
Subtract Literal from FSR2 and Return
This may be thought of as a special case
of the SUBFSR instruction, where f = 3
(binary ‘11’); it operates only on FSR2.
Words:
1
Cycles:
2
Q Cycle Activity:
03FFh
03DCh
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
No
Operation
No
Operation
No
Operation
No
Operation
Example:
© 2009 Microchip Technology Inc.
SUBULNK 23h
Before Instruction
FSR2
=
PC
=
03FFh
0100h
After Instruction
FSR2
=
PC
=
03DCh
(TOS)
DS39932C-page 453
PIC18F46J11 FAMILY
26.2.3
Note:
BYTE-ORIENTED AND
BIT-ORIENTED INSTRUCTIONS IN
INDEXED LITERAL OFFSET MODE
Enabling the PIC18 instruction set extension may cause legacy applications to
behave erratically or fail entirely
In addition to eight new commands in the extended set,
enabling the extended instruction set also enables
Indexed Literal Offset Addressing (Section 5.6.1
“Indexed Addressing with Literal Offset”). This has
a significant impact on the way that many commands of
the standard PIC18 instruction set are interpreted.
When the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations:
either as a location in the Access Bank (a = 0) or in a
GPR bank designated by the BSR (a = 1). When the
extended instruction set is enabled and a = 0, however,
a file register argument of 5Fh or less is interpreted as
an offset from the pointer value in FSR2 and not as a
literal address. For practical purposes, this means that
all instructions that use the Access RAM bit as an
argument – that is, all byte-oriented and bit-oriented
instructions, or almost half of the core PIC18 instructions – may behave differently when the extended
instruction set is enabled.
When the content of FSR2 is 00h, the boundaries of the
Access RAM are essentially remapped to their original
values. This may be useful in creating
backward-compatible code. If this technique is used, it
may be necessary to save the value of FSR2 and
restore it when moving back and forth between C and
assembly routines in order to preserve the Stack
Pointer. Users must also keep in mind the syntax
requirements of the extended instruction set (see
Section 26.2.3.1 “Extended Instruction Syntax with
Standard PIC18 Commands”).
Although the Indexed Literal Offset mode can be very
useful for dynamic stack and pointer manipulation, it
can also be very annoying if a simple arithmetic operation is carried out on the wrong register. Users who are
accustomed to the PIC18 programming must keep in
mind that, when the extended instruction set is
enabled, register addresses of 5Fh or less are used for
Indexed Literal Offset Addressing.
Representative examples of typical byte-oriented and
bit-oriented instructions in the Indexed Literal Offset
mode are provided on the following page to show how
execution is affected. The operand conditions provided
in the examples are applicable to all instructions of
these types.
DS39932C-page 454
26.2.3.1
Extended Instruction Syntax with
Standard PIC18 Commands
When the extended instruction set is enabled, the file
register argument ‘f’ in the standard byte-oriented and
bit-oriented commands is replaced with the literal offset
value ‘k’. As already noted, this occurs only when ‘f’ is
less than or equal to 5Fh. When an offset value is used,
it must be indicated by square brackets (“[ ]”). As with
the extended instructions, the use of brackets indicates
to the compiler that the value is to be interpreted as an
index or an offset. Omitting the brackets, or using a
value greater than 5Fh within the brackets, will
generate an error in the MPASM Assembler.
If the index argument is properly bracketed for Indexed
Literal Offset Addressing, the Access RAM argument is
never specified; it will automatically be assumed to be
‘0’. This is in contrast to standard operation (extended
instruction set disabled) when ‘a’ is set on the basis of
the target address. Declaring the Access RAM bit in
this mode will also generate an error in the MPASM
Assembler.
The destination argument ‘d’ functions as before.
In the latest versions of the MPASM Assembler,
language support for the extended instruction set must
be explicitly invoked. This is done with either the
command line option, /y, or the PE directive in the
source listing.
26.2.4
CONSIDERATIONS WHEN
ENABLING THE EXTENDED
INSTRUCTION SET
It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular,
users who are not writing code that uses a software
stack may not benefit from using the extensions to the
instruction set.
Additionally, the Indexed Literal Offset Addressing
mode may create issues with legacy applications
written to the PIC18 assembler. This is because
instructions in the legacy code may attempt to address
registers in the Access Bank below 5Fh. Since these
addresses are interpreted as literal offsets to FSR2
when the instruction set extension is enabled, the
application may read or write to the wrong data
addresses.
When porting an application to the PIC18F46J11 family, it is very important to consider the type of code. A
large, re-entrant application that is written in C and
would benefit from efficient compilation will do well
when using the instruction set extensions. Legacy
applications that heavily use the Access Bank will most
likely not benefit from using the extended instruction
set.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
ADD W to Indexed
(Indexed Literal Offset mode)
BSF
Bit Set Indexed
(Indexed Literal Offset mode)
Syntax:
ADDWF
Syntax:
BSF [k], b
Operands:
0 ≤ k ≤ 95
d ∈ [0,1]
Operands:
0 ≤ f ≤ 95
0≤b≤7
Operation:
(W) + ((FSR2) + k) → dest
Operation:
1 → ((FSR2) + k)<b>
Status Affected:
N, OV, C, DC, Z
Status Affected:
None
ADDWF
Encoding:
[k] {,d}
0010
Description:
01d0
kkkk
kkkk
The contents of W are added to the
contents of the register indicated by
FSR2, offset by the value ‘k’.
If ‘d’ is ‘0’, the result is stored in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’ (default).
Words:
1
Cycles:
1
Encoding:
1000
bbb0
kkkk
kkkk
Description:
Bit ‘b’ of the register indicated by
FSR2, offset by the value ‘k’, is set.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read ‘k’
Process
Data
Write to
destination
Example:
ADDWF
Before Instruction
W
OFST
FSR2
Contents
of 0A2Ch
After Instruction
W
Contents
of 0A2Ch
[OFST] ,0
=
=
=
17h
2Ch
0A00h
=
20h
=
37h
=
20h
Example:
BSF
Before Instruction
FLAG_OFST
FSR2
Contents
of 0A0Ah
After Instruction
Contents
of 0A0Ah
[FLAG_OFST], 7
=
=
0Ah
0A00h
=
55h
=
D5h
SETF
Set Indexed
(Indexed Literal Offset mode)
Syntax:
SETF [k]
Operands:
0 ≤ k ≤ 95
Operation:
FFh → ((FSR2) + k)
Status Affected:
None
Encoding:
0110
1000
kkkk
kkkk
Description:
The contents of the register indicated
by FSR2, offset by ‘k’, are set to FFh.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read ‘k’
Process
Data
Write
register
Example:
SETF
Before Instruction
OFST
FSR2
Contents
of 0A2Ch
After Instruction
Contents
of 0A2Ch
© 2009 Microchip Technology Inc.
[OFST]
=
=
2Ch
0A00h
=
00h
=
FFh
DS39932C-page 455
PIC18F46J11 FAMILY
26.2.5
SPECIAL CONSIDERATIONS WITH
MICROCHIP MPLAB® IDE TOOLS
The latest versions of Microchip’s software tools have
been designed to fully support the extended instruction
set for the PIC18F46J11 family. This includes the
MPLAB C18 C Compiler, MPASM assembly language
and MPLAB Integrated Development Environment
(IDE).
When selecting a target device for software
development, MPLAB IDE will automatically set default
Configuration bits for that device. The default setting for
the XINST Configuration bit is ‘0’, disabling the
extended instruction set and Indexed Literal Offset
Addressing. For proper execution of applications
developed to take advantage of the extended
instruction set, XINST must be set during
programming.
DS39932C-page 456
To develop software for the extended instruction set,
the user must enable support for the instructions and
the Indexed Addressing mode in their language tool(s).
Depending on the environment being used, this may be
done in several ways:
• A menu option or dialog box within the environment that allows the user to configure the
language tool and its settings for the project
• A command line option
• A directive in the source code
These options vary between different compilers,
assemblers and development environments. Users are
encouraged to review the documentation accompanying their development systems for the appropriate
information.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
27.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C18 and MPLAB C30 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
• Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debugger
- MPLAB ICD 2
• Device Programmers
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
- PICkit™ 2 Development Programmer
• Low-Cost Demonstration and Development
Boards and Evaluation Kits
27.1
MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Visual device initializer for easy register
initialization
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2009 Microchip Technology Inc.
DS39932C-page 457
PIC18F46J11 FAMILY
27.2
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for all PIC MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
27.3
MPLAB C18 and MPLAB C30
C Compilers
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI C compilers for
Microchip’s PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital
signal controllers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
27.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
27.5
MPLAB ASM30 Assembler, Linker
and Librarian
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
•
•
•
•
•
•
Support for the entire dsPIC30F instruction set
Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
27.6
MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the hardware laboratory environment, making it an
excellent, economical software development tool.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
DS39932C-page 458
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
27.7
MPLAB ICE 2000
High-Performance
In-Circuit Emulator
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC
microcontrollers. Software control of the MPLAB ICE
2000 In-Circuit Emulator is advanced by the MPLAB
Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
27.8
MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection
(CAT5).
27.9
MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by setting breakpoints, single stepping and watching variables, and CPU status and
peripheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
27.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modular, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be supported,
and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE
offers significant advantages over competitive emulators
including low-cost, full-speed emulation, real-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
© 2009 Microchip Technology Inc.
DS39932C-page 459
PIC18F46J11 FAMILY
27.11 PICSTART Plus Development
Programmer
27.13 Demonstration, Development and
Evaluation Boards
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
27.12 PICkit 2 Development Programmer
The PICkit™ 2 Development Programmer is a low-cost
programmer and selected Flash device debugger with
an easy-to-use interface for programming many of
Microchip’s baseline, mid-range and PIC18F families of
Flash memory microcontrollers. The PICkit 2 Starter Kit
includes a prototyping development board, twelve
sequential lessons, software and HI-TECH’s PICC™
Lite C compiler, and is designed to help get up to speed
quickly using PIC® microcontrollers. The kit provides
everything needed to program, evaluate and develop
applications using Microchip’s powerful, mid-range
Flash memory family of microcontrollers.
DS39932C-page 460
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
28.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any digital only I/O pin or MCLR with respect to VSS (except VDD) ........................................... -0.3V to 6.0V
Voltage on any combined digital and analog pin with respect to VSS (except VDD)........................ -0.3V to (VDD + 0.3V)
Voltage on VDDCORE with respect to VSS ................................................................................................... -0.3V to 2.75V
Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 4.0V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Maximum output current sunk by any PORTB, PORTC and RA6 I/O pin...............................................................25 mA
Maximum output current sunk by any PORTA (except RA6), PORTD and PORTE I/O pin......................................4 mA
Maximum output current sourced by any PORTB, PORTC and RA6 I/O pin .........................................................25 mA
Maximum output current sourced by any PORTA (except RA6), PORTD and PORTE I/O pin ................................4 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑ (VOL x IOL)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
FIGURE 28-1:
PIC18F46J11 FAMILY VDD FREQUENCY GRAPH (INDUSTRIAL)
4.0V
3.6V
Voltage (VDD)
3.5V
3.0V
PIC18F46J11 Family Valid Operating Range
2.5V
2.35V
2.15V
0
© 2009 Microchip Technology Inc.
8 MHz
48 MHz
DS39932C-page 461
PIC18F46J11 FAMILY
PIC18LF46J11 VDDCORE FREQUENCY GRAPH (INDUSTRIAL)(1)
FIGURE 28-2:
3.00V
Voltage (VDDCORE)
2.75V
2.75V
2.50V
PIC18LF46J11 Family Valid Operating Range
2.35V
2.25V
2.00V
0
Note 1:
48 MHz
8 MHz
Frequency
VDD and VDDCORE must be maintained so that VDDCORE ≤ VDD.
DS39932C-page 462
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
28.1
DC Characteristics: Supply Voltage PIC18F46J11 Family (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18F46J11 Family
Param
No.
Symbol
Characteristic
Supply Voltage
Min
Typ
Max
Units
Conditions
2.15
2.0
—
—
3.6
3.6
V
V
PIC18F4XJ11, PIC18F2XJ11
PIC18LF4XJ11, PIC18LF2XJ11
2.0
—
2.75
V
PIC18LF4XJ11, PIC18LF2XJ11
VDD – 0.3
—
VDD + 0.3
V
D001
VDD
D001B
VDDCORE External Supply for
Microcontroller Core
D001C
AVDD
Analog Supply Voltage
D001D
AVSS
Analog Ground Potential VSS – 0.3
—
VSS + 0.3
V
D002
VDR
RAM Data Retention
Voltage(1)
1.5
—
—
V
D003
VPOR
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
—
—
0.7
V
D004
SVDD
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
0.05
—
—
D005
VBOR
VDDCORE Brown-out
Reset Voltage
—
2.0
—
V
PIC18F4XJ11, PIC18F2XJ11
only (not used on “LF” devices)
D006
VDSBOR
VDD Brown-out Reset
Voltage
—
1.8
—
V
DSBOREN = 1 on “LF” device,
or “F” device In Deep Sleep
Note 1:
This is the limit to which VDDCORE can be lowered in Sleep mode, or during a device Reset, without losing RAM
data.
© 2009 Microchip Technology Inc.
See Section 4.3 “Power-on
Reset (POR)” for details
V/ms See Section 4.3 “Power-on
Reset (POR)” for details
DS39932C-page 463
PIC18F46J11 FAMILY
28.2
DC Characteristics: Power-Down and Supply Current
PIC18F46J50 Family (Industrial)
PIC18LFXXJ11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18FXXJ11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Typ
Max
Units
Conditions
Power-Down Current (IPD)(1) – Sleep mode
PIC18LFXXJ11 0.011
1.4
μA
-40°C
0.054
1.4
μA
+25°C
0.51
6
μA
+60°C
2.0
10.2
μA
+85°C
1.5
μA
-40°C
0.11
1.5
μA
+25°C
0.63
8
μA
+60°C
2.30
12.6
μA
+85°C
2.5
5
μA
-40°C
3.1
5
μA
+25°C
3.9
8
μA
+60°C
5.6
16
μA
+85°C
4.1
7
μA
-40°C
3.3
7
μA
+25°C
4.1
10
μA
+60°C
6.0
19
μA
+85°C
PIC18LFXXJ11 0.029
PIC18FXXJ11
PIC18FXXJ11
VDD = 2.0V,
VDDCORE = 2.0V
VDD = 2.5V,
VDDCORE = 2.5V
Sleep mode,
REGSLP = 1
VDD = 2.15V,
VDDCORE = 10 μF
Capacitor
VDD = 3.3V,
VDDCORE = 10 μF
Capacitor
Power-Down Current (IPD)(1) – Deep Sleep mode
PIC18FXXJ11
PIC18FXXJ11
Note 1:
2:
3:
1
25
nA
-40°C
13
100
nA
+25°C
108
250
nA
+60°C
428
1000
nA
+85°C
3
50
nA
-40°C
28
150
nA
+25°C
170
389
nA
+60°C
588
2000
nA
+85°C
VDD = 2.15V,
VDDCORE = 10 μF
Capacitor
Deep Sleep mode
VDD = 3.3V,
VDDCORE = 10 μF
Capacitor
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature,
also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The
test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS;
MCLR = VDD; WDT disabled unless otherwise specified.
Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to
+70°C. Extended temperature crystals are available at a much higher cost.
DS39932C-page 464
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
28.2
DC Characteristics: Power-Down and Supply Current
PIC18F46J50 Family (Industrial) (Continued)
PIC18LFXXJ11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18FXXJ11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Typ
Max
Units
Conditions
5.2
14.2
μA
-40°C
6.2
14.2
μA
+25°C
Supply Current (IDD)(2)
PIC18LFXXJ11
PIC18LFXXJ11
PIC18FXXJ11
PIC18FXXJ11
PIC18LFXXJ11
PIC18LFXXJ11
PIC18FXXJ11
PIC18FXXJ11
Note 1:
2:
3:
8.6
19.0
μA
+85°C
7.6
16.5
μA
-40°C
8.5
16.5
μA
+25°C
11.3
22.4
μA
+85°C
37
77
μA
-40°C
48
77
μA
+25°C
60
93
μA
+85°C
52
84
μA
-40°C
61
84
μA
+25°C
70
108
μA
+85°C
1.1
1.5
mA
-40°C
1.1
1.5
mA
+25°C
1.2
1.6
mA
+85°C
1.5
1.7
mA
-40°C
1.6
1.7
mA
+25°C
1.6
1.9
mA
+85°C
1.3
2.6
mA
-40°C
1.4
2.6
mA
+25°C
1.4
2.8
mA
+85°C
1.6
2.9
mA
-40°C
1.6
2.9
mA
+25°C
1.6
3.0
mA
+85°C
VDD = 2.0V,
VDDCORE = 2.0V
VDD = 2.5V,
VDDCORE = 2.5V
VDD = 2.15V,
VDDCORE = 10 μF
FOSC = 31 kHz, RC_RUN
mode, Internal RC
Oscillator, INTSRC = 0
VDD = 3.3V,
VDDCORE = 10 μF
VDD = 2.0V,
VDDCORE = 2.0
VDD = 2.5V,
VDDCORE = 2.5V
VDD = 2.15V,
VDDCORE = 10 μF
FOSC = 4 MHz, RC_RUN
mode, Internal RC Oscillator
VDD = 3.3V,
VDDCORE = 10 μF
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature,
also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The
test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS;
MCLR = VDD; WDT disabled unless otherwise specified.
Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to
+70°C. Extended temperature crystals are available at a much higher cost.
© 2009 Microchip Technology Inc.
DS39932C-page 465
PIC18F46J11 FAMILY
28.2
DC Characteristics: Power-Down and Supply Current
PIC18F46J50 Family (Industrial) (Continued)
PIC18LFXXJ11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18FXXJ11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Typ
Max
Units
Conditions
1.9
3.6
mA
-40°C
2.0
3.8
mA
+25°C
Supply Current (IDD)(2)
PIC18LFXXJ11
PIC18LFXXJ11
+85°C
-40°C
2.8
4.8
mA
+25°C
4.9
mA
+85°C
4.2
mA
-40°C
2.3
4.2
mA
+25°C
2.4
4.5
mA
+85°C
2.8
5.1
mA
-40°C
2.8
5.1
mA
+25°C
2.8
5.4
mA
+85°C
1.9
9.4
μA
-40°C
2.3
9.4
μA
+25°C
4.5
17.2
μA
+85°C
2.4
10.5
μA
-40°C
2.8
10.5
μA
+25°C
5.4
19.5
μA
+85°C
PIC18FXXJ11 33.3
75
μA
-40°C
43.8
75
μA
+25°C
+85°C
PIC18LFXXJ11
PIC18LFXXJ11
3:
mA
mA
2.8
PIC18FXXJ11
2:
3.8
4.8
2.3
PIC18FXXJ11
Note 1:
2.0
2.8
55.3
92
μA
PIC18FXXJ11 36.1
82
μA
-40°C
44.5
82
μA
+25°C
56.3
105
μA
+85°C
VDD = 2.0V,
VDDCORE = 2.0V
VDD = 2.5V,
VDDCORE = 2.5V
VDD = 2.15V,
VDDCORE = 10 μF
FOSC = 8 MHz, RC_RUN
mode, Internal RC Oscillator
VDD = 3.3V,
VDDCORE = 10 μF
VDD = 2.0V,
VDDCORE = 2.0V
VDD = 2.5V,
VDDCORE = 2.5V
VDD = 2.15V,
VDDCORE = 10 μF
FOSC = 31 kHz, RC_IDLE
mode, Internal RC Oscillator,
INTSRC = 0
VDD = 3.3V,
VDDCORE = 10 μF
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature,
also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The
test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS;
MCLR = VDD; WDT disabled unless otherwise specified.
Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to
+70°C. Extended temperature crystals are available at a much higher cost.
DS39932C-page 466
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
28.2
DC Characteristics: Power-Down and Supply Current
PIC18F46J50 Family (Industrial) (Continued)
PIC18LFXXJ11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18FXXJ11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Typ
Max
Units
Conditions
Supply Current (IDD)(2)
Note 1:
2:
3:
PIC18LFXXJ11 0.531 0.980
mA
-40°C
0.571 0.980
mA
+25°C
0.608
1.12
mA
+85°C
PIC18LFXXJ11 0.625
1.14
mA
-40°C
0.681
1.14
mA
+25°C
0.725
1.25
mA
+85°C
PIC18FXXJ11 0.613
1.21
mA
-40°C
0.680
1.21
mA
+25°C
0.730
1.30
mA
+85°C
PIC18FXXJ11 0.673
1.27
mA
-40°C
0.728
1.27
mA
+25°C
0.779
1.45
mA
+85°C
PIC18LFXXJ11 0.750
1.4
mA
-40°C
0.797
1.5
mA
+25°C
0.839
1.6
mA
+85°C
PIC18LFXXJ11 0.91
2.4
mA
-40°C
0.96
2.4
mA
+25°C
1.01
2.5
mA
+85°C
PIC18FXXJ11 0.87
2.1
mA
-40°C
0.93
2.1
mA
+25°C
+85°C
0.98
2.3
mA
PIC18FXXJ11 0.95
2.6
mA
-40°C
1.01
2.6
mA
+25°C
1.06
2.7
mA
+85°C
VDD = 2.0V,
VDDCORE = 2.0V
VDD = 2.5V,
VDDCORE = 2.5V
VDD = 2.15V,
VDDCORE = 10 μF
FOSC = 4 MHz, RC_IDLE
mode, Internal RC Oscillator
VDD = 3.3V,
VDDCORE = 10 μF
VDD = 2.0V,
VDDCORE = 2.0V
VDD = 2.5V,
VDDCORE = 2.5V
VDD = 2.15V,
VDDCORE = 10 μF
FOSC = 8 MHz, RC_IDLE
mode, Internal RC Oscillator
VDD = 3.3V,
VDDCORE = 10 μF
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature,
also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The
test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS;
MCLR = VDD; WDT disabled unless otherwise specified.
Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to
+70°C. Extended temperature crystals are available at a much higher cost.
© 2009 Microchip Technology Inc.
DS39932C-page 467
PIC18F46J11 FAMILY
28.2
DC Characteristics: Power-Down and Supply Current
PIC18F46J50 Family (Industrial) (Continued)
PIC18LFXXJ11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18FXXJ11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Typ
Max
Units
Conditions
PIC18LFXXJ11 0.879
1.25
mA
-40°C
0.881
1.25
mA
+25°C
Supply Current (IDD)(2)
Note 1:
2:
3:
0.891
1.36
mA
+85°C
PIC18LFXXJ11 1.35
1.70
mA
-40°C
1.30
1.70
mA
+25°C
1.27
1.82
mA
+85°C
PIC18FXXJ11 1.09
1.60
mA
-40°C
1.09
1.60
mA
+25°C
1.11
1.70
mA
+85°C
PIC18FXXJ11 1.36
1.95
mA
-40°C
1.36
1.89
mA
+25°C
1.41
1.92
mA
+85°C
PIC18LFXXJ11 10.9
14.8
mA
-40°C
10.6
14.8
mA
+25°C
10.6
15.2
mA
+85°C
PIC18FXXJ11 12.9
23.2
mA
-40°C
12.8
22.7
mA
+25°C
12.7
22.7
mA
+85°C
VDD = 2.0V,
VDDCORE = 2.0V
VDD = 2.0V,
VDDCORE = 2.0V
FOSC = 4 MHz, PRI_RUN
mode, EC Oscillator
VDD = 2.15V,
VDDCORE = 10 μF
VDD = 3.3V,
VDDCORE = 10 μF
VDD = 2.5V,
VDDCORE = 2.5V
FOSC = 48 MHz, PRI_RUN
mode, EC Oscillator
VDD = 3.3V,
VDDCORE = 10 μF
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature,
also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The
test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS;
MCLR = VDD; WDT disabled unless otherwise specified.
Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to
+70°C. Extended temperature crystals are available at a much higher cost.
DS39932C-page 468
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
28.2
DC Characteristics: Power-Down and Supply Current
PIC18F46J50 Family (Industrial) (Continued)
PIC18LFXXJ11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18FXXJ11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Typ
Max
Units
Conditions
Supply Current (IDD)(2)
PIC18LFXXJ11 0.285 0.700
mA
-40°C
0.300 0.700
mA
+25°C
mA
+85°C
PIC18LFXXJ11 0.372
0.336 0.750
1.00
mA
-40°C
0.397
1.00
mA
+25°C
0.495
1.10
mA
+85°C
PIC18FXXJ11 0.357 0.850
mA
-40°C
0.383 0.850
mA
+25°C
0.407 0.900
mA
+85°C
PIC18FXXJ11 0.449
1.30
mA
-40°C
0.488
1.20
mA
+25°C
0.554
1.20
mA
+85°C
4.5
6.5
mA
-40°C
4.5
6.5
mA
+25°C
4.6
6.5
mA
+85°C
4.9
12.4
mA
-40°C
5.0
11.5
mA
+25°C
5.1
11.5
mA
+85°C
PIC18LFXXJ11
PIC18FXXJ11
Note 1:
2:
3:
VDD = 2.0V,
VDDCORE = 2.0V
VDD = 2.5V,
VDDCORE = 2.5V
FOSC = 4 MHz, PRI_IDLE
mode, EC Oscillator
VDD = 2.15V,
VDDCORE = 10 μF
VDD = 3.3V,
VDDCORE = 10 μF
VDD = 2.5V,
VDDCORE = 2.5V
VDD = 3.3V,
VDDCORE = 10 μF
FOSC = 48 MHz
PRI_IDLE mode,
EC oscillator
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature,
also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The
test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS;
MCLR = VDD; WDT disabled unless otherwise specified.
Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to
+70°C. Extended temperature crystals are available at a much higher cost.
© 2009 Microchip Technology Inc.
DS39932C-page 469
PIC18F46J11 FAMILY
28.2
DC Characteristics: Power-Down and Supply Current
PIC18F46J50 Family (Industrial) (Continued)
PIC18LFXXJ11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18FXXJ11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
PIC18LFXXJ11
PIC18FXXJ11
PIC18LFXXJ11
PIC18FXXJ11
Note 1:
2:
3:
Typ
Max
Units
Conditions
5.2
6.5
mA
-40°C
5.1
6.4
mA
+25°C
5.1
6.4
mA
+85°C
5.3
7.5
mA
-40°C
5.2
7.4
mA
+25°C
5.2
7.4
mA
+85°C
9.3
12.0
mA
-40°C
9.2
11.8
mA
+25°C
9.0
11.8
mA
+85°C
9.7
17.5
mA
-40°C
9.6
17.2
mA
+25°C
+85°C
9.6
17.2
mA
PIC18LFXXJ11 12.4
13.5
mA
-40°C
12.2
13.5
mA
+25°C
12.1
13.9
mA
+85°C
PIC18FXXJ11 14.3
24.1
mA
-40°C
14.2
23.0
mA
+25°C
14.2
23.0
mA
+85°C
VDD = 2.5V,
VDDCORE = 2.5V
VDD = 3.3V,
VDDCORE = 10 μF
VDD = 2.5V,
VDDCORE = 2.5V
VDD = 3.3V,
VDDCORE = 10 μF
VDD = 2.5V,
VDDCORE = 2.5V
VDD = 3.3V,
VDDCORE = 10 μF
FOSC = 16 MHz
(PRI_RUN mode,
4 MHz Internal Oscillator
with PLL
FOSC = 32 MHz,
PRI_RUN mode,
8 MHz Internal Oscillator
with PLL
FOSC = 48 MHz,
PRI_RUN mode,
12 MHz External Oscillator
with PLL
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature,
also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The
test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS;
MCLR = VDD; WDT disabled unless otherwise specified.
Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to
+70°C. Extended temperature crystals are available at a much higher cost.
DS39932C-page 470
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
28.2
DC Characteristics: Power-Down and Supply Current
PIC18F46J50 Family (Industrial) (Continued)
PIC18LFXXJ11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18FXXJ11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Max
Units
PIC18LFXXJ11 12.5
45
μA
-40°C
11.7
45
μA
+25°C
5.2
61
μA
+85°C
PIC18FXXJ11 40.2
95
μA
-40°C
50.2
95
μA
+25°C
61.9
105
μA
+85°C
PIC18LFXXJ11 44.4
110
μA
-40°C
53.1
110
μA
+25°C
55.8
150
μA
+85°C
4.5
31
μA
-40°C
3.8
31
μA
+25°C
+85°C
PIC18FXXJ11
Note 1:
2:
3:
Typ
Conditions
4.1
50
μA
PIC18FXXJ11 34.7
87
μA
-40°C
44.6
89
μA
+25°C
+85°C
56.5
97
μA
PIC18LFXXJ11 37.3
100
μA
-40°C
45.7
100
μA
+25°C
54.6
140
μA
+85°C
VDD = 2.5V,
VDDCORE = 2.5V
VDD = 2.15V,
VDDCORE = 10 μF
FOSC = 32 kHz(3)
SEC_RUN mode,
LPT1OSC = 0
VDD = 3.3V,
VDDCORE = 10 μF
VDD = 2.5V,
VDDCORE = 2.5V
VDD = 2.15V,
VDDCORE = 10 μF
FOSC = 32 kHz(3)
SEC_IDLE mode,
LPT1OSC = 0
VDD = 3.3V,
VDDCORE = 10 μF
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature,
also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The
test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS;
MCLR = VDD; WDT disabled unless otherwise specified.
Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to
+70°C. Extended temperature crystals are available at a much higher cost.
© 2009 Microchip Technology Inc.
DS39932C-page 471
PIC18F46J11 FAMILY
28.2
DC Characteristics: Power-Down and Supply Current
PIC18F46J50 Family (Industrial) (Continued)
PIC18LFXXJ11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18FXXJ11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
D022
(ΔIWDT)
D022B
(ΔIHLVD)
D025
(ΔIOSCB)
Note 1:
2:
3:
Device
Typ
Max
Units
Module Differential Currents (ΔIWDT, ΔIOSCB, ΔIAD)
8
μA
-40°C
Watchdog Timer 0.86
0.97
8
μA
+25°C
0.98 10.4
μA
+85°C
0.71
7
μA
-40°C
0.82
7
μA
+25°C
0.65
10
μA
+85°C
1.54 12.1
μA
-40°C
1.33 12.1
μA
+25°C
1.16 13.6
μA
+85°C
8
μA
-40°C
High/Low-Voltage Detect 3.9
4.7
8
μA
+25°C
5.4
9
μA
+85°C
2.7
6
μA
-40°C
3.2
6
μA
+25°C
3.6
8
μA
+85°C
3.5
9
μA
-40°C
4.1
9
μA
+25°C
4.5
12
μA
+85°C
Conditions
VDD = 2.5V,
VDDCORE = 2.5V
PIC18LFXXJ11
VDD = 2.15V,
VDDCORE = 10 μF
PIC18FXXJ11
VDD = 3.3V,
VDDCORE = 10 μF
PIC18FXXJ11
VDD = 2.5V,
VDDCORE = 2.5V
PIC18LFXXJ11
VDD = 2.15V,
VDDCORE = 10 μF
PIC18FXXJ11
VDD = 3.3V,
VDDCORE = 10 μF
PIC18FXXJ11
Real-Time Clock/Calendar 0.67
4.0
μA
-40°C
4.5
μA
+25°C
with Low-Power 0.83
VDD = 2.15V,
VDDCORE = 10 μF
4.5
μA
+60°C
Timer1 Oscillator 0.95
1.10
4.5
μA
+85°C
0.75
4.5
μA
-40°C
PIC18FXXJ11
VDD = 2.5V,
0.92
5.0
μA
+25°C
32.768 kHz, T1OSCEN = 1,
DDCORE
=
10
μF
V
1.04
5.0
μA
+60°C
LPT1OSC = 0
1.21
5.0
μA
+85°C
0.94
6.5
μA
-40°C
VDD = 3.3V,
1.11
6.5
μA
+25°C
VDDCORE = 10 μF
1.24
8.0
μA
+60°C
1.43
8.0
μA
+85°C
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature,
also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The
test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS;
MCLR = VDD; WDT disabled unless otherwise specified.
Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to
+70°C. Extended temperature crystals are available at a much higher cost.
DS39932C-page 472
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
28.2
DC Characteristics: Power-Down and Supply Current
PIC18F46J50 Family (Industrial) (Continued)
PIC18LFXXJ11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18FXXJ11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
D026
(ΔIAD)
Note 1:
2:
3:
Device
Typ
Max
Units
Conditions
A/D Converter 3.00
10
μA
-40°C
PIC18LFXXJ11
VDD = 2.5V,
3.00
10
μA
+25°C
A/D on, not converting
VDDCORE = 2.5V
3.00
10
μA
+85°C
3.00
10
μA
-40°C
VDD = 2.15V,
3.00
10
μA
+25°C
VDDCORE = 10 μF
PIC18FXXJ11
3.00
10
μA
+85°C
A/D on, not converting
3.20
11
μA
-40°C
VDD = 3.3V,
3.20
11
μA
+25°C
VDDCORE = 10 μF
3.20
11
μA
+85°C
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature,
also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The
test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS;
MCLR = VDD; WDT disabled unless otherwise specified.
Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to
+70°C. Extended temperature crystals are available at a much higher cost.
© 2009 Microchip Technology Inc.
DS39932C-page 473
PIC18F46J11 FAMILY
28.3
DC Characteristics:
PIC18F46J50 Family (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
Symbol
No.
VIL
Characteristic
Min
Max
Units
VSS
0.15 VDD
V
—
0.8
V
Conditions
Input Low Voltage
All I/O ports:
D030
with TTL Buffer
D030A
3.3V ≤ VDD ≤ 3.6V
VSS
0.2 VDD
V
D032
MCLR
VSS
0.2 VDD
V
D033
OSC1
VSS
0.3 VDD
V
HS, HSPLL modes
D033A
OSC1
VSS
0.2 VDD
V
EC, ECPLL modes
D034
T1CKI
VSS
0.2 VDD
V
0.25 VDD + 0.8V
VDD
V
VDD < 3.3V
2.0
VDD
V
3.3V ≤ VDD ≤ 3.6V
0.8 VDD
VDD
V
0.25 VDD + 0.8V
5.5
V
VDD < 3.3V
2.0
5.5
V
3.3V ≤ VDD ≤ 3.6V
D031
with Schmitt Trigger Buffer
VIH
Input High Voltage
I/O Ports with non 5.5V
Tolerance:(4)
D040
with TTL Buffer
D040A
D041
with Schmitt Trigger Buffer
I/O Ports with 5.5V Tolerance:(4)
Dxxx
with TTL Buffer
DxxxA
Dxxx
0.8 VDD
5.5
V
D042
MCLR
with Schmitt Trigger Buffer
0.8 VDD
5.5
V
D043
OSC1
0.7 VDD
VDD
V
HS, HSPLL modes
D043A
OSC1
0.8 VDD
VDD
V
EC, ECPLL modes
D044
T1CKI
1.6
VDD
V
IIL
Input Leakage
Current(1,2)
D060
I/O Ports with non 5.5V
Tolerance:(4)
—
±0.2
μA
VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
D060A
I/O Ports with 5.5V Tolerance:(4)
—
±0.2
μA
3.3V ≤ VPIN ≤ 5.5V,
Pin at high-impedance
D061
MCLR
—
±0.2
μA
Vss ≤ VPIN ≤ VDD
D063
OSC1
—
±0.2
μA
Vss ≤ VPIN ≤ VDD
80
400
μA
VDD = 3.3V, VPIN = VSS
D070
Note 1:
2:
3:
4:
IPU
Weak Pull-up Current
IPURB
PORTB, PORTD(3) and
PORTE(3) Weak Pull-up Current
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
Only available in 44-pin devices.
Refer to Table 9-2 for the pins that have corresponding tolerance limits.
DS39932C-page 474
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
28.3
DC Characteristics:
PIC18F46J50 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
Symbol
No.
VOL
D080
Characteristic
Min
Max
Units
Conditions
PORTA (Except RA6),
PORTD, PORTE
—
0.4
V
IOL = 2 mA, VDD = 3.3V,
-40°C to +85°C
PORTB, PORTC, RA6
—
0.4
V
IOL = 8.5 mA, VDD = 3.3V,
-40°C to +85°C
2.4
—
V
2.4
—
V
IOH = -2, VDD = 3.3V,
-40°C to +85°C
IOH = -6 mA, VDD = 3.3V,
-40°C to +85°C
Output Low Voltage
I/O Ports:
VOH
D090
Output High Voltage
I/O Ports:
PORTA (Except RA6),
PORTD, PORTE
PORTB, PORTC, RA6
Capacitive Loading Specs
on Output Pins
D101
CIO
All I/O Pins and OSC2
—
50
pF
To meet the AC Timing
Specifications
D102
CB
SCLx, SDAx
—
400
pF
I2C™ Specification
Note 1:
2:
3:
4:
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
Only available in 44-pin devices.
Refer to Table 9-2 for the pins that have corresponding tolerance limits.
© 2009 Microchip Technology Inc.
DS39932C-page 475
PIC18F46J11 FAMILY
TABLE 28-1:
MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Ultra Low-Power Wake-up Current
—
60
—
nA
—
—
E/W
D100
IULP
D130
EP
Cell Endurance
10K
D131
VPR
VDDcore for Read
VMIN
—
2.75
V
D132B VPEW VDDCORE for Self-Timed Erase or
Write
2.25
—
2.75
V
Conditions
Net of I/O leakage and current
sink at 1.6V on pin,
VDD = 3.3V
See Application Note AN879,
“Using the Microchip Ultra
Low-Power Wake-up Module”
(DS00879)
Program Flash Memory
D133A TIW
Self-Timed Write Cycle Time
—
2.8
—
ms
D133B TIE
Self-Timed Block Erase Cycle Time
—
33.0
—
ms
TRETD Characteristic Retention
20
—
—
Year
IDDP
—
3
—
mA
D134
D135
Supply Current during Programming
-40°C to +85°C
VMIN = Minimum operating voltage
64 bytes
Provided no other specifications are
violated
† Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
TABLE 28-2:
COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Min
Typ
Max
Units
mV
D300
VIOFF
Input Offset Voltage
—
±5
±25
D301
VICM
Input Common Mode Voltage
0
—
VDD
V
VIRV
Internal Reference Voltage
0.57
0.60
0.63
V
D302
CMRR
Common Mode Rejection Ratio
55
—
—
dB
300
TRESP
Response Time(1)
—
150
400
ns
301
TMC2OV Comparator Mode Change to Output Valid
—
—
10
μs
Note 1:
Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD.
TABLE 28-3:
CTMU CURRENT SOURCE SPECIFICATIONS
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for Industrial
DC CHARACTERISTICS
Param
No.
Note 1:
Comments
Sym
Characteristic
Min
Typ(1)
Max
Units
Conditions
IOUT1
CTMU Current Source, Base Range
—
550
—
nA
CTMUICON<1:0> = 01
IOUT2
CTMU Current Source, 10x Range
—
5.5
—
μA
CTMUICON<1:0> = 10
IOUT3
CTMU Current Source, 100x Range
—
55
—
μA
CTMUICON<1:0> = 11
Nominal value at center point of current trim range (CTMUICON<7:2> = 000000).
DS39932C-page 476
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 28-4:
VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Min
Typ
Max
Units
D310
VRES
Resolution
VDD/24
—
VDD/32
LSb
D311
VRAA
Absolute Accuracy
—
—
1/2
LSb
D312
VRUR
Unit Resistor Value (R)
—
2k
—
Ω
310
TSET
Settling Time(1)
—
—
10
μs
Note 1:
Comments
Settling time measured while CVRR = 1 and CVR<3:0> bits transition from ‘0000’ to ‘1111’.
TABLE 28-5:
INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Min
Typ
Max
VRGOUT Regulator Output Voltage
2.35
2.5
5.4
10
CEFC
Note 1:
External Filter Capacitor Value(1)
Units
Comments
2.7
V
Regulator enabled, VDD = 3.0V
18
μF
ESR < 3Ω recommended
ESR < 5Ω required
CEFC applies for PIC18F devices in the family. For PIC18LF devices in the family, there is no specific minimum or maximum capacitance for VDDCORE, although proper supply rail bypassing should still be used.
© 2009 Microchip Technology Inc.
DS39932C-page 477
PIC18F46J11 FAMILY
FIGURE 28-3:
HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
For VDIRMAG = 1:
VDD
VHLVD
(LVDIF set by hardware)
(LVDIF can be
cleared in software)
VHLVD
For VDIRMAG = 0:
VDD
LVDIF
TABLE 28-6:
HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
Symbol
No.
D420
Characteristic
Min
Typ
Max
Units
HLVD Voltage on VDD HLVDL<3:0> = 1000
Transition High-toHLVDL<3:0> = 1001
Low
HLVDL<3:0> = 1010
2.33
2.45
2.57
V
2.47
2.60
2.73
V
2.66
2.80
2.94
V
HLVDL<3:0> = 1011
2.76
2.90
3.05
V
HLVDL<3:0> = 1100
2.85
3.00
3.15
V
HLVDL<3:0> = 1101
2.97
3.13
3.29
V
HLVDL<3:0> = 1110
3.23
3.40
3.57
V
D421
TIRVST
Time for Internal Reference Voltage to
become Stable
—
20
—
μs
D422
TLVD
High/Low-Voltage Detect Pulse Width
200
—
—
μs
DS39932C-page 478
Conditions
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
28.4
28.4.1
AC (Timing) Characteristics
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKO
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (High-impedance)
L
Low
I2C only
AA
output access
BUF
Bus free
TCC:ST (I2C specifications only)
CC
HD
Hold
ST
DAT
DATA input hold
STA
Start condition
© 2009 Microchip Technology Inc.
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T13CKI
WR
P
R
V
Z
Period
Rise
Valid
High-impedance
High
Low
High
Low
SU
Setup
STO
Stop condition
DS39932C-page 479
PIC18F46J11 FAMILY
28.4.2
TIMING CONDITIONS
The temperature and voltages specified in Table 28-7
apply to all timing specifications unless otherwise
noted. Figure 28-4 specifies the load conditions for the
timing specifications.
TABLE 28-7:
TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
AC CHARACTERISTICS
FIGURE 28-4:
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Operating voltage VDD range as described in Section 28.1 and Section 28.3.
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 2
Load Condition 1
VDD/2
RL
CL
Pin
VSS
CL
Pin
RL = 464Ω
VSS
28.4.3
CL = 50 pF
for all pins except OSC2/CLKO/RA6
and including D and E outputs as ports
CL = 15 pF
for OSC2/CLKO/RA6
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 28-5:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
1
3
3
4
4
2
CLKO
DS39932C-page 480
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 28-8:
Param.
No.
1A
EXTERNAL CLOCK TIMING REQUIREMENTS
Symbol
FOSC
1
TOSC
Characteristic
Min
Max
Units
External CLKI Frequency(1)
DC
48
MHz
EC Oscillator mode
MHz
HS Oscillator mode
ns
EC Oscillator mode
ns
HS Oscillator mode
4
12
Oscillator Frequency(1)
4
16
4
12
External CLKI Period(1)
20.8
—
Oscillator Period(1)
83.3
—
62.5
250
Conditions
ECPLL Oscillator mode
HSPLL Oscillator mode
ECPLL Oscillator mode
83.3
250
2
TCY
Instruction Cycle Time(1)
83.3
DC
ns
TCY = 4/FOSC, Industrial
3
TOSL,
TOSH
External Clock in (OSC1)
High or Low Time
10
—
ns
EC Oscillator mode
4
TOSR,
TOSF
External Clock in (OSC1)
Rise or Fall Time
—
7.5
ns
EC Oscillator mode
Note 1:
Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
TABLE 28-9:
Param
No.
PLL CLOCK TIMING SPECIFICATIONS
Sym
Characteristic
FPLLIN PLL Input Frequency Range
FPLLO PLL Output Frequency (4x FPLLIN)
F10
F11
F12
HSPLL Oscillator mode
trc
PLL Start-up Time (lock time)
Min
Typ†
Max
Units
4
16
—
—
12
48
MHz
MHz
—
—
2
ms
Conditions
† Data in “Typ” column is at 3.3V, 25°C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
TABLE 28-10: INTERNAL RC ACCURACY (INTOSC AND INTRC SOURCES)
Param
No.
Device
Min
Typ
Max
Units
Conditions
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, 31 kHz(1)
All Devices
-1
+/-0.15
+1
%
0°C to +85°C
VDD = 2.0-3.3V
-1
+/-0.25
+1
%
-40°C to +85°C
VDD = 2.0-3.6V,
VDDCORE = 2.0-2.7V
42.2
kHz
-40°C to +85°C
VDD = 2.0-3.6V,
VDDCORE = 2.0-2.7V
INTRC Accuracy @ Freq = 31 kHz(1)
All Devices
Note 1:
20.3
—
The accuracy specification of the 31 kHz clock is determined by which source is providing it at a given time.
When INTSRC (OSCTUNE<7>) is ‘1’, use the INTOSC accuracy specification. When INTSRC is ‘0’, use
the INTRC accuracy specification.
© 2009 Microchip Technology Inc.
DS39932C-page 481
PIC18F46J11 FAMILY
FIGURE 28-6:
CLKO AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKO
13
14
19
12
18
16
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
Note:
Refer to Figure 28-4 for load conditions.
TABLE 28-11: CLKO AND I/O TIMING REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ
Max
—
75
200
10
TOSH2CKL OSC1 ↑ to CLKO ↓
11
TOSH2CKH OSC1 ↑ to CLKO ↑
—
75
12
TCKR
CLKO Rise Time
—
15
13
TCKF
CLKO Fall Time
—
14
TCKL2IOV
CLKO ↓ to Port Out Valid
—
15
TIOV2CKH Port In Valid before CLKO ↑
16
TCKH2IOI
17
TOSH2IOV OSC1 ↑ (Q1 cycle) to Port Out Valid
18
TOSH2IOI
19
20
Port In Hold after CLKO ↑
Units Conditions
ns
(Note 1)
200
ns
(Note 1)
30
ns
(Note 1)
15
30
ns
(Note 1)
—
0.5 TCY + 20
ns
0.25 TCY + 25
—
—
ns
0
—
—
ns
—
50
150
ns
100
—
—
ns
TIOV2OSH Port Input Valid to OSC1 ↑
(I/O in setup time)
0
—
—
ns
TIOR
—
—
6
ns
OSC1 ↑ (Q2 cycle) to Port Input Invalid
(I/O in hold time)
Port Output Rise Time
21
TIOF
Port Output Fall Time
—
—
5
ns
22†
TINP
INTx pin High or Low Time
TCY
—
—
ns
23†
TRBP
RB7:RB4 Change INTx High or Low
Time
TCY
—
—
ns
† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in EC mode, where CLKO output is 4 x TOSC.
DS39932C-page 482
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
FIGURE 28-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
PWRT
Time-out
33
32
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pins
Note:
Refer to Figure 28-4 for load conditions.
TABLE 28-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
Symbol
No.
Characteristic
Min
Typ
Max
Units
Conditions
2
—
—
μs
—
2.8
4.0
5.3
ms
—
1024 TOSC
—
1024 TOSC
—
Power-up Timer Period
—
1.0
—
ms
TIOZ
I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—
—
3 TCY + 2
μs
36
TIRVST
Time for Internal Reference
Voltage to become Stable
—
20
—
μs
—
37
TLVD
High/Low-Voltage Detect
Pulse Width
—
200
—
μs
—
38
TCSD
CPU Start-up Time
—
200
—
μs
30
TMCL
MCLR Pulse-Width (low)
31
TWDT
Watchdog Timer Time-out Period
(no postscaler)
32
TOST
Oscillator Start-up Timer Period
33
TPWRT
34
Note 1:
2:
TOSC = OSC1 period
—
(Note 1)
(Note 2)
The maximum TIOZ is the lesser of (3 TCY + 2 μs) or 700 μs.
MCLR rising edge to code execution, assuming TPWRT (and TOST if applicable) has already expired.
© 2009 Microchip Technology Inc.
DS39932C-page 483
PIC18F46J11 FAMILY
FIGURE 28-8:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note:
Refer to Figure 28-4 for load conditions.
TABLE 28-13: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Symbol
Characteristic
40
TT0H
T0CKI High Pulse Width
No prescaler
41
TT0L
T0CKI Low Pulse Width
No prescaler
42
TT0P
T0CKI Period
No prescaler
With prescaler
With prescaler
With prescaler
45
46
47
TT1H
TT1L
T1CKI/T3CKI Synchronous, no prescaler
High Time
Synchronous, with prescaler
Units
0.5 TCY + 20
—
ns
10
—
ns
0.5 TCY + 20
—
ns
10
—
ns
TCY + 10
—
ns
Greater of:
20 ns or
(TCY + 40)/N
—
ns
0.5 TCY + 20
—
ns
10
—
ns
Asynchronous
30
—
ns
0.5 TCY + 5
—
ns
10
—
ns
Asynchronous
30
—
ns
Greater of:
20 ns or
(TCY + 40)/N
—
ns
TT1P
T1CKI/T3CKI Synchronous
Input Period
FT 1
T1CKI Input Frequency Range(1)
TCKE2TMRI Delay from External T1CKI Clock Edge to
Timer Increment
Note 1:
Max
T1CKI/T3CKI Synchronous, no prescaler
Low Time
Synchronous, with prescaler
Asynchronous
48
Min
83
—
ns
DC
12
MHz
2 TOSC
7 TOSC
—
Conditions
N = prescale
value
(1, 2, 4,..., 256)
N = prescale
value
(1, 2, 4, 8)
The Timer1 oscillator is designed to drive 32.768 kHz crystals. When T1CKI is used as a digital input,
frequencies up to 12 MHz are supported.
DS39932C-page 484
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
FIGURE 28-9:
ENHANCED CAPTURE/COMPARE/PWM TIMINGS
ECCPx
(Capture Mode)
50
51
52
ECCPx
(Compare or PWM Mode)
53
Note:
54
Refer to Figure 28-4 for load conditions.
TABLE 28-14: ENHANCED CAPTURE/COMPARE/PWM REQUIREMENTS
Param
Symbol
No.
50
TCCL
Characteristic
ECCPx Input Low Time
No prescaler
With prescaler
51
TCCH
ECCPx Input High Time
No prescaler
With prescaler
Min
Max
Units
0.5 TCY + 20
—
ns
10
—
ns
0.5 TCY + 20
—
ns
10
—
ns
3 TCY + 40
N
—
ns
TCCP
ECCPx Input Period
53
TCCR
ECCPx Output Fall Time
—
25
ns
54
TCCF
ECCPx Output Fall Time
—
25
ns
52
© 2009 Microchip Technology Inc.
Conditions
N = prescale
value (1, 4 or 16)
DS39932C-page 485
PIC18F46J11 FAMILY
FIGURE 28-10:
PARALLEL MASTER PORT READ TIMING DIAGRAM
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
System
Clock
PMA<13:18>
PMD<7:0>
Address
Address<7:0>
Data
PM6
PM2
PM7
PM3
PMRD
PM5
PMWR
PMALL/PMALH
PM1
PMCS<2:1>
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C unless otherwise stated.
TABLE 28-15: PARALLEL MASTER PORT READ TIMING REQUIREMENTS
Param.
No
Symbol
Characteristics
Min
Typ
Max
Units
PM1
PMALL/PMALH Pulse Width
—
0.5 TCY
—
ns
PM2
Address Out Valid to PMALL/PMALH
Invalid (address setup time)
—
0.75 TCY
—
ns
PM3
PMALL/PMALH Invalid to Address Out
Invalid (address hold time)
—
0.25 TCY
—
ns
PM5
PMRD Pulse Width
—
0.5 TCY
—
ns
PM6
PMRD or PMENB Active to Data In Valid
(data setup time)
—
—
—
ns
PM7
PMRD or PMENB Inactive to Data In Invalid
(data hold time)
—
—
—
ns
DS39932C-page 486
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
FIGURE 28-11:
PARALLEL MASTER PORT WRITE TIMING DIAGRAM
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
System
Clock
PMA<13:18>
Address
Address<7:0>
PMD<7:0>
Data
PM12
PM13
PMRD
PMWR
PM11
PMALL/
PMALH
PMCS<2:1>
PM16
Note:
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C unless otherwise stated.
TABLE 28-16: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS
Param.
No
Symbol
Characteristics
Min
Typ
Max
Units
PM11
PMWR Pulse Width
—
0.5 TCY
—
ns
PM12
Data Out Valid before PMWR or PMENB
goes Inactive (data setup time)
—
—
—
ns
PM13
PMWR or PMEMB Invalid to Data Out
Invalid (data hold time)
—
—
—
ns
PM16
PMCS Pulse Width
TCY – 5
—
—
ns
© 2009 Microchip Technology Inc.
DS39932C-page 487
PIC18F46J11 FAMILY
FIGURE 28-12:
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SSx
SCKx
(CKP = 0)
78
79
79
78
SCKx
(CKP = 1)
bit 6 - - - - - - 1
MSb
SDOx
LSb
75, 76
SDIx
MSb In
bit 6 - - - - 1
LSb In
74
73
Note:
Refer to Figure 28-4 for load conditions.
TABLE 28-17: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
73
Symbol
TDIV2SCH,
TDIV2SCL
Characteristic
Min
Setup Time of SDIx Data Input to SCKx Edge
35
—
ns
100
—
ns
1.5 TCY + 40
—
ns
30
—
ns
83
—
ns
73A
TB2B
Last Clock Edge of Byte 1 to the 1st Clock
Edge of Byte 2
74
TSCH2DIL,
TSCL2DIL
Hold Time of SDIx Data Input to SCKx Edge
Max Units
Conditions
VDD = 3.3V,
VDDCORE = 2.5V
VDD = 2.15V,
VDDCORE = 2.15V
VDD = 3.3V,
VDDCORE = 2.5V
VDD = 2.15V
75
TDOR
SDOx Data Output Rise Time
—
25
ns
PORTB or PORTC
76
TDOF
SDOx Data Output Fall Time
—
25
ns
PORTB or PORTC
78
TSCR
SCKx Output Rise Time (Master mode)
—
25
ns
PORTB or PORTC
79
TSCF
SCKx Output Fall Time (Master mode)
—
25
ns
PORTB or PORTC
DS39932C-page 488
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
FIGURE 28-13:
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SSx
81
SCKx
(CKP = 0)
79
73
SCKx
(CKP = 1)
78
MSb
SDOx
bit 6 - - - - - - 1
LSb
bit 6 - - - - 1
LSb In
75, 76
SDIx
MSb In
74
Note:
Refer to Figure 28-4 for load conditions.
TABLE 28-18: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
73
74
Symbol
TDIV2SCH,
TDIV2SCL
TSCH2DIL,
TSCL2DIL
Characteristic
Setup Time of SDIx Data Input to SCKx Edge
Hold Time of SDIx Data Input to SCKx Edge
Min
Max Units
35
—
ns
100
—
ns
30
—
ns
83
—
ns
Conditions
VDD = 3.3V,
VDDCORE = 2.5V
VDD = 2.15V,
VDDCORE = 2.15V
VDD = 3.3V,
VDDCORE = 2.5V
VDD = 2.15V
75
TDOR
SDOx Data Output Rise Time
—
25
ns
PORTB or PORTC
76
TDOF
SDOx Data Output Fall Time
—
25
ns
PORTB or PORTC
78
TSCR
SCKx Output Rise Time (Master mode)
—
25
ns
PORTB or PORTC
79
TSCF
SCKx Output Fall Time (Master mode)
—
25
ns
PORTB or PORTC
81
TDOV2SCH, SDOx Data Output Setup to SCKx Edge
TDOV2SCL
TCY
—
ns
© 2009 Microchip Technology Inc.
DS39932C-page 489
PIC18F46J11 FAMILY
FIGURE 28-14:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SSx
70
SCKx
(CKP = 0)
83
71
72
SCKx
(CKP = 1)
80
MSb
SDOx
LSb
bit 6 - - - - - - 1
75, 76
MSb In
SDIx
SDI
77
bit 6 - - - - 1
LSb In
74
73
Note:
Refer to Figure 28-4 for load conditions.
TABLE 28-19: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units
Conditions
70
TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input
TSSL2SCL
70A
TSSL2WB
SSx ↓ to Write to SSPxBUF
71
TSCH
SCKx Input High Time
(Slave mode)
Continuous
1.25 TCY + 30
—
ns
Single byte
40
—
ns
SCKx Input Low Time
(Slave mode)
Continuous
1.25 TCY + 30
—
ns
Single byte
40
—
ns
25
—
ns
1.5 TCY + 40
—
ns
(Note 2)
35
—
ns
71A
72
TSCL
72A
73
TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge
TDIV2SCL
73A
TB2B
74
TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
75
TDOR
SDOx Data Output Rise Time
76
TDOF
77
80
TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
83
Note 1:
2:
Last Clock Edge of Byte 1 to the First Clock Edge of
Byte 2
3 TCY
—
ns
3 TCY
—
ns
(Note 1)
(Note 1)
100
—
ns
VDD = 3.3V,
VDDCORE = 2.5V
VDD = 2.15V
—
25
ns
PORTB or PORTC
SDOx Data Output Fall Time
—
25
ns
PORTB or PORTC
TSSH2DOZ SSx ↑ to SDOx Output High-Impedance
10
70
ns
—
50
ns
100
ns
—
ns
TSCH2SSH, SSx ↑ after SCKx Edge
TSCL2SSH
1.5 TCY + 40
VDD = 3.3V,
VDDCORE = 2.5V
VDD = 2.15V
Requires the use of Parameter #73A.
Only if Parameter #71A and #72A are used.
DS39932C-page 490
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
FIGURE 28-15:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SSx
SCKx
(CKP = 0)
70
83
71
72
73
SCKx
(CKP = 1)
80
MSb
SDOx
bit 6 - - - - - - 1
LSb
75, 76
SDIx
SDI
MSb In
77
bit 6 - - - - 1
LSb In
74
Note:
Refer to Figure 28-4 for load conditions.
TABLE 28-20: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max
Units
3 TCY
—
ns
Continuous
Single byte
SCKx Input Low Time
Continuous
(Slave mode)
Single byte
Setup Time of SDIx Data Input to SCKx Edge
3 TCY
1.25 TCY + 30
40
1.25 TCY + 30
40
25
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2
Hold Time of SDIx Data Input to SCKx Edge
1.5 TCY + 40
35
—
—
ns
ns
—
25
25
ns
ns
ns
70
TSSL2SCH,
TSSL2SCL
SSx ↓ to SCKx ↓ or SCKx ↑ Input
70A
TSSL2WB
TSCH
SSx ↓ to Write to SSPxBUF
SCKx Input High Time
(Slave mode)
71
71A
72
72A
73
73A
74
TSCL
TDIV2SCH,
TDIV2SCL
T B 2B
TSCH2DIL,
TSCL2DIL
75
76
TDOR
TDOF
SDOx Data Output Rise Time
SDOx Data Output Fall Time
100
—
—
77
78
79
TSSH2DOZ
TSCR
TSCF
80
TSCH2DOV,
TSCL2DOV
SSx ↑ to SDOx Output High-Impedance
SCKx Output Rise Time (Master mode)
SCKx Output Fall Time (Master mode)
SDOx Data Output Valid after SCKx Edge
10
—
—
—
70
25
25
50
ns
ns
ns
ns
81
TDOV2SCH, SDOx Data Output Setup to SCKx Edge
TDOV2SCL
—
TCY
100
—
ns
ns
82
TSSL2DOV
—
50
ns
1.5 TCY + 40
—
ns
SDOx Data Output Valid after SSx ↓ Edge
TSCH2SSH, SSx ↑ after SCKx Edge
TSCL2SSH
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
83
© 2009 Microchip Technology Inc.
Conditions
(Note 1)
(Note 1)
(Note 2)
VDD = 3.3V,
VDDCORE = 2.5V
VDD = 2.15V
VDD = 3.3V,
VDDCORE = 2.5V
VDD = 2.15V
DS39932C-page 491
PIC18F46J11 FAMILY
I2C™ BUS START/STOP BITS TIMING
FIGURE 28-16:
SCLx
91
93
90
92
SDAx
Stop
Condition
Start
Condition
Note:
Refer to Figure 28-4 for load conditions.
TABLE 28-21: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param.
Symbol
No.
Characteristic
90
TSU:STA
Start Condition
91
THD:STA
92
TSU:STO
93
THD:STO Stop Condition
100 kHz mode
Min
Max
Units
Conditions
4700
—
ns
Only relevant for Repeated
Start condition
ns
After this period, the first
clock pulse is generated
Setup Time
400 kHz mode
600
—
Start Condition
100 kHz mode
4000
—
Hold Time
400 kHz mode
600
—
Stop Condition
100 kHz mode
4700
—
Setup Time
Hold Time
400 kHz mode
600
—
100 kHz mode
4000
—
400 kHz mode
600
—
ns
ns
I2C™ BUS DATA TIMING
FIGURE 28-17:
103
102
100
101
SCLx
90
106
107
91
92
SDAx
In
110
109
109
SDAx
Out
Note:
Refer to Figure 28-4 for load conditions.
DS39932C-page 492
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 28-22: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
100
Symbol
THIGH
101
TLOW
102
TR
Characteristic
Clock High Time
Clock Low Time
Min
Max
Units
100 kHz mode
4.0
—
μs
400 kHz mode
0.6
—
μs
MSSP modules
1.5 TCY
—
100 kHz mode
4.7
—
μs
μs
400 kHz mode
1.3
—
MSSP modules
1.5 TCY
—
—
1000
ns
20 + 0.1 CB
300
ns
SDAx and SCLx Rise Time 100 kHz mode
400 kHz mode
103
TF
SDAx and SCLx Fall Time 100 kHz mode
TSU:STA
THD:STA
91
THD:DAT
106
TSU:DAT
107
TSU:STO
92
109
TAA
110
TBUF
D102
CB
Note 1:
2:
CB is specified to be from
10 to 400 pF
—
300
ns
20 + 0.1 CB
300
ns
CB is specified to be from
10 to 400 pF
Start Condition Setup Time 100 kHz mode
4.7
—
μs
400 kHz mode
0.6
—
μs
Only relevant for Repeated
Start condition
400 kHz mode
90
Conditions
Start Condition Hold Time
Data Input Hold Time
Data Input Setup Time
100 kHz mode
4.0
—
μs
400 kHz mode
0.6
—
μs
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
μs
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
Stop Condition Setup Time 100 kHz mode
4.7
—
μs
400 kHz mode
0.6
—
μs
100 kHz mode
—
3500
ns
400 kHz mode
—
—
ns
Output Valid from Clock
Bus Free Time
Bus Capacitive Loading
100 kHz mode
4.7
—
μs
400 kHz mode
1.3
—
μs
—
400
pF
After this period, the first clock
pulse is generated
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission can
start
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.
A Fast mode I2C™ bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT ≥ 250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal.
If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, TR
max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCLx line is
released.
© 2009 Microchip Technology Inc.
DS39932C-page 493
PIC18F46J11 FAMILY
FIGURE 28-18:
MSSPx I2C™ BUS START/STOP BITS TIMING WAVEFORMS
SCLx
93
91
90
92
SDAx
Stop
Condition
Start
Condition
Note:
Refer to Figure 28-4 for load conditions.
TABLE 28-23: MSSPx I2C™ BUS START/STOP BITS REQUIREMENTS
Param.
Symbol
No.
90
TSU:STA
Characteristic
Start Condition
100 kHz mode
Setup Time
91
THD:STA Start Condition
Hold Time
92
TSU:STO Stop Condition
Setup Time
93
THD:STO Stop Condition
Hold Time
Note 1:
Min
Max
Units
2(TOSC)(BRG + 1)
—
ns
Only relevant for
Repeated Start
condition
ns
After this period, the
first clock pulse is
generated
400 kHz mode
2(TOSC)(BRG + 1)
—
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
100 kHz mode
2(TOSC)(BRG + 1)
—
400 kHz mode
2(TOSC)(BRG + 1)
—
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
100 kHz mode
2(TOSC)(BRG + 1)
—
400 kHz mode
2(TOSC)(BRG + 1)
—
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
100 kHz mode
2(TOSC)(BRG + 1)
—
400 kHz mode
2(TOSC)(BRG + 1)
—
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
Conditions
ns
—
ns
—
Maximum pin capacitance = 10 pF for all I2C™ pins.
FIGURE 28-19:
MSSPx I2C™ BUS DATA TIMING
103
102
100
101
SCLx
90
106
91
107
92
SDAx
In
109
109
110
SDAx
Out
Note:
DS39932C-page 494
Refer to Figure 28-4 for load conditions.
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 28-24: MSSPx I2C™ BUS DATA REQUIREMENTS
Param.
Symbol
No.
100
101
THIGH
TLOW
Characteristic
Min
Max
Units
Clock High Time 100 kHz mode
2(TOSC)(BRG + 1)
—
ms
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
ms
Clock Low Time 100 kHz mode
2(TOSC)(BRG + 1)
—
ms
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
(1)
2(TOSC)(BRG + 1)
—
ms
—
1000
ns
20 + 0.1 CB
300
ns
—
300
ns
1 MHz mode
102
TR
SDAx and SCLx 100 kHz mode
Rise Time
400 kHz mode
1 MHz mode(1)
103
90
91
106
107
92
109
110
D102
Note 1:
2:
TF
TSU:STA
SDAx and SCLx 100 kHz mode
Fall Time
400 kHz mode
Start Condition
Setup Time
THD:STA Start Condition
Hold Time
THD:DAT Data Input
Hold Time
TSU:DAT
Data Input
Setup Time
TSU:STO Stop Condition
Setup Time
TAA
TBUF
CB
Output Valid
from Clock
Bus Free Time
—
300
ns
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
100
ns
100 kHz mode
2(TOSC)(BRG + 1)
—
ms
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
ms
100 kHz mode
2(TOSC)(BRG + 1)
—
ms
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
ms
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
ms
1 MHz mode(1)
TBD
—
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode(1)
TBD
—
ns
100 kHz mode
2(TOSC)(BRG + 1)
—
ms
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
ms
100 kHz mode
—
3500
ns
400 kHz mode
—
1000
ns
(1)
1 MHz mode
—
—
ns
100 kHz mode
4.7
—
ms
400 kHz mode
1.3
—
ms
1 MHz mode(1)
TBD
—
ms
—
400
pF
Bus Capacitive Loading
Conditions
CB is specified to be
from 10 to 400 pF
CB is specified to be
from 10 to 400 pF
Only relevant for
Repeated Start condition
After this period, the first
clock pulse is generated
(Note 2)
Time the bus must be
free before a new
transmission can start
Maximum pin capacitance = 10 pF for all I2C™ pins.
A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter
#107 ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output
the next data bit to the SDAx line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz
mode), before the SCLx line is released.
© 2009 Microchip Technology Inc.
DS39932C-page 495
PIC18F46J11 FAMILY
FIGURE 28-20:
EUSARTx SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TXx/CKx
pin
121
121
RXx/DTx
pin
120
Note:
122
Refer to Figure 28-4 for load conditions.
TABLE 28-25: EUSARTx SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Max
Units
120
TCKH2DTV Sync XMIT (Master and Slave)
Clock High to Data Out Valid
—
40
ns
121
TCKRF
Clock Out Rise Time and Fall Time (Master mode)
—
20
ns
122
TDTRF
Data Out Rise Time and Fall Time
—
20
ns
FIGURE 28-21:
Conditions
EUSARTx SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TXx/CKx
pin
125
RXx/DTx
pin
126
Note:
Refer to Figure 28-4 for load conditions.
TABLE 28-26: EUSARTx SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
No.
Symbol
Characteristic
125
TDTV2CKL Sync RCV (Master and Slave)
Data Hold before CKx ↓ (DTx hold time)
126
TCKL2DTL
DS39932C-page 496
Data Hold after CKx ↓ (DTx hold time)
Min
Max
Units
10
—
ns
15
—
ns
Conditions
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
TABLE 28-27: A/D CONVERTER CHARACTERISTICS: PIC18F46J11 FAMILY (INDUSTRIAL)
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
—
—
10
bit
Conditions
ΔVREF ≥ 3.0V
A01
NR
Resolution
A03
EIL
Integral Linearity Error
—
—
<±1
LSb ΔVREF ≥ 3.0V
A04
EDL
Differential Linearity Error
—
—
<±1
LSb ΔVREF ≥ 3.0V
A06
EOFF
Offset Error
—
—
<±3
LSb ΔVREF ≥ 3.0V
A07
EGN
Gain Error
—
—
<±3.5
LSb ΔVREF ≥ 3.0V
Guaranteed(1)
—
VSS ≤ VAIN ≤ VREF
A20
ΔVREF
Reference Voltage Range
(VREFH – VREFL)
2.0
3
—
—
—
—
V
V
VDD < 3.0V
VDD ≥ 3.0V
A21
VREFH
Reference Voltage High
VSS
—
VREFH
V
A22
VREFL
Reference Voltage Low
VSS – 0.3V
—
VDD – 3.0V
V
A25
VAIN
Analog Input Voltage
VREFL
—
VREFH
V
A30
ZAIN
Recommended Impedance of
Analog Voltage Source
—
—
2.5
kΩ
A50
IREF
VREF Input Current(2)
—
—
—
—
5
150
μA
μA
A10
Monotonicity
Note 1:
2:
During VAIN acquisition.
During A/D conversion
cycle.
The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
VREFH current is from RA3/AN3/VREF+/C1INB pin or VDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF-/CVREF/C2INB pin or VSS, whichever is selected as the VREFL source.
FIGURE 28-22:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
Q4
A/D CLK
130
132
9
A/D DATA
8
7
...
...
2
OLD_DATA
ADRES
1
0
NEW_DATA
TCY (Note 1)
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1:
2:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
© 2009 Microchip Technology Inc.
DS39932C-page 497
PIC18F46J11 FAMILY
TABLE 28-28: A/D CONVERSION REQUIREMENTS
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
130
TAD
A/D Clock Period
0.7
25.0(1)
μs
TOSC based, VREF ≥ 3.0V
131
TCNV
Conversion Time
(not including acquisition time)(2)
11
—
12
1
TAD
μs
A/D RC Mode
132
TACQ
Acquisition Time(3)
1.4
—
μs
-40°C to +85°C
135
TSWC
Switching Time from Convert → Sample
—
(Note 4)
137
TDIS
Discharge Time
0.2
—
Note 1:
2:
3:
4:
μs
The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
ADRES registers may be read on the following TCY cycle.
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
On the following cycle of the device clock.
DS39932C-page 498
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
29.0
PACKAGING INFORMATION
29.1
Package Marking Information
Example
28-Lead SPDIP
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead SSOP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC18F26J11
/SS e3
0910017
28-Lead SOIC (.300”)
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead QFN
PIC18F26J11/SO e3
0910017
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
*
Note:
PIC18F26J11
-I/SP e3
0910017
18F26J11
/ML e3
0910017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2009 Microchip Technology Inc.
DS39932C-page 499
PIC18F46J11 FAMILY
44-Lead QFN
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
44-Lead TQFP
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
DS39932C-page 500
Example
18F46J11
-I/ML e3
0910017
Example
18F46J11
-I/PT e3
0910017
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
29.2
Package Details
The following sections give the technical details of the packages.
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DS39932C-page 508
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
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© 2009 Microchip Technology Inc.
DS39932C-page 509
PIC18F46J11 FAMILY
NOTES:
DS39932C-page 510
© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
APPENDIX A:
REVISION HISTORY
APPENDIX B:
Revision A (October 2008)
DEVICE
DIFFERENCES
The differences between the devices listed in this data
sheet are shown in Table B-1,
Original data sheet for the PIC18F46J11 family of
devices.
Revision B (February 2009)
Changes to the Electrical Characteristics and minor
edits throughout text.
Revision C (October 2009)
Removed “Preliminary” marking.
TABLE B-1:
Features
DEVICE DIFFERENCES BETWEEN PIC18F46J11 FAMILY MEMBERS
PIC18F24J11
PIC18F25J11
PIC18F26J11
PIC18F44J11
PIC18F45J11
Program Memory
16K
32K
64K
16K
32K
64K
Program Memory
(Instructions)
8,192
16,384
32,768
8,192
16,384
32,768
I/O Ports (Pins)
Ports A, B, C
10-Bit ADC Module
Packages
PIC18F46J11
Ports A, B, C, D, E
10 Input Channels
13 Input Channels
28-Pin QFN, SOIC, SSOP and SPDIP (300 mil)
44-Pin QFN and TQFP
© 2009 Microchip Technology Inc.
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NOTES:
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© 2009 Microchip Technology Inc.
PIC18F46J11 FAMILY
INDEX
A
A/D ................................................................................... 345
A/D Converter Interrupt, Configuring ....................... 349
Acquisition Requirements ........................................ 350
ADCAL Bit ................................................................ 353
ADRESH Register .................................................... 348
Analog Port Pins, Configuring .................................. 351
Associated Registers ............................................... 354
Automatic Acquisition Time ...................................... 351
Calibration ................................................................ 353
Configuring the Module ............................................ 349
Conversion Clock (TAD) ........................................... 351
Conversion Requirements ....................................... 498
Conversion Status (GO/DONE Bit) .......................... 348
Conversions ............................................................. 352
Converter Characteristics ........................................ 497
Operation in Power-Managed Modes ...................... 353
Special Event Trigger (ECCPx) ............................... 352
Use of the ECCP2 Trigger ....................................... 352
Absolute Maximum Ratings ............................................. 461
AC (Timing) Characteristics ............................................. 479
Load Conditions for Device Timing Specifications ... 480
Parameter Symbology ............................................. 479
Temperature and Voltage Specifications ................. 480
Timing Conditions .................................................... 480
ACKSTAT ........................................................................ 310
ACKSTAT Status Flag ..................................................... 310
ADCAL Bit ........................................................................ 353
ADCON0 Register
GO/DONE Bit ........................................................... 348
ADDFSR .......................................................................... 450
ADDLW ............................................................................ 413
ADDULNK ........................................................................ 450
ADDWF ............................................................................ 413
ADDWFC ......................................................................... 414
ADRESL Register ............................................................ 348
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................ 414
ANDWF ............................................................................ 415
Assembler
MPASM Assembler .................................................. 458
Auto-Wake-up on Sync Break Character ......................... 334
B
Bank Select Register ......................................................... 78
Baud Rate Generator ....................................................... 306
BC .................................................................................... 415
BCF .................................................................................. 416
BF .................................................................................... 310
BF Status Flag ................................................................. 310
Block Diagrams
+5V System Hardware Interface .............................. 126
8-Bit Multiplexed Address and Data Application ...... 187
A/D ........................................................................... 348
Analog Input Model .................................................. 349
Baud Rate Generator ............................................... 307
Capture Mode Operation ......................................... 244
Comparator Analog Input Model .............................. 358
Comparator Configurations ...................................... 360
Comparator Output .................................................. 355
Comparator Voltage Reference ............................... 363
Comparator Voltage Reference Output Buffer Example
365
© 2009 Microchip Technology Inc.
CTMU ...................................................................... 373
CTMU Current Source Calibration Circuit ............... 376
CTMU Typical Connections and Internal Configuration
for Pulse Delay Generation ............................. 384
CTMU Typical Connections and Internal Configuration
for Time Measurement .................................... 383
Demultiplexed Addressing Mode ............................. 180
Device Clock .............................................................. 32
EUSART Transmit ................................................... 331
EUSARTx Receive .................................................. 333
Fail-Safe Clock Monitor ........................................... 404
Fully Multiplexed Addressing Mode ......................... 180
Generic I/O Port Operation ...................................... 125
High/Low-Voltage Detect with External Input .......... 368
Interrupt Logic .......................................................... 110
LCD Control ............................................................. 188
Legacy Parallel Slave Port ...................................... 174
MSSPx (I2C Master Mode) ...................................... 305
MSSPx (I2C Mode) .................................................. 285
MSSPx (SPI Mode) ................................................. 266
Multiplexed Addressing Application ......................... 187
On-Chip Reset Circuit ................................................ 57
Parallel EEPROM (Up to 15-Bit Address, 16-Bit Data) .
188
Parallel EEPROM (Up to 15-Bit Address, 8-Bit Data) ...
188
Parallel Master/Slave Connection Addressed Buffer 177
Parallel Master/Slave Connection Buffered ............. 176
Partially Multiplexed Addressing Application ........... 187
Partially Multiplexed Addressing Mode .................... 180
PIC18F2XJ11 (28-Pin) .............................................. 14
PIC18F4XJ11 (44-Pin) .............................................. 15
PMP Module ............................................................ 165
PWM (Enhanced) .................................................... 249
PWM Operation (Simplified) .................................... 246
Reads From Flash Program Memory ...................... 101
RTCC ....................................................................... 221
Simplified Steering ................................................... 262
Single Comparator ................................................... 358
Table Read Operation ............................................... 97
Table Write Operation ............................................... 98
Table Writes to Flash Program Memory .................. 103
Timer0 in 16-Bit Mode ............................................. 192
Timer0 in 8-Bit Mode ............................................... 192
Timer1 ..................................................................... 199
Timer2 ..................................................................... 208
Timer3 ..................................................................... 212
Timer4 ..................................................................... 220
Using the Open-Drain Output .................................. 126
Watchdog Timer ...................................................... 399
BN .................................................................................... 416
BNC ................................................................................. 417
BNN ................................................................................. 417
BNOV .............................................................................. 418
BNZ ................................................................................. 418
BOR. See Brown-out Reset.
BOV ................................................................................. 421
BRA ................................................................................. 419
Break Character (12-Bit) Transmit and Receive .............. 336
BRG. See Baud Rate Generator.
Brown-out Reset (BOR) ..................................................... 59
and On-Chip Voltage Regulator .............................. 402
Detecting ................................................................... 59
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PIC18F46J11 FAMILY
Disabling in Sleep Mode ............................................ 59
BSF .................................................................................. 419
BTFSC ............................................................................. 420
BTFSS .............................................................................. 420
BTG .................................................................................. 421
BZ ..................................................................................... 422
C
C Compilers
MPLAB C18 ............................................................. 458
MPLAB C30 ............................................................. 458
Calibration (A/D Converter) .............................................. 353
CALL ................................................................................ 422
CALLW ............................................................................. 451
Capture (ECCP Module) .................................................. 243
CCPRxH:CCPRxL Registers ................................... 243
ECCP Pin Configuration .......................................... 243
Prescaler .................................................................. 244
Software Interrupt .................................................... 243
Timer1/Timer3 Mode Selection ................................ 243
Clock Sources .................................................................... 36
Effects of Power-Managed Modes ............................. 40
Selecting the 31 kHz Source ...................................... 37
Selection Using OSCCON Register ........................... 37
CLRF ................................................................................ 423
CLRWDT .......................................................................... 423
Code Examples
16 x 16 Signed Multiply Routine .............................. 108
16 x 16 Unsigned Multiply Routine .......................... 108
512-Byte SPI Master Mode Init and Transfer ........... 283
8 x 8 Signed Multiply Routine .................................. 107
8 x 8 Unsigned Multiply Routine .............................. 107
A/D Calibration Routine ........................................... 353
Calculating Baud Rate Error .................................... 326
Capacitance Calibration Routine ............................. 380
Capacitive Touch Switch Routine ............................ 382
Changing Between Capture Prescalers ................... 244
Communicating with the +5V System ...................... 126
Computed GOTO Using an Offset Value ................... 75
Configuring EUSART2 Input and Output Functions . 148
Current Calibration Routine ..................................... 378
Erasing Flash Program Memory .............................. 102
Fast Register Stack .................................................... 75
How to Clear RAM (Bank 1) Using Indirect Addressing .
90
Initializing PORTA .................................................... 129
Initializing PORTB .................................................... 132
Initializing PORTC .................................................... 136
Initializing PORTD .................................................... 139
Initializing PORTE .................................................... 142
Loading the SSP1BUF (SSP1SR) Register ............. 269
Reading a Flash P