ISL97656 ® Data Sheet April 2, 2010 Integrated 4A Switch PWM Step-Up Regulator Features • >90% Efficiency The ISL97656 is a high frequency, high efficiency step-up voltage regulator operated at constant frequency PWM mode. With an internal 4.0A, 120mΩ MOSFET, it can deliver up to 2A output current at over 90% efficiency. The selectable 640kHz and 1.2MHz allows smaller inductors and faster transient response. An external compensation pin gives the user greater flexibility in setting frequency compensation allowing the use of low ESR Ceramic output capacitors. When shut down, it draws <1µA of current and can operate down to 2.3V input supply. These features along with 1.2MHz switching frequency makes it an ideal device for portable equipment and TFT-LCD displays. The ISL97656 is available in a 10 Ld TDFN package with a maximum height of 1.1mm. The device is specified for operation over the full -40°C to +85°C temperature range. Pinout FN6439.4 • 4.0A, 120mΩ Power MOSFET • 2.3V to 6.0V Input • Up to 24V Output • 640kHz/1.2MHz Switching Frequency Selection • Adjustable Soft-Start • Internal Thermal Protection • 0.8mm Max Height 10 Ld TDFN Package • Pb-Free (RoHS Compliant) • Halogen Free Applications • TFT-LCD Displays • DSL Modems • PCMCIA Cards ISL97656 (10 LD TDFN) TOP VIEW • Digital Cameras • GSM/CDMA Phones • Portable Equipment COMP 1 10 SS FB 2 9 FREQ EN 3 8 IN GND 4 7 LX GND 5 6 LX • Handheld Devices Ordering Information PART NUMBER (Note) PART MARKING PACKAGE (Pb-Free) PKG. DWG. # ISL97656IRTZ 656Z 10 Ld TDFN L10.3x3B ISL97656IRTZ-T* 656Z 10 Ld TDFN L10.3x3B ISL97656IRTZ-TK* 656Z 10 Ld TDFN L10.3x3B *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007-2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL97656 Absolute Maximum Ratings (TA = +25°C) Thermal Information LX to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26V IN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V COMP, FB, EN, SS, FREQ to GND . . . . . . . . . . . -0.3V to (IN +0.3V) Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 10 Ld 3x3 TDFN Package (Notes 1, 2) 53 3 Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. ΝΟΤΕΣ: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VIN = 3V, VOUT = 12V, IOUT = 0mA, FREQ = GND, TA = -40°C to +85°C, unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 5 µA IQ1 Quiescent Current - Shutdown EN = 0V 0.1 IQ2 Quiescent Current - Not Switching EN = IN, FB = 1.3V 0.7 IQ3 Quiescent Current - Switching EN = IN, FB = 1.0V 3 5 mA VFB Feedback Voltage 1.24 1.26 V IB-FB Feedback Input Bias Current 0.01 0.5 µA 6.0 V IN 1.22 Input Voltage Range 2.3 mA DMAX - 640kHz Maximum Duty Cycle FREQ = 0V 85 92 % DMAX - 1.2MHz Maximum Duty Cycle FREQ = IN 85 90 % 3.8 4.0 5.1 A 0.5 µA ILIM Current Limit - Max Peak Input Current IEN Shutdown Input Bias Current EN = 0V 0.01 rDS(ON) Switch ON Resistance IN = 2.7V, ILX = 1A 0.12 ILX-LEAK Switch Leakage Current VSW = 27V 0.01 ΔVOUT/ΔVIN Line Regulation 2.3V < VIN < 5.5V, VOUT = 12V 0.2 % ΔVOUT/ΔIOUT Load Regulation VIN = 3.3V, VOUT = 12V, IO = 30mA to 200mA 0.3 % FOSC1 Switching Frequency Accuracy FREQ = 0V 500 640 740 kHz FOSC2 Switching Frequency Accuracy FREQ = IN 1000 1220 1500 kHz 0.5 V VIL EN, FREQ Input Low Level VIH EN, FREQ Input High Level GM Error Amp Tranconductance IN-ON IN UVLO On Threshold HYS IN UVLO hysteresis ISS Soft-Start Charge Current OTP Over-Temperature Protection 2 Ω 3 1.5 ΔI = 5µA µA V 70 130 250 1µ/Ω 2.00 2.38 2.57 V 50 2.5 4.5 150 mV 7.5 µA °C FN6439.4 April 2, 2010 ISL97656 Block Diagram EN FREQ REFERENCE GENERATOR IN OSCILLATOR SS SHUTDOWN AND START-UP CONTROL LX PWM LOGIC CONTROLLER FET DRIVER COMPARATOR CURRENT SENSE GND FB GM AMPLIFIER COMP Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION 1 COMP Compensation pin. Output of the internal error amplifier. Capacitor and resistor from COMP pin to ground. 2 FB Voltage feedback pin. Internal reference is 1.24V nominal. Connect a resistor divider from VOUT. VOUT = 1.24V (1 + R1/R2). See “Typical Application Circuit”. 3 EN Shutdown control pin. Pull EN low to turn off the device. 4, 5 GND 6, 7 LX Power switch pin. Connected to the drain of the internal power MOSFET. 8 IN Analog power supply input pin. 9 FREQ 10 SS Analog and power ground. Frequency select pin. When FREQ is set low, switching frequency is set to 620kHz. When connected to high or IN, switching frequency is set to 1.25MHz. Soft-start control pin. Connect a capacitor to control the converter start-up. Typical Application Circuit R3 3.9kΩ C5 4.7nF 1 COMP R1 86.6kΩ R2 10kΩ SS 10 2 FB FREQ 9 3 EN IN 8 4 GND LX 7 5 GND LX 6 C3 27nF C4 2.3V TO 6.0V + C1 0.1µF 22µF 10µH D1 3 + C2 12V 22µF FN6439.4 April 2, 2010 ISL97656 Typical Performance Curves 92 96 VIN = 4.5V, VO = 5V 94 VIN = 4.0V, VO = 5V 88 VIN = 3.6V, VO = 5V 86 VIN = 3.3V, VO = 5V 84 EFFICIENCY (%) EFFICIENCY (%) 90 VIN = 5.0V, VO = 9V 92 90 VIN = 3.3V, VO = 9V 88 86 84 82 82 VIN = 3.0V, VO = 5V 80 80 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 250 IOUT (A) 750 1000 1250 1500 IOUT (mA) FIGURE 1. 5V BOOST EFFICIENCY vs IOUT FIGURE 2. 9V BOOST EFFICIENCY vs IOUT 0.7 0.9 VIN = 5V, VO = 12V, 0.8 VIN = 3.3V, VO = 9V, fs = 1.25MHz VIN = 5V, VO = 9V, fs = 1.25MHz 0.6 fs = 1.25MHz VIN = 3.3V, VO = 12V, fs = 1.25MHz 0.6 LOAD REGULATION (%) 0.7 LOAD REGULATION (%) 500 VIN = 5V, VO = 9V, fs = 620kHz 0.5 0.4 0.3 0.2 fs = 620kHz 200 400 fs = 1.25kHz 0.3 0.2 VIN = 3.3, VO = 12V, fs = 620kHz 0 0 0 VIN = 3.3, VO = 9V, 0.4 0.1 VIN = 5V, VO = 12V, 0.1 0.5 600 800 1000 0 100 IOUT (mA) 200 300 400 500 IOUT (mA) FIGURE 3. LOAD REGULATION vs IOUT FIGURE 4. LOAD REGULATION vs IOUT 0.6 0.5 fs = 1.25MHz LINE REGULATION (%) VO = 12V VO = 9V, IO = 80mA 0.4 IO = 50mA to 300mA VO = 9V, IO = 100mA fs = 620kHz 0.3 VIN = 3.3V VO = 12V, IO = 80mA fs = 600kHz fs = 1.25MHz 0.2 0.1 0 VO = 12V, IO = 80mA fs = 620kHz -0.1 2 3 4 5 6 VIN (V) FIGURE 5. LINE REGULATION vs VIN 4 FIGURE 6. TRANSIENT RESPONSE FN6439.4 April 2, 2010 ISL97656 Typical Performance Curves (Continued) IO = 50mA to 300mA VO = 12V VIN = 3.3V fs = 1.2MHz FIGURE 7. TRANSIENT RESPONSE Applications Information The ISL97656 is a high frequency, high efficiency boost regulator operated at constant frequency PWM mode. The boost converter stores energy from an input voltage source and deliver it to a higher output voltage. The input voltage range is 2.3V to 6.0V and output voltage range is 5V to 25V. The switching frequency is selectable between 640kHz and 1.2MHz allowing smaller inductors and faster transient response. An external compensation pin gives the user greater flexibility in setting output transient response and tighter load regulation. The converter soft-start characteristic can also be controlled by external CSS capacitor. The EN pin allows the user to completely shutdown the device. Boost Converter Operations Figure 8 shows a boost converter with all the key components. In steady state operating and continuous conduction mode where the inductor current is continuous, the boost converter operates in two cycles. During the first cycle, as shown in Figure 9, the internal power FET turns on and the Schottky diode is reverse biased and cuts off the current flow to the output. The output current is supplied from the output capacitor. The voltage across the inductor is VIN and the inductor current ramps up in a rate of VIN/L, L is the inductance. The inductance is magnetized and energy is stored in the inductor. The change in inductor current is shown in Equation 1: V IN ΔI L1 = ΔT1 × --------L D ΔT1 = ---------f SW D = Duty Cycle I OUT ΔV O = ---------------- × ΔT 1 C OUT The Schottky diode side of the inductor is clamp to a Schottky diode above the output voltage. So the voltage drop across the inductor is VIN - VOUT. The change in inductor current during the second cycle is shown in Equation 2: V IN – V OUT ΔI L = ΔT2 × -------------------------------L 1–D ΔT2 = ------------f SW (EQ. 2) For stable operation, the same amount of energy stored in the inductor must be taken out. The change in inductor current during the two cycles must be the same as shown in Equation 3. ΔI1 + ΔI2 = 0 V IN 1 – D V IN – V OUT D ---------- × --------+ ------------- × -------------------------------- = 0 L f SW L f SW V OUT 1 ---------------- = ------------1–D V IN (EQ. 3) L D VOUT VIN CIN COUT ISL97656 FIGURE 8. BOOST CONVERTER L VOUT VIN COUT CIN ISL97656 (EQ. 1) During the second cycle, the power FET turns off and the Schottky diode is forward biased, (see Figure 10). The energy stored in the inductor is pumped to the output supplying output current and charging the output capacitor. 5 IL ΔIL1 ΔT1 ΔVO FIGURE 9. BOOST CONVERTER - CYCLE 1, POWER SWITCH CLOSED FN6439.4 April 2, 2010 ISL97656 Schottky Diode L D VOUT VIN COUT CIN ISL97656 IL ΔIL2 ΔT2 Input Capacitor ΔVO FIGURE 10. BOOST CONVERTER - CYCLE 2, POWER SWITCH OPEN Output Voltage An external feedback resistor divider is required to divide the output voltage down to the nominal 1.24V reference voltage. The current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network less than 100k is recommended. The boost converter output voltage is determined by the relationship as shown in Equation 4. The nominal VFB voltage is 1.24V.. R 1⎞ ⎛ V OUT = V FB × ⎜ 1 + -------⎟ R 2⎠ ⎝ (EQ. 4) Inductor Selection The inductor selection determines the output ripple voltage, transient response, output current capability, and efficiency. Its selection depends on the input voltage, output voltage, switching frequency, and maximum output current. For most applications, the inductance should be in the range of 2µH to 33µH. The inductor maximum DC current specification must be greater than the peak inductor current required by the regulator. The peak inductor current can be calculated using Equation 5:: V IN × ( V OUT – V IN ) I OUT × V OUT I L ( PEAK ) = ------------------------------------ + 1 ⁄ 2 × ----------------------------------------------------V IN L × V OUT × FREQ (EQ. 5) Output Capacitor Low ESR capacitors should be used to minimized the output voltage ripple. Multilayer ceramic capacitors (X5R and X7R) are preferred for the output capacitors because of their lower ESR and small packages. Tantalum capacitors with higher ESR can also be used. The output ripple can be calculated using Equation 6: I OUT × D ΔV O = ------------------------- + I OUT × ESR f SW × C O (EQ. 6) For noise sensitive application, a 0.1µF placed in parallel with the larger output capacitor is recommended to reduce the switching noise coupled from the LX switching node. 6 In selecting the Schottky diode, the reverse break down voltage, forward current and forward voltage drop must be considered for optimum converter performance. The diode must be rated to handle 4.0A, the current limit of the ISL97656. The breakdown voltage must exceed the maximum output voltage. Low forward voltage drop, low leakage current, and fast reverse recovery will help the converter to achieve the maximum efficiency. The value of the input capacitor depends the input and output voltages, the maximum output current, the inductor value and the noise allowed to put back on the input line. For most applications, a minimum 10µF is required. For applications that run close to the maximum output current limit, input capacitor in the range of 22µF to 47µF is recommended. The ISL97656 is powered from the VIN. A High frequency 0.1µF bypass capacitor is recommended to be close to the VIN pin to reduce supply line noise and ensure stable operation. Loop Compensation The ISL97656 incorporates a transconductance amplifier in its feedback path to allow the user some adjustment on the transient response and better regulation. The ISL97656 uses current mode control architecture which has a fast current sense loop and a slow voltage feedback loop. The fast current feedback loop does not require any compensation. The slow voltage loop must be compensated for stable operation. The compensation network is a series RC network from COMP pin to ground. The resistor sets the high frequency integrator gain for fast transient response and the capacitor sets the integrator zero to ensure loop stability. For most applications, the compensation resistor in the range of 0k to 2.0k and the compensation capacitor in the range of 3nF to 10nF. Soft-Start The soft-start is provided by an internal 4.5µA current source charges the external CSS, the peak MOSFET current is limited by the voltage on the capacitor. This in turn controls the rising rate of the output voltage. The regulator goes through the start-up sequence as well after the EN pin is pulled to HI. Frequency Selection The ISL97656 switching frequency can be user selected to operate at either constant 640kHz or 1.25MHz. Connecting FREQ pin to ground sets the PWM switching frequency to 640kHz. When connecting FREQ high or IN, the switching frequency is set to 1.2MHz. Shutdown Control When the EN pin is pulled down, the ISL97656 is shutdown reducing the supply current to <1µA. FN6439.4 April 2, 2010 ISL97656 Maximum Output Current Cascaded MOSFET Application The MOSFET current limit is nominally 4.0A and guaranteed 3.8A. This restricts the maximum output current, IOMAX, based on Equation 7: A 24V N-Channel MOSFET is integrated in the boost regulator. For the applications where the output voltage is greater than 24V, an external cascaded MOSFET is needed as shown in Figure 11. The voltage rating of the external MOSFET should be greater than AIN. (EQ. 7) I L = I L ( AVG ) + ( 1 ⁄ 2 × ΔI L ) where: AIN VIN IL = MOSFET current limit IL(AVG) = average inductor current ΔIL = inductor ripple current LX V IN × [ ( V O + V DIODE ) – V IN ] ΔI L = -----------------------------------------------------------------------------L × ( V O + V DIODE ) × f S (EQ. 8) INTERSIL ISL97656 FB VDIODE = Schottky diode forward voltage, typically, 0.6V fS = switching frequency, 600kHz or 1.2MHz I OUT I L-AVG = ------------1–D (EQ. 9) D = MOSFET turn-on ratio: V IN D = 1 – -------------------------------------------V OUT + V DIODE (EQ. 10) Table 1 gives typical maximum IOUT values for 1.2MHz switching frequency and 10µH inductor. TABLE 1. TYPICAL MAXIMUM IOUT VALUES VIN (V) VOUT (V) IOMAX (mA) 2.5 5 1790 2.5 9 990 2.5 12 750 3.3 5 2370 3.3 9 1300 3.3 12 970 5 9 1970 5 12 1470 FIGURE 11. CASCADED MOSFET TOPOLOGY FOR HIGH OUTPUT VOLTAGE APPLICATIONS DC PATH BLOCK APPLICATION Note that there is a DC path in the boost converter from the input to the output through the inductor and diode, hence the input voltage will be seen at output with a forward voltage drop of diode before the part is enabled. If this voltage is not desired, the following circuit (see Figure 12) can be inserted between input and inductor to disconnect the DC path when the part is disabled. TO INDUCTOR INPUT EN FIGURE 12. CIRCUIT TO DISCONNECT THE DC PATH OF BOOST CONVERTER All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7 FN6439.4 April 2, 2010 ISL97656 Package Outline Drawing L10.3x3B 10 LEAD THIN DUAL FLAT PACKAGE (TDFN) WITH E-PAD Rev 2, 03/10 3.00 6 PIN #1 INDEX AREA A B 1 2 0.50 3.00 2.38 +0.1/ - 0.15 10 6 PIN 1 INDEX AREA 4 0.25 +0.05/ - 0.07 6 (4X) 0.15 1.64 +0.1/ -0.15 TOP VIEW BOTTOM VIEW 10x 0.40 +/- 0.1 (10x0.20) PACKAGE OUTLINE SEE DETAIL "X" (10x0.40) (10X0.25) 0.75 0.10 C SEATING PLANE 0.08 C 2.38 0.05 C SIDE VIEW (8x 0.50) 1.64 TYPICAL RECOMMENDED LAND PATTERN C 0.20 REF 5 0.05 DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.18mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 8 FN6439.4 April 2, 2010