RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Data Sheet July 1999 0.3A, 60V, 6 Ohm, ESD Rated, Current Limited, Voltage Clamped, Logic Level N-Channel Power MOSFETs File Number 3948.5 Features • 0.30A, 60V These are intelligent monolithic power circuits which incorporate a lateral bipolar transistor, resistors, zener diodes and a power MOS transistor. The current limiting of these devices allow it to be used safely in circuits where a shorted load condition may be encountered. The drain to source voltage clamping offers precision control of the circuit voltage when switching inductive loads. The “Logic Level” gate allows this device to be fully biased on with only 5V from gate to source, thereby facilitating true on-off power control directly from logic level (5V) integrated circuits. These devices incorporate ESD protection and are designed to withstand 2kV (Human Body Model) of ESD. • rDS(ON) = 6.0Ω • Built in Current Limit ILIMIT 0.140 to 0.210A at 150oC • Built in Voltage Clamp • Temperature Compensating PSPICE® Model • 2kV ESD Protected • Controlled Switching Limits EMI and RFI • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol Formerly developmental type TA49028. D Ordering Information PART NUMBER PACKAGE BRAND RLD03N06CLE TO-251AA 03N06C RLD03N06CLESM TO-252AA 03N06C RLP03N06CLE TO-220AB 03N06CLE G S NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in tape and reel, i.e. RLD03N06CLESM9A. Packaging JEDEC TO-251AA JEDEC TO-252AA SOURCE DRAIN GATE DRAIN (FLANGE) DRAIN (FLANGE) GATE SOURCE JEDEC TO-220AB DRAIN (FLANGE) 6-418 SOURCE DRAIN GATE CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE® is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage (Reverse Voltage Gate Bias Not Allowed) . . . . . . . . . . . . VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrostatic Discharge Rating MIL-STD-883, Category B(2) . . . . . . . . . . . . . . . .ESD Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE 60 60 +5.5 Self Limited 30 0.2 2 -55 to 175 UNITS V V V W W/oC KV oC oC oC 300 260 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V 60 - 85 V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 1 - 2.5 V Zero Gate Voltage Drain Current IDSS Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Limiting Current IGSS rDS(ON) IDS(LIMIT) Turn-On Time tON Turn-On Delay Time td(ON) TJ = 25oC - - 25 µA TJ = 150oC - - 250 µA VGS = 5V TJ = 25oC - - 5 µA TJ = 150oC - - 20 µA ID = 0.100A, VGS = 5V TJ = 25oC - - 6.0 Ω TJ = 150oC - - 12.0 Ω VDS = 15V, VGS = 5V TJ = 25oC TJ = 150oC 280 - 420 mA 140 - 210 mA VDD = 30V, ID = 0.10A, RL = 300Ω, VGS = 5V, RGS = 25Ω - - 7.5 µs - - 2.5 µs - - 5.0 µs td(OFF) - - 7.5 µs tf - - 5.0 µs tOFF - - 12.5 µs - 100 - pF - 65 - pF Rise Time tr Turn-Off Delay Time VDS = 45V, VGS = 0V Fall Time Turn-Off Time Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS - 3.0 - pF Thermal Resistance Junction to Case RθJC RθJA - - 5.0 oC/W TO-220 Package - - 80 oC/W TO-251 and TO-252 Packages - - 100 oC/W MIN TYP MAX UNITS ISD = 0.1A - - 1.5 V ISD = 0.1A, dISD/dt = 100A/µs - - 1.0 ms Thermal Resistance Junction to Ambient VDS = 25V, VGS = 0V, f = 1MHz Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage VSD Diode Reverse Recovery Time trr TEST CONDITIONS NOTES: 2. Pulsed: pulse duration = ≤ 300µs maximum, duty cycle = ≤ 2%. 3. Repititive rating: pulse width limited by maximum junction temperature. 6-419 RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Typical Performance Curves Unless Otherwise Specified 1 TC = 25oC, TJ = MAX RATED 1.0 OPERATION IN THIS AREA IS LIMITED BY JUNCTION TEMPERATURE ID , DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 175oC OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 0.2 0 0 25 50 75 100 125 150 175 25oC DC 0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 100 FIGURE 2. FORWARD BIAS SAFE OPERATING AREA 2 ZθJC , NORMALIZED THERMAL IMPEDANCE 1 0.5 0.2 0.1 0.1 PDM 0.05 0.02 0.01 t1 SINGLE PULSE 0.01 10-5 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101 1 0.40 TC = 25oC TEMPERATURES LISTED ARE STARTING JUNCTION TEMPERATURES ID , DRAIN CURRENT (A) I(CLAMP) , CLAMPED DRAIN CURRENT (A) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 25oC 50oC 75oC 100oC 150oC 0.1 0.001 0.01 VGS = 5V VGS = 7.5V VGS = 4V 0.30 VGS = 3V 0.20 0.10 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC 125oC 0.1 tAV, TIME IN CLAMP (s) 1 FIGURE 4. SELF-CLAMPED INDUCTIVE SWITCHING 6-420 10 0 0 1 2 3 4 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 5. SATURATION CHARACTERISTICS 5 RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Unless Otherwise Specified (Continued) 0.60 2.5 -55oC VDD = 15V PULSE TEST PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0.50 0.40 NORMALIZED DRAIN TO SOURCE ON RESISTANCE ID(ON) , ON STATE DRAIN CURRENT (A) Typical Performance Curves 25oC 0.30 0.20 175oC 0.10 2.0 1.5 1.0 0.5 0 -80 0 0 1 2 3 4 VGS , GATE TO SOURCE VOLTAGE (V) 5 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE 2.0 VGS = VDS, ID = 250µA 1.0 0.5 -40 0 40 80 120 160 200 1.0 0.5 0 -80 NORMALIZED DRAIN LIMITING CURRENT C, CAPACITANCE (pF) 160 -40 0 40 80 120 160 200 FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs TEMPERATURE VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 200 CISS 100 COSS CRSS 25 FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 6-421 120 TJ , JUNCTION TEMPERATURE (oC) 300 5 10 15 20 VDS , DRAIN TO SOURCE VOLTAGE (V) 80 1.5 200 FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 0 40 ID = 10mA TJ , JUNCTION TEMPERATURE (oC) 0 0 FIGURE 7. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1.5 0 -80 -40 TJ , JUNCTION TEMPERATURE (oC) FIGURE 6. TRANSFER CHARACTERISTICS 2.0 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 5V, ID = 0.10A 2.0 VGS = 5V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX. 1.5 1.0 0.5 0 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED DRAIN LIMITING CURRENT vs JUNCTION TEMPERATURE 200 RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Typical Performance Curves Unless Otherwise Specified (Continued) VDS , DRAIN SOURCE VOLTAGE (V) 45 3.75 VDD = BVDSS 2.50 30 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS 15 RL = 600Ω IG(REF) = 0.1mA VGS = 5V 0 1.25 VGS , GATE SOURCE VOLTAGE (V) 5.00 60 0.00 I G ( REF ) 10 ---------------------I G ( ACT ) t, TIME (µs) I G ( REF ) 40 I---------------------G ( ACT ) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT. Test Circuits and Waveforms tON td(ON) VDD tOFF td(OFF) tr RL VDS VDS tf 90% 90% VGS 10% 10% DUT 90% 0V 50% VGS RGS 50% PULSE WIDTH 10% FIGURE 13. RESISTIVE SWITCHING TEST CIRCUIT Detailed Description Temperature Dependence of Current Limiting and Switching Speed Performance The RLD03N06CLE, CLESM and RLP03N06CLE are monolithic power devices which incorporate a Logic Level power MOSFET transistor with a current sensing scheme and control circuitry to enable the device to self limit the drain source current flow. The current sensing scheme supplies current to a resistor that is connected across the base to emitter of a bipolar transistor in the control section. The collector of this bipolar transistor is connected to the gate of the power MOSFET transistor. When the ratiometric current from the current sensing reaches the value required to forward bias the base emitter junction of this bipolar transistor, the bipolar “turns on”. A resistor is incorporated in series with the gate of the power MOSFET transistor allowing the bipolar transistor to adjust the drive on the gate of the power MOSFET transistor to a voltage which then maintains a constant current in the power MOSFET transistor. Since both the ratiometric current sensing scheme and the base emitter unction 6-422 FIGURE 14. RESISTIVE SWITCHING WAVEFORMS voltage of the bipolar transistor vary with temperature, the current at which the device limits is a function of temperature. This dependence is shown in Figure 3. The resistor in series with the gate of the power MOSFET transistor also results in much slower switching performance than in standard power MOSFET transistors. This is an advantage where fast switching can cause EMI or RFI. The switching speed is very predictable. DC Operation The limit on the drain to source voltage for operation in current limiting on a steady state (DC) basis is shown in the equation below. The dissipation in the device is simply the applied drain to source voltage multiplied by the limiting current. This device, like most power MOSFET devices today, is limited to 175oC. The maximum voltage allowable can, therefore, be expressed as shown in Equation 1: ( 150°C – T AMBIENT ) DS = ------------------------------------------------------I LM • ( RθJC + RθJA ) (EQ.1) RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE The results of this equation are plotted in Figure 15 for various heatsinks. These values are plotted as Figures 16 through 21 for various heatsink thermal resistances. Duty Cycle Operation Limited Time Operations In many applications either the drain to source voltage or the gate drive is not available 100% of the time. The copper header on which the RLD03N06CLE, CLESM and RLP03N06CLE is mounted has a very large thermal storage capability, so for pulse widths of less then 1ms, the temperature of the header can be considered a constant, thereby the junction temperature can be calculated simply as shown in Equation 2: Protection for a limited period of time is sufficient for many applications. As stated above the heat storage in the silicon chip can usually be ignored for computations of over 10 ms, thereby the thermal equivalent circuit reduces to a simple enough circuit to allow easy computation on the limiting conditions. The variation in limiting current with temperature complicates the calculation of junction temperature, but a simple straight line approximation of the variation is accurate enough to allow meaningful computations. The curves shown as Figures 22 through 25 (RLP03N06CLE) and Figure 26 through 29 (RLD03N06CLE and RLD03N06CLESM) give an accurate indication of how long the specified voltage can be applied to the device in the current limiting mode without exceeding the maximum specified 175oC junction temperature. In practice this tells you how long you have to alleviate the condition causing the current limiting to occur. T C = ( V DS • I D • D • R θCA ) + T AMBIENT (EQ.2) Generally the heat storage capability of the silicon chip in a power transistor is ignored for duty cycle calculations. Making this assumption, limiting junction temperature to 175oC and using the TC calculated in Equation 2, the expression for maximum VDS under duty cycle operation is shown in Equation 3 : o 150 C – T C V DS = -----------------------------------------I LM • D • R θJC (EQ.3) Typical Performance Curves 90 HSTR = 0oC/W HSTR = 1oC/W HSTR = 2oC/W 75 HSTR = 5oC/W TJ = 175oC ILIM = 0.210A RθJC = 5.0oC/W 60 HSTR = 10oC/W 45 30 HSTR = 25oC/W 15 HSTR = 80oC/W 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) VDS , DRAIN TO SOURCE VOLTAGE (V) VDS , APPLIED VOLTAGE (V) 90 175 NOTE: Heat Sink Thermal Resistance = HSTR. DC = 2% DC = 5% 60 DC = 10% 45 30 TJ = 175oC ILIM = 0.210A 15 RθJC = 5.0oC/W DUTY CYCLE = DC MAX PULSE WIDTH = 100ms 0 100 125 150 TA , AMBIENT TEMPERATURE (oC) 175 FIGURE 16. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HEATSINK THERMAL RESISTANCE = 1oC/W) FIGURE 15. DC OPERATION IN CURRENT LIMITING 90 DC = 2% 75 DC = 20% DC = 50% 60 DC = 5% DC = 10% 45 30 TJ = 175oC ILIM = 0.210A RθJC = 5.0oC/W 15 DUTY CYCLE = DC 0 100 MAX PULSE WIDTH = 100ms 125 150 TA , AMBIENT TEMPERATURE (oC) 175 FIGURE 17. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HSTR = 2oC/W) 6-423 VDS , DRAIN TO SOURCE VOLTAGE (V) 90 VDS , DRAIN TO SOURCE VOLTAGE (V) DC = 20% DC = 50% 75 DC = 20% 75 DC = 2% DC = 5% 60 DC = 10% DC = 50% 45 30 15 TJ = 175oC ILIM = 0.210A RθJC = 5.0oC/W DUTY CYCLE = DC 0 75 MAX PULSE WIDTH = 100ms 100 125 150 TA , AMBIENT TEMPERATURE (oC) 175 FIGURE 18. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HSTR = 5oC/W) RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Typical Performance Curves (Continued) 90 DC = 20% VDS , DRAIN TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V) 90 DC = 2% 75 DC = 5% DC = 50% 60 DC = 10% 45 30 TJ = 175oC ILIM = 0.210A RθJC = 5.0oC/W DUTY CYCLE = DC 15 MAX PULSE WIDTH = 100ms 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) FIGURE 19. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HSTR = 10oC/W) DC = 5% 45 DC = 50% 30 TJ = 175oC ILIM = 0.210A RθJC = 5.0oC/W DUTY CYCLE = DC 15 25 50 MAX PULSE WIDTH = 100ms 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) 175 FIGURE 20. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HSTR = 25oC/W) 90 10 DC = 10% 75 DC = 5% DC = 2% DC = 1% TJ = 175oC ILIM = 0.210A RθJC = 5.0oC/W 60 DC = 20% 45 STARTING TJ = 75oC STARTING TJ = 100oC STARTING TJ = 125oC STARTING TJ = 150oC 8 TIME TO 175oC (s) VDS , DRAIN TO SOURCE VOLTAGE (V) DC = 2% 60 0 175 DC = 10% DC = 20% 75 30 6 4 DC = 50% 2 15 0 25 NOTE: 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) 175 0 Duty Cycyle = DC, Max Pulse Width = 100ms. FIGURE 21. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HSTR = 80oC/W) 30 50 70 VDS , DRAIN TO SOURCE VOLTAGE (V) 90 FIGURE 22. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 25oC/W) (HEATSINK THERMAL CAPACITANCE = 0.5J/oC) 10 10 STARTING TJ = 75oC STARTING TJ = 100oC STARTING TJ = 125oC STARTING TJ = 150oC 8 TIME TO 175oC (s) 8 TIME TO 175oC (s) 10 6 4 STARTING TJ = 75oC 6 STARTING TJ = 100oC 4 STARTING TJ = 125oC 2 2 0 0 STARTING TJ = 150oC 10 30 50 70 VDS , DRAIN TO SOURCE VOLTAGE (V) 90 FIGURE 23. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 10oC/W) (HEATSINK THERMAL CAPACITANCE = 1.0J/oC) 6-424 10 50 70 30 VDS , DRAIN TO SOURCE VOLTAGE (V) 90 FIGURE 24. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 5oC/W) (HEATSINK THERMAL CAPACITANCE = 2.0J/oC) RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Typical Performance Curves 10 (Continued) 10 STARTING TJ = 75oC 8 TIME TO 175oC (s) TIME TO 175oC (s) 8 STARTING TJ = 100oC 6 STARTING TJ = 125oC 4 STARTING TJ = 75oC STARTING TJ = 100oC STARTING TJ = 125oC STARTING TJ = 150oC 6 4 2 2 STARTING TJ = 150oC 0 10 30 50 70 VDS , DRAIN TO SOURCE VOLTAGE (V) 0 90 FIGURE 25. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 2oC/W) (HEATSINK THERMAL CAPACITANCE = 4J/oC) 90 10 8 8 STARTING TJ = 75oC STARTING TJ = 100oC STARTING TJ = 125oC STARTING TJ = 150oC 6 TIME TO 175oC (s) TIME TO 175oC (s) 30 50 70 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 26. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 25oC/W) (HEATSINK THERMAL CAPACITANCE = 0.5J/oC) 10 4 STARTING TJ = 75oC 6 STARTING TJ = 100oC 4 STARTING TJ = 125oC 2 2 0 10 0 10 30 50 70 VDS , DRAIN TO SOURCE VOLTAGE (V) 90 STARTING TJ = 150oC 10 50 30 FIGURE 27. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 10oC/W) (HEATSINK THERMAL CAPACITANCE = 1.0J/oC) STARTING TJ = 75oC TIME TO 175oC (s) 8 6 STARTING TJ = 100oC 4 STARTING TJ = 125oC 0 STARTING TJ = 150oC 10 30 50 70 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 29. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 2oC/W) (HEATSINK THERMAL CAPACITANCE = 4J/oC) 6-425 90 FIGURE 28. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 5oC/W) (HEATSINK THERMAL CAPACITANCE = 2.0J/oC) 10 2 70 VDS , DRAIN TO SOURCE VOLTAGE (V) 90 RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE PSPICE Electrical Model SUBCKT RLD03N06CLE 2 1 3; CA 12 8 0.547e-9 CB 15 14 0.547e-9 CIN 6 8 0.301e-9 rev 4/18/94 5 DRAIN LDRAIN 2 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DESD1 91 9 DESD1MOD DESD2 91 7 DESD2MOD DPLCAP 10 5 DPLCAPMOD DBREAK DPLCAP 10 11 + EBREAK 11 20 17 18 66.5 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 EBREAK ESG 6 8 + 17 18 RDRAIN GATE IT 8 17 1 1 LDRAIN 2 5 1e-9 LGATE 1 9 2.96e-9 LSOURCE 3 7 2.96e-9 RGATE LGATE 9 VTO + EVTO + 18 8 DESD1 21 CIN DESD2 8 S1A 12 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 1.123 RGATE 9 20 3200 RIN 6 8 1e9 RSOURCE1 8 70 RDSMOD 1.12 RSOURCE2 70 7 RSMOD 2.16 RVTO 18 19 RVTOMOD 1 LSOURCE RSOURCE1 RSOURCE2 3 SOURCE 7 70 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 QCONTROL 20 70 7 QMOD 1 MOS2 MOS1 6 RIN 91 DBODY 16 S2A 14 13 13 8 S1B RVTO CB + EGS 18 17 S2B 13 CA RBREAK 15 + 6 8 EDS 14 5 8 IT 19 VBAT + S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.22 .MODEL DBDMOD D (IS = 7.97e-17 RS = 1.82 TRS1 = 3.91e-3 TRS2 = 1.24e-5 CJO = 3.00e-10 TT = 1.83e-7) .MODEL DBKMOD D (RS = 3150 TRS1 =0 TRS2 = 0) .MODEL DESD1MOD D (BV = 13.54 TBV1 = 0 TBV2 = 0 RS = 45.5 TRS1 = 0 TRS2 = 0) .MODEL DESD2MOD D (BV = 11.46 TBV1 = -7.576e-4 TBV2 = -3.0e-6 RS = 0 TRS1 = 0 TRS2 = 0) .MODEL DPLCAPMOD D (CJO = 74.2e-12 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 1.67 KP = 3.40 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL QMOD NPN (BF =5) .MODEL RBKMOD RES (TC1 = 4e-4 TC2 = 1.13e-8) .MODEL RDSMOD RES (TC1 = 6.80e-3 TC2 = 6.5e-6) .MODEL RSMOD RES (TC1 = 2.95e-3 TC2 = -1e-6) .MODEL RVTOMOD RES (TC1 = -2.22e-3 TC2 = -1.95e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF = -1) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1 VOFF = -3) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.85 VOFF = 2.15) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.15 VOFF = -2.85) .ENDS NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records 1991. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 6-426