FUJITSU SEMICONDUCTOR CONTROLLER MANUAL CM44-10106-5E 2 F MC-16LX 16-BIT MICROCONTROLLER MB90595 Series HARDWARE MANUAL 2 F MC-16LX 16-BIT MICROCONTROLLER MB90595 Series HARDWARE MANUAL Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL:http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. FUJITSU LIMITED PREFACE ■ Objectives and Intended Reader Thank you very much for your continued patronage of Fujitsu semiconductor products. The MB90595 series has been developed as a general-purpose version of the F2MC-16LX series, which is an original 16-bit single-chip microcontroller compatible with the Application Specific IC (ASIC). This manual explains the functions and operation of the MB90595 series for designers who actually use the MB90595 series to design products. Read this manual first. Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller. ■ Trademark The company names and brand names herein are the trademarks or registered trademarks of their respective owners. ■ Structure of This Manual CHAPTER 1 "OVERVIEW" The MB90595 Series is a family member of the F2MC-16LX microcontrollers. CHAPTER 2 "CPU" This chapter explains the CPU. CHAPTER 3 "INTERRUPTS" This chapter explains interrupt functions and operation. CHAPTER 4 "DELAYED INTERRUPT" This chapter explains the delayed interrupt functions and operation. CHAPTER 5 "CLOCK AND RESET" This chapter explains the clock and reset functions and operation. CHAPTER 6 "LOW-POWER CONTROL CIRCUIT" This chapter explains the functions and operation of the low-power control circuit. CHAPTER 7 "MEMORY ACCESS MODES" This chapter explains the I/O port functions and operation. CHAPTER 9 "TIME-BASE TIMER" This chapter explains the time-base timer functions and operation. CHAPTER 10 "WATCH-DOG TIMER" This chapter explains the watchdog timer functions and operation. CHAPTER 11 "16-BIT I/O TIMER" This chapter explains the 16-bit I/O timer functions and operation. i CHAPTER 12 "16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)" This chapter explains the functions and operation of the 16-bit reload timer (with the event count function). CHAPTER 13 "8/16-BIT PPG" This chapter provides an outline the 8/16-bit PPG and explains its functions. CHAPTER 14 "DTP/EXTERNAL INTERRUPTS" This chapter explains the DTP/external interrupt functions and operation. CHAPTER 15 "A/D CONVERTER" This chapter explains the A/D converter functions and operation. CHAPTER 16 "UART0" This chapter explains the UART0 functions and operation. CHAPTER 17 "UART1 (SCI)" This chapter explains the UART1 (SCI) functions and operation. CHAPTER 18 "SERIAL I/O" This chapter explains the serial I/O functions and operation. CHAPTER 19 "CAN CONTROLLER" This chapter explains the CAN controller functions and operation. CHAPTER 20 "STEPPING MOTOR CONTROLLER" This chapter explains the functions and operation of the stepping motor controller. CHAPTER 21 "ADDRESS MATCH DETECTION FUNCTION" This chapter explains the address match detection function and operation. CHAPTER 22 "ROM MIRRORING FUNCTION SELECTION MODULE" This chapter explains the ROM mirroring function selection module. CHAPTER 23 "1M-BIT FLASH MEMORY" This chapter explains the functions and operation of the 1M-bit flash memory. The following three methods are available for writing data to and erasing data from the flash memory: CHAPTER 24 "EXAMPLES OF F2MC-16LX MB90F598/F598G SERIAL PROGRAMMING CONNECTION" This chapter provides examples of F2MC-16LX MB90F598/F598G serial programming connection. APPENDIX The appendixes provide I/O maps, instructions, and other information. ii • • • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device; FUJITSU does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Copyright © 1999-2007 FUJITSU LIMITED All rights reserved iii iv CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Product Overview ................................................................................................................................ 2 Features .............................................................................................................................................. 3 Block Diagram ..................................................................................................................................... 5 Pin Assignment .................................................................................................................................... 6 Package Dimensions ........................................................................................................................... 7 Pin Functions ....................................................................................................................................... 8 Input/Output Circuits .......................................................................................................................... 11 Handling Device ................................................................................................................................ 14 CHAPTER 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.7.1 2.7.2 2.7.3 2.7.4 2.8 2.9 2.10 2.11 CPU ............................................................................................................. 19 Outline of CPU ................................................................................................................................... 20 Memory Space .................................................................................................................................. 21 Memory Space Map .......................................................................................................................... 22 Linear Addressing Mode .................................................................................................................... 23 Bank Addressing Types ..................................................................................................................... 24 Multi-byte Data in Memory Space ..................................................................................................... 26 Registers ........................................................................................................................................... 27 Accumulator (A) ............................................................................................................................ 30 User Stack Pointer (USP) and System Stack Pointer (SSP) ........................................................ 31 Processor Status (PS) .................................................................................................................. 32 Program Counter (PC) .................................................................................................................. 35 Register Bank .................................................................................................................................... 36 Prefix Codes ...................................................................................................................................... 38 Interrupt Disable Instructions ............................................................................................................. 40 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions ................................................. 41 CHAPTER 3 3.1 3.2 3.3 3.4 3.5 3.5.1 3.5.2 3.5.3 3.6 3.7 3.7.1 3.7.2 3.8 3.9 OVERVIEW ................................................................................................... 1 INTERRUPTS .............................................................................................. 43 Outline of Interrupts ........................................................................................................................... 44 Interrupt Vectors ............................................................................................................................... 47 Interrupt Control Register (ICR) ......................................................................................................... 48 Interrupt Sequence ............................................................................................................................ 51 Hardware Interrupts ........................................................................................................................... 53 Hardware Interrupt Operation ....................................................................................................... 54 Occurrence and Release of Hardware Interrupt ........................................................................... 55 Multiple Interrupts ......................................................................................................................... 57 Software Interrupts ............................................................................................................................ 58 Extended Intelligent I/O Service (EI2OS) ........................................................................................... 60 Extended Intelligent I/O Service Descriptor (ISD) ........................................................................ 62 EI2OS Status Register (ISCS) ...................................................................................................... 64 Operation Sequence and Use Sequence of Extended Intelligent I/O Service (EI2OS) ..................... 66 Exceptions ......................................................................................................................................... 69 v CHAPTER 4 4.1 4.2 4.3 CHAPTER 5 5.1 5.2 5.3 LOW-POWER CONTROL CIRCUIT ........................................................... 83 Outline of Low-Power Control Circuit ................................................................................................ 84 Registers of Low-power Control Circuit ............................................................................................ 86 Low-Power Mode Control Resister (LPMCR) .............................................................................. 87 Clock Selection Register (CKSCR) .............................................................................................. 89 Low-Power Mode Operation ............................................................................................................. 91 Sleep Mode .................................................................................................................................. 93 Timer Mode .................................................................................................................................. 94 Stop Mode ................................................................................................................................... 95 Hardware Standby Mode ............................................................................................................. 97 Intermittent CPU Operation ............................................................................................................... 98 Switching Machine Clocks ................................................................................................................ 99 Status Transition of Clock Selection ............................................................................................... 100 CHAPTER 7 7.1 7.2 7.3 CLOCK AND RESET .................................................................................. 75 Clock Generator ................................................................................................................................ 76 Reset Cause Occurrence .................................................................................................................. 77 Reset Causes ................................................................................................................................... 80 CHAPTER 6 6.1 6.2 6.2.1 6.2.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.4 6.5 6.6 DELAYED INTERRUPT .............................................................................. 71 Outline of Delayed Interrupt Module ................................................................................................. 72 Delayed Interrupt Request Register .................................................................................................. 73 Operations of Delayed Interrupt ........................................................................................................ 74 MEMORY ACCESS MODES .................................................................... 101 Outline of Memory Access Modes .................................................................................................. 102 Mode Pins ....................................................................................................................................... 103 Mode Data ...................................................................................................................................... 104 CHAPTER 8 I/O PORTS ................................................................................................ 107 8.1 I/O Ports .......................................................................................................................................... 8.2 I/O Port Registers ........................................................................................................................... 8.2.1 Port Data Registers ................................................................................................................... 8.2.2 Port Direction Register ............................................................................................................... 8.2.3 Analog Input Enable Register .................................................................................................... CHAPTER 9 9.1 9.2 9.3 108 109 110 111 112 TIME-BASE TIMER ................................................................................... 113 Outline of Time-base Timer ............................................................................................................ 114 Time-base Timer Control Register .................................................................................................. 115 Time-base Timer Operation ............................................................................................................ 116 CHAPTER 10 WATCH-DOG TIMER ................................................................................ 117 10.1 10.2 Outline of Watch-Dog Timer ........................................................................................................... 118 Watch-Dog Timer Operation ........................................................................................................... 120 vi CHAPTER 11 16-BIT I/O TIMER ...................................................................................... 121 11.1 Outline of 16-Bit I/O Timer ............................................................................................................... 122 11.2 16-Bit I/O Timer Registers ............................................................................................................... 124 11.3 16-bit Free-run Timer ....................................................................................................................... 125 11.3.1 Data Register .............................................................................................................................. 126 11.3.2 Control Status Register .............................................................................................................. 127 11.3.3 Operation of 16-bit Free-run Timer ............................................................................................. 129 11.4 Output Compare .............................................................................................................................. 131 11.4.1 Output Compare Register Details ............................................................................................... 132 11.4.2 Control Status Register of Output Compare ............................................................................... 133 11.4.3 16-bit Output Compare Operation .............................................................................................. 136 11.5 Input Capture ................................................................................................................................... 138 11.5.1 Input Capture Register Details ................................................................................................... 140 11.5.2 16-bit Input Capture Operation ................................................................................................... 142 CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) ................ 145 12.1 Outline of 16-bit Reload Timer (with Event Count Function) ........................................................... 146 12.2 Registers of 16-bit Reload Timer ..................................................................................................... 147 12.2.1 Timer Control Status Register (TMCSR) .................................................................................... 148 12.2.2 Register Layout of 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR) .................... 151 12.3 Internal Clock Operation and External Clock Operation of 16-bit Reload Timer ............................. 152 12.4 Underflow Operation of 16-bit Reload Timer ................................................................................... 154 12.5 Output Pin Functions of 16-bit Reload Timer .................................................................................. 155 12.6 Counter Operation State .................................................................................................................. 156 CHAPTER 13 8/16-BIT PPG ............................................................................................ 157 13.1 Outline of 8/16-bit PPG .................................................................................................................... 158 13.2 8/16-bit PPG Block Diagrams .......................................................................................................... 159 13.3 8/16-bit PPG Registers .................................................................................................................... 161 13.3.1 PPG0 Operation Mode Control Register (PPGC0) ..................................................................... 162 13.3.2 PPG1 Operation Mode Control Register (PPGC1) ..................................................................... 164 13.3.3 PPG0, 1 Output Pin Control Register (PPG01) .......................................................................... 166 13.3.4 Reload Registers (PRLL, PRLH) ................................................................................................ 168 13.4 8/16-bit PPG Operation ................................................................................................................... 169 13.5 Count Clock Selection of 8/16-bit PPG ............................................................................................ 171 13.6 Pulse Pin Output Control of 8/16-bit PPG ....................................................................................... 172 13.7 Interrupts of 8/16-bit PPG ................................................................................................................ 173 13.8 Default Values of Hardware Components of 8/16-bit PPG .............................................................. 174 CHAPTER 14 DTP/EXTERNAL INTERRUPTS ............................................................... 177 14.1 14.2 14.3 14.4 14.5 Outline of DTP/External Interrupt .................................................................................................... 178 DTP/External Interrupt Registers ..................................................................................................... 180 Operations of DTP/External Interrupts ............................................................................................ 182 Switching between External Interrupt and DTP Requests ............................................................... 184 Notes on Use of DTP/External Interrupts ........................................................................................ 185 vii CHAPTER 15 A/D CONVERTER ..................................................................................... 187 15.1 Features of A/D Converter .............................................................................................................. 15.2 A/D Converter Block Diagram ......................................................................................................... 15.3 A/D Converter Registers ................................................................................................................. 15.3.1 Control Status Registers (ADCS0) ............................................................................................ 15.3.2 Control Status Register (ADCS1) .............................................................................................. 15.3.3 Data Registers (ADCR0, ADCR1) ............................................................................................. 15.4 A/D Converter Operation ................................................................................................................ 15.5 Conversion Using EI2OS ................................................................................................................ 15.5.1 Example of EI2OS Activation in Single Mode ............................................................................ 15.5.2 Example of EI2OS Activation in Continuous Mode .................................................................... 15.5.3 Example of EI2OS Activation in Stop Mode ............................................................................... 15.6 Conversion Data Protection ............................................................................................................ 188 190 191 192 195 197 199 201 202 204 206 208 CHAPTER 16 UART0 ...................................................................................................... 211 16.1 UART0 ............................................................................................................................................ 16.2 Block Diagram of UART0 ................................................................................................................ 16.3 Registers of UART0 ........................................................................................................................ 16.3.1 Serial Mode Control Register 0 (UMC0) .................................................................................... 16.3.2 Status Register 0 (USR0) .......................................................................................................... 16.3.3 Input Data Register 0 (UIDR0 ) and Output Data Register 0 (UODR0) ..................................... 16.3.4 Rate and Data Register 0 (URD0) ............................................................................................. 16.4 Operations of UART0 ...................................................................................................................... 16.5 Baud Rate ....................................................................................................................................... 16.6 Internal and External Clock ............................................................................................................. 16.7 Transfer Data Format ...................................................................................................................... 16.8 Parity Bit .......................................................................................................................................... 16.9 Interrupt Generation and Flag Set Timings ..................................................................................... 16.9.1 Flag Setting Timing in Receive Mode (Mode 0, Mode 1, Or Mode 3) ........................................ 16.9.2 Flag Setting Timing in Receive Mode (mode 2) ......................................................................... 16.9.3 Flag Setting Timing in Send Mode ............................................................................................. 16.9.4 Status Flag in Transmit/receive Mode ....................................................................................... 16.10 UART0 Application Example ........................................................................................................... 212 213 214 215 217 219 220 222 223 226 227 228 229 230 231 232 233 234 CHAPTER 17 UART1 (SCI) ............................................................................................. 237 17.1 Features of UART1 ......................................................................................................................... 17.2 UART1 Block Diagram .................................................................................................................... 17.3 UART1 Registers ............................................................................................................................ 17.3.1 Serial Mode Register 1 (SMR1) ................................................................................................. 17.3.2 Serial Control Register 1 (SCR1) ............................................................................................... 17.3.3 Serial Input Data Register 1 (SIDR1) / Serial Output Data Register 1 (SODR1) ....................... 17.3.4 Serial Status Register 1 (SSR1) ................................................................................................ 17.3.5 UART1 Prescaler Control Register (U1CDCR) ......................................................................... 17.4 UART1 Operating Modes and Clock Selection ............................................................................... 17.4.1 Asynchronous (Start-Stop Synchronized) Mode ........................................................................ 17.4.2 CLK Synchronous Mode ............................................................................................................ 17.5 UART1 Flags and Interrupt Sources ............................................................................................... 17.6 UART1 Interrupts and Flag Set Timing ........................................................................................... viii 238 239 240 241 243 245 246 248 249 252 253 255 256 17.7 UART1 Sample Applications and Precautionary Information .......................................................... 259 CHAPTER 18 SERIAL I/O ................................................................................................ 261 18.1 Outline of Serial I/O ......................................................................................................................... 262 18.2 Serial I/O Registers ......................................................................................................................... 263 18.2.1 Serial Mode Control Status Register (SMCS) ............................................................................ 264 18.2.2 Serial Shift Data Register (SDR) ................................................................................................ 268 18.3 Serial I/O Prescaler (SCDCR) ......................................................................................................... 269 18.4 Serial I/O Operation ......................................................................................................................... 270 18.4.1 Shift Clock .................................................................................................................................. 271 18.4.2 Serial I/O Operation Status ......................................................................................................... 272 18.4.3 Shift Operation Start/stop Timing ............................................................................................... 274 18.4.4 Interrupt Function of Extended Serial I/O Interface .................................................................... 277 18.5 Negative Clock Operation ................................................................................................................ 278 CHAPTER 19 CAN CONTROLLER ................................................................................. 279 19.1 Features of CAN Controller ............................................................................................................. 280 19.2 CAN Controller Block Diagram ........................................................................................................ 281 19.3 List of Total Control Registers ......................................................................................................... 282 19.4 List of Message Buffers (ID Registers) ............................................................................................ 284 19.5 List of Message Buffers (DLC Registers and Data Registers) ........................................................ 287 19.6 Classification of CAN Control Registers .......................................................................................... 290 19.6.1 Control Status Register (CSR) ................................................................................................... 291 19.6.2 Bus Operation Stop Bit (HALT = 1) ............................................................................................ 294 19.6.3 Last Event Indicator Register (LEIR) .......................................................................................... 295 19.6.4 Receive and Transmit Error Counters (RTEC) ........................................................................... 297 19.6.5 Bit Timing Register (BTR) ........................................................................................................... 298 19.6.6 Message Buffer Control Registers (BVALR) .............................................................................. 301 19.6.7 IDE Register (IDER) ................................................................................................................... 302 19.6.8 Transmission Request Register (TREQR) ................................................................................. 303 19.6.9 Transmission RTR Register (TRTRR) ........................................................................................ 304 19.6.10 Remote Frame Receiving Wait Register (RFWTR) .................................................................... 305 19.6.11 Transmission Cancel Register (TCANR) .................................................................................... 306 19.6.12 Transmission Complete Register (TCR) ..................................................................................... 307 19.6.13 Transmission Interrupt Enable Register (TIER) .......................................................................... 308 19.6.14 Reception Complete Register (RCR) ......................................................................................... 309 19.6.15 Remote Request Receiving Register (RRTRR) ......................................................................... 310 19.6.16 Receive Overrun Register (ROVRR) .......................................................................................... 311 19.6.17 Reception Interrupt Enable Register (RIER) .............................................................................. 312 19.6.18 Acceptance Mask Select Register (AMSR) ................................................................................ 313 19.6.19 Acceptance Mask Registers 0 and 1 (AMR0/AMR1) .................................................................. 315 19.6.20 Message Buffers ......................................................................................................................... 317 19.6.21 ID Register x (x = 0 to 15) (IDRx) ............................................................................................... 318 19.6.22 DLC Register x (x = 0 to 15) (DLCRx) ........................................................................................ 320 19.6.23 Data Register x (x = 0 to 15) (DTRx) .......................................................................................... 321 19.7 Transmission under CAN Controller ................................................................................................ 323 19.8 Reception under CAN Controller ..................................................................................................... 325 19.9 CAN Controller Reception Flowchart ............................................................................................... 327 ix 19.10 19.11 19.12 19.13 19.14 Usage of CAN Controller ................................................................................................................ Procedure for Transmission by Message Buffer (x) ........................................................................ Procedure for Reception by Message Buffer (x) ............................................................................. Deciding Multi-level Message Buffer Configuration ........................................................................ Precautions when Using CAN Controller ........................................................................................ 328 330 332 334 336 CHAPTER 20 STEPPING MOTOR CONTROLLER ........................................................ 337 20.1 Outline of Stepping Motor Controller ............................................................................................... 20.2 Stepping Motor Controller Registers ............................................................................................... 20.2.1 PWM Control 0 Register ............................................................................................................ 20.2.2 PWM1 and PWM2 Compare Registers ..................................................................................... 20.2.3 PWM1 and PWM2 Select Registers .......................................................................................... 338 339 340 341 342 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION .......................................... 345 21.1 21.2 21.3 21.4 Outline of the Address Match Detection Function ........................................................................... Registers of the Address Match Detection Function ....................................................................... Operation of the Address Match Detection Function ...................................................................... Example of the Address Match Detection Function ........................................................................ 346 347 349 350 CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE .......................... 353 22.1 22.2 Outline of ROM Mirroring Function Selection Module ..................................................................... 354 ROM Mirroring Function Selection Register (ROMM) ..................................................................... 355 CHAPTER 23 1M-BIT FLASH MEMORY ........................................................................ 357 23.1 Outline of 1M-Bit Flash Memory ..................................................................................................... 23.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory .......... 23.3 Write/Erase Modes ......................................................................................................................... 23.4 Flash Memory Control Status Register (FMCS) ............................................................................. 23.5 Starting the Flash Memory Automatic Algorithm ............................................................................. 23.6 Confirming the Automatic Algorithm Execution State ..................................................................... 23.6.1 Data Polling Flag (DQ7) ............................................................................................................. 23.6.2 Toggle Bit Flag (DQ6) ................................................................................................................ 23.6.3 Timing Limit Exceeded Flag (DQ5) ............................................................................................ 23.6.4 Sector Erase Timer Flag (DQ3) ................................................................................................. 23.6.5 Toggle Bit-2 Flag (DQ2) ............................................................................................................. 23.7 Detailed Explanation of Writing to and Erasing Flash Memory ....................................................... 23.7.1 Setting Flash Memory to the Read/reset State .......................................................................... 23.7.2 Writing Data to Flash Memory ................................................................................................... 23.7.3 Erasing All Data (Erasing Chips) of Flash Memory ................................................................... 23.7.4 Erasing Optional Data (Erasing Sectors) in Flash Memory ....................................................... 23.7.5 Suspending Sector Erase of Flash Memory .............................................................................. 23.7.6 Restarting Sector Erase of Flash Memory ................................................................................. 23.8 Notes on Using 1M-bit Flash Memory ............................................................................................. 23.9 Reset Vector Address in Flash Memory ......................................................................................... 23.10 Flash Security Feature .................................................................................................................... 23.11 Example of the 1M-Bit Flash Memory Program .............................................................................. x 358 360 362 364 366 368 370 372 373 374 375 377 378 379 381 382 384 385 386 388 389 390 CHAPTER 24 EXAMPLES OF F2MC-16LX MB90F598/F598G SERIAL PROGRAMMING CONNECTION .......................................................................................... 395 24.1 24.2 24.3 24.4 24.5 Basic Configuration of F2MC-16LX MB90F598/F598G Serial Programming Connection ............... 396 Example of Serial Programming Connection (User Power Supply Used) ....................................... 400 Example of Serial Programming Connection (Power Supplied from the Programmer) ................... 402 Example of Minimum Connection to the Flash Microcontroller Programmer (User Power Supply Used) .............................................................................................................. 404 Example of Minimum Connection to the Flash Microcontroller Programmer (Power Supplied from the Programmer) ........................................................................................... 406 APPENDIX .......................................................................................................................... 409 APPENDIX A I/O Maps ............................................................................................................................ 410 APPENDIX B Instructions ............................................................................................................................ 419 B.1 Instruction Types ............................................................................................................................. 420 B.2 Addressing ...................................................................................................................................... 421 B.3 Direct Addressing ............................................................................................................................ 423 B.4 Indirect Addressing ......................................................................................................................... 429 B.5 Execution Cycle Count .................................................................................................................... 437 B.6 Effective Address Field ................................................................................................................... 440 B.7 How to Read the Instruction List ..................................................................................................... 441 B.8 F2MC-16LX Instruction List ............................................................................................................. 444 B.9 Instruction Map ................................................................................................................................ 458 APPENDIX C Timing Diagrams in Flash Memory Mode ............................................................................. 480 APPENDIX D List of MB90595 Interrupt Vectors ........................................................................................ 485 INDEX ...................................................................................................................................489 xi xii Main changes in this edition Page Section Changes (For details, refer to main body.) 14 CHAPTER 1 OVERVIEW 1.8 Handling Device ❍ Stabilization of power supply voltage was added. 78 CHAPTER 5 CLOCK AND RESET 5.2 Reset Cause Occurrence Table 5.2-2 Registers not Initialized by Reset Input was changed. 92 CHAPTER 6 LOW-POWER CONTROL CIRCUIT 6.3 Low-Power Mode Operation Table 6.3-2 List of Instructions Used for Transition to Low-power Mode was changed. 186 CHAPTER 14 DTP/EXTERNAL INTERRUPTS 14.5 Notes on Use of DTP/External Interrupts ❍ External interrupt request level was changed. CHAPTER15 A/D CONVERTER ■ Example of EI2OS Activation in Single Mode was changed. 202 15.5.1 Example of in Single Mode 204 EI2OS Figure 14.5-1 Interrupt Request Flag Bit (EIRR:ER) upon Level Set was changed. Activation CHAPTER15 A/D CONVERTER ■ Example of EI2OS Activation in Continuous Mode was changed. 15.5.2 Example of EI2OS Activation in Continuous Mode 206 CHAPTER15 A/D CONVERTER ■ Example of EI2OS Activation in Stop Mode was changed. 2 15.5.3 Example of EI OS Activation in Stop Mode 291 CHAPTER 19 CAN CONTROLLER 19.6.1 Control Status Register (CSR) 19.6.1 Control Status Register (CSR) was changed. 293 CHAPTER 19 CAN CONTROLLER 19.6.1 Control Status Register (CSR) [bit0] HALT: Bus operation stop bit was changed. 294 CHAPTER 19 CAN CONTROLLER 19.6.2 Bus Operation Stop Bit (HALT = 1) ■ Conditions for Canceling Bus Operation Stop (HALT = 0) was changed. "When 0 is written to HALT bit during the node status is Bus Off, ensure that 1 is written to this bit." was added. 383 CHAPTER 23 1M-BIT FLASH MEMORY Figure 23.7-2 Example of the Flash Memory Sector Erase Procedure 23.7.4 Erasing Optional Data (Erasing was changed. Sectors) in Flash Memory 444 APPENDIX B Instructions Table B.8-1 41 Transfer Instructions (Byte) was changed. 2 B.8 F MC-16LX Instruction List 445 APPENDIX B Instructions 2 B.8 F MC-16LX Instruction List 456 APPENDIX B Instructions 2 B.8 F MC-16LX Instruction List Table B.8-2 38 Transfer Instructions (Word, Long Word) was changed. Table B.8-17 6 Accumulator Operation Instructions (Byte, Word) was changed. The vertical lines marked in the left side of the page show the changes. xiii xiv CHAPTER 1 OVERVIEW CHAPTER 1 OVERVIEW The MB90595 Series is a family member of the F2MC-16LX microcontrollers. 1.1 "Product Overview" 1.2 "Features" 1.3 "Block Diagram" 1.4 "Pin Assignment" 1.5 "Package Dimensions" 1.6 "Pin Functions" 1.7 "Input/Output Circuits" 1.8 "Handling Device" 1 CHAPTER 1 OVERVIEW 1.1 Product Overview The following table provides a quick outlook of the MB90595 Series ■ Overview Table 1.1-1 Overview Features MB90V595/V595G F2MC-16LX CPU CPU System clock MB90598 MB90598G MB90F598/F598G On-chip PLL clock multiplier (x1, x2, x3, x4, 1/2 when PLL stop) Minimum instruction execution time: 62.5 ns (4 MHz osc. PLL x4) Boot-block Flash memory 128 Kbytes Hard-wired reset vector ROM External RAM 6 Kbytes Package PGA-256 QFP100 None - Emulatorspecific power supply * Mask ROM 128 Kbytes 4 Kbytes 4 Kbytes *: It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used. Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details. Note: With the product with G-suffix at the end of part numbers, functionality the CAN controller is enhanced. Please refer to the description of the Bit Timing Register in the CAN chapter. 2 CHAPTER 1 OVERVIEW 1.2 Features Table 1.2-1 lists the features of the MB90595 series. ■ Features Table 1.2-1 MB90595 Features (1/2) Function Feature UART0 Full duplex double buffer Supports asynchronous/synchronous (with start/stop bit) transfer Baud rate: 4808/5208/9615/10417/19230/38460/62500/500000bps (asynchronous) 500K/1M/2Mbps (synchronous) at System clock = 16 MHz UART1 (SCI) Full duplex double buffer Asynchronous (start-stop synchronized) and CLK-synchronous communication Baud rate: 1202/2404/4808/9615/31250bps (asynchronous) 62.5k/125k/250k/500k/1Mbps (synchronous) at 6,8,10,12,16 MHz Serial I/O Transfer can be started from MSB or LSB Supports internal clock synchronized transfer and external clock synchronized transfer Supports positive-edge and negative-edge clock synchronization Baud rate : 31.25k/62.5k/125k/500k/1M/2Mbps at System clock = 16 MHz A/D Converter 10-bit or 8-bit resolution 8 input channels Conversion time: 26.3µs (per one channel) 16-bit Reload Timer (2 channels) Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = Sysem clock frequency) Supports External Event Count function 16-bit I/O Timer Signals an interrupt when overflow Supports Timer Clear when a match with Output Compare (Channel 0) Operation clock freq.: fsys/22, fsys/24, fsys/26, fsys/28 (fsys = System clock freq.) 16-bit Output Compare (4 channels) Signals an interrupt when a match with 16-bit I/O Timer Four 16-bit compare registers A pair of compare registers can be used to generate an output signal 16-bit Input Capture (4 channels) Rising edge, falling edge or rising & falling edge sensitive Four 16-bit Capture registers Signals an interrupt upon external event 3 CHAPTER 1 OVERVIEW Table 1.2-1 MB90595 Features (2/2) Function Feature 8/16-bit Programmable Pulse Generator (6 channels) Supports 8-bit and 16-bit operation modes Twelve 8-bit reload counters Twelve 8-bit reload registers for L pulse width Twelve 8-bit reload registers for H pulse width A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter 6 output pins Operation clock freq.: fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128µs@fosc = 4 MHz (fsys = System clock frequency, fosc = Oscillation clock frequency) CAN Interface Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Prioritized 16 message buffers for data and ID's Supports multiple messages Flexible configuration of acceptance filtering: Full bit compare / Full bit mask / Two partial bit masks Supports up to 1Mbps Stepping Motor Controller (4 channels) Four high current outputs for each channel Synchronized two 8-bit PWM's for each channel Succeeds to MB89940 design resource External Interrupt (8 channels) Either edge detection or level detection can be specified. I/O Ports Virtually all external pins can be used as general purpose I/O All push-pull outputs and schmitt trigger inputs Bit-wise programmable as input/output or peripheral signal Flash Memory Supports automatic programming, Embedded AlgorithmTM * Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of erase cycles: 10,000 times Data retention time: 10 years Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory Boot block configuration Erase can be performed on each block * : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc. 4 CHAPTER 1 OVERVIEW 1.3 Block Diagram Figure 1.3-1 shows a block diagram of the MB90595 series. ■ Block Diagram Figure 1.3-1 Block Diagram X0,X1 RST HST Clock Controller 16LX CPU IO Timer RAM 4K ROM/Flash 128K Input Capture 4ch IN[3:0] Output Compare 4ch OUT[3:0] 8/16-bit PPG 6ch PPG[5:0] Prescaler SOT0 SCK0 SIN0 UART0 CAN Controller Prescaler SOT1 SCK1 SIN1 UART1 (SCI) 16-bit Reload Timer 2ch RX TX TIN[1:0] TOT[1:0] SOT2 SCK2 SIN2 AVCC AVSS AN[7:0] AVRH AVRL ADTG Serial I/O 10-bit ADC 8ch FMC-16 Bus Prescaler SMC 4ch External Interrupt 8ch PWM1M[3:0] PWM1P[3:0] PWM2M[3:0] PWM2P[3:0] DVCC[1:0] DVSS[2:0] INT[7:0] 5 CHAPTER 1 OVERVIEW 1.4 Pin Assignment Figure 1.4-1 shows the pin assignments of the MB90595 series. ■ Pin Assignment 81 X1 Vcc P00/IN0 83 84 85 86 6 MD2 P72/PWM2P0 P71/PWM1M0 P70/PWM1P0 DVss HST P73/PWM2M0 P77/PWM2M1 P76/PWM2P1 P75/PWM1M1 P74/PWM1P1 DVcc 41 40 39 38 37 36 35 34 97 P50/SIN2 P51/INT4 P52/INT5 P47/SCK2 C P46/SOT2 Vcc P45/SOT1 P44/SCK1 P41/SCK0 P42/SIN0 P43/SIN1 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P20 P21 P22 P23 P24 P17/TOT1 42 95 96 P40/SOT0 P12/PPG2 P13/PPG3 P14/PPG4 P15/PPG5 P16/TIN1 43 Packagecode (mold) FPT-100P-M06 P33 P11/PPG1 48 47 46 45 44 QFP - 100 89 90 91 92 93 94 P34 P35 P36 P37 P05/OUT1 P06/OUT2 P07/OUT3 P10/PPG0 87 88 P25 P26 P27 P30 P31 Vss P32 P03/IN3 P04/OUT0 P83/PWM2M2 P82/PWM2P2 P81/PWM1M2 P80/PWM1P2 DVss 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 82 Vss X0 P01/IN1 P02/IN2 P87/PWM2M3 P86/PWM2P3 P85/PWM1M3 P84/PWM1P3 DVcc P95/INT3 P94/INT2 P93/INT1 RST P92/INT0 P91/RX P90/TX DVss Figure 1.4-1 Pin Assignment MD1 MD0 P57/TOT0 P56/TIN0 P67/AN7 P66/AN6 P65/AN5 P64/AN4 Vss P63/AN3 P62/AN2 P61/AN1 P60/AN0 AVss AVRL AVRH AVcc P55/ADTG P54/INT7 P53/INT6 CHAPTER 1 OVERVIEW 1.5 Package Dimensions Figure 1.5-1 shows the package dimensions of the MB90595 series. Note that the dimensions show below are reference dimensions. For formal dimensions of each package, contact us. ■ Package Dimensions Figure 1.5-1 Package Dimensions 100-pin plastic QFP Lead pitch 0.65 mm Package width × package length 14.00 × 20.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 3.35 mm MAX Code (Reference) P-QFP100-14×20-0.65 (FPT-100P-M06) 100-pin plastic QFP (FPT-100P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 80 51 81 50 0.10(.004) 17.90±0.40 (.705±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 100 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8° 31 1 30 0.65(.026) 0.32±0.05 (.013±.002) 0.13(.005) M 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) "A" C 2002 FUJITSU LIMITED F100008S-c-5-5 0.25±0.20 (.010±.008) (Stand off) Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 7 CHAPTER 1 OVERVIEW 1.6 Pin Functions Table 1.6-1 lists the pin functions of the MB90595 series. ■ Pin Functions Table 1.6-1 Pin Functions (1/3) No. Pin name 82 X0 83 X1 77 RST B Reset input 52 HST C Hardware standby input 85 to 88 P00 to P03 IN0 to IN3 Circuit type A G P04 to P07 89 to 92 OUT0 to OUT3 99 100 P16 TIN1 P17 TOT1 Oscillator pin General purpose I/O Inputs for the Input Captures Outputs for the Output Compares. General purpose I/O D D D Outputs for the Programmable Pulse Generators General purpose I/O TIN input for the 16-bit Reload Timer 1 General purpose I/O TOT output for the 16-bit Reload Timer 1 1 to 8 P20 to P27 G General purpose I/O 9 to 10 P30 to P31 G General purpose I/O 12 to 16 P32 to P36 G General purpose I/O 17 P37 D General purpose I/O 18 19 20 21 8 PPG0 to PPG5 Oscillator pin General purpose I/O G P10 to P15 93 to 98 Function P40 SOT0 P41 SCK0 P42 SIN0 P43 SIN1 G G G G General purpose I/O SOT output for UART 0 General purpose I/O SCK input/output for UART 0 General purpose I/O SIN input for UART 0 General purpose I/O SIN input for UART 1 CHAPTER 1 OVERVIEW Table 1.6-1 Pin Functions (2/3) No. 22 24 25 26 28 29 to 32 Pin name P44 SCK1 P45 SOT1 P46 SOT2 P47 SCK2 P50 SIN2 P51 to P54 INT4 to INT7 Circuit type G G G G D D P55 33 38 to 41 43 to 46 47 48 ADTG P60 to P63 AN0 to AN3 P64 to P67 AN4 to AN7 P56 TIN0 P57 TOT0 PWM1P0 PWM1M0 PWM2P0 PWM2M0 D E E D D PWM1P1 PWM1M1 PWM2P1 PWM2M1 F PWM1P2 PWM1M2 PWM2P2 PWM2M2 General purpose I/O SOT output for UART 1 General purpose I/O SOT output for the Serial I/O General purpose I/O SCK input/output for the Serial I/O General purpose I/O SIN Input for the Serial I/O General purpose I/O External interrupt input for INT4 to INT7 Input for the external trigger of the A/D Converter General purpose I/O Inputs for the A/D Converter General purpose I/O Inputs for the A/D Converter General purpose I/O TIN input for the 16-bit Reload Timer 0 General purpose I/O TOT output for the 16-bit Reload Timer 0 Output for Stepping Motor Controller channel 0 General purpose I/O F P80 to P83 64 to 67 SCK input/output for UART 1 General purpose I/O P74 to P77 59 to 62 General purpose I/O General purpose I/O P70 to P73 54 to 57 Function Output for Stepping Motor Controller channel 1 General purpose I/O F Output for Stepper Motor Controller channel 2 9 CHAPTER 1 OVERVIEW Table 1.6-1 Pin Functions (3/3) No. Pin name Circuit type P84 to P87 69 to 72 74 75 76 78 to 80 10 PWM1P3 PWM1M3 PWM2P3 PWM2M3 P90 TX P91 RX P92 INT0 P93 to P95 INT1 to INT3 Function General purpose I/O F D D D D Output for Stepper Motor Controller channel 3 General purpose I/O TX output for CAN Interface General purpose I/O RX input for CAN Interface General purpose I/O External interrupt input for INT0 General purpose I/O External interrupt input for INT1 to INT3 58 68 DVCC - Dedicated power supply pins for the high current output buffers (Pin No. 54 to 72) 53 63 73 DVSS - Dedicated ground pins for the high current output buffers (Pin No. 54 to 72) 34 AVCC - Dedicated power supply pin for the A/D Converter 37 AVSS - Dedicated ground pin for the A/D Converter 35 AVRH - Upper reference voltage input for the A/D Converter 36 AVRL - Lower reference voltage input for the A/D Converter 49 50 MD0 MD1 C Test mode inputs. These pins should be connected to VCC 51 MD2 H Test mode input. This pin should be connected to VSS 27 C - External capacitor pin. A capacitor of 0.1 µF should be connected to this pin and VSS. 23 84 VCC - Power supply pins 11 42 81 VSS - Ground pins CHAPTER 1 OVERVIEW 1.7 Input/Output Circuits Table 1.7-1 shows input/output circuits. ■ Input/Output Circuits Table 1.7-1 Input/Output Circuits (1/3) Circuit type Diagram Remarks A • Oscillation feedback resistor: 1 MΩ approx. • Hysteresis input with pull-up resistor Pull-up resistor: 50 kΩ approx. • Hysteresis input • • CMOS output Hysteresis input X1 Oscillation feedback resistor Clock pulse input X0 Hard, soft standby control B R (pull-up) HYS R C HYS R D P-ch N-ch R HYS 11 CHAPTER 1 OVERVIEW Table 1.7-1 Input/Output Circuits (2/3) Circuit type Diagram Remarks E • • • CMOS output Hysteresis input Analog input • • CMOS high current output Hysteresis input • • • CMOS output Hysteresis input TTL input (MB90F598/F598G, only in flash mode) P-ch N-ch P-ch Analog input N-ch R HYS F High current HYS R G P-ch N-ch R HYS R T 12 TTL CHAPTER 1 OVERVIEW Table 1.7-1 Input/Output Circuits (3/3) Circuit type Diagram Remarks H • R HYS • Hysteresis input with pull-down resistor Pull-down resistor: 50 kΩ approx. No pull-down resistor in Flash R (pull-down) 13 CHAPTER 1 OVERVIEW 1.8 Handling Device When handling devices, be careful about the following: • Preventing latch-up • Stabilization of power supply voltage • Treatment of unused pins • Using external clock • Power supply input pins (VCC/VSS) • • • • • • • • • • • Pull-up/down resistors Crystal Oscillator Circuit Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Processing of Unused Pins of A/D Converter N.C. Pin Notes on Energization Initialization Indeterminate outputs from ports 0 and 1 (MB90598/F598/V595/V595G only) Using the "DIV A,Ri" and "DIVW A, RWi" instructions Using REALOS Notes on during operation of PLL clock mode ■ Handling Device ❍ Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions: • A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between VCC and VSS. • The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. ❍ Stabilization of power supply voltage If the power supply voltage varies acutely even within the operation assurance range of the VCC power supply voltage, a malfunction may occur. The VCC power supply voltage must therefore be stabilized. As stabilization guidelines, control the power supply voltage so that VCC ripple fluctuations (peak to peak value) in the commercial frequencies (50 Hz to 60 Hz) fall within 10% of the standard VCC power supply voltage and the transient fluctuation rate becomes 0.1V/ms or less in instantaneous fluctuation for power supply switching. 14 CHAPTER 1 OVERVIEW ❍ Treatment of unused pins Unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. Unused input pins should be pulled up or pulled down through at least at 2 kΩ resistance. Unused input/output pins may be left open in output state, but if such pins are in input state they should be handled in the same way as input pins. ❍ Using external clock To use external clock, drive the X0 pin and leave X1 pin open. Figure 1.8-1 is a diagram of how to use external clock. Figure 1.8-1 Using External Clock MB90595 Series X0 X1 Open ❍ Power supply pins (VCC/VSS) Ensure that all VCC-level power supply pins are at the same potential. In addition, ensure the same for all VSS-level power supply pins. (See the Figure 1.8-2 ). If there are more than one VCC or VSS system, the device may operate incorrectly even within the guaranteed operating range. Figure 1.8-2 Power Supply Pins (VCC/VSS) Vcc Vss Vcc Vss Vss Vcc MB90595 Series Vcc Vss Vss Vcc ❍ Pull-up/down resistors The MB90595 Series does not support internal pull-up/down resistors. Use external components where needed. 15 CHAPTER 1 OVERVIEW ❍ Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground area for stabilizing the operation. ❍ Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable). ❍ Connection of Unused Pins of A/D Converter Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS. ❍ N.C. Pin The N.C. (internally connected) pin must be opened for use. ❍ Notes on Energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 or more µs (0.2 V to 2.7 V) ❍ Initialization In the device, there are internal registers which is initialized only by a power-on reset. To initialize these registers turning on the power again. ❍ Indeterminate outputs from ports 0 and 1 (MB90598/F598/V595/V595G only) During oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on, the outputs from ports 0 and 1 become following state. • If RST pin is "H", the outputs become indeterminate. • If RST pin is "L", the outputs become high-impedance. Pay attention to the port output timing shown as follow 16 CHAPTER 1 OVERVIEW Figure 1.8-3 Indeterminate Output from Ports 0 and 1 (RST Pin is "H") Oscillation setting time Power-on reset Vcc (Power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal KB (internal operation clock B) signal PORT (port output) signal Period of indeterminated *1: Power-on reset time: Period of " 217/clock frequency " (Clock frequency of 16 MHz: 8.19 ms) *2: Oscillation setting time: Period of " 218/clock frequency " (Clock frequency of 16 MHz: 16.38ms) Figure 1.8-4 High-impedance Output from Ports 0 and 1 (RST Pin is "L") Oscillation setting time Power-on reset Vcc (Power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal KB (internal operation clock B) signal PORT (port output) signal High-impedance *1: Power-on reset time: Period of " 217/clock frequency " (Clock frequency of 16 MHz: 8.19 ms) *2: Oscillation setting time: Period of " 218/clock frequency " (Clock frequency of 16 MHz: 16.38ms) ❍ Using the "DIV A, Ri" and "DIVW A, RWi" instructions Before using the multiplication and division instructions using signs ("DIV A, Ri" and "DIVW A, RWi"), set "00H" in the corresponding bank registers (DTB, ADB, USB, and SSB). If the corresponding bank registers (DTB, ADB, USB, and SSB) are set to other than "00H", the remainder in the execution results of the instruction is not stored in the register of the instruction operand. For more information, see Section "2.11 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions". 17 CHAPTER 1 OVERVIEW ❍ Using REALOS The use of EI2OS is not possible with the REALOS real time operating system. ❍ Notes on during operation of PLL clock mode On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs. 18 CHAPTER 2 CPU CHAPTER 2 CPU This chapter explains the CPU. 2.1 "Outline of CPU" 2.2 "Memory Space" 2.3 "Memory Space Map" 2.4 "Linear Addressing Mode" 2.5 "Bank Addressing Types" 2.6 "Multi-byte Data in Memory Space" 2.7 "Registers" 2.8 "Register Bank" 2.9 "Prefix Codes" 2.10 "Interrupt Disable Instructions" 2.11 "Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions" 19 CHAPTER 2 CPU 2.1 Outline of CPU The F2MC-16LX CPU core is a 16-bit CPU designed for applications that require highspeed real-time processing, such as home-use or vehicle-mounted electronic appliances. The F2MC-16LX instruction set is designed for controller applications, and is capable of high-speed, highly efficient control processing. ■ Outline of CPU The F2MC-16LX CPU core can process 32-bit data by using an internal 32-bit accumulator. (32bit data can be processed with some instructions.) Up to 16 Mbytes of memory space (expandable) can be used, which can be accessed by either the linear pointer or bank method. The instruction system, based on the F2MC-8 AT architecture, has been reinforced by adding instructions compatible with high-level languages, expanding addressing modes, reinforcing multiplication and division instructions, and enhancing bit processing. The features of the F2MC-16LX CPU are explained below. ❍ Minimum instruction execution time 62.5 ns (at 4-MHz oscillation, 4 times clock multiplication) ❍ Maximum memory space 16 Mbytes, accessed in linear or bank mode ❍ Instruction set optimized for controller applications • Rich data types: Bit, byte, word, long word • Extended addressing modes: 23 types • High-precision operation (32-bit length) based on 32-bit accumulator ❍ Powerful interrupt functions Eight priority levels (programmable) ❍ CPU-independent automatic transfer Up to 16 channels of the extended intelligent I/O service ❍ Instruction set compatible with high-level language (C)/multitasking System stack pointer/instruction set symmetry/barrel-shift instructions ❍ Improved execution speed 4-byte queue 20 CHAPTER 2 CPU 2.2 Memory Space An F2MC-16LX CPU has a 16-Mbyte memory space. All data, program, and input and output managed by the F2MC-16LX CPU are located in this 16-Mbyte memory space. The CPU accesses the resources by indicating their addresses using a 24-bit address bus. ■ Outline of CPU Memory Space Figure 2.2-1 shows an example of the relationship between F2MC-16LX system and memory map. Figure 2.2-1 Sample Relationship between F2MC-16LX System and Memory Map F2MC-16LX CPU Program FFFFFFH FF8000H Data 810000H Interrupt 800000H Data area 0000C0H [Device] Program area Peripheral circuits 0000B0H Generalpurpose ports 000020H Interrupt controller Peripheral circuits General-purpose ports 000000H ■ Address Generation Types The F2MC-16LX CPU has the following two addressing modes: ❍ Linear addressing mode An entire 24-bit address is specified by an instruction. ❍ Bank addressing mode Eight high-order bits of an address are specified by an appropriate bank register while the remaining 16 bits of the address are specified by an instruction. 21 CHAPTER 2 CPU 2.3 Memory Space Map The memory space of the MB90595 Series is shown in Figure 2.3-1 . ■ Memory Space Map The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without using the far specification in the pointer declaration. For example, an attempt to access 00C000H accesses the value at FFC000H in ROM. The ROM area in bank FF exceeds 48 Kbytes, and its entire image cannot be shown in bank 00. The image between FF4000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF3FFFH is visible only in bank FF. Figure 2.3-1 Memory Space Map MB90V595/V595G FFFFFFH FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H 00FFFFH 004000H ROM (FF bank) ROM (FE bank) FF0000H FEFFFFH FE0000H ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (Image of FF bank) 001FFFH 001900H 0018FFH MB90F598/F598G/598 MB90598G 00FFFFH 004000H ROM (Image of FF bank) 001FFFH Peripheral RAM 6K 001900H Peripheral 0010FFH RAM 4K 000100H 0000BFH 000000H 22 000100H Peripheral 0000BFH 000000H Peripheral CHAPTER 2 CPU 2.4 Linear Addressing Mode Linear addressing includes two specification modes: • 24-bit operand specification: Specifies a 24-bit address directly by using an operand. • 32-bit register indirect specification: Specifies the 24 low-order bits of a 32-bit general-purpose register value as an address. ■ 24-bit Operand Specification Figure 2.4-1 shows an example of a 24-bit operand specification, and Figure 2.4-2 shows an example of a 32-bit register indirect specification. Figure 2.4-1 Example of Linear Method (24-bit Register Operand Specification) JMPP 123456H Old program counter + program bank 17 17452DH 452D JMPP 123456H 123456H New program counter + program bank 12 Next instruction 3456 Figure 2.4-2 Example of Linear Method (32-bit Register Indirect Specification) MOV A, @RL1+7 Old AL XXXX 090700H 3A RL1 240906F9 +7 (The high-order eight bits are ignored.) New AL 003A 23 CHAPTER 2 CPU 2.5 Bank Addressing Types In the bank method, the 16-Mbyte space is divided into 256 64-Kbyte banks. The following five bank registers are used to specify the banks corresponding to each space: • Program bank register (PCB) • Data bank register (DTB) • User stack bank register (USB) • System stack bank register (SSB) • Additional data bank register (ADB) ■ Bank Addressing Types ❍ Addressing by using the program bank register (PCB) The 64-Kbyte bank specified by the PCB is called a program (PC) space. The PC space contains instruction codes, vector tables, and immediate value data, for example. ❍ Addressing by using the data bank register (DTB) The 64-Kbyte bank specified by the DTB is called a data (DT) space. The DT space contains readable/writable data, and control/data registers for internal and external resources. ❍ Addressing by using the user stack bank register (USB) or system stack bank register (SSB) The 64-Kbyte bank specified by the USP or SSP is called a stack (SP) space. The SP space is accessed when a stack access occurs during a push/pop instruction or interrupt register saving. The S flag in the condition code register determines the stack space to be accessed. ❍ Addressing by using the additional data bank register (ADB) The 64-Kbyte bank specified by the ADB is called an additional (AD) space. The AD space, for example, contains data that cannot fit into the DT space. Table 2.5-1 lists the default spaces used in each addressing mode, which are pre-determined to improve instruction coding efficiency. To use a non-default space for an addressing mode, specify a prefix code corresponding to a bank before the instruction. This enables access to the bank space corresponding to the specified prefix code. After reset, the DTB, USB, SSB, and ADB are initialized to 00H. The PCB is initialized to a value specified by the reset vector. After reset, the DT, SP, and AD spaces are allocated in bank 00H (000000H to 00FFFFH), and the PC space is allocated in the bank specified by the reset vector. 24 CHAPTER 2 CPU Table 2.5-1 Default Space Default Space Addressing Mode Program space PC indirect, program access, branch Data space Addressing mode using @RW0, @RW1, @RW4, or @RW5, @A, addr16, and dir Stack space Addressing mode using PUSHW, POPW, @RW3, or @RW7 Additional space Addressing mode using @RW2 or @RW6 Figure 2.5-1 is an example of a memory space divided into register banks. Figure 2.5-1 Physical Addresses of Each Space FFFFFFH FF0000H Program space FFH : PCB (Program bank register) B3H : ADB (Additional data bank register) 92H : USB (User stack bank register) 68H : DTB (Data bank register) 4BH : SSB (System stack bank register) Physical address B3FFFFH B30000H 92FFFFH 920000H Additional space User stack space 68FFFFH 680000H Data space 4BFFFFH 4B0000H System stack space 000000H 25 CHAPTER 2 CPU 2.6 Multi-byte Data in Memory Space Data is written to memory in ascending order of addresses. For 32-bit data, for instance, 16 low-order bits are transferred first and then 16 high-order bits are transferred. If a reset signal is input immediately after low-order data is written, high-order data may not get written. ■ Multi-byte Data in Memory Space Figure 2.6-1 is a diagram of multi-byte data configuration in memory. The low-order eight bits of a data item are stored at address n, then address n+1, address n+2, address n+3, etc. Figure 2.6-1 Sample Allocation of Multi-byte Data in Memory MSB 01010101 H LSB 11001100 11111111 00010100 01010101 11001100 11111111 Address n 00010100 L ■ Accessing Multi-byte Data Fundamentally, accesses are made within a bank. For an instruction accessing a multi-byte data item, address FFFFH is followed by address 0000H of the same bank. Figure 2.6-2 is an example of an instruction accessing multi-byte data. Figure 2.6-2 Execution of MOVW A, 080FFFFH H 80FFFFH AL before execution ?? ?? AL after execution 23H 01H 01H • • • 800000H 23H L 26 CHAPTER 2 CPU 2.7 Registers The F2MC-16LX registers are largely classified into two types: Special registers in the CPU and general-purpose registers in memory. The special registers are dedicated internal hardware of the CPU, and they have specific use defined by the CPU architecture. The general-purpose registers share the CPU address space with RAM. The generalpurpose registers are the same as the special registers in that they can be accessed without using an address. The applications of the general-purpose registers can be specified by the user however, as is ordinary memory space. ■ Special Registers The F2MC-16LX CPU core has the following 13 special registers: • Accumulator (A=AH:AL): Two 16-bit accumulators (Can be used as a single 32-bit accumulator) • User stack pointer (USP): 16-bit pointer indicating the user stack area • System stack pointer (SSP): 16-bit pointer indicating the system stack area • Processor status (PS): 16-bit register indicating the system status • Program counter: 16-bit register holding the address of the program • Program bank register: 8-bit register indicating the PC space • Data bank register: 8-bit register indicating the DT space • User stack bank register (USB): 8-bit register indicating the user stack space • System stack bank register (SSB): 8-bit register indicating the system stack space • Additional data bank register (ADB): 8-bit register indicating the AD space • Direct page register (DPR): 8-bit register indicating a direct page Figure 2.7-1 is a diagram of the special registers. 27 CHAPTER 2 CPU Figure 2.7-1 Special Registers AH Accumulator AL User stack pointer USP System stack pointer SSP PS Processor status PC Program counter DPR Direct page register PCB Program bank register DTB Data bank register USB User stack bank register SSB System stack bank register ADB Additional data bank register 8 bit 16 bit 32 bit ■ General-purpose Registers The F2MC-16LX general-purpose registers are located from addresses 000180H to 00037FH (maximum configuration) of main storage. The register bank pointer (RP) indicates which of the above addresses are currently being used as a register bank. Each bank has the following three types of registers. These registers are mutually dependent as described in Figure 2.7-2 . • R0 to R7: 8-bit general-purpose register • RW0 to RW7: 16-bit general-purpose register • RL0 to RL3: 32-bit general-purpose register Figure 2.7-2 General-purpose Registers LSB MSB 16 bit 000180H + RP*10H RW0 Low-order First address of general-purpose register RL0 RW1 RW2 RL1 RW3 R1 R0 RW4 R3 R2 RW5 R5 R4 RW6 R7 R6 RW7 RL2 RL3 High-order The relationship between the high-order and low-order bytes of a byte or word register is expressed as follows: 28 CHAPTER 2 CPU RW (i+4) = R (i*2+1)*256+R (i*2) [i=0 to 3] The relationship between the high-order and low-order bytes of Rli and RW can be expressed as follows: RL (i) = RW (i*2+1)*65536+RW (i*2) [i=0 to 3] 29 CHAPTER 2 CPU 2.7.1 Accumulator (A) The A register consists of two 16-bit arithmetic operation registers (AH and AL). The A register is used as a temporary storage for operation results and transfer data. ■ Accumulator (A) During 32-bit data processing, AH and AL are used together. Only AL is used for word processing in 16-bit data processing mode or for byte processing in 8-bit data processing mode (see Figure 2.7-3 and Figure 2.7-4 . The data stored in the A register can be operated upon with the data in memory or registers (Ri, Rwi, or Rli). In the same manner as with the F2MC-8L, when a word or shorter data item is transferred to AL, the previous data item in AL is automatically sent to AH (data preservation function). The data preservation function and operation between AL and AH help improve processing efficiency. When a byte or shorter data item is transferred to AL, the data is sign-extended or zeroextended and stored as a 16-bit data item in AL. The data in AL can be handled either as word or byte long. When a byte-processing arithmetic operation instruction is executed on AL, the high-order eight bits of AL before operation are ignored. The high-order eight bits of the operation result all become zeroes. The A register is not initialized by a reset. The A register holds an undefined value immediately after a reset. Figure 2.7-3 32-bit Data Transfer MOVL A,@RW1+6 Old A XXXXH XXXXH A6H DTB New A LSB MSB 8F74H 2B52H AH AL A61540H 8FH 74H A6153EH 2BH 52H 15H 38H +6 RW1 Figure 2.7-4 AL-AH Transfer MSB MOVW A,@RW1+6 Old A XXXXH 1234H DTB New A 30 1234H A6H 1234H LSB A61540H 8FH 74H A6153EH 2BH 52H 15H 38H +6 RW1 CHAPTER 2 CPU 2.7.2 User Stack Pointer (USP) and System Stack Pointer (SSP) USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data in the event of a push/pop instruction or subroutine execution. ■ User Stack Pointer (USP) and System Stack Pointer (SSP) The USP and SSP registers are used by stack instructions. The USP register is enabled when the S flag in the processor status register is "0", and the SSP register is enabled when the S flag is "1" (see Figure 2.7-5 ). Since the S flag is set when an interrupt is accepted, register values are always saved in the memory area indicated by SSP during interrupt processing. SSP is used for stack processing in an interrupt routine, while USP is used for stack processing outside an interrupt routine. If the stack space is not divided, use only the SSP. During stack processing, the high-order eight bits of an address are indicated by SSB (for SSP) or USB (for USP). USP and SSP are not initialized by a reset. Instead, they hold undefined values. Figure 2.7-5 Stack Manipulation Instruction and Stack Pointer Example 1 PUSHW A when the S flag is "0" Before execution AL A624H USB C6H USP F328H 0 SSB 56H SSP 1234H A624 H USB C6H USP F326H 0 SSB 56H SSP 1234H C6F326H A6H 24H 561232H XX XX 561232H A6H 24H S flag After execution AL LSB MSB C6F326H XX XX User stack is used because the S flag is "0". Example 2 PUSHW A when the S flag is "1" AL AL A624 H USB C6H USP F328H 1 SSB 56H SSP 1234H A624 H USB C6H USP F328H 1 SSB 56H SSP 1232H System stack is used because the S flag is "1". Note: Specify an even-numbered address in the stack pointer whenever possible. 31 CHAPTER 2 CPU 2.7.3 Processor Status (PS) The PS register consists of the bits controlling the CPU Operation and the bits indicating the CPU status. ■ Processor Status (PS) As shown in Figure 2.7-6 , the high-order byte of the PS register consists of a register bank pointer (RP) and an interrupt level mask register (ILM). The RP indicates the start address of a register bank. The low-order byte of the PS register is a condition code register (CCR), containing the flags to be set or reset depending on the results of instruction execution or interrupt occurrences. Figure 2.7-6 PS Structure bit 15 PS 13 12 0 8 7 ILM RP CCR ■ Condition Code Register (CCR) Figure 2.7-7 is a diagram of condition code register (CCR) configuration. Figure 2.7-7 Condition Code Register Configuration bit Initial value 7 6 5 4 3 2 1 0 - I S T N Z V C - 0 * * * * 1 * : CCR *: Undefined ❍ Interrupt enable flag (I) Interrupts other than software interrupts are enabled when the I flag is 1 and are masked when the I flag is 0. The I flag is cleared by a reset. ❍ Stack fag (S) When the S flag is 0, USP is enabled as the stack manipulation pointer. When the S flag is 1, SSP is enabled as the stack manipulation pointer. The S flag is set by an interrupt reception or a reset. ❍ Sticky bit flag (T) 1 is set in the T flag when there is at least one "1" in the data shifted out from the carry after execution of a logical right/arithmetic right shift instruction. Otherwise, "0" is set in the T flag. In addition, "0" is set in the T flag when the shift amount is zero. ❍ Negative flag (N) The N flag is set when the MSB of the operation result is "1", and is otherwise cleared. ❍ Zero flag (Z) The Z flag is set when the operation result is all zeroes, and is otherwise cleared. 32 CHAPTER 2 CPU ❍ Overflow flag (V) The V flag is set when an overflow of a signed value occurs as a result of operation execution and is otherwise cleared. ❍ Carry flag (C) The C flag is set when a carry-up or carry-down from the MSB occurs as a result of operation execution and is otherwise cleared. ■ Register Bank Pointer (RP) The RP register indicates the relationship between the general-purpose registers of the F2MC16L and the internal RAM addresses. Specifically, the RP register indicates the first memory address of the currently used register bank in the following conversion expression: [00180H + (RP)*10H] (see Figure 2.7-8 ). The RP register consists of five bits, and can take a value between 00H and 1FH. Register banks can be allocated at addresses from 000180H to 00037H in memory. Even within that range, however, the register banks cannot be used as general-purpose registers if the banks are not in internal RAM. The RP register is initialized to all zeroes by a reset. An instruction may transfer an eight-bit immediate value to the RP register; however, only the low-order five bits of that data are used. Figure 2.7-8 Register Bank Pointer Initial value B4 B3 B2 B1 B0 0 0 0 0 0 : RP ■ Interrupt Level Mask Register (ILM) The ILM register consists of three bits, indicating the CPU interrupt masking level. An interrupt request is accepted only when the level of the interrupt is higher than that indicated by these three bits. Level 0 is the highest priority interrupt, and level 7 is the lowest priority interrupt (see Figure 2.7-9 ). Therefore, for an interrupt to be accepted, its level value must be smaller than the current ILM value. When an interrupt is accepted, the level value of that interrupt is set in ILM. Thus, an interrupt of the same or lower level cannot be accepted subsequently. ILM is initialized to all zeroes by a reset. An instruction may transfer an eight-bit immediate value to the ILM register, but only the low-order three bits of that data are used. Figure 2.7-9 Interrupt Level Register Initial value ILM2 ILM1 ILM0 0 0 0 : ILM 33 CHAPTER 2 CPU Table 2.7-1 Levels Indicated by the Interrupt Level Mask (ILM) Register 34 ILM2 ILM1 ILM0 Level value Acceptable interrupt level 0 0 0 0 Interrupt disabled 0 0 1 1 0 only 0 1 0 2 Level value smaller than 1 0 1 1 3 Level value smaller than 2 1 0 0 4 Level value smaller than 3 1 0 1 5 Level value smaller than 4 1 1 0 6 Level value smaller than 5 1 1 1 7 Level value smaller than 6 CHAPTER 2 CPU 2.7.4 Program Counter (PC) The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory address of an instruction code to be executed by the CPU. The high-order eight bits of the address are indicated by the PCB. The PC register is updated by a conditional branch instruction, subroutine call instruction, interrupt, or reset. The PC register can also be used as a base pointer for operand access. ■ Program Counter (PC) Figure 2.7-10 shows a program counter. Figure 2.7-10 Program Counter PCB FEH PC ABCDH Next instruction to be executed FEABCDH 35 CHAPTER 2 CPU 2.8 Register Bank A register bank consists of eight words. The register bank can be used as the following general-purpose registers for arithmetic operations: byte registers R0 to R7, word registers RW0 to RW7, and long word registers RL0 to RL3. In addition, the register bank can be used as instruction pointers. ■ Register Bank Table 2.8-1 lists the functions of the registers. Table 2.8-2 indicates the relationship between the registers. In the same manner as for an ordinary RAM area, the register bank values are not initialized by a reset. The status before a reset is maintained. When the power is turned on, however, the register bank will have an undefined value. Table 2.8-1 Register Functions R0 to R7 RW0 to RW7 RL0 to RL3 Used as operands of instructions. Note: R0 is also used as a counter for barrel shift or normalization instructions. Used as pointers. Used as operands of instructions. Note: RW0 is used as a counter for string instructions. Used as long pointers. Used as operands of instructions. Table 2.8-2 Relationship Between Registers RW0 RL0 RW1 RW2 RL1 RW3 R0 RW4 R1 RL2 R2 RW5 R3 R4 RW6 R5 RL3 R6 RW7 R7 36 CHAPTER 2 CPU ❍ Direct page register (DPR) <Initial value: 01H> DPR specifies addr8 to addr15 of the instruction operands in direct addressing mode as shown in Figure 2.8-1 . DPR is eight bits long, and is initialized to 01H by a reset. DPR can be read or written to by an instruction. Figure 2.8-1 Generating a Physical Address in Direct Addressing Mode DTB register DPR register αααααααα Direct address during instruction ββββββββ MSB 24-bit physical address γγγγγγγγ LSB ααααααααββββββββγγγγγγγγ ❍ Program counter bank register (PCB) <Initial value: Value in reset vector ❍ Data bank register (DTB) <Initial value: 00H> ❍ User stack bank register (USB) <Initial value: 00H> ❍ System stack bank register (SSB) <Initial value: 00H> ❍ Additional data bank register (ADB) <Initial value: 00H> Each bank register indicates the memory bank where the PC, DT, SP (user), SP (system), or AD space is allocated. All bank registers are one byte long. PCB is initialized to 00H by a reset. Bank registers other than PCB can be read or written to. PCB can be read but cannot be written to. PCB is updated when the JMPP, CALLP, RETP, RETI, or RETF instruction branching to the entire 16-Mbyte space is executed or when an interrupt occurs. For operation of each register, see Section 2.2 "Memory Space". 37 CHAPTER 2 CPU 2.9 Prefix Codes Placing a prefix code before an instruction partially changes the operation of the instruction. Three types of prefix codes can be used: bank select prefix, common register bank prefix, and flag change disable prefix. ■ Bank Select Prefix The memory space used for accessing data is determined for each addressing mode. When a bank select prefix is placed before an instruction, the memory space used for accessing data by that instruction can be selected regardless of the addressing mode. Table 2.9-1 lists the bank select prefixes and the corresponding memory spaces. Table 2.9-1 Bank Select Prefix Bank select prefix Space selected PCB PC space DTB Data space ADB AD space SPB Either the SSP or USP space is used according to the stack flag value. Use the following instructions with care: ❍ String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) The bank register specified by an operand is used regardless of the prefix. ❍ Stack manipulation instructions (PUSHW, POPW) SSB or USB is used according to the S flag regardless of the prefix. ❍ I/O access instructions MOV A, io / MOV io, A /MOVX A, io / MOVW A, io /MOVW io, A / MOV io, #imm8 MOVW io, #imm16 / MOVB A, io:bp / MOVB io:bp, A /SETB io:bp / CLRB io:bp BBC io:bp, rel / BBS io:bp, rel WBTC, WBTS The IO space of the bank is used regardless of the prefix. ❍ Flag change instructions (AND CCR,#imm8, OR CCR,#imm8) The instruction is executed normally, but the prefix affects the next instruction. ❍ POPW PS SSB or USB is used according to the S flag regardless of the prefix. The prefix affects the next instruction. 38 CHAPTER 2 CPU ❍ MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction. ❍ RETI SSB is used regardless of the prefix. ■ Common Register Bank Prefix (CMR) To simplify data exchange between multiple tasks, the same register bank must be accessed relatively easily regardless of the RP value. When CMR is placed before an instruction that accesses a register bank, that instruction accesses the common bank (the register bank selected when RP=0) at addresses from 000180H to 00018FH regardless of the current RP value. Use the following instructions with care: ❍ String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) If an interrupt request occurs during execution of a string instruction with a prefix code, the prefix code becomes invalid when the string instruction is resumed after the interrupt is processed. Thus, the string instruction is executed falsely after the interrupt is processed. Do not prefix any of the above string instructions with CMR. ❍ Flag change Instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS) The instruction is executed normally, but the prefix affects the next instruction. ❍ MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction. ■ Flag Change Disable Prefix (NCC) To disable flag changes, use the flag change disable prefix code (NCC). Placing NCC before an instruction disables flag changes associated with that instruction. Use the following instructions with care: ❍ String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) If an interrupt request occurs during execution of a string instruction with a prefix code, the prefix code becomes invalid when the string instruction is resumed after the interrupt is processed. Thus, the string instruction is executed incorrectly after the interrupt is processed. Do not prefix any of the above string instructions with NCC. ❍ Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS) The instruction is executed normally, but the prefix affects the next instruction. ❍ Interrupt instructions (INT #vct8, INT9, INT addr16, INTP addr24, RETI) CCR changes according to the instruction specifications regardless of the prefix. ❍ JCTX @A CCR changes according to the instruction specifications regardless of the prefix. ❍ MOV ILM, imm8 The instruction is executed normally, but the prefix affects the next instruction. 39 CHAPTER 2 CPU 2.10 Interrupt Disable Instructions Interrupt requests are not sampled for the following ten instructions: - MOV ILM,#imm8 - PCB - SPB - OR CCR,#imm8 - NCC - AND CCR,#imm8 - ADB - CMR - POPW PS - DTB ■ Interrupt Disable Instructions If a valid interrupt request occurs during execution of any of the above instructions, the interrupt can be processed only when an instruction other than the above is executed. For details, see Figure 2.10-1 . Figure 2.10-1 Interrupt Disable Instruction Interrupt disable instruction (a) •••••••• ••• (a) Ordinary instruction Interrupt acceptance Interrupt request ■ Restrictions on Interrupt Disable Instructions and Prefix Instructions When a prefix code is placed before an interrupt disable instruction, the prefix code affects the first instruction after the code other than the interrupt disable instruction. Figure 2.10-2 Interrupt Disable Instructions and Prefix Codes Interrupt disable instruction MOV A, FFH CCR:XXX10XX NCC •••• MOV ILM,#imm8 ADD A,01H CCR:XXX10XX CCR does not change with NCC. ■ Consecutive Prefix Codes When competitive prefix codes are placed consecutively, the latter becomes valid. In the figure below, competitive prefix codes are PCB, ADB, DTB, and SPB. Figure 2.10-3 Consecutive Prefix Codes Prefix code ••••• ADB DTB PCB ADD A,01H •••• PCB is valid as the prefix code 40 CHAPTER 2 CPU 2.11 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions Set "00H" in the bank register before using the "DIV A, Ri" and "DIVW A, RWi" Instructions. ■ Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions Table 2.11-1 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions (i = 0 to 7) Instruction Bank register affected by the execution of the instructions listed on the left Address that stores the remainder DIV A, R0 (DTB: Upper 8 bits) + (0180H + RP x 10H + 8H : Lower 16 bits) DIV A, R1 (DTB: Upper 8 bits) + (0180H + RP x 10H + 9H : Lower 16 bits) DIV A, R4 (DTB: Upper 8 bits) + (0180H + RP x 10H + CH : Lower 16 bits) DIV A, R5 DTB (DTB: Upper 8 bits) + (0180H + RP x 10H + DH : Lower 16 bits) DIVW A, RW0 (DTB: Upper 8 bits) + (0180H + RP x 10H + 0H : Lower 16 bits) DIVW A, RW1 (DTB: Upper 8 bits) + (0180H + RP x 10H + 2H : Lower 16 bits) DIVW A, RW4 (DTB: Upper 8 bits) + (0180H + RP x 10H + 8H : Lower 16 bits) DIVW A, RW5 (DTB: Upper 8 bits) + (0180H + RP x 10H + AH : Lower 16 bits) DIV A, R2 (ADB: Upper 8 bits) + (0180H + RP x 10H + AH : Lower 16 bits) DIV A, R6 ADB (ADB: Upper 8 bits) + (0180H + RP x 10H + EH : Lower 16 bits) DIVW A, RW2 (ADB: Upper 8 bits) + (0180H + RP x 10H + 4H : Lower 16 bits) DIVW A, RW6 (ADB: Upper 8 bits) + (0180H + RP x 10H + EH : Lower 16 bits) DIV A, R3 (USB *2: Upper 8 bits) + (0180H + RP x 10H + BH : Lower 16 bits) DIV A, R7 DIVW A, RW3 DIVW A, RW7 USB SSB *1 (USB *2: Upper 8 bits) + (0180H + RP x 10H + FH : Lower 16 bits) (USB *2: Upper 8 bits) + (0180H + RP x 10H + 6H : Lower 16 bits) (USB *2: Upper 8 bits) + (0180H + RP x 10H + EH : Lower 16 bits) *1 Depends on the S bit of the CCR register. *2 In the event that the S bit of the CCR register is zero If the value of the bank registers (DTB, ADB, USB, and SSB) is "00H", the remainder after division is stored in the register of the instruction operands. Otherwise, the upper eight bits is specified by the bank register corresponding to the register of the instruction operand, and the lower 16 bits is the same as the address of the register of the instruction operand. The remainder is stored in the bank register specified by the upper eight bits. 41 CHAPTER 2 CPU Example: If "DIV A,R0" is executed with DTB = 053H and RP = 03H the address of R0 is "0180H" + RP ("03H") x "10H" + "08H" (R0 corresponding address) = 0001B8H. Since the data bank register (DTB) is specified by "DIV A,R0" as the bank register, the remainder is stored in address "05301B8H", which was obtained by adding the bank address "053H". Note: For information about the bank register and Ri and RWi registers, see Section 2.7 "Registers". ■ Use of the "DIV A, Ri" and "DIVW A, RWi" Instructions without Precautions To enable users to develop programs without having to take precautions for using the "DIV A,Ri" and "DIVW A,RWi" instructions, special compilers and assemblers are available. The special compiler does not generate the instructions in Table 2.11-1 . The special assemblers have a function that replaces the instructions in Table 2.11-1 with equivalent instruction strings. For the MB90595 series, use the following types of compilers and assemblers: ❍ Compiler • cc907 V02L06 or later, or fcc907s V30L02 or later ❍ Assembler • 42 asm907a V03L04 or later, or fasm907s V30L04 (Rev. 300004) or later CHAPTER 3 INTERRUPTS CHAPTER 3 INTERRUPTS This chapter explains interrupt functions and operation. 3.1 "Outline of Interrupts" 3.2 "Interrupt Vectors" 3.3 "Interrupt Control Register (ICR)" 3.4 "Interrupt Sequence" 3.5 "Hardware Interrupts" 3.6 "Software Interrupts" 3.7 "Extended Intelligent I/O Service (EI2OS)" 3.8 "Operation Sequence and Use Sequence of Extended Intelligent I/O Service (EI2OS)" 3.9 "Exceptions" 43 CHAPTER 3 INTERRUPTS 3.1 Outline of Interrupts The F2MC-16LX has interrupt functions that terminate the currently executing processing and transfer control to another specified program when a specified event occurs. There are four types of interrupt functions: • Hardware interrupt: Interrupt processing due to an internal resource event • Software interrupt: Interrupt processing due to a software event occurrence instruction • Extended intelligent I/O service (EI2OS): Transfer processing due to an internal resource event • Exception: Termination due to an operation exception ■ Hardware Interrupts A hardware interrupt is caused by an interrupt request from an internal resource. A hardware interrupt request is issued when the interrupt request flag and interrupt enable flag in the internal resource are set. Therefore, to issue a hardware request, the internal resource must have an interrupt request flag and interrupt enable flag. ❍ Specification of an interrupt level An interrupt level can be specified for a hardware interrupt. To specify an interrupt level, use the level setting bits (IL0, IL1, and IL2) of the interrupt controller. ❍ Hardware interrupt request mask A hardware interrupt request can be masked by using the ILM bits (IL0, IL1, and IL2) and the I flag in the processor status register (PS) of the CPU. If a nonmasked interrupt request is issued, the CPU saves 12-byte data consisting of the PS, PC, PCB, DTB, ADB, DPR, and A registers in the memory area indicated by the SSB and SSP registers. 44 CHAPTER 3 INTERRUPTS Figure 3.1-1 Occurrence and Release of Hardware Interrupt PS Register file F2MC-16 bus Microcode IR (6) I Check (5) F 2 M C - 1 6 LX C P U AND (2) Interrupt level IL Level comparator Enable FF (7) Comparator (4) PS : Processor status I : Interrupt enable flag ILM: Interrupt level mask register IR : Instruction register (3) Peripheral Cause FF (1) ILM Interrupt controller ■ Software Interrupts A software interrupt is a function that transfers control from the program that was being executed by the CPU to a user-defined interrupt processing routine. A software interrupt request is made by executing an INT instruction. The interrupt request flag and interrupt enable flag do not apply to any software interrupt requests made by an INT instruction. A software interrupt request is issued whenever an INT instruction is executed. The INT instruction does not have an interrupt level. Therefore, the INT instruction does not update the ILM, and instead clears the I flag to suspend subsequent interrupt requests. Figure 3.1-2 Outline of a Software Interrupt (1) PS 2 F MC-16 bus Register file I (2) Microcode S B unit IR Queue PS: Processor status I: Interrupt enable flag S: Stack flag IR: Instruction register B unit: Bus interface unit Fetch F2MC-16LX CPU Save Instruction bus RAM ■ Extended Intelligent I/O Service (EI2OS) The EI2OS function automatically transfers data between input and output and memory. An interrupt processing program was conventionally used for such processing, but EI2OS enables data transfer to be performed like DMA (direct memory access). To generate the extended intelligent I/O service function from the internal resource, the interrupt control register (ICR) of the interrupt controller must have an extended intelligent I/O service enable flag (ISE). 45 CHAPTER 3 INTERRUPTS The extended intelligent I/O service is activated when an interrupt request occurs with the ISE flag set to 1. To generate a normal interrupt by a hardware interrupt request, set the ISE flag to "0". Figure 3.1-3 Outline of Extended Intelligent I/O Service Memory space by IOA I/O register I/O register Peripheral Interrupt request CPU ③ ③ ISD by ICS ② ① Interrupt control register Interrupt controller ① I/O requests transfer. by BAP ④ ② The interrupt controller selects the descriptor. Buffer by DCT ③ The transfer source and destination are read from the descriptor. ④ Data is transferred between I/O and memory. ■ Exception Exception processing is basically the same as interrupt processing. If an exceptional event is detected between instructions, normal processing is interrupted and exception processing is performed. Exception processing is generally caused as a result of an unexpected operation. It is recommended that exception processing be used only for debugging or starting recovery software in an emergency. 46 CHAPTER 3 INTERRUPTS 3.2 Interrupt Vectors An interrupt vector uses the same area for both hardware and software interrupts. For example, interrupt request number INT42 is used for a delayed hardware interrupt and for software interrupt INT #42. Therefore, the delayed interrupt and INT #42 call the same interrupt processing routine. Interrupt vectors are allocated between addresses FFFC00H and FFFFFFH as shown in Table 3.2-1 . ■ Interrupt Vectors Table 3.2-1 Interrupt Vectors Interrupt request Vector address L Vector address H Vector address bank Mode register INT 0 *1 FFFFFCH FFFFFDH FFFFFEH Unused INT 1 *1 FFFFF8H FFFFF9H FFFFFAH Unused . . . . . . . . . . . . . . . INT 7 *1 FFFFE0H FFFFE1H FFFFE2H Unused INT 8 *2 FFFFDCH FFFFDDH FFFFDEH FFFFDFH INT 9 FFFFD8H FFFFD9H FFFFDAH Unused INT 10 *3 FFFFD4H FFFFD5H FFFFD6H Unused INT 11 FFFFD0H FFFFD1H FFFFD2H Unused . . . . . . . . . . . . . . . INT 254 FFFC04H FFFC05H FFFC06H Unused INT 255 FFFC00H FFFC01H FFFC02H Unused *1: When PCB is FFH, the vector area for the CALLV instruction is the same as that for INT #vct8(#0 to #7). Care must be taken when using the vector for the CALLV instruction. *2: The vector is a reset vector. *3: The vector is an exception processing vector. ■ Interrupt Vector List See Table D-1 in Appendix D "List of MB90595 Interrupt Vectors" for a listing of the MB90595 interrupt vectors. 47 CHAPTER 3 INTERRUPTS 3.3 Interrupt Control Register (ICR) The interrupt control register is in the interrupt controller. This register corresponds to I/Os that have the interrupt function. This register has the following three functions: • Sets the interrupt level of the corresponding peripheral. • Selects whether to handle the interrupt of the corresponding peripheral as an ordinary interrupt or as an extended intelligent I/O service. • Selects the extended intelligent I/O service channel. Do not access this register by a read-modify-write instruction, as doing so causes misoperation. ■ Interrupt Control Register (ICR) Figure 3.3-1 is a diagram of the bit configuration of the interrupt control register. Figure 3.3-1 Interrupt Control Register (ICR) bit 15/7 14/6 13/5 12/4 ICS3 ICS2 ICS1 or S1 ICS0 or S0 W W * * 11/3 10/2 9/1 8/0 ISE IL2 IL1 IL0 R/W R/W R/W R/W Interrupt control register 00000111B when reset R/W : Readable/Writable W : Write only Note: ICS3 to ICS0 are valid only when EI2OS is activated. Set ISE to "1" to activate EI2OS, and to "0" not to activate it. When EI2OS is not to be activated, any value can be written to ICS3 to ICS0. "1" is always read for ICS3 and ICS2. * ICS1 and ICS0 are valid for write only. S1 and S0 are valid for read only. [bit10 to bit8] or [bit2 to bit0] IL2, IL1, and IL0 These are interrupt level setting bits. Specify the interrupt level of the corresponding internal resource. These bits can be read and written to. These bits are initialized to level 7 (no interrupt) upon a reset. Table 3.3-1 describes the relationship between the interrupt level setting bits and interrupt levels. 48 CHAPTER 3 INTERRUPTS Table 3.3-1 Interrupt Level Setting Bits and Interrupt Levels ILM2 ILM1 ILM0 Level 0 0 0 0 (Highest interrupt level) 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 (Lowest interrupt level) 1 1 1 7 (No interrupt) [bit11] or [bit3] : ISE (extended intelligent I/O service enable bits) This is the EI2OS enable bit. This bit can be read or written to. Upon issuance of an interrupt request, EI2OS is activated if this bit is set to "1" and the interrupt sequence is activated if this bit is set to "0". If the EI2OS end condition is satisfied (the S1 and S0 bits are not "00"), the ISE bit is cleared to "0". If the corresponding peripheral does not have the EI2OS function, the software must set ISE to "0". This bit is initialized to "0" upon a reset. [bit15 to bit12] or [bit7 to bit4] : ICS3 to ICS0 (extended intelligent I/O service channel select bits) These bits are used to select the EI2OS channel. These bits are write-only. The value specified in these bits determines the address of the extended intelligent I/O service descriptor in memory, which is explained later. ICS is initialized upon a reset. Table 3.3-2 shows the correspondence between ICS, channel numbers, and descriptor addresses. 49 CHAPTER 3 INTERRUPTS Table 3.3-2 ICS Bits, Channel Numbers, and Descriptor Addresses ICS3 ICS2 ICS1 ICS0 Selected channel Descriptor address 0 0 0 0 0 000100H 0 0 0 1 1 000108H 0 0 1 0 2 000110H 0 0 1 1 3 000118H 0 1 0 0 4 000120H 0 1 0 1 5 000128H 0 1 1 0 6 000130H 0 1 1 1 7 000138H 1 0 0 0 8 000140H 1 0 0 1 9 000148H 1 0 1 0 10 000150H 1 0 1 1 11 000158H 1 1 0 0 12 000160H 1 1 0 1 13 000168H 1 1 1 0 14 000170H 1 1 1 1 15 000178H [bit13, bit12] or [bit5, bit4]:S0 and S1 (extended intelligent I/O service status bits) These are EI2OS end status bits. These bits are read-only. When the EI2OS is completed, the end condition can be identified by checking the value in these bits. These bits are set to "00" upon a reset. Table 3.3-3 shows the relationship between the S bits and end conditions. Table 3.3-3 S Bits and End Conditions 50 S1 S0 End condition 0 0 EI2OS running or not activated 0 1 Count completion 1 0 Reserved 1 1 Resource request CHAPTER 3 INTERRUPTS 3.4 Interrupt Sequence Figure 3.4-1 shows a hardware interrupt operation sequence. ■ Interrupt Operation Sequence Figure 3.4-1 Interrupt Operation Sequence I:Flag in CCR ILM:CPU level register IF:Internal resource interrupt request IE:Internal resource interrupt enable flag ISE:EI2OS enable flag IL:Internal resource interrupt request level S:Flag in CCR I & IF & IE =1 AND ILM > IL YES NO NO Fetching and decoding next instruction YES ISE = 1 Saving PS, PC, PCB, DTB, ADB, DPR, and A to SSP stack, and setting ILM=IL Extended intelligent I/O service YES INT instruction? NO Executing ordinary instruction NO String instruction repetition completed? Saving PS, PC, PCB, DTB, ADB, DPR, and A to SSP stack, and setting I=0 and ILM=IL S←1 Fetching interrupt vector YES Updating PC 51 CHAPTER 3 INTERRUPTS Figure 3.4-2 Saving Register Contents during Interrupt Processing Word (16 bits) MSB LSB H SSP (SSP value before interrupt) AH AL DPR ADB DPB PCB PC PS L 52 SSP (SSP value after interrupt) CHAPTER 3 INTERRUPTS 3.5 Hardware Interrupts In response to an interrupt request signal from an internal resource, the CPU pauses current program execution and transfers control to the interrupt processing program defined by the user. ■ Hardware Interrupts A hardware interrupt occurs when relevant conditions are satisfied as a result of two operations: comparison between the interrupt request level and the value in the interrupt level mask register of PS of the CPU, and hardware reference to the I flag value in PS. The CPU performs the following processing when a hardware interrupt occurs: • Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to the system stack. • Sets ILM in the PS register. The currently requested interrupt level is automatically set. • Fetches the corresponding interrupt vector value and branches to the processing indicated by that value. ■ Structure of Hardware Interrupt Hardware interrupts are handled by the following three sections: ❍ Internal resources Interrupt enable and request bits: Used to control interrupt requests from resources. ❍ Interrupt controller ICR: Assigns interrupt levels and determines the priority levels of simultaneously requested interrupts. ❍ CPU I and ILM: Used to compare the requested and current interrupt levels and to identify the interrupt enable status. Microcode: Interrupt processing step The status of these sections are indicated by the resource control registers for internal resources, the ICR for the interrupt controller, and the CCR value for the CPU. To use a hardware interrupt, set the three sections beforehand by using software. The interrupt vector table referenced during interrupt processing is assigned to addresses FFFC00H to FFFFFFH in memory. These addresses are shared with software interrupts. Table D-2 in Appendix D lists assignments for the MB90595 Series. 53 CHAPTER 3 INTERRUPTS 3.5.1 Hardware Interrupt Operation An internal resource that has the hardware interrupt request function has an interrupt request flag and interrupt enable flag. The interrupt request flag indicates whether an interrupt request exists, and the interrupt enable flag indicates whether the relevant internal resource requests an interrupt to the CPU. The interrupt request flag is set when an event occurs that is unique to the internal resource. When the interrupt enable flag indicates "enable," the resource issues an interrupt request to the interrupt controller. ■ Hardware Interrupt Operation When two or more interrupt requests are received at the same time, the interrupt controller compares the interrupt levels (IL) in ICR, selects the request at the highest level (the smallest IL value), then reports that request to the CPU. If multiple requests are at the same level, the interrupt controller selects the request with the lowest interrupt number. The relationship between the interrupt requests and ICRs is determined by the hardware. The CPU compares the received interrupt level and the ILM in the PS register. If the interrupt level is smaller than the ILM value and the I bit of the PS register is set to 1, the CPU activates the interrupt processing microcode after the currently executing instruction is completed. The CPU references the ISE bit of the ICR of the interrupt controller at the beginning of the interrupt processing microcode, checks that the ISE bit is 0 (interrupt), and activates the interrupt processing body. The interrupt processing body saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP, fetches three bytes of interrupt vector and loads them onto PC and PCB, updates the ILM of PS to a level value of the received interrupt, sets the S flag, then performs branch processing. As a result, the interrupt processing program defined by the user is executed next. 54 CHAPTER 3 INTERRUPTS 3.5.2 Occurrence and Release of Hardware Interrupt Figure 3.5-1 illustrates the flow from the occurrence of a hardware interrupt until there is no interrupt request in the interrupt processing program. ■ Occurrence and Release of Hardware Interrupt Figure 3.5-1 Occurrence and Release of Hardware Interrupt PS Register file IR (6) Check (5) F 2 M C - 1 6 LX C P U AND (2) Level comparator Enable FF (7) Comparator (4) PS : Processor status I : Interrupt enable flag ILM: Interrupt level mask register IR : Instruction register (3) Peripheral Cause FF (1) ILM Interrupt level IL F2MC-16 bus Microcode I Interrupt controller (1) An interrupt cause occurs in a peripheral. (2) The interrupt enable bit in the peripheral is referenced. If interrupts are enabled, the peripheral issues an interrupt request to the interrupt controller. (3) Upon reception of the interrupt request, the interrupt controller determines the priority levels of simultaneously requested interrupts. Then, the interrupt controller transfers the interrupt level of the corresponding interrupt to the CPU. (4) The CPU compares the interrupt level requested by the interrupt controller with the ILM bit of the processor status register. (5) If the comparison shows that the requested level is higher than the current interrupt processing level, the I flag value of the same processor status register is checked. (6) If the check in step (5) shows that the I flag indicates interrupt enable status, the requested level is written to the ILM bit. Interrupt processing is performed as soon as the currently executing instruction is completed, then control is transferred to the interrupt processing routine. (7) When the interrupt cause of step (1) is cleared by software in the user interrupt processing routine, the interrupt request is completed. The time required for the CPU to execute the interrupt processing in steps (6) and (7) is shown below. Interrupt start: 24 + 6 × compensation value machine cycles Interrupt return: 15 + 6 × compensation value machine cycles (RETI instruction) 55 CHAPTER 3 INTERRUPTS Table 3.5-1 Compensation Values for Interrupt Processing Cycle Count Address indicated by the stack pointer 56 Cycle count compensation value Internal area, even-numbered address 0 Internal area, odd-numbered address +2 CHAPTER 3 INTERRUPTS 3.5.3 Multiple Interrupts As a special case, no hardware interrupt request can be accepted while data is being written to the I/O area. This is intended to prevent the CPU from operating falsely because of an interrupt request issued while an interrupt control register for a resource is being updated. If another interrupt occurs while an interrupt is being processed, the interrupt with a higher interrupt level is processed first. ■ Multiple Interrupts The F2MC-16LX CPU supports multiple interrupts. If an interrupt of a higher level occurs while another interrupt is being processed, control is transferred to the high-level interrupt after the currently executing instruction is completed. After processing of the high-level interrupt is completed, the original interrupt processing is resumed. An interrupt of the same or lower level may be generated while another interrupt is being processed. If this happens, the new interrupt request is suspended until the current interrupt processing is completed, unless the ILM value or I flag is changed by an instruction. The extended intelligent I/O service cannot be activated from multiple sources; while an extended intelligent I/O service is being processed, all other interrupt requests or extended intelligent I/O service requests are suspended. Figure 3.5-2 shows the order of the registers saved in the stack. Register saving upon interrupt Figure 3.5-2 Registers Saved in Stack Word (16 bits) MSB LSB H SSP (SSP value before interrupt) AH AL DPR ADB DPB PCB PC PS SSP (SSP value after interrupt) L 57 CHAPTER 3 INTERRUPTS 3.6 Software Interrupts In response to the execution of a special instruction, a software interrupt transfers control from the program currently being executed by the CPU to a user-defined interrupt processing routine. A software interrupt always occurs when a software interrupt instruction is executed. ■ Software Interrupts The CPU performs the following processing when a software interrupt occurs: • Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to the system stack. • Sets I in the PS register. Interrupts are automatically disabled. • Fetches the corresponding interrupt vector value, then branches to the processing indicated by that value. A software interrupt request issued by the INT instruction has no interrupt request or enable flag. A software interrupt request is always issued by executing the INT instruction. The INT instruction does not have an interrupt level. Therefore, the INT instruction does not update ILM. The INT instruction clears the I flag to suspend subsequent interrupt requests. ■ Structure of Software Interrupts Software interrupts are handled within the CPU: • CPU: Microcode: Interrupt processing step ■ List of MB90595 Interrupt Vectors Table D-1 lists the MB90595 series interrupt vectors. As shown in Table D-1 , software interrupts share the same interrupt vector area as hardware interrupts. For instance, interrupt request number INT13 is not only used for software interrupt INT#13 but also for external interrupt #0/#1 of the hardware interrupts. Thus, external interrupt #0 and INT#13 call the same interrupt processing routine. ■ Operation of Software Interrupts When the CPU fetches and executes the software interrupt instruction, the software interrupt processing microcode is activated. The software interrupt processing microcode saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP. The microcode then fetches three bytes of interrupt vector and loads them onto PC and PCB, resets the I flag, and sets the S flag. Then, the microcode performs branch processing. As a result, the interrupt processing program defined by the user application program is executed next. Figure 3.6-1 illustrates the flow from the occurrence of a software interrupt until there is no interrupt request in the interrupt processing program. 58 CHAPTER 3 INTERRUPTS Figure 3.6-1 Occurrence and Release of Software Interrupt (1) PS F2MC-16 bus Register file I (2) Microcode S B unit IR Queue PS: Processor status I: Interrupt enable flag S: Stack flag IR: Instruction register B unit: Bus interface unit Fetch F2MC-16LX CPU Save Instruction bus RAM (1) The software interrupt instruction is executed. (2) Special CPU registers in the register file are saved according to the microcode corresponding to the software interrupt instruction. (3) The interrupt processing is completed with the RETI instruction in the user interrupt processing routine. ■ Others When the program bank register (PCB) is FFH, the CALLV instruction vector area overlaps the table of the INT #vct8 instruction. When designing software, ensure that the CALLV instruction does not use the same address as that of the #vct8 instruction. Table D-2 shows the relationship between the interrupt causes, interrupt vectors, and interrupt control registers for the MB90595 Series. 59 CHAPTER 3 INTERRUPTS 3.7 Extended Intelligent I/O Service (EI2OS) EI2OS is a type of hardware interrupt operation that automatically transfers data between I/O and memory. Conventionally, data is transferred between I/O and memory by an interrupt processing program. EI2OS, however, enables data to be transferred as if in DMA mode. ■ Extended Intelligent I/O Service (EI2OS) EI2OS has the following advantages over the conventional interrupt processing method: • Writing a transfer program is unnecessary, thus the entire program size can be small. • No internal register is used for transfer. Therefore, saving the register values is unnecessary, resulting in a higher transfer speed. • I/O can stop transfer at any time. Therefore, unnecessary data is not transferred. • The buffer address can be incremented, decremented, or left unupdated. • The I/O address can be incremented, decremented, or left unupdated (when the buffer address is updated). At the end of EI2OS processing, the CPU automatically branches to the interrupt processing routine after setting the end condition. Therefore, the user can identify the end condition type. To implement EI2OS, hardware is distributed to two locations, and the register and descriptor shown below exist in the hardware blocks: • Interrupt control register • • This register exists in the interrupt controller and indicates an IDS address. Extended intelligent I/O service descriptor • This descriptor exists in RAM and retains an I/O address, transfer count, and buffer address. Note: The use of EI2OS is not possible with REALOS real time operating system. Figure 3.7-1 outlines the EI2OS. 60 CHAPTER 3 INTERRUPTS Figure 3.7-1 Outline of Extended Intelligent I/O Service Memory space by IOA I/O register CPU ••• ••• ••• ••• I/O register Peripheral Interrupt request (1) (3) ISD by ICS (3) (2) Interrupt control register Interrupt controller by BAP (4) Buffer (1) I/O requests transfer. (2) The interrupt controller selects the descriptor. (3) The transfer source and destination by are read from the descriptor. DCT (4) Data is transferred between I/O and memory. Note: The area that can be specified by IOA is between 000000H and 00FFFFH. The area that can be specified by BAP is between 000000H and FFFFFFH. The maximum transfer count that can be specified by DCT is 65,536. ■ Structure of Extended Intelligent I/O Service (EI2OS) EI2OS is handled by the following four sections: • Internal resources • • Interrupt controller • • • Interrupt enable and request bits: Used to control interrupt requests from resources. ICR: Assigns interrupt levels, determines the priority levels of simultaneously requested interrupts, and selects the EI2OS operation. CPU • I and ILM: Used to compare the requested and current interrupt levels and to identify the interrupt enable status. • Microcode: EI2OS processing step RAM • Descriptor: Describes the EI2OS transfer information. 61 CHAPTER 3 INTERRUPTS 3.7.1 Extended Intelligent I/O Service Descriptor (ISD) The extended intelligent I/O service descriptor exists between 000100H and 00017FH in internal RAM, and consists of the following items: • Data transfer control data • Status data • Buffer address pointer ■ Extended Intelligent I/O Service Descriptor (ISD) Figure 3.7-2 shows the configuration of the extended intelligent I/O service descriptor. Figure 3.7-2 Extended Intelligent I/O Service Descriptor Configuration H High-order 8 bits of data counter (DCTH) Low-order 8 bits of data counter (DCTL) High-order 8 bits of I/O address pointer (IOAH) Low-order 8 bits of I/O address pointer (IOAL) EI2OS status (ISCS) High-order 8 bits of buffer address pointer (BAPH) 000100 H + 8 × ICS Medium-order 8 bits of buffer address pointer (BAPM) ISD start address Low-order 8 bits of buffer address pointer (BAPL) L ■ Data Counter (DCT) This is a 16-bit register that works as a counter corresponding to the number of data items transferred. This counter is decremented by one before data transfer. EI2OS is terminated when this counter reaches 0. Figure 3.7-3 is a diagram of the data counter configuration. Figure 3.7-3 Data Counter Configuration bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DCT B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 (Undefined when reset) ■ I/O Register Address Pointer (IOA) This is a 16-bit register that indicates the low-order address (A15 to A00) of the buffer and I/O register used for data transfer. The high-order address (A23 to A16) are all zeroes, and any I/O between addresses 000000H and 00FFFFH can be specified. Figure 3.7-4 is a diagram of the IOA configuration. 62 CHAPTER 3 INTERRUPTS Figure 3.7-4 I/O Register Address Pointer Configuration bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IOA A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 (Undefined when reset) ■ Buffer Address Pointer (BAP) This 24-bit register holds the address used for the next EI2OS transfer. BAP exists for each EI2OS channel. Therefore, each EI2OS channel can be used for transfer with anywhere in the 16-Mbyte space. If the BF bit of ISCS is set to "0" (update enabled), only the low-order 16 bits of BAP changes and BAPH does not change. 63 CHAPTER 3 INTERRUPTS EI2OS Status Register (ISCS) 3.7.2 This eight-bit register indicates the update direction (increment/decrement), transfer data format (byte/word), and transfer direction of the buffer address pointer and the I/O register address pointer. This register also indicates whether the buffer address pointer or I/O register address pointer is updated or fixed. ■ EI2OS Status Register (ISCS) Figure 3.7-5 is a diagram of the ISCS configuration. Figure 3.7-5 ISCS Configuration bit 7 6 5 Reserved Reserved Reserved 4 3 IF BW 2 BF 1 0 DIR SE ISCS (Undefined when reset) * Always write 0 to bit7 to bit5 of ISCS. Each bit is described below. [bit4] IF Specify whether the I/O register address pointer is updated or fixed. 0: The I/O register address pointer is updated after data transfer. 1: The I/O register address pointer is not updated after data transfer. Note: Only increment is allowed. [bit3] BW: Specify the transfer data length. 0: Byte 1: Word [bit2] BF Specify whether the buffer address pointer is updated or fixed. 0: The buffer address pointer is updated after data transfer. 1: The buffer address pointer is not updated after data transfer. Note: Only the low-order 16 bits of the buffer address are updated. Only increment is allowed. [bit1] DIR Specify the data transfer direction. 0: I/O to Buffer 1: Buffer to I/O 64 CHAPTER 3 INTERRUPTS [bit0] SE Control the termination of the extended intelligent I/O service based on resource requests. 0: The extended intelligent I/O service is not terminated by a resource request. 1: The extended intelligent I/O service is terminated by a resource request. 65 CHAPTER 3 INTERRUPTS 3.8 Operation Sequence and Use Sequence of Extended Intelligent I/O Service (EI2OS) Figure 3.8-1 shows the operation sequence of the extended intelligent I/O service (EI2OS), and Figure 3.8-2 shows the use sequence of the service. ■ Operation Sequence of the Extended Intelligent I/O Service (EI2OS) Figure 3.8-1 Operation Sequence of the Extended Intelligent I/O Service (EI2OS) BAP:Buffer address pointer I/OA:I/O address pointer ISD:EI 2OS descriptor ISCS:EI 2OS status DCT:Data counter ISE:EI 2OS enable bit S1 and S0:EI 2OS end status Interrupt request issued from internal resource NO ISE = 1 YES Interrupt sequence Reading ISD/ISCS End request from resource NO YES SE = 1 YES DIR = 1 NO Data indicated by IOA (Data transfer) Memory indicated by BAP Data indicated by BAP (Data transfer) Memory indicated by IOA YES IF = 0 NO Update value depends on BW. Updating IOA Update value depends on BW. Updating BAP YES BF = 0 NO Decrementing DCT DCT = 00 YES NO Setting S1 and S0 to "01" Setting S1 and S0 to "11" Setting S1 and S0 to "00" 66 Clearing resource interrupt request Clearing ISE to "0" CPU operation return Interrupt sequence CHAPTER 3 INTERRUPTS Figure 3.8-2 EI2OS Use Flow Processing by EI 2OS Processing by CPU EI2OS initialization JOB execution Normal termination (Interrupt request) AND (ISE = 1) Data transfer Interrupt occurence due to a count-out or end reuest from a resource Re-setting of extended intelligent I/O service (Switching channels) Processing data in buffer The extended EI2OS execution time for each flow is described below. ❍ When data transfer continues (when the stop condition is not satisfied) Table 3.8-1 + Table 3.8-2 machine cycles ❍ When a stop request is issued from a resource 36 + 6 × Table 3.5-1 machine cycles ❍ When the counting is completed Table 3.8-1 + Table 3.8-2 + ( 21+6 × Table 3.5-1 ) machine cycles Table 3.8-1 Execution Time When the Extended EI2OS Continues ISCS SE bit Set to "0" I/O address pointer Buffer address pointer Set to "1" Fixed Updated Fixed Updated Fixed 32 34 33 35 Updated 34 36 35 37 67 CHAPTER 3 INTERRUPTS Table 3.8-2 Data Transfer Compensation Values for Extended EI2OS Execution Time Internal access I/O address pointer Buffer address pointer Internal access B: Byte data transfer E: Even address word transfer O: Odd address word transfer 68 B/E O B/E 0 +2 O +2 +4 CHAPTER 3 INTERRUPTS 3.9 Exceptions The F2MC-16LX performs exception processing when the following event occurs: ■ Execution of an Undefined Instruction Exception processing is fundamentally the same as interrupt processing. When an exception is detected between instructions, exception processing is performed separately from ordinary processing. In general, exception processing is performed as a result of an unexpected operation. Fujitsu recommends using exception processing only for debugging or for activating emergency recovery software. ■ Exception Due to Execution of an Undefined Instruction The F2MC-16LX handles all codes that are not defined in the instruction map as undefined instructions. When an undefined instruction is executed, processing equivalent to the INT 10 software interrupt instruction is performed. Specifically, the AL, AH, DPR, DTB, ADB, PCB, PC, and PS values are saved into the system stack, and processing branches to the routine indicated by the interrupt number 10 vector. In addition, the I flag is cleared and the S flag is set. The PC value saved in the stack is the address at which the undefined instruction is stored. Processing can be restored by the RETI instruction, but is of no use, however, because the same exception occurs again. 69 CHAPTER 3 INTERRUPTS 70 CHAPTER 4 DELAYED INTERRUPT CHAPTER 4 DELAYED INTERRUPT This chapter explains the delayed interrupt functions and operation. 4.1 "Outline of Delayed Interrupt Module" 4.2 "Delayed Interrupt Request Register" 4.3 "Operations of Delayed Interrupt" 71 CHAPTER 4 DELAYED INTERRUPT 4.1 Outline of Delayed Interrupt Module The delayed interrupt source module is used to generate interrupts for switching tasks. Using this module, interrupt requests to the F2MC-16LX CPU can be issued and canceled by software. ■ Block Diagram of Delayed Interrupt Figure 4.1-1 is a block diagram of the delayed interrupt source module. Figure 4.1-1 Block Diagram F2MC-16 bus Delayed interrupt cause issuance/cancellation decoder Cause latch ■ Note on Using the Delayed Interrupt Request Lock This lock is set by writing "1" to the corresponding bit of DIRR, and is cleared by writing "0" to the same bit. Therefore, interrupt processing is reactivated immediately after control returns from interrupt processing, unless the software is designed so that the cause of the interrupt is cleared within the interrupt processing routine. 72 CHAPTER 4 DELAYED INTERRUPT 4.2 Delayed Interrupt Request Register The delayed interrupt request register (DIRR) controls the generation and release of delayed interrupt requests. Writing 1 to the register issues a delayed interrupt request, and writing 0 cancels the delayed interrupt request. Upon a reset, the request is canceled. ■ Delayed Interrupt Cause Issuance/Cancellation Register (DIRR: Delayed Interrupt Request Register) DIRR controls issuance and cancellation of delayed interrupt requests. Writing "1" to this register issues a delayed interrupt request, and writing "0" cancels the delayed interrupt request. Upon a reset, the request is canceled. Either "0" or "1" can be written to the reserved bit area. To access this register, use the set bit or clear bit instruction for future expansions. bit DIRR Address: 00009FH R/W : Readable/Writable : Undefined 15 14 13 12 11 10 9 8 R0 Initial value - - - - - - -0B R/W The request is canceled upon a reset. 73 CHAPTER 4 DELAYED INTERRUPT 4.3 Operations of Delayed Interrupt When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in the delayed interrupt source module is set and an interrupt request is issued to the interrupt controller. ■ Delayed Interrupt Occurrence If this interrupt has the highest priority or if there is no other interrupt request, the interrupt controller issues an interrupt request to the F2MC-16LX CPU. The F2MC-16LX CPU compares the ILM bit of its internal CCR register and the interrupt request, and starts the hardware interrupt processing microprogram as soon as the current instruction is completed if the interrupt level of the request is higher than that of the ILM bit. The interrupt processing routine for this interrupt is thus executed. Figure 4.3-1 Delayed Interrupt Issuance Delayed interrupt source module Interrupt controller F2MC-16LX CPU WRITE Other requests ICR yy IL CMP CMP DIRR ICR xx ILM INTA The interrupt cause is cleared and tasks are switched by writing "0" to the corresponding bit of DIRR in the interrupt processing routine. 74 CHAPTER 5 CLOCK AND RESET CHAPTER 5 CLOCK AND RESET This chapter explains the clock and reset functions and operation. 5.1 "Clock Generator" 5.2 "Reset Cause Occurrence" 5.3 "Reset Causes" 75 CHAPTER 5 CLOCK AND RESET 5.1 Clock Generator The clock generator controls internal clock operation, including such functions as sleep, timer, stop, and PLL multiplication. This internal clock is called the machine clock, and one cycle of the machine clock is called a machine cycle. A clock based on the source oscillation is called the main clock, and a clock based on the internal VCO oscillation is called the PLL clock. ■ Note of Clock Generator When the operating voltage is 5 V, the OSC source oscillation can be between 3 MHz and 5 MHz. When an external clock source is used, its frequency can be between 3 MHz and 16 MHz. The highest operating frequency for the CPU and peripheral resource circuits is 16 MHz, however. Normal operation is not guaranteed if a multiplication factor resulting in a higher frequency than 16 MHz is specified. For example, if the external clock frequency is 16 MHz, only 1 can be specified as the multiplication factor. The lowest operating frequency of the VCO oscillation is 4 MHz, and an oscillation below 4 MHz must not be specified. Figure 5.1-1 is a block diagram of the clock generator circuit. Figure 5.1-1 Clock Generator Circuit Block Diagram S Q Reset Interrupt HST Transition to stop mode S Q Machine clock Transition to timer or sleep mode R R Selecting the machine clock S Q 1 R Selecting the oscillation stabilization wait time 2 3 4 PLL multiplication Time-base timer 1/2 X0 1/2048 1/4 1/4 1/8 X1 Selecting the watch-dog timer interval Monitoring timer Watch-dog reset 76 CHAPTER 5 CLOCK AND RESET 5.2 Reset Cause Occurrence When a reset cause occurs, F2MC-16LX terminates the currently executing processing and waits for reset release. ■ Reset Cause Occurrence A reset is caused by the following factors: • Power-on reset • Hardware standby release • Watch-dog timer overflow • External reset request via RST pin • Reset request by software ■ Operation after Reset Release When a reset cause is removed, the F2MC-16LX immediately outputs the address in which the reset vector is stored, then fetches the reset vector and mode data. The reset vector and mode data are assigned to the four bytes between FFFFDCH and FFFFDFH. After reset is released, the reset vector and mode data are transferred to the registers by the hardware as described in Figure 5.2-1 . The bus mode after the reset vector and mode data are read is specified by the mode data. Figure 5.2-1 Source and Destination of Reset Vector and Mode Data F2MC-16LX CPU Mode Memory space Register FFFFDFH Mode data FFFFDEH Reset vector bit23 to bit16 FFFFDDH Reset vector bit15 to bit8 FFFFDCH Reset vector bit7 to bit0 Micro ROM Reset sequence PCB PC Note: For MB90F598/F598G, the reset vector and mode data have predetermined values by the hard-wired logic (refer to section 23.9 "Reset Vector Addresses in Flash Memory"). If a reset vector other than FFA000H or mode data other than 00H are used in a software code, then this code will behave differently between Mask ROM and Flash devices. 77 CHAPTER 5 CLOCK AND RESET ■ Registers not Initialized by Reset Input This microcontroller contains registers initialized only by a power-on reset. Table 5.2-1 lists registers not initialized by each reset cause. Table 5.2-1 Registers not Initialized by Reset Input CKSCR LPMCR Type of reset WS1 WS0 MCS CS1 CS0 CG1 CG0 Software reset (Only RST is used.) N N N N N N N Watchdog reset N N Y N N Y Y Power-on reset Y Y Y Y Y Y Y Hardware standby N N Y N N Y Y WS1 and WS0:Set the oscillation stabilization time for the main clock. MCS: Specifies the machine clock (0 = PLL clock or 1 = main clock). CS1 and CS0:Set the multiplication factor for the PLL clock. WDCS: Specifies the input clock source for the watchdog timer (0 = watch timer or 1 = timebase timer). Y: Initialized N: Not initialized In particular, handle the MCS bit carefully because it sets the machine clock. For example, if power-on does not satisfy the power-on reset specification, no power-on reset occurs. For this reason, the internal operating frequency may become outside the valid operation range, because MCS is not initialized, and the microcontroller may not operate normally. If the CPU crashes for some reason and MCS, CS1, or CS0 is rewritten, the internal operating frequency may also become outside the valid operation range. The microcontroller may not be able to recover normally from this status by RST input only (however, if the internal watchdog state occurs, MCS is initialized and the microcontroller operates normally). When either of the above cases occurs, use of HST plus RST (connecting HST and RST with a jumper) is recommended. Table 5.2-2 lists registers that are not initialized by reset input using HST plus RST. Note that the operation status after the reset is released differs depending on the reset input type, HST plus RST reset input, or only RST input, as listed in Table 5.2-2 . Table 5.2-2 Registers not Initialized by Reset Input CKSCR LPMCR Type of reset HST + RST Y: Initialized N: Not initialized 78 WS1 WS0 MCS CS1 CS0 CG1 CG0 N N Y N N Y Y CHAPTER 5 CLOCK AND RESET Figure 5.2-2 Operation Transition by Reset Input [Operation Transition by Reset Input] Reset input (RST, HST+RST) A. Oscillation status Status Only RST used (HST ="H") Oscillating HST + RST used Waiting for main clock oscillation stabilization Oscillating Stopped Main clock operation enabled B. Execution timing (L: Stop, H: Start) Only RST used (HST ="H") HST plus RST used Main clock mode Oscillation stabilization time set before reset input Power-on reset Vcc (power supply) Status Power-on reset Oscillating Stopped Waiting for main clock oscillation stabilization Main clock operation enabled Oscillation stabilization time of 218main clock cycles Main mode 79 CHAPTER 5 CLOCK AND RESET 5.3 Reset Causes Table 5.3-1 lists the five reset causes. The machine clock and watch-dog function are initialized differently for each reset cause. The reset cause register indicates the reset cause. ■ Reset Causes Table 5.3-1 Reset Causes Reset Cause Machine clock Watch-dog timer Oscillation stabilization wait Power-on When the power is turned on Main clock Stop Yes Hardware standby "L" level input to HST pin Main clock Stop Yes Watch-dog timer Watch-dog timer overflow Main clock Stop Yes External pin "L" level input to RST pin Previous status maintained Previous status maintained No Software "0" written to RST bit of LPMCR Previous status maintained Previous status maintained No * In stop or hardware standby mode, a reset input allows for oscillation stabilization time regardless of the reset cause. * The oscillation stabilization time for a power-on reset is fixed to 218 cycles of source oscillation. For other types of reset, the oscillation stabilization wait time is determined by CS1 and CS0 of the clock selection register. As shown in Figure 5.3-1 , each reset cause has a corresponding flip-flop. The contents of the flip-flop can be obtained by reading the watch-dog timer control register. If identifying the reset cause is required after the reset is released, ensure that the value read from the watch-dog timer control register is processed by software and processing branches to an appropriate program. Figure 5.3-2 is a diagram of the watch-dog timer control register. 80 CHAPTER 5 CLOCK AND RESET Figure 5.3-1 Reset Cause Bit Block Diagram HST pin HST=L Power on Power-on detection circuit RST pin RST=L H Hardware standby release detection circuit R S S Q External reset request detection circuit R S F/F F/F Watch-dog timer reset detection circuit R S F/F Q Without periodic clear F/F Q Q LPMCR.RST bit write detection circuit R S F/F RST bit set Q Delay circuit WDTC register WDTC register read F2MC-16LX internal bus Figure 5.3-2 WDTC (Watch-dog Timer Control Register bit Address: 0000A8H 7 6 PONR STBR (R) (X) Read/write Initial value 5 4 WRST ERST (R) (X) (R) (X) (R) (X) 3 2 1 0 SRST WTE WT1 WT0 (R) (X) (W) (1) (W) (1) (W) (1) WDTC When there are multiple reset causes, the corresponding reset cause bits in the watch-dog timer control register are set. Therefore, if an external reset request and a watch-dog reset occur at the same time, both the ERST and WRST bits are set to 1. A power-on reset is an exception; while the PONR bit is 1, the values of other bits do not indicate the correct reset causes. Therefore, design software so that the other reset cause bit values are ignored while the PONR bit is set to 1. Table 5.3-2 Reset Cause Bits Reset cause PONR STBR WRST ERST SRST Power-on 1 -– -– -– -– Hardware standby * 1 * * * Watch-dog timer * * 1 * * External pin * * * 1 * RST bit * * * * 1 (An asterisk (*) in the table means that the previous value is maintained.) A reset cause bit is cleared only by reading the watch-dog timer control register. Thus, once a reset occurs, the corresponding reset cause bit remains 1 even if another reset cause occurs. 81 CHAPTER 5 CLOCK AND RESET 82 CHAPTER 6 LOW-POWER CONTROL CIRCUIT CHAPTER 6 LOW-POWER CONTROL CIRCUIT This chapter explains the functions and operation of the low-power control circuit. 6.1 "Outline of Low-Power Control Circuit" 6.2 "Registers of Low-power Control Circuit" 6.3 "Low-Power Mode Operation" 6.4 "Intermittent CPU Operation" 6.5 "Switching Machine Clocks" 6.6 "Status Transition of Clock Selection" 83 CHAPTER 6 LOW-POWER CONTROL CIRCUIT 6.1 Outline of Low-Power Control Circuit The MB90595 Series supports various operation modes to help reduce the power dissipation. The operation modes include PLL clock mode, PLL sleep mode, timer mode, main clock mode, main sleep mode, stop mode, and hardware standby mode. Modes other than PLL clock mode are classified as low-power modes. ■ Outline of Low-power Control Circuit In main clock mode or main sleep mode, the main clock (OSC oscillation clock) is used. The operation clock is generated by dividing the main clock by two, and the PLL clock (VCO oscillation clock) is stopped. In PLL sleep mode or main sleep mode, only the CPU operation clock is stopped. All other clocks are in operation. In timer mode, only the time-base timer is in operation.In stop mode or hardware standby mode, oscillation is stopped. The data can be maintained at the lowest power consumption possible. The intermittent CPU operation function is used to intermittently enable the clock supplied to the CPU when a register, internal memory, or internal resource is accessed. CPU execution is slowed while high-speed clock is supplied to the internal resources, enabling processing at lowpower consumption. The PLL clock multiplication factor can be selected from 1, 2, 3, and 4 by setting the CS1 and CS0 bits. The oscillation stabilization wait time for the main clock upon release of stop or hardware standby mode can be set by the WS1 and WS0 bits. Note: In attempting to switch the clock mode, do not attempt to switch to another clock mode or low-power consumption mode until the first switching is completed. The MCM bit of the clock selection register (CKSCR) indicates that switching is completed. 84 CHAPTER 6 LOW-POWER CONTROL CIRCUIT ■ Block Diagram of Low-power Control Circuit Figure 6.1-1 Low-power Control Circuit and Clock Generator CKSCR MCM MCS Main clock (OSC oscillation) PLL multiplication circuit 1 2 3 4 1/2 CPU clock generation CKSCR CS1 CPU clock selector 0/9/17/33 intermittent cycle selection CS0 F2MC-16 bus CPU clock LPMCR CG1 CG0 Intermittent CPU operation function Cycle count selection circuit Peripheral clock generation LPMCR SLP STP Standby control circuit Peripheral clock HST RST Release activation HST pin Interrupt request or RST CKSCR WS1 WS0 Oscillation stabilization wait time selector 210 213 215 217* Clock input Time base timer Time base clock 212 214 216 219 LPMCR SPL LPMCR RST Pin high-impedance control circuit Internal reset generation circuit Pin HI-Z RST pin Internal RST To watch-dog timer WDGRST 18 *: 2 at power-on 85 CHAPTER 6 LOW-POWER CONTROL CIRCUIT 6.2 Registers of Low-power Control Circuit The low-power control circuit has the following two registers: • Low-power mode control register (LPMCR) • Clock selection register (CKSCR) ■ Registers of Low-power Control Circuit Low power mode control register 7 6 Address: 5 4 3 2 1 0 0000A0H STP SLP SPL RST Reserved CG1 CG0 Reserved Read/write Initial value (W) (0) (W) (0) (R/W) (0) (W) (1) (-) (1) (R/W) (0) (R/W) (0) (-) (0) Bit No. LPMCR Clock selection register Address: 0000A1H Read/write Initial value 15 14 Reserved MCM (-) (1) (R) (1) R/W : Readable/Writable W : Write only R : Read only : Undefined 86 13 12 11 10 9 8 WS1 WS0 Reserved MCS CS1 CS0 (R/W) (1) (R/W) (1) (-) (1) (R/W) (1) (R/W) (0) (R/W) (0) Bit No. CKSCR CHAPTER 6 LOW-POWER CONTROL CIRCUIT 6.2.1 Low-Power Mode Control Resister (LPMCR) The low-power mode control register works in combination with the clock selection register to set various types of operation modes for reduction of power consumption. ■ Low-power Mode Control Register (LPMCR) 7 6 5 4 3 2 1 0000A0H STP SLP SPL RST Reserved CG1 CG0 Read/write Initial value (W) (0) (W) (0) (R/W) (0) (W) (1) (-) (1) (R/W) (0) (R/W) (0) Address: 0 Bit No. Reserved LPMCR (-) (0) R/W : Readable/Writable W : Write only : Undefined [bit7] STP Writing "1" to this bit starts timer mode (CKSCR.MCS=0) or stop mode (CKSCR.MCS=1). Writing "0" performs no operation. This bit is cleared to "0" upon a reset, clock release, or stop release. This is a write-only bit. '0' is always read from this bit. [bit6] SLP Writing "1" to this bit starts sleep mode. Writing "0" performs no operation. This bit is cleared to "0" upon a reset, clock release, or stop release. Writing "1" to the STOP and SLP bits simultaneously starts clock or stop mode. This is a write-only bit. "0" is always read from this bit. [bit5] SPL When "0" is written to this bit, the external pin level in timer mode or stop mode is maintained. When "1" is written to this bit, the external pin in timer mode or stop mode is set to high impedance. This bit is cleared to "0" upon a reset. This bit is readable and writable. Note: It is recommended to set SPL to "1". If it is set to "0", take care that all inputs are defined in timer mode or stop mode (either set the ports to output or apply defined input signals). [bit4] RST Writing "0" to this bit generates internal reset signals for three machine cycles. Writing "1" performs no operation. "1" is always read from this bit. [bit3] Reserved This bit must be set to "1". 87 CHAPTER 6 LOW-POWER CONTROL CIRCUIT [bit2, bit1] CG1 and CG0 These bits are used to set the clock pause cycle count during intermittent CPU operation. These bits are initialized to "00" upon a reset by power-on, hardware standby, or watch-dog. These bits are not initialized by any other type of reset. These bits are readable and writable. The intermittent CPU operation function pauses the clock to the CPU when a register, internal memory, or internal resource is accessed, thus delaying the activation of the internal bus cycle. CPU execution is slowed while high-speed clock is supplied to an internal resource, enabling processing at low-power consumption. Table 6.2-1 CG Bit Setting CG1 CG0 CPU clock pause cycle count 0 0 0 cycle (CPU clock = Resource clock) 0 1 9 cycles (CPU clock: Resource clock = 1:3 to 4 approx.) 1 0 17 cycles (CPU clock: Resource clock = 1:5 to 6 approx.) 1 1 33 cycles (CPU clock: Resource clock = 1:9 to 10 approx.) [bit0] Reserved This bit must be set to "0". Note: To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode or watch mode, disable the output of peripheral functions, and set the STP bit of the low-power mode control register (LPMCR) to 1. This applies to the following pins: P04/OUT0, P05/OUT1, P06/OUT2, P07/OUT3, P10/PPG0, P11/PPG1, P12/PPG2, P13/ PPG3, P14/PPG4, P15/PPG5, and P17/TOT1 88 CHAPTER 6 LOW-POWER CONTROL CIRCUIT 6.2.2 Clock Selection Register (CKSCR) The clock selection register sets and controls the CPU machine lock, and sets the oscillation stabilization wait time applicable during power on or oscillation recovery. ■ Clock Selection Register (CKSCR) Address: 0000A1H Read/write Initial value 15 14 13 12 11 10 9 Reserved MCM WS1 WS0 (-) (1) (R) (1) (R/W) (1) (R/W) (1) 8 Reserved MCS CS1 CS0 (-) (1) (R/W) (1) (R/W) (0) (R/W) (0) Bit No. CKSCR R/W : Readable/Writable R : Read only : Undefined [bit15] Reserved This bit must be set to "1". [bit14] MCM This bit indicates whether the main clock or PLL clock is selected as the machine clock. "0" indicates that the PLL clock is selected, and "1" indicates that the main clock is selected. When MCS=0 and MCM=1, the system is waiting for the PLL clock oscillation to stabilize. The PLL clock oscillation stabilization wait time is fixed to 213 main clock cycles. [bit13, bit12] WS1, WS0 These bits are used to set the main clock oscillation stabilization wait time upon release of stop or hardware standby mode. These bits are initialized to "11" upon a power-on reset. These bits are not initialized by any other type of reset. These bits are readable and writable. Table 6.2-2 WS Bit Setting WS1 WS0 Oscillation stabilization wait time (at 4 MHz source oscillation) 0 0 About 256 µs (210 counts of source oscillation) 0 1 About 2.05 ms (213 counts of source oscillation) 1 0 About 8.19 ms (215 counts of source oscillation) 1 1 About 32.77 ms (217 counts of source oscillation) About 65.54 ms (218 counts of source oscillation) only upon with the power-on reset [bit11] Reserved This bit must be set to "1". 89 CHAPTER 6 LOW-POWER CONTROL CIRCUIT [bit10] MCS This bit is used to select the main clock or PLL clock as the machine clock. Writing "0" selects the PLL clock and writing "1" selects the main clock. When this bit is updated from "1" to "0", the PLL clock oscillation stabilization wait period is created by automatically clearing the time-base timer and the TBOF bit of the time-base timer control register. The oscillation stabilization wait time for the PLL clock is fixed to 213 main clock cycles. (The oscillation wait time is about 2 ms at 4 MHz source oscillation.) When the main clock is selected, the operation clock is generated by dividing the main clock by two. (The operation clock is 2 MHz at 4 MHz source oscillation.) This bit is initialized to "1" by a power-on reset, hardware standby, or watch-dog reset. It is not initialized by the external reset (RST pin) or by the software reset (the RST bit in the LPMCR register) Note: When updating the MCS bit from "1" to "0", ensure that the time-base timer interrupt is masked by the TBIE bit or the ILM bit of the CPU. [bit9, bit8] CS1, CS0 These bits are used to select the multiplication factor of the PLL clock. These bits are initialized to "00" by a power-on reset. They are not initialized by any other type of reset. Write is disabled when "0" is written to the MCS bit. To update the CS bit, set "1" in the MCS bit (to start main clock mode). These bits are readable and writable. Table 6.2-3 CS Bit Setting CS1 CS0 Machine clock (at 4 MHz source oscillation) 0 0 4 MHz (Operation frequency = OSC oscillation frequency) 0 1 8 MHz (Operation frequency = OSC oscillation frequency *2) 1 0 12 MHz (Operation frequency = OSC oscillation frequency *3) 1 1 16 MHz (Operation frequency = OSC oscillation frequency *4) Note: When the operating voltage is 5 V, the OSC source oscillation can be between 3 MHz and 5 MHz. When an external clock source is used, its frequency can be between 3 MHz and 16MHz. Since the highest operating frequency for the CPU and peripheral resource circuits is 16 MHz, however, normal operation is not guaranteed if a multiplication factor resulting in a higher frequency than 16 MHz is specified. For example, if the external clock frequency is 16 MHz, only 1 can be specified as the multiplication factor. The lowest operating frequency of the VCO oscillation is 4 MHz, and an oscillation below 4 MHz must not be specified. 90 CHAPTER 6 LOW-POWER CONTROL CIRCUIT 6.3 Low-Power Mode Operation Table 6.3-1 lists the chip status in each operation mode. ■ Low-Power Mode Operation Table 6.3-1 Low-power Mode Status Transition condition Oscillation & T.B.T PLL CPU Peripheral Pin Main sleep MCS=1 SLP=1 Operating Stopped Stopped Operating Operating External Reset Interrupt PLL sleep MCS=0 SLP=1 Operating Operating Stopped Operating Operating External Reset Interrupt Timer (SPL=0) MCS=0 STP=1 Operating Stopped Stopped Stopped Held * External Reset External Interrupt Timer (SPL=1) MCS=0 STP=1 Operating Stopped Stopped Stopped HI-Z External Reset External Interrupt Stop (SPL=0) MCS=1 STP=1 Stopped Stopped Stopped Stopped Held * External Reset External Interrupt Stop (SPL=1) MCS=1 STP=1 Stopped Stopped Stopped Stopped HI-Z External Reset External Interrupt Hardware standby HST=L Stopped Stopped Stopped Stopped HI-Z HST=H Release method * : When SPL is set to 0 in timer mode or stop mode, stable digital values must always be input. Otherwise, power is consumed in the input buffer (except for A/D analog input). Note: To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode or watch mode, disable the output of peripheral functions, and set the STP bit of the low-power mode control register (LPMCR) to 1. This applies to the following pins: P04/OUT0, P05/OUT1, P06/OUT2, P07/OUT3, P10/PPG0, P11/PPG1, P12/PPG2, P13/ PPG3, P14/PPG4, P15/PPG5, and P17/TOT1 91 CHAPTER 6 LOW-POWER CONTROL CIRCUIT ■ Note of Low-power Mode Control Register Access Writing data to the low-power mode control register starts low-power mode (stop or sleep mode). In this case, use an instruction shown in Table 6.3-2 . If any other instruction is used to start low-power mode, misoperation may result. Any instruction can be used to control functions other than transition of the low-power mode control register to low-power mode. To write data to the low-power mode control register in word length, ensure that the data is written to an even-number address. If low-power mode is started by writing data to an oddnumber address, misoperation may result. Table 6.3-2 List of Instructions Used for Transition to Low-power Mode MOV io,#imm8 MOV io,A MOV @RLi+dip8,A MOVW io,#imm16 MOVW io,A MOVW @RLi+dip8,A SETB io:bp CLRB io:bp MOV dir,#imm8 MOV dir,A MOV eam,#imm8 MOV addr16,A MOV eam,Ri MOV eam,A MOVW dir,#imm16 MOVW dir,A MOVW eam,#imm16 MOVW eam,RWi MOVW addr16,A MOVW eam,A SETB dir:bp CLRB dir:bp SETB addr16:bp CLRB addr16:bp ■ Notes on the Transition to Low-power Mode To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode or watch mode, use the following procedure: 1. Disable the output of peripheral functions. 2. Set the SPL bit of the low-power mode control register (LPMCR) to "1", and set the STP bit to "1". 92 CHAPTER 6 LOW-POWER CONTROL CIRCUIT 6.3.1 Sleep Mode In sleep mode, only the clock supplied to the CPU is stopped. In this mode the peripheral circuits keep operating while the CPU is stopped. ■ Transition to Sleep Mode The standby control circuit is set in sleep mode by writing "1" to the SLP bit and "0" to the STP bit of the low-power mode control register. If an interrupt request has been issued when "1" is written to the SLP bit, the standby control circuit does not enter sleep mode. Therefore, the CPU executes the next instruction if the interrupt cannot be accepted, or immediately branches to the interrupt processing routine if the interrupt can be accepted. In sleep mode, the values of special registers such as the accumulator and the internal RAM are maintained. ■ Releasing Sleep Mode The standby control circuit releases sleep mode in the event of a reset input or an interrupt. If sleep mode is released by a reset, the reset status takes effect after sleep mode is released. If a peripheral circuit or similar issues an interrupt request of a higher interrupt level than 7 in sleep mode, the standby control circuit releases sleep mode. After sleep mode is released, processing is handled as normal interrupt processing. The CPU executes interrupt processing if the interrupt can be accepted according to the I flag, ILM, and the interrupt control register (ICR). If the interrupt cannot be accepted, processing continues from the instruction following the instruction that was being executed before the transition to sleep mode. Note: Usually, interrupt processing is started after the instruction following the instruction that was executed during the transition to sleep mode. 93 CHAPTER 6 LOW-POWER CONTROL CIRCUIT 6.3.2 Timer Mode In timer mode, the operations other than the source oscillation and time-base timer are stopped. Almost all chip functions are stopped in this mode. ■ Transition to Timer Mode The standby control circuit is set to timer mode when the MCS bit of the clock selection register is "0" and "1" is written to the STP bit of the low-power mode control register. In timer mode, all operations are stopped except for the source oscillation and time-base timer. Most functions of the chip stop. Using the STP bit of the low-power mode control register, the I/O pin may be maintained at the immediately preceding status or at high impedance in timer mode. If an interrupt request has been issued when "1" is written to the STP bit, the standby control circuit does not enter timer mode. In timer mode, the values of special registers such as the accumulator and the internal RAM are maintained. Note: To set a pin to high impedance when the pin is shared by a peripheral function and a port in watch mode, disable the output of peripheral functions, and set the STP bit of the low-power mode control register (LPMCR) to 1. This applies to the following pins: P04/OUT0, P05/OUT1, P06/OUT2, P07/OUT3, P10/PPG0, P11/PPG1, P12/PPG2, P13/ PPG3, P14/PPG4, P15/PPG5, and P17/TOT1 ■ Releasing Timer Mode The standby control circuit releases timer mode in the event of a reset input or an interrupt. If timer mode is released by a reset, the reset status takes effect after timer mode is released. To return from timer mode, the standby control circuit initially releases timer mode, then enters the PLL clock oscillation stabilization wait state. The MCS bit is not cleared by an external reset, so the reset sequence is performed using the main clock if the reset period is shorter than the PLL clock oscillation stabilization wait period. The PLL clock oscillation stabilization wait period is 213 to 3 × 213 main clock cycles depending on the time-base timer status, because the timebase timer is not cleared. If a peripheral circuit or similar issues an interrupt request of a higher interrupt level than 7 in timer mode, the standby control circuit releases timer mode. After the timer mode is released, processing is handled as normal interrupt processing. The CPU executes interrupt processing if the interrupt can be accepted according to the I flag, ILM, and the interrupt control register (ICR). If the interrupt cannot be accepted, processing continues from the instruction following the instruction that was being executed during transition to timer mode. Note: Usually, interrupt processing is started after the instruction following the instruction that was being executed during the transition to timer mode. The standby control circuit enters PLL clock oscillation stabilization wait status when timer mode is released. If the PLL clock is not used, write '1' to the MCS bit by an instruction immediately following the reset or interrupt. 94 CHAPTER 6 LOW-POWER CONTROL CIRCUIT 6.3.3 Stop Mode In stop mode, source oscillation is stopped and therefore all chip functions are stopped. Data can be retained with the least power consumption. ■ Transition to Stop Mode The standby control circuit is set to stop mode when the MCS bit of the clock selection register is "1" and "1" is written to the STP bit of the low-power mode control register. In stop mode, the source oscillation is stopped and all functions of the chip are stopped. Therefore, data can be maintained at the lowest power consumption possible. Using the SPL bit of the LPMCR, the I/O pin may be maintained at the immediately preceding status or at high impedance in stop mode. Note: It is recommended to set SPL to "1". If it is set to "0", take care that all inputs are defined in stop mode (either set the ports to output or apply defined input signals). Note: To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode, disable the output of peripheral functions, and set the STP bit of the low-power mode control register (LPMCR) to 1. This applies to the following pins: P04/OUT0, P05/OUT1, P06/OUT2, P07/OUT3, P10/PPG0, P11/PPG1, P12/PPG2, P13/ PPG3, P14/PPG4, P15/PPG5, and P17/TOT1 If an interrupt request has been issued when "1" is written to the STP bit, the standby control circuit does not enter the stop mode. In stop mode, the values of special registers such as the accumulator and the internal RAM are maintained. ■ Releasing Stop Mode The standby control circuit releases stop mode in the event of a reset input or an interrupt. If stop mode is released by a reset, the reset status takes effect after stop mode is released. If a peripheral circuit or similar issues an interrupt request of a higher interrupt level than 7 in stop mode, the standby control circuit releases stop mode. After stop mode is released, the processing is handled as normal interrupt processing after the main clock oscillation stabilization wait period specified by the WS1 and WS0 bits of CKSCR. The CPU executes interrupt processing if the interrupt can be accepted according to the I flag, ILM, and the interrupt control register (ICR). If the interrupt cannot be accepted, processing continues from the instruction following the instruction that was being executed during transition to stop mode. Note: Usually, interrupt processing is started after the instruction following the instruction that was being executed during the transition to stop mode. 95 CHAPTER 6 LOW-POWER CONTROL CIRCUIT ■ Setting the Oscillation Stabilization Wait Time Use the WS1 and WS0 bits to specify the oscillation stabilization wait time when stop mode or hardware standby mode is released. Specify the oscillation stabilization wait time according to the types and characteristics of the oscillator circuit and oscillator device connected to the X0 and X1 pins. These bits are not initialized upon a reset, except for a power-on reset. Upon a power-on reset, these bits are initialized to "11". Therefore, at power-on, the oscillation stabilization wait time is about 217 counts of source oscillation. 96 CHAPTER 6 LOW-POWER CONTROL CIRCUIT 6.3.4 Hardware Standby Mode In hardware standby mode, oscillation is stopped and every I/O pin is put in the highimpedance state while the HST pin is at the "L" level regardless of any other states including the reset state. ■ Transition to Hardware Standby Mode The standby control circuit can be set in hardware standby mode from any status by setting the HST pin at "L" level. In hardware standby mode, oscillation is stopped and all I/O pins are set to high impedance while the HST pin is at "L" level, regardless of other status including reset. In hardware standby mode, the internal RAM contents are maintained but the special registers such as the accumulator are initialized. ■ Releasing Hardware Standby Mode Hardware standby mode can be released only by the HST pin. When the HST pin is set at "H" level, the standby control circuit releases hardware standby mode, enables the internal reset signal, and enters oscillation stabilization wait status. After the oscillation stabilization wait period, the standby control circuit releases the internal reset, and consequently the CPU starts execution from the reset sequence. ■Setting the Oscillation Stabilization Wait Time Use the WS1 and WS0 bits to specify the oscillation stabilization wait time when stop mode or hardware standby mode is released. Specify the oscillation stabilization wait time according to the types and characteristics of the oscillator circuit and oscillator device connected to the X0 and X1 pins. These bits are not initialized upon a reset, except for a power-on reset. Upon a power-on reset, these bits are initialized to "11". Therefore, at power-on, the oscillation stabilization wait time is about 217counts of source oscillation. 97 CHAPTER 6 LOW-POWER CONTROL CIRCUIT 6.4 Intermittent CPU Operation The intermittent CPU operation function pauses the clock supplied to the CPU when a register, or internal memory (ROM, RAM, I/O, or resource) is accessed, delaying the activation of the internal bus cycle. The CPU execution speed is decreased while a high-speed clock is supplied to internal resources, thus enabling processing at lowpower consumption. ■ Intermittent CPU Operation Figure 6.4-1 is a diagram of intermittent CPU operation. The cycle count for clock pausing is specified by the CG1 and CG0 bits. The external bus operation itself is performed using the same clock as that for the resources. The instruction execution time using the intermittent CPU operation function can be obtained by adding the compensation value to the ordinary execution time. The compensation value is obtained by multiplying the number of accesses to a register, internal memory, or internal resource by the cycle count for pausing. Figure 6.4-1 Intermittent CPU Operation Peripheral clock CPU clock Intermittent operation pause cycle 98 Internal bus activation cycle CHAPTER 6 LOW-POWER CONTROL CIRCUIT 6.5 Switching Machine Clocks Write data to the MCS bit of the CKSCR register to switch between the main clock and PLL clock. ■ Switching between Main Clock and PLL Clock When the MCS bit is changed from "1" to "0", the PLL clock takes over the main clock after the PLL clock oscillation stabilization wait time (213 machine clock cycles). When the MCS bit is changed from "0" to "1", the main clock takes over the PLL clock when the edges of the PLL and main clocks match (after about 1 to 8 PLL clock cycles). Writing to the MCS bit does not change the machine clock immediately. To manipulate a resource that depends on the machine clock, always reference the MCM bit before hand to check that the machine clock has been switched. Note: When the clock mode is switched, do not switch to low-power consumption mode and other clock mode before this switching is completed. Confirm the completion of clock mode switching by referring to the MCM bit of the clock selection register (CKSCR). ■ Initializing the Machine Clock The MCS bit cannot be initialized by a reset that uses the RST external reset pin or the RST bit. The MCS bit is initialized to "1" by any other reset. 99 CHAPTER 6 LOW-POWER CONTROL CIRCUIT 6.6 Status Transition of Clock Selection The oscillation stabilization wait time for the PLL clock is fixed to 213 main clock cycles. (The oscillation wait time is about 2 ms at a source oscillation of 4 MHz.) ■ Status Transition of Clock Selection When the operating voltage is 5 V, the OSC source oscillation can be between 3 MHz and 5 MHz. When an external clock source is used, its frequency can be between 3 MHz and 16MHz. Figure 6.6-1 is a diagram of status transition of clock selection. Figure 6.6-1 Status Transition of Clock Selection Power on ➀ Main ⇒PLLx MCS = 0 MCM = 1 CS1/0=xx Main MCS = 1 MCM = 1 CS1/0=xx ➆ ➁ ➂ ➃ PLL⇒Main MCS = 1 MCM = 0 CS1/0=00 ➅ PLL1 multiplication MCS = 0 MCM = 0 CS1/0=00 ➆ PLL2 multiplication MCS = 0 PLL2⇒Main ➆ MCS = 1 ➅ MCM = 0 CS1/0=01 MCM = 0 CS1/0=01 ➄ CS1/0=10 PLL3 multiplication MCS = 0 MCM = 0 CS1/0=10 PLL4⇒Main MCS = 1 MCM = 0 CS1/0=11 PLL4 multiplication MCS = 0 MCM = 0 CS1/0=11 PLL3⇒Main ➆ ① ② ③ ④ ⑤ ⑥ ⑦ MCS = 1 MCM = 0 ➅ ➅ MCS bit clear End of PLL clock oscillation stabilization wait & CS1/0=00 End of PLL clock oscillation stabilization wait & CS1/0=01 End of PLL clock oscillation stabilization wait & CS1/0=10 End of PLL clock oscillation stabilization wait & CS1/0=11 MCS bit set (including hardware standby and watch-dog reset) Synchronization timing between PLL clock and main clock Note: When the clock mode is switched, do not switch to low-power consumption mode and other clock mode before this switching is completed. Confirm the completion of clock mode switching by referring to the MCM bit of the clock selection register (CKSCR). 100 CHAPTER 7 MEMORY ACCESS MODES CHAPTER 7 MEMORY ACCESS MODES This chapter explains the functions and operation of the memory access modes. 7.1 "Outline of Memory Access Modes" 7.2 "Mode Pins" 7.3 "Mode Data" 101 CHAPTER 7 MEMORY ACCESS MODES 7.1 Outline of Memory Access Modes The F2MC-16LX supports the following two memory access modes for each of access method and access area: • Operation mode • Bus mode ■ Memory Access Modes Operation mode RUN Flash programming Bus mode Single chip For the MB90595 Series, the external bus function is not supported. Therefore the following part of this document is not fully supported. In user applications, please use the MB90595 Series in the single chip mode. To set the MB90595 Series into the single chip mode, the mode inputs (MD2 to 0) should be "011" and the most significant two bits of the mode data (M1 and M0) should be "00". ❍ Operation mode Operation mode means the mode for controlling the device operation status. The operation mode is specified by the MDx mode setting pin and the Ex bit in mode data. By selecting an operation mode, normal operation, internal test program activation, or special test function activation can be performed. ❍ Bus mode Bus mode means the mode for controlling the internal ROM operation and external access function. The bus mode is specified by the MDx mode setting pin and the Mx bit in mode data. The MDx mode setting pin specifies the bus mode for reading the reset vector and mode data, and the Mx bit in mode data specifies the bus mode for normal operation. 102 CHAPTER 7 MEMORY ACCESS MODES 7.2 Mode Pins A desired mode can be specified by combining three external pins (MD2, MD1, and MD0). ■ Mode Pins Table 7.2-1 Mode Pins and Modes Mode pin setting MD2 MD1 MD0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Mode name Reset vector access area External data bus width Remarks (Specification not allowed) Internal vector mode Internal (Mode data) Reset sequence and later segments are controlled based on mode data. (Specification not allowed) Flash memory serial programming * Flash memory - - - - Mode for use of a parallel programmer * : Data cannot be written only by setting the flash serial programming mode by mode pins. Other must be set. For details, see the examples of flash memory serial programming connection. 103 CHAPTER 7 MEMORY ACCESS MODES 7.3 Mode Data Mode data is stored at FFFFDFH of main memory and used for controlling the CPU operation. This data is fetched during a reset sequence and stored in the mode register inside the device. The mode register value can be changed only by a reset sequence. The setting of this register is valid after the reset sequence. Always set the reserved bits to "0". ■ Mode Data Figure 7.3-1 is a diagram of the setting of the bits. Figure 7.3-1 Mode Data Structure bit Mode data 7 6 5 4 3 2 1 0 M1 M0 0 0 0 0 0 0 Function extension bit (reserved area) Bus mode setting bits 104 CHAPTER 7 MEMORY ACCESS MODES ■ Bus Mode Setting Bits These bits are used to specify the operation mode after the reset sequence is completed. Table 7.3-1 shows the relationship between the bits and the functions. Table 7.3-1 Bus Mode Setting Bits and Functions M1 M0 0 0 0 1 1 0 1 1 Function Single chip mode (Inhibited) Figure 7.3-2 is a diagram of the correspondence between the access areas and physical addresses for each bus mode. Figure 7.3-2 Access Areas and Physical Addresses in Each Bus Mode FFFFFFH ROM Devicedependent #1 010000H ROM 004000H 002000H I/O (all initial) 001900H Devicedependent #3 000100H 0000C0H 000000H RAM : No access : Internal access I/O Single chip Note: "Device-dependent" means an address that is determined depending on the device. 105 CHAPTER 7 MEMORY ACCESS MODES ■ Recommended Setting Table 7.3-2 lists a sample recommended setting of mode pins and mode data. Table 7.3-2 Sample Recommended Setting of Mode Pins and Mode Data Sample setting Single chip MD2 MD1 MD0 M1 M0 0 1 1 0 0 Note: For the MB90595 series devices with flash memory, the mode data have predetermined values by the hard-wired logic (refer to Section 23.9 "Reset Vector Address in Flash Memory"). If a mode data than 00H is used in a software code, then this code will behave differently between Mask and Flash devices. 106 CHAPTER 8 I/O PORTS CHAPTER 8 I/O PORTS This chapter explains the I/O port functions and operation. 8.1 "I/O Ports" 8.2 "I/O Port Registers" 107 CHAPTER 8 I/O PORTS 8.1 I/O Ports Each pin of the ports can be specified as input or output using the direction register if the corresponding peripheral does not use the pin. When a pin is specified as input, the logic level at the pin is read. When a pin is specified as output, the data register value is read. The above also applies to a read operation for the read-modify-write instructions. ■ I/O Ports For only ports 0 to 3 among other I/O ports, the corresponding bits of the port direction register must be set to 1 to enable output of peripheral signals. When a pin is used as an output of other peripheral function, the logic level at the pin is read regardless of the direction register value. It is generally recommended that the read-modify-write instructions should not be used for setting the data register prior to setting the port as an output. This is because the read-modifywrite instruction in this case results reading the logic level at the port rather than the register value. Figure 8.1-1 is a block diagram of the I/O ports. Figure 8.1-1 I/O Port Block Diagram Internal data bus Data register read Data register Data register write Direction register Direction register write Direction register read 108 Pin CHAPTER 8 I/O PORTS 8.2 I/O Port Registers The following three types of I/O port registers are used: • Port data registers (PDR0 to PDR9) • Port direction registers (DDR0 to DDR9) • Port analog input enable register (ADER) ■ I/O Port Registers Figure 8.2-1 shows the I/O port registers. Figure 8.2-1 I/O Port Registers 7 6 5 4 3 2 1 0 Address : 000000H P07 P06 P05 P04 P03 P02 P01 P00 Port 0 data register (PDR0) Address : 000001H P17 P16 P15 P14 P13 P12 P11 P10 Port 1 data register (PDR1) Address : 000002H P27 P26 P25 P24 P23 P22 P21 P20 Port 2 data register (PDR2) Address : 000003H P37 P36 P35 P34 P33 P32 P31 P30 Port 3 data register (PDR3) Address : 000004H P47 P46 P45 P44 P43 P42 P41 P40 Port 4 data register (PDR4) Address : 000005H P57 P56 P55 P54 P53 P52 P51 P50 Port 5 data register (PDR5) Address : 000006H P67 P66 P65 P64 P63 P62 P61 P60 Port 6 data register (PDR6) Address : 000007H P77 P76 P75 P74 P73 P72 P71 P70 Port 7 data register (PDR7) Address : 000008H P87 P86 bit Address : 000009H P85 P84 P83 P82 P81 P80 Port 8 data register (PDR8) P95 P94 P93 P92 P91 P90 Port 9 data register (PDR9) 7 6 5 4 3 2 1 0 Address : 000010H D07 D06 D05 D04 D03 D02 D01 D00 Port 0 direction register (DDR0) Address : 000011H D17 D16 D15 D14 D13 D12 D11 D10 Port 1 direction register (DDR1) Address : 000012H D27 D26 D25 D24 D23 D22 D21 D20 Port 2 direction register (DDR2) Address : 000013H D37 D36 D35 D34 D33 D32 D31 D30 Port 3 direction register (DDR3) Address : 000014H D47 D46 D45 D44 D43 D42 D41 D40 Port 4 direction register (DDR4) Address : 000015H D57 D56 D55 D54 D53 D52 D51 D50 Port 5 direction register (DDR5) Address : 000016H D67 D66 D65 D64 D63 D62 D61 D60 Port 6 direction register (DDR6) Address : 000017H D77 D76 D75 D74 D73 D72 D71 D70 Port 7 direction register (DDR7) Address : 000018H D86 D85 D84 D83 D82 D81 D80 Port 8 direction register (DDR8) D95 D94 D93 D92 D91 D90 Port 9 direction register (DDR9) 5 4 3 2 1 0 bit D87 Address : 000019H bit 7 6 Address : 00001BH ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 Port 6 analog input enable register (ADER) 109 CHAPTER 8 I/O PORTS 8.2.1 Port Data Registers Note that I/O port read/write operation is a little different from memory read/write operation. Input mode Read: The level at the corresponding pin is read. Write: A value is written to the output latch. Output mode Read: The value of the data register latch is read. Write: A value is written to the output latch and output to the corresponding pin. ■ Port Data Registers Figure 8.2-2 shows the port data registers. Figure 8.2-2 Port Data Registers bit 7 PDR0 P07 Address: 000000H 5 4 3 2 1 0 Initial value Access P05 P04 P03 P02 P01 P00 Undefined R/W Undefined R/W Undefined R/W Undefined R/W 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 7 bit PDR2 P27 Address: 000002H 6 5 4 3 2 1 0 P26 P25 P24 P23 P22 P21 P20 7 bit PDR3 P37 Address: 000003H 6 5 4 3 2 1 0 P36 P35 P34 P33 P32 P31 P30 7 bit PDR4 P47 Address: 000004H 6 5 4 3 2 1 0 P46 P45 P44 P43 P42 P41 P40 Undefined R/W bit 7 PDR5 P57 Address: 000005H 6 P56 5 P55 4 P54 3 P53 2 P52 1 P51 0 P50 Undefined R/W 7 bit PDR6 P67 Address: 000006H 6 5 4 3 2 1 0 P66 P65 P64 P63 P62 P61 P60 Undefined R/W Undefined R/W Undefined R/W Undefined R/W bit PDR1 Address: 000001H 7 6 5 4 3 2 1 0 P77 P76 P75 P74 P73 P72 P71 P70 bit 7 PDR8 P87 Address: 000008H 6 5 4 3 2 1 0 P86 P85 P84 P83 P82 P81 P80 bit PDR7 Address: 000007H bit PDR9 Address: 000009H R/W : Readable/Writable 110 6 P06 7 6 5 4 3 2 1 0 P95 P94 P93 P92 P91 P90 CHAPTER 8 I/O PORTS 8.2.2 Port Direction Register When each pin functions as a port, the port direction register controls the corresponding pin as follows: 0: Input mode 1: Output mode ■ Port Direction Register Figure 8.2-3 shows the port direction registers. Figure 8.2-3 Port Direction Register bit DDR0 Address: 000010H 7 6 5 4 D07 D06 D05 D04 6 5 4 bit 7 DDR1 D17 Address: 000011H bit 7 DDR2 D27 Address: 000012H 7 bit DDR3 D37 Address: 000013H D16 6 D26 D15 5 D25 D14 4 D24 3 D03 3 D13 3 D23 2 D02 2 D12 2 D22 D01 1 D11 0 D00 D10 1 0 D21 D20 6 5 4 3 D35 D34 D33 6 5 4 3 D46 D45 D44 6 5 4 3 D56 D55 D54 D53 7 6 5 4 3 D67 D66 D64 D63 7 bit DDR7 D77 Address: 000017H 6 5 4 3 2 1 0 D76 D75 D74 D73 D72 D71 D70 7 bit DDR8 D87 Address: 000018H D86 bit 7 DDR5 D57 Address: 000015H bit DDR6 Address: 000016H bit DDR9 Address: 000019H 7 6 6 D65 D43 3 D32 2 D42 1 0 D31 D30 1 0 D41 D40 2 1 0 D52 D51 D50 2 1 0 D61 D60 D62 Initial value Access 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 0 D36 bit 7 DDR4 Address: 000014H D47 2 1 5 4 2 1 0 D85 D84 D83 D82 D81 D80 00000000B R/W 5 D95 4 D94 3 D93 2 D92 1 D91 0 D90 __000000B R/W R/W : Readable/Writable Note: • If a pin is set to output mode by its peripheral resource, the corresponding bit in the DDR is always read as "1". • The Port Direction Registers for Ports 0 and 1 will stay undefined during Power-On reset and will be initialized to 00H after the completion of Power-On reset. For this reason, the Port 0 and 1 outputs become undefined during Power-On reset. 111 CHAPTER 8 I/O PORTS 8.2.3 Analog Input Enable Register The analog input enable register controls the pins of port 6 as follows: 0: Port input/output mode 1: Analog input mode When an external pin is used as an analog input for the A/D converter, the corresponding bit must be set to "1". ■ Analog Input Enable Register Figure 8.2-4 shows the analog input enable register. Figure 8.2-4 Analog Input Enable Register bit Address: 00001BH 7 6 5 4 3 2 1 0 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable/Writable 112 Initial value 11111111B CHAPTER 9 TIME-BASE TIMER CHAPTER 9 TIME-BASE TIMER This chapter explains the time-base timer functions and operation. 9.1 "Outline of Time-base Timer" 9.2 "Time-base Timer Control Register" 9.3 "Time-base Timer Operation" 113 CHAPTER 9 TIME-BASE TIMER 9.1 Outline of Time-base Timer The time-base timer consists of an 18-bit time-base counter and a control register. The 18-bit time-base counter divides the system clock. The time-base timer issues interrupts at specified intervals based on carry signals of the time-base counter. ■ Outline of Time-base Timer When the power is turned on, the time-base counter can be cleared to all zeroes by setting the stop mode or by software (writing "0" to the TBR bit). The time-base counter is incremented while the source oscillation is input. The time-base counter can be used as a timer for supplying clock to the watch-dog timer or for waiting for the oscillation to stabilize. ■ Block Diagram of Time-base Timer Figure 9.1-1 shows the block diagram of time-base timer. Figure 9.1-1 Time-base Timer Block Diagram WTE Output enable WT1 WT0 2-bit counter Selector Reset control Reset Time-base counter f/2 Power-on reset STOP mode 1 1 2 211 1 1 1 14 15 16 17 2 2 Selector 2 2 2 2 1 218 IRQ TBOF Clear EI 2OS 1/210 to 1/217 Time-base devision output WS1 114 1 13 TBOF TBC1 WS0 1 12 Clear control TBR TBC0 1 Selector Osciliation stabilization wait completion signal CHAPTER 9 TIME-BASE TIMER 9.2 Time-base Timer Control Register The time-base timer control register is used to control time-base timer interrupts or clear the time-base counter. ■ Time-base Timer Control Register (TBTC) 15 bit TBTC Address: 0000A9H Reserved 14 W R/W : Readable/Writable W : Write only - 13 - 12 11 10 9 8 TBIE TBOF TBR TBC1 TBC0 R/W R/W W R/W R/W Initial value 1--00100B [bit15] Reserved This is a reserved bit. When writing data to this register, ensure that "1" is written to this bit. [bit12] TBIE This bit is used to enable interval interrupts based on the time-base timer. Writing "1" to this bit enables interrupts, and writing "0" disables interrupts. This bit is initialized to "0" upon a reset. This bit is readable and writable. [bit11] TBOF This is an interrupt request flag for the time-base timer. While the TBIE bit is "1", an interrupt request is issued when "1" is written to TBOF. This bit is set to "1" for each interval specified with the TBC1 and TBC0 bits. This bit is cleared by writing "0", transition to stop or hardware standby mode, or a reset. Writing "1" has no effect. "1" is always read by a read-modify-write instruction. [bit10] TBR This bit clears all bits of the time-base timer counter to "0". Writing "0" clears the time-base counter. Writing "1" has no effect. "1" is always read from this bit. [bit9, bit8] TBC1, TBC0 These bits are used to set the time-base timer interval. Table 9.2-1 lists the specifiable intervals. Table 9.2-1 Selecting the Time-base Timer Interval TBC1 TBC0 Interval at 4 MHz source oscillation 0 0 1.024 ms 0 1 4.096 ms 1 0 16.384 ms 1 1 131.072 ms 115 CHAPTER 9 TIME-BASE TIMER 9.3 Time-base Timer Operation The time-base timer functions as a watch-dog timer clock source, timer for waiting for the oscillation to stabilize, and interval timer for generating interrupts at specified intervals. ■ Time-base Counter The time-base counter consists of an 18-bit counter for a clock generated by dividing the source oscillation input by two. This clock is used to generate the machine clock. While the source oscillation is input, the time-base counter keeps counting. The time-base counter is cleared by a power-on reset, transition to stop or hardware standby mode, or writing "0" to the TBR bit of the TBTC register. ■ Interval Interrupt Function Interrupts are generated at specified intervals according to the carry signals of the time-base counter. The TBOF flag is set at the intervals specified with the TBC1 and TBC0 bits of the TBTC register. The flag is written to reference to the time at which the time-base timer is cleared last. Upon transition to stop or hardware standby mode, the time-base timer is used as a timer for waiting for the oscillation to stabilize upon recovery. Therefore, the TBOF flag is immediately cleared upon mode transition. 116 CHAPTER 10 WATCH-DOG TIMER CHAPTER 10 WATCH-DOG TIMER This chapter explains the watchdog timer functions and operation. 10.1 "Outline of Watch-Dog Timer" 10.2 "Watch-Dog Timer Operation" 117 CHAPTER 10 WATCH-DOG TIMER 10.1 Outline of Watch-Dog Timer The watch-dog timer consists of a two-bit watch-dog counter, control register, and watch-dog reset controller. The two-bit watch-dog counter uses the carry signals of an 18-bit time-base counter as a clock source. ■ Watch-dog Timer Block Diagram Figure 10.1-1 shows the watchdog timer block diagram. Figure 10.1-1 Watch-dog Timer Block Diagram WTE Output enable WT1 WT0 2-bit counter Selector Reset control Reset Time-base counter φ/2 Power-on reset STOP mode 1 1 1 1 1 1 1 1 2 11 12 13 14 15 16 17 2 2 2 Clear control 2 2 2 1 218 2 IRQ TBOF Selector TBR TBOF Clear TBC1 EI 2OS 1/210 to 1/217 Time-base devision output TBC0 WS1 Osciliation stabilization wait completion signal Selector WS0 φ : Machine cycle ■ Watch-dog Timer Control Register (WDTC) bit 7 6 5 4 3 WDTC PONR STBR WRST ERST SRST Address : 0000A8H R R R R R W : Write only R : Read only 118 2 1 0 WTE WT1 WT0 W W W Initial value XXXXX111B CHAPTER 10 WATCH-DOG TIMER [bit7 to bit3] PONR, STBR, WRST, ERST, and SRST These flags indicate the reset causes. The flags are set upon a reset as described in Table 10.1-1 . All bits are cleared to "0" after the WDTC register is read. These bits are read-only bits. For details, see Section 5.2 "Reset Cause Occurrence". Table 10.1-1 Reset Cause Registers Reset cause PONR STBR WRST ERST SRST Power-on 1 — — — — Hardware standby * 1 * * * Watch-dog timer * * 1 * * External pin * * * 1 * RST bit * * * * 1 *: The previous value is maintained. [bit2] WTE While the watch-dog timer is stopped, writing "0" to this bit activates the watch-dog timer. Subsequently, writing "0" clears the watch-dog timer counter. Writing "1" has no effect. The watch-dog timer is stopped by power-on, hardware standby, or reset by watch-dog timer. "1" is always read from this bit. [bit1, bit0] WT1, WT0 These bits are used to select the watch-dog timer interval. Only the data items written during watch-dog timer activation are valid. Data items that are written outside watch-dog timer activation are ignored. Table 10.1-2 lists the interval settings. These bits are write-only bits. Table 10.1-2 Watch-dog Timer Interval Selection Bit WT1 WT0 Interval (at a source oscillation of 4 MHz) Minimum Maximum * Main clock cycle count 0 0 About 3.58 ms About 4.61 ms 214 ± 211 cycles 0 1 About 14.33 ms About 18.43 ms 216 ± 213 cycles 1 0 About 57.23 ms About 73.73 ms 218 ± 215 cycles 1 1 About 458.7 ms About 589.82 ms 221 ± 218 cycles *: The interval becomes the maximum when the time-base counter is not reset during watchdog timer operation. 119 CHAPTER 10 WATCH-DOG TIMER 10.2 Watch-Dog Timer Operation The watch-dog timer function enables detection of program surge. If the watch-dog timer is not accessed within the specified time due to, for example, a program surge, the watch-dog timer resets the system. ■ Activating the Watch-dog Timer The watch-dog timer is activated by writing "0" to the WTE bit of the WTC register while the watch-dog timer is stopped. At the same time, the WT1 and WT0 bits are used to set the watchdog timer reset interval. Only the interval setting specified during activation is valid. ■ Watch-dog Counter Once the watch-dog timer is activated, the watch-dog timer counter must be periodically cleared within the program. Writing "0" to the WTE bit of the WTC register clears the watch-dog counter. The watch-dog counter consists of a two-bit counter which uses the carry signals of the timebase counter as a clock source. Therefore, the watch-dog reset time may become shorter than the setting if the time-base counter is cleared. The watch-dog counter is cleared not only by writing "0" to the WTE bit but also by a Reset signal, transition to the sleep or stop mode. (The counter is not cleared by transition to the timer mode.) Figure 10.2-1 is a diagram of the watch-dog timer operation. Figure 10.2-1 Watch-dog Timer Operation Time-base Watch-dog 00 01 10 00 01 10 11 00 WTE write Watch-dog activation Watch-dog clear Watch-dog reset ■ Watch-dog Stop Once activated, the watch-dog timer is initialized and stopped only by power-on, hardware standby, or reset by watch-dog. Reset by an external pin or software merely clears the watchdog counter without stopping the watch-dog function. 120 CHAPTER 11 16-BIT I/O TIMER CHAPTER 11 16-BIT I/O TIMER This chapter explains the 16-bit I/O timer functions and operation. 11.1 "Outline of 16-Bit I/O Timer" 11.2 "16-Bit I/O Timer Registers" 11.3 "16-bit Free-run Timer" 11.4 "Output Compare" 11.5 "Input Capture" 121 CHAPTER 11 16-BIT I/O TIMER 11.1 Outline of 16-Bit I/O Timer The MB90595 Series contains one 16-bit free-run timer module, two output compare modules, and two input capture modules and supports four input channels and four output channels. The following sections only describes the 16-bit free-run timer, Output Compare 0/1 and Input Capture 0/1. The remaining modules have the identical functions and the register addresses should be found in the I/O map. ■ 16-bit Free-run Timer The 16-bit free-run timer consists of a 16-bit up counter, control register, and prescaler. The values output from this timer counter are used as the base timer for input capture and output compare. ❍ Four Counter Clocks are Available. Internal clock: φ/4, φ/16, φ/64, φ/256 ❍ An interrupt can be generated upon a counter overflow or a match with compare register 0. ❍ The counter value can be initialized to "0000H" upon a reset, software clear, or match with compare register 0. ■ Output Compare (2 Channels Per One Module) The output compare module consists of two 16-bit compare registers, compare output latch, and control register. When the 16-bit free-run timer value matches the compare register value, the output level is reversed and an interrupt is issued. ❍ The two compare registers can be used independently. Output pins and interrupt flags corresponding to compare registers ❍ Output pins can be controlled based on pairs of the two compare registers. Output pins can be reversed by using the two compare registers. ❍ Initial values for output pins can be set. ❍ Interrupts can be generated upon a compare match. 122 CHAPTER 11 16-BIT I/O TIMER ■ Input Capture (2 Channels Per One Module) The input capture module consists of two 16-bit capture registers and control registers corresponding to two independent external input pins. The 16-bit free-run timer value can be stored in the capture register and an interrupt is issued simultaneously upon detection of an edge of a signal input from an external input pin. ❍ The detection edge of an external input signal can be specified. Rising, falling, or both edges ❍ Two input channels can operate independently. ❍ An interrupt can be issued upon a valid edge of an external input signal. The intelligent I/O service can be activated upon an input capture interrupt. ■ 16-bit I/O Timer Block Diagram Figure 11.1-1 shows a 16-bit I/O timer block diagram. Figure 11.1-1 16-bit I/O Timer Block Diagram Control logic To each block Interrupt 16-bit free-run timer 16-bit timer Bus Clear Output compare 0 Compare register 0 T Q OUT0 T Q OUT1 Output compare 1 Compare register 1 Input capture 0 Capture register 0 Input capture 1 Capture register 1 Edge selection IN0 Edge selection IN1 123 CHAPTER 11 16-BIT I/O TIMER 11.2 16-Bit I/O Timer Registers The 16-bit I/O timer uses the following three types of registers: • 16-bit free-run timer register • 16-bit output compare register • 16-bit input capture register ■ 16-bit Free-run Timer bit 15 0 000066H Timer data register TCDT 000068H Timer status register TCCS ■ 16-bit Output Compare bit 15 0 001928H 00192AH Compare register OCCP0/1 000058H OCS1 OCS0 Control status register ■ 16-bit Input Capture bit 15 001920H 001922H 00005CH 124 0 Capture register IPCP0/1 ICS01 Control status register CHAPTER 11 16-BIT I/O TIMER 11.3 16-bit Free-run Timer The 16-bit free-run timer consists of a 16-bit up counter and a control status register. The count values of this timer are used as the base timer for the output compares and input captures. • Four counter clock frequencies are available. • An interrupt can be generated upon a counter value overflow. • The counter value can be initialized upon a match with compare register 0, depending on the mode. ■ 16-bit Free-run Timer Block Diagram Figure 11.3-1 shows a 16-bit free-run timer block diagram. Figure 11.3-1 16-bit Free-run Timer Block Diagram Interrupt request Bus IVF IVFE STOP MODE CLR CLK1 CLK0 φ Divider Comparator 0 16-bit up counter Clock Count value output T15 to T00 125 CHAPTER 11 16-BIT I/O TIMER 11.3.1 Data Register The data register can read the counter value of the 16-bit free-run timer. The counter value is cleared to "0000" upon a reset. The timer value can be set by writing a value to this register. However, the timer operation must be stopped (STOP = 1) prior to writing the value. The data register must be accessed by word access instructions. ■ Data Register bit 15 Address: 000067H 14 13 12 11 10 9 8 T15 T14 T13 T12 T11 T10 T09 T08 R/W 0 R/W 0 bit Address: 000066H R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W ←Attribute 0 ←Initial value 7 6 5 4 3 2 1 0 T07 T06 T05 T04 T03 T02 T01 T00 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W : Readable/Writable R/W 0 TCDT R/W ←Attribute 0 ←Initial value The 16-bit free-run timer is initialized upon the following factors: 126 • - Reset • Clear bit (CLR) of control status register • A match between compare register 0 and the timer counter value. (Setting the mode is required.) CHAPTER 11 16-BIT I/O TIMER 11.3.2 Control Status Register The control status register sets the 16-bit free-run timer operation mode or controls timer activation/termination and interrupts. ■ Control Status Register 7 6 5 Address: 000068H Reserved IVF IVFE R/W 0 R/W : Readable/Writable R/W 0 R/W 0 bit 4 3 STOP MODE R/W 0 R/W 0 2 1 0 CLR CLK1 CLK0 R/W 0 R/W 0 R/W 0 TCCS ←Attribute ←Initial value [bit7] Reserved bit Always write "0" to this bit. [bit6] IVF This bit is an interrupt request flag of the 16-bit free-run timer. If the 16-bit free-run timer overflows, or if the counter is cleared by a match with compare register 0, "1" is set to this bit. An interrupt is issued if the interrupt request enable bit (bit 5: IVFE) is set. This bit is cleared by writing "0". Writing "1" has no effect. "1" is always read by a read-modify-write instruction. 0 No interrupt request (Initial value) 1 Interrupt request [bit5] IVFE IVFE is an interrupt enable bit of the 16-bit free-run timer. While this bit is "1", an interrupt is issued if "1" is set to the interrupt flag (bit 6: IVF). 0 Interrupt disabled (Initial value) 1 Interrupt enabled [bit4] STOP The STOP bit is used to stop the 16-bit free-run timer. Writing "1" to this bit stops the timer. Writing "0" starts the timer. 0 Counter enabled (operation) (Initial value) 1 Counter disabled (stop) 127 CHAPTER 11 16-BIT I/O TIMER Note: The output compare operation stops when the 16-bit free-run timer stops. [bit3] MODE The MODE bit is used to set the reset condition of the 16-bit free-run timer. When "0" is set, the counter value can be initialized by RESET or a clear bit (bit 2: CLR). When "1" is set, the counter value can be initialized by a match with compare register 0 in addition to RESET and a clear bit (bit 2: CLR). 0 Initialization by reset or clear bit (Initial value) 1 Initialization by reset, clear bit, or compare register 0 Note: The clear bit and the match with compare register initializes the timer when the timer value changes. [bit2] CLR The CLR bit initializes the operating 16-bit free-run timer value to "0000". When "1" is set, the counter value is initialized to "0000". Writing "0" has no effect. "0" is always read from this bit. The counter value is initialized when the count value changes. 0 No effect (Initial value) 1 The counter value is initialized to "0000". Note: To initialize the counter value while the timer is stopped, write "0000" to the data register. [bit1, bit0] CLK1, CLK0 CLK1 and CLK0 are used to select the count clock for the 16-bit free-run timer. The clock is updated immediately after a value is written to these bits. Therefore, ensure that the output compare and input capture operations are stopped before a value is written to these bits. CLK1 CLK0 Count clock φ =16 MHz φ =8 MHz φ =4 MHz φ =2 MHz 0 0 φ/4 0.25 µs 0.5 µs 1 µs 2 µs 0 1 φ / 16 1 µs 2 µs 4 µs 8 µs 1 0 φ / 64 4 µs 8 µs 16 µs 32 µs 1 1 φ / 256 16 µs 32 µs 64 µs 128 µs φ = Machine clock 128 CHAPTER 11 16-BIT I/O TIMER 11.3.3 Operation of 16-bit Free-run Timer The 16-bit free-run timer starts counting from counter value "0000" after the reset is released. The counter value is used as the reference time for the 16-bit output compare and 16-bit input capture operations. ■ Operation of 16-bit Free-run Timer The counter value is cleared in the following conditions: • When an overflow occurs. • When a match with the output compare register 0 occurs. (This depends on the mode.) • When "1" is written to the CLR bit of the TCCS register during operation. • When "0000" is written to the TCDT register during stop. • Reset An interrupt can be generated when an overflow occurs or when the counter is cleared by a match with the compare register 0. (Compare match interrupts can be used only in an appropriate mode.) ■ Clearing the Counter by an Overflow Counter value FFFFH Overflow BFFFH 7FFFH 3FFFH 0000H Time Reset Interrupt 129 CHAPTER 11 16-BIT I/O TIMER ■ Clearing the Counter Upon a Match with Output Compare Register 0 Counter value FFFFH Match BFFFH Match 7FFFH 3FFFH Time 0000H Reset Compare register value Interrupt BFFFH ■ 16-bit Free-run Timer Timing ❍ 16-bit free-run timer timing The counter can be cleared upon a reset, software clear, or a match with the compare register 0. By a reset or software clear, the counter is immediately cleared. By a match with compare register 0, the counter is cleared in synchronization with the count timing. φ Compare register value N Compare match Counter value 130 N 0000H CHAPTER 11 16-BIT I/O TIMER 11.4 Output Compare The output compare module consists of two 16-bit compare registers, two compare output pins, and control register. If the value written to the compare register of this module matches the 16-bit free-run timer value, the output level of the pin can be reversed and an interrupt can be issued. ■ Output Compare • Two compare registers exist that can be used independently. Depending on the setting, the two compare registers can be used to control pin outputs. • The initial value for the pin output can be specified. • An interrupt can be issued upon a match as a result of comparison. ■ Output Compare Block Diagram Figure 11.4-1 shows an output compare block diagram. Figure 11.4-1 Output Compare Block Diagram 16-bit timer counter value (T15 to T00) T Compare control Q OTE0 OUT0 OTE1 OUT1 Compare register 0 Bus 16-bit timer counter value (T15 to T00) CMOD T Compare control Q Compare register 1 ICP1 ICP0 ICE1 ICE0 Controller Control blocks Compare 1 interrupt Compare 0 interrupt 131 CHAPTER 11 16-BIT I/O TIMER 11.4.1 Output Compare Register Details These 16-bit compare registers are compared with the 16-bit free-run timer. Since the initial register values are undefined, set appropriate value before enabling the operation. These registers must be accessed by the word access instructions. When the value of the register matches that of the 16-bit free-run timer, a compare signal is generated and the output compare interrupt flag is set. If output is enabled, the output level corresponding to the compare register is reversed. ■ Output Compare Register Details bit 001929H 00192BH 15 14 13 12 11 10 9 C15 C14 C13 C12 C11 C10 C09 C08 R/W X R/W X R/W X R/W X R/W ←Attribute X ←Initial value bit 001928H 00192AH R/W : Readable/Writable : Undefined X 132 R/W X R/W X R/W X 8 7 6 5 4 3 2 1 0 C07 C06 C05 C04 C03 C02 C01 C00 OCCP0/1 R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X ←Attribute ←Initial value CHAPTER 11 16-BIT I/O TIMER 11.4.2 Control Status Register of Output Compare The control status register sets the output compare operation mode, controls output compare activation/termination and interrupts, or sets external output pins. ■ Control Status Register of Output Compare bit 15 14 13 12 11 10 CMOD OTE1 OTE0 000059H bit 000058H R/W 0 6 7 ICP1 R/W 0 R/W : Readable/Writable : Undefined R/W 0 5 R/W 0 4 ICP0 ICE1 ICE0 R/W 0 R/W 0 R/W 0 9 8 OTD1 OTD0 R/W 0 3 OCS1 R/W ←Attribute 0 ←Initial value 2 1 0 CST1 CST0 R/W 0 R/W 0 OCS0 ←Attribute ←Initial value [bit15 to bit13] Unused bits [bit12] CMOD CMOD is used to switch the pin output level reverse mode upon a match while pin output is enabled (OTE1=1 or OTE0=1). • • When CMOD=0 (default), the output level of the pin corresponding to the compare register is reversed. • OUT0: The level is reversed upon a match with compare register 0. • OUT1: The level is reversed upon a match with compare register 1. When CMOD=1, the output level is reversed for the compare register 0 in the same manner as for CMOD=0. The output level of the pin corresponding to compare register 1 (OUT1), however, is reversed upon a match with compare register 0 or 1. If compare registers 0 and 1 have the same value, the same operation as with a single compare register is performed. • OUT0: The level is reversed upon a match with compare register 0. • OUT1: The level is reversed upon a match with compare register 0 or 1. [bit11, bit10] OTE1, OTE0 These bits are used to enable the output compare output pins. The initial value for these bits is "0". 0 General-purpose port (Initial value) 1 Output compare pin output Note: OTE1: Corresponds to output compare 1 (OUT1) OTE0: Corresponds to output compare 0 (OUT0). 133 CHAPTER 11 16-BIT I/O TIMER [bit9, bit8] OTD1, OTD0 These bits are used to change the pin output level when the output compare pin output is enabled. The initial value of the compare pin output is "0". Ensure that the compare operation is stopped before a value is written. When read, these bits indicate the output compare pin output value. 0 Sets "0" for the compare pin output. (Initial value) 1 Sets "1" for the compare pin output. Note: OTD1: Corresponds to output compare 1 OTD0: Corresponds to output compare 0 [bit7, bit6] ICP1, ICP0 These bits are used as output compare interrupt flags. "1" is set to these bits when the compare register value matches the 16-bit free-run timer value. While the interrupt request bits (ICE1 and ICE0) are enabled, an output compare interrupt occurs when the ICP1 and ICP0 bits are set. These bits are cleared by writing "0". Writing "1" has no effect. "1" is always read by a read-modify-write instruction. 0 No compare match (Initial value) 1 Compare match Note: ICP1: Corresponds to output compare 1 ICP0: Corresponds to output compare 0 [bit5, bit4] ICE1, ICE0 These bits are used as output compare interrupt enable flags. While the "1" is written to these bits, an output compare interrupt occurs when an interrupt flag (ICP1 or ICP0) is set. 0 Output compare interrupt disabled (Initial value) 1 Output compare interrupt enabled Note: CE1: Corresponds to output compare 1 ICE0: Corresponds to output compare 0 [bit3, bit2] Unused bits [bit1, bit0] CST1, CST0 These bits are used to enable the comparison with 16-bit free-run timer. 0 Compare operation disabled (Initial value) 1 Compare operation enabled Ensure that a value is written to the compare register before the compare operation is enabled. 134 CHAPTER 11 16-BIT I/O TIMER Note: CST1: Corresponds to output compare 1. CST0: Corresponds to output compare 0. Since output compare is synchronized with the 16-bit free-run timer clock, stopping the 16-bit free-run timer stops compare operation. 135 CHAPTER 11 16-BIT I/O TIMER 11.4.3 16-bit Output Compare Operation In the 16-bit output compare operation, an interrupt request flag can be set and the output level can be reversed when the specified compare register value matches the 16-bit free-run timer value. ■ Sample of Output Waveform When Compare Registers 0 and 1 are Used (The Initial Output Value is 0.) Figure 11.4-2 Sample Waveform Output When Compare Registers 0 and 1 are Used Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset Compare register 0 value Compare register 1 value OUT0 BFFF H 7FFF H OUT1 Compare 0 interrupt Compare 1 interrupt The output level can be changed using two compare registers (when CMOD=1). ■ Sample of a Output Waveform with Two Compare Registers (The Initial Output Value is "0".) Figure 11.4-3 Sample Waveform Output When Two Compare Registers are Used (The Initial Output Value is "0".) Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset Compare register 0 value Compare register 1 value OUT0 OUT1 Compare 0 interrupt Compare 1 interrupt 136 BFFFH 7FFFH Corresponds to compare 0 and 1 CHAPTER 11 16-BIT I/O TIMER ■ Output Compare Timing In output compare operation, a compare match signal is generated when the free-run timer value matches the specified compare register value. The output value can be reversed and an interrupt can be issued. The output reverse timing upon a compare match is synchronized with the counter count timing. ❍ Compare operation upon update of compare register When the compare register is updated, comparison with the counter value is not performed. N Counter value N+1 N+2 N+3 No match signal is generated. Compare register 0 value Compare register 0 write M Compare register 1 value Compare register 1 write M N+1 N+3 Compare 0 stop Compare 1 stop ❍ Interrupt timing of Output Compare φ N Counter value N+1 Compare register value N Compare match Interrupt ❍ Output pin change timing of Output Compare Counter value Compare register value N N+1 N N+1 N Compare match signal Pin output 137 CHAPTER 11 16-BIT I/O TIMER 11.5 Input Capture This module detects a rising or falling edge or both edges of an external input signal and stores the 16-bit free-run timer value in a register. In addition, this module can generate an interrupt upon detection of an edge. The input capture module consists of input capture data registers and control register. ■ Input Capture Each input capture has a corresponding external input pin. ❍ The detection edge of an external input can be selected from three types. Rising edge Falling edge Both edges ❍ An interrupt can be generated upon detection of a valid edge of an external input. 138 CHAPTER 11 16-BIT I/O TIMER ■ Input Capture Block Diagram Figure 11.5-1 shows a block diagram of input capture. Figure 11.5-1 Input Capture Block Diagram Bus 16-bit timer counter value (T15 to T00) Capture data register 1 IN0 Edge detection Capture data register 0 EG11 EG10 EG01 EG00 Edge detection IN1 ICP1 ICP0 ICE1 ICE0 Interrupt Interrupt 139 CHAPTER 11 16-BIT I/O TIMER 11.5.1 Input Capture Register Details This register stores the 16-bit timer value when a valid edge of the corresponding external pin input waveform is detected. (This register must be accessed in word mode. No value can be written to this register.) • Input capture data register • Input capture control register ■ Input Capture Data Register bit 15 001921H 001923H 14 CP15 CP14 bit 001920H 001922H 12 CP13 CP12 R X R X R X 13 R X 7 6 : Read only : Undefined R X 5 R X 10 9 8 CP12 CP11 CP09 R X CP07 CP06 R X 11 R X CP08 R X 4 R X 3 2 CP05 CP04 CP03 CP02 R X R X ←Attribute ←Initial value R X 1 0 CP01 CP00 R X R X R X IPCP0/IPCP1 ←Attribute ←Initial value ■ Input Capture Control Status Register 7 6 5 4 3 2 1 0 ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 R/W R/W 0 0 R/W : Readable/Writable R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 bit 00005CH ICS01 ←Attribute ←Initial value [bit7, bit6] ICP1, ICP0 These bits are used as input capture interrupt flags. "1" is set to this bit upon detection of a valid edge of an external input pin. While the interrupt enable bits (ICE0 and ICE1) are set, an interrupt can be generated upon detection of a valid edge. These bits are cleared by writing "0". Writing "1" has no effect. "1" is always read by a readmodify-write instruction. 0 No valid edge detection (default) 1 Valid edge detection Note: ICP0: Corresponds to input capture 0 ICP1: Corresponds to input capture 1 140 CHAPTER 11 16-BIT I/O TIMER [bit5, bit4] ICE1, ICE0 These bits are used to enable input capture interrupts. While these bits are "1", an input capture interrupt is generated when the interrupt flag (ICP0 or ICP1) is set. 0 Interrupt disabled (default) 1 Interrupt enabled Note: ICE0: Corresponds to input capture 0 ICE1: Corresponds to input capture 1 [bit3 to bit0] EG11, EG10, EG01, and EG00 These bits are used to specify the valid edge polarity of the external inputs. These bits are also used to enable input capture operation. EG11 EG01 EG10 EG00 0 0 No edge detection (stop) (default) 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both edge detection Edge detection polarity Note: EG01 and EG00: Correspond to input capture 0 EG11 and EG10: Correspond to input capture 1 141 CHAPTER 11 16-BIT I/O TIMER 11.5.2 16-bit Input Capture Operation In 16-bit input capture operation, an interrupt can be generated upon detection of at the specified edge, fetching the 16-bit free-run timer value and writing it to the capture register. ■ Sample of Input Capture Fetch Timing • Capture 0: Rising edge • Capture 1: Falling edge • Capture example: Both edges Figure 11.5-2 Sample of Input Capture Fetch Timing Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset IN0 IN1 IN example Capture 0 Capture 1 Capture example Capture 0 interrupt Capture 1 interrupt Capture interrupt 142 Undefined 3FFFH Undefined Undefined 7FFFH BFFFH 3FFFH CHAPTER 11 16-BIT I/O TIMER ■ Input Capture Input Timing ❍ Capture timing for input signals φ Counter value Input capture input N N+1 Valid edge Capture signal Capture register N+1 Interrupt 143 CHAPTER 11 16-BIT I/O TIMER 144 CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) This chapter explains the functions and operation of the 16-bit reload timer (with the event count function). 12.1 "Outline of 16-bit Reload Timer (with Event Count Function)" 12.2 "Registers of 16-bit Reload Timer" 12.3 "Internal Clock Operation and External Clock Operation of 16-bit Reload Timer" 12.4 "Underflow Operation of 16-bit Reload Timer" 12.5 "Output Pin Functions of 16-bit Reload Timer" 12.6 "Counter Operation State" 145 CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 12.1 Outline of 16-bit Reload Timer (with Event Count Function) The 16-bit reload timer consists of a 16-bit down-counter, a 16-bit reload register, one input pin (TIN) and one output pin (TOT), and a control register. The input clock can be selected from one external clock and three types of internal clock. ■ Outline of 16-bit Reload Timer (With Event Count Function) The output pin (TOT) outputs a toggle output waveform in reload mode or a square waveform during counting in one-shot mode. The input pin (TIN) functions as the event input in event count mode, or as the trigger input or gate input in internal clock mode. The MB90595 Series has two 16-bit reload timers. ■ Intelligent I/O Service (EI2OS) Function and Interrupts The timer includes a circuit that supports EI2OS. The timer can activate EI2OS when an underflow occurs. EI2OS can be used with both timers on this product. ■ Block Diagram of 16-bit Reload Timer Figure 12.1-1 shows Block Diagram of 16-bit Reload Timer. Figure 12.1-1 Block Diagram of 16-bit Reload Timer 16 16-bit reload register 8 Reload RELD 16-bit down-counter 16 OUTE UF F2 M C - 16 B U S OUTL 2 INTE OUT CTL. GATE UF IRQ CSL1 Clock selector CNTE Clear TRG EI2OS CLR CSL0 Re-trigger 2 IN CTL Port (TIN) EXCK Output enable 3 21 23 25 Prescaler clear Port (TOT) MOD2 MOD1 Peripheral clock 3 146 MOD0 UART baud rate (ch.0) A/DC (ch.1) CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 12.2 Registers of 16-bit Reload Timer The 16-bit reload timer uses the following two types of registers: • Time control status register (TMCSR) • 16-bit timer register/16-bit reload register (TMR/TMRLR) ■ Registers of 16-bit Reload Timer Timer control status register (upper) Address:ch.0 000051H ch.1 000055 H Read/write Initial value 15 Read/write Initial value — — — — — — — — — — 11 10 9 CSL0 MOD2 MOD1 (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) CSL1 7 6 5 4 MOD0 OUTE OUTL RELD INTE (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) 15 (R/W) (X) 3 1 UF CNTE TRG (R/W) (0) (R/W) (0) (R/W) (0) 13 12 11 10 (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) 7 6 5 4 3 Bit number 8 2 14 16-bit timer register (lower)/ 16-bit reload register (lower) Address:ch.0 000052 H ch.1 ch1 000056 00003EHH Read/write Initial value 12 — 16-bit timer register (upper)/ 16-bit reload register (upper) Address: ch.0 000053 H ch.1 000057 H Read/write Initial value 13 — Timer control status register (lower) Address: ch.0 000050 H ch.1 000054 H 14 9 0 Bit number TMCSR Bit number 8 (R/W) (X) 2 1 0 Bit number TMR/ TMRLR (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) R/W : Readable/Writable X : Undefined : Undefined 147 CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 12.2.1 Timer Control Status Register (TMCSR) Controls the operation mode and interrupts for the 16-bit timer. Only modify bits other than UF, CNTE, and TRG when CNTE = 0. ■ Structure of Timer Control Status Register (TMCSR) Timer control status register (upper) Address:ch.0 000051H ch1 000055 00003DHH ch.1 ⎫ ⎬ ⎭ Read/write Initial value 15 ⎫ ⎬ ⎭ Read/write Initial value 13 12 — — — — — — — — — — — — Timer control status register (lower) Address:ch.0 000050 H ch1 000054 00003CHH ch.1 14 MOD0 (R/W) (0) CSL1 (R/W) (0) 7 6 5 OUTE OUTL RELD (R/W) (0) (R/W) (0) (R/W) (0) 11 10 9 CSL0 MOD2 MOD1 (R/W) (0) (R/W) (0) (R/W) (0) 4 INTE (R/W) (0) 3 2 Bit number 8 1 UF CNTE TRG (R/W) (0) (R/W) (0) (R/W) (0) 0 Bit number TMCSR R/W : Readable/Writable : Undefined ❍ Contents of Timer Control Status Register (TMCSR) [bit11, bit10] CSL1, CSL0 (Clock select 1, 0) The count clock select bits. Table 12.2-1 lists the selected clock sources. Table 12.2-1 Clock Sources for CSL Bit Settings Clock Source (Machine cycle φ = 16 MHz) CSL1 CSL0 0 0 φ/21 (0.125 µs) 0 1 φ/23 (0.5 µs) 1 0 φ/25 (2.0 µs) 1 1 External event count mode [bit9 to bit7] MOD2 to MOD0 These bits set the operation mode and I/O pin functions. The MOD2 bit selects the I/O functions. When MOD2 = 0, the input pin functions as a trigger input. In this case, the reload register contents is loaded to the counter when an active edge is input to the input pin and count operation proceeds. When MOD2 = 1, the timer operates in gate counter mode and the input pin functions as a gate input. In this mode, the counter only counts while an active level is input to the input pin. 148 CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) The MOD1 and 0 bits set the pin functions for each mode. Table 12.2-2 and Table 12.2-4 list the MOD2, 1, 0 bit settings. Table 12.2-2 MOD2 to MOD0 Bit Settings (1) MOD2 MOD1 MOD0 Input Pin Function Active Edge or Level 0 0 0 Trigger disabled – 0 0 1 Trigger input Rising edge 0 1 0 Falling edge 0 1 1 Both edges 1 × 0 1 × 1 Gate input "L" level "H" level Internal clock mode (CSL0, 1 = 00, 01, or 10) Table 12.2-3 MOD2 to MOD0 Bit Settings (2) MOD2 MOD1 MOD0 Input Pin Function Active Edge or Level 0 0 — — 0 1 Trigger input Rising edge 1 0 Falling edge 1 1 Both edges × • Event counter mode (CSL0,1 = 11) • Bits marked as × in the table can be set to any value. [bit6] OUTE Output enable bit. The TOT pin functions as a general-purpose port when this bit is "0" and as the timer output pin when this bit is "1". In reload mode, the output waveform toggles. In one-shot mode, TOT outputs a square waveform that indicates that counting is in progress. 149 CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) [bit5] OUTL This bit sets the output level for the TOT pin. Table 12.2-4 OUTE, RELD, and OUTL Settings OUTE RELD OUTL Output Waveform 0 × × General-purpose port 1 0 0 Output an "H" level square waveform during counting. 1 0 1 Output an "L" level square waveform during counting. 1 1 0 Toggle output. Starts with "L" level output. 1 1 1 Toggle output. Starts with "H" level output. [bit4] RELD (Reload) This bit enables reload operations. When RELD is "1", the timer operates in reload mode. In this mode, the timer loads the reload register contents into the counter and continues counting whenever an underflow occurs (when the counter value changes from 0000H to FFFFH). When RELD is "0", the timer operates in one-shot mode. In this mode, the count operation stops when an underflow occurs due to the counter value changing from 0000H to FFFFH. [bit3] INTE (Interrupt enable) Timer interrupt request enable bit. When INTE is "1", an interrupt request is generated when the UF bit changes to "1". When INTE is "0", no interrupt request is generated, even when the UF bit changes to "1". [bit2] UF (Underflow) Timer interrupt request flag. UF is set to "1" when an underflow occurs (when the counter value changes from 0000H to FFFFH). Cleared by writing "0" or by the intelligent I/O service. Writing "1" to this bit has no meaning. Read as "1" by read-modify-write instructions. [bit1] CNTE (Count enable) Timer count enable bit. Writing "1" to CNTE sets the timer to wait for a trigger. Writing "0" stops count operation. [bit0] TRG (Trigger) Software trigger bit. Writing "1" to TRG applies a software trigger, causing the timer to load the reload register contents to the counter and start counting. Writing "0" has no meaning. Reading always returns "0". Applying a trigger using this register is only valid when CNTE = 1. Writing "1" has no effect if CNTE = 0. 150 CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 12.2.2 Register Layout of 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR) TMR contents (for reading) Reading this register reads the count value of the 16-bit timer. The initial value is undefined. Always read this register using the word access instructions. TMRLR contents (for writing) The 16-bit reload register holds the initial count value. The initial value is undefined. Always write to this register using the word access instructions. ■ Register Layout of 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR) 16-bit timer register (upper)/ 16-bit reload register (upper) Address:ch.0 000053H ch1 000057 00003FHH ch.1 15 Read/write Initial value 16-bit timer register (lower)/ 16-bit reload register (lower) Address:ch.0 000052 H ch1 000056 00003EHH ch.1 14 13 12 (R/W) (X) (R/W) (X) (R/W) (X) 7 6 11 10 9 Bit number 8 ⎫ ⎬ ⎭ (R/W) (X) (R/W) (X) 5 (R/W) (X) 4 (R/W) (X) 3 (R/W) (X) 2 1 ⎫ ⎬ ⎭ Read/write Initial value 0 Bit number TMR/ TMRLR (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) R/W : Readable/Writable X : Undefined 151 CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 12.3 Internal Clock Operation and External Clock Operation of 16-bit Reload Timer The machine clock divided by 21, 23, or 25 can be selected as the clock sources for operating the timer from an internal divide clock. The external input pin can be selected as either a trigger input or gate input by a register setting. When an external clock is selected, the TIN pin functions as an external event input pin and counts on the active edge specified in the register. ■ Internal Clock Operation of 16-bit Reload Timer Writing "1" to both the CNTE and TRG bits in the control register enables and starts counting at one time. Using the TRG bit as a trigger input is always available when the timer is enabled (CNTE = 1), regardless of the operation mode. Figure 12.3-1 shows counter activation and counter operation. A time period T (T: machine cycle) is required from the counter start trigger being input until the reload register data is loaded into counter. Figure 12.3-1 Counter Activation and Operation of 16-bit Reload Timer Count clock Reload data Counter -1 -1 -1 Data load CNTE (bit) TRG (bit) T ■ Input Pin Functions of 16-bit Reload Timer (for Internal Clock Mode) The TIN pin can be used as either a trigger input or a gate input when an internal clock is selected as the clock source. When used as a trigger input, input of an active edge causes the timer to load the reload register contents to the counter and then start count operation after clearing the internal prescaler. Input a pulse width of at least 2T (T is the machine cycle) to TIN. Figure 12.3-2 shows the operation of trigger input. 152 CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) Figure 12.3-2 Trigger Input Operation of 16-bit Reload Timer Count clock Rising edge detected TIN Prescaler clear Counter Reload data 0000H -1 -1 -1 Load 2T to 2.5T When used as a gate input, the counter only counts while the active level specified by the MOD0 bit of the control register is input to the TIN pin. In this case, the count clock continues to operate unless stopped. The software trigger can be used in gate mode, regardless of the gate level. Input a pulse width of at least 2T (T is the machine cycle) to the TIN pin. Figure 12.3-3 shows the operation of gate input. Figure 12.3-3 Gate Input Operation of 16-bit Reload Timer Count clock When MOD0 = 1 (Count when "H" is input) TIN -1 Counter -1 -1 ■ External Event Counter The TIN pin functions as an external event input pin when an external clock is selected. The counter counts on the active edge specified in the register. Input a pulse width of at least 4T (T is the machine cycle) to the TIN pin. 153 CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 12.4 Underflow Operation of 16-bit Reload Timer An underflow is defined for this timer as the time when the counter value changes from 0000H to FFFFH. Therefore, an underflow occurs after (reload register setting + 1) counts. ■ Underflow Operation of 16-bit Reload Timer If the RELD bit in the control register is "1" when the underflow occurs, the contents of the reload register is loaded into the counter and counting continues. When RELD is "0", counting stops with the counter at FFFFH. The UF bit in the control register is set when the underflow occurs. If the INTE bit is "1" at this time, an interrupt request is generated. Figure 12.4-1 shows the operation when an underflow occurs. Figure 12.4-1 Underflow Operation of 16-bit Reload Timer Count clock Counter 0000H Reload data Data load Underflow set [RELD=1] Count clock Counter 0000H Underflow set [RELD=0] 154 FFFFH -1 -1 -1 CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 12.5 Output Pin Functions of 16-bit Reload Timer In reload mode, the TOT pin performs toggle output (inverts at each underflow). In oneshot mode, the TOT pin functions as a pulse output. ■ Output Pin Functions of 16-bit Reload Timer The OUTL bit of the control register can set the output polarity of the 16-bit reload timer. When OUTL is set to "0", the initial value for toggle output is "0" and the one-shot pulse output is "1" while the count is in progress. When OUTL is set to "1", the output waveform inverts. Figure 12.5-1 and show the output pin functions. Figure 12.5-1 Output Pin Functions of 16-bit Reload Timer (1) Count start Underflow Level is opposite when OUTL = 1. TOT General-purpose port CNTE Trigger [RELD=1, OUTL=0] Figure 12.5-2 Output Pin Functions of 16-bit Reload Timer (2) Underflow TOT Level is opposite when OUTL = 1. General-purpose port CNTE Trigger Waiting for a trigger [RELD=0, OUTL=0] 155 CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 12.6 Counter Operation State The counter state is determined by the CNTE bit in the control register and the internal WAIT signal. Available states are: CNTE = 0 and WAIT = 1 (STOP state), CNTE = 1 and WAIT = 1 (WAIT state for trigger), and CNTE = 1 and WAIT = 0 (RUN state). ■ Counter Operation State Figure 12.6-1 shows the transitions between each state. Figure 12.6-1 Counter State Transitions Reset State transitions by hardware STOP CNTE=0, WAIT=1 State transitions by register access TIN pin: Input disabled TOT pin: General-purpose port Counter: Stores the value when counting stopped. Undefined immediately after a reset. CNTE=0 CNTE=0 CNTE=1 TRG=1 CNTE=1 TRG=0 WAIT RUN CNTE=1, WAIT=1 CNTE=1, WAIT=0 TIN pin: Only trigger input enabled TIN pin: Functions as TIN pin TOT pin: Initial value output TOT pin: Functions as TOT pin Counter: Stores the value when counting stopped. Undefined just after a reset until loaded. RELD·UF TRG=1 Counter: Running TRG=1 RELD·UF LOAD CNTE=1, WAIT= 0 Load contents of the reload register to the counter. 156 Load complete CHAPTER 13 8/16-BIT PPG CHAPTER 13 8/16-BIT PPG This chapter provides an outline the 8/16-bit PPG and explains its functions. 13.1 "Outline of 8/16-bit PPG" 13.2 "8/16-bit PPG Block Diagrams" 13.3 "8/16-bit PPG Registers" 13.4 "8/16-bit PPG Operation" 13.5 "Count Clock Selection of 8/16-bit PPG" 13.6 "Pulse Pin Output Control of 8/16-bit PPG" 13.7 "Interrupts of 8/16-bit PPG" 13.8 "Default Values of Hardware Components of 8/16-bit PPG" 157 CHAPTER 13 8/16-BIT PPG 13.1 Outline of 8/16-bit PPG The 8/16-bit Programmable Pulse Generator (PPG) consists of two eight-bit down counters, four eight-bit reload registers, one 16-bit control register, two external pulse output signals, and two interrupt outputs. The following functions are implemented: ■ 8/16-bit PPG Functions ❍ 8-bit PPG output, 2-channel independent operation mode: Two independent channels of PPG output operation are implemented. ❍ 16-bit PPG output operation mode: One channel of 16-bit PPG output operation is implemented. ❍ 8+8-bit PPG output operation mode: 8-bit PPG output operation is implemented at specifies intervals, channel 0 output as channel 1 clock input. ❍ PPG output operation: Pulse waves are output at specified intervals and duty ratio. With an external circuit, this module can be used as a D/A converter. The MB90595 Series contains six PPG's. The following sections only describe the functionality of the PPG 0/1. The remaining PPG's have the identical function and the register addresses should be found in the I/O map. The output signal from the Channel 0 PPG is not connected to any external pin. 158 CHAPTER 13 8/16-BIT PPG 13.2 8/16-bit PPG Block Diagrams Figure 13.2-1 is an 8/16-bit PPG (ch.0) block diagram. Figure 13.2-2 is an 8/16-bit PPG (ch.1) block diagram. ■ 8/16-bit PPG Block Diagram Figure 13.2-1 8-bit PPG (ch.0) Block Diagram PPG Channel 0 PPG00 output enable PPG00 Peripheral clock 16-division Peripheral clock 8-division Peripheral clock 4-division Peripheral clock 2-division Peripheral clock In MB90595 Series, this signal is not connected to any external pin. PPG0 Output latch Invert Clear PEN0 In MB90595 Series, this IRQ signal merged with the Channel 1 IRQ signal Count clock selection Time-base counter output 512-division of main clock L/H selection by OR logic. S RQ PCNT (down counter) IRQ Reload ch.1-borrow L/H selector PRLL0 PRLBH0 PIE0 PRLH0 PUF0 L data bus H data bus PPGC0 (Operation mode control) 159 CHAPTER 13 8/16-BIT PPG Figure 13.2-2 8-bit PPG (ch.1) Block Diagram PPG Channel 1 PPG10 output enable PPG10 Peripheral clock 16-division Peripheral clock 8-division Peripheral clock 4-division Peripheral clock 2-division Peripheral clock In MB90595 Series this pin is connected the "PPG0" external pin. PPG1 Output latch Invert Count clock selection Clear PEN1 In MB90595 Series, this IRQ signal merged with the Channel 0 IRQ signal by OR logic. ch.0 borrow Time-base counter output 512-division of main clock L/H selection S RQ PCNT (down counter) IRQ Reload L/H selector PRLL1 PRLBH1 PIE1 PRLH1 PUF1 L data bus H data bus PPGC1 (Operation mode control) PPG0 PPG 2/3 PPG1 PPG 4/5 PPG2 PPG 6/7 PPG3 PPG 8/9 PPG4 PPG A/B PPG5 ⎧ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎨ ⎪ ⎪ ⎪ ⎪ ⎪ ⎩ 160 PPG 0/1 external pins t CHAPTER 13 8/16-BIT PPG 13.3 8/16-bit PPG Registers The following five types of 8/16-bit PPG registers are used: • PPG0 Operation Mode Control Register • PPG1 Operation Mode Control Register • PPG0, 1 Output Pin Control Register • Reload Register H • Reload Register L ■ 8/16-bit PPG Registers PPG0 Operation Mode Control Register 7 bit Address: ch.0 000038H Read/write Initial value 5 4 3 2 PEN0 PE00 (R/W) (0) (R/W) (R/W) (R/W) (0) (0) (0) PPG1 Operation Mode Control Register bit 15 Address: ch.1 000039H PEN1 Read/write Initial value 6 14 13 12 11 Reload Register H Address: ch.0 001901H ch.1 001903H Read/write Initial value Reload Register L 10 9 8 MD0 Reserved (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) PPGC1 (W) (1) 0 PPG01 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) bit 15 14 13 12 11 10 9 8 PRLH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) bit 7 6 5 4 3 2 1 0 Address: ch.0 001900H ch.1 001902H Read/write Initial value PPGC0 (W) (1) PPG0,1 Output Pin Control Register 6 5 4 3 2 1 bit 7 Address: ch.0, ch.1 PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 00003AH Read/write Initial value 0 Reserved PIE0 PUF0 PEN10 PIE1 PUF1 MD1 (R/W) (0) 1 PRLL (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) R/W : Readable/Writable W : Write only X : Undefined 161 CHAPTER 13 8/16-BIT PPG 13.3.1 PPG0 Operation Mode Control Register (PPGC0) PPGC0 is a five-bit control register that selects the operation mode of the block, controls pin outputs, selects count clock, and controls triggers. ■ PPG0 Operation Mode Control Register (PPGC0) PPG0 operation mode control register 7 6 Address: ch.0 000038H PEN0 Read/write Initial value (R/W) (0) - 5 4 3 PE00 PIE0 PUF0 (R/W) (0) (R/W) (0) (R/W) (0) 2 - 1 - 0 Reserved Bit No. PPGC0 (W) (1) R/W : Readable/Writable W : Write only [bit7] PEN0 (PPG enable): Operation enable bit This bit enables the counter operation of the PPG. PEN0 Operation 0 Stop ("L" level output maintained) 1 PPG operation enabled Setting this bit to 1 enables the counter operation. This bit is initialized to "0" upon a reset. This bit is readable and writable. [bit5] PE00 (PPG output enable 00): PPG00 pin output enable bit This bit controls the PPG00 pulse output external pin as described below. 0 General-purpose port pin (pulse output disabled) 1 PPG00 = pulse output pin (pulse output enabled) This bit is initialized to "0" upon a reset. This bit is readable and writable. For MB90595 Series, this bit should always be set to "0". [bit4] PIE0 (PPG interrupt enable): PPG interrupt enable bit This bit controls PPG interrupt as described below. 0 Interrupt disabled 1 Interrupt enabled While this bit is "1", an interrupt request is issued as soon as PUF0 is set to "1". No interrupt request is issued while this bit is set to "0". This bit is initialized to "0" upon a reset. This bit is readable and writable. 162 CHAPTER 13 8/16-BIT PPG [bit3] PUF0 (PPG underflow flag): PPG counter underflow bit This bit indicates the PPG counter underflow as described below. 0 PPG counter underflow is not detected. 1 PPG counter underflow is detected. In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to "1" when an underflow occurs as a result of the ch.0 counter value becoming from 00H to FFH. In 16bit PPG mode, this bit is set to "1" when an underflow occurs as a result of the Channel 0 and 1 counter value becoming from 0000H to FFFFH. To set this bit to "0", write "0" Writing "1" to this bit has not effect. Upon a read operation during a read-modify-write instruction, "1" is read. This bit is initialized to "0" upon a reset. This bit is readable and writable. [bit0] Reserved bit This is a reserved bit. When setting PPGC0, always set this bit to "1". 163 CHAPTER 13 8/16-BIT PPG 13.3.2 PPG1 Operation Mode Control Register (PPGC1) PPGC1 is a seven-bit control register that selects the operation mode of the block, controls pin outputs, selects count clock, and controls triggers. ■ PPG1 Operation Mode Control Register (PPGC1) PPG1 operation mode control register 14 Address: ch.1 000039H 15 PEN1 Read/write (R/W) Initial value (0) R/W : Readable/Writable W : Write only − 13 12 11 10 9 8 PE10 PIE1 PUF1 MD1 MD0 Reserved (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (W) (1) Bit No. PPGC1 [bit15] PEN1 (PPG enable): Operation enable bit This bit enables the counter operation of the PPG. PEN1 Operation 0 Stop ("L" level output maintained) 1 PPG operation enabled Setting this bit to 1 enables the counter operation. This bit is initialized to "0" upon a reset. This bit is readable and writable. [bit13] PE10 (PPG output enable 10): PPG10 pin output enable bit This bit controls the PPG10 pulse output external pin as described below. 0 General-purpose port pin (pulse output disabled) 1 PPG10 = pulse output pin (pulse output enabled) This bit is initialized to "0" upon a reset. This bit is readable and writable. For MB90595 Series , the pulse signal is output to the "PPG0" external pin. [bit12] PIE1 (PPG interrupt enable): PPG interrupt enable bit This bit controls PPG interrupt as described below. 0 Interrupt disabled 1 Interrupt enabled While this bit is "1", an interrupt request is issued as soon as PUF0 is set to "1". No interrupt request is issued while this bit is set to "0". This bit is initialized to "0" upon a reset. This bit is readable and writable. 164 CHAPTER 13 8/16-BIT PPG [bit11] PUF1 (PPG underflow flag): PPG counter underflow bit This bit indicates the PPG counter underflow as described below. 0 PPG counter underflow is not detected. 1 PPG counter underflow is detected. In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to "1" when an underflow occurs as a result of the Channel 1 counter value becoming from 00H to FFH. In 16-bit PPG mode, this bit is set to "1" when an underflow occurs as a result of the Channel 0 and 1 counter value becoming from 0000H to FFFFH. To set this bit to "0" write "0". Writing "1" to this bit has not effect. Upon a read operation during a read-modify-write instruction, "1" is read. This bit is initialized to "0" upon a reset. This bit is readable and writable. [bit10, bit9] MD1, 0 (PPG count mode): Operation mode selection bit These bits selects the PPG timer operation mode as described below. MD1 MD0 Operation mode 0 0 8-bit PPG 2ch independent mode 0 1 8-bit prescaler + 8-bit PPG 1ch mode 1 0 Reserved 1 1 16-bit PPG 1ch mode These bits are initialized to "00" upon a reset. These bits are readable and writable. Note: Do not set "10" in these bits. To write "01" to these bits, ensure that "01" is not written to the PEN0 bit of PPGC0 or PEN1 bit of PPGC1. Write "11" or "00" in both the PEN0 and PEN1 bits simultaneously. To write "11" to these bits, update PPGC0 and PPGC1 by word transfer and write "11" or "00" to both the PEN0 and PEN1 bits simultaneously. [bit8] This is a reserved bit. When setting PPGC1, always write 1 to this bit. 165 CHAPTER 13 8/16-BIT PPG 13.3.3 PPG0, 1 Output Pin Control Register (PPG01) The PPG0, 1 output pin control register (PPG01) is an 8-bit control register that controls the output of the 8/16-bit PPG pins. ■ PPG0, 1 Output Pin Control Register (PPG01) PPG0, 1 Output Pin Control Register 7 6 Address: ch.0, ch.1 00003AH PCS2 PCS1 Read/write Initial value (R/W) (0) (R/W) (0) 5 4 3 2 PCS0 PCM2 PCM1 PCM0 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) 1 0 Bit No. PPG01 R/W : Readable/Writable [bit7 to bit5] PCS2 to 0 (PPG count select): Count clock selection bit These bits select the operation clock for the down counter of Channel 1 as described below. PCS2 PCS1 PCS0 Operation mode 0 0 0 Peripheral clock (62.5 ns machine clock, 16 MHz) 0 0 1 Peripheral clock/2 (125 ns machine clock, 16 MHz) 0 1 0 Peripheral clock/4 (250 ns machine clock, 16 MHz) 0 1 1 Peripheral clock/8 (500 ns machine clock, 16 MHz) 1 0 0 Peripheral clock/16 (1 µs machine clock, 16 MHz) 1 1 1 Clock input from the time-base timer (128 µs, 4 MHz source) These bits are initialized to "000" upon a reset. These bits are readable and writable. Note: In 8-bit prescaler + 8-bit PPG mode or in 16-bit PPG mode, since ch.1 PPG operates in response to a counter clock from ch.0, the settings from PCS2 to PCS0 bits are not valid. 166 CHAPTER 13 8/16-BIT PPG [bit4 to bit2] PCM2 to 0 (PPG count mode): Count clock selection bit These bits select the operation clock for the down counter of Channel 0 as described below. PCM2 PCM1 PCM0 Operation mode 0 0 0 Peripheral clock (62.5 ns machine clock, 16 MHz) 0 0 1 Peripheral clock/2 (125 ns machine clock, 16 MHz) 0 1 0 Peripheral clock/4 (250 ns machine clock, 16 MHz) 0 1 1 Peripheral clock/8 (500 ns machine clock, 16 MHz) 1 0 0 Peripheral clock/16 (1 µs machine clock, 16 MHz) 1 1 1 Clock input from the time-base timer (128 µs, 4 MHz source) These bits are initialized to "000" upon a reset. These bits are readable and writable. 167 CHAPTER 13 8/16-BIT PPG 13.3.4 Reload Registers (PRLL, PRLH) Each of the reload registers PRLL and PRLH is an 8-bit register that retains a value to be reloaded to the down counter PCNT. Either register can be read and written. ■ Reload Registers (PRLL, PRLH) 15 14 13 12 11 10 9 8 Reload register H Address: ch.0 001901H ch.1 001903H Bit No. PRLH Read/write Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) 7 6 5 4 (R/W) (R/W) (X) (X) 3 2 (R/W) (X) 1 Reload register L Address: ch.0 001900H ch.1 001902H 0 Bit No. PRLL Read/write Initial value (R/W) (X) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (R/W) (R/W) (X) (X) (R/W) (X) R/W : Readable/Writable X : Undefined Register name Function PRLL Holds the L side reload value. PRLH Holds the H side reload value. Note: In 8-bit prescaler + 8-bit PPG mode, different values in PRLL and PRLH of Channel 0 may cause the PPG waveform of ch.1 to vary in each cycle. Write the same value to PRLL and PRLH of ch.0. 168 CHAPTER 13 8/16-BIT PPG 13.4 8/16-bit PPG Operation One 8/16-bit PPG consists of two channels of 8-bit PPG units. These two channels can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG mode, and single-channel 16-bit PPG mode. ■ 8/16-bit PPG Operation Each of the 8-bit PPG units has two eight-bit reload registers. One reload register is for the "L" pulse width (PRLL) and the other is for the "H" pulse width (PRLH). The values stored in these registers are reloaded into the 8-bit down counter (PCNT), from the PRLL and PRLH in turn. The pin output value is inverted upon a reload caused by counter borrow. This operation results in the pulses of the specified "L" pulse width and "H" pulse width. Table 13.4-1 lists the relationship between the reload operation and pulse outputs. Table 13.4-1 Reload Operation and Pulse Output Reload operation Pin output change PRLH —> PCNT PPG00/01 [0 —> 1] Rise PRLL —> PCNT PPP00/01 [1 —> 0] Fall When "1" is set in bit 4 (PIE0) of PPGC0 or in bit 12 (PIE1) of PPGC1, an interrupt request is output upon a borrow from 00 to FF (from 0000 to FFFF in 16-bit PPG mode) of each counter. ■ 8/16-bit PPG Operation This block can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG mode, and single-channel 16-bit PPG mode. ❍ Independent two-channel mode In independent two-channel mode, the two channels of 8-bit PPG units operate independently. The PPG00 pin is connected to the ch.0 PPG output, while the PPG10 pin is connected to the ch.1 PPG output. ❍ 8-bit prescaler + 8-bit PPG mode In 8-bit prescaler + 8-bit PPG mode, ch.0 is used as an 8-bit prescaler while the count in ch.1 is based on borrow outputs from ch.0. Thus, 8-bit PPG waveforms can be output with arbitrary length of cycle time. The PPG00 pin is connected to the ch.0 prescaler output, while the PPG10 pin is connected to the ch.1 PPG output. 169 CHAPTER 13 8/16-BIT PPG ❍ 16-bit PPG 1ch mode In 16-bit PPG 1ch mode, ch.0 and ch.1 are connected and used as a single 16-bit PPG. The PPG00 and PPG10 pins are connected to the 16-bit PPG output. For the MB90595 Series, the output signal from the Channel 0 PPG is not connected to any external pin. ■ 8/16-bit PPG Output Operation In this block, the ch.0 PPG is activated to start counting when "1" is written to bit 7 (PEN0) of the PPGC0 (PWM operation mode control) register. Similarly, the ch.1 PPG is activated to start counting when "1" is written to bit 15 (PEN1) of the PPGC1 register. Once the operation has started, counting is terminated by writing "0" to bit 7 (PEN0) of PPGC0 or in bit 15 (PEN1) of PPGC1. Once the counting is terminated, the output is maintained at the L level. For the MB90595 Series, the output signal from the Channel 0 PPG is not connected to any external pin. In 8-bit prescaler + 8-bit PPG mode, do not set ch.1 to be in operation while ch.0 operation is stopped. In 16-bit PPG mode, ensure that bit 7 (PEN0) of PPGC0 register and bit 15 (PEN1) of PPGC1 register are started or stopped simultaneously. Figure 13.4-1 is a diagram of PPG output operation. During PPG operation, a pulse wave is continuously output at a frequency and duty ratio (the ratio of the H-level period of the pulse wave to the L-level period). PPG continues operation until stop is specified explicitly. Figure 13.4-1 PPG Output Operation, Output Waveform PEN Starts operation based on PEN (from Lside). Output pin PPG T x (L+1)T x (H+1) L:PRLL value H:PRLH value T:Input from peripheral clock (φ, φ/4, φ/16) (Start) or timer-base counter (depending on the φ : Machine cycle clock selection by PPGC) ■ Relationship between 8/16-bit PPG Reload Value and Pulse Width The width of the output pulse is determined by adding 1 to the reload register value and multiplying it by the count clock cycle. Note that when the reload register value is 00H during 8-bit PPG operation or 0000H during 16bit PPG operation, the pulse width is equivalent to one count clock cycle. In addition, note that when the reload register value is FFH during 8-PPG operation, the pulse width is equivalent to 256 count clock cycles. When the reload register value is FFFFH during 16-bit PPG operation, the pulse width is equivalent to 65536 count clock cycles. An example of pulse width calculation is given below. P1=T x (L+1) Ph=T x (H+1) 170 L :PRLL value H :PRLH value T :Input clock cycle Ph :High pulse width Pl :Low pulse width CHAPTER 13 8/16-BIT PPG 13.5 Count Clock Selection of 8/16-bit PPG The count clock used for the operation is supplied from the peripheral clock or the time-base timer. The count clock can be selected from six choices. ■ Count Clock Selection of 8/16-bit PPG Select ch.0 clock at bit 4 to 2 (PCM2 to 0) of the PPG01 register, and ch.1 clock at bit 7 to 5 (PCS2 to 0) of the PPG01 register. The clock is selected from a peripheral clock 1/16 to 1 times higher than a machine clock or an input clock from the time-base timer. In 8-bit prescaler + 8-bit PPG mode or 16-bit PPG mode, however, the setting in the PCS2 to 0 has no effect. When the time-base timer input is used, the first count cycle after a trigger or a stop may be shifted. The cycle may also be shifted if the time-base counter is cleared during operation of this module. In 8-bit prescaler + 8-bit PPG mode, if ch.1 is activated while ch.0 is in operation and ch.1 is stopped, the first count cycle may be shifted. 171 CHAPTER 13 8/16-BIT PPG 13.6 Pulse Pin Output Control of 8/16-bit PPG The pulses generated by this module can be output from external pins PPG00 and PPG10. ■ Pulse Pin Output Control of 8/16-bit PPG To output the pulses from an external pin, write "1" to the bit corresponding to each pin (PPGC0:PE00, PPGC1:PE10). When "0" is written to these bits (default), the pulses are not output from the corresponding external pins; the pins work as general-purpose ports. In 16-bit PPG mode, the same waveform is output from PPG00 and PPG10. Thus, the same output can be obtained by enabling both external pin. In 8-bit prescaler + 8-bit PPG mode, the 8-bit prescaler toggle output waveform is output from PPG00, while the 8-bit PPG waveform is output from PPG10. Figure 13.6-1 is a diagram of output waveforms in this mode. For the MB90595 Series, the output signal from the Channel 0 PPG is not connected to any external pin. Figure 13.6-1 8+8 PPG Output Operation Waveform Ph0 Pl0 PPG00 PPG10 Ph1 Pl1 L0:ch.0 PRLL value and ch.0 PRLH value L1:ch.1 PRLL value Pl0 = T x (L0+1) Ph0 = T x (L0+1) Pl1 = T x (L0+1) x (Ll+1) Ph1 = T x (L0+1) x (Hl+1) H1:ch.1 PRLH value T: Input clock cycle Ph0:PPG00 high pulse width Pl0:PPG00 low pulse width Ph1:PPG10 high pulse width Pl1:PPG10 low pulse width Note: Set the same value in ch.0 PRLL and ch.0 PRLH. 172 CHAPTER 13 8/16-BIT PPG 13.7 Interrupts of 8/16-bit PPG For this module, an interrupt becomes active when the reload value is counted out and a borrow occurs. ■ Interrupts of 8/16-bit PPG In 8-bit PPG 2ch mode or 8-bit prescaler + 8-bit PPG mode, an interrupt is requested by a borrow in each counter. In 16-bit PPG mode, PUF0 and PUF1 are simultaneously set by a borrow in the 16-bit counter. Therefore, enable only PIE0 or PIE1 to unify the interrupt causes. In addition, simultaneously clear the interrupt flags for PUF0 and PUF1. 173 CHAPTER 13 8/16-BIT PPG 13.8 Default Values of Hardware Components of 8/16-bit PPG The hardware components of this block are initialized to the following values when reset: ■ Default Values of Hardware Components of 8/16-bit PPG <Registers> • PPGC0 • PPGC1 0X000001B • PPG10 XXXXXX00B • • • • PPG00 "L" PPG10 "L" PE00 PPG00 output disabled PE10 PPG10 output disabled 00000001B <Pulse outputs> <Interrupt requests> • IRQ0 "L" • IRQ1 "L" Hardware components other than the above are not initialized. Note: Reload register write timing In a mode other than 16-bit PPG mode, it is recommended to use a word transfer instruction to write data in reload registers PRLL and PRLH. If two byte transfer instructions are used to write a data item to these registers, a pulse of unexpected cycle time may be output depending on the timing. Figure 13.8-1 Write Timing Chart PPG0 A B A B C B C D C D (1) Assume that PRLL is updated from A to C before point (1) in the time chart above, and PRLH is updated from B to D after point (1). Since the PRL values at point (1) are PRLL=C and PRLH=B, a pulse of L side count value C and H side count value B is output only once. Similarly, to write data in PRL of ch.0 and ch.1 in 16-bit PPG mode, use a long word transfer instruction, or use word transfer instructions in the order of ch.0 and then ch.1. In this mode, the data is only temporarily written to ch.0 PRL. Then, the data is actually written into ch.0 PRL when the ch.1 PRL is written to. In a mode other than 16-bit PPG mode, ch.0 and ch.1 PRL are written independently. 174 CHAPTER 13 8/16-BIT PPG Figure 13.8-2 PRL Write Operation Block Diagram ch.0 PRL write data ch.1 PRL write data Transferred in synchronization Temporary latch with ch.1 write in 16-bit PPG mode ch.0 write in a mode other than 16-bit PPG mode ch.1 write ch.0 PRL ch.1 PRL 175 CHAPTER 13 8/16-BIT PPG 176 CHAPTER 14 DTP/EXTERNAL INTERRUPTS CHAPTER 14 DTP/EXTERNAL INTERRUPTS This chapter explains the DTP/external interrupt functions and operation. 14.1 "Outline of DTP/External Interrupt" 14.2 "DTP/External Interrupt Registers" 14.3 "Operations of DTP/External Interrupts" 14.4 "Switching between External Interrupt and DTP Requests" 14.5 "Notes on Use of DTP/External Interrupts" 177 CHAPTER 14 DTP/EXTERNAL INTERRUPTS 14.1 Outline of DTP/External Interrupt The data transfer peripheral (DTP) is located between an external peripheral and the F2MC-16LX CPU. The DTP receives a DMA request or interrupt request from the external peripheral, transfers the request to the F2MC-16LX CPU to activate the intelligent I/O service or interrupt processing. ■ Outline of DTP/External Interrupt For the intelligent I/O service, "H" and "L" request levels are available. For an external interrupt request, four request levels are available: "H", "L", rising edge, and falling edge. For the MB90595 Series, the external bus interface is not supported. Therefore the DTP/ External Interrupt can not serve as the data transfer peripheral. It can be only used as the External Interrupt. ■ Block Diagram of DTP/External Interrupts Figure 14.1-1 Block Diagram 8 8 178 Interrupt/DTP enable register Gate Cause F/F Edge detection circuit 8 Interrupt/DTP cause register 16 Request level setting register 8 Request input CHAPTER 14 DTP/EXTERNAL INTERRUPTS ■ Registers of DTP/External Interrupts bit Address : 000030H bit Address : 000031H bit Address : 000032H bit Address : 000033H 7 6 5 4 3 2 1 0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 15 14 13 12 11 10 9 8 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 7 6 5 4 3 2 1 0 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 15 14 13 12 11 10 9 8 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 Interrupt/DTP enable register (ENIR) Interrupt/DTP cause register (EIRR) Request level setting register (ELVR) Request level setting register (ELVR) 179 CHAPTER 14 DTP/EXTERNAL INTERRUPTS 14.2 DTP/External Interrupt Registers The following three types of DTP/external interrupt registers are used: • Interrupt/DTP enable register (ENIR: Interrupt request enable register) • Interrupt/DTP source register (EIRR: External interrupt request register) • Request level setting register (ELVR: External level register) ■ Interrupt/DTP Enable Register (ENIR: Interrupt Request Enable Register) bit ENIR Address : 000030H 7 6 5 EN7 EN6 EN5 EN4 R/W R/W R/W R/W 2 1 0 Initial value EN3 EN2 EN1 EN0 00000000B R/W R/W R/W R/W 4 3 R/W : Readable/Writable ENIR enables the function to issue a request to the interrupt controller using a device pin as an external interrupt/DTP request input. A pin corresponding to a "1" bit of this register is used as an external interrupt/DTP request input. A pin corresponding to a "0" bit holds the external interrupt/DTP request input cause, but does not issue a request to the interrupt controller. ■ Interrupt/DTP Source Register (EIRR: External Interrupt Request Register) bit EIRR Address : 000031H Initial value 15 14 13 12 11 10 9 8 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 R/W R/W R/W R/W R/W R/W R/W R/W ........The objects differ for R and W. R/W : Readable/Writable XXXXXXXXB The EIRR indicates the presence of external interrupt/DTP requests at the pins corresponding to the "1" bits of this register. Writing "0" to a bit of this register clears the corresponding request flag. Writing "1" has no effect. "1" is always read from this register by read-modify-write instruction. Note: If more than one external interrupt request output is enabled (EN7 to EN0 of ENIR are set to "1"), clear to 0 only the bit for which the CPU accepted an interrupt (any of bits ER7 to ER0 that are set to "1"). Do not clear the other bits without a valid reason. 180 CHAPTER 14 DTP/EXTERNAL INTERRUPTS ■ Request Level Setting Register (ELVR: External Level Register) bit Address : 000032H bit Address : 000033H 7 6 LB3 LA3 R/W R/W 15 5 4 LB2 3 2 1 0 Initial value 00000000B LA2 LB1 LA1 LB0 LA0 R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 Initial value LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 00000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable/Writable ELVR defines the request event at the external pin. Each pin is assigned two bits as described in the table below. If a request is detected by the input level, the interrupt flag is set as long as the input is at the specified level even after the flag is reset by software. Table 14.2-1 Interrupt Request Detection Factor for LBx and LAx Pins LBx LAx 0 0 1 1 0 1 0 1 Interrupt request detection factor L level pin input H level pin input Rising edge pin input Falling edge pin input 181 CHAPTER 14 DTP/EXTERNAL INTERRUPTS 14.3 Operations of DTP/External Interrupts When the interrupt flag is set, this block signals an interrupt to the interrupt controller. The interrupt controller judges the priority levels of the simultaneous interrupts, and issues an interrupt request to the F2MC-16LX CPU if the interrupt from this block has the highest priority. The F2MC-16LX CPU compares the ILM bits of its internal CCR register and the interrupt request. If the interrupt level of the request is higher than that indicated by the ILM bits, the F2MC-16LX CPU activates the hardware interrupt processing microprogram as soon as the currently executing instruction is terminated. ■ External Interrupts In the hardware interrupt processing microprogram, the CPU reads the ISE bit information from the interrupt controller, identifies that the request is for interrupt processing based on that information, and branches to the interrupt processing microprogram. The interrupt processing microprogram reads the interrupt vector area and issues an interrupt acknowledgment signal for the interrupt controller. Then, the microprogram transfers the jump destination address of the macro instruction generated from the vector to the program counter, and executes the user interrupt processing program. Figure 14.3-1 External Interrupt External interrupt/DTP Interrupt controller F2MC-16 CPU ICRyy IL Other request ELVR EIRR ENIR Cause CMP ICRxx CMP ILM INTA ■ DTP Operation To activate the intelligent I/O service, the user program initially sets the address of a register, assigned between 000000H and 0000FFH, in the I/O address pointer of the intelligent I/O service descriptor. Then, the user program sets the start address of the memory buffer in the buffer address pointer. The DTP operation sequence is almost the same as for external interrupts. The operation is identical until the CPU activates the hardware interrupt processing microprogram. Then, for the DTP, control is transferred to the intelligent I/O service processing microprogram, since the ISE bit read by the CPU within the hardware interrupt processing microprogram indicates the DTP. Once the intelligent I/O service is activated, a read or write signal is sent to the addresses external peripheral, and data is transferred between the peripheral and the chip. The external peripheral must cancel the interrupt request to this chip within three machine cycles after the transfer is made. When the transfer is completed, the descriptor is updated, and the interrupt controller generates a signal that clears the transfer cause. Upon receiving the signal to clear the transfer cause, this resource clears the flip-flop holding the cause and prepares for the next request from the pin. For details of the intelligent I/O service processing, refer to the MB90500 Programming Manual. 182 CHAPTER 14 DTP/EXTERNAL INTERRUPTS Figure 14.3-2 Timing to Cancel the External Interrupt at the End of DTP Operation Internal operation Interrupt cause Selecting and reading descriptor Edge request or H level request * When data is transferred from the I/O register to memory in the intelligent I/O service Read address Address bus pin Write address Data bus pin Read data Read signal ➀ Write data Write signal ➁ Cancel within three machine cycles. Data, address bus Internal bus Register External peripheral Figure 14.3-3 Sample Interface to the External Peripheral ➀ INT IRQ DTP Cancel within three machine cycles after transfer. ➁ CORE MEMORY MB90595 183 CHAPTER 14 DTP/EXTERNAL INTERRUPTS 14.4 Switching between External Interrupt and DTP Requests To switch between external interrupt and DTP requests, use the ISE bit in the ICR register corresponding to this block, which is in the interrupt controller. Each pin is individually assigned ICR. Thus, a pin is used for a DTP request if "1" is written to the ISE bit of the corresponding ICR, and is used for an external interrupt request if "0" is written to the bit. ■ Switching between External Interrupt and DTP Requests Figure 14.4-1 Switching between External Interrupt and DTP Requests Interrupt controller 0 ICR xx ICR yy 1 F2MC-16 CPU Pin External interrupt/DTP DTP External interrupt 184 CHAPTER 14 DTP/EXTERNAL INTERRUPTS 14.5 Notes on Use of DTP/External Interrupts When using the DTP/external interrupt, be careful about the following: • Conditions on the externally connected peripheral when DTP is used • Recovery from standby • DTP/external interrupt operation procedure • External interrupt request level ■ Notes on Use of DTP/External Interrupts ❍ Conditions on the externally connected peripheral when DTP is used DTP supports only external peripherals that automatically clear a request once a transfer is completed. The system must be designed so that a transfer request is canceled within three machine cycles (provisional) after transfer operation starts. Otherwise, this resource assumes that a transfer request is issued. ❍ Recovery from standby To use an external interrupt to recover from the standby state in stop mode and timer mode, use an H or L level request as an input request. If an edge request is used, recovery from the standby state in stop mode and timer mode cannot be performed. ❍ External interrupt/DTP operation procedure To set registers in the external interrupt/DTP, follow the steps below: 1. Disable the bits corresponding to the enable register. 2. Set the bits corresponding to the request level setting register. 3. Clear the bits corresponding to the cause register. 4. Enable the bits corresponding to the enable register. Steps 3. and 4. can be simultaneously performed by word specification.) To set a register in this resource, ensure that the enable register is disabled. Before enabling the enable register, ensure that the cause register is cleared. Clearing the cause register prevents a false interrupt cause from being determined while registers are set or interrupts are enabled. 185 CHAPTER 14 DTP/EXTERNAL INTERRUPTS ❍ External interrupt request level To detect an edge for a edge request level, the pulse width must be at least three machine cycles. If the request input level is related to level setting, the request to the interrupt controller is kept active as shown in Figure 14.5-1 . Because of the internal interrupt request flag bit (EIRR:ER), the request is kept active even if it is input from the external device and then canceled. To cancel the request to the interrupt controller, clear the interrupt request flag bit (EIRR : ER) as shown in Figure 14.5-2 . Figure 14.5-1 Interrupt Request Flag Bit (EIRR:ER) upon Level Set Level detection Interrupt cause Interrupt request flag bit (EIRR:ER) Enable gate To interrupt controller The cause is kept held unless cleared. Figure 14.5-2 Interrupt Cause and Interrupt Request to the Interrupt Controller while Interrupts are Enabled Interrupt cause Interrupt request to the interrupt controller 186 H level Set inactive when the interrupt request flag bit (EIRR:ER) is cleared. CHAPTER 15 A/D CONVERTER CHAPTER 15 A/D CONVERTER This chapter explains the A/D converter functions and operation. 15.1 "Features of A/D Converter" 15.2 "A/D Converter Block Diagram" 15.3 "A/D Converter Registers" 15.4 "A/D Converter Operation" 15.5 "Conversion Using EI2OS" 15.6 "Conversion Data Protection" 187 CHAPTER 15 A/D CONVERTER 15.1 Features of A/D Converter The A/D converter converts analog input voltages into digital values. The A/D converter has the following features: ■ Features of A/D Converter ❍ Conversion time: 26.3 µs min. per channel (at 16 MHz machine clock) ❍ RC sequential compare conversion with sample and hold circuit ❍ 10 bit or 8 bit resolution ❍ Analog input selected from eight channels by programming • Single conversion mode: One channel is selected for conversion. • Scan conversion mode: Voltages in multiple consecutive channels are converted. Up to eight channels can be programmed. • Continuous conversion mode: Voltages at the specified channel are converted repeatedly. • Stop conversion mode: Voltages at the specified channel are converted, then the system pauses and stands by for the next activation. (The conversion start points can be synchronized.) ❍ Interrupt request At the end of A/D conversion, a relevant interrupt request can be issued to the CPU. This interrupt can be used to activate the EI2OS, which automatically transfers A/D conversion result to memory. This feature is suitable for continuous processing. ❍ Selectable activation cause The activation can be done by software, external trigger (falling edge), or timer (rising edge). ■ Analog Input Enable Register Always write "1" to the ADEx bit corresponding to a pin used as analog input. 188 CHAPTER 15 A/D CONVERTER bit Address: 00001BH 7 6 5 4 3 2 1 0 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value 11111111B R/W : Readable/Writable Port 6 pins are controlled as described below. 0: Port input/output mode 1: Analog input mode "1" is set upon a reset. ■ Input Impedance The sampling circuit of the A/D Converter can be represented by the equivalent circuit shown below. ADC Analog input 30 pF max. The driving impedance to an analog input should be lower than 15.5 kΩ when the sampling time is set to 4µs (ST1=0 and ST0=0 at 16MHz machine clock). Otherwise the conversion accuracy will be worsened. If this is the case, set the sampling time longer (ST1=1 and ST0=1) or add external capacitor in order to compensate the driving impedance. 189 CHAPTER 15 A/D CONVERTER 15.2 A/D Converter Block Diagram Figure 15.2-1 is an A/D converter block diagram. ■ A/D Converter Block Diagram Figure 15.2-1 A/D Converter Block Diagram AVcc AVRH/L AVss D/A converter MPX Comparator Input circuit Sequential compare register Data bus AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Decoder Sample and hold circuit Data register ADCR0, ADCR1 ADCS0, ADCS1 A/D control register 0 A/D control register 1 ADTG Activation by external trigger Activation by timer Operation clock 16-bit Reload Timer 1 φ 190 Prescaler CHAPTER 15 A/D CONVERTER 15.3 A/D Converter Registers The following two types of A/D converter registers are used: • Control status register • Data register ■ A/D Converter Registers Figure 15.3-1 A/D Converter Register Configuration 15 bit Address : 000034H bit Address : 00035H bit Address : 000036H bit Address : 000037H 8 7 0 ADCS1 ADCS0 ADCR1 ADCR0 8SSR bit 8 bit 7 6 MD1 MD0 5 4 3 ANS2 ANS1 ANS0 2 ANE2 15 14 13 12 11 10 BUSY INT INTE PAUS STS1 STS0 7 6 5 4 3 2 D7 D6 D5 D4 D3 15 14 13 12 11 S10 ST1 ST0 CT1 CT0 1 0 ANE1 ANE0 9 8 Control status registers (ADCS0 and ADCS1) STRT Reserved 1 0 D2 D1 D0 10 9 8 D9 D8 Data registers (ADCR0 and ADCR1) 191 CHAPTER 15 A/D CONVERTER 15.3.1 Control Status Registers (ADCS0) These registers are used to control the A/D converter and indicate the status. Do not update ADCS0 during A/D conversion. ■ Control Status Registers (ADCS0) bit ADCS0 Address: 000034H 7 6 5 4 3 2 1 0 MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 0 R/W R/W : Readable/Writable 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial value Bit attribute [bit7, bit6] MD1 and MD0 (A/D converter mode set): These bits are used to set the A/D converter operation mode. MD1 MD0 Operation mode 0 0 Single mode. Reactivation during operation is allowed. 0 1 Single mode. Reactivation during operation is not allowed. 1 0 Continuous mode. Reactivation during operation is not allowed. 1 1 Stop mode. Reactivation during operation is not allowed. ❍ Single mode: A/D conversion is continuously performed from the channel specified with ANS2 to ANS0 to the channel specified with ANE2 to ANE0. The conversion stops once it has been done for all these channels. ❍ Continuous mode: A/D conversion is repeatedly performed from the channel specified with ANS2 to ANS0 to the channel specified with ANE2 to ANE0. 192 CHAPTER 15 A/D CONVERTER ❍ Stop mode: A/D conversion is performed from the channel specified with ANS2 to ANS0 to the channel specified with ANE2 to ANE0, pausing for each channel. The A/D conversion is resumed upon an activation. Upon a reset, these bits are initialized to "00". Note: When activated in the continuous or stop mode, A/D conversion continues until it is stopped by the BUSY bit. The conversion is stopped by writing "0" to the BUSY bit. The prohibition of activation in single, continuous, or stop mode applies to timer, external trigger, and software activation. This disables all kinds of activations. [bit5 to bit3] ANS2 to ANS0 (Analog start channel set): Use these bits to specify the start channel for A/D conversion. When the A/D converter is activated, A/D conversion starts from the channel selected with these bits. ANS2 ANS1 ANS0 Start channel 0 0 0 AN0 0 0 1 AN1 0 1 0 AN2 0 1 1 AN3 1 0 0 AN4 1 0 1 AN5 1 1 0 AN6 1 1 1 AN7 Note: Read: During A/D conversion, the current conversion channel is read from these bits. If the system is stopped in the stop mode, the last conversion channel is read. Upon a reset, these bits are initialized to "000". 193 CHAPTER 15 A/D CONVERTER [bit2 to bit0] ANE2 to ANE0 (Analog end channel set): Use these bits to set the A/D conversion end channel. ANE2 ANE1 ANE0 End channel 0 0 0 AN0 0 0 1 AN1 0 1 0 AN2 0 1 1 AN3 1 0 0 AN4 1 0 1 AN5 1 1 0 AN6 1 1 1 AN7 Note: When the same channel is written to ANE2 to ANE0 and ANS2 to ANS0, conversion is performed for one channel only (single conversion). In the continuous or stop mode, operation returns to the start channel specified in ANS2 to ANS0 after the conversion is completed for the channel specified in ANE2 to ANE0. If the ANS value is greater than the ANE value, conversion starts from the ANS channel. Then, once conversion is complete up to channel 7, operation returns to channel 0 and conversion is performed up to the ANE channel. Upon a reset, these bits are initialized to "000". Example: ANS=ch.6, ANE=ch.3, single mode Conversion is performed in the following sequence: ch.6, ch.7, ch.0, ch.1, ch.2, ch.3 194 CHAPTER 15 A/D CONVERTER 15.3.2 Control Status Register (ADCS1) The control status register (ADCS1) controls the A/D converter and displays status information. ■ Control Status Register (ADCS1) ADCS1 Address: 000035H bit 15 BUSY 0 R/W R/W : Readable/Writable W : Write only 14 13 12 11 10 9 8 INT INTE PAUS STS1 STS0 STRT Reserved 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 W 0 R/W ←Initial value ←Bit attribute [bit15] BUSY (busy flag and stop): Read: This bit indicates the A/D converter operation. This bit is set when the A/D conversion is activated, and cleared when the conversion ends. Write: Writing "0" to this bit during A/D conversion forces the conversion to terminate. This features is used for forced stop in the continuous or stop mode. "1" cannot be written to the BUSY bit. With a read-modify-write instruction, "1" is read from this bit. In the single mode, this bit is cleared at the end of A/D conversion. In the continuous or stop mode, this bit is not cleared until conversion is stopped by writing "0". This bit is initialized to "0" upon a reset. Do not perform a forced stop and activation by software simultaneously. (BUSY=0, STRT=1) [bit14] INT (Interrupt): This bit is set when conversion data is written to ADCR. An interrupt request is issued if this bit is set while bit 5 (INTE) is "1". In addition, the EI2OS is activated if it is enabled. Writing "1" has no effect. This bit is cleared by writing "0" or by the EI2OS interrupt clear signal. Note: To clear this bit by writing "0", ensure that A/D conversion is not in progress. This bit initialized to "0" upon a reset. [bit13] INTE (Interrupt enable): This bit is used to enable or disable interrupts at the end of conversion. 0: Interrupts are disabled. 1: Interrupts are enabled. Set this bit when using the EI2OS. The EI2OS is activated when an interrupt request is issued. Upon a reset, this bit is initialized to "0". 195 CHAPTER 15 A/D CONVERTER [bit12] PAUS (A/D conversion pause): This bit is set when the A/D conversion is paused. Only one register is available for storing the A/D conversion result. Therefore, unless the conversion results are transferred by the EI2OS, the result data would be continuously updated and destroyed in continuous conversion. To prevent the above condition, the system is designed so that a data register value must be transferred by the EI2OS before the next conversion data is saved. A/D conversion pauses during that period. A/D conversion is resumed at the end of transfer by the EI2OS. This register is valid only when the EI2OS is used. Note: For the conversion data protection function, see Section 15.4 "A/D Converter Operation". Upon a reset, this bit is initialized to "0". [bit11, bit10] STS1 and STS0 (Start source select): Upon a reset, these bits are initialized to "00". These bits are used to select the A/D conversion activation source. STS1 STS0 Function 0 0 Activation by software 0 1 Activation by external pin trigger and software 1 0 Activation by timer and software 1 1 Activation by external pin trigger, timer, and software In a mode allowing two or more activation factors, A/D conversion is activated by the source that occurs first. The activation source setting changes as soon as it is updated. Thus, take care when updating it during A/D conversion. Note: The external pin trigger is detected by the falling edge. If this bit is updated to external trigger activation while the external trigger input level is "L", A/D may be activated at once. When timer is selected, the 16-bit Reload Timer 1 is selected. [bit9] STRT (Start): A/D conversion is activated when "1" is written to this bit. To reactivate A/D conversion, write "1" to this bit again. Upon a reset, this bit is initialized to "0". In the stop mode, a reactivation during the operation is not supported. Check the BUSY bit before writing "1". Do not perform a forced stop and activation by software simultaneously. (BUSY=0, STRT=1) [bit8] Reserved This is a reserved bit. Always write "0" to this bit. 196 CHAPTER 15 A/D CONVERTER 15.3.3 Data Registers (ADCR0, ADCR1) These registers are used to store the digital values produced as a result of the conversion. ADCR1 stores the most significant two bits of the conversion result, while ADCR0 stores the lower eight bits. These register values are updated each time conversion is completed. Usually, the final conversion value is stored in these bits. ■ Data Registers (ADCR0, ADCR1) bit ADCR0 Address : 000036H bit ADCR1 Address : 000037 H R W - 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R R R R R R R R 15 14 13 12 11 10 9 8 S10 ST1 ST0 CT1 CT0 D9 D8 W W W W W R R Initial value XXXXXXXX Initial value 00001_XX : Read only : Write only :Undefined "0" is always read from the bit10 to bit15 of ADCR1. The conversion data protection function is available. See Section 15.4 "A/D Converter Operation". Ensure that no data is written to these registers during A/D conversion. [bit15] S10 This bit specifies the resolution of the conversion. When it is set to "0", the 10-bit A/D conversion is performed. Otherwise the 8-bit A/D conversion is performed and the result is stored in the D7 to D0. Reading this bit always results in the reading value "0". [bit14, bit13] ST1 and ST0 (Sampling time): ST1 ST0 Function 0 0 64 machine cycles (4µs at 16MHz) 0 1 Reserved 1 0 Reserved 1 1 4096 machine cycles (256µs at 16MHz) These bits determine the duration of the voltage sampling time at the input. Reading this bit group always results in the reading value "00". 197 CHAPTER 15 A/D CONVERTER [bit12, bit11] CT1, CT0 (Compare time): CT1 CT0 Function 0 0 176 machine cycles (22µs at 8MHz) 0 1 352 machine cycles (22µs at 16MHz) 1 0 Reserved 1 1 Reserved These bits determine the duration of the compare operation time. Do not set to '"0" unless the machine clock is 8MHz. Otherwise the conversion accuracy is not guaranteed. Reading this bit group always results in the reading value "00". [bit9 to bit0] D9 to D0 198 CHAPTER 15 A/D CONVERTER 15.4 A/D Converter Operation The A/D converter operates employs the sequential compare technique, and can be selected from 10-bit or 8-bit resolution. Since the A/D converter has one register (16 bit) for storing the conversion result, the conversion data registers (ADCR0 and ADCR1) are updated each time conversion is completed. Thus, the A/D converter alone must not be used for the continuous conversion. Use the Extended intelligent I/O service (EI2OS) function to transfer converted data to memory while conversion is in progress. ■ Single Mode In this mode, the converter sequentially converts the analog inputs specified with the ANS and ANE bits. The converter stops operation after the conversion is completed for the end channel specified with the ANE bits. If the start and end channels are the same (ANS=ANE), conversion is performed only for one channel. Example: ANS = 0 0 0 , ANE = 0 1 1 Start AN0 AN1 AN2 AN3 End ANS = 0 1 0 , ANE = 0 1 0 Start AN2 End ■ Continuous Mode In this mode, the converter sequentially converts the analog inputs specified with the ANS and ANE bits. After the conversion is completed for the end channel specified with the ANE bits, conversion is repeated from the analog inputs of the ANS. If the start and end channels are the same (ANS=ANE), conversion for one channel is repeated. Example: ANS = 0 0 0 , ANE = 0 1 1 Start AN0 AN1 AN2 ANS = 0 1 0 , ANE = 0 1 0 Start AN2 AN2 AN2 AN3 AN0 Repeat Repeat In continuous mode, conversion is repeated until "0" is written to the BUSY bit. (Writing "0" to the BUSY bit forces the operation to end.) If the operation is terminated forcibly, conversion stops before conversion is completed. (Upon a forced stop, the conversion register stores the last data that has been converted completely.) 199 CHAPTER 15 A/D CONVERTER ■ Stop Mode In this mode, the converter sequentially converts the analog inputs specified with the ANS and ANE bits, pausing each time conversion for one channel is completed. To release pausing, activate the converter again. After the conversion is completed for the end channel specified with the ANE bits, conversion is repeated from the analog inputs of the ANS. If the start and end channels are the same (ANS=ANE), conversion is performed only for one channel. Example: ANS = 0 0 0 , ANE = 0 1 1 Start AN0 End Restart AN3 End AN1 Restart AN0 Restart AN2 End Restart AN2 End Restart Repeat ANS = 0 1 0 , ANE = 0 1 0 Start AN2 End End Restart AN2 Repeat Only the activation sources specified with STS1 and STS0 are used. Using this mode, start of conversion can be synchronized with the activation source. 200 CHAPTER 15 A/D CONVERTER 15.5 Conversion Using EI2OS Sample flow from A/D conversion activation to transfer of converted data (continuous mode). ■ Conversion Using EI2OS Figure 15.5-1 Sample Sequence from A/D Conversion Activation to Transfer of Converted Data (Continuous Mode) Starting A/D conversion Sample and hold Starting EI 2 OS Conversion Transferring data Interrupt processing End of conversion Issuing interrupt ✩ The portion indicated by the star ( Clearing interrupt ) is determined according to the EI2OS setting. 201 CHAPTER 15 A/D CONVERTER 15.5.1 Example of EI2OS Activation in Single Mode Starting EI2OS in single mode • To terminate conversion after analog inputs AN1 to AN3 are converted • To transfer conversion data sequentially to addresses 200H to 205H • To start conversion by software • To use the highest interrupt level ■ Example of EI2OS Activation in Single Mode Settings Sample program MOV ICR10, #08H Function Specifies the highest interrupt level, EI2OS activation upon an interrupt, and the descriptor address. MOV BAPL, #00H MOV BAPM, #02H Specifies the transfer destination address of converted data. MOV BAPH, #00H EI2OS setting MOV ISCS, #18H Specifies word data transfer. The transfer destination address is incremented after transfer. Data is transferred from I/O to memory. Transfer is not terminated in response to a request from a resource. MOV IOA, #36H Transfer source address MOV DCT, #03H EI2OS transfer is performed three times. This count is the same as the conversion count. MOV ADCS0, #0BH Specifies single mode, start channel AN1, and end channel AN3. MOV ADCS1, #A2H Specifies activation by software and start of A/D conversion. RETI Specifies return from an interrupt. A/D converter setting Interrupt sequence 202 • ICR10: Interrupt control register • BAPL: Buffer address pointer, low-order • BAPM: Buffer address pointer, medium-order • BAPH: Buffer address pointer, high-order • ISCS: EI2OS status register • IOA: I/O address counter • DCT: Data counter CHAPTER 15 A/D CONVERTER Activation AN1 → Interrupt → EI2OS transfer AN2 → Interrupt → EI2OS transfer AN3 → Interrupt → EI2OS transfer EndInterrupt sequence Parallel processing 203 CHAPTER 15 A/D CONVERTER 15.5.2 Example of EI2OS Activation in Continuous Mode Starting EI2OS in continuous mode • To convert analog inputs AN3 to AN5 and obtain two conversion data items for each channel • To transfer conversion data sequentially to addresses 600H to 60BH • To start conversion by external edge input • To use the highest interrupt level ■ Example of EI2OS Activation in Continuous Mode Settings Sample program MOV ICR10, #08H Function Specifies the highest interrupt level, EI2OS activation upon an interrupt, and the descriptor address. MOV BAPL, #00H MOV BAPM, #06H Specifies the transfer destination address of converted data. MOV BAPH, #00H EI2OS setting MOV ISCS, #18H Specifies word data transfer. The transfer destination address is incremented after transfer. Data is transferred from I/O to memory. Transfer is not terminated in response to a request from a resource. MOV IOA, #36H Transfer source address MOV DCT, #06H EI2OS transfer is performed six times. Data is transferred for three channels × 2. MOV ADCS0, #9DH Specifies continuous mode, start channel AN3, and end channel AN5. MOV ADCS1, #A4H Specifies activation by external edge and start of A/D conversion. A/D converter setting Interrupt sequence 204 MOV ADCS1, #00H Specifies return from an interrupt. RETI • ICR10: Interrupt control register • BAPL: Buffer address pointer, low-order • BAPM: Buffer address pointer, medium-order • BAPH: Buffer address pointer, high-order • ISCS: EI2OS status register • IOA: I/O address counter • DCT: Data counter CHAPTER 15 A/D CONVERTER Activation AN3 → Interrupt → EI2OS transfer AN4 → Interrupt → EI2OS transfer After six transfers Interrupt sequence AN5 → Interrupt → EI2OS transfer End 205 CHAPTER 15 A/D CONVERTER 15.5.3 Example of EI2OS Activation in Stop Mode Starting IE2OS in stop mode • To convert analog input AN3 12 times at fixed intervals • To transfer conversion data sequentially to addresses 600H to 617H • To start conversion by external edge input • To use the highest interrupt level ■ Example of EI2OS Activation in Stop Mode Settings Sample program MOV ICR10, #08H Function Specifies the highest interrupt level, EI2OS activation upon an interrupt, and the descriptor address. MOV BAPL, #00H MOV BAPM, #06H Specifies the transfer destination address of converted data. MOV BAPH, #00H EI2OS setting MOV ISCS, #18H Specifies word data transfer. The transfer destination address is incremented after transfer. Data is transferred from I/O to memory. Transfer is not terminated in response to a request from a resource. MOV IOA, #36H Transfer source address MOV DCT, #0CH EI2OS transfer is performed 12 times. MOV ADCS0, #DBH Specifies stop mode, start channel AN3, and end channel AN3 (one-channel conversion). MOV ADCS1, #A4H Specifies activation by external edge and start of A/D conversion. A/D converter setting Interrupt sequence 206 MOV ADCS1, #00H Specifies return from an interrupt. RETI • ICR10: Interrupt control register • BAPL: Buffer address pointer, low-order • BAPM: Buffer address pointer, medium-order • BAPH: Buffer address pointer, high-order • ISCS: EI2OS status register • IOA: • DCT: Data counter I/O address counter CHAPTER 15 A/D CONVERTER Activation AN3 → Interrupt → EI2OS transfer After 12 transfers Stop Activation by external edge Interrupt sequence End 207 CHAPTER 15 A/D CONVERTER 15.6 Conversion Data Protection The A/D converter has a conversion data protection function that enables continuous conversion and preservation of multiple data items using EI2OS. Since there is only one conversion data register, its value is updated each time conversion is completed. Thus, continuous data conversion results in the loss of the previous data due to storage of the new data. To prevent this situation, the A/D converter pauses after conversion if the previous data item has not been transferred to memory by EI2OS. The converted data is not saved until the previous data is transferred to memory. ■ Conversion Data Protection The pause is released after data is transferred to memory by EI2OS. If the previous data has been transferred to memory, the A/D converter continues operation without pausing. Note: This function is related to the INT and INTE bits of ADCS2. The data protection function operates only when interrupts are enabled (INTE=1). If interrupts are disabled (INTE=0), this function is disabled. Continuous A/D conversion results in loss of previous data, since the converted data items are saved to the register one after another. If EI2OS is not used while interrupts are enabled (INTE=1), the INT bit is not cleared. Thus, the data protection function works and the A/D converter pauses. In this case, clearing the INT bit in the interrupt sequence releases the pause. If the A/D converter is pausing during EI2OS operation, disabling interrupts may restart the A/D converter. In this case, the value in the conversion data register may be changed without being transferred. Restarting the A/D converter while it is pausing destroys the standby data. 208 CHAPTER 15 A/D CONVERTER ■ Flow of Data Protection Function (When EI2OS is Used) Setting EI 2OS The flow while A/D converter is stopped is omitted. Starting continuous A/D conversion * : Restarting the converter while paused destroys the standby conversion data. Ending first conversion Saving the result in the data register Starting EI 2OS Ending second conversion NO End EI2OS? Pausing A/D conversion * YES Saving the result in the data register YES End EI 2OS? NO Starting EI 2 OS Ending third conversion Continued Starting EI 2 OS Ending the last conversion Interrupt routine End Stooping A/D conversion ■ Notes on Use To start the A/D converter upon an external trigger or internal timer, A/D activation factor bits STS1 and STS0 of the ADCS2 register are used. Ensure that the input values of the external trigger or internal timer are inactive. If the values are active, A/D conversion may start immediately. When setting STS1 and STS0, ensure that "1" (input) is specified for ADTG and "0" (output) is specified for the internal timer (timer 2). 209 CHAPTER 15 A/D CONVERTER 210 CHAPTER 16 UART0 CHAPTER 16 UART0 This chapter explains the UART0 functions and operation. 16.1 "UART0" 16.2 "Block Diagram of UART0" 16.3 "Registers of UART0" 16.4 "Operations of UART0" 16.5 "Baud Rate" 16.6 "Internal and External Clock" 16.7 "Transfer Data Format" 16.8 "Parity Bit" 16.9 "Interrupt Generation and Flag Set Timings" 16.10 "UART0 Application Example" 211 CHAPTER 16 UART0 16.1 UART0 UART0 is a serial I/O port for synchronous or asynchronous communications with external devices. ■ UART0 UART0 has the following features. 212 • Full duplex double buffer • Supports CLK synchronous and CLK asynchronous start-stop data transfer. • Multiprocessor mode support (mode 2) • Internally dedicated baud rate generator (12 types) • Supports flexible baud rate setting using an external clock input or internal timer. • Variable data length (7 to 9 bits, [no parity]; 6 to 8 bits [with parity]). • Error detect function (framing, overrun, and parity) • Interrupt function (receive and transmit interrupts) • NRZ type transfer format CHAPTER 16 UART0 16.2 Block Diagram of UART0 Figure 16.2-1 is a UART0 block diagram. ■ Block Diagram of UART0 Figure 16.2-1 Overall Block Diagram CONTROL BUS Receive interrupt (to CPU) Dedicated baud rate clock SCK0 Transmit clock 16-bit reload timer 0 Clock select circuit Transmit interrupt (to CPU) Receive clock SCK0 SIN0 Receive control circuit Transmit control circuit Start bit detect circuit Transmit start circuit Receive bit counter Transmit bit counter Receive parity counter Transmit parity counter SOT0 Receive status evaluation circuit Transmit shifter Receive shifter Receive complete Transmit start UIDR0 UODR0 Receive error indication signal for EI2OS (to CPU) Data bus UMC0 register PEN SBL MC1 MC0 SMDE RFC SCKE SOE USR0 register RDRF ORFE PE TDRE RIE TIE RBF TBF URD0 register BCH RC3 RC2 RC1 RC0 BCH0 P D8 CONTROL BUS 213 CHAPTER 16 UART0 16.3 Registers of UART0 The UART0 has the following four registers: • Serial mode control register • Status register • Input data/output data register • Rate and date register ■ Registers of UART0 Serial mode control register 0 Address: 000020H Read/write Initial value Status register 0 Address: 000021H Read/write Initial value 7 6 5 4 3 2 1 PEN SBL MC1 MC0 SMDE RFC SCKE SOE (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (W) (1) (R/W) (0) (R/W) (0) 15 14 13 12 11 10 9 8 RDRF ORFE PE TDRE RIE TIE RBF TBF (R) (0) (R) (0) (R) (1) (R/W) (0) (R/W) (0) (R) (0) (R) (0) (R) (0) Input data register 0/ Output data register 0 Address: Read/write Initial value Address: W R X 214 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) 14 13 12 11 10 9 8 000023H BCH RC3 RC2 RC1 RC0 BCH0 P D8 Read/write Initial value (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (X) : Write only : Read only : Undefined Bit number UIDR0(read) UODR0(write) (R/W) (X) 15 R/W : Readable/Writable UMC0 USR0 6 (R/W) (X) Bit number Bit number 7 000022H Rate and data register 0 0 Bit number URD0 CHAPTER 16 UART0 16.3.1 Serial Mode Control Register 0 (UMC0) UMC0 specifies the operation mode of UART0. Set the operation mode while operation is halted. However, the RFC bit can be accessed during operation. ■ Serial Mode Control Register 0 (UMC0) Serial mode control register 0 bit Address: 000020H Read/write Initial value 7 6 5 4 3 2 1 0 PEN SBL MC1 MC0 SMDE RFC SCKE SOE (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (W) (1) (R/W) (0) (R/W) (0) UMC0 R/W : Readable/Writable W : Write only ❍ Contents of Serial Mode Control Register 0 (UMC0) [bit7] PEN (Parity enable) Specifies whether to add (for transmit) or detect (for receive) a parity bit in serial data I/O. Set to "0" in mode 2. 0: Do not use parity 1: Use parity [bit6] SBL (Stop bit length) Specifies the number of stop bits for transmit data. For receive data, the first stop bit only is recognized and any second stop bit is ignored. 0: 1 bit length 1: 2 bits length 215 CHAPTER 16 UART0 [bit5, bit4] MC1, MC0 (Mode control) These bits control the length of the transferred data. Table 16.3-1 lists the four transfer modes (data lengths) selectable by these bits. Table 16.3-1 UART0 Operation Modes Mode MC1 MC0 Data Length *1 0 0 0 7 (6) 1 0 1 8 (7) 2*2 1 0 8+1 3 1 1 9 (8) *1: Each figure in parentheses indicates the data length with parity. *2: Mode 2 is used when a number of slave CPUs are connected to a single host CPU. As the receive parity check function cannot be used, set PEN in the UMC0 register to "0" (see Section 16.4 "Operations of UART0" for details). The transmit data length is 9 bits and no parity bit can be added. [bit3] SMDE (Synchro mode enable) This bit selects the transfer method. 0: Start-stop CLK synchronous transfer (clocked synchronous transfer using start and stop bits.) 1: Start-stop CLK asynchronous transfer [bit2] RFC (Receiver flag clear) Writing "0" to this bit clears the RDRF, ORFE, and PE flags in the USR0 register. Writing "1" has no effect. Reading always returns "1". Note: When receive interrupts are enabled during UART0 operation, only write "0" to RFC when either RDRF, ORFE, or PE is "1". [bit1] SCKE (SCLK enable) Writing "1" to this bit in CLK synchronous mode switches the port pin to the UART0 serial clock output pin and outputs the synchronizing clock. Set to zero in CLK asynchronous mode or external clock mode. 0: The pin functions as a general purpose I/O port and does not output the serial clock. The pin functions as the external clock input pin when the port is set to input mode (DDR=0) and RC3 to 0 are set to "1111". 1: The pin functions as the UART0 serial clock output pin. [bit0] SOE (Serial output enable) Writing "1" to this bit switches the port pin to the UART0 serial data output pin and enables serial output. 0: The pin functions as a port pin and does not output serial data. 1: The pin functions as the UART0 serial data output pin (SOT). 216 CHAPTER 16 UART0 16.3.2 Status Register 0 (USR0) USR0 indicates the current state of the UART0 port. ■ Status Register 0 (USR0) Status register 0 Address: bit 000021H Read/write Initial value 15 14 13 12 11 10 9 8 RDRF ORFE PE TDRE RIE TIE RBF TBF (R) (0) (R) (0) (R) (1) (R/W) (0) (R/W) (0) (R) (0) (R) (0) (R) (0) USR0 R/W : Readable/Writable R : Read only ❍ Contents of Status Resister (USR0) [bit15] RDRF (Receiver data register full) This flag indicates the state of the UIDR0 (input data register 0). The flag is set when the receive data is loaded into UIDR0. Reading UIDR0 or writing "0" to RFC in the UMC0 register clears the flag. If RIE is active, a receive interrupt request is generated when RDRF is set. 0: No data in UIDR0 1: Data present in UIDR0 [bit14] ORFE (Over-run/framing error) The flag is set when an overrun or framing error occurs in receiving. Writing "0" to RFC in the UMC0 register clears the flag. When this flag is set, the data in UIDR0 is invalid and the load from the receive shifter to UIDR0 is not performed. If RIE is active, a receive interrupt request is generated when ORFE is set. 0: No error 1: Error Table 16.3-2 lists the UIDR0 states after receive completion by RDRF or ORFE. Table 16.3-2 UIDR0 State after Receive Completion RDRF ORFE UIDR0 Data State 0 0 Empty 0 1 Framing error 1 0 Valid data 1 1 Overrun error The data in UIDR0 is invalid if an overrun or framing error has occurred. Next data can be received after clearing the flag(s). 217 CHAPTER 16 UART0 [bit13] PE (Parity error) The flag is set when a receive parity error occurs. Writing "0" to RFC in the UMC0 register clears the flag. When this flag is set, the data in UIDR0 is invalid and the load from the receive shifter to UIDR0 is not performed. If RIE is active, a receive interrupt request is generated when PE is set. 0: No parity error 1: Parity error [bit12] TDRE (Transmit data register empty) This flag indicates the state of the UODR0 (output data register 0). Writing transmit data to the UODR0 register clears the flag. The flag is set when the data is loaded to the transmit shifter and the transmission is started. If TIE is active, a transmit interrupt request is generated when TDRE is set. 0: Data present in UODR0 1: No data in UODR0 [bit11] RIE (Receiver interrupt enable) Enables receive interrupt requests. 0: Disable interrupts. 1: Enable interrupts. [bit10] TIE (Transmit interrupt enable) Enables transmit interrupt requests. A transmit interrupt is generated immediately if transmit interrupts are enabled when TDRE is "1". 0: Disable interrupts. 1: Enable interrupts. [bit9] RBF (Receiver busy flag) This flag indicates that UART0 is receiving input data. The flag is set when the start bit is detected and cleared when the stop bit is detected. 0: Receiver idle 1: Receiver busy [bit8] TBF (Transmitter busy flag) This flag indicates that UART0 is transmitting input data. The flag is set when transmit data is written to the UODR0 register and cleared when transmission completes. 0: Transmitter idle 1: Transmitter busy 218 CHAPTER 16 UART0 16.3.3 Input Data Register 0 (UIDR0) and Output Data Register 0 (UODR0) UIDR0 (input data register 0) is the serial data input register. UODR0 (output data register 0) is the serial data output register. The most significant two bits (D7 and D6) are ignored if the data length is 6 bits and the most significant bit (D7) is ignored if the data length is 7 bits. Write to UODR0 only when TDRE = 1 in the USR0 register. Read UIDR0 only when RDRF = 1 in the USR0 register. ■ Input Data Register 0 (UIDR0) and Output Data Register 0 (UODR0) Input data register 0/ Output data register 0 Address: bit 000022H Read/write Initial value 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) UIDR0 (read) UODR0 (write) (R/W) (X) R/W : Readable/Writable X : Undefined 219 CHAPTER 16 UART0 16.3.4 Rate and Data Register 0 (URD0) URD0 selects the data transfer speed (baud rate) for UART0. The register also holds the most significant bit (bit 8) of the data when the transmit data length is 9 bits. Set the baud rate and parity when UART0 is halted. ■ Rate and Data Register 0 (URD0) Rate and data register 0 Address: bit 15 14 13 12 11 10 9 8 000023H BCH RC3 RC2 RC1 RC0 BCH0 P D8 Read/write Initial value (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (X) URD0 R/W : Readable/Writable X : Undefined ❍ Contents of Rate and Data Register 0 (URD) [bit15, bit10] BCH, BCH0 (Baud rate clock change) Specifies the machine cycles for the baud rate clock (see Section "16.4 Operations of UART0" for details). Table 16.3-3 Clock Input Selection BCH BCH0 Divider ratio 0 0 — 0 1 Divide by 4 For a 16-MHz machine cycle: 16/4 = 4 MHz 1 0 Divide by 3 For a 12-MHz machine cycle: 12/3 = 4 MHz 1 1 Divide by 5 For a 10-MHz machine cycle: 10/5 = 2 MHz Note: Do not set BCH and BCH0 to "00". 220 Setting Example for Each Machine Cycle Prohibited setting CHAPTER 16 UART0 [bit14 to bit11] RC3 to RC0 (Rate control) Selects the clock input for the UART0 port (see Section "16.4 Operations of UART0" for details). Table 16.3-4 Clock Input Selection RC3 to RC0 "0000" to "1011" Clock Input Dedicated baud rate generator "1101" 16-bit Reload Timer 0 "1111" External clock Note: Do not set the rate control bits to "1100" "1110". [bit9] P (Parity): Sets even or odd parity when parity is active (PEN = 1). 0: Even parity 1: Odd parity [bit8] D8 Holds the bit 8 of the transfer data in mode 2 or 3 (9-bit data length) and no parity. Treated as bit 8 of the UIDR0 register for reading. Treated as bit 8 of the UODR0 register for writing. The bit has no meaning in the other modes. Write to D8 only when TDRE = 1 in the USR0 register. 221 CHAPTER 16 UART0 16.4 Operations of UART0 Table 16.4-1 lists the operating modes for UART0. Set the UMC0 register to switch between modes. ■ Operating Modes of UART0 Table 16.4-1 UART0 Operating Modes Mode Parity Data Length On 6 Off 7 On 7 Off 8 Off 8+1 On 8 Off 9 Clock Mode Length of Stop Bits 0 1 2 CLK asynchronous or CLK synchronous 1 bit or 2 bits 3 The number of stop bits can only be set for transmission. The number of receive stop bits is always set to one. Do not set modes other than those listed above. UART0 does not operate if an invalid mode is set. Note: UART0 uses start-stop clock synchronous transfer. Therefore, a start and stop bit are added to the data even in clock synchronous transfer. 222 CHAPTER 16 UART0 16.5 Baud Rate When the dedicated baud rate generator is used, the following two types of baud rates are available: • CLK synchronous baud rate • CLK asynchronous baud rate ■ CLK Synchronous Baud Rate The five bits of URD0 register : BCH, BCH0 and RC3, RC2, RC1 select the baud rate for CLK synchronous transfer. First select the machine clock divider ratio using BCH and BCH0. BCH BCH0 0 1 ⇒ Divide by 4 [For example, at 16 MHz: 16/4 = 4 MHz] 1 0 ⇒ Divide by 3 [For example, at 12 MHz: 12/3 = 4 MHz] 1 1 ⇒ Divide by 5 [For example, at 10 MHz: 10/5 = 2 MHz] Then, set the division ratio for the clock selected above in RC3, RC2, and RC1. The following three settings are available for CLK synchronous transfer. Other settings are prohibited. RC3 RC2 RC1 0 1 0 ⇒ Divide by 2 [For example, at 4 MHz: 4/2 = 2.0 M (bps)] 0 1 1 ⇒ Divide by 4 [For example, at 4 MHz: 4/4 = 1.0 M (bps)] 1 0 0 ⇒ Divide by 8 [For example, at 4 MHz: 4/8 = 0.5 M (bps)] (At 2 MHz, the speed becomes half the above examples.) ■ CLK Asynchronous Baud Rate The six bits of URD0 register : BCH, BCH0 and RC3, RC2, RC1, RC0 select the baud rate for CLK asynchronous transfer. First select the machine clock divider ratio using BCH and BCH0. BCH BCH0 0 1 ⇒ Divide by 4 [For example, at 16 MHz: 16/4 = 4 MHz] 1 0 ⇒ Divide by 3 [For example, at 12 MHz: 12/3 = 4 MHz] 1 1 ⇒ Divide by 5 [For example, at 10 MHz: 10/5 = 2 MHz] Then, set the asynchronous transfer clock division ratio for the clock selected above in RC3, RC2, RC1, and RC0. The following settings are available. 223 CHAPTER 16 UART0 0 0 0 ⇒ Divide by 8 × 1 0 1 0 ⇒ Divide by 8 × 2 0 1 1 ⇒ Divide by 8 × 4 1 0 0 ⇒ Divide by 8 × 8 0 0 1 ⇒ Not divided 1 0 1 ⇒ Divide by 8 ⎧ ⎪ ⎪ ⎨ ⎪ ⎩ ⎧ ⎪ ⎨ ⎪ ⎪ ⎩ RC0 × × ⎧ ⎪ ⎨ 0 ⇒ Divide by 12 ⎪ 1 ⇒ Divide by 13 ⎪ ⎩ ⎧ ⎪ ⎪ ⎨ ⎪ ⎩ RC3 RC2 RC1 0 ⇒ Prohibited setting 1 ⇒ Divide by 8 The above 12 baud rates can be selected. The following formula shows how to calculate the CLK synchronous baud rate. Baud rate = φ/4 [bps] (machine cycle = 16 MHz) 2m-1 Baud rate = φ/3 [bps] (machine cycle = 12 MHz) 2m-1 Baud rate = φ/5 [bps] (machine cycle = 10 MHz) 2m-1 where φ is a machine cycle and m is in decimal notation for RC3 to 1. Note: The above formula for m=0 or m=1 cannot be calculated. Data transfer is possible if the CLK asynchronous baud rate is in the range -1% to +1%. The baud rate is the CLK synchronous baud rate divided by 8 × 13, 8 × 12, or 8. Table 16.5-1 shows examples for 16 MHz, 12 MHz, and 10 MHz machine cycles. However, do not use the settings marked as "_" in the table. 224 CHAPTER 16 UART0 Table 16.5-1 Baud Rate CLK asynchronous (µs/Baud) RC3 RC2 RC1 RC0 16 MHz 12 MHz 10 MHz BCH/ BCH0=01 BCH/ BCH0=10 BCH/ BCH0=11 CLK asynchronous divider ratio CLK synchronous (µs/Baud) 16 MHz 12 MHz 10 MHz BCH/ BCH0=01 BCH/ BCH0=10 BCH/ BCH0=11 0 0 0 0 - - 48 / 20833 8 x 12 - - - 0 0 0 1 26 / 38460 26/ 38460 52 / 19230 8 x 13 - - - 0 0 1 0 - - - 8 - - - 0 0 1 1 2 / 500000 2 / 500000 4 / 250000 8 - - - 0 1 0 0 48 / 20833 48 / 20833 96 / 10417 8 x 12 - - - 0 1 0 1 52 / 19230 52 / 19230 104 / 9615 8 x 13 0.5 / 2M 0.5 / 2M 1 / 1M 0 1 1 0 96/10417 96/10417 192/ 5208 8 x 12 - - - 0 1 1 1 104/ 9615 104/ 9615 208/ 4808 8 x 13 1 / 1M 1 / 1M 2 / 500k 1 0 0 0 192 / 5208 192 / 5208 - 8 x 12 - - - 1 0 0 1 208 / 4808 208 / 4808 416 / 2404 8 x 13 2 / 500k 2 / 500k 4 / 250k 1 0 1 0 - - - 8 - - - 1 0 1 1 16 / 62500 16 / 62500 32 / 31250 8 - - - 225 CHAPTER 16 UART0 16.6 Internal and External Clock Setting RC3 to 0 to "1101" selects the clock signal from the 16-bit Reload Timer. Setting RC3 to 0 to "1111" selects the external clock. The external clock frequency has a maximum value of 2 MHz. ■ Internal and External Clock The CLK asynchronous baud rate is the CLK synchronous baud rate divided by 8. Also, data transfer is possible if the CLK asynchronous baud rate is in the range -1% to +1% of the selected baud rate. Table 16.6-1 lists the baud rates when the internal timer is selected as the clock. The values in this table are calculated for a machine cycle of 7.3728 MHz. However, do not use the settings marked as ‘_‘ in the table. Baud rate= φ/X 8 × 2 (n+1) [bps] ⎛ φ: Machine cycle ⎜ ⎜ X: Divider ratio for the count clock source for ⎜ the internal timer ⎜ ⎝ n: Reload value (decimal) ⎞ ⎟ ⎟ ⎟ ⎟ ⎠ Table 16.6-1 Baud Rate and Reload Value Reload Value Baud Rate (bps) X = 21 (divide machine cycle by 2) X = 23 (divide machine cycle by 8) 76800 2 — 38400 5 — 19200 11 2 9600 23 5 4800 47 11 2400 95 23 1200 191 47 600 383 95 300 767 191 The values in the table are the reload values (decimal) for reload count operation of the 16-bit Reload Timer. 226 CHAPTER 16 UART0 16.7 Transfer Data Format UART0 only handles NRZ (non-return-to-zero) type data. Figure 16.7-1 shows the relationship between the transmit/receive clock and the data for CLK synchronous mode. ■ Transfer Data Format Figure 16.7-1 Transfer Data Format SCK0 SIN0, SOT0 0 Start 1 LSB 0 1 1 0 1 0 0 1 1 ⎫ MSB Stop Depends D8 Stop ⎬ on the mode. ⎭ The transferred data is 01001101B (mode 1) or 101001101B (mode 3). As shown in Figure 16.7-1 , the transfer data always starts with the start bit ("L" level data), the specified number of data bits are transmitted with the LSB first, then transmission ends with the stop bit ("H" level data). Always input a clock if external clock operation is selected. When an internal clock (the dedicated baud rate generator or 16-bit Reload Timer) is selected, the clock is output continuously. When using CLK synchronous transfer, do not start data transfer until the selected baud rate clock has stabilized (for two baud rate clock cycles). When using CLK asynchronous transfer, set the SCKE bit in the UMC0 register to "0" to disable clock output. The transfer data format of SIN0 and SOT0 is the same as shown in Figure 16.7-1 . 227 CHAPTER 16 UART0 16.8 Parity Bit The P bit in the URD0 register specifies whether to use even or odd parity when parity is enabled. The PEN bit in the UMC0 register enables parity. ■ Parity Bit Inputting the data shown in Figure 16.8-1 to SIN0 when even parity is set causes a receive parity error. Figure 16.8-1 also shows the data transmitted when sending 001101B with even parity and odd parity. Figure 16.8-1 Serial Data with Parity Enabled SIN0 (Receive parity error occurs P = 0) 0 Start 1 LSB 0 1 1 0 0 MSB 0 1 Stop (Parity) SOT0 (Even parity transmission P = 0) 0 Start 1 LSB 0 1 1 0 0 MSB 1 1 Stop (Parity) SOT0 (Odd parity transmission P = 1) 0 Start 1 LSB 0 1 1 0 0 MSB 0 (Parity) 228 1 Stop CHAPTER 16 UART0 16.9 Interrupt Generation and Flag Set Timings The UART0 has two interrupt causes and six flags. The two interrupt causes are receive interrupt and send interrupt. The six flags are RDRF, ORFE, PE, TDRE, RBF, and TBF. The RDRF, ORFE, or PE flag requests an interrupt for receiving data, and the TDRE flag requests an interrupt for sending data. ■ Set Timing of Six Flags ❍ RDRF Flag RDRF is set when receive data is loaded into the UIDR0 register. Writing "0" to RFC in the UMC0 register or reading UIDR0 clears RDRF. ❍ ORFE Flag ORFE is the overrun or framing error flag. The flag is set when a receive error occurs. Writing "0" to RFC in the UMC0 register clears ORFE. ❍ PE Flag PE is the parity error flag. The flag is set when a receive parity error occurs. Writing "0" to RFC in the UMC0 register clears PE. Note that the parity detect function is not available in mode 2. ❍ TDRE Flag TDRE is set when the UODR0 register becomes empty and available for writing. Writing to the UODR0 register clears TDRE. The above four flags (RDRF, ORFE, PE, and TDRE) trigger transmit or receive interrupts. ❍ RBF and TBF Flags The RBF and TBF flags indicate that reception or transmission is in progress. RBF is active during reception. TBF is active during transmission. 229 CHAPTER 16 UART0 16.9.1 Flag Setting Timing in Receive Mode (Mode 0, Mode 1, Or Mode 3) The RDRF, ORFE, and PE flags are set and an interrupt request to the CPU generated when the final stop bit is detected indicating the end of reception transfer. The data in UIDR0 is invalid when either the ORFE or PE bit is active. ■ Flag Setting Timing in Receive Mode (Mode 0, Mode 1, or Mode 3) Figure 16.9-1 , Figure 16.9-2 , and Figure 16.9-3 are the timing charts for setting the RDRF, ORFE, and PE flags. Figure 16.9-1 RDRF Set Timing (Mode 0, 1, or 3) Data Stop (Stop) RDRF Receive interrupt Figure 16.9-2 ORFE Set Timing (Mode 0, 1, or 3) Data Stop Data RDRF = 1 RDRF = 0 ORFE ORFE Receive interrupt Stop Receive interrupt (Overrun error) (Framing error) Figure 16.9-3 PE Set Timing (Mode 0, 1, or 3) Data PE Receive interrupt 230 Stop (Stop) CHAPTER 16 UART0 16.9.2 Flag Setting Timing in Receive Mode (mode 2) The RDRF flag is set when the final stop bit is detected and reception transfer ends with the last data bit (D8) having the value "1". The ORFE flag is set when the final stop bit is detected, irrespective of the value of the last data bit (D8). The data in UIDR0 is invalid when the ORFE bit is active. The interrupt request to the CPU is generated when either of the flags are set (see Section 16.10 "UART0 Application Example" for details on using mode 2). ■ Flag Setting Timing in Receive Mode (mode 2) Figure 16.9-4 RDRF Set Timing (Mode 2) Data D6 D7 Stop D8 (Stop) RDRF Receive interrupt Figure 16.9-5 ORFE Set Timing (Mode 2) Data D7 D8 Stop Data RDRF = 1 RDRF = 0 ORFE ORFE Receive interrupt D7 D8 Stop Receive interrupt (Overrun error) (Framing error) 231 CHAPTER 16 UART0 16.9.3 Flag Setting Timing in Send Mode TDRE is set and an interrupt request to the CPU is generated when the data written in UODR0 register is transferred to the internal shift register and the next data can be written to UODR0. ■ Flag Setting Timing in Send Mode Figure 16.9-6 TDRE Set Timing (Mode 0) UODR0 write TDRE Interrupt request to the CPU Transmit interrupt SOT0 output ST ST: Start bit 232 D0 D1 D2 D3 D4 D5 D6 D7 SP SP D0 to D7: Data bits SP: Stop bit ST D0 D1 D2 D3 CHAPTER 16 UART0 16.9.4 Status Flag in Transmit/receive Mode RBF is set when the start bit is detected and cleared when a stop bit is detected. The receive data in UIDR0 at the RBF clear timing is not yet valid. The data in UIDR0 becomes valid at the RDRF set timing. ■ Status Flag in Transmit/receive Mode Figure 16.9-7 shows the relationship between the RBF and receive interrupt flag timing. Figure 16.9-7 RBF Set Timing (Mode 0) SIN0 input ST D0 D1 D2 D3 D4 D5 D6 D7 SP RBF RDRF, PE, ORFE D0 to D7: Data bits ST: Start bit SP: Stop bit Writing the transmission data to UODR0 sets TBF. TBF is cleared when transmission completes. Figure 16.9-8 TBF Set Timing (Mode 0) UODR0 write ST SOT0 output D0 D1 D2 D3 D4 D5 D6 D7 SP SP TBF ST: Start bit D0 to D7: Data bits SP: Stop bit Note: Receive operation starts after releasing a reset unless the SIN0 input pin is fixed at "1". Therefore, before setting the mode, write "0" to RFC in the UMC0 register to clear any receive flags that have been set. Set the communication mode when the RBF and TBF flags in the USR0 register are "0". The data transmitted and received during mode setting cannot be guaranteed. EI2OS (Extended intelligent I/O service) See the Section "3.7 Extended Intelligent I/O Service (EI2OS)" for details on EI2OS. 233 CHAPTER 16 UART0 16.10 UART0 Application Example Mode 2 is used when a number of slave CPUs are connected to a host CPU (see Figure 16.10-1 ). ■ UART0 Application Example Figure 16.10-1 RBF Set Timing (Mode 0) SIN0 input ST D0 D1 D2 D3 D4 D5 D6 D7 SP RBF RDRF, PE, ORFE ST: Start bit D0 to D7: Data bits SP: Stop bit ST: Start bit, D0 - D7: Data bits, SP: Stop bit Communication starts with the host CPU transmitting address data. Address data has the ninth bit (D8) set to "1". The address selects the slave CPU with which to communicate. The selected slave CPU communicates with the host CPU using a protocol determined by the user. Normal data has D8 set to "0". Unselected slave CPUs wait in standby until the next communication session starts. Figure 16.10-3 shows a flow chart of operation in this mode. As the parity check function is not available in this mode, set the PEN bit in the UMC0 register to "0". Figure 16.10-2 Example of System Configuration in Mode 2 SOT0 SIN0 Host CPU 234 SOT0 SIN0 SOT0 SIN0 Slave CPU #0 Slave CPU #1 CHAPTER 16 UART0 Figure 16.10-3 Communication Flowchart for Mode 2 Operation (Host CPU)(Slave CPU) Start Set the transfer mode to 3 Set the slave CPU selection in D0 to D7. Set D8 to “1”. Transfer the byte. Start Set the transfer mode to 2 Receive a byte Selected? Set D8 to “0” and perform communications End NO YES Set the transfer mode to 3 and enable SOT0 output Perform communications with the master CPU Use the status flag to confirm transfer completion, then set the transfer mode to 2 and disable SOT0 output 235 CHAPTER 16 UART0 236 CHAPTER 17 UART1 (SCI) CHAPTER 17 UART1 (SCI) This chapter explains the UART1 (SCI) functions and operation. 17.1 "Features of UART1" 17.2 "UART1 Block Diagram" 17.3 "UART1 Registers" 17.4 "UART1 Operating Modes and Clock Selection" 17.5 "UART1 Flags and Interrupt Sources" 17.6 "UART1 Interrupts and Flag Set Timing" 17.7 "UART1 Sample Applications and Precautionary Information" 237 CHAPTER 17 UART1 (SCI) 17.1 Features of UART1 The UART1 is a serial I/O port used for asynchronous (start-stop synchronized) communication as well as for CLK-synchronized communication. ■ Features of UART1 UART provides the following features. • Full-duplex double buffer • Asynchronous (start-stop synchronized) and CLK-synchronous communication capability • Multi-processor mode support • On-chip dedicated baud rate generator At internal machine clock speeds of 6, 8, 10, 12, 16MHz. 238 • Asynchronous: 9615/31250/4808/2404/1202 bps • CLK synchronous: 1M/500k/250k/125k/62.5 kbps • Automatic baud rate setting from external clock input or internal timer • Error detection function (parity, framing, overrun) • Transfer communication in NRZ transfer format • Intelligent I/O service support CHAPTER 17 UART1 (SCI) 17.2 UART1 Block Diagram Figure 17.2-1 shows the UART1 block diagram. ■ UART1 Block Diagram Figure 17.2-1 UART1 Block Diagram Control signals Receive interrupt (to CPU) Dedicated baud rate generator 16-bit reload timer 0 SCK1 Transmit clock Clock selector circuit Transmit interrupt (to CPU) Receive clock External clock SIN1 Receive control circuit Transmit control circuit Start bit detect circuit Transmit start circuit Receive bit counter Transmit bit counter Receive parity counter Transmit parity counter SOT1 Receive status decision circuit Receive shifter Transmit shifter Receive complete Transmit Start SIDR1 SODR1 EI2OSreceive error indication signal (to CPU) F2MC-16 BUS SMR1 register MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR1 register PEN P SBL CL A/D REC RXE TXE SSR1 register PE ORE FRE RDRF TDRE RIE TIE Control bus 239 CHAPTER 17 UART1 (SCI) 17.3 UART1 Registers Figure 17.3-1 lists the UART1 registers. ■ UART1 Registers Figure 17.3-1 UART1 Registers bit 15 8 7 0 SCR1 SMR1 (R/W) SSR1 SIDR1(R)/SODR1(W) (R/W) bit 7 Address: 000024 H MD1 – U1CDCR 8bit 8bit 6 MD0 5 CS2 4 CS1 3 CS0 2 Reseved (R/W) 1 SCKE 0 SOE Serial mode register 1 (SMR1) bit 15 Address: 000025H PEN 14 P 13 SBL 12 CL 11 A/D 10 REC 9 RXE 8 TXE Serial control register 1 (SCR1) bit Address: 000026H 7 D7 6 D6 5 D5 bit Address: 000027H 15 PE 14 ORE 13 FRE 4 D4 3 D3 12 11 RDRF TDRE 2 D2 1 D1 0 D0 10 – 9 RIE 8 TIE Serial input register 1 Serial output register 1 (SIDR1/SODR1) Serial status register 1 (SSR1) bit 7 Address: 000028H MD R/W : Readable/Writable 240 6 – 5 – 4 – 3 DIV3 2 DIV2 1 DIV1 0 DIV0 UART1 prescaler control register (U1CDCR) CHAPTER 17 UART1 (SCI) 17.3.1 Serial Mode Register 1 (SMR1) The serial mode register 1 (SMR1) sets the operating mode of the UART1. Operating mode settings should be entered when the unit is not in operation. Do not write to this register during operation. ■ Serial Mode Register 1 (SMR1) The SMR1 register has the following bit configuration. SMR1 bit Address: 000024H 7 6 MD1 MD0 R/W R/W : Readable/Writable R/W 5 CS2 R/W 4 3 2 1 0 CS1 CS0 Reseved SCKE SOE R/W R/W R/W R/W R/W Initial value 00000000B [bit7, bit6] MD1, MD0 (MoDe select) These bits select the UART1 operation mode, according to the settings listed in Table 17.3-1 . Table 17.3-1 Operating Mode Selections Mode MD1 MD0 Operating mode 0 0 0 Asynchronous (start-stop synchronized) normal mode 1 0 1 Asynchronous (start-stop synchronized) multiprocessor mode 2 1 0 CLK synchronous mode — 1 1 Prohibited Note: Mode 1, CLK-asynchronous multi-processor mode, is used when one host CPU is connected to multiple slave CPUs. This UART1 resource is not able to determine the data format of incoming data, and therefore in multi-processor mode supports only the master processor. Also, in this configuration the receive parity check function cannot be used, and therefore the PEN bit in the UMC1 register should be set to "0". 241 CHAPTER 17 UART1 (SCI) [bit5 to bit3] CS2 to CS0 (Clock Select) These bits select the baud rate clock source. The baud rate is determined at the same time as selection of the baud rate generator. Table 17.3-2 shows the clock input selection settings. Table 17.3-2 Clock Input Selection Settings CS2 to CS0 Clock input 000B to 100B Dedicated baud rate generator 101B Reserved 110B Internal timer 111B External clock When the internal timer is selected, the MB90595 series selects 16-bit reload timer 0 output. [bit2] Reserved Always write "0" to this bit. [bit1] SCKE (SCLK Enable) For communication in CLK synchronous mode (mode 2), this bit determines whether the SCK1 pin is used as a clock input pin or a clock output pin. In CLK asynchronous modes or external clock mode, this bit should be set to "0". 0: SCK1 pin functions as clock input pin 1: SCK1 pin functions as clock output pin Note: When the pin functions as a clock input, an external clock source must be selected. [bit0] SOE (Serial Output Enable) This bit determines whether external pins that also can be used as general purpose I/O port pins will function as serial output pins (SOT1) or as I/O port pins. 0: General purpose I/O port pin function 1: Serial data output pin (SOT1) function 242 CHAPTER 17 UART1 (SCI) 17.3.2 Serial Control Register 1 (SCR1) The serial control register (SCR1) register controls the transfer protocol used for serial transmission. ■ Serial Control Register 1 (SCR1) The SCR1 register has the following bit configuration. Figure 17.3-2 Serial Control Register (SCR1) SCR1 15 bit Address: 000025H PEN 14 P 13 SBL 12 CL 11 A/D 10 REC 9 RXE 8 TXE R/W R/W : Readable/Writable W : Write only R/W R/W R/W R/W W R/W R/W Initial value 00000100B [bit15] PEN (Parity Enable) This bit determines whether parity bits are attached to data in serial transmission. 0: No parity 1: Parity Note: Parity bit attachment is available only in asynchronous (start-stop synchronized) communications in normal mode (mode 0). In multi-processor mode (mode 1) and all CLKsynchronous communication (mode 2), no parity bits may be attached. [bit14] P (Parity) This bit selects even or odd parity for data communications in which a parity bit is used. 0: Even parity 1: Odd parity [bit13] SBL (Stop Bit Length) This bit sets the length of the stop bit that marks the frame end in asynchronous (start-stop synchronized) communication. 0: 1 stop bit 1: 2 stop bits [bit12] CL (Character Length) This bit sets the data length of one frame. 0: 7-bit data 1: 8-bit data Note: 7-bit data handling is available only in asynchronous (start-stop synchronized) communications in normal mode (mode 0). In multi-processor mode (mode 1) and all CLKsynchronous communication (mode 2), 8-bit data should be used. 243 CHAPTER 17 UART1 (SCI) [bit11] A/D (Address/Data) This bit determines the data format of transmit frames in asynchronous (start-stop synchronized) communication in multi-processor mode (mode 1). 0: Data frame 1: Address frame [bit10] REC (Receiver Error Clear) This bit clears the error flags (PE, ORE, FRE) in the SSR1 register. A write value of "1" is not valid, and the read value is "1" at all times. [bit9] RXE (Receiver Enable) This bit controls UART1 receiver operations. 0: Receiver operation prohibited 1: Receiver operation enabled Note: If receiver operation is prohibited while reception is in progress (while data is present in the receive shift register), the receiver will not stop operating until reception of the current frame is completed, and the data has been stored in the receive data buffer SIDR1 register. [bit8] TXE (Transmit Enable) This bit controls UART1 transmit operation. 0: Transmit operation prohibited 1: Transmit operation enabled Note: If transmit operation is prohibited while transmission is in progress (while data is being output from the transmit register), the transmitter will not stop operating until there is no more data remaining in the transmit data buffer SODR1 register. After data is written into the SODR1 register, wait for the time described in the following before writing "0". The wait time should be one sixteenth that of the baud rate when in clock asynchronous transfer mode, and equivalent to that of the baud rate when in clock synchronous transfer mode. 244 CHAPTER 17 UART1 (SCI) 17.3.3 Serial Input Data Register 1 (SIDR1) / Serial Output Data Register 1 (SODR1) These registers function as receive and transmit data buffer registers. ■ Serial Input Data Register 1 (SIDR1) / Serial Output Data Register 1 (SODR1) The SIDR1 and SODR1 registers have the following bit configuration. 7 6 5 1 0 Initial value D3 D2 D1 D0 Undefined R 3 D3 R 2 D2 R 1 D1 R 0 D0 Undefined W W W W 3 D5 D4 R 5 D5 R 4 D4 W D7 D6 bit SODR1 Address: 000026H R 7 D7 R 6 D6 W W W W R 2 4 SIDR1 bit Address: 000026H : Write only : Read only The serial input data register 1 (SIDR1) functions as a data buffer register for receiving serial data. The serial output data register 1 (SODR1) functions as a data buffer register for transmitting serial data. When using 7-bit data length, the top bit (D7) contains invalid data. Be sure the DTRE bit in the SSR1 register is set to "1" before writing to the SODR1 register. Note: Writing to these addresses refers to writing to the SODR1 register, and reading refers to reading from the SIDR1 register. 245 CHAPTER 17 UART1 (SCI) 17.3.4 Serial Status Register 1 (SSR1) The serial status register (SSR1) is composed of flags that indicate the operating status of the UART1. ■ Serial Status Register 1 (SSR1) The SSR1 register has the following bit configuration. SSR1 bit Address: 000027H 15 PE 14 ORE 13 FRE 12 RDRF R R R R R/W : Readable/Writable R : Read only : Undefined 11 TDRE R 10 – 9 RIE 8 TIE – R/W R/W Initial value 00001_00B [bit15] PE (Parity Error) This interrupt request flag is set when a parity error occurs during receive. Once set, this flag is cleared by writing "0" to the REC bit (bit 10) in the SCR1 register. When this bit is set, data in the SIDR1 register is invalid. 0: No parity error 1: Parity error occurred [bit14] ORE (Over Run Error) This interrupt request flag is set when an overrun error occurs during receive. Once set, this flag is cleared by writing "0" to the REC bit (bit 10) in the SCR1 register. When this bit is set, data in the SIDR1 register is invalid. 0: No overrun error 1: Overrun error occurred [bit13] FRE (Framing Error) This interrupt request flag is set when a framing error occurs during receive. Once set, this flag is cleared by writing "0" to the REC bit (bit 10) in the SCR1 register. When this bit is set, data in the SIDR1 register is invalid. 0: No framing error 1: Framing error occurred [bit12] RDRF (Receiver Data Register Full) This interrupt request flag is set to indicate that data is present in the SIDR1 register. This flag is set when receive data is loaded into the SIDR1 register, and is automatically cleared when the data is read from the SIDR1 register. 0: No receive data 1: Receive data present 246 CHAPTER 17 UART1 (SCI) [bit11] TDRE (Transmit Data Register Empty) This interrupt request flag is set to indicate that outgoing data can be written to the SODR1 register. This flag is cleared when outgoing data is written to the SODR1 register. It is then reset when the written data starts loading into the transmit shifter to indicate that the next data can be written to the SODR1 register. 0: Prohibits writing of send data 1: Enables writing of send data [bit9] RIE (Receiver Interrupt Enable) This bit controls receiver interrupts. 0: Interrupt prohibited 1: Interrupt enabled Note: Receiver interrupt sources include PE, ORE and FRE errors, as well as normal receive as indicated by the RDRF flag. [bit8] TIE (Transmit Interrupt Enable) This bit controls transmit interrupts. 0: Interrupt prohibited 1: Interrupt enabled Note: Transmit interrupt sources include transmission requests indicated by the TDRE flag. 247 CHAPTER 17 UART1 (SCI) 17.3.5 UART1 Prescaler Control Register (U1CDCR) The prescaler control register (U1CDCR) controls the machine clock frequency divider. The UART1 operating clock signal can be generated by dividing the machine clock signal pulse. The prescaler is designed to enable constant baud rates from a variety of machine clock speeds. The output from the prescaler is used by the I/O expanded serial interface. ■ UART1 Prescaler Control Register (U1CDCR) The U1CDCR register has the following bit configuration. 7 6 5 4 3 2 1 0 MD R/W R/W : Readable/Writable : Undefined – – – – – – DIV3 R/W DIV2 R/W DIV1 R/W DIV0 R/W U1CDCR bit Address: 000028H Initial value 0---1111 B [bit7] MD (Machine clock divide MoDe select) This bit enables the prescaler operation. 0: Prescaler stopped 1: Prescaler operating [bit3 to bit0] DIV3 to DIV0 (DIVide3 to DIVide0) These bits determine the division of the machine clock frequency as shown in Table 17.3-3 . Table 17.3-3 Machine Clock Division Ratios DIV3 to DIV0 Division ratio 1101B Divide by 3 1100B Divide by 4 1011B Divide by 5 1010B Divide by 6 1001B Divide by 7 1000B Divide by 8 Note: After changing the division ratio, allow an interval of two cycles for the clock frequency to stabilize before starting communication. 248 CHAPTER 17 UART1 (SCI) 17.4 UART1 Operating Modes and Clock Selection The UART1 has two types of operating mode, asynchronous mode and CLKsynchronous mode. Changes of mode are controlled by settings in the SMR1 register and SCR1 register. ■ UART1 Operating Modes Table 17.4-1 shows the UART1 operating modes. Table 17.4-1 UART1 Operating Modes Mode Parity bit Data length Y/N 7 Y/N 8 0 Operating mode Stop bit length Asynchronous (startstop synchronized) normal mode 1-bit or 2-bit 1 N 8+1 2 N 8 Asynchronous (startstop synchronized) multi-processor mode CLK synchronous mode N Note: In asynchronous (start-stop synchronized) normal mode, stop bit length can be set for outgoing transmission only. For receive, the setting is always 1-bit. The unit does not operate in modes other than those shown, and only these settings should be used. ■ UART1 Clock Selection ❍ Dedicated baud rate generator When the dedicated baud rate generator is selected, the baud rate settings listed in Table 17.4-2 and Table 17.4-3 are available. Also, prescaler settings are shown in Table 17.4-4 . Table 17.4-2 Baud Rates (Asynchronous Communication) CS2 CS1 CS0 Asynchronous (startstop synchronized) Calculation formula 0 0 0 9615 (φ / div) / (8×13×2) 0 0 1 4808 (φ / div) / (8× 3×22) 0 1 0 2404 (φ / div) / (8×13×23) 0 1 1 1202 (φ / div) / (8×13×24) 1 0 0 31250 (φ / div) / 26 249 CHAPTER 17 UART1 (SCI) Table 17.4-3 Baud Rates (CLK-synchronized Communication) CS2 CS1 CS0 CLK - sychronized Calculation formula 0 0 0 1M (φ / div) / 2 0 0 1 500 K (φ / div) / 22 0 1 0 250 K (φ / div) / 23 0 1 1 125 K (φ / div) / 24 1 0 0 62.5 K (φ / div) / 25 Table 17.4-4 Prescaler Settings 250 MD DIV3 DIV2 IDV1 DIV0 div Recommended machine clock speed 1 1 1 0 1 3 6 MHz 1 1 1 0 0 4 8 MHz 1 1 0 1 1 5 10 MHz 1 1 0 1 0 6 12 MHz 1 1 0 0 0 8 16 MHz CHAPTER 17 UART1 (SCI) ❍ Internal timer When bits CS2-0 are set to "110", the internal timer signal is selected, and the 16-bit (timer0) operates in reload mode. In this case, baud rates are determined as follows. Asynchronous (start-stop synchronized): (φ / N) / (16 × 2 × (n + 1)) CLK synchronous: (φ / N) / ( 2 × (n + 1)) N: timer count clock source n: timer reload value Table 17.4-5 shows the relation between baud rates and reload values (decimal values) at a machine cycle speed of 7.3728 MHz. Table 17.4-5 Baud Rates and Reload Values Reload value Baud rate (bps) N=21 (machine cycle division by 2) N=23 (machine cycle division by 8) 38400 2 — 19200 5 — 9600 11 2 4800 23 5 2400 47 11 1200 95 23 600 191 47 300 383 95 When selecting the internal timer (16-bit timer0) as the baud rate clock source, note that the 16bit timer0 output signal TOT0 is already connected to the MB90595 controller internally. Therefore, it is not necessary to make an external connection from the 16-bit timer0 external output pins TOT0 to the UART1 external clock input pin SCK1. Also, this means that unless used in some other fashion, the timer pins are available for use as I/O port pins. ❍ External clock When bits CS2 to CS0 are set to "111" the external clock source is selected and baud rates are determined by the following formula, in which f represents the external clock frequency. Asynchronous (start-stop synchronized) mode: f/16 CLK synchronous: f Note that f has a maximum value of 2 MHz. 251 CHAPTER 17 UART1 (SCI) 17.4.1 Asynchronous (Start-Stop Synchronized) Mode The UART1 handles only data in NRZ (non-return to zero) format. ■ Asynchronous (Start-Stop Synchronized) Mode Data Transfer Format Figure 17.4-1 shows transfer data format. Figure 17.4-1 Asynchronous (Start-Stop Synchronized) Mode Data Transfer Format (Mode 0, 1) SIN1,SOT1 0 1 0 Start LSB 1 1 0 0 1 0 1 1 MSB Stop........(Mode 0) A/D Stop........(Mode 1) Transferred data "01001101B" As shown in Figure 17.4-1 , transfer data must begin with a start bit ("L" level data value), followed by LSB-first data of the designated bit-length, and ending with a stop bit ("H" level data value). When an external clock signal is selected, the clock should be input at all times. In normal mode (mode 0), data length may be set to 7 bits or 8 bits, however in multi-processor mode (mode 1) the data length must be 8 bits. Also, no parity bit may be attached in multiprocessor mode. Instead, an A/D bit must be attached. ■ Asynchronous (Start-Stop Synchronized) Mode Receive Operation Whenever the RXE bit (bit 9) in the SCR1 register is set to "1" the UART1 is receiving. The appearance of a start bit on the receive line allows one frame of data to be received according to the data format determined by the SCR1 register. When one frame of data has been received, error flags will be set if the corresponding errors have occurred, and then the RDRF flag (SST register bit 12) will be set. At this time if the RIE bit (bit 9) in the SSR1 register is set to "1" a receive interrupt will be sent to the CPU. The CPU will check each of the flags in the SSR1 register and read the SIDR1 register if data has been received normally. If any errors have occurred, the necessary processing should be followed. The RDRF flag is cleared when the SIDR1 register is read. ■ Asynchronous (Start-Stop Synchronized) Mode Transmit Operation Whenever the TDRE flag (bit 11) in the SSR1 register is set to "1" the UART1 is writing outgoing data to the SODR1 register. If the TXE bit (bit 8) is set to "1" transmit operation is in progress. As soon as data in the SODR1 register starts to be transferred to the transmit shift register for transmission, the TDRE flag is reset. This enables the next unit of outgoing data to be placed in the SODR1 register. At this time if the TIE bit (bit 8) in the SSR1 register is set to "1" a transmission interrupt is sent to the CPU, causing outgoing data to be placed into the SODR1 register. The TDRE flag is momentarily cleared each time data is placed into the SODR1 register. 252 CHAPTER 17 UART1 (SCI) 17.4.2 CLK Synchronous Mode The UART1 handles only data in NRZ (non-return to zero) format. ■ CLK Synchronous Mode Data Transfer Format Figure 17.4-2 shows the relation between the transmit and receive clock and data in CLK synchronous mode. Figure 17.4-2 CLK Synchronous Mode Data Transfer Format (Mode 2) SODRwrite Mark SCLK RXE,TXE SIN1,SOT1 1 LSB 0 1 1 0 0 1 0 MSB............(Mode 2) Transferred data "01001101B" When an internal clock signal source (dedicated baud rate generator or internal timer) is selected, a receive clock signal is automatically generated each time data is transmitted. When an external clock source is selected it is necessary to provide an accurate 1-byte clock signal after data is confirmed present in the transmit data buffer register SODR1 (indicated by the TDRE flag = 0). Note also that the signal must return to mark level before and after transmit operation. Data length is 8-bit only, and no parity bit may be attached. Also, there is no start/stop bit so that no error detection is enabled except for overrun errors. 253 CHAPTER 17 UART1 (SCI) ■ Control Register Settings for CLK Synchronous Mode When using CLK synchronous mode, the following settings are made to each of the control registers. ❍ SMR1 register MD1, MD0: 10 CS2, CS1, CS0: Indicate clock input SCKE: 1 for dedicated baud rate generator or internal timer, 0 for external clock SOE: 1 to send, 0 to receive only ❍ SCR1 register PEN: 0 P, SBL, A/D: These bits have no significance CL: 1 REC: 0 (to initialize) RXE, TXE: At least one must be "1" ❍ SSR1 Register RIE: 1 if interrupts are used, 0 if interrupts are not used TIE: 0 ■ Start of Communication in CLK Synchronous Mode Communication starts by writing to the SODR1 register. Even if data is to be only received (not sent), it is first necessary to write dummy data to the SODR1 register. ■ End of Communication in CLK Synchronous Mode The end of communication can be verified by the change of the RDRF flag in the SSR1 register to "1". To determine whether the communication was performed normally, read the ORE bit in the SSR1 register. 254 CHAPTER 17 UART1 (SCI) 17.5 UART1 Flags and Interrupt Sources The UART1 has five flags, PE, ORE, FRE, RDRF and TDRE, and two interrupt sources, one for transmit and one for receive. ■ UART1 Flags The five flags are the PE, ORE, FRE, RDRF and TDRE flags. The first three are set when transmit errors occur, the PE flag for a parity error, the ORE flag for an overrun error, and the FRE flag for a framing error, and are released by writing "0" to the REC bit in the SCR1 register. The RDRF flag is set when receive data is loaded into the SIDR1 register, and cleared when the data is read out of the SIDR1 register. Note however that there is no parity detect function in mode 1, and no parity detect function or framing error detect function in mode 2. The TDRE flag is set when the SODR1 register is empty and ready for data write access, and is cleared when data is written to the SODR1 register. ■ UART1 Interrupt Sources The UART1 has two interrupt sources, one for receive and one for transmit. During receive, interrupt requests are initiated by setting the PE, ORE, FRE or RDRF flags. During transmit, interrupt requests are initiated by setting the TDRE flag. Interrupt flag set timing in each operating mode is described in section "17.6 UART1 Interrupts and Flag Set Timing". 255 CHAPTER 17 UART1 (SCI) 17.6 UART1 Interrupts and Flag Set Timing This section describes the timing of interrupts and flag setting in each UART1 operating mode. ■ UART1 Interrupts and Flag Set Timing ❍ Mode 0 Receive The PE, ORE, FRE and RDRF flags are set and the interrupt request signal is sent to the CPU following the end of a receive transfer, when the final stop bit is detected. If any one of the PE, ORE or FRE flags is active, the data in the SIDR1 register will be invalid. Figure 17.6-1 shows the timing of the PE, ORE, FRE, and RDRF flags (mode 0). Figure 17.6-1 PE, ORE, FRE, RDRF Flag Set Timing (Mode 0) Data D6 D7 Stop PE,ORE,FRE RDRF Receiving interrupt ❍ Mode 1 Receive The ORE, FRE and RDRF flags are set and the interrupt request signal is sent to the CPU after the end of a receive transfer, when the final stop bit is detected. Also, if the receive data length is 8 bits, the 9th bit indicating address/data will be invalid. If either the ORE or FRE flags is active, the data in the SIDR1 register will be invalid. Figure 17.6-2 shows the timing of the ORE, FRE, and RDRF flags (mode 1). Figure 17.6-2 ORE, FRE, RDRF Flag Set Timing (Mode 1) Data ORE,FRE RDRF Receiving interrupt 256 D7 Address/data Stop CHAPTER 17 UART1 (SCI) ❍ Mode 2 Receive The ORE and RDRF flags are set and the interrupt request signal is sent to the CPU after the end of a receive transfer, when the final data (D7) is detected. If the ORE flag is active, the data in the SIDR1 register will be invalid. Figure 17.6-3 shows the timing of the ORE and RDRF flags (mode 2). Figure 17.6-3 ORE, RDRF Flag Set Timing (Mode 2) Data D5 D6 D7 ORE RDRF Receiving interrupt ❍ Mode 0, Mode 1, and Mode 2 Transmit The TDRE flag is cleared when data is written to the SODR1 register. The TDRE flag is set (and an interrupt request sent to the CPU) as soon as the data in the SODR1 register is transferred to the internal shift register, to ready the SODR1 register for the next data write cycle. During a transmit operation, if "0" is written to the TXE bit in the SCR1 register (including the RXE bit in mode 2), the TDRE bit in the SSR1 register will be set to "1" and the UART1 transmit operation will be disabled as soon as the transmit shifter stops. The data written to the SODR1 register will be sent, however, between the writing of "0" to the TXE bit in the SCR1 register (including the RXE bit in mode 2), and the end of the transmit operation. Figure 17.6-4 shows the timing of the TDRE flag (mode 0, 1), and Figure 17.6-5 shows the timing of the TDRE flag (mode 2). Figure 17.6-4 TDRE Flag Set Timing (Mode 0, 1) SODR write TDRE Interrupt request to CPU SOT1 interrupt SOT1 output ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3 A/D ST: Start bit D0 to D7: Data bits SP: Stop bit A/D: Address/data multiplexer 257 CHAPTER 17 UART1 (SCI) Figure 17.6-5 TDRE Flag Set Timing (Mode 2) SODR write TDRE Interrupt request to CPU SOT1 interrupt SOT1 output D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 to D7: Data bits 258 CHAPTER 17 UART1 (SCI) 17.7 UART1 Sample Applications and Precautionary Information This section presents a sample system configuration and communication flow chart as a sample application of the UART1 used in Mode 1. ■ UART1 Sample Application (System Configuration in Mode 1) Mode 1 is used when one host CPU is connected to multiple slave CPU's (see Figure 17.7-1 ). This UART1 resource supports only communication interface with the host-side unit. Figure 17.7-1 Sample System Configuration in Mode 1 SO SI Host CPU SO SI Slave CPU #0 SO SI Slave CPU #1 ■ UART1 Communication Flow Chart Transmission begins with the transfer of address data by the host CPU. Address data is data handled while the A/D bit in the SCR1 register is set to "1" and is used to select the slave CPU that is to receive the transmission, and to enable communication with the host CPU. In normal data, the A/D bit in the SCR1 register is set to "0". Figure 17.7-2 illustrates the flow of this process. No parity check function is available in mode 2, so that the PEN bit in the SCR1 register should be set to "0". 259 CHAPTER 17 UART1 (SCI) Figure 17.7-2 Communications Flowchart Using Mode 1 (Host CPU) START Set transfer mode to 1 Set D0 to D7 to data selecting slave CPU, set A/D to "1" and transfer 1 byte Set A/D to "0" Enable the receiving operation Communicate with the slave CPU NO Communication ended? YES Communicate with other slave CPU? NO YES Disable receiving operation END ■ Intelligent I/O Service (EI2OS) For information about EI2OS, see section 3.7 "Extended Intelligent I/O Service (EI2OS)". ■ Precautions for UART1 Use Always make communications mode settings when the UART1 is not operating. Transmit and receive data values are not assured during mode setting. 260 CHAPTER 18 SERIAL I/O CHAPTER 18 SERIAL I/O This chapter explains the serial I/O functions and operation. 18.1 "Outline of Serial I/O" 18.2 "Serial I/O Registers" 18.3 "Serial I/O Prescaler (SCDCR)" 18.4 "Serial I/O Operation" 18.5 "Negative Clock Operation" 261 CHAPTER 18 SERIAL I/O 18.1 Outline of Serial I/O The following two serial I/O operation modes are available: • Internal shift clock mode: Data is transferred in synchronization with the internal clock. • External shift clock mode: Data is transferred in synchronization with the clock input through the external pin (SCK2). In this mode, data transfer by CPU instructions is enabled by operating a general-purpose port that shares the external pin (SCK2). ■ Serial I/O Block Diagram This block is a serial I/O interface that allows data transfer using clock synchronization. The interface consists of a single eight-bit channel. Data can be transferred from the LSB or MSB. Figure 18.1-1 Serial I/O Interface Block Diagram Internal data bus (MSB first) D7 to D0 D7 to D0 (LSB first) Transfer direction selection SIN2 Read Write SDR (Serial data register) SOT2 SCK2 Control circuit Shift clock counter Internal clock 2 1 0 SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT MODE BDS Interrupt request Internal data bus 262 SOE SCOE CHAPTER 18 SERIAL I/O 18.2 Serial I/O Registers The following two serial I/O registers are used: • Serial mode control status register (SMCS) • Serial shift data register (SDR) ■ Serial I/O Registers bit Address: 00002D H bit 15 14 13 SMD2 SMD1 SMD0 7 6 5 12 11 SIE 4 Address: 00002C H bit Address: 00002E H 10 9 SIR BUSY STOP 3 2 1 MODE 7 6 5 4 3 D7 D6 D5 D4 D3 BDS 8 Serial mode control STRT status register (SMCS) 0 SOE SCOE 2 1 0 D2 D1 D0 Serial data register (SDR) 263 CHAPTER 18 SERIAL I/O 18.2.1 Serial Mode Control Status Register (SMCS) The serial mode control status register (SMCS) controls the serial I/O transfer mode. ■ Serial Mode Control Status Register (SMCS) bit 15 14 13 SMCS Address: 00002DH SMD2 SMD1 SMD0 R/W R/W R/W R/W 12 11 10 SIE SIR BUSY R/W R/W R 9 7 bit R/W 5 4 : Undefined 00000010B R/W *2 3 2 MODE R/W : Readable/Writable R : Read only - 6 Initial value STOP STRT *1 SMCS Address: 00002CH 8 BDS 1 0 Initial value SOE SCOE ----0000B R/W R/W R/W R/W *1: Only "0" can be written. *2: Only "1" can be written. "0" is always read. ❍ Functions of the bits [bit3] Serial mode selection bit (MODE) The serial mode selection bit is used to select the conditions to start the transfer operation from the stop state. This bit must not be updated during operation. Table 18.2-1 Setting the Serial Mode Selection Bit MODE Operation 0 Transfer starts when STRT=1. [Default] 1 Transfer starts when the serial data register is read or written to. This bit is initialized to a "0" upon a reset, and can be read or written to. To activate the intelligent I/O service, ensure that "1" is written to this bit. [bit2] Bit order select bit (BDS) This bit specifies the bit ordering of the data transfer. The data can be transferred from the least significant bit (LSB first mode) or from the most significant bit (MSB first mode). Table 18.2-2 Setting the Transfer Direction Selection Bit 0 LSB first [default] 1 MSB first Note: Specify the bit ordering before any data is written to SDR. 264 CHAPTER 18 SERIAL I/O [bit1] Serial output enable bit (SOE: Serial out enable) The output of external output pin (SOT2) for the serial I/O is controlled as shown in Table 18.2-3 . Table 18.2-3 Setting the Serial Output Enable Bit 0 General-purpose port pin [default] 1 Serial data output This bit is initialized to "0" upon a reset. This bit is readable and writable. [bit0] Shift clock output enable bit (SCOE: SCK2 output enable) The output of external I/O pin (SCK2) for the shift clock is controlled as shown in Table 18.2-4 . Table 18.2-4 Setting the Shift Clock Output Enable Bit 0 General-purpose port pin, transfer for each instruction [default] 1 Shift clock output pin Ensure that "0" is written to this bit when data is transferred for each instruction in external shift clock mode. This bit is initialized to "0" upon a reset. This bit is readable and writable. [bit15 to bit13] Shift clock selection bits (SMD2, SMD1, SMD0: Serial shift clock mode) The shift clock selection bits are used to select the serial shift clock mode as described below. Table 18.2-5 Setting the Serial Shift Clock Mode SMD2 SMD1 SMD0 φ=16MHz div=4 φ=8MHz div=4 φ=4MHz div=4 0 0 0 2 MHz 1 MHz 500 kHz 0 0 1 1 MHz 500 kHz 250 kHz 0 1 0 250 kHz 125 kHz 62.5 kHz 0 1 1 125 kHz 62.5 kHz 31.25 kHz 1 0 0 62.5 kHz 31.2 kHz 15.625 kHz 1 0 1 External shift clock mode 1 1 0 Reserved 1 1 1 Reserved 265 CHAPTER 18 SERIAL I/O div M1 DIV3 DIV2 DIV1 DIV0 Recommended machine cycle 3 1 1 1 0 1 6 MHz 4 1 1 1 0 0 8 MHz 5 1 1 0 1 1 10 MHz 6 1 1 0 1 0 12 MHz 7 1 1 0 0 1 14 MHz 8 1 1 0 0 0 16 MHz Setting of the Serial I/O * : For details, see 18.3 "Serial I/O Prescaler (SCDCR)". These bits are initialized to "000" upon a reset. These bits must not be updated during data transfer. Five types of internal shift clock and an external shift clock are available. Do not set "110" or "111" in SMD2, SMD1, and SMD0 as these values are reserved. When a clock is selected and SCOE is 0, shift operations can be enabled for individual instructions by operating the port shared with the SCK2 pin. [bit12] Serial I/O interrupt enable bit (SIE: Serial I/O interrupt enable) The serial I/O interrupt enable bit controls the serial I/O interrupt request as described below. Table 18.2-6 Setting the Interrupt Request Enable Bit 0 Serial I/O interrupt disabled [default] 1 Serial I/O interrupt enabled This bit is initialized to "0" upon a reset. This bit is readable and writable. [bit11] Serial I/O interrupt request bit (SIR: Serial I/O interrupt request) When serial data transfer is completed, "1" is set to this bit. If this bit is set while interrupts are enabled (SIE=1), an interrupt request is issued to the CPU. The clear condition varies with the MODE bit. When "0" is written to the MODE bit, the SIR bit is cleared by writing "0". When "1" is written to the MODE bit, the SIR bit is cleared by reading or writing to SDR. When the system is reset or "1" is written to the STOP bit, the SIR bit is cleared regardless of the MODE bit value. Writing "1" to the SIR bit has no effect. "1" is always read by a read operation of a readmodify-write instruction. 266 CHAPTER 18 SERIAL I/O [bit10] Transfer status bit (BUSY) The transfer status bit indicates whether serial transfer is being executed. Table 18.2-7 Setting the Transfer Status Bit BUSY Operating 0 Stopped, or standing by for serial data register R/W 1 Serial transfer [default] This bit is initialized to "0" upon a reset. This is a read-only bit. [bit9] Stop bit (STOP) The stop bit forcibly terminates serial transfer. When "1" is written to this bit, the transfer is stopped. Table 18.2-8 Setting the Stop Bit STOP Operating 0 Normal operation 1 Transfer stop by STOP=1 [default value] This bit is initialized to "1" upon a reset. This bit is readable and writable. [bit8] Start bit (STRT: Start) The start bit activates serial transfer. Writing "1" to this bit starts the data transfer when the MODE bit is set to 0. When the MODE bit is set to 1 and the STRT bit is set to 1, writing the data into the serial data register starts the transfer. Writing "1" is ignored while the system is performing serial transfer or standing by for a serial shift register read or write. Writing "0" has no effect. "0" is always read. 267 CHAPTER 18 SERIAL I/O 18.2.2 Serial Shift Data Register (SDR) The serial data register (SDR) retains serial I/O transfer data. This register cannot be read or written during data transfer. ■ Serial Shift Data Register (SDR) bit SDR Address : 00002E H 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W : Readable/Writable 268 R/W Initial value XX H (undefined) CHAPTER 18 SERIAL I/O 18.3 Serial I/O Prescaler (SCDCR) The serial I/O prescaler (SCDCR) provides a serial I/O shift clock. The serial I/O operation clock can be obtained by dividing the machine clock. The serial I/O interface is designed so that constant baud rate can be obtained for a variety of machine clocks by the use of this communication prescaler. The SCDCR register controls machine clock division. ■ Serial I/O Prescaler (SCDCR) SCDCR bit Address: 00002BH 15 14 13 12 MD 11 10 9 DIV3 DIV2 DIV1 DIV0 R/W R/W R/W R/W R/W R/W : Readable/Writable 8 Initial value 0---1111B [bit15] MD (Machine clock divide mode select): This bit is used to control the operation of the communication prescaler. 0: The Serial I/O Prescaler is disabled. 1: The Serial I/O Prescaler is enabled. [bit11 to bit8] DIV3 to DIV0 (Divide3 to Divide0): These bits are used to determine the machine clock division ratio. Table 18.3-1 Machine Clock Division Ratio DIV3 to DIV0 Division ratio 1101B 3 1100B 4 1011B 5 1010B 6 1001B 7 1000B 8 Note: When the division ratio is changed, allow two cycles for the clock to stabilize before starting communication. 269 CHAPTER 18 SERIAL I/O 18.4 Serial I/O Operation The serial I/O consists of the serial mode control status register (SMCS) and shift register (SDR), and is used for input and output of 8-bit serial data. ■ Serial I/O Operation The bits in the shift register are serially output via the serial output pin (SOT2 pin) at the falling edge of the serial shift clock (external clock or internal clock). The bits are serially input to the shift register (SDR) via the serial input pin (SIN2 pin) at the rising edge of the serial shift clock. The shift direction (transfer from MSB or LSB) is specified by the direction specification bit (BDS) of the serial mode control status register (SMCS). At the end of serial data transfer, this block is stopped or stands by for a read or write of the data register according to the MODE bit of the serial mode control status register (SMCS). To start transfer from the stop or standby state, follow the procedure below. 270 • To resume operation from the stop state, write "0" to the STOP bit and "1" to the STRT bit. (The STOP and STRT bits can be set simultaneously.) • To resume operation from the serial shift data register R/W standby state, read or write to the data register. CHAPTER 18 SERIAL I/O 18.4.1 Shift Clock There are two modes of shift clock: internal or external shift clock. These two modes are selected by setting the SMCS. To switch the modes, ensure that serial I/O transfer is stopped. To check whether the serial I/O transfer is stopped, read the BUSY bit. ■ Internal Shift Cock Mode In internal shift clock mode, data transfer is based on the internal clock. As a synchronization timing output, a shift clock of 50% duty ratio can be output from the SCK2 pin. Data is transferred at one bit per clock. The transfer speed is expressed as follows: Transfer speed (s)= A x div Internal clock machine cycle (Hz) "A" is the division ratio indicated by the SMD bit of SMCS. The value can be 21, 22, 24, 25, or 26. Table 18.4-1 Formulas for Calculation Baud Rate in Internal Shift Clock Mode SMD2 SMD1 SMD0 φ/div = 4 MHz φ/div = 2 MHz φ/div = 1 MHz Formula 0 0 0 2 MHz 1 MHz 500 kHz (φ/div)/21 0 0 1 1 MHz 500 kHz 250 kHz (φ/div)/22 0 1 0 250 kHz 125 kHz 62.5 kHz (φ/div)/24 0 1 1 125 kHz 62.5 kHz 31.25 kHz (φ/div)/25 1 0 0 62.5 kHz 31.2 kHz 15.625 kHz (φ/div)/26 See Table 18.3-1 for the div value. ■ External Shift Clock Mode In external shift clock mode, the data transfer is based on the external clock supplied via the SCK2 pin. Data is transferred at one bit per clock. The transfer speed can be between DC and 1/(8 machine cycles). For example, the transfer speed can be up to 2 MHz when 1 machine cycle is equal to 62.5 ns. The external clock frequency has maximum value of 2 MHz. A data bit can also be transferred by software, which is enabled as described below. Select external shift clock mode, and write "0" to the SCOE bit of SMCS. Then, write "1" to the direction register for the port sharing the SCK2 pin, and place the port in output mode. Then, when "1" and "0" are written to the data register (PDR) of the port, the port value output via the SCK2 pin is fetched as the external clock and transfer starts. Ensure that the shift clock starts from "H". Note: The SMCS or SDR must not be written to during serial I/O operation. 271 CHAPTER 18 SERIAL I/O 18.4.2 Serial I/O Operation Status There are four types of serial I/O operation status as follows: • STOP • Halt • SDR R/W standby • Transfer ■ Serial I/O Operation Status ❍ STOP The STOP state is initiated upon RESET or when "1" is written to the STOP bit of SMCS. The shift counter is initialized, and "0" is written to SIR. To resume operation from the STOP state, write "0" to STOP and "1" to STRT. (These two bits can be written to simultaneously.) Since the STOP bit overrides the STRT bit, transfer cannot be started by writing "1" to STRT while "1" is written to STOP. ❍ Halt When transfer is completed while the MODE bit is "0", "0" is set to BUSY and "1" is set to SIR of the SMCS, the counter is initialized, and the system stops. To resume operation from the stop state, write "1" to STRT. ❍ Serial Data Register R/W Standby When transfer is completed while the MODE bit is "1", "0" is set to BUSY and "1" is set to SIR of the SMCS, and the system enters the serial data register R/W standby state. If the interrupt enable flag is set, an interrupt signal is output from this block. To resume operation from R/W standby state, read or write to the serial data register. This sets the BUSY bit to "1" and starts data transfer. ❍ Transfer "1" is set to the BUSY bit and serial transfer is being performed. According to the MODE bit, the halt state or R/W standby state comes next. The Table 18.4-1 and Figure 18.4-2 are diagrams of the operation transitions. 272 CHAPTER 18 SERIAL I/O Figure 18.4-1 Extended I/O Serial Interface Operation Transitions Reset STOP=0 & STRT=0 End of transfer STOP STRT=0, BUSY=0 STRT=0, BUSY=0 STOP=1 MODE=0 MODE=0 STOP=0 & & STOP=0 STOP=1 STOP=0 STOP=1 STRT=1 & & END STRT=1 Transfer Serial data register R/W standby MODE=1 & END & STOP=0 STRT=1, BUSY=1 STRT=1, BUSY=0 MODE=1 SDR R/W & MODE=1 Serial data Figure 18.4-2 Serial Data Register Read/Write Data bus Data bus Read Write Interrupt output SOT2 SIN2 Extended I/O serial interface Read Write CPU (1) (2) Interrupt input Data bus Interrupt controller (1) If "1" is written to MODE, transfer ends according to the shift clock counter. The read/write standby state starts when "1" is written to SIR. If "1" is written to the SIE bit, an interrupt signal is generated. No interrupt signal is generated when SIE is inactive or transfer has been terminated by writing "1" to STOP. (2) Reading or writing to the serial data register clears the interrupt request and starts serial transfer. 273 CHAPTER 18 SERIAL I/O 18.4.3 Shift Operation Start/stop Timing To start shift operation, set the SMCS STOP bit to "0" and STRT bit to "1". The shift operation is stopped by setting the STOP bit to "1" or upon the end of transfer. • Stop by STOP = 1: Shift operation stops with SIR = 0 regardless of the MODE bit. • Stop upon end of transfer: Shift operation stops with SIR = 1 regardless of the MODE bit. Regardless of the MODE bit, the BUSY bit is set to "1" during serial transfer and reset to "0" in stop or R/W standby state. Read the BUSY bit to check the transfer status. ■ Shift Operation Start/Stop Timing ❍ Internal shift clock mode (LSB first) Figure 18.4-3 Shift Operation Start/stop Timing (Internal Clock) "1" output SCK2 STRT BUSY SOT2 (Transfer start) (Transfer end) If MODE=0 DO0 DO7 (Data maintained) ❍ External shift clock mode (LSB first) Figure 18.4-4 Shift Operation Start/stop Timing (External Clock) SCK2 STRT BUSY SOT2 274 (Transfer start) (Transfer end) If MODE=0 DO0 DO7 (Data maintained) CHAPTER 18 SERIAL I/O ❍ External shift clock mode with instruction shift (LSB first) Figure 18.4-5 Shift Operation Start/stop Timing (External Shift Clock Mode with Instruction Shift) SCK2= 0 in PDR SCK2 SCK2= 0 in PDR SCK2= 1 in PDR (Transfer end) STRT If MODE=0 BUSY SOT2 DO6 DO7 (Data maintained) * : For an instruction shift, "H" is output when "1" is written to the bit corresponding to SCK2 of PDR, and "L" is output when "0" is written. (When SCOE=0 in external shift clock mode) Note: For an instruction shift, "H" is output when "1" is written to the bit corresponding to SCK2 of PDR, and "L" is output when "0" is written. (When SCOE=0 in external shift clock mode) ❍ Stop by STOP=1 (LSB first, internal clock) Figure 18.4-6 Stop Timing When "1" is Written to the STOP Bit "1" output SCK2 (Transfer start) (Transfer stop) If MODE=0 STRT BUSY STOP DO3 SOT2 DO4 DO5 (Data maintained) Note: DO7 to DO0 indicate output data. During serial data transfer, data is output from the serial output pin (SOT2) at the falling edge of the shift clock, and input from the serial input pin (SIN2) at the rising edge. 275 CHAPTER 18 SERIAL I/O ❍ LSB first (When the BDS bit is "0") SCK2 SIN2 Input SIN2 DI0 DI1 DI2 DI3 SOT2 Output DI4 DI5 DI6 DI7 SOT2 DO0 DO1 DO2 DO4 DO5 DO6 DO7 DI3 DI2 DI1 DI0 DO3 DO2 DO1 DO0 DO3 ❍ MSB first (When the BDS bit is "1") Figure 18.4-7 I/O Shift Timing SCK2 SIN2 SIN2 Input DI7 DI6 DI5 DI4 SOT2 Output SOT2 276 DO7 DO6 DO5 DO4 CHAPTER 18 SERIAL I/O 18.4.4 Interrupt Function of Extended Serial I/O Interface This block can issue an interrupt request to the CPU. At the end of data transfer, the SIR bit is set as an interrupt flag. When "1" is written to the interrupt enable bit (SIE bit) of SMCS, an interrupt request is issued to the CPU. ■ Interrupt Function of Extended Serial I/O Interface Figure 18.4-8 Interrupt Signal Output Timing SCK2 (Transfer end) BUSY Note: When MODE=1 SIE=1 SIR SDR RD/WR SOT2 DO6 DO7 (Data is maintained.) 277 CHAPTER 18 SERIAL I/O 18.5 Negative Clock Operation The MB90595 Series supports the negative clock operation of the Serial I/O. In this operation, the shift clock signal is simply negated by a inverter. Therefore the definition of the shift clock signal in the proceeding sections of the Serial I/O is inverted from the logic low level to logic high level, from the negative edge to the positive edge and vice versa. This is the same for both the serial clock input and output. ■ Negative Clock Operation bit 7 6 5 4 3 2 1 0 Address : 00002FH NEG SES (Serial Edge Select) R/W R/W : Readable/Writable Table 18.5-1 Setting the NEG Bit NEG 278 Operation 0 Normal operation [default] 1 The shift clock signal is inverted Initial value -------0 B CHAPTER 19 CAN CONTROLLER CHAPTER 19 CAN CONTROLLER This chapter explains the CAN controller functions and operation. 19.1 "Features of CAN Controller" 19.2 "CAN Controller Block Diagram" 19.3 "List of Total Control Registers" 19.4 "List of Message Buffers (ID Registers)" 19.5 "List of Message Buffers (DLC Registers and Data Registers)" 19.6 "Classification of CAN Control Registers" 19.7 "Transmission under CAN Controller" 19.8 "Reception under CAN Controller" 19.9 "CAN Controller Reception Flowchart" 19.10 "Usage of CAN Controller" 19.11 "Procedure for Transmission by Message Buffer (x)" 19.12 "Procedure for Reception by Message Buffer (x)" 19.13 "Deciding Multi-level Message Buffer Configuration" 19.14 "Precautions when Using CAN Controller" 279 CHAPTER 19 CAN CONTROLLER 19.1 Features of CAN Controller The CAN controller is a module built into a 16-bit microcontroller (F2MC-16LX). The CAN (Controller Area Network) is the standard protocol for serial communication between automobile controllers and is widely used in industrial applications. ■ Features of CAN Controller The CAN controller has the following features: ❍ Conforms to CAN Specification Version 2.0 Part A and B Supports transmission/reception in standard frame and extended frame formats ❍ Supports transmitting of data frames by receiving remote frames ❍ 16 transmitting/receiving message buffers 29-bit ID and 8-byte data Multi-level message buffer configuration ❍ Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as 1D acceptance mask Two acceptance mask registers in either standard frame format or extended frame formats. ❍ Bit rate programmable from 10 kbps to 1 Mbps (A minimum 8 MHz machine clock is required if 1 Mbps is used) 280 CHAPTER 19 CAN CONTROLLER 19.2 CAN Controller Block Diagram Figure 19.2-1 is a CAN controller block diagram. ■ CAN Controller Block Diagram Figure 19.2-1 CAN Controller Block Diagram F2MC-16LX bus TQ (Operating clock) Prescaler 1 to 64 frequency division Clock Bit timing generation SYNC, TSEG1, TSEG2 PSC TS1 BTR TS2 RSJ TOE TS RS CSR IDLE, INT, SUSPND, transmit, receive, ERR, OVRLD HALT NIE NT Node status change interrupt generation Bus state machine Node status change interrupt NS1, 0 Error control RTEC Transmitting/receiving sequencer BVALR TREQR TBFx, clear Transmitting buffer x decision TBFx Data counter Error frame generation Acceptance filter control Overload frame generation TDLC RDLC TBFx IDSEL BITER, STFER, CRCER, FRMER, ACKER TCANR Output driver ARBLOST TX TRTRR TCR TBFx, set, clear Transmission complete interrupt Transmissioncomplete interrupt generation TIER RCR CRC generation TDLC ACK generation CRCER RBFx, set RDLC Reception complete interrupt Reception complete interrupt generation RIER RRTRR Stuf?ng Transmission shift register RFWTR RBFx, TBFx, set, clear RBFx, set CRCgeneration/error check Receive shift register STFER Destufing/stufing error check IDSEL ROVRR ARBLOST AMSR AMR0 0 1 Acceptance filter RBFx IDR0 to 15 DLCR0 to 15 DTR0 to 15 RAM RAM address generation BITER Bit error check ACKER Acknowledgment error check FRMER Form error check Receivingbufferx decision AMR1 Arbitration check PH1 Input latch RX RBFx, TBFx, RDLC, TDLC, IDSEL LEIR IDER 281 CHAPTER 19 CAN CONTROLLER 19.3 List of Total Control Registers Table 19.3-1 lists the total control registers. ■ List of Total Control Registers Table 19.3-1 Total Control Registers (1/2) Address 000080H Register Access Initial Value Message buffer valid register BVALR R/W 00000000 00000000 Transmit request register TREQR R/W 00000000 00000000 Transmit cancel register TCANR W 00000000 00000000 Transmit complete register TCR R/W 00000000 00000000 Receive complete register RCR R/W 00000000 00000000 Remote request receiving register RRTRR R/W 00000000 00000000 Receive overrun register ROVRR R/W 00000000 00000000 Receive interrupt enable register RIER R/W 00000000 00000000 Control status register CSR R/W, R 00---000 0----0-1 Last event indicator register LEIR R/W -------- 000-0000 Receive/transmit error counter RTEC R 00000000 00000000 BTR R/W -1111111 11111111 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH 001B00H 001B01H 001B02H 001B03H 001B04H 001B05H 001B06H 001B07H 282 Bit timing register CHAPTER 19 CAN CONTROLLER Table 19.3-1 Total Control Registers (2/2) Address 001B08H Register Access Initial Value IDER R/W XXXXXXXX XXXXXXXX Transmit RTR register TRTRR R/W 00000000 00000000 Remote frame receive waiting register RFWTR R/W XXXXXXXX XXXXXXXX TIER R/W 00000000 00000000 IDE register 001B09H 001B0AH 001B0BH 001B0CH 001B0DH 001B0EH Transmit interrupt enable register 001B0FH 001B10H 001B11H XXXXXXXX XXXXXXXX Acceptance mask select register AMSR R/W 001B12H XXXXXXXX XXXXXXXX 001B13H 001B14H 001B15H XXXXXXXX XXXXXXXX Acceptance mask register 0 AMR0 R/W 001B16H XXXXX--- XXXXXXXX 001B17H 001B18H 001B19H 001B1AH XXXXXXXX XXXXXXXX Acceptance mask register 1 AMR1 R/W XXXXX--- XXXXXXXX 001B1BH 283 CHAPTER 19 CAN CONTROLLER 19.4 List of Message Buffers (ID Registers) Table 19.4-1 lists the message buffers (ID registers). ■ List of Message Buffers (ID Registers) Table 19.4-1 Message Buffers (ID Registers) (1/3) Address 001A00H to 001A1FH Register General-purpose RAM Abbreviation Access Initial Value -- R/W XXXXXXXX to XXXXXXXX 001A20H 001A21H XXXXXXXX XXXXXXXX ID register 0 IDR0 R/W 001A22H XXXXX--- XXXXXXXX 001A23H 001A24H 001A25H XXXXXXXX XXXXXXXX ID register 1 IDR1 R/W 001A26H XXXXX--- XXXXXXXX 001A27H 001A28H 001A29H XXXXXXXX XXXXXXXX ID register 2 IDR2 R/W 001A2AH XXXXX--- XXXXXXXX 001A2BH 001A2CH 001A2DH XXXXXXXX XXXXXXXX ID register 3 IDR3 R/W 001A2EH XXXXX--- XXXXXXXX 001A2FH 001A30H 001A31H 001A32H 001A33H 284 XXXXXXXX XXXXXXXX ID register 4 IDR4 R/W XXXXX--- XXXXXXXX CHAPTER 19 CAN CONTROLLER Table 19.4-1 Message Buffers (ID Registers) (2/3) Address Register Abbreviation Access 001A34H 001A35H Initial Value XXXXXXXX XXXXXXXX ID register 5 IDR5 R/W 001A36H XXXXX--- XXXXXXXX 001A37H 001A38H 001A39H XXXXXXXX XXXXXXXX ID register 6 IDR6 R/W 001A3AH XXXXX--- XXXXXXXX 001A3BH 001A3CH 001A3DH XXXXXXXX XXXXXXXX ID register 7 IDR7 R/W 001A3EH XXXXX--- XXXXXXXX 001A3FH 001A40H 001A41H XXXXXXXX XXXXXXXX ID register 8 IDR8 R/W 001A42H XXXXX--- XXXXXXXX 001A43H 001A44H 001A45H XXXXXXXX XXXXXXXX ID register 9 IDR9 R/W 001A46H XXXXX--- XXXXXXXX 001A47H 001A48H 001A49H XXXXXXXX XXXXXXXX ID register 10 IDR10 R/W 001A4AH XXXXX--- XXXXXXXX 001A4BH 001A4CH 001A4DH XXXXXXXX XXXXXXXX ID register 11 IDR11 R/W 001A4EH XXXXX--- XXXXXXXX 001A4FH 001A50H 001A51H 001A52H XXXXXXXX XXXXXXXX ID register 12 IDR12 R/W XXXXX--- XXXXXXXX 001A53H 285 CHAPTER 19 CAN CONTROLLER Table 19.4-1 Message Buffers (ID Registers) (3/3) Address Register Abbreviation Access 001A54H 001A55H Initial Value XXXXXXXX XXXXXXXX ID register 13 IDR13 R/W 001A56H XXXXX--- XXXXXXXX 001A57H 001A58H 001A59H XXXXXXXX XXXXXXXX ID register 14 IDR14 R/W 001A5AH XXXXX--- XXXXXXXX 001A5BH 001A5CH 001A5DH 001A5EH 001A5FH 286 XXXXXXXX XXXXXXXX ID register 15 IDR15 R/W XXXXX--- XXXXXXXX CHAPTER 19 CAN CONTROLLER 19.5 List of Message Buffers (DLC Registers and Data Registers) Table 19.5-1 lists the message buffers (DLC registers), and Table 19.5-2 lists the message buffers (data registers). ■ List of Message Buffers (DLC Registers) Table 19.5-1 List of Message Buffers (DLC Registers) (1/2) Address 001A60H Register Abbreviation Access Initial Value DLC register 0 DLCR0 R/W ----XXXX DLC register 1 DLCR1 R/W ----XXXX DLC register 2 DLCR2 R/W ----XXXX DLC register 3 DLCR3 R/W ----XXXX DLC register 4 DLCR4 R/W ----XXXX DLC register 5 DLCR5 R/W ----XXXX DLC register 6 DLCR6 R/W ----XXXX DLC register 7 DLCR7 R/W ----XXXX DLC register 8 DLCR8 R/W ----XXXX DLC register 9 DLCR9 R/W ----XXXX DLC register 10 DLCR10 R/W ----XXXX DLC register 11 DLCR11 R/W ----XXXX 001A61H 001A62H 001A63H 001A64H 001A65H 001A66H 001A67H 001A68H 001A69H 001A6AH 001A6BH 001A6CH 001A6DH 001A6EH 001A6FH 001A70H 001A71H 001A72H 001A73H 001A74H 001A75H 001A76H 001A77H 287 CHAPTER 19 CAN CONTROLLER Table 19.5-1 List of Message Buffers (DLC Registers) (2/2) Address 001A78H Register Abbreviation Access Initial Value DLC register 12 DLCR12 R/W ----XXXX DLC register 13 DLCR13 R/W ----XXXX DLC register 14 DLCR14 R/W ----XXXX DLC register 15 DLCR15 R/W ----XXXX 001A79H 001A7AH 001A7BH 001A7CH 001A7DH 001A7EH 001A7FH ■ List of Message Buffers (Data Registers) Table 19.5-2 List of Message Buffers (Data Registers) (1/2) Address Register Abbreviation Access Initial Value 001A80H to 001A87H Data register 0 (8 bytes) DTR0 R/W XXXXXXXX to XXXXXXXX 001A88H to 001A8FH Data register 1 (8 bytes) DTR1 R/W XXXXXXXX to XXXXXXXX 001A90H to 001A97H Data register 2 (8 bytes) DTR2 R/W XXXXXXXX to XXXXXXXX 001A98H to 001A9FH Data register 3 (8 bytes) DTR3 R/W XXXXXXXX to XXXXXXXX 001AA0H to 001AA7H Data register 4 (8 bytes) DTR4 R/W XXXXXXXX to XXXXXXXX 001AA8H to 001AAFH Data register 5 (8 bytes) DTR5 R/W XXXXXXXX to XXXXXXXX 001AB0H to 001AB7H Data register 6 (8 bytes) DTR6 R/W XXXXXXXX to XXXXXXXX 001AB8H to 001ABFH Data register 7 (8 bytes) DTR7 R/W XXXXXXXX to XXXXXXXX 001AC0H to 001AC7H Data register 8 (8 bytes) DTR8 R/W XXXXXXXX to XXXXXXXX 001AC8H to 001ACFH Data register 9 (8 bytes) DTR9 R/W XXXXXXXX to XXXXXXXX 001AD0H to 001AD7H Data register 10 (8 bytes) DTR10 R/W XXXXXXXX to XXXXXXXX 001AD8H to 001ADFH Data register 11 (8 bytes) DTR11 R/W XXXXXXXX to XXXXXXXX 288 CHAPTER 19 CAN CONTROLLER Table 19.5-2 List of Message Buffers (Data Registers) (2/2) Address Register Abbreviation Access Initial Value 001AE0H to 001AE7H Data register 12 (8 bytes) DTR12 R/W XXXXXXXX to XXXXXXXX 001AE8H to 001AEFH Data register 13 (8 bytes) DTR13 R/W XXXXXXXX to XXXXXXXX 001AF0H to 001AF7H Data register 14 (8 bytes) DTR14 R/W XXXXXXXX to XXXXXXXX 001AF8H to 001AFFH Data register 15 (8 bytes) DTR15 R/W XXXXXXXX to XXXXXXXX 289 CHAPTER 19 CAN CONTROLLER 19.6 Classification of CAN Control Registers The CAN controller registers are classified into the following three types: • Total control registers • Message buffer control registers • Message buffers ■ Total Control Registers The total control registers include the following four registers: 1. Control status register (CSR) 2. Last event indicator register (LEIR) 3. Receive/transmit error counter (RTEC) 4. Bit timing register (BTR) ■ Message Buffer Control Registers The message buffer control registers include the following 14 registers: 1. Message buffer valid register (BVALR) 2. IDE register (IDER) 3. Transmit request register (TREQR) 4. Transmit RTR register (TRTRR) 5. Remote frame receive waiting register (RFWTR) 6. Transmit cancel register (TCANR) 7. Transmit complete register (TCR) 8. Transmit interrupt enable register (TIER) 9. Receive complete register (RCR) 10.Remote request receiving register (RRTRR) 11.Receive overrun register (ROVRR) 12.Receive interrupt enable register (RIER) 13.Acceptance mask select register (AMSR) 14.Acceptance mask registers 0 and 1 (AMR0, AMR1) ■ Message Buffers The message buffers include the following three types of registers: 1. ID register x (x = 0 to 15) (IDRx) 2. DLC register x (x = 0 to 15) (DLCRx) 3. Data register x (x = 0 to 15) (DTRx) 290 CHAPTER 19 CAN CONTROLLER 19.6.1 Control Status Register (CSR) The lower 8 bits with the control status register (CSR) is prohibited from executing any bit operation instructions (Read-Modify-Write instructions). Only in the case of HALT bits unchanged, use any bit operation instructions without problems (initialization of the macro instructions etc.). ■ Control Status Register (CSR) bit 15 14 13 11 10 9 8 Address: 001B01H TS RS — — — NT NS1 NS0 Read/write: (R) (R) (—) (—) (—) (R/W) (R) (R) Initial value: (0) (0) (—) (—) (—) (0) (0) (0) 7 6 5 4 3 2 1 0 Address: 001B00H TOE — — — — NIE — HALT Read/write: (R/W) (—) (—) (—) (—) (R/W) (—) Initial value: (0) (—) (—) (—) (—) (0) (—) bit 12 (R/W) (1) R/W : Readable/Writable R : Read only : Undefined [bit15] TS: Transmit status bit This bit indicates whether a message is being transmitted. 0: Message not transmitted 1: Message transmitted This bit is 0 even while error and overload frames are transmitted. [bit14] RS: Receive status bit This bit indicates whether a message is being received. 0: Message not received 1: Message received While a message is on the bus, this bit becomes 1. Therefore, this bit is also 1 while a message is being transmitted. This bit does not necessarily indicates whether a receiving message passes through the acceptance filter. As a result, when this bit is 0, it implies that the bus operation is stopped (HALT = 0); the bus is in the intermission/bus idle or a error/overload frame is on the bus. 291 CHAPTER 19 CAN CONTROLLER [bit10] NT: Node status transition flag If the node status is changed to increment, or from Bus Off to Error Active, this bit is set to 1. In other words, the NT bit is set to 1 if the node status is changed from Error Active (00) to Warning (01), from Warning (01) to Error Passive (10), from Error Passive (10) to Bus Off (11), and from Bus Off (11) to Error Active (00). Numbers in parentheses indicate the values of NS1 and NS0 bits. When the node status transition interrupt enable bit (NIE) is 1, an interrupt is generated. Writing 0 sets the NT bit to 0. Writing 1 to the NT bit is ignored. 1 is read when read-modifywrite instruction is read. [bit9, bit8] NS1 and NS0: Node status bits 1 and 0 These bits indicate the current node status. Table 19.6-1 Correspondence between NS1 and NS0 and Node Status NS1 NS0 Node status 0 0 Error active 0 1 Warning (error active) 1 0 Error passive 1 1 Bus off Note: Warning (error active) is included in the error active in CAN Specification 2.0B for the node status, however, indicates that the transmit error counter or receive error counter has exceeded 96. The node status change diagram is shown in Figure 19.6-1 . Figure 19.6-1 Node Status Transition Diagram Hardware reset REC: Receive error counter TEC: Transmit error counter Error active After 0 hasbeenwrittentothe HALT bitof theregister( CSR ),continuous11-bitHigh levels(recessivebits)areinput128times to the receive input pin ( RX ). REC 96 or TEC 96 REC < 96 and TEC < 96 Warning (Error active) REC 128 or TEC 128 REC < 128 and TEC < 128 Error passive Bus off (HALT = 1) TEC 292 256 CHAPTER 19 CAN CONTROLLER [bit7] TOE: Transmit output enable bit Writing 1 to this bit switches from a general-purpose port pin to a transmit pin of the CAN controller. 0: General-purpose port pin 1: Transmit pin of CAN controller [bit2] NIE: Node status transition interrupt enable bit This bit enables or disables a node status transition interrupt (when NT = 1). 0: Node status transition interrupt disabled 1: Node status transition interrupt enabled [bit0] HALT: Bus operation stop bit This bit sets or cancels the bus operation stop, or indicates its status. Reading this bit 0 : Bus operation not in stop state 1 : Bus operation in stop state Writing to this bit 0 : Cancels bus operation stop 1 : Sets bus operation stop Note: When "0" is written to this bit during the node status is Bus Off, ensure that "1" is written to this bit. Example program: switch ( IO_CANCTO.CSR.bit.NS ) { case 0 : /* error active */ break; case 1 : /* warning */ break; case 2 : /* error passive */ break; default : /* bus off */ for ( i=0; ( i<=500 ) && ( IO_CANCTO.CSR.bit.HALT==0); i++); IO_CANCTO.CSR.word = 0x0084; /* HALT = 0 */ break; } * The variable "i" is used for fail-safe. 293 CHAPTER 19 CAN CONTROLLER 19.6.2 Bus Operation Stop Bit (HALT = 1) The bus operation stop bit initiates or cancels bus operation stop, or displays its state. ■ Conditions for Setting Bus Operation Stop (HALT = 1) One of the following three conditions initiates bus operation stop (HALT = 1): • After hardware reset • When node status changed to bus off • By writing 1 to HALT Note: The bus operation should be stopped by writing 1 to HALT before the F2MC-16LX is changed in low-power consumption mode (stop mode, timer mode, and hardware stand-by mode). If transmission is in progress when 1 is written to HALT, the bus operation is stopped (HALT = 1) after transmission is terminated. If reception is in progress when 1 is written to HALT, the bus operation is stopped immediately (HALT = 1). If received messages are being stored in the message buffer (x), stop the bus operation (HALT = 1) after storing the messages. To check whether the bus operation has stopped, always read the HALT bit. When write "0" to this bit during the node status is Bus Off, ensure that "1" is written to this bit. ■ Conditions for Canceling Bus Operation Stop (HALT = 0) By writing 0 to HALT Note: Canceling the bus operation stop after hardware reset or by writing 1 to HALT as above conditions is performed after 0 is written to HALT and continuous 11-bit High levels (recessive bits) have been input to the receive input pin (RX) (HALT = 0). Canceling the bus operation stop when the node status is changed to bus off as above conditions is performed after 0 is written to HALT and continuous 11-bit High levels (recessive bits) have been input 128 times to the receive input pin (RX) (HALT = 0). Then, the values of both transmit and receive error counters reach 0 and the node status is changed to error active. When 0 is written to HALT bit during the node status is Bus Off, ensure that 1 is written to this bit. ■ State during Bus Operation Stop (HALT = 1) • The bus does not perform any operation, such as transmission and reception. • The transmit output pin (TX) outputs a High level (recessive bit). • The values of other registers and error counters are not changed. Note: The bit timing register (BTR) should be set during bus operation stop (HALT = 1). 294 CHAPTER 19 CAN CONTROLLER 19.6.3 Last Event Indicator Register (LEIR) This register indicates the last event. The NTE, TCE, and RCE bits are exclusive. When the bit of the last event is set to 1, other bits are set to 0s. ■ Last Event Indicator Register (LEIR) 7 bit Address: 001B02H NTE 6 TCE 5 4 3 2 1 0 RCE — MBP3 MBP2 MBP1 MBP0 Read/write: (R/W) (R/W) (R/W) (—) (R/W) (R/W) (R/W) (R/W) Initial value: (0) (0) (0) (—) (0) (0) (0) (0) R/W : Readable/Writable : Undefined [bit7] NTE: Node status transition event bit When this bit is 1, it indicates that node status transition is the last event. This bit is set to 1 at the same time as the NT bit of the control status register (CSR). This bit is also set to 1, irrespective of the setting of the node status transition interrupt enable bit (NIE) of the CSR. Writing 0 to this bit sets the NT bit to 0. Writing 1 to this bit is ignored. 1 is read when read-modify-write instruction is read. [bit6] TCE: Transmit completion event bit When this bit is 1, it indicates that transmit completion is the last event. This bit is set to 1 at the same time as any one of the bits of the transmit completion register (TCR). This bit is also set to 1, irrespective of the settings of the bits of the transmit interrupt enable register (TIER). Writing 0 sets this bit to 0. Writing 1 to this bit is ignored. 1 is read when read-modify-write instruction is read. When this bit is set to 1, the MBP3 to MBP0 bits are used to indicate the numbers of the message buffers completing the transmit operation. [bit5] RCE: Receive completion event bit When this bit is 1, it indicates that receive completion is the last event. This bit is set to 1 at the same time as any one of the bits of the receive complete register (RCR). This bit is also set to 1 irrespective of the settings of the bits of the receive interrupt enable register (RIER). Writing 0 sets this bit to 0. Writing 1 to this bit is ignored. 1 is read when read-modify-write instruction is read. When this bit is set to 1, the MBP3 to MBP0 bits are used to indicate the numbers of the message buffers completing the receive operation. 295 CHAPTER 19 CAN CONTROLLER [bit3 to bit0] MBP3 to MBP0: Message buffer pointer bits When the TCE or RCE bit is set to 1, these bits indicate the corresponding numbers of the message buffers (0 to 15). If the NTE bit is set to 1, these bits have no meaning. Writing 0 sets these bits to 0s. Writing 1 to these bits is ignored. 1s are read when read-modify-write instruction is read. If LEIR is accessed within an CAN interrupt handler, the event causing the interrupt in not necessarily the same as indicated by LEIR. In the time from interrupt request to the LEIR access within the interrupt handler there may occur other CAN events. 296 CHAPTER 19 CAN CONTROLLER 19.6.4 Receive and Transmit Error Counters (RTEC) The receive and transmit error counter indicates the receive and transmit error counts specified in the CAN specifications. This register is for read only. ■ Receive and Transmit Error Counters (RTEC) bit Address: 001B05H 14 13 12 11 10 9 8 TEC2 TEC1 TEC0 TEC7 TEC6 TEC5 TEC4 TEC3 Read/write: (R) (R) (R) (R) (R) (R) (R) (R) Initial value: (0) (0) (0) (0) (0) (0) (0) (0) 7 6 5 4 3 2 1 0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 Read/write: (R) (R) (R) (R) (R) (R) (R) (R) Initial value: (0) (0) (0) (0) (0) (0) (0) (0) bit Address: 001B04H R 15 : Read only [bit15 to bit8] TEC7 to TEC0: Transmit error counter These are transmit error counters. TEC7 to TEC0 values indicate 0 to 7 when the counter value is more than 256, and the subsequent increment is not counted for counter value. In this case, Bus Off is indicated for the node status (NS1 and NS0 of control status register CSR = 11). [bit7 to bit0] REC7 to REC0: Receive error counter These are receive error counters. REC7 to REC0 values indicate 0 to 7 when the counter value is more than 256, and the subsequent increment is not counted for counter value. In this case, Error Passive is indicated for the node status (NS1 and NS0 of control status register CSR = 10). 297 CHAPTER 19 CAN CONTROLLER 19.6.5 Bit Timing Register (BTR) This register sets the prescaler and bit timing. ■ Bit Timing Register (BTR) bit Address: 001B07H 15 14 — TS2.2 13 TS2.1 12 TS2.0 11 TS1.3 10 9 8 TS1.2 TS1.1 TS1.0 Read/write: (—) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (—) (1) (1) (1) (1) (1) (1) (1) 7 6 5 4 3 2 1 0 Address: 001B06H RSJ1 RSJ0 PSC5 PSC4 PSC3 PSC2 PSC1 PSC0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (1) (1) (1) (1) (1) (1) (1) (1) bit R/W : Readable/Writable : Undefined Note: This register should be set during bus operation stop (HALT = 1). [bit14 to bit12] TS2.2 to TS2.0: Time segment 2 setting bit2 to bit0 These bits cause the time quanta (TQ) to undergo [(TS2.2 to TS2.0) +1] frequency division to determine time segment 2 (TSEG2). The time segment 2 is equal to the phase buffer segment 2 (PHASE_SEG2) in the CAN specification. [bit11 to bit8] TS1.3 to TS1.0: Time segment 1 setting bit3 to bit0 These bits cause the time quanta (TQ) to undergo [(TS1.3 to TS1.0) +1] frequency division to determine time segment 1 (TSEG1). The time segment 1 is equal to the propagation segment (PROP_SEG) + phase buffer segment 1 (PHASE_SEG1) in the CAN specification. [bit7, bit6] RSJ1, RSJ0: Resynchronization jump width setting bit1, bit0 These bits cause the time quanta (TQ) to undergo [(RSJ1 to RSJ0) +1] frequency division to determine the resynchronization jump width. [bit5 to bit0] PSC5 to PSC0: Prescaler setting bit5 to bit0 These bits cause the input clock to undergo [(PSC5 to PSC0) +1] frequency division to determine the time quanta (TQ) of the CAN controller. The bit time segments in the CAN specification, CAN controller are shown in Figure 19.6-2 and Figure 19.6-3 respectively. 298 CHAPTER 19 CAN CONTROLLER Figure 19.6-2 Bit Time Segment in CAN Specification Nominal bit time SYNC_SEG PROP_SEG PHASE_SEG1 PHASE_SEG2 Sample point Figure 19.6-3 Bit Time Segment in CAN Controller Nominal bit time SYNC_SEG TSEG1 TSEG2 Sample point The relationship between PSC = PSC5 to PSC0, TSI = TS1.3 to TS1.0, TS2 = TS2.2 to TS1.0, and RSJ = RSJ1 and RSJ0 when the input clock (CLK), time quanta (TQ), bit time (BT), synchronous segment (SYNC_ SEG), time segment 1 and 2 (TSEG1 and TSEG2), and resynchronization jump width [(RSJ1 and RSJ0) +1] frequency division is shown below. TQ BT = (PSC + 1) x CLK = SYNC_SEG + TSEG1 + TSEG2 = (1 + (TS1 + 1) + (TS2 +1)) x TQ = (3 + TS1 +TS2) x TQ RSJW = (RSJ + 1) x TQ 299 CHAPTER 19 CAN CONTROLLER For correct operation, the following conditions should be met. Device with "G" suffix: For 1 PSC TSEG1 TSEG1 TSEG2 TSEG2 For PSC = 0: TSEG1 TSEG2 TSEG2 63: 2TQ RSJW 2TQ RSJW 5TQ 2TQ RSJW Device without "G" suffix: For 1 PSC 63: TSEG1 RSJW TSEG2 RSJW + 2TQ For PSC = 0: TSEG1 5TQ TSEG2 RSJW + 2TQ In order to meet the bit timing requirements defined in the CAN specification, additions have to be met, e.g. the propagation delay has to be considered. 300 CHAPTER 19 CAN CONTROLLER 19.6.6 Message Buffer Control Registers (BVALR) The message buffer valid register (BVALR) validates or invalidates a message buffer (x) or indicates the state of the buffer. ■ Message Buffer Valid Register (BVALR) bit Address: 000081H 15 14 13 12 11 10 9 BVAL15 BVAL14 BVAL13 BVAL12 BVAL11 BVAL10 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (0) (0) (0) (0) (0) (0) (0) (0) 7 6 5 4 3 2 1 0 Address: 000080H BVAL7 BVAL6 BVAL5 BVAL4 BVAL3 BVAL2 BVAL1 BVAL0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (0) (0) (0) (0) (0) (0) (0) (0) bit BVAL9 8 BVAL8 R/W : Readable/Writable 0: Message buffer (x) invalid 1: Message buffer (x) valid If the message buffer (x) is set to invalid, it will not transmit or receive messages. If the buffer is set to invalid during transmission operating, it becomes invalid (BVALx = 0) after the transmission is completed or terminated by an error. If the buffer is set to invalid during reception operating, it immediately becomes invalid (BVALx = 0). If received messages are stored in a message buffer (x), the message buffer (x) is invalid after storing the messages. Note: x indicates a message buffer number (x = 0 to 15). When invaliding a message buffer (x) by writing 0 to a bit (BVALx), execution of a bit manipulation instruction is prohibited until the bit is set to 0. To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while CAN Controller is participating in CAN communication (the read value of the CSR: HALT bit is 0 and CAN Controller is ready to receive or transmit messages), follow the cautions in Section 19.14 "Precautions when Using CAN Controller". 301 CHAPTER 19 CAN CONTROLLER 19.6.7 IDE Register (IDER) This register sets the frame format used by the message buffer (x) during transmission/reception. ■ IDE Register (IDER) bit 15 14 Address: 001B09H IDE15 IDE14 Read/write: (R/W) (R/W) Initial value: (X) 13 11 10 9 8 IDE12 IDE11 IDE10 IDE9 IDE8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 Address: 001B08H IDE7 IDE6 IDE5 IDE4 IDE3 IDE2 IDE1 IDE0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (X) (X) (X) (X) (X) (X) (X) (X) bit IDE13 12 R/W : Readable/Writable X : Undefined 0: The standard frame format (ID11 bit) is used for the message buffer (x). 1: The extended frame format (ID29 bit) is used for the message buffer (x). Note: This register should be set when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) = 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while CAN Controller is participating in CAN communication (the read value of the CSR: HALT bit is 0 and CAN Controller is ready to receive or transmit messages), follow the cautions in Section 19.14 "Precautions when Using CAN Controller". 302 CHAPTER 19 CAN CONTROLLER 19.6.8 Transmission Request Register (TREQR) Transmission request register (TREQR) sets a transmission request to the message buffer (x) or displays its state. ■ Transmission Request Register (TREQR) bit 15 14 13 12 9 8 TREQ10 TREQ9 TREQ8 TREQ14 TREQ13 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (0) (0) (0) (0) (0) (0) (0) (0) 7 6 5 4 3 2 1 0 Address: 000082H TREQ7 TREQ6 TREQ5 TREQ4 TREQ3 TREQ2 TREQ1 TREQ0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (0) (0) (0) (0) (0) (0) (0) (0) bit TREQ11 10 TREQ15 Address: 000083H TREQ12 11 R/W : Readable/Writable When 1 is written to TREQx, transmission to the message buffer (x) starts. If RFWTx of the remote frame receiving wait register (RFWTR)*1 is 0, transmission starts immediately. However, if RFWTx = 1, transmission starts after waiting until a remote frame is received (RRTRx of the remote request receiving register (RRTRR)*1 becomes 1). Transmission starts*2 immediately even when RFWTx = 1, if RRTRx is already 1 when 1 is written to TREQx. *1: For RFWTR and TRTRR, see "19.6.9 Transmission RTR Register (TRTRR)" and "19.6.10 Remote Frame Receiving Wait Register (RFWTR)". *2: For cancellation of transmission, see "19.6.11 Transmission Cancel Register (TCANR)" and "19.6.12 Transmission Complete Register (TCR)". Writing 0 to TREQx is ignored. 0 is read when read-modify-write instruction is read. If clearing (to 0) at completion of the transmit operation and setting by writing 1 are concurrent, clearing is preferred. If 1 is written to more than one bit, transmission is performed, starting with the lower-numbered message buffer (x). TREQx is 1 while transmission is pending, and becomes 0 when transmission is completed or canceled. 303 CHAPTER 19 CAN CONTROLLER 19.6.9 Transmission RTR Register (TRTRR) This register sets the RTR (Remote Transmission Request) bit during transmission by the message buffer (x). ■ Transmission RTR Register (TRTRR) 15 bit Address: 001B0BH 14 13 TRTR15 TRTR14 TRTR13 Read/write: (R/W) (R/W) Initial value: (0) 11 10 9 8 TRTR12 TRTR11 TRTR10 TRTR9 TRTR8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) 7 6 5 4 3 2 1 0 Address: 001B0AH TRTR7 TRTR6 TRTR5 TRTR4 TRTR3 TRTR2 TRTR1 TRTR0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (0) (0) (0) (0) (0) (0) (0) (0) bit R/W : Readable/Writable 0: Data frame transmitted 1: Remote frame transmitted 304 12 CHAPTER 19 CAN CONTROLLER 19.6.10 Remote Frame Receiving Wait Register (RFWTR) Remote frame receiving wait register (RFWTR) sets the condition for starting transmission when a request for data frame transmission is set (TREQx of the transmission request register (TREQR) is 1 and TRTRx of the transmitting RTR register (TRTRR) is 0). 0: Transmission starts immediately 1: Transmission starts after waiting until remote frame received (RRTRx of remote request receiving register (RRTRR) becomes 1) ■ Remote Frame Receiving Wait Register (RFWTR) bit Address: 001B0DH 15 RFWT15 14 RFWT14 13 RFWT13 12 11 10 9 RFWT12 RFWT11 RFWT10 RFWT9 8 RFWT8 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (X) (X) (X) (X) (X) (X) (X) (X) bit 7 6 5 4 3 2 1 0 Address: 001B0CH RFWT7 RFWT6 RFWT5 RFWT4 RFWT3 RFWT2 RFWT1 RFWT0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (X) (X) (X) (X) (X) (X) (X) (X) R/W : Readable/Writable : Undefined X Note: Transmission starts immediately if RRTRx is already 1 when a request for transmFor remote frame transmission, do not set RFWTx to 1.ission is set. 305 CHAPTER 19 CAN CONTROLLER 19.6.11 Transmission Cancel Register (TCANR) When 1 is written to TCANx, this register cancels a pending request for transmission to the message buffer (x). At completion of transmission, TREQx of the transmission request register (TREQR) becomes 0. Writing 0 to TCANx is ignored. This is a write only register and its read value is always 0. ■ Transmission Cancel Register (TCANR) bit Address: 000085H 13 12 11 10 9 8 TCAN14 TCAN13 TCAN12 TCAN11 TCAN10 TCAN9 TCAN8 Read/write: (W) (W) (W) (W) (W) (W) (W) (W) Initial value: (0) (0) (0) (0) (0) (0) (0) (0) 7 6 5 4 3 2 1 0 TCAN7 TCAN6 TCAN5 TCAN3 TCAN2 TCAN1 TCAN0 Read/write: (W) (W) (W) (W) (W) (W) (W) (W) Initial value: (0) (0) (0) (0) (0) (0) (0) (0) Address: 000084H 306 14 TCAN15 bit R 15 : Write only TCAN4 CHAPTER 19 CAN CONTROLLER 19.6.12 Transmission Complete Register (TCR) At completion of transmission by the message buffer (x), the corresponding TCx becomes 1. If TIEx of the transmission complete interrupt enable register (TIER) is 1, an interrupt occurs. ■ Transmission Complete Register (TCR) bit 15 14 13 12 11 10 9 8 Address: 000087H TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (0) (0) (0) (0) (0) (0) (0) (0) 7 6 5 4 3 2 1 0 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (0) (0) (0) (0) (0) (0) (0) (0) bit Address: 000086H R/W : Readable/Writable ❍ Conditions for TCx = 0 • Write 0 to TCx. • Write 1 to TREQx of the transmission request register (TREQR). After the completion of transmission, write 0 to TCx to set it to 0. Writing 1 to TCx is ignored. 1 is read when read-modify-write instruction is read. Note: If setting (to 1) at completion of the transmit operation and clearing by writing 0 are concurrent, setting is preferred. 307 CHAPTER 19 CAN CONTROLLER 19.6.13 Transmission Interrupt Enable Register (TIER) This register enables or disables the transmission interrupt by the message buffer (x). The transmission interrupt is generated at transmission completion (when TCx of the transmission complete register (TCR) is 1). ■ Transmission Interrupt Enable Register (TIER) bit 15 14 13 12 11 10 9 8 Address: 001B0FH TIE15 TIE14 TIE13 TIE12 TIE11 TIE10 TIE9 TIE8 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (0) (0) (0) (0) (0) (0) (0) (0) 7 6 5 4 3 2 1 0 TIE7 TIE6 TIE5 TIE4 TIE3 TIE2 TIE1 TIE0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (0) (0) (0) (0) (0) (0) (0) (0) bit Address: 001B0EH R/W : Readable/Writable 0: Transmission interrupt disabled 1: Transmission interrupt enabled 308 CHAPTER 19 CAN CONTROLLER 19.6.14 Reception Complete Register (RCR) At completion of storing received messages in the message buffer (x), RCx becomes 1. If RIEx of the reception complete interrupt enable register (RIER) is 1, an interrupt occurs. ■ Reception Complete Register (RCR) bit 15 14 13 12 11 10 9 8 Address: 000089H RC15 RC14 RC13 RC12 RC11 RC10 RC9 RC8 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (0) (0) (0) (0) (0) (0) (0) (0) 7 6 5 4 3 2 1 0 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (0) (0) (0) (0) (0) (0) (0) (0) bit Address: 000088H R/W : Readable/Writable ❍ Conditions for RCx = 0 Write 0 to RCx. After completion of storing received messages, write 0 to RCx to set it to 0. Writing 1 to RCx is ignored. 1 is read when read-modify-write instruction is read. Note: If setting (to 1) at completion of the receive operation and clearing by writing 0 are concurrent, setting is preferred. 309 CHAPTER 19 CAN CONTROLLER 19.6.15 Remote Request Receiving Register (RRTRR) After a received remote frame is stored in the message buffer (x), RRTRx becomes 1 (at the same time as RCx setting to 1). ■ Remote Request Receiving Register (RRTRR) bit Address: 00008BH 15 RRTR15 14 RRTR14 13 12 11 RRTR13 RRTR12 RRTR11 10 9 8 RRTR10 RRTR9 RRTR8 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (0) (0) (0) (0) (0) (0) (0) (0) 7 6 5 4 3 2 1 0 Address: 00008AH RRTR7 RRTR6 RRTR5 RRTR4 RRTR3 RRTR2 RRTR1 RRTR0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (0) (0) (0) (0) (0) (0) (0) (0) bit R/W : Readable/Writable ❍ Conditions for RRTRx = 0 • Write 0 to RRTRx. • After a received data frame is stored in the message buffer (x) (at the same time as RCx setting to 1). • Transmission by the message buffer (x) is completed (TCx of the transmission complete register (TCR) is 1). Writing 1 to RRTRx is ignored. 1 is read when read-modify-write instruction is read. Note: If setting (to 1) and clearing by writing 0 are concurrent, setting is preferred. 310 CHAPTER 19 CAN CONTROLLER 19.6.16 Receive Overrun Register (ROVRR) If RCx of the reception complete register (RCR) is 1 when completing storing of a received message in the message buffer (x), ROVRx becomes 1, indicating that reception has overrun. ■ Receive Overrun Register (ROVRR) 15 bit Address: 00008DH 14 13 12 11 10 9 8 ROVR15 ROVR14 ROVR13 ROVR12 ROVR11 ROVR10 ROVR9 ROVR8 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (0) (0) (0) (0) (0) (0) (0) (0) 7 6 5 4 3 2 1 0 ROVR6 ROVR5 ROVR4 ROVR3 ROVR2 ROVR1 ROVR0 bit Address: 00008CH ROVR7 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (0) (0) (0) (0) (0) (0) (0) (0) R/W : Readable/Writable Writing 0 to ROVRx results in ROVRx = 0. Writing 1 to ROVRx is ignored. After checking that reception has overrun, write 0 to ROVRx to set it to 0. 1 is read when read-modify-write instruction is read. Note: If setting (to 1) and clearing by writing 0 are concurrent, setting is preferred. 311 CHAPTER 19 CAN CONTROLLER 19.6.17 Reception Interrupt Enable Register (RIER) This register enables or disables the reception interrupt by the message buffer (x). The reception interrupt is generated at reception completion (when RCx of the reception completion register (RCR) is 1). ■ Reception Interrupt Enable Register (RIER) bit Address: 00008FH 15 RIE15 14 RIE14 13 12 11 RIE13 RIE12 RIE11 9 8 RIE10 RIE9 RIE8 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (0) (0) (0) (0) (0) (0) (0) (0) 7 6 5 4 3 2 1 0 Address: 00008EH RIE7 RIE6 RIE5 RIE4 RIE3 RIE2 RIE1 RIE0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (0) (0) (0) (0) (0) (0) (0) (0) bit R/W : Readable/Writable 0: Reception interrupt disabled 1: Reception interrupt enabled 312 10 CHAPTER 19 CAN CONTROLLER 19.6.18 Acceptance Mask Select Register (AMSR) This register selects a mask (acceptance mask) for comparison between the received message ID and the message buffer (x) ID. ■ Acceptance Mask Select Register (AMSR) BYTE0 bit 7 6 5 4 3 2 1 0 AMS3.1 AMS3.0 AMS2.1 AMS2.0 AMS1.1 AMS1.0 AMS0.1 AMS0.0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (X) (X) (X) (X) (X) (X) (X) (X) 11 10 9 8 AMS6.0 AMS5.1 AMS5.0 AMS4.1 AMS4.0 Address: 001B10H BYTE1 bit 15 Address: 001B11H 14 13 AMS7.1 AMS7.0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 AMS11.1 AMS11.0 AMS9.1 AMS9.0 AMS8.1 AMS8.0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (X) (X) (X) (X) (X) (X) (X) (X) 11 10 9 8 bit BYTE2 Address: 001B12H BYTE3 bit Address: 001B13H 15 AMS15.1 14 AMS6.1 12 AMS10.1 AMS10.0 13 AMS15.0 AMS14.1 12 AMS14.0 AMS13.1 AMS13.0 AMS12.1 AMS12.0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (X) (X) (X) (X) (X) (X) (X) (X) R/W : Readable/Writable X : Undefined 313 CHAPTER 19 CAN CONTROLLER Table 19.6-2 Selection of Acceptance Mask AMSx.1 AMSx.0 Acceptance MasK 0 0 Full-bit comparison 0 1 Full-bit mask 1 0 Acceptance mask register 0 (AMR0) 1 1 Acceptance mask register 1 (AMR1) Note: AMSx.1 and AMSx.0 should be set when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while CAN Controller is participating in CAN communication (the read value of the CSR: HALT bit is 0 and CAN Controller is ready to receive or transmit messages), follow the cautions in Section 19.14 "Precautions when Using CAN Controller". 314 CHAPTER 19 CAN CONTROLLER 19.6.19 Acceptance Mask Registers 0 and 1 (AMR0/AMR1) There are two acceptance mask registers, AMR0 and AMR1, both of which are available either in the standard frame format or extended frame format. AM28 to AM18 (11 bits) are used for acceptance masks in the standard frame format and AM28 to AM0 (29 bits) are used for acceptance masks in the extended format. ■ Acceptance Mask Registers 0 and 1 (AMR0/AMR1) AMR0 BYTE0 7 6 5 4 3 2 1 0 Address: 001B14H AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (X) AMR0 BYTE1 bit bit (X) (R/W) (R/W) (X) (X) (X) (X) (X) (X) 11 10 9 8 AM15 AM14 AM13 (R/W) (R/W) 15 14 13 12 Address: 001B15H AM20 AM19 AM18 AM17 AM16 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 AM12 AM11 AM10 AM9 AM8 AM7 AM6 AM5 (R/W) (R/W) AMR0 BYTE2 bit Address: 001B16H Read/write: (R/W) Initial value: (X) AMR0 BYTE3 bit (R/W) (X) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) 12 11 10 9 8 AM1 AM0 — — — 15 14 13 AM4 AM3 AM2 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (—) (—) (—) Initial value: (X) (X) (X) (X) (X) (—) (—) (—) Address: 001B17H R/W : Readable/Writable X : Undefined : Undefined (Continued) 315 CHAPTER 19 CAN CONTROLLER (Continued) AMR1 BYTE0 bit 7 6 5 4 3 2 1 0 Address: 001B18H AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21 Read/write: (R/W) (R/W) (R/W) Initial value: (X) AMR1 BYTE1 bit 15 (X) 14 (X) 13 (R/W) (X) 12 (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) 11 10 9 8 Address: 001B19H AM20 AM19 AM18 Read/write: (R/W) (R/W) (R/W) Initial value: (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 Address: 001B1AH AM12 AM11 AM10 AM9 AM8 AM7 AM6 AM5 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (X) (X) (X) (X) (X) (X) (X) (X) 13 12 11 10 9 8 bit AMR1 BYTE2 AMR1 BYTE3 bit 15 14 AM4 AM3 AM2 Read/write: (R/W) (R/W) Initial value: (X) (X) Address: 001B1BH AM17 (R/W) AM16 (R/W) AM15 (R/W) AM14 (R/W) AM13 (R/W) AM1 AM0 — — — (R/W) (R/W) (R/W) (—) (—) (—) (X) (X) (X) (—) (—) (—) R/W : Readable/Writable X : Undefined : Undefined ❍ 0: Compare Compare the bit of the acceptance code (ID register IDRx for comparing with the received message ID) corresponding to this bit with the bit of the received message ID. If there is no match, no message is received. ❍ 1: Mask Mask the bit of the acceptance code ID register (IDRx) corresponding to this bit. No comparison is made with the bit of the received message ID. Note: AMR0 and AMR1 should be set when all the message buffers (x) selecting AMR0 and AMR1 are invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffers are valid (BVALx = 1) may cause unnecessary received messages to be stored. To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while CAN Controller is participating in CAN communication (the read value of the CSR: HALT bit is 0 and CAN Controller is ready to receive or transmit messages), follow the cautions in Section 19.14 "Precautions when Using CAN Controller". 316 CHAPTER 19 CAN CONTROLLER 19.6.20 Message Buffers There are 16 message buffers. One message buffer x (x = 0 to 15) consists of an ID register (IDRx), DLC register (DLCRx), and data register (DTRx). ■ Message Buffers ❍ The message buffer (x) is used both for transmission and reception. ❍ The lower-numbered message buffers are assigned higher priority. • At transmission, when a request for transmission is made to more than one message buffer, transmission is performed, starting with the lowest-numbered message buffer (See Section "19.7 Transmission under CAN Controller"). • At reception, when the received message ID passes through the acceptance filter (mechanism for comparing the acceptance-masked ID of received message and message buffer) of more than one message buffer, the received message is stored in the lowestnumbered message buffer (See Section "19.9 CAN Controller Reception Flowchart"). ❍ When the same acceptance filter is set in more than one message buffer, the message buffers can be used as a multi-level message buffer. This provides allowance for receiving time (See Section "19.13 Deciding Multi-level Message Buffer Configuration"). Note: A write operation to message buffers and general-purpose RAM areas should be performed in words to even addresses only. A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is ignored. When the BVALx bit of the message buffer valid register (BVALR) is 0 (Invalid), the message buffers x (IDRx, DLCRx, and DTRx) can be used as general-purpose RAM. However, during the receive operation, there may be a maximum waiting time of 64 machine cycles. The same is true for the general-purpose RAM areas (addresses 001A00H to 001A1FH). 317 CHAPTER 19 CAN CONTROLLER 19.6.21 ID Register x (x = 0 to 15) (IDRx) This is the ID register for message buffer (x). ■ ID Register x (x = 0 to 15) (IDRx) BYTE0 bit 7 6 5 4 3 2 1 Address: 001A20H + 4x ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (X) (X) (X) (X) (X) (X) (X) (X) 13 12 11 10 9 8 BYTE1 bit 15 14 0 Address: 001A21H + 4x ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 ID9 ID8 ID7 ID6 ID5 BYTE2 bit ID12 ID11 ID10 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (X) (X) (X) (X) (X) (X) (X) (X) 13 12 11 10 9 8 Address: 001A22H + 4x BYTE3 bit 15 14 ID4 ID3 ID2 ID1 ID0 — — — Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (—) (—) (—) Initial value: (X) (X) (X) (X) (X) (—) (—) (—) Address: 001A23H + 4x R/W : Readable/Writable X : Undefined : Undefined When using the message buffer (x) in the standard frame format (IDEx of the IDE register (IDER) = 0), use 11 bits of ID28 to ID18. When using the buffer in the extended frame format (IDEx = 1), use 29 bits of ID28 to ID0. ID28 to ID0 have the following functions: ❍ Set acceptance code ID for comparing with the received message ID. 318 CHAPTER 19 CAN CONTROLLER ❍ Set transmitted message ID. Note: In the standard frame format, setting 1s to all bits of ID28 to ID22 is prohibited). ❍ Store the received message ID. Note: Received message IDs are also stored in acceptance-masked bits. In the standard frame format, ID17 to ID0 are undefined. Note: A write operation to this register should be performed in words. A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is ignored. This register should be set when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while CAN Controller is participating in CAN communication (the read value of the CSR: HALT bit is 0 and CAN Controller is ready to receive or transmit messages), follow the cautions in Section 19.14 "Precautions when Using CAN Controller". 319 CHAPTER 19 CAN CONTROLLER 19.6.22 DLC Register x (x = 0 to 15) (DLCRx) This is the DLC register for message buffer x. ■ DLC Register x (x = 0 to 15) (DLCRx) bit Address: 001A60H + 2x Read/write: Initial value: R/W : Readable/Writable X : Undefined : Undefined 7 6 5 4 3 2 1 0 — — — — DLC3 DLC2 DLC1 DLC0 (—) (—) (—) (—) (R/W) (R/W) (R/W) (R/W) (—) (—) (—) (—) (X) (X) (X) (X) ❍ Transmission • Set the data length (byte count) of a transmitted message when a data frame is transmitted (TRTRx of the transmitting RTR register (TRTRR) is 0). • Set the data length (byte count) of a requested message when a remote frame is transmitted (TRTRx = 1). Note: Setting other than 0000 to 1000 (0 to 8 bytes) is prohibited. ❍ Reception • Store the data length (byte count) of a received message when a data frame is received (RRTRx of the remote frame request receiving register (RRTRR) is 0). • Store the data length (byte count) of a requested message when a remote frame is received (RRTRx = 1). Note: A write operation to this register should be performed in words. A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte, and causes undefined data to be written to the lower byte at writing to the upper byte. 320 CHAPTER 19 CAN CONTROLLER 19.6.23 Data Register x (x = 0 to 15) (DTRx) This is the data register for message buffer (x). This register is used only in transmitting and receiving a data frame but not in transmitting and receiving a remote frame. ■ Data Register x (x = 0 to 15) (DTRx) BYTE0 bit 7 D7 Address: 001A80H + 8x 6 5 4 3 2 1 D6 D5 D4 D3 D2 D1 0 D0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (X) (X) (X) (X) (X) (X) (X) (X) 14 13 12 11 10 9 8 D7 D6 D5 D4 D3 D2 D1 D0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (X) (X) (X) (X) (X) (X) (X) (X) BYTE1 bit Address: 001A81H + 8x BYTE2 bit Address: 001A82H + 8x BYTE3 15 15 14 13 12 11 10 9 8 D7 D6 D5 D4 D3 D2 D1 D0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (X) (X) (X) (X) (X) (X) (X) (X) bit Address: 001A83H + 8x R/W : Readable/Writable X : Undefined (Continued) 321 CHAPTER 19 CAN CONTROLLER (Continued) BYTE4 bit 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (X) (X) (X) (X) (X) (X) (X) (X) 15 14 13 12 11 9 8 D7 D6 D5 D4 D3 D1 D0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Read/write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value: (X) (X) (X) (X) (X) (X) Address: 001A84H + 8x BYTE5 bit Address: 001A85H + 8x BYTE6 bit Address: 001A86H + 8x BYTE7 bit 7 15 14 D7 D6 Read/write: (R/W) (R/W) (R/W) Initial value: (X) (X) (X) Address: 001A87H + 8x 13 D5 (X) 10 D2 12 11 10 D4 D3 D2 (R/W) (X) 9 (R/W) (X) 8 D1 D0 (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) R/W : Readable/Writable X : Undefined ❍ Sets transmitted message data (any of 0 to 8 bytes). Data is transmitted in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB. ❍ Stores received message data. Data is stored in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB. Even if the received message data is less than 8 bytes, the remaining bytes of the data register (DTRx), to which data are stored, are undefined. Note: A write operation to this register should be performed in words. A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is ignored. 322 CHAPTER 19 CAN CONTROLLER 19.7 Transmission under CAN Controller When 1 is written to TREQx of the transmission request register (TREQR), transmission by the message buffer (x) starts. At this time, TREQx becomes 1 and TCx of the transmission complete register (TCR) becomes 0. ■ Starting Transmission If RFWTx of the remote frame receiving wait register (RFWTR) is 0, transmission starts immediately. If RFWTx is 1, transmission starts after waiting until a remote frame is received (RRTRx of the remote request receiving register (RRTRR) becomes 1). If a request for transmission is made to more than one message buffer (more than one TREQx is 1), transmission is performed, starting with the lowest-numbered message buffer. Message transmission to the CAN bus (by the transmit output pin TX) starts when the bus is idle. If TRTRx of the transmission RTR register (TRTRR) is 0, a data frame is transmitted. If TRTRx is 1, a remote frame is transmitted. If the message buffer competes with other CAN controllers on the CAN bus for transmission and arbitration fails, or if an error occurs during transmission, the message buffer waits until the bus is idle and repeats retransmission until it is successful. ■ Canceling a CAN Controller Transmission Request ❍ Canceling by transmission cancel register (TCANR) A transmission request for message buffer (x) having not executed transmission during transmission pending can be canceled by writing 1 to TCANx of the transmission cancel register (TCANR). At completion of cancellation, TREQx becomes 0. ❍ Canceling by storing received message The message buffer (x) having not executed transmission despite transmission request also performs reception. If the message buffer (x) has not executed transmission despite a request for transmission of a data frame (TRTRx = 0 or TREQx = 1), the transmission request is canceled after storing received data frames passing through the acceptance filter (TREQx = 0). Note: A transmission request is not canceled by storing remote frames (TREQx = 1 remains unchanged). If the message buffer (x) has not executed transmission despite a request for transmission of a remote frame (TRTRx = 1 or TREQx = 1), the transmission request is canceled after storing received remote frames passing through the acceptance filter (TREQx = 0). Note: The transmission request is canceled by storing either data frames or remote frames. 323 CHAPTER 19 CAN CONTROLLER ■ Completing CAN Controller Transmission When transmission is successful, RRTRx becomes 0, TREQx becomes 0, and TCx of the transmission complete register (TCR) becomes 1. If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt enable register (TIER) is 1), an interrupt occurs. ■ CAN Controller Transmission Flowchart Figure 19.7-1 shows a CAN controller transmission flowchart. Figure 19.7-1 CAN Controller Transmission Flowchart Detection of start of data frame or remote frame (SOF) NO Is any message buffer(x) passing to the acceptance filter found? YES NO Is reception successful? YES Determine message buffer(x) where received messages to be stored. Store the received message in the message buffer (x). 1 RCx? 0 Data frame ROVRx := 1 Remote frame Received message? RRTRx := 0 RRTRx := 1 1 TRTRx? 0 TREQx := 0 RCx := 1 RIEx ? 0 End of reception 324 1 A reception interrupt occurs. CHAPTER 19 CAN CONTROLLER 19.8 Reception under CAN Controller Reception starts when the start of data frame or remote frame (SOF) is detected on the CAN bus. ■ Acceptance Filtering The received message in the standard frame format is compared with the message buffer (x) set (IDEx of the IDE register (IDER) is 0) in the standard frame format. The received message in the extended frame format is compared with the message buffer (x) set (IDEx is 1) in the extended frame format. If all the bits set to Compare by the acceptance mask agree after comparison between the received message ID and acceptance code (ID register (IDRx) for comparing with the received message ID), the received message passes to the acceptance filter of the message buffer (x). ■ Storing Received Message When the receive operation is successful, received messages are stored in a message buffer x including IDs passed through the acceptance filter. When receiving data frames, received messages are stored in the ID register (IDRx), DLC register (DLCRx), and data register (DTRx). Even if received message data is less than 8 bytes, the data is stored in the remaining bytes of the DTRx and its value is undefined. When receiving remote frames, received messages are stored only in the IDRx and DLCRx, and the DTRx remains unchanged. If there is more than one message buffer including IDs passed through the acceptance filter, the message buffer x in which received messages are to be stored is determined according to the following rules. • The order of priority of the message buffer x (x = 0 to 15) rises as its number lower; in other words, message buffer 0 is given the highest and the message buffer 15 is given the lowest priority. • Basically, message buffers with the RCx bit of the receive completion register (RCR) set to 0 are preferred in storing received messages. • If the bits of the acceptance mask select register (AMSR) are set to All Bits Compare (for message buffers with the AMSx.1 and AMSx.0 bits set to 00), received messages are stored irrespective of the setting of the RCx bit of the RCR. • If there are message buffers with the RCx bit of the RCR set to 0, or with the bits of the AMSR set to All Bits Compare, received messages are stored in the lowest-number (highestpriority) message buffer x. • If there are no message buffers above-mentioned, received messages are stored in a lowernumber message buffer x. Figure 19.8-1 shows the flowchart in determining the message buffer x where received messages are to be stored. Message buffers should be arranged in ascending numeric order; that is, message buffer with the bits of the AMSR set to All Bits Compare, message buffer using AMR0 or AMR1, and message buffer with the bits of the AMSR set to All Bits Mask. 325 CHAPTER 19 CAN CONTROLLER Figure 19.8-1 Flowchart Determining Message Buffer (x) Where Received Messages Stored Start Are message buffers with RCx set to "0" or with AMSx.1 and AMSx.0 set to "00" found? NO YES Select the lowest-numbered message buffer (of applicable message buffers with RCx set to "0" or with AMSx.1 and AMSx.0 set to "00"). Select the lowest-numbered message buffer (of applicable message buffers). End ■ Receive Overrun When the RCx bit of the receive complete register (RCR) corresponding to the message buffer x where received messages are to be stored is set to 1 and storing of received messages in the message buffer x is completed, the ROVRx bit of the receive overrun register (ROVRR) is set to 1, indicating receive overrun. ■ Processing for Reception of Data Frame and Remote Frame ❍ Processing for reception of data frame RRTRx of the remote request receiving register (RRTRR) becomes 0. TREQx of the transmission request register (TREQR) becomes 0 (immediately before storing the received message). A transmission request for message buffer (x) having not executed transmission will be canceled. Note: A request for transmission of either a data frame or remote frame is canceled. ❍ Processing for reception of remote frame RRTRx becomes 0. If TRTRx of the transmitting RTR register (TRTRR) is 1, TREQx becomes 0. A request for transmitting remote frame to message buffer having not executed transmission will be canceled. Note: A request for data frame transmission is not canceled. For cancellation of a transmission request, see Section "19.7 Transmission under CAN Controller". ■ Completing Reception RCx of the reception complete register (RCR) becomes 1 after storing the received message. If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is 1), an interrupt occurs. Note: This CAN controller will not receive any messages transmitted by itself. 326 CHAPTER 19 CAN CONTROLLER 19.9 CAN Controller Reception Flowchart Figure 19.9-1 shows a CAN controller reception flowchart. ■ CAN Controller Reception Flowchart Figure 19.9-1 CAN Controller Reception Flowchart Detection of start of data frame or remote frame (SOF) NO Is any message buffer(x) passing to the acceptance filter found? YES NO Is reception successful? YES Determine message buffer(x) where received messages to be stored. Store the received message in the message buffer (x). 1 RCx? 0 Data frame ROVRx := 1 Remote frame Received message? RRTRx := 0 RRTRx := 1 1 TRTRx? 0 TREQx := 0 RCx := 1 RIEx ? 0 1 A reception interrupt occurs. End of reception 327 CHAPTER 19 CAN CONTROLLER 19.10 Usage of CAN Controller The CAN controller requires the following settings: • Bit timing • Frame format • ID • Acceptance filter • Low power consumption mode ■ Setting Bit Timing The bit timing register (BTR) should be set during bus operation stop (when the bus operation stop bit (HALT) of the control status register (CSR) is 1). After the setting completion, write 0 to HALT to cancel bus operation stop. ■ Setting Frame Format Set the frame format used by the message buffer (x). When using the standard frame format, set IDEx of the IDE register (IDER) to 0. When using the extended frame format, set IDEx to 1. This setting should be made when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. ■ Setting ID Set the message buffer (x) ID to ID28 to ID0 of ID register (IDRx). The message buffer (x) ID need not be set to ID11 to ID0 in the standard frame format. The message buffer (x) ID is used as a transmission message at transmission and is used as an acceptance code at reception. This setting should be made when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. ■ Setting Acceptance Filter The acceptance filter of the message buffer (x) is set by an acceptance code and acceptance mask. It should be set when the acceptance message buffer (x) is invalid (BVALx of the message buffer enable register (BVALR) is 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. Set the acceptance mask used in each message buffer (x) by the acceptance mask select register (AMSR). The acceptance mask registers (AMR0 and AMR1) should also be set if used (For the setting details, see Section "19.6.17 Reception Interrupt Enable Register (RIER)" and "19.6.18 Acceptance Mask Select Register (AMSR)"). The acceptance mask should be set so that a transmission request may not be canceled when unnecessary received messages are stored. For example, it should be set to a full-bit comparison if receiving only the message of the same ID as transmission ID. 328 CHAPTER 19 CAN CONTROLLER ■ Setting Low-power Consumption Mode To set the F2MC-16LX in a low-power consumption mode (Stop, Watch, Hardware Standby, etc.), write 1 to the bus operation stop bit (HALT) of the control status register (CSR), and then check that the bus operation has stopped (HALT = 1). 329 CHAPTER 19 CAN CONTROLLER 19.11 Procedure for Transmission by Message Buffer (x) After setting the bit timing, frame format, ID, and acceptance filter, set BVALx to 1 to validate the message buffer (x). ■ Procedure for Transmission by Message Buffer (x) ❍ Setting transmit data length code Set the transmit data length code (byte count) to DLC3 to DLC0 of the DLC register (DLCRx). For data frame transmission (when TRTRx of the transmission RTR register (TRTRR) is 0), set the data length of the transmitted message. For data frame transmission (when TRTRx of the transmission RTR register (TRTRR) is 0), set the data length of the transmitted message. For remote frame transmission (when TRTRx = 1), set the data length (byte count) of the requested message. Note: Setting other than 0000 to 1000 (0 to 8 bytes) is prohibited. ❍ Setting transmit data (only for transmission of data frame) For data frame transmission (when TRTRx of the transmission register (TRTRR) is 0), set data as the count of byte transmitted in the data register (DTRx). Note: Transmit data should be rewritten with the TREQx bit of the transmission request register (TREQR) set to 0. There is no need for setting the BVALx bit of the message buffer valid register (BVALR) to 0. Setting the BVALx bit to 0 disables remote frame receiving. ❍ Setting transmission RTR register For data frame transmission, set TRTRx of the transmission RTR register (TRTRR) to 0. For remote frame transmission, set TRTRx to 1. ❍ Setting conditions for starting transmission (only for transmission of data frame) Set RFWTx of the remote frame receiving wait register (RFWTR) to 0 to start transmission immediately after a request for data frame transmission is set (TREQx of the transmission request register (TREQR) is 1 and TRTRx of the transmission RTR register (TRTRR) is 0). Set RFWTx to 1 to start transmission after waiting until a remote frame is received (RRTRx of the remote request receiving register (RRTRR) becomes 1) after a request for data frame transmission is set (TREQx = 1 and TRTRx = 0). Note: Remote frame transmission can not be made, if RFWTx is set to 1. 330 CHAPTER 19 CAN CONTROLLER ❍ Setting transmission complete interrupt When generating a transmission complete interrupt, set TIEx of the transmission complete interrupt enable register (TIER) to 1. When not generating a transmission complete interrupt, set TIEx to 0. ❍ Setting transmission request For a transmission request, set TREQx of the transmission request register (TREQR) to 1. ❍ Canceling transmission request When canceling a pending request for transmission to the message buffer (x), write 1 to TCANx of the transmission cancel register (TCANR). Check TREQx. For TREQx = 0, transmission cancellation is terminated or transmission is completed. Check TCx of the transmission complete register (TCR). For TCx = 0, transmission cancellation is terminated. For TCx = 1, transmission is completed. ❍ Processing for completion of transmission If transmission is successful, TCx of the transmission complete register (TCR) becomes 1. If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt enable register (TIER) is 1), an interrupt occurs. After checking the transmission completion, write 0 to TCx to set it to 0. This cancels the transmission complete interrupt. In the following cases, the pending transmission request is canceled by receiving and storing a message. • Request for data frame transmission by reception of data frame • Request for remote frame transmission by reception of data frame • Request for remote frame transmission by reception of remote frame Request for data frame transmission is not canceled by receiving and storing a remote frame. ID and DLC, however, are changed by the ID and DLC of the received remote frame. Note that the ID and DLC of data frame to be transmitted become the value of received remote frame. 331 CHAPTER 19 CAN CONTROLLER 19.12 Procedure for Reception by Message Buffer (x) After setting the bit timing, frame format, ID, and acceptance filter, make settings as shown below. ■ Procedure for Reception by Message Buffer (x) ❍ Setting reception interrupt When a reception interrupt is enabled, set RIEx of the reception interrupt enable register (RIER) to 1. When a reception interrupt is disabled, set RIEx to 0. ❍ Starting reception When starting reception after setting, set BVALx of the message buffer valid register (BVALR) to 1 to make the message buffer (x) valid. ❍ Processing for reception completion If reception is successful after passing to the acceptance filter, the received message is stored in the message buffer (x) and RCx of the reception complete register (RCR) becomes 1. For data frame reception, RRTRx of the remote request receiving register (RRTRR) becomes 0. For remote frame reception, RRTRx becomes 1. If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is 1), an interrupt occurs. After checking the reception completion (RCx = 1), process the received message. After completion of processing the received message, check ROVRx of the reception overrun register (ROVRR). For ROVRx = 0, the processed received message is valid. Write 0 to CRx to set it to 0 (the reception complete interrupt is also canceled) to terminate reception. For ROVRx = 1, a reception overrun occurred and the new received message may overwrite the processed received message. In this case, received messages should be processed again after setting the ROVRx bit to 0 by writing 0 to it. Figure 19.12-1 shows an example of receive interrupt handling. 332 CHAPTER 19 CAN CONTROLLER Figure 19.12-1 Example of Receive Interrupt Handling Interrupt with RCx = 1 Read received messages. A := ROVRx ROVRx := 0 A = 0? NO YES RCx := 0 End 333 CHAPTER 19 CAN CONTROLLER 19.13 Deciding Multi-level Message Buffer Configuration If the receptions are performed frequently, or if an unspecified count of message is received, in other words, if there is insufficient time for receiving messages, more than one message buffer can be combined into a multi-level message buffer to provide allowance for processing time of the received message by CPU. ■ Setting Configuration of Multi-level Message Buffer To provide a multi-level message buffer, the same acceptance filter must be set in the combined message buffers. If the bits of the acceptance mask select register (AMSR) are set to All Bits Compare ((AMSx.1, AMSx.0) = (0, 0)), multi-level message configuration of message buffers is not allowed. This is because All Bits Compare causes received messages to be stored irrespective of the value of the RCx bit of the receive completion register (RCR), so received messages are always stored in lower-numbered (lower-priority) message buffers even if All Bits Compare and identical acceptance code (ID register (IDRx)) are specified for more than one message buffer. Therefore, All Bits Compare and identical acceptance code should not be specified for more than one message buffer. Figure 19.13-1 shows operational examples of multi-level message buffers. 334 CHAPTER 19 CAN CONTROLLER Figure 19.13-1 Examples of Operation of Multi-level Message Buffer Initialization AMS15, AMS14, AMS13 AMSR 10 10 10 ... AM28 to AM18 Select AMR0. AMS0 ID28 to ID18 0000 1111 111 RC15, RC14, RC13 IDE ... Message buffer 13 0101 0000 000 0 ... RCR 0 0 0 ... Message buffer 14 0101 0000 000 0 ... ROVRR 0 0 0 ... Message buffer 15 0101 0000 000 0 ... ROVR15, ROVR14, ROVR13 Mask Message receiving " The received message is stored in message buffer 13. IDE ID28 to ID18 Message receiving 0101 1111 000 0 ... Message buffer 13 0101 1111 000 0 ... RCR 0 0 1 ... Message buffer 14 0101 0000 000 0 ... ROVRR 0 0 0 ... Message buffer 15 0101 0000 000 0 ... Message receiving " The received message is stored in message buffer 14. Message receiving 0101 1111 001 0 ... Message buffer 13 0101 1111 000 0 ... RCR 0 1 1 ... Message buffer 14 0101 1111 001 0 ... ROVRR 0 0 0 ... Message buffer 15 0101 0000 000 0 ... Message receiving " The received message is stored in message buffer 15. Message receiving 0101 1111 010 0 ... Message buffer 13 0101 1111 000 0 ... RCR 1 1 1 ... Message buffer 14 0101 1111 001 0 ... ROVRR 0 0 0 ... Message buffer 15 0101 1111 010 0 ... Message receiving " An overrun occurs (ROVR13 = 1) and the received message is stored in message buffer 13. Message receiving 0101 1111 011 0 ... Message buffer 13 0101 1111 011 0 ... RCR 1 1 1 ... Message buffer 14 0101 1111 001 0 ... ROVRR 0 0 1 ... Message buffer 15 0101 1111 010 0 ... Note: Four messages are received with the same acceptance filter set in message buffers 13, 14 and 15. 335 CHAPTER 19 CAN CONTROLLER 19.14 Precautions when Using CAN Controller Use of the CAN Controller requires the following cautions. ■ Caution for Disabling Message Buffers by BVAL Bits The use of BVAL bits may affect malfunction of CAN Controller when messages buffers are set disabled while CAN Controller is participating in CAN communication (read value of HALT bit is 0 and CAN Controller is ready to receive or transmit messages). This section shows the work around of this malfunction. ❍ Condition When following two conditions occur at the same time, CAN Controller will not perform to receive or transmit messages normally. • CAN Controller is participating in the CAN communication. (i.e. The read value of HALT bit is 0 and CAN Controller is ready to receive or transmit messages) • Message buffers are read or written when the message buffers are disabled by BVAL bits. ❍ Work around Operation for re-configuring receiving message buffers While CAN Controller is participating in CAN communication (the read value of HALT bit is 0 and CAN Controller is ready to receive or transmit messages), it is necessary to following one from the two operations described below to re-configure message buffers by ID, AMS and AMR0/1 register-settings. • Use of HALT bit Write 1 to HALT bit and read it back for checking the result is 1. Then change the settings for ID/AMS/AMR0/1 registers. • No Use of Message Buffer 0 Don't use the message buffer 0. In other words, disable message buffer (BVAL0=0), prohibit receive interrupt (RIE0=0) and do not request transmission (TREQ0=0). Operation for processing received message Don't use the receiving prohibition by BVAL bit to avoid over-written of next message. Use the ROVR bit for checking if over-write has been performed. For details, refer to sections 19.6.16 "Receive Overrun Register (ROVRR)" and 19.12 "Procedure for Reception by Message Buffer (x)". Operation for suppressing transmission request Don't use BVAL bit for suppressing transmission request, use TCAN bit instead of it. Operation for composing transmission message For composing a transmission message, it is necessary to disable the message buffer by BVAL bit to change contents of ID and IDE registers. In this case, BVAL bit should reset (BVAL=0) after checking if TREQ bit is 0 or after completion of the previous message transmission (TC=1). 336 CHAPTER 20 STEPPING MOTOR CONTROLLER CHAPTER 20 STEPPING MOTOR CONTROLLER This chapter explains the functions and operation of the stepping motor controller. 20.1 "Outline of Stepping Motor Controller" 20.2 "Stepping Motor Controller Registers" 337 CHAPTER 20 STEPPING MOTOR CONTROLLER 20.1 Outline of Stepping Motor Controller The Stepping Motor Controller consists of two PWM Pulse Generators, four motor drivers and the Selector Logic. The four motor drivers have high output drive capabilities and they can be directly connected to the four ends of two motor coils. The combination of the PWM Pulse Generators and Selector Logic is designed to control the rotation of the motor. A synchronization mechanism assures the synchronous operations of the two PWMs. The following sections describe the Stepping Motor Controller 0 only. The other controllers have the same function. The register addresses are found in the I/O map. ■ Stepping Motor Controller Block Diagram Figure 20.1-1 is a stepping motor controller block diagram. Figure 20.1-1 Block Diagram of Stepping Motor Controller Machine Clock OE1 CK PWM1P0 Prescaler Selector PWM1 pulse generator EN P1 PWM PWM1M0 P0 PWM1 Compare register PWM1 Select register OE2 CK EN Output enable PWM2P0 PWM2 pulse generator CE Selector PWM2M0 PWM Load PWM2 Compare register 338 Output enable BS PWM2 Select register CHAPTER 20 STEPPING MOTOR CONTROLLER 20.2 Stepping Motor Controller Registers The stepping motor controller registers include the following five types of registers: • PWM Control 0 register • PWM1 Compare 0 register • PWM2 Compare 0 register • PWM1 Select register • PWM2 Select register ■ Stepping Motor Controller Registers PWM Control 0 register Address: 00005EH bit Read/write Initial value 7 6 5 4 3 2 1 0 OE2 OE1 P1 P0 CE Reserved (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) PWC0 PWM1 Compare 0 register Address: bit 000070H Read/write Initial value PWM2 Compare 0 register Address: bit (R/W) (X) (R/W) (X) 15 14 13 12 11 10 9 8 D7 D6 D5 D4 D3 D2 D1 D0 (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) 000071H Read/write Initial value (R/W) (X) PWC10 PWC20 (R/W) (X) PWM1 Select register bit Address: 7 6 Read/write Initial value PWM2 Select register Address: 5 4 3 2 1 0 P2 P1 P0 M2 M1 M0 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) 000072H 000073H Read/write Initial value bit 15 14 13 12 11 10 9 BS P2 P1 P0 M2 M1 M0 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) PWS10 8 PWS20 R/W : Readable/Writable X : Undefined : Undefined 339 CHAPTER 20 STEPPING MOTOR CONTROLLER 20.2.1 PWM Control 0 Register The PWM control 0 register controls the start and stop of the stepping motor controller, controls interrupts, or sets external output pins. ■ PWM Control 0 Register PWM Control 0 register Address: 00005EH Read/write Initial value 7 6 5 4 3 2 1 0 OE2 OE1 P1 P0 CE Reserved (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) Bit number PWC0 R/W : Readable/Writable : Undefined [bit7] OE2: Output enable bit When this bit is set to "1", the external pins are assigned as PWM2P0 and PWM2M0 outputs. Otherwise they can be used as general purpose I/O. [bit6] OE1: Output enable bit When this bit is set to "1", the external pins are assigned as PWM1P0 and PWM1M0 outputs. Otherwise they can be used as general purpose I/O. [bit5, bit4] P1, P0: Operation clock select bits These bits specify the clock input signal for the PWM pulse generators. P1 P0 Clock input 0 0 Machine clock 0 1 1/2 Machine clock 1 0 1/4 Machine clock 1 1 1/8 Machine clock [bit3] CE: Count enable bit This bit enables the operation of the PWM pulse generators. When it is set to "1", the PWM pulse generators start their operation. Note that the PWM2 pulse generator starts the operation one machine clock cycle after the PWM1 pulse generators is started. This is to help reduce the switching noise from the output drivers. [bit0] Reserved This is a reserved bit. Always write "0" to this bit. 340 CHAPTER 20 STEPPING MOTOR CONTROLLER 20.2.2 PWM1 and PWM2 Compare Registers The contents of the two 8-bit compare registers determine the widths of PWM pulses. The stored value of "00H" represents the PWM duty of 0% and "FFH" represents the duty of 99.6%. ■ PWM1 and PWM2 Compare Registers These registers are accessible at any time, however the modified values are reflected to the pulse width at the end of the current PWM cycle after the BS bit of the PWM2 Select register is set to "1". PWM1 Compare 0 register Address: Read/write Initial value PWM2 Compare 0 register Address: 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) 000070H (R/W) (X) 15 14 13 12 11 10 9 8 D7 D6 D5 D4 D3 D2 D1 D0 (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) PWC10 (R/W) (X) 000071H Read/write Initial value Bit number Bit number PWC20 (R/W) (X) R/W : Readable/Writable X : Undefined One PWM Cycle 256 input clock cycles Register value 00H 80H 128 input clock cycles FFH 255 input clock cycles 341 CHAPTER 20 STEPPING MOTOR CONTROLLER 20.2.3 PWM1 and PWM2 Select Registers The PWM1 and PWM2 select registers are used to indicate whether the output of the external pin of the stepping motor controller is "0", "1", PWM pulse, or high impedance. ■ PWM1 and PWM2 Select Registers PWM1 Select register 7 Address: 6 Read/write Initial value PWM2 Select register Address: 5 4 3 2 1 0 P2 P1 P0 M2 M1 M0 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) 000072H 000073H Read/write Initial value 15 14 13 12 11 10 9 8 BS P2 P1 P0 M2 M1 M0 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) Bit number PWS10 Bit number PWS20 R/W : Readable/Writable : Undefined [bit14] BS: Update bit This bit is prepared to synchronize the settings for the PWM outputs. Any modifications in the two compare registers and two select registers are not reflected to the output signals until this bit is set. When this bit is set to "1", the PWM pulse generators and selectors load the register contents at the end of the current PWM cycle. The BS bit is reset to "0" automatically at the beginning of the next PWM cycle. If the BS bit is set to "1" by software at the same time as this automatic reset, the BS bit is set to "1" (or remains unchanged) and the automatic reset is cancelled. [bit13 to bit11] P2 to P0: Output Select bits These bits selects the output signal at PWM2P0. [bit10 to bit8] M2 to M0: Output Select bits These bits selects the output signal at PWM2M0. [bit5 to bit3] P2 to P0: Output Select bits These bits selects the output signal at PWM1P0. 342 CHAPTER 20 STEPPING MOTOR CONTROLLER [bit2 to bit0] M2 to M0: Output Select bits These bits selects the output signal at PWM1M0. The following table shows the relationship between the output levels and select bits. P2 P1 P0 PWMnP0 M2 M1 M0 PWMnM0 0 0 0 L 0 0 0 L 0 0 1 H 0 0 1 H 0 1 X PWM pulses 0 1 X PWM pulses 1 X X High impedance 1 X X High impedance 343 CHAPTER 20 STEPPING MOTOR CONTROLLER 344 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION This chapter explains the address match detection function and operation. 21.1 "Outline of the Address Match Detection Function" 21.2 "Registers of the Address Match Detection Function" 21.3 "Operation of the Address Match Detection Function" 21.4 "Example of the Address Match Detection Function" 345 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.1 Outline of the Address Match Detection Function When an address matches the value set in the address detection register, the instruction code to be read by the CPU is replaced with the INT9 instruction code (01H). Consequently, the CPU executes the INT9 instruction when executing a specified instruction. The address match detection function can be achieved using the INT9 interrupt routine for processing. There are two address detection registers, each with an interrupt permission bit. When an address matches the value set in the address detection register and the interrupt permission bit is 1, the instruction code to be read by the CPU is replaced with the INT9 instruction code. ■ Block Diagram of the Address Match Detection Function Address latch Address detection register Permission bit F2MC-16LX bus 346 Comparison Figure 21.1-1 Block Diagram of the Address Match Detection Function INT9 instruction F2MC-16LX CPU core CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.2 Registers of the Address Match Detection Function The two types of registers for the address match detection function are as follows: • Program address detection registers (PADR0 and PADR1) • Program address detection control status register (PACSR) ■ Program Address Detection Registers (PADR0 and PADR1) The program address detection registers 0 and 1 (PADR0 and PADR1) compare the address with the value written in each register. If they match when the interrupt permission bit corresponding to ADCSR is 1, the CPU is requested to issue the INT9 instruction. When the corresponding interrupt bit is 0, nothing occurs. Figure 21.2-1 Program Address Detection Registers (PADR0 and PADR1) Program address detection registers byte byte byte Access Initial value PADR0 1FF2H/1FF1H/1FF0H R/W Not defined PADR1 1FF5H/1FF4H/1FF3H R/W Not defined Table 21.2-1 lists the correspondence between the program address detection registers (PADR0 and PADR1) and PACSR. Table 21.2-1 Correspondence between PADR0 and PADR1 Registers and PACSR Address detection register Interrupt permission bit PADR0 AD0E PADR1 AD1E ■ Program Address Detection Control Status Register (PACSR) The program address detection control status register (PACSR) controls the operation of the address detection function. Figure 21.2-2 Program Address Detection Control Status Register (PACSR) Program address detection control status register bit Address: 009EH Read/write Initial value 7 6 5 4 2 AD1E Reserved 1 0 AD0E Reserved (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (R/W) (0) Reserved Reserved Reserved Reserved (R/W) (R/W) (R/W) (0) (0) (0) 3 PACSR R/W : Readable/Writable [bit7 to bit4] Reserved bits Bit7 to bit4 are reserved. Set these bits to 0 before setting PACSR. 347 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION [bit3] AD1E (Address detect register 1 enable) The AD1E bit is the operation permission bit of PADR1. When this bit is 1, the address is compared with the PADR1 register. If they match, the INT9 instruction is issued. [bit2] Reserved bit Bit2 is reserved. Set this bit to 0 before setting PACSR. [bit1] AD0E (Address Detect register 0 Enable) The AD0E bit is the operation permission bit of PADR0. When this bit is 1, the address is compared with the PADR0 register. If they match, the INT9 instruction is issued. [bit0] Reserved bit Bit0 is reserved. Set this bit to 0 before setting PACSR. 348 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.3 Operation of the Address Match Detection Function If the program counter specifies the same address as the address match detection register, the INT9 instruction is executed. The address match detection function can be achieved by processing the INT9 instruction routine. ■ Operation of the Address Match Detection Function There are two address detection registers with a compare enable bit. When the value set in the address detection register and the value of the program counter match and the compare enable bit is set to 1, the CPU executes the INT9 instruction. Note: If the value of the address detection register and the value of the program counter match, the contents of internal data bus is changed to 01H. Consequently, the INT9 instruction is executed. Before changing the contents of the address detection register, always set the compare enable bit to 0. While the compare enable bit is set to 1, changing the contents of the address detection register may result in a malfunction. 349 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.4 Example of the Address Match Detection Function Figure 21.4-1 shows a system configuration example of the address match detection function. Table 21.4-1 lists the E2PROM memory map. ■ System Configuration Example of the Address Match Detection Function Figure 21.4-1 System Configuration Example of the Address Match Detection Function MCU E2PROM F2MC-16LX SIN Pull-up resistor Connector (UART) Table 21.4-1 E2PROM Memory Map Address Description 0000H Number of bytes of patch program No.0 (If 0, no program error exists.) 0001H Program address No.0 bit7 to bit0 0002H Program address No.0 bit15 to bit8 0003H Program address No.0 bit24 to bit16 0004H Number of bytes of patch program No.1 (If 0, no program error exists.) 0005H Program address No.1 bit7 to bit0 0006H Program address No.1 bit15 to bit8 0007H Program address No.1 bit24 to bit16 0010H or higher Main body of patch program No. 0 ❍ Initial status E2PROM is set to all 0s. ❍ When a program error occurs: The main body of the patch program and program address are transferred to the MCU through the connector (UART). The MCU writes the information to E2PROM. 350 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ❍ Reset sequence The MCU reads the value of E2PROM after reset. If the number of bytes of the patch program is not 0, the main body of the patch program is read from E2PROM and written to RAM. The MCU then uses either PADR0 or PADR1 to set the patch address and sets the compare enable bit. If the relocatable patch program is required, the first address of the patched program can be written to the RAM area. In this case, the INT9 routine accesses this user-defined RAM area and jumps to the patched program. ❍ INT9 interrupt The interrupt routine can know the address where the interrupt occurs by checking the value of the stack program counter. The information that has been placed on the stack during the interrupt is discarded. ■ Example of Program Patch Processing Figure 21.4-2 Example of Program Patch Processing FFFFFFH Abnormal program PC = address in error ROM External E2PROM Register set for program patch Number of program bytes Address where the interrupt occurs Corrected program Data transfer using UART Corrected program RAM 000000H 351 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION Figure 21.4-3 Flow of Program Patch Processing Reset Reads 00H of E2PROM INT9 YES 0000H (E2PROM)=0 To patch program JMP 000400H NO Read address 0001H to 0003H (E2PROM) MOV PADR0 (MCU) Execute patch program 000400H to 000480H Read patch program 0010H to 0090H (E2PROM) MOV 000400H to 000480H (MCU) Terminate patch program JMP FF0050H Enable compare MOV PACSR, #02H Execute normal program NO PC=PADR0 YES INT9 FFFFFFH FF0050H Abnormal program ROM E2PROM FF0000H FFFFH FE0000H 0090H Patch program 0010H 001100H Stack area 0003H 0002H 0001H 0000H 352 Program address low-order: Program address middle-order: Program address high-order: Number of bytes of the patch program: RAM area 00 00 FF 80 000480H Patch program RAM 000400H RAM and register area 000100H I/O area 000000H CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE This chapter explains the ROM mirroring function selection module. 22.1 "Outline of ROM Mirroring Function Selection Module" 22.2 "ROM Mirroring Function Selection Register (ROMM)" 353 CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE 22.1 Outline of ROM Mirroring Function Selection Module The ROM Mirroring module switches whether to mirror the image of the FF bank of the ROM to the 00 bank. ■ Block Diagram of ROM Mirroring Function Selection Module Figure 22.1-1 Block Diagram of ROM Mirroring Function Selection Module F2MC-16LX BUS ROM Mirroring Register Address Area FF bank 00 bank ROM 354 CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE 22.2 ROM Mirroring Function Selection Register (ROMM) Do not access the ROM mirroring function selection register (ROMM) while addresses 004000H to 00FFFF H are being used. ■ ROM Mirroring Function Selection Register (ROMM) Address : 0006FH Read/write Initial value 15 14 13 12 11 10 9 8 — — — — — — — MI (–) (–) (–) (–) (–) (–) (–) (–) (–) (–) (–) (–) (–) (–) (W) Bit number ROMM (1) W : Write only - : Undefined [bit 8]: MI The image of the ROM data in the FF bank can also be found in the 00 bank when "1" is written to this bit. However, this memory mapping will not be done when this bit is written to "0". This bit is write only. Note: Only FF4000 to FFFFFF is mirrored to 004000 to 00FFFF when ROM mirroring function is activated. Therefore, addresses FF0000 to FF3FFF will not be mirrored to 00 bank. 355 CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE 356 CHAPTER 23 1M-BIT FLASH MEMORY CHAPTER 23 1M-BIT FLASH MEMORY This chapter explains the functions and operation of the 1M-bit flash memory. The following three methods are available for writing data to and erasing data from the flash memory: • Parallel programmer • Serial programmer • Executing programs to write/erase data This chapter explains "Executing programs to write/erase data". 23.1 "Outline of 1M-Bit Flash Memory" 23.2 "Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory" 23.3 "Write/Erase Modes" 23.4 "Flash Memory Control Status Register (FMCS)" 23.5 "Starting the Flash Memory Automatic Algorithm" 23.6 "Confirming the Automatic Algorithm Execution State" 23.7 "Detailed Explanation of Writing to and Erasing Flash Memory" 23.8 "Notes on Using 1M-bit Flash Memory" 23.9 "Reset Vector Address in Flash Memory" 23.10 "Flash Security Feature" 23.11 "Example of the 1M-Bit Flash Memory Program" 357 CHAPTER 23 1M-BIT FLASH MEMORY 23.1 Outline of 1M-Bit Flash Memory The 1M-bit flash memory is mapped to the FE to FF banks in the CPU memory map. The functions of the flash memory interface circuit enable read-access and programaccess from the CPU in the same way as mask ROM. Instructions from the CPU can be used via the flash memory interface circuit to write data to and erase data from the flash memory. Internal CPU control therefore enables rewriting of the flash memory while it is mounted. As a result, improvements in programs and data can be performed efficiently. ■ 1M-bit Flash Memory Features • Sectors of 128K words x 8/64K words x 16 bits (MB90F598: 16K + 512 x 2 + 7K +8K + 32K + 64K, MB90F598G: 16K + 8K x 2 + 32K + 64K) • Use of automatic program algorithm (Embedded Algorithm: Equivalent to MBM29F400T for MB90F598, MBM29LV200 for MB90F598G) • Erase pause/restart function provided • Detection of completion of writing/erasing using data polling or toggle bit functions • Detection of completion of writing/erasing using CPU interrupts • Sector erase function (any combination of sectors) • Minimum of 10,000 write/erase operations • Flash read cycle time (min.): 2 machine cycle • Flash security feature Embedded AlgorithmTM is a trademark of Advanced Micro Devices, Inc. Note: The manufacturer code and device code do not have the reading function. These codes cannot be accessed by the command. ■ Writing to/Erasing Flash Memory The flash memory cannot be written to and read at the same time. That is, when data is written to or erased from the flash memory, the program in the flash memory must first be copied to RAM. The entire process is then executed in RAM so that data is simply written to the flash memory. This eliminates the need for the program to access the flash memory from the flash memory itself. 358 CHAPTER 23 1M-BIT FLASH MEMORY ■ Flash Memory Register ❍ Flash memory control status register (FMCS) 7 6 5 4 3 2 1 0 Address: 0000AEH INTE RDYINT WE RDY Reserved LPM1 Reserved LPM0 Read/write ⇒ (R/W) (R/W) (R/W) (R) (R/W) (R/W) (R/W) (R/W) Initial value ⇒ (0) (0) (0) (X) (0) (0) (0) (0) ⇐ Bit No. FMCS R/W : Readable/Writable R : Read only X : Undefined 359 CHAPTER 23 1M-BIT FLASH MEMORY 23.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory Figure 23.2-1 shows a block diagram of the entire flash memory with the flash memory interface circuit included. Figure 23.2-2 shows the sector configuration of the flash memory. ■ Block Diagram of the Entire Flash Memory Figure 23.2-1 Block Diagram of the Entire Flash Memory Flash memory interface circuit 1Mbit Flash memory BYTE Port 2 Port 3 Port 4 F2MC-16 bus INT BYTE CE CE OE OE WE WE AQ0 to AQ16 AQ0 to AQ15 AQ-1 DQ0 to DQ15 DQ0 to DQ15 RY/BY RY/BY RESET Write enable interrupt signal (to CPU) External reset signal RY/BY write enable signal ■ Sector Configuration of the 1M-bit Flash Memory Figure 23.2-2 shows the sector configuration of the 1M-bit flash memory. The addresses in the figure indicate the high-order and low-order addresses of each sector. 360 CHAPTER 23 1M-BIT FLASH MEMORY Figure 23.2-2 Sector Configuration of the 1M-bit Flash Memory MB90F598 CPU address Programmer address * FFFFFFH 7FFFFH SA6 (16K bytes) SA3 (7K bytes) SA2 (8K bytes) SA1 (32K bytes) SA0 (64K bytes) CPU address Programmer address * FFFFFFH 7FFFFH FFC000H 7C000H FFBFFFH 7BFFFH FFA000H 7A000H FF9FFFH 79FFFH FF8000H 78000H SA4 (16K bytes) FFC000H 7C000H FFBFFFH 7BFFFH SA5 (512 bytes) SA4 (512 bytes) MB90F598G SA3 (8K bytes) FFBE00H 7BE00H FFBDFFH 7BDFFH FFBC00H 7BC00H FFBBFFH 7BBFFH FFA000H 7A000H FF9FFFH FF8000H 79FFFH 78000H FF7FFFH 77FFFH FF0000H 70000H FEFFFFH FE0000H 6FFFFH 60000H SA2 (8K bytes) SA1 (32K bytes) SA0 (64K bytes) FF7FFFH 77FFFH FF0000H 70000H FEFFFFH FE0000H 6FFFFH 60000H *: Use the programmer address for writing/erasing with a parallel programmer. 361 CHAPTER 23 1M-BIT FLASH MEMORY 23.3 Write/Erase Modes The flash memory can be accessed in two different ways: Flash memory mode and alternative mode. Flash memory mode enables data to be directly written to or erased from the external pins. Alternative mode enables data to be written to or erased from the CPU via the internal bus. Use the mode external pins to select the mode. ■ Flash Memory Mode The CPU stops when the mode pins are set to 111 while the reset signal is asserted. The flash memory interface circuit is connected directly to ports 0, 2, 3, and 4, enabling direct control from the external pins. This mode makes the MCU seem like a standard flash memory to the external pins, and write/erase can be performed using a flash memory programmer. In flash memory mode, all operations supported by the flash memory automatic algorithm can be used. ■ Alternative Mode The flash memory is located in the FE to FF banks of the CPU memory space and, like ordinary mask ROM, can be read-accessed and program-accessed from the CPU via the flash memory interface circuit. Since writing/erasing the flash memory is performed by instructions from the CPU via the flash memory interface circuit, this mode allows rewriting even when the MCU is soldered on the target board. Sector protect operations cannot be performed in these modes. 362 CHAPTER 23 1M-BIT FLASH MEMORY ■ Flash Memory Control Signals Table 23.3-1 lists the flash memory control signals in flash memory mode. There is almost a one-to-one correspondence between the flash memory control signals and the external pins of the MBM29F400T/MBM29LV200. The VID (12 V) pins required by the sector protect operations are MD0, MD1, and MD2 instead of A9, RESET, and OE or the MBM29F400T/MBM29LV200. In flash memory mode, the external data bus signal width is limited to eight bits, enabling only one-byte access. The DQ15 to DQ8 pins are not supported. The BYTE pin should always be set to 0. Table 23.3-1 Flash Memory Control Signals MB90F598/F598G MBM29F400T/ MBM29LV200 Pin number Normal function Flash memory mode 1 to 8 P20 to P27 AQ0 to AQ7 A-1, A0 to A6 9 P30 AQ16 A15 10 P31 CE CE 12 P32 OE OE 13 P33 WE WE 16 P36 BYTE BYTE 17 P37 RY/BY RY/BY 18 to 22 P40 to P44 AQ8 to AQ12 A7 to A11 24 to 26 P45 to P47 AQ13 to AQ15 A12 to A14 49 MD0 MD0 A9(VID) 50 MD1 MD1 RESET(VID) 51 MD2 MD2 OE(VID) 85 to 92 P00 to P07 DQ0 to DQ7 DQ0 to DQ7 77 RST RESET RESET Not supported DQ8 to DQ15 363 CHAPTER 23 1M-BIT FLASH MEMORY 23.4 Flash Memory Control Status Register (FMCS) The flash memory control status register (FMCS), together with the flash memory interface circuit, is used to write data to and erase data from the flash memory. ■ Flash Memory Control Status Register (FMCS) 7 6 5 4 3 2 1 0 Address: 0000AEH INTE RDYINT WE RDY Reserved LPM1 Reserved LPM0 Read/write ⇒ (R/W) (R/W) (R/W) (R) (R/W) (R/W) (R/W) (R/W) Initial value ⇒ (0) (0) (0) (X) (0) (0) (0) (0) ⇐ Bit No. R/W : Readable/Writable R : Read only X : Undefined ❍ Explanation of Bits [bit7] INTE (interrupt enable) This bit generates an interrupt to the CPU when flash memory write/erase terminates. An interrupt to the CPU is generated when the INTE and RDYINT bits are 1. No interrupt is generated when the INTE bit is 0. 0: Disables interrupts when write/erase terminates. 1: Enables interrupts when write/erase terminates. [bit6] RDYINT (ready interrupt) This bit indicates the operating state of the flash memory. This bit is set to 1 when flash memory write/erase terminates. Data cannot be written to or erased from the flash memory while this bit is 0 after a flash memory write/erase. Flash memory write/erase is enabled when write/erase terminates and this bit is set to 1. Writing 0 clears this bit to 0. Writing 1 is ignored. This bit is set to 1 at the termination timing of the flash memory automatic algorithm (see Section 23.5 "Starting the Flash Memory Automatic Algorithm"). When the read-modify-write (RMW) instruction is used, 1 is always read. 0: Write/erase is being executed. 1: Write/erase has terminated (interrupt request generated). 364 CHAPTER 23 1M-BIT FLASH MEMORY [bit5] WE (write enable) This bit enables writing to the flash memory area. When this bit is 1, writing after the command sequence (see Section 23.5 "Starting the Flash Memory Automatic Algorithm") is issued to the FE to FF bank writes to the flash memory area. When this bit is 0, the write/erase signal is not generated. This bit is used when the flash memory write/erase command is started. If write/erase is not performed, it is recommended that this bit be set to 0 to prevent data from being mistakenly written to the flash memory. 0: Disables flash memory write/erase. 1: Enables flash memory write/erase. [bit4] RDY (ready) This bit enables flash memory write/erase. Flash memory write/erase is disabled while this bit is 0. However, Suspend commands, such as the Read/Reset command and Sector Erase Suspend command, can be accepted even if this bit is 0. 0: Write/erase is being executed. 1: Write/erase has terminated (next data write/erase enabled). [bit3, bit1] Reserved bits These bits are reserved for testing. During regular use, they should always be set to 0. [bit2, bit0] LPM1 and LPM0 (low power mode) These bits control the current consumed by the flash memory when the flash memory is accessed. Since the access time to the flash memory from the CPU is largely dependent on this setting, select a setting value based on the operating frequency of the CPU. 01: Low power consumption mode (Operates at an internal operating frequency up to 4 MHz.) 10: Low power consumption mode (Operates at an internal operating frequency up to 8 MHz.) 11: Low power consumption mode (Operates at an internal operating frequency up to 10 MHz.) 00: Regular low power consumption mode (Operates at an internal operating frequency up to 16 MHz.) Note: The RDYINT and RDY bits cannot be changed at the same time. Create a program so that decisions are made using one or the other of these bits. Automatic algorithm Termination timing RDYINT bit RDY bit 1 machine cycle 365 CHAPTER 23 1M-BIT FLASH MEMORY 23.5 Starting the Flash Memory Automatic Algorithm Four types of commands are available for starting the flash memory automatic algorithm: Read/Reset, Write, and Chip Erase. Control of suspend and restart is enabled for sector erase. ■ Command Sequence Table Table 23.5-1 lists the commands used for flash memory write/erase. All of the data written to the command register is in bytes, but use word access to write. The data in the high-order bytes at this time is ignored. Table 23.5-1 Command Sequence Table Command sequence Bus write access 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle Address Data Address Data Address Data Address Data Address Data Address Data Read/Reset *1 1 FxXXXX XXF0 - - - - - - - - - - Read/Reset *1 4 FxAAAA XXAA Fx5554 XX55 FxAAAA XXF0 RA RD - - - - Write program 4 FxAAAA XXAA Fx5554 XX55 FxAAAA XXA0 PA (even) PD (word) - - - - Chip Erase 6 FxAAAA XXAA Fx5554 XX55 FxAAAA XX80 FxAAAA XXAA Fx5554 XX55 FxAAAA XX10 Sector Erase 6 FxAAAA XXAA Fx5554 XX55 FxAAAA XX80 FxAAAA XXAA Fx5554 XX55 SA (even) XX30 Sector Erase Suspend Sector Erase Restart Auto-select *2 3 Entering address FxXXXX data (xxB0H) suspends erasing during sector erase. Entering address FxXXXX data (xx30H) restarts erasing after erasing is suspended during sector erase. FxAAA XXAA Fx5554 XX55 FxAAAA XX90 - - - - - - Notes: • The addresses Fx in the table mean FF and FE. Use these addresses as the access target bank values for operations. • The addresses in the table are the values in the CPU memory map. All addresses and data are represented using hexadecimal notation. However, the letter X is an optional value. • RA: Read address • PA: Write address. Only even addresses can be specified. • SA: Sector address. See Section 23.2 "Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory ". • RD: Read data • PD: Write data. Only word data can be specified. *1 Both of the two types of Read/Reset commands can reset the flash memory to read mode. *2: MB90F598G only 366 CHAPTER 23 1M-BIT FLASH MEMORY The Auto-select command shown in Table 23.5-1 is used to know the state of sector protection. When using the Auto-select command, set the address as follows. Table 23.5-2 Address Setting at Auto-select (MB90F598G Only) Sector protection AQ13 to AQ16 AQ7 AQ2 AQ1 AQ0 DQ7 to DQ0 Sector Address L H L L CODE* *: When the sector address is protected, the output is "01H". When the sector address is not protected, the output is "00H". 367 CHAPTER 23 1M-BIT FLASH MEMORY 23.6 Confirming the Automatic Algorithm Execution State Because the write/erase flow of the flash memory is controlled using the automatic algorithm, the flash memory has hardware for posting its internal operating state and completion of operation. This automatic algorithm enables confirmation of the operating state of the built-in flash memory using the following hardware sequences. ■ Hardware Sequence Flags The hardware sequence flags are configured from the five-bit output of DQ7, DQ6, DQ5, DQ3, and DQ2. The functions of these bits are those of the data polling flag (DQ7), toggle bit flag (DQ6), timing limit exceeded flag (DQ5), and sector erase timer flag (DQ3), toggle bit 2 flag (DQ2). The hardware sequence flags can therefore be used to confirm that writing or chip sector erase has been completed or that erase code write is valid. Note that toggle bit 2 flag (DQ2) can not be used for MB90F598. The hardware sequence flags can be accessed by read-accessing the addresses of the target sectors in the flash memory after setting of the command sequence (see Table 23.5-1 in Section 23.5 "Starting the Flash Memory Automatic Algorithm"). Table 23.6-1 lists the bit assignments of the hardware sequence flags. Table 23.6-1 Bit Assignments of Hardware Sequence Flags Bit No. Hardware sequence flag 7 6 5 4 3 2 1 0 DQ7 DQ6 DQ5 - DQ3 DQ2 * - - *: MB90F598G only To determine whether automatic writing or chip sector erase is being executed, the hardware sequence flags can be checked or the status can be determined from the RDY bit of the flash memory control register (FMCS) that indicates whether writing has been completed. After writing/erasing has terminated, the state returns to the read/reset state. When creating a program, use one of the flags to confirm that automatic writing/erasing has terminated. Then, perform the next processing operation, such as data read. In addition, the hardware sequence flags can be used to confirm whether a second or subsequent sector erase code write is valid. The following sections describe each hardware sequence flag separately. Table 23.6-2 lists the functions of the hardware sequence flags. 368 CHAPTER 23 1M-BIT FLASH MEMORY Table 23.6-2 Hardware Sequence Flag Functions State State change for normal operation Abnormal operation Write --> Write completed (write address specified) Chip/sector erase --> Erase completed DQ7 DQ7 --> DATA:7 DQ6 Toggle --> DATA:6 DQ5 DQ3 0 --> DATA:5 0 --> DATA:3 DQ2 *2 1 --> DATA:2 0 --> 1 Toggle --> Stop 0 --> 1 1 Toggle --> Stop Sector erase wait --> Erase started 0 Toggle 0 0 --> 1 Toggle Erase --> Sector erase suspended (sector being erased) 0 --> 1 Toggle --> 1 0 1 --> 0 Toggle Sector erase suspend --> Erase restarted (sector being erased) 1 --> 0 1 --> Toggle 0 0 --> 1 Toggle Sector erase suspended (sector not being erased) DATA:7 DATA:6 DATA:5 DATA:3 DATA:2 DQ7 Toggle 1 0 1 0 Toggle 1 1 *1 Write Chip/sector erase *1: If the DQ5 outputs "1" (exceed the timing limit), successive reads from a writing or erasing sector cause DQ2 to toggle. DQ2 does not toggle when the successive reads are executed from other sectors. *2: MB90F598G only 369 CHAPTER 23 1M-BIT FLASH MEMORY 23.6.1 Data Polling Flag (DQ7) The data polling flag (DQ7) uses the data polling function to post that the automatic algorithm is being executed or has terminated. ■ Data Polling Flag (DQ7) Table 23.6-3 and Table 23.6-4 list the state transitions of the data polling flag. Table 23.6-3 Data Polling Flag State Transitions (State Change for Normal Operation) Operating state Write --> Completed Chip/sector erase --> Completed DQ7 DQ7 --> DATA:7 0 --> 1 Sector erase wait --> Started Sector erase --> Erase suspend (sector being erased) Sector erase suspend --> Restarted (sector being erased) Sector erase suspended (sector not being erased) 0 0 --> 1 1 --> 0 DATA:7 Table 23.6-4 Data Polling Flag State Transitions (State Change for Abnormal Operation) Operating state Write Chip/sector erase DQ7 DQ7 0 ❍ Write Read-access during execution of the automatic write algorithm causes the flash memory to output the opposite data of bit 7 last written, regardless of the value at the address specified by the address signal. Read-access at the end of the automatic write algorithm causes the flash memory to output bit 7 of the read value of the address specified by the address signal. ❍ Chip/sector erase For a sector erase, read-access during execution of the chip erase/sector erase algorithm causes the flash memory to output 0 from the sector currently being erased. For a chip erase, read-access causes the flash memory to output 0 regardless of the value at the address specified by the address signal. Read-access at the end of the automatic write algorithm causes the flash memory to output 1 in the same way. 370 CHAPTER 23 1M-BIT FLASH MEMORY ❍ Sector erase suspend Read-access for an access from sector erase suspend causes the flash memory to output 1 if the address specified by the address signal belongs to the sector being erased. The flash memory outputs bit 7 (DATA: 7) of the read value at the address specified by the address signal if the address specified by the address signal does not belong to the sector being erased. Referencing this flag together with the toggle bit flag (DQ6) enables a decision to be made on whether the flash memory is in the erase suspended state and which sector is being erased. Note: When the automatic algorithm is being started, read-access to the specified address is ignored. Since termination of the data polling flag (DQ7) can be accepted for a data read and other bits output, data read after the automatic algorithm has terminated should be performed after read-access has confirmed that data polling has terminated. 371 CHAPTER 23 1M-BIT FLASH MEMORY 23.6.2 Toggle Bit Flag (DQ6) Like the data polling flag, the toggle bit flag (DQ6) uses the toggle bit function to post that the automatic algorithm is being executed or has terminated. ■ Toggle Bit Flag (DQ6) Table 23.6-5 and Table 23.6-6 list the state transitions of the toggle bit flag. Table 23.6-5 Toggle Bit Flag State Transitions (State Change for Normal Operation) Operating state Write --> Completed Chip/sector erase --> Completed DQ6 Toggle --> DATA:6 Toggle --> Stop Sector erase wait --> Started Sector erase --> Erase suspend (sector being erased) Sector erase suspend --> Restarted (sector being erased) Sector erase suspended (sector not being erased) Toggle Toggle --> 1 1 --> Toggle DATA:6 Table 23.6-6 Toggle Bit Flag State Transitions (State Change for Abnormal Operation) Operating state Write Chip/sector erase DQ6 Toggle Toggle ❍ Write/chip sector erase Continuous read-access during execution of the automatic write algorithm and chip/sector erase algorithm causes the flash memory to toggle the 1 or 0 state for every read cycle, regardless of the value at the address specified by the address signal. Continuous read-access at the end of the automatic write algorithm and chip/sector erase algorithm causes the flash memory to stop toggling bit 6 and output bit 6 (DATA: 6) of the read value of the address specified by the address signal. ❍ Sector erase suspend Read-access during a sector erase suspend causes the flash memory to output 1 if the address specified by the address signal belongs to the sector being erased. The flash memory outputs bit 6 (DATA: 6) of the read value at the address specified by the address signal if the address specified by the address signal does not belong to the sector being erased. Note: For a write, if the sector where data is to be written is rewrite-protected, the toggle bit terminates the toggle operation after approximately 2 µs and without any data being rewritten. For an erase, if all of the selected sectors are write-protected, the toggle bit performs toggling for approximately 100 µs and then returns to the read/reset state without any data being rewritten. 372 CHAPTER 23 1M-BIT FLASH MEMORY 23.6.3 Timing Limit Exceeded Flag (DQ5) The timing limit exceeded flag (DQ5) is used to post that execution of the automatic algorithm has exceeded the time (internal pulse count) prescribed in the flash memory. ■ Timing Limit Exceeded Flag (DQ5) Table 23.6-7 and Table 23.6-8 list the state transitions of the timing limit exceeded flag. Table 23.6-7 Timing Limit Exceeded Flag State Transitions (State Change for Normal Operation) Operating state Write --> Completed Chip/sector erase --> Completed DQ5 0 --> DATA:5 0 --> 1 Sector erase wait --> Started Sector erase --> Erase suspend (sector being erased) Sector erase suspend --> Restarted (sector being erased) Sector erase suspended (sector not being erased) 0 0 0 DATA:5 Table 23.6-8 Timing Limit Exceeded Bit Flag State Transitions (State Change for Abnormal Operation) Operating state Write Chip/sector erase DQ5 1 1 ❍ Write/chip sector erase Read-access after write or chip/sector erase automatic algorithm activation causes the flash memory to output 0 if the time is within the prescribed time (time required for write/erase) or to output 1 if the prescribed time has been exceeded. Because this is done regardless of whether the automatic algorithm is being executed or has terminated, it is possible to determine whether write/erase was successful or unsuccessful. That is, when this flag outputs 1, writing can be determined to have been unsuccessful if the automatic algorithm is still being executed by the data polling function or toggle bit function. For example, writing 1 to a flash memory address where 0 has been written will cause the fail state to occur. In this case, the flash memory will lock and execution of the automatic algorithm will not terminate. As a result, valid data will not be output from the data polling flag (DQ7). In addition, the toggle bit flag (DQ6) will exceed the time limit without stopping the toggle operation and the timing limit exceeded flag (DQ5) will output 1. Note that this state indicates that the flash memory is not faulty, but has been used correctly. When this state occurs, execute the Reset command. 373 CHAPTER 23 1M-BIT FLASH MEMORY 23.6.4 Sector Erase Timer Flag (DQ3) The sector erase timer flag (DQ3) is used to post whether the automatic algorithm is being executed during the sector erase wait period after the Sector Erase command has been started. ■ Sector Erase Timer Flag (DQ3) Table 23.6-9 and Table 23.6-10 list the state transitions of the sector erase timer flag. Table 23.6-9 Sector Erase Timer Flag State Transitions (State Change for Normal Operation) Operating state Write --> Completed Chip/sector erase --> Completed DQ3 0 --> DATA:3 1 Sector erase wait --> Started Sector erase --> Erase suspend (sector being erased) Sector erase suspend --> Restarted (sector being erased) Sector erase suspended (sector not being erased) 0 --> 1 1 --> 0 0 --> 1 DATA:3 Table 23.6-10 Sector Erase Timer Flag State Transitions (State Change for Abnormal Operation) Operating state Write Chip/sector erase DQ3 0 1 ❍ Sector erase Read-access after the Sector Erase command has been started causes the flash memory to output 0 if the automatic algorithm is being executed during the sector erase wait period, regardless of the value at the address specified by the address signal of the sector that issued the command. The flash memory outputs 1 if the sector erase wait period has been exceeded. When the data polling function or toggle bit function indicates that the erase algorithm is being executed, internally controlled erase has already started if this flag is 1. Continuous write of the sector erase codes or commands other than the Sector Erase Suspend command will be ignored until erase is terminated. If this flag is 0, the flash memory will accept write of additional sector erase codes. To confirm this, it is recommended that the state of this flag be checked before continuing to write sector erase codes. If this flag is 1 after the second state check, it is possible that additional sector erase codes may not be accepted. ❍ Sector erase Read-access during execution of sector erase suspend causes the flash memory to output 1 if the address specified by the address signal belongs to the sector being erased. The flash memory outputs bit 3 (DATA: 3) of the read value of the address specified by the address signal if the address specified by the address signal does not belong to the sector being erased. 374 CHAPTER 23 1M-BIT FLASH MEMORY 23.6.5 Toggle Bit-2 Flag (DQ2) The toggle bit-2 flag (DQ2) is a flag that uses the toggle bit function to indicate that the sector is in the erase-suspended state. Note: The toggle bit 2 flag can not be used for MB90F598. ■ Toggle Bit-2 Flag (DQ2) Table 23.6-11 and Table 23.6-12 list the state transitions of the toggle bit flag. Table 23.6-11 Toggle Bit-2 Flag State Transitions (State Change for Normal Operation) Operating state Write --> Completed Chip/ sector erase --> Completed DQ2 1 --> DATA:2 Toggle --> Stop Sector erase wait --> Started Sector erase --> Erase suspend (sector being erased) Sector erase suspend --> Restarted (sector being erased) Sector erase suspended (sector not being erased) Toggle Toggle Toggle DATA:2 Table 23.6-12 Toggle Bit-2 Flag State Transitions (State Change for Abnormal Operation) Operating state Write Chip/sector erase DQ2 1 * *: If the DQ5 outputs "1" (exceed the timing limit), successive reads from a writing or erasing sector cause DQ2 to toggle. DQ2 does not toggle when the successive reads are executed from other sectors. ❍ During a sector erase operation If successive reads are executed during the execution of the chip sector erase algorithm, a flash memory toggles to output "1" and "0" to addresses alternately at every read access regardless of the location indicated by the addresses. If successive reads are executed after the chip sector erase algorithm is completed, the flash memory stops the toggle operation of the bit 2 and outputs the read value of the bit 2 (DATA: 2) to the location indicated by the address. 375 CHAPTER 23 1M-BIT FLASH MEMORY ❍ While a sector erase operation is suspended If successive reads are executed while a sector erase operation is suspended, and if the address indicates the sector to be erased, the flash memory toggles to alternately output "1" and "0". If the address indicates the sector is not to be erased, the flash memory outputs the read value of the bit 2 (DATA: 2) to the location indicated by the address. In the erase-suspend-program mode, successive reads from the non-erase suspended sector causes the flash memory to output "1". Both DQ2 and DQ6 are used for detecting an erase-suspended sector (DQ2 toggles, but DQ6 does not). DQ2 is also used for detecting an erasing sector. While erasing a sector, if a read access is executed from the erasing sector, DQ2 toggles. Reference: If all sectors selected for erasing are write-protected, the toggle bit-2 toggles for about 100µs, and then returns to the read/reset mode without writing the data. 376 CHAPTER 23 1M-BIT FLASH MEMORY 23.7 Detailed Explanation of Writing to and Erasing Flash Memory This section describes each operation procedure of flash memory Read/Reset, Write, Chip Erase, Sector Erase, Sector Erase Suspend, and Sector Erase Restart when a command that starts the automatic algorithm is issued. ■ Detailed Explanation of Flash Memory Write/Erase The flash memory executes the automatic algorithm by issuing a command sequence (see Table 23.5-1 in Section 23.5 "Starting the Flash Memory Automatic Algorithm") for a write cycle to the bus to perform Read/Reset, Write, Chip Erase, Sector Erase, Sector Erase Suspend, or Sector Erase Restart operations. Each bus write cycle must be performed continuously. In addition, whether the automatic algorithm has terminated can be determined using the data polling or other function. At normal termination, the flash memory is returned to the read/reset state. Each operation of the flash memory is described in the following order: • Setting the read/reset state • Writing data • Erasing all data (erasing chips) • Erasing optional data (erasing sectors) • Suspending sector erase • Restarting sector erase 377 CHAPTER 23 1M-BIT FLASH MEMORY 23.7.1 Setting Flash Memory to the Read/reset State This section describes the procedure for issuing the Read/Reset command to set the flash memory to the read/reset state. ■ Setting the Flash Memory to the Read/Reset State The flash memory can be set to the read/reset state by sending the Read/Reset command in the command sequence table (see Table 23.5-1 in Section 23.5 "Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. The Read/Reset command has two types of command sequences that execute the first and third bus operations. However, there are no essential differences between these command sequences. The read/reset state is the initial state of the flash memory. When power is supplied on and when a command terminates normally, the flash memory is set to the read/reset state. In the read/reset state, other commands wait for input. In the read/reset state, data is read by regular read-access. As with the mask ROM, program access from the CPU is enabled. The Read/Reset command is not required to read data by a regular read. The Read/Reset command is mainly used to initialize the automatic algorithm in such cases as when a command does not terminate normally. 378 CHAPTER 23 1M-BIT FLASH MEMORY 23.7.2 Writing Data to Flash Memory This section describes the procedure for issuing the Write command to write data to the flash memory. ■ Writing Data to the Flash Memory The data write automatic algorithm of the flash memory can be started by sending the Write command in the command sequence table (see Table 23.5-1 in Section 23.5 "Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. When data write to the target address is completed in the fourth cycle, the automatic algorithm and automatic write are started. ❍ Specifying addresses Only even addresses can be specified as the write addresses specified in a write data cycle. Odd addresses cannot be written correctly. That is, writing to even addresses must be done in units of word data. Writing can be done in any order of addresses or even if the sector boundary is exceeded. However, the Write command writes only data of one word for each execution. ❍ Notes on writing data Writing cannot return data 0 to data 1. When data 1 is written to data 0, the data polling algorithm (DQ7) or toggle operation (DQ6) does not terminate and the flash memory elements are determined to be faulty. If the time prescribed for writing is thus exceeded, the timing limit exceeded flag (DQ5) is determined to be an error. Otherwise, the data is viewed as if dummy data 1 had been written. However, when data is read in the read/reset state, the data remains 0. Data 0 can be set to data 1 only by erase operations. All commands are ignored during execution of the automatic write algorithm. If a hardware reset is started during writing, the data of the written addresses will be unpredictable. ■ Writing to the Flash Memory Figure 23.7-1 is an example of the procedure for writing to the flash memory. The hardware sequence flags (see Section 23.6 "Confirming the Automatic Algorithm Execution State") can be used to determine the state of the automatic algorithm in the flash memory. Here, the data polling flag (DQ7) is used to confirm that writing has terminated. The data read to check the flag is read from the address written to last. The data polling flag (DQ7) changes at the same time that the timing limit exceeded flag (DQ5) changes. For example, even if the timing limit exceeded flag (DQ5) is 1, the data polling flag bit (DQ7) must be rechecked. Also for the toggle bit flag (DQ6), the toggle operation stops at the same time that the timing limit exceeded flag bit (DQ5) changes to 1. The toggle bit flag (DQ6) must therefore be rechecked. 379 CHAPTER 23 1M-BIT FLASH MEMORY Figure 23.7-1 Example of the Flash Memory Write Procedure Start writing FMCS: WE (bit 5) Enable flash memory write Write command sequence (1) FxAAAA <-- XXAA (2) Fx5554 <-- XX55 (3) FxAAAA <-- XXA0 (4) Write address <-- Write data Read internal address Data polling (DQ7)? Next address Data Data 0 Timing limit (DQ5)? 1 Read internal address Data Data polling (DQ7)? Data Write error Final address? FMCS: WE (bit 5) Disable flash memory write Complete writing 380 Confirm with the hardware sequence flags. CHAPTER 23 1M-BIT FLASH MEMORY 23.7.3 Erasing All Data (Erasing Chips) of Flash Memory This section describes the procedure for issuing the Chip Erase command to erase all data in the flash memory. ■ Erasing All Data in the Flash Memory (Erasing Chips) All data can be erased from the flash memory by sending the Chip Erase command in the command sequence table (see Table 23.5-1 in Section 23.5 "Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. The Chip Erase command is executed in six bus operations. When writing of the sixth cycle is completed, the chip erase operation is started. For chip erase, the user need not write to the flash memory before erasing. During execution of the automatic erase algorithm, the flash memory writes 0 for verification before all of the cells are erased automatically. 381 CHAPTER 23 1M-BIT FLASH MEMORY 23.7.4 Erasing Optional Data (Erasing Sectors) in Flash Memory This section describes the procedure for issuing the Sector Erase command to erase optional data (erase sector) in the flash memory. Individual sectors can be erased. Multiple sectors can also be specified at one time. ■ Erasing Optional Data (Erasing Sectors) in the Flash Memory Optional sectors in the flash memory can be erased by sending the Sector Erase command in the command sequence table (see Table 23.5-1 in Section 23.5 "Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. ❍ Specifying sectors The Sector Erase command is executed in six bus operations. Sector erase wait of 50 µs is started by writing the sector erase code (30H) to an accessible even-numbered address in the target sector in the sixth cycle. To erase multiple sectors, write the erase code (30H) to the addresses in the target sectors after the above processing operation. ❍ Notes on specifying multiple sectors Erase is started when the sector erase wait period of 50 µs terminates after the final sector erase code has been written. That is, to erase multiple sectors at one time, an erase code (sixth cycle of the command sequence) must be written within 50 µs of writing of the address of a sector and the address of the next sector must be written within 50 µs of writing of the previous erase code. Otherwise, the address and erase code may not be accepted. The sector erase timer (hardware sequence flag DQ3) can be used to check whether writing of the subsequent sector erase code is valid. At this time, specify so that the address used for reading the sector erase timer indicates the sector to be erased. ■ Erasing Sectors in the Flash Memory The hardware sequence flags (see Section 23.6 "Confirming the Automatic Algorithm Execution State") can be used to determine the state of the automatic algorithm in the flash memory. Figure 23.7-2 an example of the procedure for erasing sectors in the flash memory. Here, the toggle bit flag (DQ6) is used to confirm that erasing has terminated. The data that is read to check the flag is read from the sector to be erased. The toggle bit flag (DQ6) stops the toggle operation at the same time that the timing limit exceeded flag (DQ5) is changed to 1. For example, even if the timing limit exceeded flag (DQ5) is 1, the toggle bit flag (DQ6) must be rechecked. The data polling flag (DQ7) also changes at the same time that the timing limit exceeded flag bit (DQ5) changes. As a result, the data polling flag (DQ7) must be rechecked. 382 CHAPTER 23 1M-BIT FLASH MEMORY Figure 23.7-2 Example of the Flash Memory Sector Erase Procedure Start erasing FMCS: WE (bit 5) Enable flash memory erase Erase command sequence (1) FxAAAA <-- XXAA (2) Fx5554 <-- XX55 (3) FxAAAA <-- XX80 (4) FxAAAA <-- XXAA (5) Fx5554 <-- XX55 (6) Sector address <-- Erase code (30H) YES Another erase sector? NO Read internal address 1 NO Next sector Read internal address 2 YES Sector erase completed? YES Toggle bit (DQ6) data 1(DQ6) = data 2(DQ6)? NO 0 Timing limit (DQ5)? 1 Read internal address 1 Read internal address 2 NO Toggle bit (DQ6) data 1(DQ6) = data 2(DQ6)? YES Final sector? NO Erase error YES FMCS: WE (bit 5) Disable flash memory erase Confirm with the hardware sequence flags. Complete erasing 383 CHAPTER 23 1M-BIT FLASH MEMORY 23.7.5 Suspending Sector Erase of Flash Memory This section describes the procedure for issuing the Sector Erase Suspend command to suspend erasing of flash memory sectors. Data can be read from sectors that are not being erased. ■ Suspending Erasing of Flash Memory Sectors Erasing of flash memory sectors can be suspended by sending the Sector Erase Suspend command in the command sequence table (see Table 23.5-1 in Section 23.5 "Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. The Sector Erase Suspend command suspends the sector erase operation being executed and enables data to be read from sectors that are not being erased. In this state, only reading is enabled; data cannot be written. This command is valid only during sector erase operations that include an erase wait time. The command will be ignored during chip erase or write operations. This command is implemented by writing the erase suspend code (B0H). At this time, specify an optional address in the flash memory for the address. An Erase Suspend command issued again during erasing of sectors will be ignored. Entering the Sector Erase Suspend command during the sector erase wait period will immediately terminate sector erase wait, cancel the erase operation, and set the erase stop state. Entering the Erase Suspend command during the erase operation after the sector erase wait period has terminated will set the erase suspend state after a maximum period of 15 µs has elapsed. 384 CHAPTER 23 1M-BIT FLASH MEMORY 23.7.6 Restarting Sector Erase of Flash Memory This section describes the procedure for issuing the Sector Erase Restart command to restart suspended erasing of flash memory sectors. ■ Restarting Erasing of Flash Memory Sectors Suspended erasing of flash memory sectors can be restarted by sending the Sector Erase Restart command in the command sequence table (see Table 23.5-1 in Section 23.5 "Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. The Sector Erase Restart command is used to restart erasing of sectors from the sector erase suspend state set using the Sector Erase Suspend command. The Sector Erase Restart command is implemented by writing the erase restart code (30H). At this time, specify an optional address in the flash memory area for the address. If a Sector Erase Restart command is issued during sector erase, the command will be ignored. 385 CHAPTER 23 1M-BIT FLASH MEMORY 23.8 Notes on Using 1M-bit Flash Memory This section contains notes on using 1M-bit flash memory. ■ Notes on Using Flash Memory ❍ Input of a hardware reset (RST) To input a hardware reset when the automatic algorithm has not been started and reading is in progress, a minimum low-level width of 500 ns must be maintained. In this case, a maximum of 500 ns is required until data can be read from the flash memory after a hardware reset has been activated. Similarly, to input a hardware reset when the automatic algorithm has been activated and writing or erasing is in progress, a minimum low-level width of 50 ns must be maintained. In this case, 20 (s are required until data can be read after the operation for initializing the flash memory has terminated. A hardware reset during writing the data being written to be undefined. A hardware reset during erasing may make the sector being erased unusable. ❍ Canceling of a software reset, watchdog timer reset, and hardware standby When the flash memory is being written to or erased with CPU access and if reset conditions occur while the automatic algorithm is active, the CPU may run out of control. This occurs because these reset conditions cause the automatic algorithm to continue without initializing the flash memory unit, possibly preventing the flash memory unit from entering the read state when the CPU starts the sequence after the reset has been deasserted. These reset conditions must be disabled during writing to or erasing of the flash memory. ❍ Program access to flash memory When the automatic algorithm is operating, read access to the flash memory is disabled. With the memory access mode of the CPU set to internal ROM mode, writing or erasing must be started after the program area is switched to another area such as RAM. In this case, when sectors (SA6/SA4) containing interrupt vectors are erased, writing or erasing interrupt processing cannot be executed. For the same reason, all interrupt sources other than the flash memory are disabled while the automatic algorithm is operating. Also, while the automatic algorithm is being executed, all interrupt sources except flash memory are disabled. ❍ Hold function When the CPU accepts a hold request, the Write signal WE of the flash memory unit may be skewed, causing erroneous writing or erasing due to an erroneous write. When the acceptance of a hold request is enabled (HDE bit of EPCR set to 1), ensure that the WE bit of the control status register (FMCS) is 0. ❍ Extended intelligent I/O service (EI2OS) Because write and erase interrupts issued to the CPU from the flash memory interface circuit cannot be accepted by the EI2OS, they should not be used. 386 CHAPTER 23 1M-BIT FLASH MEMORY ❍ Applying VID Applying VID required for the sector protect operation should always be started and terminated when the supply voltage is on. 387 CHAPTER 23 1M-BIT FLASH MEMORY 23.9 Reset Vector Address in Flash Memory The MB90F598/F598G supports a hard-wired reset vector. When the addresses FFFFDCH to FFFFDFH are accessed for reading data in internal vector mode, the values that have been determined by the hard-wired logic in advance are read. However, in flash memory mode, as mentioned in the previous chapter, all addresses can be accessed. Consequently, it is meaningless to write data to these addresses. Especially when programming flash memory from the CPU (that is, not in flash memory mode), do not read these addresses for software polling. Otherwise, the flash memory returns a fixed reset vector instead of the hardware sequence flag value. ■ Reset Vector Address in Flash Memory The following table shows the reset vector and mode data values determined in advance. Reset vector FFA000H Mode data 00H Note: Because of the hard-wired reset vector, it is not necessary to specify the reset vector in the software. However it is recommended to specify the same vector and the same mode data in the program, this will prevent the Mask ROM device to behave differently from the Flash device when the same program is used. 388 CHAPTER 23 1M-BIT FLASH MEMORY 23.10 Flash Security Feature The Flash security Controller provides possibilities to protect the content of the flash memory from being read from external pins. ■ Flash Security Feature One predefined address of the flash memory is assigned to the Flash Security Controller (1M-bit flash memory: FE0001). If the protection code of "01H" is written is this address, access to the flash memory is restricted. Once the flash memory is protected, performing the chip erase operation only can unlock the function otherwise read/write access to the flash memory from any external pins is not generally possible. This function is suitable for applications requiring security of self-containing and data stored in the flash memory. If the target application requires any part of program to locate outside the microcontroller, the Flash Security Controller can not offer the intended features. For this reason, the External Vector Fetch mode should not be used when the protection code is set. Programming of the flash microcontroller by standard parallel programmer may require unique set-up. For example, with the programmer from Minato Electronics the device checking should be turned off. Writing the protection code is generally recommended to take place at the end of the flash programming. This is to avoid unnecessary protection during the programming. In order to re-program the once protected flash memory, the chip erase operation should be performed. For further information, please contact Fujitsu. 389 CHAPTER 23 1M-BIT FLASH MEMORY 23.11 Example of the 1M-Bit Flash Memory Program This section provides an example of the 1M-bit flash memory program. ■ Example of the 1M-bit Flash Memory Program NAME FLASHWE TITLE FLASHWE ;------------------------------------------------------------------;1M-bit FLASH sample program ; ;1: Transferring the program (address FFBC00H, sector SA4/SA3) ; in FLASH to the RAM (address 000700H) ;2: Executing the program on the RAM ;3: Writing a PDR1 value to FLASH (address FE0000H, sector SA0) ;4: Reading the written value (address FE0000H, sector SA0) and ; outputting it to PDR2 ;5: Deleting the written sector (SA0) ;6: Outputting the deletion data confirmation ; Conditions ; -Number of RAM transfer bytes: 100H (256B) ; -Judgment for the end of writing and deletion ; Judgment with DQ5 (timing limit excess flag) ; Judgment with DQ6 (toggle bit flag) ; Judgment with RDY (FMCS) ; -Error handling ; Outputting Hi to P00 to P07 ; Issuing the reset command ;------------------------------------------------------------------; RESOUS IOSEG ABS=00 ;Definition of the RESOUS I/O ORG 0000H ;segment PDR0 RB 1 PDR1 RB 1 PDR2 RB 1 PDR3 RB 1 ORG 0010H DDR0 RB 1 DDR1 RB 1 DDR2 RB 1 DDR3 RB 1 ORG 00A1H CKSCR RB 1 ORG 00AEH FMCS RB 1 ORG 006FH ROMM RB 1 RESOUS ENDS ; SSTA SSEG RW 0127H STA_T RW 1 390 CHAPTER 23 1M-BIT FLASH MEMORY SSTA ; DATA ENDS DSEG ABS=0FFH ;FLASH command address ORG 5554H COMADR2 RW 1 ORG 0AAAAH COMADR1 RW 1 DATA ENDS ;///////////////////////////////////////////////////////////// ;Main program (SA1) ;///////////////////////////////////////////////////////////// CODE CSEG START: ;///////////////////////////////////////////////////// ;Initialization ;///////////////////////////////////////////////////// MOV CKSCR,#0BAH ;Setting to threefold MOV RP,#0 MOV A,#!STA_T MOV SSB,A MOVW A,#STA_T MOVW SP,A MOV ROMM,#00H ;Mirror OFF MOV PDR0,#00H ;For error confirmation MOV DDR0,#0FFH MOV PDR1,#00H ;Data input port MOV DDR1,#00H MOV PDR2,#00H ;Data output port MOV DDR2,#0FFH ;/////////////////////////////////////////////////////////// ;The FLASH write deletion program (FFBC00H) is transferred ;to the RAM (address 700H). ;/////////////////////////////////////////////////////////// MOVW A,#0700H ;Transfer destination RAM area MOVW A,#0BC00H ;Transfer source address (program ; location) MOVW RW0,#100H ;Number of bytes to be transferred MOVS ADB,PCB ;100H transfer from FFBC00H to ; 000700H CALLP 000700H ;Jump to the address in which the ; transferred program exists ;///////////////////////////////////////////////////// ;Data output ;///////////////////////////////////////////////////// OUT MOV A,#0FEH MOV ADB,A MOVW RW2,#0000H MOVW A,@RW2+00 MOV PDR2,A END JMP * CODE ENDS ;//////////////////////////////////////////////////////////// ;FLASH write deletion program (SA4/SA3) ;//////////////////////////////////////////////////////////// RAMPRG CSEG ABS=0FFH ORG 0BC00H 391 CHAPTER 23 1M-BIT FLASH MEMORY ; ; ; ; ; //////////////////////////////////////////// Initialization //////////////////////////////////////////// MOVW RW0,#0500H ;RW0: RAM space for input data acquisition 00:0500 to MOVW RW2,#0000H ;RW2: Flash memory writing address FD:0000 to MOV A,#00H ;DTB change MOV DTB,A ;@RW0 bank specification MOV A,#0FEH ;ADB change 1 MOV ADB,A ;Specification of the bank for the ;write mode specification address MOV PDR3,#00H ;Switch initialization MOV DDR3,#00H ; WAIT1 BBC PDR3:0,WAIT1 ;PDR3:0 Start of writing with Hi ; ;//////////////////////////////////////////////// ; Writing(SA0) ;//////////////////////////////////////////////// MOV A,PDR1 MOVW @RW0+00,A ;Allocation of PDR1 data in ; the RAM MOV FMCS,#20H ;Write mode setting MOVW ADB:COMADR1,#00AAH ;Flash write command 1 MOVW ADB:COMADR2,#0055H ;Flash write command 2 MOVW ADB:COMADR1,#00A0H ;Flash write command 3 ; MOVW A,@RW0+00 ;Writing of input data (RW0) ; into the flash memory (RW2) MOVW @RW2+00,A WRITE ;Wait time check ; //////////////////////////////////////////////////////////// ; Error when the time limit excess check flag is set and the ; toggle operation is ongoing ; //////////////////////////////////////////////////////////// MOVW A,@RW2+00 AND A,#20H ;DQ5 time limit check BZ NTOW ;Time limit over MOVW A,@RW2+00 ;AH MOVW A,@RW2+00 ;AL XORW A ;XOR of AH and AL (1 if the ; value is different) AND A,#40H ;Is the DQ6 toggle bit ; different? BNZ ERROR ;If it is different, go to ; ERROR. ; /////////////////////////////////////// ; Write end check (FMCS-RDY) ; /////////////////////////////////////// NTOW MOVW A,FMCS AND A,#10H ;Extraction of the FMCS RDY ;bit (4 bits) BZ WRITE ;Is writing ended? MOV FMCS,#00H ;Release of the write mode 392 CHAPTER 23 1M-BIT FLASH MEMORY ;///////////////////////////////////////////////////// ;Write data output ;///////////////////////////////////////////////////// MOVW RW2,#0000H ;Write data output MOVW A,@RW2+00 MOV PDR2,A ; WAIT2 BBC PDR3:1,WAIT2 ;PDR3:1 Start of the sector ;deletion with Hi ; ;///////////////////////////////////////////// ;Sector deletion (SA0) ;///////////////////////////////////////////// MOV @RW2+00,#0000H ;Address initialization MOV FMCS,#20H ;Deletion mode setting MOVW ADB:COMADR1,#00AAH ;Flash deletion command 1 MOVW ADB:COMADR2,#0055H ;Flash deletion command 2 MOVW ADB:COMADR1,#0080H ;Flash deletion command 3 MOVW ADB:COMADR1,#00AAH ;Flash deletion command 4 MOVW ADB:COMADR2,#0055H ;Flash deletion command 5 MOV @RW2+00,#0030H ;Issuance of the deletion ; command to the sector to be ; deleted 6 ELS ;Wait time check ; //////////////////////////////////////////////////////////// ; Error when the time limit excess check flag is set and the ; toggle operation is ongoing ; //////////////////////////////////////////////////////////// MOVW A,@RW2+00 AND A,#20H ;DQ5 time limit check BZ NTOE ;Time limit over MOVW A,@RW2+00 ;AH Hi and low are ; alternately output, MOVW A,@RW2+00 ;AL for each reading, ; from DQ6 during ; writing. XORW A ;XOR of AH and AL (1 writing ; (writing ongoing) ; if the DQ6 value is ; different) AND A,#40H ;Is the DQ6 toggle bit Hi? BNZ ERROR ;If it is Hi, go to ERROR. ; /////////////////////////////////////// ; Deletion end check (FMCS-RDY) ; /////////////////////////////////////// NTOE MOVW A,FMCS ; AND A,#10H ;Extraction of the FMCS RDY ; bit (4 bits) BZ ELS ;Is sector deletion ended? MOV FMCS,#00H ;Release of the FLASH ; deletion mode RETP ;Return to the main program ;////////////////////////////////////////////// ;Error ;////////////////////////////////////////////// ERROR MOV ADB:COMADR1,#0F0H ;Reset command (reading ; possible) 393 CHAPTER 23 1M-BIT FLASH MEMORY MOV MOV ; FMCS,#00H PDR0,#0FFH ;Release of the FLASH mode ;Confirmation of the error handling ;Return to the main program RETP RAMPRG ENDS ;///////////////////////////////////////////// VECT CSEG ABS=0FFH ORG 0FFDCH DSL START DB 00H VECT ENDS ; END START 394 CHAPTER 24 EXAMPLES OF F2MC-16LX MB90F598/F598G SERIAL PROGRAMMING CONNECTION CHAPTER 24 EXAMPLES OF F2MC-16LX MB90F598/ F598G SERIAL PROGRAMMING CONNECTION This chapter provides examples of F2MC-16LX MB90F598/F598G serial programming connection. 24.1 "Basic Configuration of F2MC-16LX MB90F598/F598G Serial Programming Connection" 24.2 "Example of Serial Programming Connection (User Power Supply Used)" 24.3 "Example of Serial Programming Connection (Power Supplied from the Programmer)" 24.4 "Example of Minimum Connection to the Flash Microcontroller Programmer (User Power Supply Used)" 24.5 "Example of Minimum Connection to the Flash Microcontroller Programmer (Power Supplied from the Programmer)" 395 CHAPTER 24 EXAMPLES OF F2MC-16LX MB90F598/F598G SERIAL PROGRAMMING CONNECTION 24.1 Basic Configuration of F2MC-16LX MB90F598/F598G Serial Programming Connection The MB90F598/F598G supports flash ROM serial onboard writing (Fujitsu standard). This section describes the specifications. ■ Basic Configuration of F2MC-16LX MB90F598/F598G Serial Programming Connection The AF220/AF210/AF120/AF110 flash microcontroller programmer from Yokogawa Digital Computer Co., Ltd. is used for Fujitsu standard serial onboard writing. Host interface cable (AZ201) AF220/AF210/ AF120/AF110 flash microcontroller programmer + memory card General-purpose common cable (AZ210) CLK synchronous serial MB90F598/ MB90F598G user system Stand-alone operation enabled Note: Ask the company representative from Yokogawa Digital Computer Co., Ltd for details about the functions and operations of the AF220/AF210/AF120/AF110 flash microcontroller programmer, general-purpose common cable for connection (AZ210), and connectors. Table 24.1-1 Pins Used for Fujitsu Standard Serial Onboard Writing (1/2) Pin 396 Function Additional information MD2, MD1, MD0 Mode pins Controls programming mode from the flash microcontroller programmer. X0, X1 Oscillation pins In programming mode, the CPU internal operation clock signal is one multiple of the PLL clock signal frequency. Therefore, because the oscillation clock frequency becomes the internal operation clock signal, the resonator used for serial rewriting is 3 MHz to 5 MHz. P00, P01 programming activation pins — RST Reset pin — CHAPTER 24 EXAMPLES OF F2MC-16LX MB90F598/F598G SERIAL PROGRAMMING CONNECTION Table 24.1-1 Pins Used for Fujitsu Standard Serial Onboard Writing (2/2) Pin Function SIN1 Serial data input pin SOT1 Serial data output pin Additional information UART0 is used for CLK synchronous mode. SCK1 Serial clock signal input pin C C pin This external capacitor pin is used to stabilize the power supply. Connect a ceramic capacitor of approximately 0.1 µF to the outside. VCC Supply voltage pin If the programming voltage (5 V 10%) is supplied from the user system, the flash microcontroller programmer need not be connected. Connect so that the power supply on the user side is not shortcircuited. VSS GND pin Common to the ground of the flash microcontroller programmer. HST Hardware standby pin Input high level during serial programming mode. Even if the P00, SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required. The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial writing. Sections 24.2 "Example of Serial Programming Connection (User Power Supply Used)" to 24.5 "Example of Minimum Connection to the Flash Microcontroller Programmer (Power Supplied from the Programmer)" present examples of the following four types of serial programming connection. See each section as required. • Serial programming connection (user power supply used) • Serial programming connection (power supplied from the programmer) • Minimum connection to the flash microcontroller programmer (user power supply used) • Minimum connection to the flash microcontroller programmer (power supplied from the programmer) AF220/AF210/ AF120/AF110 write control pin MB90F598/MB90F598G write control pin 10kΩ AF220/AF210/ AF120/AF110 /TICS pin User 397 CHAPTER 24 EXAMPLES OF F2MC-16LX MB90F598/F598G SERIAL PROGRAMMING CONNECTION Table 24.1-2 System Configuration of Flash Microcontroller Programmers (Manufactured by Yokogawa Digital Computer Co., Ltd.) Model Main unit Function AF220/AC4P Ethernet interface built-in model and 100 to 220 V AC power adapter AF210/AC4P Standard model and 100 to 220 V AC power adapter AF120/AC4P Single-key Ethernet interface built-in model and 100 to 220 V AC power adapter AF110/AC4P Single-key model and 100 to 220 V AC power adapter AZ221 PC/AT RS232C cable for programmer AZ210 Standard target probe (a) with a 1 m cable FF201 Fujitsu F2MC-16LX flash microcontroller control module /P2 2 MB PC card (optional) for flash memory sizes up to 128 KB /P4 4 MB PC card (optional) for flash memory sizes up to 512 KB Inquiries: Yokogawa Digital Computer Co., Ltd. Telephone number: (81)-42-333-6224 Note: Although the AF200 flash microcontroller programmer is no longer manufactured, the programmer still can be used in combination with the FF201 control module. Examples of serial programming connection are given in Sections 24.2 "Example of Serial Programming Connection (User Power Supply Used)" and 24.3 "Example of Serial Programming Connection (Power Supplied from the Programmer)". 398 CHAPTER 24 EXAMPLES OF F2MC-16LX MB90F598/F598G SERIAL PROGRAMMING CONNECTION ■ Oscillating Clock Frequency and Serial Clock Input Frequency The equation listed below can be used to calculate the serial clock frequencies that can be used for the MB90F598/F598G. Set an appropriate serial clock input frequency in the flash microcontroller programmer according to the oscillating clock frequency in use. Serial clock frequency that can be used = 0.125 x oscillating clock frequency Table 24.1-3 Examples of Serial Clock Frequencies that can be Used Oscillating clock frequency Maximum serial clock frequency that can be used for microcontrollers Maximum serial clock frequency that can be used for the AF220, AF210, AF120, and AF110 Maximum serial clock frequency that can be used for the AF200 4 MHz 500 kHz 500 kHz 500 kHz 8 MHz * 1 MHz 850 kHz 500 kHz 16 MHz * 2 MHz 1.25 MHz 500 kHz *: External clock only 399 CHAPTER 24 EXAMPLES OF F2MC-16LX MB90F598/F598G SERIAL PROGRAMMING CONNECTION 24.2 Example of Serial Programming Connection (User Power Supply Used) Figure 24.2-1 is an example of a serial programming connection for internal vector modes (single-chip mode) when the user power supply is used. The value 1 and 0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the AF220/AF210/AF120/AF110 programmer. Serial reprogramming mode: MD2, MD1, MD0 = 110. ■ Example of Serial Programming Connection (User Power Supply Used) Figure 24.2-1 Example of Serial Programming Connection for MB90F598/F598G Internal Vector Modes (User Power Supply Used) AF220/AF210/AF120/AF110 User system flash microcontroller Connector programmer DX10-28S or DX20-28S TAUX3 MB90F598/F598G MD2 (19) 10kΩ 10kΩ MD1 10kΩ TMODE MD0 X0 (12) 3MHz to 5MHz X1 TAUX P00 (23) 10kΩ /TICS (10) User 10kΩ User HST 10kΩ /TRES RST (5) 10kΩ P01 C User 0.1µF TTXD TRXD TCK (13) (27) (6) TVcc (2) GND (7,8, 14,15. 21,22 1,28) SIN1 SOT1 SCK1 Vcc User power supply Vss Pin 14 Pins 3, 4, 9, 11, 16, 17, 18, 20, 24, 25, and 26 are open. DX10-28S: Right-angle type DX20-28S: Straight type 400 Pin 1 DX10-28S DX20-28S Pin 28 Pin 15 Connector (Hirose Electronics Ltd.) pin arrangement CHAPTER 24 EXAMPLES OF F2MC-16LX MB90F598/F598G SERIAL PROGRAMMING CONNECTION • Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required in the same way that it is for P00. The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial writing. • Connect the AF220/AF210/AF120/AF110 while the user power is off. AF220/AF210/ AF120/AF110 write control pin MB90F598/MB90F598G write control pin 10kΩ AF220/AF210/ AF120/AF110 /TICS pin User 401 CHAPTER 24 EXAMPLES OF F2MC-16LX MB90F598/F598G SERIAL PROGRAMMING CONNECTION 24.3 Example of Serial Programming Connection (Power Supplied from the Programmer) Figure 24.3-1 is an example of a serial programming connection for internal vector modes (single-chip mode) when power is supplied from the programmer. The value 1 and 0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the AF220/AF210/AF120/AF110 programmer. Serial reprogramming mode: MD2, MD1, MD0 = 110. ■ Example of Serial Programming Connection (Power Supplied from the Programmer) Figure 24.3-1 Example of Serial Programming Connection for MB90F598/F598G Internal Vector Modes (Power Supplied from the Programmer) AF220/AF210/AF120/AF110 User system flash microcontroller Connector programmer DX10-28S or DX20-28S TAUX3 MB90F598/F598G MD2 (19) 10kΩ 10kΩ MD1 10kΩ TMODE MD0 X0 (12) 3MHz to 5MHz X1 TAUX P00 (23) 10kΩ /TICS (10) User 10kΩ User HST 10kΩ /TRES RST (5) 10kΩ User 0.1µF TTXD TRXD TCK TVcc Vcc TVPP1 GND (13) (27) (6) (2) (3) (16) (7,8, 14,15. 21,22 1,28) Pins 4, 9, 11, 17, 18, 20, 24, 25, and 26 are open. DX10-28S: Right-angle type DX20-28S: Straight type P01 C SIN1 SOT1 SCK1 Vcc User power supply Vss Pin 14 Pin 1 Pin 28 Pin 15 DX10-28S DX20-28S Connector (Hirose Electronics Ltd.) pin arrangement 402 CHAPTER 24 EXAMPLES OF F2MC-16LX MB90F598/F598G SERIAL PROGRAMMING CONNECTION • Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required in the same way that it is for P00. The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial writing. • Connect the AF220/AF210/AF120/AF110 while the user power is off. • When the programming power is supplied from the AF220/AF210/AF120/AF110, be careful not to short-circuit the user power supply. AF220/AF210/ AF120/AF110 write control pin MB90F598/MB90F598G write control pin 10kΩ AF220/AF210/ AF120/AF110 /TICS pin User 403 CHAPTER 24 EXAMPLES OF F2MC-16LX MB90F598/F598G SERIAL PROGRAMMING CONNECTION 24.4 Example of Minimum Connection to the Flash Microcontroller Programmer (User Power Supply Used) Figure 24.4-1 is an example of the minimum connection to the flash microcontroller programmer when the user power supply is used. Serial reprogramming mode: MD2, MD1, MD0 = 110. ■ Example of Minimum Connection to the Flash Microcontroller Programmer (User Power Supply Used) For a flash memory write, the MD2, MD1, MD0, and P00 pins and flash microcontroller programmer need not be connected if the pins are set as described below. Figure 24.4-1 Example of Minimum Connection to the Flash Microcontroller Programmer (User Power Supply Used) AF220/AF210/AF120/AF110 flash microcontroller programmer User system MB90F598/F598G 1 for serial reprogrmming 10kΩ MD2 10kΩ 10kΩ 10kΩ 10kΩ 1 for serial reprogrmming MD1 MD0 0 for serial reprogrmming 10kΩ X0 3MHz to 5MHz 0 for serial reprogrmming 10kΩ X1 P00 10kΩ User circuit P01 1 for serial reprogrmming 10kΩ Connector DX10-28S or DX20-28S /TRES TTXD TRXD TCK TVcc GND (5) User circuit 0.1µF 10kΩ RST (13) SIN1 SOT1 SCK1 (27) (6) (2) (7,8, 14,15, 21,22, 1,28) HST C Vcc User power supply Pins 3, 4, 9, 10, 11, 12, 17, 18, 19, 20, 23, 24, 25, and 26 are open. DX10-28S: Right-angle type Vss Pin 14 Pin 1 Pin 28 Pin 15 DX10-28S Connector (Hirose Electronics Ltd.) pin arrangement 404 CHAPTER 24 EXAMPLES OF F2MC-16LX MB90F598/F598G SERIAL PROGRAMMING CONNECTION • Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required. The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial writing. • Connect the AF220/AF210/AF120/AF110 while the user power is off. AF220/AF210/ AF120/AF110 write control pin MB90F598/MB90F598G write control pin 10kΩ AF220/AF210/ AF120/AF110 /TICS pin User 405 CHAPTER 24 EXAMPLES OF F2MC-16LX MB90F598/F598G SERIAL PROGRAMMING CONNECTION 24.5 Example of Minimum Connection to the Flash Microcontroller Programmer (Power Supplied from the Programmer) Figure 24.5-1 is an example of the minimum connection to the flash microcontroller programmer (power supplied from the programmer)" is an example of the minimum connection to the flash microcontroller programmer when power is supplied from the programmer. Serial reprogramming mode: MD2, MD1, MD0 = 110B. ■ Example of Minimum Connection to the Flash Microcontroller Programmer (Power Supplied from the Programmer) For a flash memory write, the MD2, MD1, MD0, and P00 pins and flash microcontroller programmer need not be connected if the pins are set as described below. Figure 24.5-1 Example of Minimum Connection to the Flash Microcontroller Programmer (Power Supplied from the Programmer) AF220/AF210/AF120/AF110 flash microcontroller programmer User system MB90F598/F598G 1 for serial reprogrmming 10kΩ MD2 10kΩ 10kΩ MD1 1 for serial reprogrmming 10kΩ 10kΩ MD0 0 for serial reprogrmming 10kΩ X0 3MHz to 5MHz 0 for serial reprogrmming 10kΩ X1 P00 10kΩ User circuit P01 1 for serial reprogrmming User circuit 10kΩ Connector DX10-28S or DX20-28S /TRES TTXD TRXD TCK TVcc Vcc TVPP1 GND (5) 0.1µF 10kΩ RST (13) SIN1 SOT1 SCK1 (27) (6) (2) (3) (16) (7,8, 14,15, 21,22, 1,28) HST C Vcc User power supply Pins 4, 9, 10, 11, 12, 17, 18, 19, 20, 23, 24, 25, and 26 are open. DX10-28S: Right-angle type Vss Pin 14 Pin 1 Pin 28 Pin 15 DX10-28S Connector (Hirose Electronics Ltd.) pin arrangement 406 CHAPTER 24 EXAMPLES OF F2MC-16LX MB90F598/F598G SERIAL PROGRAMMING CONNECTION • Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required. The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial writing. • Connect the AF220/AF210/AF120/AF110 while the user power is off. • When the programming power is supplied from the AF220/AF210/AF120/AF110, be careful not to short-circuit the user power supply. AF220/AF210/ AF120/AF110 write control pin MB90F598/MB90F598G write control pin 10kΩ AF220/AF210/ AF120/AF110 /TICS pin User 407 CHAPTER 24 EXAMPLES OF F2MC-16LX MB90F598/F598G SERIAL PROGRAMMING CONNECTION 408 APPENDIX The appendixes provide I/O maps, instructions, and other information. APPENDIX A "I/O Maps" APPENDIX B "Instructions" APPENDIX C "Timing Diagrams in Flash Memory Mode" APPENDIX D "List of MB90595 Interrupt Vectors" 409 APPENDIX A I/O Maps APPENDIX A I/O Maps Table A-1 lists the addresses assigned to the registers in the peripheral function blocks. ■ I/O Maps Table A-1 I/O Map (1) (1/6) Address Register Access Peripheral Initial value 00 H Port 0 Data Register PDR0 R/W Port 0 XXXXXXXXB 01 H Port 1 Data Register PDR1 R/W Port 1 XXXXXXXXB 02 H Port 2 Data Register PDR2 R/W Port 2 XXXXXXXXB 03 H Port 3 Data Register PDR3 R/W Port 3 XXXXXXXXB 04 H Port 4 Data Register PDR4 R/W Port 4 XXXXXXXXB 05 H Port 5 Data Register PDR5 R/W Port 5 XXXXXXXXB 06 H Port 6 Data Register PDR6 R/W Port 6 XXXXXXXXB 07 H Port 7 Data Register PDR7 R/W Port 7 XXXXXXXXB 08 H Port 8 Data Register PDR8 R/W Port 8 XXXXXXXXB 09 H Port 9 Data Register PDR9 R/W Port 9 --XXXXXXB 0A to 0F H Reserved 10 H Port 0 Direction Register DDR0 R/W Port 0 00000000B 11 H Port 1 Direction Register DDR1 R/W Port 1 00000000B 12 H Port 2 Direction Register DDR2 R/W Port 2 00000000B 13 H Port 3 Direction Register DDR3 R/W Port 3 00000000B 14 H Port 4 Direction Register DDR4 R/W Port 4 00000000B 15 H Port 5 Direction Register DDR5 R/W Port 5 00000000B 16 H Port 6 Direction Register DDR6 R/W Port 6 00000000B 17 H Port 7 Direction Register DDR7 R/W Port 7 00000000B 18 H Port 8 Direction Register DDR8 R/W Port 8 00000000B 19 H Port 9 Direction Register DDR9 R/W Port 9 --000000B R/W Port 6, A/D 11111111B 1A H 1B H 1C to 1F H 410 Abbreviation Reserved Analog Input Enable Register ADER Reserved APPENDIX A I/O Maps Table A-1 I/O Map (1) (2/6) Address Register Abbreviation Access Peripheral Initial value 20 H Serial Mode Control Register 0 UMC0 R/W 00000100B 21 H Status Register 0 USR0 R/W 00010000B 22 H Input/Output Data Register 0 UIDR0/ UODR0 R/W XXXXXXXXB 23 H Rate and Data Register 0 URD0 R/W 0000000XB 24 H Serial Mode Register 1 SMR1 R/W 00000000B 25 H Serial Control Register 1 SCR1 R/W 00000100B 26 H Input/Output Data Register 1 SIDR1/ SODR1 R/W 27 H Serial Status Register 1 SSR1 R/W 00001-00B 28 H UART1 Prescaler Control Register U1CDCR R/W 0---1111B SCDCR R/W 0---1111B ----0000B 29 to 2A H UART0 UART1 (SCI) XXXXXXXXB Reserved 2B H Serial IO Prescaler 2C H Serial Mode Control Register (loworder) SMCS R/W 2D H Serial Mode Control Register (highorder) SMCS R/W 2E H Serial Data Register SDR R/W XXXXXXXXB 2F H Edge Selector Register SES R/W -------0B 30 H External Interrupt Enable Register ENIR R/W 00000000B 31 H External Interrupt Request Register EIRR R/W XXXXXXXXB 32 H External Interrupt Level Register (low-order) ELVR R/W 33 H External Interrupt Level Register (high-order) ELVR R/W 00000000B 34 H A/D Control Status Register 0 ADCS0 R/W 00000000B 35 H A/D Control Status Register 1 ADCS1 R/W 36 H A/D Data Register 0 ADCR0 R XXXXXXXXB 37 H A/D Data Register 1 ADCR1 R/W 00001-XXB 38 H PPG0 Operation Mode Control Register PPGC0 R/W 39 H PPG1 Operation Mode Control Register PPGC1 R/W 3A H PPG0, 1 Output Pin Control Register PPG01 R/W 3B H Serial IO External Interrupt A/D Converter 16-bit Programmable Pulse Generator 0/1 00000010B 00000000B 00000000B 0-000--1B 0-000001B 000000--B Reserved 411 APPENDIX A I/O Maps Table A-1 I/O Map (1) (3/6) Abbreviation Access PPG2 Operation Mode Control Register PPGC2 R/W 3D H PPG3 Operation Mode Control Register PPGC3 R/W 3E H PPG2, 3 Output Pin Control Register PPG23 R/W Address 3C H Register 3F H 40 H PPGC4 41 H PPG5 Operation Mode Control Register PPGC5 R/W 42 H PPG4, 5 Output Pin Control Register PPG45 R/W 43 H 45 H PPG7 Operation Mode Control Register PPGC7 R/W 46 H PPG6, 7 Output Pin Control Register PPG67 R/W 47 H 16-bit Programmable Pulse Generator 4/5 0-000--1B 0-000001B 000000--B R/W 16-bit Programmable Pulse Generator 6/7 0-000--1B 0-000001B 000000--B Reserved PPG8 Operation Mode Control Register PPGC8 49 H PPG9 Operation Mode Control Register PPGC9 R/W 4A H PPG8, 9 Output Pin Control Register PPG89 R/W 4B H R/W 16-bit Programmable Pulse Generator 8/9 0-000--1B 0-000001B 000000--B Reserved PPGA Operation Mode Control Register PPGCA 4D H PPGB Operation Mode Control Register PPGCB R/W 4E H PPGA, B Output Pin Control Register PPGAB R/W 000000--B 4F H 412 0-000001B Reserved PPGC6 4C H 0-000--1B 000000--B R/W PPG6 Operation Mode Control Register 48 H 16-bit Programmable Pulse Generator 2/3 Initial value Reserved PPG4 Operation Mode Control Register 44 H Peripheral R/W 16-bit Programmable Pulse Generator A/B 0-000--1B 0-000001B Reserved 50 H Timer Control Status Register 0 TMCSR0 R/W 00000000B 51 H Timer Control Status Register 0 TMCSR0 R/W ---0000B 52 H Timer Register 0/Reload Register 0 TMR0/ TMRLR0 R/W 53 H Timer Register 0/Reload Register 0 TMR0/ TMRLR0 R/W 16-bit Reload Timer 0 XXXXXXXXB XXXXXXXXB APPENDIX A I/O Maps Table A-1 I/O Map (1) (4/6) Address Register Abbreviation Access Peripheral Initial value 54 H Timer Control Status Register 1 TMCSR1 R/W 00000000B 55 H Timer Control Status Register 1 TMCSR1 R/W ---0000B 56 H Timer Register 1/Reload Register 1 TMR1/ TMRLR1 R/W 57 H Timer Register 1/Reload Register 1 TMR1/ TMRLR1 R/W 58 H Output Compare Control Status Register 0 OCS0 R/W 59 H Output Compare Control Status Register 1 OCS1 R/W 5A H Output Compare Control Status Register 2 OCS2 R/W 5B H Output Compare Control Status Register 3 OCS3 R/W 5C H Input Capture Control Status Register 0/1 ICS01 R/W Input Capture 0/1 00000000B 5D H Input Capture Control Status Register 2/3 ICS23 R/W Input Capture 2/3 00000000B 5E H PWM Control Register 0 PWC0 R/W Stepping Motor Controller 0 00000--0B R/W Stepping Motor Controller 1 00000--0B R/W Stepping Motor Controller 2 00000--0B R/W Stepping Motor Controller 3 00000--0B 5F H 60 H PWM Control Register 1 XXXXXXXXB Output Compare 0/1 0000--00B ---00000B Output Compare 2/3 0000--00B ---00000B PWC1 Reserved PWM Control Register 2 63 H 64 H XXXXXXXXB Reserved 61 H 62 H 16-bit Reload Timer 1 PWC2 Reserved PWM Control Register 3 65 H PWC3 Reserved 66 H Timer Data Register (low-order) TCDT R/W 67 H Timer Data Register (high-order) TCDT R/W 68 H Timer Control Status Register TCCS R/W 00000000B IO Timer 00000000B 00000000B 413 APPENDIX A I/O Maps Table A-1 I/O Map (1) (5/6) Address Register 69 to 6E Abbreviation Access Peripheral Initial value ROM Mirror -------1B Reserved H 6F H ROM Mirror Function Selection Register ROMM R/W 70 H PWM1 Compare Register 0 PWC10 R/W 71 H PWM2 Compare Register 0 PWC20 R/W 72 H PWM1 Select Register 0 PWS10 R/W 73 H PWM2 Select Register 0 PWS20 R/W -0000000B 74 H PWM1 Compare Register 1 PWC11 R/W XXXXXXXXB 75 H PWM2 Compare Register 1 PWC21 R/W 76 H PWM1 Select Register 1 PWS11 R/W 77 H PWM2 Select Register 1 PWS21 R/W -0000000B 78 H PWM1 Compare Register 2 PWC12 R/W XXXXXXXXB 79 H PWM2 Compare Register 2 PWC22 R/W 7A H PWM1 Select Register 2 PWS12 R/W 7B H PWM2 Select Register 2 PWS22 R/W -0000000B 7C H PWM1 Compare Register 3 PWC13 R/W XXXXXXXXB 7D H PWM2 Compare Register 3 PWC23 R/W 7E H PWM1 Select Register 3 PWS13 R/W 7F H PWM2 Select Register 3 PWS23 R/W XXXXXXXXB Stepping Motor Controller 0 Stepping Motor Controller 1 Stepping Motor Controller 2 Stepping Motor Controller 3 XXXXXXXXB --000000B XXXXXXXXB --000000B XXXXXXXXB --000000B XXXXXXXXB --000000B -0000000B 80 to 8F H Reserved for CAN Interface. Refer to CHAPTER 19 "CAN CONTROLLER" 90 to 9D H Reserved 9E H R/W Address Match Detection Function 00000000B DIRR R/W Delayed Interrupt -------0B Low-Power Mode Control Register LPMCR R/W Low Power Controller 00011000B Clock Selection Register CKSCR R/W Low Power Controller 11111100B R/W Watchdog Timer XXXXX111B Program Address Detection Control Status Register PACSR 9F H Delayed Interrupt Request Register A0 H A1 H A2 to A7 H A8 H 414 Reserved Watchdog timer Control Register WDTC APPENDIX A I/O Maps Table A-1 I/O Map (1) (6/6) Address A9 H Register Abbreviation Access Peripheral Initial value TBTC R/W Time Base Timer 1--00100B R/W Flash Memory 000X0000B Time-base Timer Control Register AA to AD H AE H Reserved Flash Memory Control Status Register (MB90F598/598G only. Otherwise reserved) AF H FMCS Reserved B0 H Interrupt Control Register 00 ICR00 R/W 00000111B B1 H Interrupt Control Register 01 ICR01 R/W 00000111B B2 H Interrupt Control Register 02 ICR02 R/W 00000111B B3 H Interrupt Control Register 03 ICR03 R/W 00000111B B4 H Interrupt Control Register 04 ICR04 R/W 00000111B B5 H Interrupt Control Register 05 ICR05 R/W 00000111B B6 H Interrupt Control Register 06 ICR06 R/W 00000111B B7 H Interrupt Control Register 07 ICR07 R/W B8 H Interrupt Control Register 08 ICR08 R/W B9 H Interrupt Control Register 09 ICR09 R/W 00000111B BA H Interrupt Control Register 10 ICR10 R/W 00000111B BB H Interrupt Control Register 11 ICR11 R/W 00000111B BC H Interrupt Control Register 12 ICR12 R/W 00000111B BD H Interrupt Control Register 13 ICR13 R/W 00000111B BE H Interrupt Control Register 14 ICR14 R/W 00000111B BF H Interrupt Control Register 15 ICR15 R/W 00000111B C0 to FF H Interrupt controller 00000111B 00000111B Reserved Table A-2 I/O Map (2) (1/4) Address 1900 H Register Reload Register L Abbreviation Access PRLL0 R/W 1901 H Reload Register H PRLH0 R/W 1902 H Reload Register L PRLL1 R/W 1903 H Reload Register H PRLH1 R/W Peripheral Initial value XXXXXXXXB 16-bit Programmable Pulse Generator 0/1 XXXXXXXXB XXXXXXXXB XXXXXXXXB 415 APPENDIX A I/O Maps Table A-2 I/O Map (2) (2/4) Address 1904 H Register Reload Register L Abbreviation Access PRLL2 R/W 1905 H Reload Register H PRLH2 R/W 1906 H Reload Register L PRLL3 R/W 1907 H Reload Register H PRLH3 R/W 1908 H Reload Register L PRLL4 R/W 1909 H Reload Register H PRLH4 R/W 190A H Reload Register L PRLL5 R/W 190B H Reload Register H PRLH5 R/W 190C H Reload Register L PRLL6 R/W 190D H Reload Register H PRLH6 R/W 190E H Reload Register L PRLL7 R/W 190F H Reload Register H PRLH7 R/W 1910 H Reload Register L PRLL8 R/W 1911 H Reload Register H PRLH8 R/W 1912 H Reload Register L PRLL9 R/W 1913 H Reload Register H PRLH9 R/W 1914 H Reload Register L PRLLA R/W 1915 H Reload Register H PRLHA R/W 1916 H Reload Register L PRLLB R/W 1917 H Reload Register H PRLHB R/W 1918 to 191F H Peripheral Initial value XXXXXXXXB 16-bit Programmable Pulse Generator 2/3 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 16-bit Programmable Pulse Generator 4/5 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 16-bit Programmable Pulse Generator 6/7 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 16-bit Programmable Pulse Generator 8/9 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 16-bit Programmable Pulse Generator A/B XXXXXXXXB XXXXXXXXB XXXXXXXXB Reserved 1920 H Input Capture Register 0 (low-order) IPCP0 R XXXXXXXXB 1921 H Input Capture Register 0 (high-order) IPCP0 R XXXXXXXXB 1922 H Input Capture Register 1 (low-order) IPCP1 R XXXXXXXXB 1923 H Input Capture Register 1 (high-order) IPCP1 R XXXXXXXXB Input Capture 0/1 416 APPENDIX A I/O Maps Table A-2 I/O Map (2) (3/4) Address Register Abbreviation Access Peripheral Initial value 1924 H Input Capture Register 2 (low-order) IPCP2 R XXXXXXXXB 1925 H Input Capture Register 2 (high-order) IPCP2 R XXXXXXXXB 1926 H Input Capture Register 3 (low-order) IPCP3 R XXXXXXXXB 1927 H Input Capture Register 3 (high-order) IPCP3 R XXXXXXXXB 1928 H Output Compare Register 0 (low-order) OCCP0 R/W XXXXXXXXB 1929 H Output Compare Register 0 (high-order) OCCP0 R/W XXXXXXXXB 192A H Output Compare Register 1 (low-order) OCCP1 R/W XXXXXXXXB 192B H Output Compare Register 1 (high-order) OCCP1 R/W XXXXXXXXB 192C H Output Compare Register 2 (low-order) OCCP2 R/W XXXXXXXXB 192D H Output Compare Register 2 (high-order) OCCP2 R/W XXXXXXXXB 192E H Output Compare Register 3 (low-order) OCCP3 R/W XXXXXXXXB 192F H Output Compare Register 3 (high-order) OCCP3 R/W XXXXXXXXB Input Capture 2/3 Output Compare 0/1 Output Compare 2/3 1930 to 19FF H Reserved 1A00 to 1AFF H Reserved for CAN Interface. Refer to CHAPTER 19 "CAN CONTROLLER" 1B00 to 1BFF H Reserved for CAN Interface. Refer to CHAPTER 19 "CAN CONTROLLER" 1C00 to 1EFF H Reserved 417 APPENDIX A I/O Maps Table A-2 I/O Map (2) (4/4) Address Register Abbreviation Access Peripheral Initial value 1FF0 H Program Address Detection Register 0 (low-order) PADR0 R/W XXXXXXXXB 1FF1 H Program Address Detection Register 0 (middle-order) PADR0 R/W XXXXXXXXB 1FF2 H Program Address Detection Register 0 (high-order) PADR0 R/W 1FF3 H Program Address Detection Register 1 (low-order) PADR1 R/W XXXXXXXXB 1FF4 H Program Address Detection Register 1 (middle-order) PADR1 R/W XXXXXXXXB 1FF5 H Program Address Detection Register 1 (high-order) PADR1 R/W XXXXXXXXB Address Match Detection Function 1FF6 to 1FFF H Reserved • Initial value of “?” represents unused bit, "X" represents unknown value. • Addresses in the range 0000Hto 00FFH, which are not listed in the table, are reserved for the primary functions of the MCU. A read access to these reserved addresses results reading “X” and any write access should not be performed. • Explanation of "Access (R, W)" • 418 XXXXXXXXB • R/W: Both read and write enabled • R: Read only • W: Write only Explanation of "Initial value" • 0: The initial value of this bit is "0". • 1: The initial value of this bit is "1". • X: The initial value of this bit is undefined. • -: This bit is not used. The initial value is undefined. APPENDIX B Instructions APPENDIX B Instructions APPENDIX B describes the instructions used by the F2MC-16LX. B.1 Instruction Types B.2 Addressing B.3 Direct Addressing B.4 Indirect Addressing B.5 Execution Cycle Count B.6 Effective Address Field B.7 How to Read the Instruction List B.8 F2MC-16LX Instruction List B.9 Instruction Map 419 APPENDIX B Instructions B.1 Instruction Types The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an effective address field of each instruction or using the instruction code itself. ■ Instruction Types The F2MC-16LX supports the following 351 types of instructions: 420 • 41 transfer instructions (byte) • 38 transfer instructions (word or long word) • 42 addition/subtraction instructions (byte, word, or long word) • 12 increment/decrement instructions (byte, word, or long word) • 11 comparison instructions (byte, word, or long word) • 11 unsigned multiplication/division instructions (word or long word) • 11 signed multiplication/division instructions (word or long word) • 39 logic instructions (byte or word) • 6 logic instructions (long word) • 6 sign inversion instructions (byte or word) • 1 normalization instruction (long word) • 18 shift instructions (byte, word, or long word) • 50 branch instructions • 6 accumulator operation instructions (byte or word) • 28 other control instructions (byte, word, or long word) • 21 bit operation instructions • 10 string instructions APPENDIX B Instructions B.2 Addressing With the F2MC-16LX, the address format is determined by the instruction effective address field or the instruction code itself (implied). When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used. Some instructions permit the user to select several types of addressing. ■ Addressing The F2MC-16LX supports the following 23 types of addressing: • Immediate (#imm) • Register direct • Direct branch address (addr16) • Physical direct branch address (addr24) • I/O direct (io) • Abbreviated direct address (dir) • Direct address (addr16) • I/O direct bit address (io:bp) • Abbreviated direct bit address (dir:bp) • Direct bit address (addr16:bp) • Vector address (#vct) • Register indirect (@RWj j = 0 to 3) • Register indirect with post increment (@RWj+ j = 0 to 3) • Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) • Long register indirect with displacement (@RLi + disp8 i = 0 to 3) • Program counter indirect with displacement (@PC + disp16) • Register indirect with base index (@RW0 + RW7, @RW1 + RW7) • Program counter relative branch address (rel) • Register list (rlst) • Accumulator indirect (@A) • Accumulator indirect branch address (@A) • Indirectly-specified branch address (@ear) • Indirectly-specified branch address (@eam) 421 APPENDIX B Instructions ■ Effective Address Field Table B.2-1 lists the address formats specified by the effective address field. Table B.2-1 Effective Address Field Code Representation 00 R0 RW0 RL0 01 R1 RW1 (RL0) 02 R2 RW2 RL1 03 R3 RW3 (RL1) 04 R4 RW4 RL2 05 R5 RW5 (RL2) 06 R6 RW6 RL3 07 R7 RW7 (RL3) 08 @RW0 09 @RW1 Address format Register direct: Individual parts correspond to the byte, word, and long word types in order from the left. Default bank None DTB DTB Register indirect 0A @RW2 ADB 0B @RW3 SPB 0C @RW0+ DTB 0D @RW1+ DTB Register indirect with post increment 0E @RW2+ ADB 0F @RW3+ SPB 10 @RW0+disp8 DTB 11 @RW1+disp8 DTB Register indirect with 8-bit displacement 12 @RW2+disp8 ADB 13 @RW3+disp8 SPB 14 @RW4+disp8 DTB 15 @RW5+disp8 DTB Register indirect with 8-bit displacement 16 @RW6+disp8 ADB 17 @RW7+disp8 SPB 18 @RW0+disp16 DTB 19 @RW1+disp16 DTB Register indirect with 16-bit displacement 422 1A @RW2+disp16 ADB 1B @RW3+disp16 SPB 1C @RW0+RW7 Register indirect with index DTB 1D @RW1+RW7 Register indirect with index DTB 1E @PC+disp16 PC indirect with 16-bit displacement PCB 1F addr16 Direct address DTB APPENDIX B Instructions B.3 Direct Addressing An operand value, register, or address is specified explicitly in direct addressing mode. ■ Direct Addressing ● Immediate addressing (#imm) Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). Figure B.3-1 Example of Immediate Addressing (#imm) MOVW A, #01212H (This instruction stores the operand value in A.) Before execution A 2233 4455 After execution A 4455 1 2 1 2 (Some instructions transfer AL to AH.) ● Register direct addressing Specify a register explicitly as an operand. Table B.3-1 lists the registers that can be specified. Figure B.32 shows an example of register direct addressing. Table B.3-1 Direct Addressing Registers General-purpose register Special-purpose register Byte R0, R1, R2, R3, R4, R5, R6, R7 Word RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 Long word RL0, RL1, RL2, RL3 Accumulator A, AL Pointer SP * Bank PCB, DTB, USB, SSB, ADB Page DPR Control PS, CCR, RP, ILM *: One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on the value of the S flag bit in the condition code register (CCR). For branch instructions, the program counter (PC) is not specified in an instruction operand but is specified implicitly. 423 APPENDIX B Instructions Figure B.3-2 Example of Register Direct Addressing MOV R0, A (This instruction transfers the eight low-order bits of A to the generalpurpose register R0.) Before execution A 0716 2534 Memory space R0 After execution A 0716 2564 ?? Memory space R0 34 ● Direct branch addressing (addr16) Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which indicates the branch destination in the logical address space. Direct branch addressing is used for an unconditional branch, subroutine call, or software interrupt instruction. Bit23 to bit16 of the address are specified by the program bank register (PCB). Figure B.3-3 Example of Direct Branch Addressing (addr16) JMP 3B20H (This instruction causes an unconditional branch by direct branch addressing in a bank.) Before execution After execution 424 PC 3 C 2 0 PC 3 B 2 0 PCB 4 F PCB 4 F Memory space 4F3B20H Next instruction 4F3C20H 62 4F3C21H 20 4F3C22H 3B JMP 3B20H APPENDIX B Instructions ● Physical direct branch addressing (addr24) Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction. Figure B.3-4 Example of Direct Branch Addressing (addr24) JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit addressing.) Before execution After execution PC 3 C 2 0 PC 3 B 2 0 PCB 4 F PCB 3 3 Memory space 333B20H Next instruction 4F3C20H 63 4F3C21H 20 4F3C22H 3B 4F3C23H 33 JMPP 333B20H ● I/O direct addressing (io) Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB) and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an instruction using I/O direct addressing. Figure B.3-5 Example of I/O Direct Addressing (io) MOVW A, i : 0C0H (This instruction reads data by I/O direct addressing and stores it in A.) Before execution After execution A 0716 2534 Memory space 0000C0H EE 0000C1H FF A 2534 FFEE 425 APPENDIX B Instructions ● Abbreviated direct addressing (dir) Specify the eight low-order bits of a memory address explicitly in an operand. Address bit8 to bit15 are specified by the direct page register (DPR). Address bit16 to bit23 are specified by the data bank register (DTB). Figure B.3-6 Example of Abbreviated Direct Addressing (dir) MOV S : 20H, A (This instruction writes the contents of the eight low-order bits of A in abbreviated direct addressing mode.) Before execution A 4455 DPR 6 6 After execution A 4455 DPR 6 6 1212 DTB 7 7 Memory space 776620H 1212 DTB 7 7 ?? Memory space 776620H 12 ● Direct addressing (addr16) Specify the 16 low-order bits of a memory address explicitly in an operand. Address bit16 to bit23 are specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for this mode of addressing. Figure B.3-7 Example of Direct Addressing (addr16) MOVW A, 3B20H (This instruction reads data by direct addressing and stores it in A.) Before execution After execution 426 A 2020 A AABB AABB 0123 DTB 5 5 DTB 5 5 Memory space 553B21H 01 553B20H 23 APPENDIX B Instructions ● I/O direct bit addressing (io:bp) Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-8 Example of I/O Direct Bit Addressing (io:bp) SETB i : 0C1H : 0 (This instruction sets bits by I/O direct bit addressing.) Memory space Before execution 0000C1H 00 Memory space After execution 0000C1H 01 ● Abbreviated direct bit addressing (dir:bp) Specify the eight low-order bits of a memory address explicitly in an operand. Address bit8 to bit15 are specified by the direct page register (DPR). Address bit16 to bit23 are specified by the data bank register (DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-9 Example of Abbreviated Direct Bit Addressing (dir:bp) SETB S : 10H : 0 (This instruction sets bits by abbreviated direct bit addressing.) Memory space Before execution DTB 5 5 DPR 6 6 556610H 00 Memory space After execution DTB 5 5 DPR 6 6 556610H 01 ● Direct bit addressing (addr16:bp) Specify arbitrary bits in 64 kilobytes explicitly. Address bit16 to bit23 are specified by the data bank register (DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-10 Example of Direct Bit Addressing (addr16:bp) SETB 2222H : 0 (This instruction sets bits by direct bit addressing.) Memory space Before execution DTB 5 5 552222H 00 Memory space After execution DTB 5 5 552222H 01 427 APPENDIX B Instructions ● Vector Addressing (#vct) Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction. Figure B.3-11 Example of Vector Addressing (#vct) CALLV #15 (This instruction causes a branch to the address indicated by the interrupt vector specified in an operand.) Before execution PC 0 0 0 0 Memory space PCB F F After execution FFC000H EF FFFFE0H 00 FFFFE1H D0 CALLV #15 PC D 0 0 0 PCB F F Table B.3-2 CALLV Vector List Instruction Vector address L Vector address H CALLV #0 XXFFFEH XXFFFFH CALLV #1 XXFFFCH XXFFFDH CALLV #2 XXFFFAH XXFFFBH CALLV #3 XXFFF8H XXFFF9H CALLV #4 XXFFF6H XXFFF7H CALLV #5 XXFFF4H XXFFF5H CALLV #6 XXFFF2H XXFFF3H CALLV #7 XXFFF0H XXFFF1H CALLV #8 XXFFEEH XXFFEFH CALLV #9 XXFFECH XXFFEDH CALLV #10 XXFFEAH XXFFEBH CALLV #11 XXFFE8H XXFFE9H CALLV #12 XXFFE6H XXFFE7H CALLV #13 XXFFE4H XXFFE5H CALLV #14 XXFFE2H XXFFE3H CALLV #15 XXFFE0H XXFFE1H Note: A PCB register value is set in XX. Note: When the program bank register (PCB) is FFH, the vector area overlaps the vector area of INT #vct8 (#0 to #7). Use vector addressing carefully (see Table B.3-2 ). 428 APPENDIX B Instructions B.4 Indirect Addressing In indirect addressing mode, an address is specified indirectly by the address data of an operand. ■ Indirect Addressing ● Register indirect addressing (@RWj j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. Address bit16 to bit23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used. Figure B.4-1 Example of Register Indirect Addressing (@RWj j = 0 to 3) MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores it in A.) Before execution A 0716 2534 Memory space RW1 D 3 0 F After execution DTB 7 8 78D30FH EE 78D310H FF A 2534 FFEE RW1 D 3 0 F DTB 7 8 ● Register indirect addressing with post increment (@RWj+ j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. After operand operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word). Address bit16 to bit23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used. If the post increment results in the address of the register that specifies the increment, the incremented value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to writing by an instruction and, therefore, the register that would be incremented becomes write data. 429 APPENDIX B Instructions Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3) MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post increment and stores it in A.) Before execution A 0716 2534 Memory space RW1 D 3 0 F After execution DTB 7 8 78D30FH EE 78D310H FF A 2534 FFEE RW1 D 3 1 1 DTB 7 8 ● Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) Memory is accessed using the address obtained by adding an offset to the contents of general-purpose register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric values. Address bit16 to bit23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is used, or additional data bank register (ADB) when RW2 or RW6 is used. Figure B.4-3 Example of Register Indirect Addressing with Offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with an offset and stores it in A.) Before execution A 0716 2534 (+10H) RW1 D 3 0 F After execution A 2534 FFEE RW1 D 3 0 F 430 DTB 7 8 DTB 7 8 Memory space 78D31FH EE 78D320H FF APPENDIX B Instructions ● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3) Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value. Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3) MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with an offset and stores it in A.) Before execution A 0716 2534 (+25H) RL2 F 3 8 2 After execution 4B02 Memory space 824B27H EE 824B28H FF A 2534 FFEE RL2 F 3 8 2 4B02 ● Program counter indirect addressing with offset (@PC + disp16) Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one word long. Address bit16 to bit23 are specified by the program bank register (PCB). Note that the operand address of each of the following instructions is not deemed to be (next instruction address + disp16): • DBNZ eam, rel • DWBNZ eam, rel • CBNE eam, #imm8, rel • CWBNE eam, #imm16, rel • MOV eam, #imm8 • MOVW eam, #imm16 Figure B.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16) MOVW A, @PC+20H (This instruction reads data by program counter indirect addressing with an offset and stores it in A.) Before execution A 0716 2534 Memory space PCB C 5 PC 4 5 5 6 After execution A 2534 FFEE PCB C 5 PC 4 5 5 A +4 C54556H 73 C54557H 9E C54558H 20 C54559H 00 MOVW A, @PC+20H C5455AH . . . +20H C5457AH EE C5457BH FF 431 APPENDIX B Instructions ● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7) Memory is accessed using the address determined by adding RW0 or RW1 to the contents of generalpurpose register RW7. Address bit16 to bit23 are indicated by the data bank register (DTB). Figure B.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7) MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with a base index and stores it in A.) Before execution A 0716 RW1 D 3 0 F WR7 0 1 0 1 After execution A 2534 RW1 D 3 0 F WR7 0 1 0 1 432 2534 + DTB 7 8 FFEE DTB 7 8 Memory space 78D410H EE 78D411H FF APPENDIX B Instructions ● Program counter relative branch addressing (rel) The address of the branch destination is a value determined by adding an 8-bit offset to the program counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte bank. This addressing is used for both conditional and unconditional branch instructions. Address bit16 to bit23 are indicated by the program bank register (PCB). Figure B.4-7 Example of Program Counter Relative Branch Addressing (rel) BRA 10H (This instruction causes an unconditional relative branch.) Before execution After execution PC 3 C 2 0 PC 3 C 3 2 PCB 4 F PCB 4 F Memory space 4F3C32H Next instruction 4F3C21H 10 4F3C20H 60 BRA 10H ● Register list (rlst) Specify a register to be pushed onto or popped from a stack. Figure B.4-8 Configuration of the Register List MSB LSB RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0 A register is selected when the corresponding bit is 1 and deselected when the bit is 0. 433 APPENDIX B Instructions Figure B.4-9 Example of Register List (rlist) POPW, RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple word registers indicated by the register list.) SP 34FA SP 34FE RW0 ×× ×× RW0 02 01 RW1 ×× ×× RW1 ×× ×× RW2 ×× ×× RW2 ×× ×× RW3 ×× ×× RW3 ×× ×× RW4 ×× ×× RW4 04 03 RW5 ×× ×× RW5 ×× ×× RW6 ×× ×× RW6 ×× ×× RW7 ×× ×× RW7 ×× ×× Memory space SP Memory space 01 34FAH 01 34FAH 02 34FBH 02 34FBH 03 34FCH 03 34FCH 04 34FDH 04 34FEH 34FDH SP Before execution 34FEH After execution ● Accumulator indirect addressing (@A) Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the accumulator (AL). Address bit16 to bit23 are specified by a mnemonic in the data bank register (DTB). Figure B.4-10 Example of Accumulator Indirect Addressing (@A) MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.) Before execution A 0716 2534 DTB B B After execution A 0716 DTB B B 434 FFEE Memory space BB2534H EE BB2535H FF APPENDIX B Instructions ● Accumulator indirect branch addressing (@A) The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the accumulator. It indicates the branch destination in the bank address space. Address bit16 to bit23 are specified by the program bank register (PCB). For the Jump Context (JCTX) instruction, however, address bit16 to bit23 are specified by the data bank register (DTB). This addressing is used for unconditional branch instructions. Figure B.4-11 Example of Accumulator Indirect Branch Addressing (@A) JMP @A (This instruction causes an unconditional branch by accumulator indirect branch addressing.) Before execution PC 3 C 2 0 A 6677 After execution PC 3 B 2 0 A 6677 PCB 4 F 3B20 Memory space 4F3B20H Next instruction 4F3C20H 61 JMP @A PCB 4 F 3B20 ● Indirect specification branch addressing (@ear) The address of the branch destination is the word data at the address indicated by ear. Figure B.4-12 Example of Indirect Specification Branch Addressing (@ear) JMP @@RW0 (This instruction causes an unconditional branch by register indirect addressing.) Before execution After execution PC 3 C 2 0 PCB 4 F RW0 7 F 4 8 DTB 2 1 PC 3 B 2 0 RW0 7 F 4 8 PCB 4 F Memory space 217F48H 20 217F49H 3B 4F3B20H Next instruction 4F3C20H 73 4F3C21H 08 JMP @@RW0 DTB 2 1 435 APPENDIX B Instructions ● Indirect specification branch addressing (@eam) The address of the branch destination is the word data at the address indicated by eam. Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam) JMP @RW0 (This instruction causes an unconditional branch by register indirect addressing.) Before execution PC 3 C 2 0 PCB 4 F RW0 3 B 2 0 After execution PC 3 B 2 0 RW0 3 B 2 0 436 PCB 4 F Memory space 4F3B20H Next instruction 4F3C20H 73 4F3C21H 00 JMP @RW0 APPENDIX B Instructions B.5 Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. ■ Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments. Therefore, intervening in data access increases the execution cycle count. Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the program fetches every byte of an instruction being executed. Therefore, intervening in data access increases the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register, internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register. Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add the "access count x cycle count for the halt" as a correction value to the normal execution count. 437 APPENDIX B Instructions ■ Calculating the Execution Cycle Count Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value data. Table B.5-1 Execution Cycle Counts in Each Addressing Mode (a) * Code Operand 00 | 07 Ri Rwi RLi 08 | 0B Execution cycle count in each addressing mode Register access count in each addressing mode See the instruction list. See the instruction list. @RWj 2 1 0C | 0F @RWj+ 4 2 10 | 17 @RWi+disp8 2 1 18 | 1B @RWi+disp16 2 1 1C 1D 1E 1F @RW0+RW7 @RW1+RW7 @PC+disp16 addr16 4 4 2 1 2 2 0 0 *: (a) is used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction List". 438 APPENDIX B Instructions Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles (b) byte * Operand (c) word * (d) long * Cycle count Access count Cycle count Access count Cycle count Access count Internal register +0 1 +0 1 +0 2 Internal memory Even address +0 1 +0 1 +0 2 Internal memory Odd address +0 1 +2 2 +4 4 External data bus 16-bit even address +1 1 +1 1 +2 2 External data bus 16-bit odd address +1 1 +4 2 +8 4 External data bus 8-bits +1 1 +4 2 +8 4 *: (b), (c), and (d) are used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction List". Note: When an external data bus is used, the cycle counts during which an instruction is made to wait by ready input or automatic ready must also be added. Table B.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles Instruction Byte boundary Word boundary Internal memory - +2 External data bus 16-bits - +3 External data bus 8-bits +3 - Notes: • When an external data bus is used, the cycle counts during which an instruction is made to wait by ready input or automatic ready must also be added. • Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the correction values to calculate the worst case. 439 APPENDIX B Instructions B.6 Effective Address Field Table B.6-1 shows the effective address field. ■ Effective Address Field Table B.6-1 Effective Address Field Code Representation 00 R0 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R1 RW1 R2 RW2 R3 RW3 R4 RW4 R5 RW5 R6 RW6 R7 RW7 @RW0 @RW1 @RW2 @RW3 @RW0+ @RW1+ @RW2+ @RW3+ @RW0+disp8 @RW1+disp8 @RW2+disp8 @RW3+disp8 @RW4+disp8 @RW5+disp8 @RW6+disp8 @RW7+disp8 @RW0+disp16 @RW1+disp16 @RW2+disp16 @RW3+disp16 @RW0+RW7 @RW1+RW7 @PC+disp16 addr16 RW0 Address format Byte count of extended address part * Register direct: Individual parts correspond to the byte, word, and long word types in order from the left. - Register indirect 0 Register indirect with post increment 0 Register indirect with 8-bit displacement 1 Register indirect with 16-bit displacement 2 Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address 0 0 2 2 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) * : Each byte count of the extended address part applies to + in the # (byte count) column in "B.8 F2MC-16LX Instruction List". 440 APPENDIX B Instructions B.7 How to Read the Instruction List Table B.7-1 describes the items used in the F2MC-16LX Instruction List, and Table B.7-2 describes the symbols used in the same list. ■ Description of Instruction Presentation Items and Symbols Table B.7-1 Description of Items in the Instruction List (1/2) Item Mnemonic Description Uppercase, symbol: Represented as is in the assembler. Lowercase: Rewritten in the assembler. Number of following lowercase: Indicates bit length in the instruction. # Indicates the number of bytes. ~ Indicates the number of cycles. See Table B.2-1 for the alphabetical letters in items. RG B Operation Indicates the number of times a register access is performed during instruction execution. The number is used to calculate the correction value for CPU intermittent operation. Indicates the correction value used to calculate the actual number of cycles during instruction execution. The actual number of cycles during instruction execution can be determined by adding the value in the ~ column to this value. Indicates the instruction operation. LH Indicates the special operation for bit15 to bit08 of the accumulator. Z: Transfers 0. X: Transfers after sign extension. -: No transfer AH Indicates the special operation for the 16 high-order bits of the accumulator. *: Transfers from AL to AH. -: No transfer Z: Transfers 00 to AH. X: Transfers 00H or FFH to AH after AL sign extension. I S T N Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), C (carry). *: Changes upon instruction execution. -: No change Z: Set upon instruction execution. X: Reset upon instruction execution. Z V C 441 APPENDIX B Instructions Table B.7-1 Description of Items in the Instruction List (2/2) Item Description RMW Indicates whether the instruction is a Read Modify Write instruction (reading data from memory by the I instruction and writing the result to memory). *: Read Modify Write instruction -: Not Read Modify Write instruction Note: Cannot be used for an address that has different meanings between read and write operations. Table B.7-2 Explanation on Symbols in the Instruction List (1/2) Symbol A The bit length used varies depending on the 32-bit accumulator instruction. Byte: Low-order 8 bits of byte AL Word: 16 bits of word AL Long word: 32 bits of AL and AH AH 16 high-order bits of A AL 16 low-order bits of A SP Stack pointer (USP or SSP) PC Program counter PCB Program bank register DTB Data bank register ADB Additional data bank register SSB System stack bank register USB User stack bank register SPB Current stack bank register (SSB or USB) DPR Direct page register brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB brg2 DTB, ADB, SSB, USB, DPR, SPB Ri R0, R1, R2, R3, R4, R5, R6, R7 RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RWj RW0, RW1, RW2, RW3 RLi RL0, RL1, RL2, RL3 dir Abbreviated direct addressing addr16 Direct addressing addr24 Physical direct addressing ad24 0-15 442 Explanation Bit0 to bit15 of addr24 APPENDIX B Instructions Table B.7-2 Explanation on Symbols in the Instruction List (2/2) Symbol ad24 16-23 io Explanation Bit16 to bit23 of addr24 I/O area (000000H to 0000FFH) #imm4 4-bit immediate data #imm8 8-bit immediate data #imm16 16-bit immediate data #imm32 32-bit immediate data ext (imm8) 16-bit data obtained by sign extension of 8-bit immediate data disp8 8-bit displacement disp16 16-bit displacement bp Bit offset vct4 Vector number (0 to 15) vct8 Vector number (0 to 255) ( )b Bit address rel PC relative branch ear Effective addressing (code 00 to 07) eam Effective addressing (code 08 to 1F) rlst Register list 443 APPENDIX B Instructions B.8 F2MC-16LX Instruction List Table B.8-1 to Table B.8-18 list the instructions used by the F2MC-16LX. ■ F2MC-16LX Instruction List Table B.8-1 41 Transfer Instructions (Byte) Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV XCH XCH XCH XCH A,dir A,addr16 A,Ri A,ear A,eam A,io A,#imm8 A,@A A,@RLi+disp8 A,#imm4 A,dir A,addr16 A,Ri A,ear A,eam A,io A,#imm8 A,@A A,@RWi+disp8 A,@RLi+disp8 dir,A addr16,A Ri,A ear,A eam,A io,A @RLi+disp8,A Ri,ear Ri,eam ear,Ri eam,Ri Ri,#imm8 io,#imm8 dir,#imm8 ear,#imm8 eam,#imm8 @AL,AH A,ear A,eam Ri,ear Ri,eam # ~ RG B 2 3 1 2 2+ 2 2 2 3 1 2 3 2 2 2+ 2 2 2 2 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+ 3 4 2 2 3 + (a) 3 2 3 10 1 3 4 2 2 3 + (a) 3 2 3 5 10 3 4 2 2 3 + (a) 3 10 3 4 + (a) 4 5 + (a) 2 5 5 2 4 + (a) 3 4 5 + (a) 7 9 + (a) 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2 x (b) 0 2 x (b) Operation byte (A) ← (dir) byte (A) ← (addr16) byte (A) ← (Ri) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← (io) byte (A) ← imm8 byte (A) ← ((A)) byte (A) ← ((RLi)+disp8) byte (A) ← imm4 byte (A) ← (dir) byte (A) ← (addr16) byte (A) ← (Ri) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← (io) byte (A) ← imm8 byte (A) ← ((A)) byte (A) ← ((RWi)+disp8) byte (A) ← ((RLi)+disp8 byte (dir) ← (A) byte (addr16) ← (A) byte (Ri) ← (A) byte (ear) ← (A) byte (eam) ← (A) byte (io) ← (A) byte ((RLi)+disp8) ← (A) byte (Ri) ← (ear) byte (Ri) ← (eam) byte (ear) ← (Ri) byte (eam) ← (Ri) byte (Ri) ← imm8 byte (io) ← imm8 byte (dir) ← imm8 byte (ear) ← imm8 byte (eam) ← imm8 byte ((A)) ← (AH) byte (A) ↔ (ear) byte (A) ↔ (eam) byte (Ri) ↔ (ear) byte (Ri) ↔ (eam) LH AH I S T N Z V C RMW Z Z Z Z Z Z Z Z Z Z X X X X X X X X X X Z Z - * * * * * * * * * * * * * * * * * * - - - * * * * * * * * * R - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - * * * * * * * * * * * * * * * * * * * * * * * * - - - - Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 444 APPENDIX B Instructions Table B.8-2 38 Transfer Instructions (Word, Long Word) Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW XCHW XCHW XCHW XCHW MOVL MOVL MOVL MOVL MOVL A,dir A,addr16 A,SP A,RWi A,ear A,eam A,io A,@A A,#imm16 A,@RWi+disp8 A,@RLi+disp8 dir,A addr16,A SP,A RWi,A ear,A eam,A io,A @RWi+disp8,A @RLi+disp8,A RWi,ear ear,Rwi eam,Rwi RWi,#imm16 io,#imm16 ear,#imm16 eam,#imm16 @AL,AH A,ear A,eam RWi, ear RWi, eam A,ear A,eam A,#imm32 ear,A eam,A # ~ RG B 2 3 3 1 2 2+ 2 2 3 2 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 2 2+ 5 2 2+ 3 4 1 2 2 3 + (a) 3 3 2 5 10 3 4 1 2 2 3 + (a) 3 5 10 3 4 + (a) 4 5 + (a) 2 5 2 4 + (a) 3 4 5 + (a) 7 9 + (a) 4 5 + (a) 3 4 5 + (a) 0 0 0 1 1 0 0 0 2 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 2 0 0 2 0 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) 0 2 x (c) 0 2 x (c) 0 (d) 0 0 (d) Operation word (A) ← (dir) word (A) ← (addr16) word (A) ← (SP) word (A) ← (RWi) word (A) ← (ear) word (A) ← (eam) word (A) ← (io) word (A) ← ((A)) word (A) ← imm16 word (A) ← ((RWi)+disp8) word (A) ← ((RLi)+disp8) word (dir) ← (A) word (addr16) ← (A) word (SP) ← (A) word (RWi) ← (A) word (ear) ← (A) word (eam) ← (A) word (io) ← (A) word ((RWi)+disp8) ← (A) word ((RLi)+disp8) ← (A) word (RWi) ← (ear) word (RWi) ← (eam) word (ear) ← (RWi) word (eam) ← (RWi) word (RWi) ← imm16 word (io) ← imm16 word (ear) ← imm16 word (eam) ← imm16 word ((A)) ← (AH) word (A) ↔ (ear) word (A) ↔ (eam) word (RWi) ↔ (ear) word (RWi) ↔ (eam) long (A) ← (ear) long (A) ← (eam) long (A) ← imm32 long (ear1) ← (A) long(eam1) ← (A) LH AH I S T N Z V C RMW - * * * * * * * * * * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 445 APPENDIX B Instructions Table B.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word) Mnemonic # ~ RG B ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam A 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4 + (a) 3 5 + (a) 2 3 4 + (a) 3 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2 x (b) 0 0 (b) 0 SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam A 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4 + (a) 3 5 + (a) 2 3 4 + (a) 3 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2 x (b) 0 0 (b) 0 ADDW ADDW ADDW ADDW ADDW ADDW ADDCW ADDCW SUBW SUBW SUBW SUBW SUBW SUBW SUBCW SUBCW ADDL ADDL ADDL SUBL SUBL SUBL A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam A,ear A,eam A,#imm32 A,ear A,eam A,#imm32 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 2+ 5 2 2+ 5 2 3 4+(a) 2 3 5+(a) 3 4+(a) 2 3 4+(a) 2 3 5+(a) 3 4+(a) 6 7+(a) 4 6 7+(a) 4 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 2 0 0 2 0 0 0 0 (c) 0 0 2 x (c) 0 (c) 0 0 (c) 0 0 2 x (c) 0 (c) 0 (d) 0 0 (d) 0 Operation byte (A) ← (A) + imm8 byte (A) ← (A) + (dir) byte (A) ← (A) + (ear) byte (A) ← (A) + (eam) byte (ear) ← (ear) + (A) byte (eam) ← (eam) + (A) byte (A) ← (AH) + (AL) + (C) byte (A) ← (A) + (ear)+ (C) byte (A) ← (A) + (eam)+ (C) byte (A) ← (AH) + (AL) + (C) (decimal) byte (A) ← (A) - imm8 byte (A) ← (A) - (dir) byte (A) ← (A) - (ear) byte (A) ← (A) - (eam) byte (ear) ← (ear) - (A) byte (eam) ← (eam) - (A) byte (A) ← (AH) - (AL) - (C) byte (A) ← (A) - (ear) - (C) byte (A) ← (A) - (eam) - (C) byte (A) ← (AH) - (AL) - (C) (decimal) word (A) ← (AH) + (AL) word (A) ← (A) + (ear) word (A) ← (A) + (eam) word (A) ← (A) + imm16 word (ear) ← (ear) + (A) word (eam) ← (eam) + (A) word (A) ← (A) + (ear) + (C) word (A) ← (A) + (eam) + (C) word (A) ← (AH) - (AL) word (A) ← (A) - (ear) word (A) ← (A) - (eam) word (A) ← (A) - imm16 word (ear) ← (ear) - (A) word (eam) ← (eam) - (A) word (A) ← (A) - (ear) - (C) word (A) ← (A) - (eam) - (C) long (A) ← (A) + (ear) long (A) ← (A) + (eam) long (A) ← (A) + imm32 long (A) ← (A) - (ear) long (A) ← (A) - (eam) long (A) ← (A) - imm32 LH AH I S T N Z V C RMW Z Z Z Z Z Z Z Z Z - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - Z Z Z Z Z Z Z Z - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 446 APPENDIX B Instructions Table B.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word) # ~ RG B INC Mnemonic ear 2 3 2 0 INC eam 2+ 5+(a) 0 2 x (b) DEC ear 2 3 2 0 DEC eam 2+ 5+(a) 0 2 x (b) INCW ear 2 3 2 0 INCW eam 2+ 5+(a) 0 2 x (c) DECW ear 2 3 2 0 DECW eam 2+ 5+(a) 0 2 x (c) INCL ear 2 7 4 0 INCL eam 2+ 9+(a) 0 2 x (d) DECL ear 2 7 4 0 DECL eam 2+ 9+(a) 0 2 x (d) LH AH I S T N Z V C byte (ear) ← (ear) + 1 Operation - - - - - * * * - RMW - byte (eam) ← (eam) + 1 - - - - - * * * - * byte (ear) ← (ear) - 1 - - - - - * * * - - byte (eam) ← (eam) - 1 - - - - - * * * - * word (ear) ← (ear) + 1 - - - - - * * * - - word (eam) ← (eam) + 1 - - - - - * * * - * word (ear) ← (ear) - 1 - - - - - * * * - - word (eam) ← (eam) - 1 - - - - - * * * - * long (ear) ← (ear) + 1 - - - - - * * * - - long (eam) ← (eam) + 1 - - - - - * * * - * long (ear) ← (ear) - 1 - - - - - * * * - - long (eam) ← (eam) - 1 - - - - - * * * - * Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. Table B.8-5 11 Compare Instructions (Byte, Word, Long Word) Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW CMP A 1 1 0 0 byte (AH) - (AL) - - - - - * * * * - CMP A,ear 2 2 1 0 byte (A) - (ear) - - - - - * * * * - CMP A,eam 2+ 3+(a) 0 (b) byte (A) - (eam) - - - - - * * * * - CMP A,#imm8 2 2 0 0 byte (A) - imm8 - - - - - * * * * - CMPW A 1 1 0 0 word (AH) - (AL) - - - - - * * * * - CMPW A,ear 2 2 1 0 word (A) - (ear) - - - - - * * * * - CMPW A,eam 2+ 3+(a) 0 (c) word (A) - (eam) - - - - - * * * * - CMPW A,#imm16 3 2 0 0 word (A) - imm16 - - - - - * * * * - CMPL A,ear 2 6 2 0 long (A) - (ear) - - - - - * * * * - CMPL A,eam 2+ 7+(a) 0 (d) long (A) - (eam) - - - - - * * * * - CMPL A,#imm32 5 3 0 0 long (A) - imm32 - - - - - * * * * - Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 447 APPENDIX B Instructions Table B.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word) # ~ RG B LH AH I S T N Z V C RMW DIVU Mnemonic A 1 *1 0 0 word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) Operation - - - - - - - * * - DIVU A,ear 2 *2 1 0 word (A) / byte (ear) quotient → byte (A) remainder → byte (ear) - - - - - - - * * - DIVU A,eam 2+ *3 0 *6 word (A) / byte (eam) quotient → byte (A) remainder → byte (eam) - - - - - - - * * - DIVUW A,ear 2 *4 1 0 long (A) / word (ear) quotient → word (A) remainder → word (ear) - - - - - - - * * - DIVUW A,eam 2+ *5 0 *7 long (A) / word (eam) quotient → word (A) remainder → word (eam) - - - - - - - * * - MULL A 1 *8 0 0 byte (AH) * byte (AL) → word (A) - - - - - - - - - - MULL A,ear 2 *9 1 0 byte (A) * byte (ear) → word (A) - - - - - - - - - - MULL A,eam 2+ *10 0 (b) byte (A) * byte (eam) → word (A) - - - - - - - - - - MULEY A 1 *11 0 0 word (AH) * word (AL) → Long (A) - - - - - - - - - - MULEY A,ear 2 *12 1 0 word (A) * word (ear) → Long (A) - - - - - - - - - - MULEY A,eam 2+ *13 0 (c) word (A) * word (eam) → Long (A) - - - - - - - - - - *1: 3: Division by 0 7: Overflow 15: Normal *2: 4: Division by 0 8: Overflow 16: Normal *3: 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal *4: 4: Division by 0 7: Overflow 22: Normal *5: 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal *6: (b): Division by 0 or overflow 2 x (b): Normal *7: (c): Division by 0 or overflow 2 x (c): Normal *8: 3: Byte (AH) is 0. 7: Byte (AH) is not 0. *9: 4: Byte (ear) is 0. 8: Byte (ear) is not 0. *10: 5+(a): Byte (eam) is 0, 9+(a): Byte (eam) is not 0. *11: 3: Word (AH) is 0. 11: Word (AH) is not 0. *12: 4: Word (ear) is 0. 12: Word (ear) is not 0. *13: 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0. Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 448 APPENDIX B Instructions Table B.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word) # ~ RG B LH AH I S T N Z V C RMW DIV Mnemonic A 2 *1 0 0 word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) Operation Z - - - - - - * * - DIV A,ear 2 *2 1 0 word (A) / byte (ear) quotient → byte (A) remainder → byte (ear) Z - - - - - - * * - DIV A,eam 2+ *3 0 *6 word (A) / byte (eam) quotient → byte (A) remainder → byte (eam) Z - - - - - - * * - DIVW A,ear 2 *4 1 0 long (A) / word (ear) quotient → word (A) remainder → word (ear) - - - - - - - * * - DIVW A,eam 2+ *5 0 *7 long (A) / word (eam) quotient → word (A) remainder → word (eam) - - - - - - - * * - MUL A 2 *8 0 0 byte (AH) * byte (AL) → word (A) - - - - - - - - - - MUL A,ear 2 *9 1 0 byte (A) * byte (ear) → word (A) - - - - - - - - - - MUL A,eam 2+ *10 0 (b) byte (A) * byte (eam) → word (A) - - - - - - - - - - MULW A 2 *11 0 0 word (AH) * word (AL) → Long (A) - - - - - - - - - - MULW A,ear 2 *12 1 0 word (A) * word (ear) → Long (A) - - - - - - - - - - MULW A,eam 2+ *13 0 (c) word (A) * word (eam) → Long (A) - - - - - - - - - - *1: *2: *3: *4: 3: Division by 0, 8 or 18: Overflow, 18: Normal 4: Division by 0, 11 or 22: Overflow, 23: Normal 5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal When dividend is positive; 4: Division by 0, 12 or 30: Overflow, 31: Normal When dividend is negative; 4: Division by 0, 12 or 31: Overflow, 32: Normal *5: When dividend is positive; 5+(a): Division by 0, 12+(a) or 31+(a): Overflow, 32+(a): Normal When dividend is negative; 5+(a): Division by 0, 12+(a) or 32+(a): Overflow, 33+(a): Normal *6: (b): Division by 0 or overflow, 2 x (b): Normal *7: (c): Division by 0 or overflow, 2 x (c): Normal *8: 3: Byte (AH) is 0, 12: result is positive, 13: result is negative *9: 4: Byte (ear) is 0, 13: result is positive, 14: result is negative *10: 5+(a): Byte (eam) is 0, 14+(a): result is positive, 15+(a): result is negative *11: 3: Word (AH) is 0, 16: result is positive, 19: result is negative *12: 4: Word (ear) is 0, 17: result is positive, 20: result is negative *13: 5+(a): Word (eam) is 0, 18+(a): result is positive, 21+(a): result is negative Notes: • The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may be a pre-operation count or a post-operation count depending on the detection timing. • When an overflow occurs with DIV or DIVW instruction, the contents of the AL are destroyed. • See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 449 APPENDIX B Instructions Table B.8-8 39 Logic 1 Instructions (Byte, Word) Mnemonic # ~ RG B Operation LH AH I S T N Z V C AND A,#imm8 2 2 0 0 byte (A) ← (A) and imm8 - - - - - * * R - RMW - AND A,ear 2 3 1 0 byte (A) ← (A) and (ear) - - - - - * * R - - AND A,eam 2+ 4+(a) 0 (b) byte (A) ← (A) and (eam) - - - - - * * R - AND ear,A 2 3 2 0 byte (ear) ← (ear) and (A) - - - - - * * R - - AND eam,A 2+ 5+(a) 0 2 x (b) byte (eam) ← (eam) and (A) - - - - - * * R - * OR A,#imm8 2 2 0 0 byte (A) ← (A) or imm8 - - - - - * * R - - OR A,ear 2 3 1 0 byte (A) ← (A) or (ear) - - - - - * * R - - OR A,eam 2+ 4+(a) 0 (b) byte (A) ← (A) or (eam) - - - - - * * R - - OR ear,A 2 3 2 0 byte (ear) ← (ear) or (A) - - - - - * * R - - OR eam,A 2+ 5+(a) 0 2 x (b) byte (eam) ← (eam) or (A) - - - - - * * R - * XOR A,#imm8 2 2 0 0 byte (A) ← (A) xor imm8 - - - - - * * R - - XOR A,ear 2 3 1 0 byte (A) ← (A) xor (ear) - - - - - * * R - - XOR A,eam 2+ 4+(a) 0 (b) byte (A) ← (A) xor (eam) - - - - - * * R - - XOR ear,A 2 3 2 0 byte (ear) ← (ear) xor (A) - - - - - * * R - - XOR eam,A 2+ 5+(a) 0 2 x (b) byte (eam) ← (eam) xor (A) - - - - - * * R - * NOT A 1 2 0 0 byte (A) ← not (A) - - - - - * * R - - NOT ear 2 3 2 0 byte (ear) ← not (ear) - - - - - * * R - - NOT eam 2+ 5+(a) 0 2 x (b) byte (eam) ← not (eam) - - - - - * * R - * ANDW A 1 2 0 0 word (A) ← (AH) and (A) - - - - - * * R - - ANDW A,#imm16 3 2 0 0 word (A) ← (A) and imm16 - - - - - * * R - - ANDW A,ear 2 3 1 0 word (A) ← (A) and (ear) - - - - - * * R - - ANDW A,eam 2+ 4+(a) 0 (c) word (A) ← (A) and (eam) - - - - - * * R - - ANDW ear,A 2 3 2 0 word (ear) ← (ear) and (A) - - - - - * * R - - ANDW eam,A 2+ 5+(a) 0 2 x (c) word (eam) ← (eam) and (A) - - - - - * * R - * ORW A 1 2 0 0 word (A) ← (AH) or (A) - - - - - * * R - - ORW A,#imm16 3 2 0 0 word (A) ← (A) or imm16 - - - - - * * R - - ORW A,ear 2 3 1 0 word (A) ← (A) or (ear) - - - - - * * R - - ORW A,eam 2+ 4+(a) 0 (c) word (A) ← (A) or (eam) - - - - - * * R - - ORW ear,A 2 3 2 0 word (ear) ← (ear) or (A) - - - - - * * R - - ORW eam,A 2+ 5+(a) 0 2 x (c) word (eam) ← (eam) or (A) - - - - - * * R - * XORW A 1 2 0 0 word (A) ← (AH) xor (A) - - - - - * * R - - XORW A,#imm16 3 2 0 0 word (A) ← (A) xor imm16 - - - - - * * R - - XORW A,ear 2 3 1 0 word (A) ← (A) xor (ear) - - - - - * * R - - XORW A,eam 2+ 4+(a) 0 (c) word (A) ← (A) xor (eam) - - - - - * * R - - XORW ear,A 2 3 2 0 word (ear) ← (ear) xor (A) - - - - - * * R - - XORW eam,A 2+ 5+(a) 0 2 x (c) word (eam) ← (eam) xor (A) - - - - - * * R - * NOTW A 1 2 0 0 word (A) ← not (A) - - - - - * * R - - NOTW ear 2 3 2 0 word (ear) ← not (ear) - - - - - * * R - - NOTW eam 2+ 5+(a) 0 2 x (c) word (eam) ← not (eam) - - - - - * * R - * Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 450 APPENDIX B Instructions Table B.8-9 6 Logic 2 Instructions (Long Word) Mnemonic # ~ RG B LH AH I S T N Z V C RMW ANDL A,ear 2 6 2 0 long (A) ← (A) and (ear) Operation - - - - - * * R - - ANDL A,eam 2+ 7+(a) 0 (d) long (A) ← (A) and (eam) - - - - - * * R - - ORL A,ear 2 6 2 0 long (A) ← (A) or (ear) - - - - - * * R - - ORL A,eam 2+ 7+(a) 0 (d) long (A) ← (A) or (eam) - - - - - * * R - - XORL A,ear 2 6 2 0 long (A) ← (A) xor (ear) - - - - - * * R - - XORL A,eam 2+ 7+(a) 0 (d) long (A) ← (A) xor (eam) - - - - - * * R - - Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. Table B.8-10 6 Sign Inversion Instructions (Byte, Word) Mnemonic NEG A # ~ RG B 1 2 0 0 byte (A) ← 0 - (A) Operation LH AH I S T N Z V C RMW X - - - - * * * * - byte (ear) ← 0 - (ear) - - - - byte (eam) ← 0 - (eam) - - - - - * * * * - - * * * * * - - - - - * * * * - NEG ear 2 3 2 0 NEG eam 2+ 5+(a) 0 2 x (b) NEGW A 1 2 0 0 word (A) ← 0 - (A) word (ear) ← 0 - (ear) - - - - - * * * * - word (eam) ← 0 - (eam) - - - - - * * * * * NEGW ear 2 3 2 0 NEGW eam 2+ 5+(a) 0 2 x (c) Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. Table B.8-11 1 Normalization Instruction (Long Word) Mnemonic NRML A,R0 # ~ RG B 2 *1 1 0 Operation long (A) ← Shifts to the position where '1' is set for the first time. byte (RD) ← Shift count at that time LH AH I S T N Z V C RMW - - - - - - * - - - *1: 4 when all accumulators have a value of 0; otherwise, 6+(R0) 451 APPENDIX B Instructions Table B.8-12 18 Shift Instructions (Byte, Word, Long Word) # ~ RG B LH AH I S T N Z V C RMW RORC Mnemonic A 2 2 0 0 byte (A) ← With right rotation carry Operation - - - - - * * - * - ROLC A 2 2 0 0 byte (A) ← With left rotation carry - - - - - * * - * - RORC ear 2 3 2 0 byte (ear) ← With right rotation carry - - - - - * * - * - RORC eam 2+ 5+(a) 0 2 x (b) byte (eam) ← With right rotation carry - - - - - * * - * * ROLC ear 2 3 2 0 byte (ear) ← With left rotation carry - - - - - * * - * - ROLC eam 2+ 5+(a) 0 2 x (b) byte (eam) ← With left rotation carry - - - - - * * - * * ASR A,R0 2 *1 1 0 byte (A) ← Arithmetic right shift (A, 1 bit) - - - - - * * - * - LSR A,R0 2 *1 1 0 byte (A) ← Logical right barrel shift (A, R0) - - - - - * * - * - LSL A,R0 2 *1 1 0 byte (A) ← Logical left barrel shift (A, R0) - - - - - * * - * - ASRW A 1 2 0 0 word (A) ← Arithmetic right shift (A, 1 bit) - - - - * * * - * - LSRW A/SHRW A 1 2 0 0 word (A) ← Logical right shift (A, 1 bit) - - - - * R * - * - LSLW A/SHLW A 1 2 0 0 word (A) ← Logical left shift (A, 1 bit) - - - - - * * - * - ASRW A,R0 2 *1 1 0 word (A) ← Arithmetic right barrel shift (A, R0) - - - - * * * - * LSRW A,R0 2 *1 1 0 word (A) ← Logical right barrel shift (A, R0) - - - - * * * - * - LSLW A,R0 2 *1 1 0 word (A) ← Logical left barrel shift (A, R0) - - - - - * * - * - ASRL A,R0 2 *2 1 0 long (A) ← Arithmetic right barrel shift (A, R0) - - - - * * * - * LSRL A,R0 2 *2 1 0 long (A) ← Logical right barrel shift (A, R0) - - - - * * * - * - LSLL A,R0 2 *2 1 0 long (A) ← Logical left barrel shift (A, R0) - - - - - * * - * - *1: 6 when R0 is 0; otherwise, 5 + (R0) *2: 6 when R0 is 0; otherwise, 6 + (R0) Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 452 APPENDIX B Instructions Table B.8-13 31 Branch 1 Instructions # ~ RG B LH AH I S T N Z V C BZ/BEQ Mnemonic rel 2 *1 0 0 Branch on (Z) = 1 Operation - - - - - - - - - RMW - BNZ/ BNE rel 2 *1 0 0 Branch on (Z) = 0 - - - - - - - - - - BC/BLO rel 2 *1 0 0 Branch on (C) = 1 - - - - - - - - - - BNC/ BHS rel 2 *1 0 0 Branch on (C) = 0 - - - - - - - - - - BN rel 2 *1 0 0 Branch on (N) = 1 - - - - - - - - - - BP rel 2 *1 0 0 Branch on (N) = 0 - - - - - - - - - - BV rel 2 *1 0 0 Branch on (V) = 1 - - - - - - - - - - BNV rel 2 *1 0 0 Branch on (V) = 0 - - - - - - - - - - BT rel 2 *1 0 0 Branch on (T) = 1 - - - - - - - - - - BNT rel 2 *1 0 0 Branch on (T) = 0 - - - - - - - - - - BLT rel 2 *1 0 0 Branch on (V) nor (N) = 1 - - - - - - - - - - BGE rel 2 *1 0 0 Branch on (V) nor (N) = 0 - - - - - - - - - - BLE rel 2 *1 0 0 Branch on ((V) xor (N)) or (Z) = 1 - - - - - - - - - - BGT rel 2 *1 0 0 Branch on ((V) xor (N)) or (Z) = 0 - - - - - - - - - - BLS rel 2 *1 0 0 Branch on (C) or (Z) = 1 - - - - - - - - - - BHI rel 2 *1 0 0 Branch on (C) or (Z) = 0 - - - - - - - - - - BRA rel 2 *1 0 0 Unconditional branch - - - - - - - - - - JMP @A 1 2 0 0 word (PC) ← (A) - - - - - - - - - - JMP addr16 3 3 0 0 word (PC) ← addr16 - - - - - - - - - - JMP @ear 2 3 1 0 word (PC) ← (ear) - - - - - - - - - - JMP @eam 2+ 4+(a) 0 (c) word (PC) ← (eam) - - - - - - - - - - JMPP @ear *3 2 5 2 0 word (PC) ← (ear), (PCB) ← (ear+2) - - - - - - - - - - JMPP @eam *3 2+ 6+(a) 0 (d) word (PC) ← (eam), (PCB) ← (eam+2) - - - - - - - - - - JMPP addr24 4 4 0 0 word (PC) ← ad24 0-15, (PCB) ← ad24 16-23 - - - - - - - - - - CALL @ear *4 2 6 1 (c) word (PC) ← (ear) - - - - - - - - - - CALL addr16 *5 2+ 7+(a) 0 2 x (c) word (PC) ← (eam) - - - - - - - - - - CALL @eam *4 3 6 0 (c) word (PC) ← addr16 - - - - - - - - - - CALLV #vct4 *5 1 7 0 2 x (c) Vector call instruction - - - - - - - - - - CALLP @ear *6 2 10 2 2 x (c) word (PC) ← (ear)0-15, (PCB) ← (ear)16-23 - - - - - - - - - - CALLP @eam *6 2+ 11+(a) 0 *2 word (PC) ← (eam)0-15, (PCB) ← (eam)16-23 - - - - - - - - - - CALLP addr24 *7 4 10 0 2 x (c) word (PC) ← addr0-15, (PCB) ← addr16-23 - - - - - - - - - - *1: 4 when a branch is made; otherwise, 3 *2: 3 x (c) + (b) *3: Read (word) of branch destination address *4: W: Save to stack (word) R: Read (word) of branch destination address *5: Save to stack (word) *6: W: Save to stack (long word), R: Read (long word) of branch destination address *7: Save to stack (long word) Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 453 APPENDIX B Instructions Table B.8-14 19 Branch 2 Instructions Mnemonic # ~ RG B LH AH I S T N Z V C CBNE A,#imm8,rel 3 *1 0 0 Branch on byte (A) not equal to imm8 - - - - - * * * * CWBNE A,#imm16,rel 4 *1 0 0 Branch on word (A) not equal to imm16 - - - - - * * * * - CBNE ear,#imm8,rel 4 *2 1 0 Branch on byte (ear) not equal to imm8 - - - - - * * * * - CBNE eam,#imm8,rel *9 4+ *3 0 (b) Branch on byte (eam) not equal to imm8 - - - - - * * * * - CWBNE ear,#imm16,rel 5 *4 1 0 Branch on word (ear) not equal to imm16 - - - - - * * * * - CWBNE eam,#imm16,rel*9 5+ *3 0 (c) Branch on word (eam) not equal to imm16 - - - - - * * * * - DBNZ ear,rel 3 *5 2 0 Branch on byte (ear) = (ear) - 1, (ear) not equal to 0 - - - - - * * * - - DBNZ eam,rel 3+ *6 2 - - - - - * * * - * DWBNZ ear,rel 3 *5 2 - - - - - * * * - - DWBNZ eam,rel 3+ *6 2 2 x (c) Branch on word (eam) = (eam) - 1, (eam) not equal to 0 - - - - - * * * - * INT #vct8 2 20 0 8 x (c) Software interrupt - - R S - - - - - - INT addr16 3 16 0 6 x (c) Software interrupt - - R S - - - - - - INTP addr24 4 17 0 6 x (c) Software interrupt - - R S - - - - - - INT9 1 20 0 8 x (c) Software interrupt - - R S - - - - - - RETI 1 *8 0 *7 Return from interrupt - - * * * * * * * - 2 6 0 (c) Saves the old frame pointer in the stack upon entering the function, then sets the new frame pointer and reserves the local pointer area. - - - - - - - - - - 1 5 0 (c) Recovers the old frame pointer from the stack upon exiting the function. - - - - - - - - - - LINK #imm8 UNLINK Operation 2 x (b) Branch on byte (eam) = (eam) - 1, (eam) not equal to 0 0 Branch on word (ear) = (ear) - 1, (ear) not equal to 0 RMW - RET *10 1 4 0 (c) Return from subroutine - - - - - - - - - - RETP *11 1 6 0 (d) Return from subroutine - - - - - - - - - - *1: 5 when a branch is made; otherwise, 4 *2: 13 when a branch is made; otherwise, 12 *3: 7+(a) when a branch is made; otherwise, 6+(a) *4: 8 when a branch is made; otherwise, 7 *5: 7 when a branch is made; otherwise, 6 *6: 8+(a) when a branch is made; otherwise, 7+(a) *7: 3 x (b) + 2 x (c) when jumping to the next interruption request; 6 x (c) when returning from the current interruption *8: 15 when jumping to the next interruption request; 17 when returning from the current interruption *9: Do not use RWj+ addressing mode with a CBNE or CWBNE instruction. *10: Return from stack (word) *11: Return from stack (long word) Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 454 APPENDIX B Instructions Table B.8-15 28 Other Control Instructions (Byte, Word, Long Word) # ~ RG B LH AH I S T N Z V C RMW PUSHW Mnemonic A 1 4 0 (c) word (SP) ← (SP) - 2, ((SP)) ← (A) Operation - - - - - - - - - - PUSHW AH 1 4 0 (c) word (SP) ← (SP) - 2, ((SP)) ← (AH) - - - - - - - - - - PUSHW PS 1 4 0 (c) word (SP) ← (SP) - 2, ((SP)) ← (PS) - - - - - - - - - - PUSHW rlst 2 *3 *5 *4 (SP) ← (SP) - 2n, ((SP)) ← (rlst) - - - - - - - - - - POPW A 1 3 0 (c) word (A) ← ((SP)), (SP) ← (SP) + 2 - * - - - - - - - - POPW AH 1 3 0 (c) word (AH) ← ((SP)), (SP) ← (SP) + 2 - - - - - - - - - - POPW PS 1 4 0 (c) word (PS) ← ((SP)), (SP) ← (SP) + 2 - - * * * * * * * - POPW rlst 2 *2 *5 *4 (rlst) ← ((SP)), (SP) ← (SP) - - - - - - - - - - JCTX @A 1 14 0 6 x (c) Context switch instruction - - * * * * * * * - AND CCR,#imm8 2 3 0 0 byte (CCR) ← (CCR) and imm8 - - * * * * * * * - OR CCR,#imm8 2 3 0 0 byte (CCR) ← (CCR) or imm8 - - * * * * * * * - MOV RP,#imm8 2 2 0 0 byte (RP) ← imm8 - - - - - - - - - - MOV ILM,#imm8 2 2 0 0 byte (ILM) ← imm8 - - - - - - - - - - MOVEA RWi,ear 2 3 1 0 word (RWi) ← ear - - - - - - - - - - MOVEA RWi,eam 2+ 2+(a) 1 0 word (RWi) ← eam - - - - - - - - - - MOVEA A,ear 2 1 0 0 word (A) ← ear - * - - - - - - - - MOVEA A,eam 2+ 1+(a) 0 0 word (A) ← eam - * - - - - - - - - ADDSP #imm8 2 3 0 0 word (SP) ← ext(imm8) - - - - - - - - - - ADDSP #imm16 3 3 0 0 word (SP) ← imm16 - - - - - - - - - - MOV A,brg1 2 *1 0 0 byte (A) ← (brg1) Z * - - - * * - - - MOV brg2,A - 2 1 0 0 byte (brg2) ← (A) - - - - - * * - - NOP 1 1 0 0 No operation - - - - - - - - - - ADB 1 1 0 0 Prefix code for AD space access - - - - - - - - - - DTB 1 1 0 0 Prefix code for DT space access - - - - - - - - - PCB 1 1 0 0 Prefix code for PC space access - - - - - - - - - - SPB 1 1 0 0 Prefix code for SP space access - - - - - - - - - - NCC 1 1 0 0 Prefix code for flag no-change - - - - - - - - - - CMR 1 1 0 0 Prefix code for common register bank - - - - - - - - - - *1: PCB, ADB, SSB, USB, SPB: 1, DTB, DPR: 2 *2: 7 + 3 x (POP count) + 2 x (POP last register number), 7 when RLST = 0 (no transfer register) *3: 29 + 3 x (PUSH count) - 3 x (PUSH last register number), 8 when RLST = 0 (no transfer register) *4: (POP count) x (c) or (PUSH count) x (c) *5: (POP count) or (PUSH count) Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 455 APPENDIX B Instructions Table B.8-16 21 Bit Operand Instructions Mnemonic # ~ RG B LH AH I S T N Z V C RMW MOVB A,dir:bp 3 5 0 (b) byte (A) ← (dir:bp)b Operation Z * - - - * * - - - MOVB A,addr16:bp 4 5 0 (b) byte (A) ← (addr16:bp)b Z * - - - * * - - - MOVB A,io:bp 3 4 0 (b) byte (A) ← (io:bp)b Z * - - - * * - - - MOVB dir:bp,A 3 7 0 2 x (b) bit (dir:bp)b ← (A) - - - - - * * - - * MOVB addr16:bp,A 4 7 0 2 x (b) bit (addr16:bp)b ← (A) - - - - - * * - - * MOVB io:bp,A 3 6 0 2 x (b) bit (io:bp)b ← (A) - - - - - * * - - * SETB dir:bp 3 7 0 2 x (b) bit (dir:bp)b ← 1 - - - - - - - - - * SETB addr16:bp 4 7 0 2 x (b) bit (addr16:bp)b ← 1 - - - - - - - - - * SETB io:bp 3 7 0 2 x (b) bit (io:bp)b ← 1 - - - - - - - - - * CLRB dir:bp 3 7 0 2 x (b) bit (dir:bp)b ← 0 - - - - - - - - - * CLRB addr16:bp 4 7 0 2 x (b) bit (addr16:bp)b ← 0 - - - - - - - - - * CLRB io:bp 3 7 0 2 x (b) bit (io:bp)b ← 0 - - - - - - - - - * BBC dir:bp,rel 4 *1 0 (b) Branch on (dir:bp) b = 0 - - - - - - * - - - BBC addr16:bp,rel 5 *1 0 (b) Branch on (addr16:bp) b = 0 - - - - - - * - - - BBC io:bp,rel 4 *2 0 (b) Branch on (io:bp) b = 0 - - - - - - * - - - BBS dir:bp,rel 4 *1 0 (b) Branch on (dir:bp) b = 1 - - - - - - * - - - BBS addr16:bp,rel 5 *1 0 (b) Branch on (addr16:bp) b = 1 - - - - - - * - - - BBS io:bp,rel 4 *1 0 (b) Branch on (io:bp) b = 1 - - - - - - * - - - SBBS addr16:bp,rel 5 *3 0 2 x (b) Branch on (addr16:bp) b = 1, bit = 1 - - - - - - * - - * WBTS io:bp 3 *4 0 *5 Waits until (io:bp) b = 1 - - - - - - - - - - WBTC io:bp 3 *4 0 *5 Waits until (io:bp) b = 0 - - - - - - - - - - *1: 8 when a branch is made; otherwise, 7 *2: 7 when a branch is made; otherwise, 6 *3: 10 when the condition is met; otherwise, 9 *4: Undefined count *5: Until the condition is met Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. Table B.8-17 6 Accumulator Operation Instructions (Byte, Word) Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW - SWAP 1 3 0 0 byte (A)0-7 ↔ (A)8-15 - - - - - - - - - SWAPW 1 2 0 0 word (AH) ↔ (AL) - * - - - - - - - - EXT 1 1 0 0 Byte sign extension X - - - - * * - - - EXTW 1 2 0 0 Word sign extension - X - - - * * - - - ZEXT 1 1 0 0 Byte zero extension Z - - - - R * - - - ZEXTW 1 1 0 0 Word zero extension - Z - - - R * - - - 456 APPENDIX B Instructions Table B.8-18 10 String Instructions # ~ RG B LH AH I S T N Z V C RMW MOVS / MOVSI Mnemonic 2 *2 *5 *3 byte transfer @AH+ ← @AL+, counter = RW0 Operation - - - - - - - - - - MOVSD 2 *2 *5 *3 byte transfer @AH- ← @AL-, counter = RW0 - - - - - - - - - - SCEQ / SCEQI 2 *1 *5 *4 byte search @AH+ ← AL, counter RW0 - - - - - * * * * - SCEQD 2 *1 *5 *4 byte search @AH- ← AL, counter RW0 - - - - - * * * * - FILS / FILSI 2 6m+6 *5 *3 byte fill @AH+ ← AL, counter RW0 - - - - - * * - - - MOVSW / MOVSWI 2 *2 *5 *6 word transfer @AH+ ← @AL+, counter = RW0 - - - - - - - - - - MOVSWD 2 *2 *5 *6 word transfer @AH- ← @AL-, counter = RW0 - - - - - - - - - - SCWEQ / SCWEQI 2 *1 *5 *7 word search @AH+ - AL, counter = RW0 - - - - - * * * * - SCWEQD 2 *1 *5 *7 word search @AH- - AL, counter = RW0 - - - - - * * * * - FILSW / FILSWI 2 6m+6 *5 *6 word fill @AH+ ← AL, counter = RW0 - - - - - * * - - - *1: 5 when RW0 is 0, 4 + 7 x (RW0) when the counter expires, or 7n + 5 when a match occurs *2: 5 when RW0 is 0; otherwise, 4 + 8 x (RW0) *3: (b) x (RW0) + (b) x (RW0) When the source and destination access different areas, calculate the (b) item individually. *4: (b) x n *5: 2 x (RW0) *6: (c) x (RW0) + (c) x (RW0) When the source and destination access different areas, calculate the (c) item individually. *7: (c) x n Note: m: RW0 value (counter value), n: Loop count See Table B.5-1 and Table B.5-2 for information on (b) to (c) in the table. 457 APPENDIX B Instructions B.9 Instruction Map Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F2MC-16LX instruction map. ■ Structure of Instruction Map Figure B.9-1 Structure of Instruction Map Basic page map Bit operation instructions Character string operation instructions 2-byte instructions : Byte 1 ea instructions × 9 : Byte 2 An instruction such as the NOP instruction that ends in one byte is completed within the basic page. An instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it references byte 1, and can check the following one byte by referencing the map for byte 2. Figure B.9-2 shows the correspondence between an actual instruction code and instruction map. 458 APPENDIX B Instructions Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map Some instructions do not contain byte 2. Instruction code Length varies depending on the instruction. Byte 1 Byte 2 Operand Operand ... [Basic page map] XY +Z [Extended page map]* UV +W *: The extended page map is a generic name of maps for bit operation instructions, character string operation instructions, 2-byte instructions, and ea instructions. Actually, there are multiple extended page maps for each type of instructions. An example of an instruction code is shown in Table B.9-1 . Table B.9-1 Example of an Instruction Code Byte 1 (from basic page map) Byte 2 (from extended page map) NOP 00 +0=00 - AND A, #8 30 +4=34 - MOV A, ADB 60 +F=6F 00 +0=00 @RW2+d8, #8rel 70 +0=70 F0 +2=F2 Instruction 459 460 +F +E +D +C +B +A +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 A ZEXT SWAP ADDSP DTB ADB SPB #8 A, #8 dir, A A, dir io, A A, io JMP BRA 60 MULU DIVU ea @A instruction 2 A MOVW MOVX RET SP, A A, addr16 A0 B0 C0 ea instruction 8 D0 E0 rel rel LSRW ASRW LSLW SWAPW ZEXTW XORW ORW ANDW ORW PUSHW POPW A, #16 AH AH MOVW ea, RWi Bit operation MOV A instruction ea, Ri MOVW RWi, ea PUSHW POPW 2-byte XCHW A rlst rlst instruction RWi, ea Character XORW PUSHW POPW XCH operation A A, #16 PS PS string Ri, ea instruction A ANDW PUSHW POPW A A, #16 A CMPW MOVL MOVW RETI A, #16 A, #32 addr16, A ADDSP MULUW NOTW A #16 A A A EXTW A BHI BLS BGT BLE rel rel rel rel rel BGE CMPL CMPW A, #32 NEGW A rel rel rel rel rel rel BLT BT BNV BV BP BN BNC/BHS rel BC/BL0 BNZ/BNE rel BZ/BEQ MOV MOV CBNE A, CWBNE A, MOVW MOVW INTP MOV RP, #8 ILM, #8 #8, rel #16, rel A, #16 A,addr16 addr24 Ri, ea #4 F0 rel ADDW MOVW MOVW INT ea MOVW MOVW MOVW MOV A, MOVW @R A, #16 A, dir A, io #vct8 instruction 9 A, RWi RWi, A RWi, #16 @RWi+d8 Wi+d8, A NOT ea instruction 7 MOVX MOVX CALLP ea A, dir A, io addr24 instruction 6 MOVW MOVW RETP A, #8 A, SP io, #16 A, #8 90 BNT SUBL SUBW A, #32 A A A XOR OR OR CCR, #8 80 ea MOV MOV MOV MOV MOVX A, MOV CALL rel instruction 1 A, Ri Ri, A Ri, #8 A, Ri @RWi+d8 A, #4 70 MOV JMP ea A, addr16 addr16 instruction 3 MOV MOV 50 MOVX MOV JMPP ea A, #8 A, #8 addr16, A adde24 instruction 4 MOV MOV MOV 40 SUBW MOVW MOVW INT MOVEA A A, #16 dir, A io, A addr16 RWi, ea UNLINK A CMP A A, #8 A, #8 SUBC SUB ADD 30 AND AND MOV MOV CALL ea CCR, #8 A, #8 dir, #8 io, #8 addr16 instruction 5 CMP A A, dir A, dir ADDC SUB ADD 20 LINK ADDL ADDW #imm8 A, #32 EXT @A PCB A JCTX SUBDC ADDDC NEG NCC INT9 A CMR 10 NOP 00 APPENDIX B Instructions Table B.9-2 Basic Page Map +F +E +D +C +B +A +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 10 MOVB io:bp, A 20 30 CLRB io:bp 40 50 SETB io:bp 60 70 BBC io;bp, rel 80 90 BBS io:bp, rel A0 B0 MOVB MOVB A, MOVB MOVB CLRB CLRB SETB SETB BBC BBC BBS BBS A, dir:bp addr16:bp dir:bp, A addr16:bp,A dir:bp addr16:bp dir:bp addr16:bp dir:bp, rel addr16:bp,rel dir:bp, rel addr16:bp,rel MOVB A, io:bp 00 WBTS io:bp C0 D0 WBTC io:bp E0 SBBS addr16:bp F0 APPENDIX B Instructions Table B.9-3 Bit Operation Instruction Map (First Byte = 6CH) 461 462 MOVSI MOVSD PCB, PCB PCB, DTB PCB, ADB PCB, SPB DTB, PCB DTB, DTB DTB, ADB DTB, SPB ADB, PCB ADB, DTB ADB, ADB ADB, SPB SPB, PCB SPB, DTB SPB, ADB SPB, SPB +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F 10 +0 00 MOVSWI 20 MOVSWD 30 40 50 60 70 90 A0 B0 C0 SPB ADB DTB SPB ADB DTB SPB ADB DTB SPB ADB DTB SPB ADB DTB SCEQI SCEQD SCWEQI SCWEQD FILSI PCB PCB PCB PCB PCB 80 D0 FILSI SPB ADB DTB PCB E0 F0 APPENDIX B Instructions Table B.9-4 Character String Operation Instruction Map (First Byte = 6EH) LSLW LSLL LSL MOVW MOVW A, R0 A, R0 A, R0 @RL2+d8, A A, @RL2+d8 MOVW MOVW NRML A, @A @AL, AH A, R0 ASRW ASRL ASR MOVW MOVW A, R0 A, R0 A, R0 @RL3+d8, A A, @RL3+d8 LSRW LSRL LSR A, R0 A, R0 A, R0 +D +E +F MOVW MOVW @RL1+d8, A A, @RL1+d8 MOVW MOVW @RL0+d8, A A, @RL0+d8 +C +B +A +9 +8 A MOV MOV MOVX MOV MOV A, PCB A, @A A, @RL3+d8 @RL3+d8, A A, @RL3+d8 +6 ROLC MOV MOV A, @A @AL, AH +5 A MOV MOV MOVX MOV MOV A, DPR DPR, A A, @RL2+d8 @RL2+d8, A A, @RL2+d8 +4 ROLC MOV MOV A, USB USB, A +3 +7 MOV MOV MOVX MOV MOV A, SSB SSB, A A, @RL1+d8 @RL1+d8, A A, @RL1+d8 +2 40 MOV MOV A, ADB ADB, A 30 +1 20 MOV MOV MOVX MOV MOV A, DTB DTB, A A, @RL0+d8 @RL0+d8, A A, @RL0+d8 10 +0 00 50 DIVU MULW MUL 60 A A A 70 80 90 A0 B0 C0 D0 E0 F0 APPENDIX B Instructions Table B.9-5 2-byte Instruction Map (First Byte = 6FH) 463 464 50 90 B0 D0 @RW1, @RW1+d16 CMPL CMPL A, ANDL ANDL A, ORL ORL A, XORL XORL A, #16, rel #16, rel A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW2, @RW2+d16 CMPL CMPL A, ANDL ANDL A, ORL ORL A, XORL XORL A, #16, rel #16, rel A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW3, @RW3+d16 CMPL CMPL A, ANDL ANDL A, ORL ORL A, XORL XORL A, #16, rel #16, rel A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 SUBL SUBL A, A, RL2 @RW5+d8 SUBL SUBL A, A, RL3 @RW6+d8 SUBL SUBL A, A, RL3 @RW7+d8 ADDL ADDL A, A, RL2 @RW5+d8 ADDL ADDL A, A, RL3 @RW6+d8 ADDL ADDL A, A, RL3 @RW7+d8 ADDL ADDL A, SUBL SUBL A, A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 ADDL ADDL A, SUBL SUBL A, A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 ADDL ADDL A, SUBL SUBL A, A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 ADDL ADDL A, SUBL SUBL A, A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 ADDL ADDL A, SUBL SUBL A, Use @RW0+RW7 CMPL CMPL A, ANDL ANDL A, ORL ORL A, XORL XORL A, Use @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited #16, rel A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited ,#8, rel ADDL ADDL A, SUBL SUBL A, Use @RW1+RW7 CMPL CMPL A, ANDL ANDL A, ORL ORL A, XORL XORL A, Use @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited #16, rel A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited ,#8, rel ADDL ADDL A, A,@RW2+ @PC+d16 ADDL ADDL A, SUBL SUBL A, Use A,@RW3+ addr16 A,@RW3+ addr16 prohibited +5 +6 +7 +8 +9 +A +B +C +D +E +F SUBL SUBL A, A,@RW2+ @PC+d16 @RW0, @RW0+d16 CMPL CMPL A, ANDL ANDL A, ORL ORL A, XORL XORL A, #16, rel #16, rel A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 SUBL SUBL A, A, RL2 @RW4+d8 Use prohibited ANDL ANDL A, A,@RW2+ @PC+d16 ANDL ANDL A, A, RL3 @RW7+d8 ANDL ANDL A, A, RL3 @RW6+d8 ANDL ANDL A, A, RL2 @RW5+d8 ANDL ANDL A, A, RL2 @RW4+d8 ORL ORL A, A,@RW2+ @PC+d16 ORL ORL A, A, RL3 @RW7+d8 ORL ORL A, A, RL3 @RW6+d8 ORL ORL A, A, RL2 @RW5+d8 ORL ORL A, A, RL2 @RW4+d8 XORL XORL A, A,@RW2+ @PC+d16 XORL XORL A, A, RL3 @RW7+d8 XORL XORL A, A, RL3 @RW6+d8 XORL XORL A, A, RL2 @RW5+d8 XORL XORL A, A, RL2 @RW4+d8 XORL XORL A, A, RL1 @RW3+d8 addr16, ,#8, rel Use @PC+d16, prohibited ,#8, rel @RW3, @RW3+d16 #8, rel ,#8, rel @RW2, @RW2+d16 #8, rel ,#8, rel @RW1, @RW1+d16 #8, rel ,#8, rel @RW0, @RW0+d16 #8, rel ,#8, rel R7, @RW7+d8, #8, rel #8, rel R6, @RW6+d8, #8, rel #8, rel R5, @RW5+d8, #8, rel #8, rel R4, @RW4+d8, #8, rel #8, rel R3, @RW3+d8, #8, rel #8, rel addr16, CMPL CMPL A, ANDL ANDL A, ORL ORL A, XORL XORL A, Use #16, rel A,@RW3+ addr16 A,@RW3+ addr16 A,@RW3+ addr16 A,@RW3+ addr16 prohibited @PC+d16, CMPL CMPL A, #16, rel A,@RW2+ @PC+d16 RW7, @RW7+d8 CMPL CMPL A, #16, rel #16, rel A, RL3 @RW7+d8 RW6, @RW6+d8 CMPL CMPL A, #16, rel #16, rel A, RL3 @RW6+d8 RW5, @RW5+d8 CMPL CMPL A, #16, rel #16, rel A, RL2 @RW5+d8 RW4, @RW4+d8 CMPL CMPL A, #16, rel #16, rel A, RL2 @RW4+d8 ORL ORL A, A, RL1 @RW3+d8 R2, @RW2+d8, #8, rel #8, rel R1, @RW1+d8, #8, rel #8, rel ADDL ADDL A, A, RL2 @RW4+d8 ANDL ANDL A, A, RL1 @RW3+d8 XORL XORL A, A, RL1 @RW2+d8 XORL XORL A, A, RL0 @RW1+d8 +4 RW3, @RW3+d8 CMPL CMPL A, #16, rel #16, rel A, RL1 @RW3+d8 ORL ORL A, A, RL1 @RW2+d8 ORL ORL A, A, RL0 @RW1+d8 SUBL SUBL A, A, RL1 @RW3+d8 ANDL ANDL A, A, RL1 @RW2+d8 ANDL ANDL A, A, RL0 @RW1+d8 ADDL ADDL A, A, RL1 @RW3+d8 RW2, @RW2+d8 CMPL CMPL A, #16, rel #16, rel A, RL1 @RW2+d8 RW1, @RW1+d8 CMPL CMPL A, #16, rel #16, rel A, RL0 @RW1+d8 +3 CBNE ↓ F0 R0, @RW0+d8, #8, rel #8, rel CBNE ↓ E0 SUBL SUBL A, A, RL1 @RW2+d8 XORL XORL A, A, RL0 @RW0+d8 C0 ADDL ADDL A, A, RL1 @RW2+d8 ORL ORL A, A, RL0 @RW0+d8 A0 +2 ANDL ANDL A, A, RL0 @RW0+d8 80 SUBL SUBL A, A, RL0 @RW1+d8 70 ADDL ADDL A, A, RL0 @RW1+d8 60 RW0, @RW0+d8 CMPL CMPL A, #16, rel #16, rel A, RL0 @RW0+d8 CWBNE ↓ CWBNE ↓ 40 +1 30 +0 20 SUBL SUBL A, A, RL0 @RW0+d8 10 ADDL ADDL A, A, RL0 @RW0+d8 00 APPENDIX B Instructions Table B.9-6 ea Instruction 1 (First Byte = 70H) JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL3 @@RW7+d8 @RL3 @@RW7+d8 RL3 @RW7+d8 RL3 @RW7+d8 A, RL3 @RW7+d8 RL3, A @RW7+d8,A R7, #8 @RW7+d8,#8 A, RW7 @RW7+d8 JMPP JMPP @ CALLP CALLP @ INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW0 @RW0+d16 @@RW0 @RW0+d16 @RW0 @RW0+d16 @RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #8 @RW0+d16,#8 A,@RW0 @RW0+d16 JMPP JMPP @ CALLP CALLP @ INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW1 @RW1+d16 @@RW1 @RW1+d16 @RW1 @RW1+d16 @RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1,A @RW1+d16,A @RW1, #8 @RW1+d16,#8 A,@RW1 @RW1+d16 JMPP JMPP @ CALLP CALLP @ INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW2 @RW2+d16 @@RW2 @RW2+d16 @RW2 @RW2+d16 @RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2,A @RW2+d16,A @RW2, #8 @RW2+d16,#8 A,@RW2 @RW2+d16 JMPP JMPP @ CALLP CALLP @ INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW3 @RW3+d16 @@RW3 @RW3+d16 @RW3 @RW3+d16 @RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3,A @RW3+d16,A @RW3, #8 @RW3+d16,#8 A,@RW3 @RW3+d16 JMPP JMPP @ CALLP CALLP @ INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+,A @RW0+RW7,A @RW0+, #8 @RW0+RW7,#8 A,@RW0+ @RW0+RW7 JMPP JMPP @ CALLP CALLP @ INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+,A @RW1+RW7,A @RW1+, #8 @RW1+RW7,#8 A,@RW1+ @RW1+RW7 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW2+ @@PC+d16 @@RW2+ @@PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+,A @PC+d16, A @RW2+, #8 @PC+d16, #8 A,@RW2+ @PC+d16 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW3+ @addr16 @@RW3+ @addr16 @RW3+ addr16 @RW3+ addr16 A,@RW3+ addr16 @RW3+,A addr16, A @RW3+, #8 addr16, #8 A,@RW3+ addr16 +8 +9 +A +B +C +D +E +F F0 +7 E0 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL3 @@RW6+d8 @RL3 @@RW6+d8 RL3 @RW6+d8 RL3 @RW6+d8 A, RL3 @RW6+d8 RL3, A @RW6+d8,A R6, #8 @RW6+d8,#8 A, RW6 @RW6+d8 D0 +6 C0 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL2 @@RW5+d8 @RL2 @@RW5+d8 RL2 @RW5+d8 RL2 @RW5+d8 A, RL2 @RW5+d8 RL2, A @RW5+d8,A R5, #8 @RW5+d8,#8 A, RW5 @RW5+d8 B0 +5 A0 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL2 @@RW4+d8 @RL2 @@RW4+d8 RL2 @RW4+d8 RL2 @RW4+d8 A, RL2 @RW4+d8 RL2, A @RW4+d8,A R4, #8 @RW4+d8,#8 A, RW4 @RW4+d8 90 +4 80 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL1 @@RW3+d8 @RL1 @@RW3+d8 RL1 @RW3+d8 RL1 @RW3+d8 A, RL1 @RW3+d8 RL1, A @RW3+d8,A R3, #8 @RW3+d8,#8 A, RW3 @RW3+d8 70 +3 60 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL1 @@RW2+d8 @RL1 @@RW2+d8 RL1 @RW2+d8 RL1 @RW2+d8 A, RL1 @RW2+d8 RL1, A @RW2+d8,A R2, #8 @RW2+d8,#8 A, RW2 @RW2+d8 50 +2 40 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL0 @@RW1+d8 @RL0 @@RW1+d8 RL0 @RW1+d8 RL0 @RW1+d8 A, RL0 @RW1+d8 RL0, A @RW1+d8,A R1, #8 @RW1+d8,#8 A, RW1 @RW1+d8 30 +1 20 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL0 @@RW0+d8 @RL0 @@RW0+d8 RL0 @RW0+d8 RL0 @RW0+d8 A, RL0 @RW0+d8 RL0, A @RW0+d8,A R0, #8 @RW0+d8,#8 A, RW0 @RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-7 ea Instruction 2 (First Byte = 71H) 465 466 D0 E0 F0 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 A,@RW3+ addr16 @RW3+, A addr16, A A,@RW3+ addr16 A,@RW3+ addr16 +D +E +F DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R7 @RW7+d8 A, R7 @RW7+d8 R7, A @RW7+d8,A A, R7 @RW7+d8 A, R7 @RW7+d8 DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R6 @RW6+d8 A, R6 @RW6+d8 R6, A @RW6+d8,A A, R6 @RW6+d8 A, R6 @RW6+d8 DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R5 @RW5+d8 A, R5 @RW5+d8 R5, A @RW5+d8,A A, R5 @RW5+d8 A, R5 @RW5+d8 DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R4 @RW4+d8 A, R4 @RW4+d8 R4, A @RW4+d8,A A, R4 @RW4+d8 A, R4 @RW4+d8 DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R3 @RW3+d8 A, R3 @RW3+d8 R3, A @RW3+d8,A A, R3 @RW3+d8 A, R3 @RW3+d8 DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R2 @RW2+d8 A, R2 @RW2+d8 R2, A @RW2+d8,A A, R2 @RW2+d8 A, R2 @RW2+d8 DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R1 @RW1+d8 A, R1 @RW1+d8 R1, A @RW1+d8,A A, R1 @RW1+d8 A, R1 @RW1+d8 +C INC DEC R7 @RW7+d8 C0 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW3 @RW3+d16 @RW3 @RW3+d16 @RW3 @RW3+d16 @RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 ROLC RORC RORC INC R7 @RW7+d8 R7 @RW7+d8 ROLC INC DEC R6 @RW6+d8 B0 +B ROLC RORC RORC INC R6 @RW6+d8 R6 @RW6+d8 ROLC INC DEC R5 @RW5+d8 A0 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW2 @RW2+d16 @RW2 @RW2+d16 @RW2 @RW2+d16 @RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 ROLC RORC RORC INC R5 @RW5+d8 R5 @RW5+d8 ROLC INC DEC R4 @RW4+d8 90 +A ROLC RORC RORC INC R4 @RW4+d8 R4 @RW4+d8 ROLC INC DEC R3 @RW3+d8 INC DEC R2 @RW2+d8 INC DEC R1 @RW1+d8 80 DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R0 @RW0+d8 A, R0 @RW0+d8 R0, A @RW0+d8,A A, R0 @RW0+d8 A, R0 @RW0+d8 70 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW1 @RW1+d16 @RW1 @RW1+d16 @RW1 @RW1+d16 @RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 ROLC RORC RORC INC R3 @RW3+d8 R3 @RW3+d8 ROLC 60 INC DEC R0 @RW0+d8 50 +9 ROLC RORC RORC INC R2 @RW2+d8 R2 @RW2+d8 ROLC 40 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW0 @RW0+d16 @RW0 @RW0+d16 @RW0 @RW0+d16 @RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0, A @RW0+d16,A A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 ROLC RORC RORC INC R1 @RW1+d8 R1 @RW1+d8 ROLC 30 ROLC RORC RORC INC R0 @RW0+d8 R0 @RW0+d8 20 ROLC 10 +8 +7 +6 +5 +4 +3 +2 +1 +0 00 APPENDIX B Instructions Table B.9-8 ea Instruction 3 (First Byte = 72H) JMP JMP @ CALL CALL @ INCW INCW @ DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @@RW3 @RW3+d16 @@RW3 @RW3+d16 @RW3 @RW3+d16 @RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, #16 @RW3+d16,#16 A,@RW3 @RW3+d16 +B JMP JMP CALL CALL INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @@RW3+ @addr16 @@RW3+ @addr16 @RW3+ addr16 @RW3+ addr16 A,@RW3+ addr16 @RW3+, A addr16, A @RW3+, #16 addr16, #16 A,@RW3+ addr16 INCW @ +F INCW JMP JMP CALL CALL INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @@RW2+ @@PC+d16 @@RW2+ @@PC+d16 @RW2+ @@PC+d16 @RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A @RW2+, #16 @PC+d16, #16 A,@RW2+ @PC+d16 CALL @ +E CALL DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, #16 @RW1+RW7,#16 A,@RW1+ @RW1+RW7 XCHW XCHW A, A, RW7 @RW7+d8 XCHW XCHW A, A, RW6 @RW6+d8 XCHW XCHW A, A, RW5 @RW5+d8 +D @@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 INCW @ MOVW MOVW RW7, #16 @RW7+d8,#16 MOVW MOVW RW6, #16 @RW6+d8,#16 MOVW MOVW RW5, #16 @RW5+d8,#16 XCHW XCHW A, A, RW4 @RW4+d8 DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, #16 @RW0+RW7,#16 A,@RW0+ @RW0+RW7 INCW INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW7 @RW7+d8 RW7 @RW7+d8 A, RW7 @RW7+d8 RW7, A @RW7+d8,A INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW6 @RW6+d8 RW6 @RW6+d8 A, RW6 @RW6+d8 RW6, A @RW6+d8,A INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW5 @RW5+d8 RW5 @RW5+d8 A, RW5 @RW5+d8 RW5, A @RW5+d8,A MOVW MOVW RW4, #16 @RW4+d8,#16 +C @@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 JMP @ JMP JMP @ CALL CALL @ INCW INCW @ DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @@RW2 @RW2+d16 @@RW2 @RW2+d16 @RW2 @RW2+d16 @RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, #16 @RW2+d16,#16 A,@RW2 @RW2+d16 +A JMP JMP JMP @ CALL CALL @ INCW INCW @ DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @@RW1 @RW1+d16 @@RW1 @RW1+d16 @RW1 @RW1+d16 @RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, #16 @RW1+d16,#16 A,@RW1 @RW1+d16 +9 CALL @ JMP JMP @ CALL CALL @ INCW INCW @ DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @@RW0 @RW0+d16 @@RW0 @RW0+d16 @RW0 @RW0+d16 @RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #16 @RW0+d16,#16 A,@RW0 @RW0+d16 +8 CALL CALL CALL RW7 @@RW7+d8 JMP JMP @RW7 @@RW7+d8 +7 JMP @ CALL CALL RW6 @@RW6+d8 JMP JMP @RW6 @@RW6+d8 +6 JMP CALL CALL RW5 @@RW5+d8 JMP JMP @RW5 @@RW5+d8 +5 INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW4 @RW4+d8 RW4 @RW4+d8 A, RW4 @RW4+d8 RW4, A @RW4+d8,A XCHW XCHW A, A, RW3 @RW3+d8 XCHW XCHW A, A, RW2 @RW2+d8 XCHW XCHW A, A, RW1 @RW1+d8 CALL CALL RW4 @@RW4+d8 MOVW MOVW RW3, #16 @RW3+d8,#16 MOVW MOVW RW2, #16 @RW2+d8,#16 MOVW MOVW RW1, #16 @RW1+d8,#16 JMP JMP @RW4 @@RW4+d8 INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW3 @RW3+d8 RW3 @RW3+d8 A, RW3 @RW3+d8 RW3, A @RW3+d8,A INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW2 @RW2+d8 RW2 @RW2+d8 A, RW2 @RW2+d8 RW2, A @RW2+d8,A INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW1 @RW1+d8 RW1 @RW1+d8 A, RW1 @RW1+d8 RW1, A @RW1+d8,A +4 F0 XCHW XCHW A, A, RW0 @RW0+d8 E0 CALL CALL RW3 @@RW3+d8 D0 MOVW MOVW RW0, #16 @RW0+d8,#16 C0 JMP JMP @RW3 @@RW3+d8 B0 +3 A0 CALL CALL RW2 @@RW2+d8 90 JMP JMP @RW2 @@RW2+d8 80 +2 70 CALL CALL RW1 @@RW1+d8 60 JMP JMP @RW1 @@RW1+d8 50 INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW0 @RW0+d8 RW0 @RW0+d8 A, RW0 @RW0+d8 RW0, A @RW0+d8,A 40 +1 30 CALL CALL RW0 @@RW0+d8 20 JMP JMP @RW0 @@RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-9 ea Instruction 4 (First Byte = 73H) 467 468 ADD A, SUB SUB SUB ADDC A, ADDC A, ADDC ADDC A, A, CMP CMP CMP CMP A, A, A, AND AND AND AND AND AND A, A, A, OR OR A, XOR XOR A, DBNZ DBNZ @ A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r PC+d16, r +F A,@RW3+ ADD ADD SUB SUB ADDC ADDC CMP CMP AND AND OR OR XOR XOR DBNZ DBNZ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 @RW3+, r addr16, r +E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 ADD SUB CMP XOR XOR A, DBNZ DBNZ @R A,@RW1+ @RW1+RW7 @RW1+, r W1+RW7, r A, CMP OR OR A, A,@RW1+ @RW1+RW7 ADD ADD ADDC A, +D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 ADDC XOR XOR A, DBNZ DBNZ @R A,@RW0+ @RW0+RW7 @RW0+, r W0+RW7, r A, OR OR A, A,@RW0+ @RW0+RW7 SUB +C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 SUB XOR XOR A, DBNZ DBNZ @R A,@RW3 @RW3+d16 @RW3, r W3+d16, r ADD ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 +B A, XOR XOR A, DBNZ DBNZ @R A,@RW2 @RW2+d16 @RW2, r W2+d16, r ADD ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 +A ADD XOR XOR A, DBNZ DBNZ @R A,@RW1 @RW1+d16 @RW1, r W1+d16, r ADD ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 +9 ADD XOR XOR A, DBNZ DBNZ @R A,@RW0 @RW0+d16 @RW0, r W0+d16, r ADD ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R7 @RW7+d8 A, R7 @RW7+d8 A, R7 @RW7+d8 A, R7 @RW7+d8 A, R7 @RW7+d8 A, R7 @RW7+d8 A, R7 @RW7+d8 R7, r RW7+d8, r ADD F0 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R6 @RW6+d8 A, R6 @RW6+d8 A, R6 @RW6+d8 A, R6 @RW6+d8 A, R6 @RW6+d8 A, R6 @RW6+d8 A, R6 @RW6+d8 R6, r RW6+d8, r E0 ADD D0 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R5 @RW5+d8 A, R5 @RW5+d8 A, R5 @RW5+d8 A, R5 @RW5+d8 A, R5 @RW5+d8 A, R5 @RW5+d8 A, R5 @RW5+d8 R5, r RW5+d8, r C0 ADD B0 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R4 @RW4+d8 A, R4 @RW4+d8 A, R4 @RW4+d8 A, R4 @RW4+d8 A, R4 @RW4+d8 A, R4 @RW4+d8 A, R4 @RW4+d8 R4, r RW4+d8, r A0 ADD 90 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R3 @RW3+d8 A, R3 @RW3+d8 A, R3 @RW3+d8 A, R3 @RW3+d8 A, R3 @RW3+d8 A, R3 @RW3+d8 A, R3 @RW3+d8 R3, r RW3+d8, r 80 ADD 70 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R2 @RW2+d8 A, R2 @RW2+d8 A, R2 @RW2+d8 A, R2 @RW2+d8 A, R2 @RW2+d8 A, R2 @RW2+d8 A, R2 @RW2+d8 R2, r RW2+d8, r 60 ADD 50 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R1 @RW1+d8 A, R1 @RW1+d8 A, R1 @RW1+d8 A, R1 @RW1+d8 A, R1 @RW1+d8 A, R1 @RW1+d8 A, R1 @RW1+d8 R1, r RW1+d8, r 40 ADD 30 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R0 @RW0+d8 A, R0 @RW0+d8 A, R0 @RW0+d8 A, R0 @RW0+d8 A, R0 @RW0+d8 A, R0 @RW0+d8 A, R0 @RW0+d8 R0, r RW0+d8, r 20 ADD 10 +8 +7 +6 +5 +4 +3 +2 +1 +0 00 APPENDIX B Instructions Table B.9-10 ea Instruction 5 (First Byte = 74H) NOT NOT R2 @RW2+d8 SUB SUB SUB SUB ADD SUB SUB @RW1+RW7,A @RW1+, A @RW1+RW7,A ADD @R @RW0+RW7,A @RW0+, A @RW0+RW7,A ADD @R +F ADD ADD @RW3+, A addr16, A SUB SUB @RW3+, A addr16, A +E @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A ADD +D @RW1+, A ADD +C @RW0+, A ADD NOT NOT @RW1+ @RW1+RW7 NOT NOT @RW0+ @RW0+RW7 SUBC SUBC A, NEG NEG A, AND AND A,@RW3+ addr16 @RW3+ addr16 @RW3+, A addr16, A OR OR @RW3+, A addr16, A XOR XOR @RW3+, A addr16, A NOT NOT @RW3+ addr16 SUBC SUBC A, NEG NEG A, AND AND OR OR XOR XOR NOT NOT A,@RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+ @PC+d16 SUBC SUBC A, NEG NEG A, AND AND OR OR XOR XOR A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A SUBC SUBC A, NEG NEG A, AND AND OR OR XOR XOR A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A NOT NOT @RW3 @RW3+d16 ADD ADD @R SUB SUB SUBC SUBC A, NEG NEG A, AND AND OR OR XOR XOR @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16 @RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A +B XOR NOT NOT R7, A @RW7+d8, A R7 @RW7+d8 XOR NOT NOT R6, A @RW6+d8, A R6 @RW6+d8 XOR NOT NOT R5, A @RW5+d8, A R5 @RW5+d8 XOR NOT NOT R4, A @RW4+d8, A R4 @RW4+d8 XOR NOT NOT R3, A @RW3+d8, A R3 @RW3+d8 XOR R2, A @RW2+d8,A XOR NOT NOT R1, A @RW1+d8, A R1 @RW1+d8 NOT NOT @RW2 @RW2+d16 XOR F0 ADD ADD @R SUB SUB SUBC SUBC A, NEG NEG A, AND AND OR OR XOR XOR @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16 @RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A NEG A, AND AND OR OR R7 @RW7+d8 R7, A @RW7+d8, A R7, A @RW7+d8, A XOR XOR XOR XOR XOR XOR E0 XOR NOT NOT R0, A @RW0+d8, A R0 @RW0+d8 D0 +A ADD SUB SUB SUBC SUBC A, NEG R7, A @RW7+d8, A R7, A @RW7+d8, A A, R7 @RW7+d8 ADD NEG A, AND AND OR OR R6 @RW6+d8 R6, A @RW6+d8, A R6, A @RW6+d8, A NEG A, AND AND OR OR R5 @RW5+d8 R5, A @RW5+d8, A R5, A @RW5+d8, A NEG A, AND AND OR OR R4 @RW4+d8 R4, A @RW4+d8, A R4, A @RW4+d8, A NEG A, AND AND OR OR R3 @RW3+d8 R3, A @RW3+d8, A R3, A @RW3+d8, A NEG A, AND AND OR OR R2 @RW2+d8 R2, A @RW2+d8,A R2, A @RW2+d8,A NEG A, AND AND OR OR R1 @RW1+d8 R1, A @RW1+d8, A R1, A @RW1+d8, A XOR C0 NOT NOT @RW1 @RW1+d16 ADD SUB SUB SUBC SUBC A, NEG R6, A @RW6+d8, A R6, A @RW6+d8, A A, R6 @RW6+d8 ADD B0 ADD ADD @R SUB SUB SUBC SUBC A, NEG NEG A, AND AND OR OR XOR XOR @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16 @RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A ADD SUB SUB SUBC SUBC A, NEG R5, A @RW5+d8, A R5, A @RW5+d8, A A, R5 @RW5+d8 ADD A0 +9 ADD SUB SUB SUBC SUBC A, NEG R4, A @RW4+d8, A R4, A @RW4+d8, A A, R4 @RW4+d8 ADD 90 NOT NOT @RW0 @RW0+d16 ADD SUB SUB SUBC SUBC A, NEG R3, A @RW3+d8, A R3, A @RW3+d8, A A, R3 @RW3+d8 ADD 80 NEG A, AND AND OR OR R0 @RW0+d8 R0, A @RW0+d8, A R0, A @RW0+d8, A 70 ADD ADD SUB SUB SUBC SUBC A, NEG NEG A, AND AND OR OR XOR XOR @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16 @RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A ADD SUB SUB SUBC SUBC A, NEG R2, A @RW2+d8,A R2, A @RW2+d8,A A, R2 @RW2+d8 60 ADD 50 ADD SUB SUB SUBC SUBC A, NEG R1, A @RW1+d8, A R1, A @RW1+d8, A A, R1 @RW1+d8 40 ADD 30 ADD SUB SUB SUBC SUBC A, NEG R0, A @RW0+d8, A R0, A @RW0+d8, A A, R0 @RW0+d8 20 ADD 10 +8 +7 +6 +5 +4 +3 +2 +1 +0 00 APPENDIX B Instructions Table B.9-11 ea Instruction 6 (First Byte = 75H) 469 470 ADDW A, SUBW ADDW ADDCW CMPW ADDCW A, CMPW ADDCW A, ANDW CMPW A, ANDW CMPW A, ORW ORW ANDW A, ORW ANDW A, ANDW A, ORW ORW ORW A, A, A, XORW XORW A, DWBNZ DWBNZ +F A,@RW3+ ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ addr 16 A,@RW3+ addr 16 A,@RW3+ addr 16 A,@RW3+ addr 16 A,@RW3+ addr 16 A,@RW3+ addr r16 A,@RW3+ addr 16 @RW3+, r addr r16, r +E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r @PC+d16,r SUBW A, ADDCW SUBW A, ANDW XORW XORW A, DWBNZ DWBNZ A,@RW1+ @RW1+RW7 @RW1+, r @RW1+RW7,r SUBW ADDW A, ADDW CMPW A, +D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 CMPW XORW XORW A, DWBNZ DWBNZ A,@RW0+ @RW0+RW7 @RW0+, r @RW0+RW7,r ADDCW A, +C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 ADDCW XORW XORW A, DWBNZ DWBNZ A,@RW3 @RW3+d16 @RW3, r @RW3+d16,r ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 +B SUBW A, XORW XORW A, DWBNZ DWBNZ A,@RW2 @RW2+d16 @RW2, r @RW2+d16,r ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 +A SUBW XORW XORW A, DWBNZ DWBNZ A,@RW1 @RW1+d16 @RW1, r @RW1+d16,r ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 +9 ADDW A, XORW XORW A, DWBNZ DWBNZ A,@RW0 @RW0+d16 @RW0, r @RW0+d16,r ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 +8 ADDW ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW7 @RW7+d8 A, RW7 @RW7+d8 A, RW7 @RW7+d8 A, RW7 @RW7+d8 A, RW7 @RW7+d8 A, RW7 @RW7+d8 A, RW7 @RW7+d8 RW7, r @RW7+d8,r F0 +7 E0 ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW6 @RW6+d8 A, RW6 @RW6+d8 A, RW6 @RW6+d8 A, RW6 @RW6+d8 A, RW6 @RW6+d8 A, RW6 @RW6+d8 A, RW6 @RW6+d8 RW6, r @RW6+d8,r D0 +6 C0 ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW5 @RW5+d8 A, RW5 @RW5+d8 A, RW5 @RW5+d8 A, RW5 @RW5+d8 A, RW5 @RW5+d8 A, RW5 @RW5+d8 A, RW5 @RW5+d8 RW5, r @RW5+d8,r B0 +5 A0 ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW4 @RW4+d8 A, RW4 @RW4+d8 A, RW4 @RW4+d8 A, RW4 @RW4+d8 A, RW4 @RW4+d8 A, RW4 @RW4+d8 A, RW4 @RW4+d8 RW4, r @RW4+d8,r 90 +4 80 ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW3 @RW3+d8 A, RW3 @RW3+d8 A, RW3 @RW3+d8 A, RW3 @RW3+d8 A, RW3 @RW3+d8 A, RW3 @RW3+d8 A, RW3 @RW3+d8 RW3, r @RW3+d8,r 70 +3 60 ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW2 @RW2+d8 A, RW2 @RW2+d8 A, RW2 @RW2+d8 A, RW2 @RW2+d8 A, RW2 @RW2+d8 A, RW2 @RW2+d8 A, RW2 @RW2+d8 RW2, r @RW2+d8,r 50 +2 40 ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW1 @RW1+d8 A, RW1 @RW1+d8 A, RW1 @RW1+d8 A, RW1 @RW1+d8 A, RW1 @RW1+d8 A, RW1 @RW1+d8 A, RW1 @RW1+d8 RW1, r @RW1+d8,r 30 +1 20 ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW0 @RW0+d8 A, RW0 @RW0+d8 A, RW0 @RW0+d8 A, RW0 @RW0+d8 A, RW0 @RW0+d8 A, RW0 @RW0+d8 A, RW0 @RW0+d8 RW0, r @RW0+d8,r 10 +0 00 APPENDIX B Instructions Table B.9-12 ea Instruction 7 (First Byte = 76H) NEGW NEGW ANDW ANDW ORW ORW XORW XORW NOTW NOTW @RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3 @RW3+d16 SUBW SUBW @RW3+, A addr16, A ADDW ADDW @RW3+, A addr16, A +F SUBCW SUBCW A, NEGW NEGW ANDW ANDW A,@RW3+ addr16 @RW3+ addr16 @RW3+, A addr16, A ORW ORW @RW3+, A addr16, A XORW XORW @RW3+, A addr16, A NOTW NOTW @RW3+ addr16 SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW XORW XORW NOTW NOTW A,@RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+ @PC+d16 SUBW SUBW @RW2+, A @PC+d16,A ADDW ADDW @RW2+, A @PC+d16,A +E SUBCW A, ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW XORW XORW NOTW NOTW @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+ @RW1+RW7 SUBCW +D SUBW SUBCW A, ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW XORW XORW NOTW NOTW @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+ @RW0+RW7 SUBW SUBCW +C ADDW ADDW SUBW SUBCW A, +B @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16 SUBW SUBCW NEGW NEGW ANDW ANDW ORW ORW XORW XORW NOTW NOTW @RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2 @RW2+d16 ADDW ADDW SUBW +A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16 SUBW NEGW NEGW ANDW ANDW ORW ORW XORW XORW NOTW NOTW @RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1 @RW1+d16 ADDW ADDW SUBCW A, +9 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16 SUBCW NEGW NEGW ANDW ANDW ORW ORW XORW XORW NOTW NOTW @RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0 @RW0+d16 SUBW NOTW NOTW RW7 @RW7+d8 NOTW NOTW RW6 @RW6+d8 NOTW NOTW RW5 @RW5+d8 +8 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16 SUBW XORW XORW RW7, A @RW7+d8, A ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW RW7, A @RW7+d8, A RW7, A @RW7+d8, A A, RW7 @RW7+d8 RW7 @RW7+d8 RW7, A @RW7+d8, A RW7, A @RW7+d8, A +7 ADDW XORW XORW RW6, A @RW6+d8, A ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW RW6, A @RW6+d8, A RW6, A @RW6+d8, A A, RW6 @RW6+d8 RW6 @RW6+d8 RW6, A @RW6+d8, A RW6, A @RW6+d8, A +6 ADDW XORW XORW RW5, A @RW5+d8, A ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW RW5, A @RW5+d8, A RW5, A @RW5+d8, A A, RW5 @RW5+d8 RW5 @RW5+d8 RW5, A @RW5+d8, A RW5, A @RW5+d8, A +5 NOTW NOTW RW4 @RW4+d8 XORW XORW RW4, A @RW4+d8, A ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW RW4, A @RW4+d8, A RW4, A @RW4+d8, A A, RW4 @RW4+d8 RW4 @RW4+d8 RW4, A @RW4+d8, A RW4, A @RW4+d8, A +4 F0 NOTW NOTW RW0 @RW0+d8 E0 NOTW NOTW RW3 @RW3+d8 D0 XORW XORW RW3, A @RW3+d8, A C0 ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW RW3, A @RW3+d8, A RW3, A @RW3+d8, A A, RW3 @RW3+d8 RW3 @RW3+d8 RW3, A @RW3+d8, A RW3, A @RW3+d8, A B0 +3 A0 NOTW NOTW RW2 @RW2+d8 90 ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW XORW XORW RW2, A @RW2+d8,A RW2, A @RW2+d8,A A, RW2 @RW2+d8 RW2 @RW2+d8 RW2, A @RW2+d8,A RW2, A @RW2+d8,A RW2, A @RW2+d8,A 80 +2 70 NOTW NOTW RW1 @RW1+d8 60 XORW XORW RW1, A @RW1+d8, A 50 ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW RW1, A @RW1+d8, A RW1, A @RW1+d8, A A, RW1 @RW1+d8 RW1 @RW1+d8 RW1, A @RW1+d8, A RW1, A @RW1+d8, A 40 +1 30 XORW XORW RW0, A @RW0+d8, A 20 ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW RW0, A @RW0+d8, A RW0, A @RW0+d8, A A, RW0 @RW0+d8 RW0 @RW0+d8 RW0, A @RW0+d8, A RW0, A @RW0+d8, A 10 +0 00 APPENDIX B Instructions Table B.9-13 ea Instruction 8 (First Byte = 77H) 471 472 DIV DIV A, DIVW DIVW A, A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 DIV DIV A, DIVW DIVW A, A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, A, @RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, A, @RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, A, @RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 MULU MULU A, MULUW MULUW A, A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 MULU MULU A, MULUW MULUW A, A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 MULU MULU A, MULUW MULUW A, A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 +9 +A +B +C +D +E +F A, @RW3+ MULU DIV DIV A, DIVW DIVW A, A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, A, @RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 MULU MULU A, MULUW MULUW A, A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 +8 MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV addr16 A,@RW3+ addr16 A,@RW3+ addr16 A,@RW3+ addr16 A,@RW3+ addr16 A,@RW3+ addr16 A,@RW3+ A, DIVW DIVW A, addr16 A,@RW3+ addr16 DIV DIV A, DIVW DIVW A, A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 DIV DIV A, DIVW DIVW A, A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 DIV DIV A, DIVW DIVW A, A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R7 @RW7+d8 A, RW7 @RW7+d8 A, R7 @RW7+d8 A, RW7 @RW7+d8 A, R7 @RW7+d8 A, RW7 @RW7+d8 A, R7 @RW7+d8 A, RW7 @RW7+d8 F0 +7 E0 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R6 @RW6+d8 A, RW6 @RW6+d8 A, R6 @RW6+d8 A, RW6 @RW6+d8 A, R6 @RW6+d8 A, RW6 @RW6+d8 A, R6 @RW6+d8 A, RW6 @RW6+d8 D0 +6 C0 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R5 @RW5+d8 A, RW5 @RW5+d8 A, R5 @RW5+d8 A, RW5 @RW5+d8 A, R5 @RW5+d8 A, RW5 @RW5+d8 A, R5 @RW5+d8 A, RW5 @RW5+d8 B0 +5 A0 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R4 @RW4+d8 A, RW4 @RW4+d8 A, R4 @RW4+d8 A, RW4 @RW4+d8 A, R4 @RW4+d8 A, RW4 @RW4+d8 A, R4 @RW4+d8 A, RW4 @RW4+d8 90 +4 80 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R3 @RW3+d8 A, RW3 @RW3+d8 A, R3 @RW3+d8 A, RW3 @RW3+d8 A, R3 @RW3+d8 A, RW3 @RW3+d8 A, R3 @RW3+d8 A, RW3 @RW3+d8 70 +3 60 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R2 @RW2+d8 A, RW2 @RW2+d8 A, R2 @RW2+d8 A, RW2 @RW2+d8 A, R2 @RW2+d8 A, RW2 @RW2+d8 A, R2 @RW2+d8 A, RW2 @RW2+d8 50 +2 40 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R1 @RW1+d8 A, RW1 @RW1+d8 A, R1 @RW1+d8 A, RW1 @RW1+d8 A, R1 @RW1+d8 A, RW1 @RW1+d8 A, R1 @RW1+d8 A, RW1 @RW1+d8 30 +1 20 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R0 @RW0+d8 A, RW0 @RW0+d8 A, R0 @RW0+d8 A, RW0 @RW0+d8 A, R0 @RW0+d8 A, RW0 @RW0+d8 A, R0 @RW0+d8 A, RW0 @RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-14 ea Instruction 9 (First Byte = 78H) MOVEA MOVEA RW1 RW1,RW4 ,@RW4+d8 MOVEA MOVEA RW1 RW1,RW5 ,@RW5+d8 MOVEA MOVEA RW1 RW1,RW6 ,@RW6+d8 MOVEA MOVEA RW1 RW1,RW7 ,@RW7+d8 MOVEA MOVEA RW1 RW1,@RW0 ,@RW0+d16 MOVEA MOVEA RW1 RW1,@RW1 ,@RW1+d16 MOVEA MOVEA RW1 RW1,@RW2 ,@RW2+d16 MOVEA MOVEA RW1 RW1,@RW3 ,@RW3+d16 MOVEA MOVEA RW0 RW0,RW4 ,@RW4+d8 MOVEA MOVEA RW0 RW0,RW5 ,@RW5+d8 MOVEA MOVEA RW0 RW0,RW6 ,@RW6+d8 MOVEA MOVEA RW0 RW0,RW7 ,@RW7+d8 MOVEA RW0 MOVEA RW0 MOVEA RW0 MOVEA RW0 MOVEA RW0 MOVEA RW0 MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA +4 +5 +6 +7 50 70 90 B0 C0 D0 F0 MOVEA MOVEA RW3 RW3,@RW2+ ,@PC+d16 MOVEA MOVEA RW4 RW4,@RW2+ ,@PC+d16 MOVEA MOVEA RW7 RW7,@RW2+ ,@PC+d16 MOVEA MOVEA MOVEA MOVEA RW6,@RW3+ RW6, addr16 RW7@RW3+ RW7, addr16 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,@RW2+ ,@PC+d16 RW6,@RW2+ ,@PC+d16 MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA RW0,@RW3+ RW0, addr16 RW1,@RW3+ RW1, addr16 RW2,@RW3+ RW2, addr16 RW3,@RW3+ RW3, addr16 RW4,@RW3+ RW4, addr16 RW5,@RW3+ RW5, addr16 MOVEA MOVEA RW2 RW2,@RW2+ ,@PC+d16 +F MOVEA MOVEA RW1 RW1,@RW2+ ,@PC+d16 MOVEA MOVEA RW0 RW0,@RW2+ ,@PC+d16 MOVEA RW1 +E MOVEA MOVEA MOVEA RW5 MOVEA MOVEA RW6 MOVEA MOVEA RW7 RW5,@RW1+ ,@RW1+RW7 RW6,@RW1+ ,@RW1+RW7 RW7,@RW1+ ,@RW1+RW7 MOVEA MOVEA RW7 RW7,@RW3 ,@RW3+d16 MOVEA MOVEA RW7 RW7,@RW2 ,@RW2+d16 MOVEA MOVEA RW7 RW7,@RW1 ,@RW1+d16 MOVEA MOVEA RW7 RW7,@RW0 ,@RW0+d16 MOVEA MOVEA RW7 RW7,RW7 ,@RW7+d8 MOVEA MOVEA RW7 RW7,RW6 ,@RW6+d8 MOVEA MOVEA RW7 RW7,RW5 ,@RW5+d8 MOVEA MOVEA RW7 RW7,RW4 ,@RW4+d8 MOVEA MOVEA RW7 RW7,RW3 ,@RW3+d8 MOVEA MOVEA RW7 RW7,RW2 ,@RW2+d8 MOVEA MOVEA RW7 RW7,RW1 ,@RW1+d8 MOVEA MOVEA RW7 RW7,RW0 ,@RW0+d8 E0 MOVEA MOVEA RW2 MOVEA MOVEA RW3 MOVEA MOVEA RW4 RW2,@RW1+ ,@RW1+RW7 RW3,@RW1+ ,@RW1+RW7 RW4,@RW1+ ,@RW1+RW7 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,@RW3 ,@RW3+d16 RW6,@RW3 ,@RW3+d16 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,@RW2 ,@RW2+d16 RW6,@RW2 ,@RW2+d16 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,@RW1 ,@RW1+d16 RW6,@RW1 ,@RW1+d16 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,@RW0 ,@RW0+d16 RW6,@RW0 ,@RW0+d16 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW7 ,@RW7+d8 RW6,RW7 ,@RW7+d8 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW6 ,@RW6+d8 RW6,RW6 ,@RW6+d8 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW5 ,@RW5+d8 RW6,RW5 ,@RW5+d8 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW4 ,@RW4+d8 RW6,RW4 ,@RW4+d8 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW3 ,@RW3+d8 RW6,RW3 ,@RW3+d8 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW2 ,@RW2+d8 RW6,RW2 ,@RW2+d8 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW1 ,@RW1+d8 RW6,RW1 ,@RW1+d8 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW0 ,@RW0+d8 RW6,RW0 ,@RW0+d8 A0 +D RW0,@RW1+ ,@RW1+RW7 RW1,@RW1+ ,@RW1+RW7 MOVEA MOVEA RW4 RW4,@RW3 ,@RW3+d16 MOVEA MOVEA RW4 RW4,@RW2 ,@RW2+d16 MOVEA MOVEA RW4 RW4,@RW1 ,@RW1+d16 MOVEA MOVEA RW4 RW4,@RW0 ,@RW0+d16 MOVEA MOVEA RW4 RW4,RW7 ,@RW7+d8 MOVEA MOVEA RW4 RW4,RW6 ,@RW6+d8 MOVEA MOVEA RW4 RW4,RW5 ,@RW5+d8 MOVEA MOVEA RW4 RW4,RW4 ,@RW4+d8 MOVEA MOVEA RW4 RW4,RW3 ,@RW3+d8 MOVEA MOVEA RW4 RW4,RW2 ,@RW2+d8 MOVEA MOVEA RW4 RW4,RW1 ,@RW1+d8 MOVEA MOVEA RW4 RW4,RW0 ,@RW0+d8 80 MOVEA MOVEA RW5 MOVEA MOVEA RW6 MOVEA MOVEA RW7 RW5,@RW0+ ,@RW0+RW7 RW6,@RW0+ ,@RW0+RW7 RW7,@RW0+ ,@RW0+RW7 MOVEA MOVEA RW3 RW3,@RW3 ,@RW3+d16 MOVEA MOVEA RW3 RW3,@RW2 ,@RW2+d16 MOVEA MOVEA RW3 RW3,@RW1 ,@RW1+d16 MOVEA MOVEA RW3 RW3,@RW0 ,@RW0+d16 MOVEA MOVEA RW3 RW3,RW7 ,@RW7+d8 MOVEA MOVEA RW3 RW3,RW6 ,@RW6+d8 MOVEA MOVEA RW3 RW3,RW5 ,@RW5+d8 MOVEA MOVEA RW3 RW3,RW4 ,@RW4+d8 MOVEA MOVEA RW3 RW3,RW3 ,@RW3+d8 MOVEA MOVEA RW3 RW3,RW2 ,@RW2+d8 MOVEA MOVEA RW3 RW3,RW1 ,@RW1+d8 MOVEA MOVEA RW3 RW3,RW0 ,@RW0+d8 60 MOVEA MOVEA RW2 MOVEA MOVEA RW3 MOVEA MOVEA RW4 RW2,@RW0+ ,@RW0+RW7 RW3,@RW0+ ,@RW0+RW7 RW4,@RW0+ ,@RW0+RW7 MOVEA MOVEA RW2 RW2,@RW3 ,@RW3+d16 MOVEA MOVEA RW2 RW2,@RW2 ,@RW2+d16 MOVEA MOVEA RW2 RW2,@RW1 ,@RW1+d16 MOVEA MOVEA RW2 RW2,@RW0 ,@RW0+d16 MOVEA MOVEA RW2 RW2,RW7 ,@RW7+d8 MOVEA MOVEA RW2 RW2,RW6 ,@RW6+d8 MOVEA MOVEA RW2 RW2,RW5 ,@RW5+d8 MOVEA MOVEA RW2 RW2,RW4 ,@RW4+d8 MOVEA MOVEA RW2 RW2,RW3 ,@RW3+d8 MOVEA MOVEA RW2 RW2,RW2 ,@RW2+d8 MOVEA MOVEA RW2 RW2,RW1 ,@RW1+d8 MOVEA MOVEA RW2 RW2,RW0 ,@RW0+d8 40 +C RW0,@RW0+ ,@RW0+RW7 RW1,@RW0+ ,@RW0+RW7 +B RW0,@RW3 ,@RW3+d16 +A RW0,@RW2 ,@RW2+d16 +9 RW0,@RW1 ,@RW1+d16 MOVEA RW1 MOVEA MOVEA RW1 RW1,RW3 ,@RW3+d8 MOVEA MOVEA RW0 RW0,RW3 ,@RW3+d8 +3 MOVEA MOVEA MOVEA RW1 RW1,RW2 ,@RW2+d8 MOVEA MOVEA RW0 RW0,RW2 ,@RW2+d8 +2 +8 RW0,@RW0 ,@RW0+d16 MOVEA MOVEA RW1 RW1,RW1 ,@RW1+d8 MOVEA MOVEA RW0 RW0,RW1 ,@RW1+d8 +1 30 MOVEA MOVEA RW1 RW1,RW0 ,@RW0+d8 20 MOVEA MOVEA RW0 RW0,RW0 ,@RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-15 MOVEA RWi, ea Instruction (First Byte = 79H) 473 474 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R7 @RW7+d8 R1, R7 @RW7+d8 R2, R7 @RW7+d8 R3, R7 @RW7+d8 R4, R7 @RW7+d8 R5, R7 @RW7+d8 R6, R7 @RW7+d8 R7, R7 @RW7+d8 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0,@RW2 @RW2+d16 R1,@RW2 @RW2+d16 R2,@RW2 @RW2+d16 R3,@RW2 @RW2+d16 R4,@RW2 @RW2+d16 R5,@RW2 @RW2+d16 R6,@RW2 @RW2+d16 R7,@RW2 @RW2+d16 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16 MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7, @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7, @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7, @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7, @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 +8 +9 +A +B +C +D +E +F F0 +7 E0 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R6 @RW6+d8 R1, R6 @RW6+d8 R2, R6 @RW6+d8 R3, R6 @RW6+d8 R4, R6 @RW6+d8 R5, R6 @RW6+d8 R6, R6 @RW6+d8 R7, R6 @RW6+d8 D0 +6 C0 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R5 @RW5+d8 R1, R5 @RW5+d8 R2, R5 @RW5+d8 R3, R5 @RW5+d8 R4, R5 @RW5+d8 R5, R5 @RW5+d8 R6, R5 @RW5+d8 R7, R5 @RW5+d8 B0 +5 A0 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R4 @RW4+d8 R1, R4 @RW4+d8 R2, R4 @RW4+d8 R3, R4 @RW4+d8 R4, R4 @RW4+d8 R5, R4 @RW4+d8 R6, R4 @RW4+d8 R7, R4 @RW4+d8 90 +4 80 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R3 @RW3+d8 R1, R3 @RW3+d8 R2, R3 @RW3+d8 R3, R3 @RW3+d8 R4, R3 @RW3+d8 R5, R3 @RW3+d8 R6, R3 @RW3+d8 R7, R3 @RW3+d8 70 +3 60 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R2 @RW2+d8 R1, R2 @RW2+d8 R2, R2 @RW2+d8 R3, R2 @RW2+d8 R4, R2 @RW2+d8 R5, R2 @RW2+d8 R6, R2 @RW2+d8 R7, R2 @RW2+d8 50 +2 40 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R1 @RW1+d8 R1, R1 @RW1+d8 R2, R1 @RW1+d8 R3, R1 @RW1+d8 R4, R1 @RW1+d8 R5, R1 @RW1+d8 R6, R1 @RW1+d8 R7, R1 @RW1+d8 30 +1 20 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R0 @RW0+d8 R1, R0 @RW0+d8 R2, R0 @RW0+d8 R3, R0 @RW0+d8 R4, R0 @RW0+d8 R5, R0 @RW0+d8 R6, R0 @RW0+d8 R7, R0 @RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-16 MOV Ri, ea Instruction (First Byte = 7AH) MOVW MOVW RW5, RW5,@RW3 @RW3+d16 MOVW MOVW MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW0,@RW1 @RW1+d16 RW1,@RW1 @RW1+d16 RW2,@RW1 @RW1+d16 RW3,@RW1 @RW1+d16 RW4,@RW1 @RW1+d16 MOVW MOVW MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW0,@RW2 @RW2+d16 RW1,@RW2 @RW2+d16 RW2,@RW2 @RW2+d16 RW3,@RW2 @RW2+d16 RW4,@RW2 @RW2+d16 MOVW MOVW MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW0,@RW3 @RW3+d16 RW1,@RW3 @RW3+d16 RW2,@RW3 @RW3+d16 RW3,@RW3 @RW3+d16 RW4,@RW3 @RW3+d16 MOVW MOVW MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, MOVW MOVW RW5, MOVW MOVW RW6, MOVW MOVW RW7, RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, @RW2+ @PC+d16 RW2, @RW2+ @PC+d16 RW3, @RW2+ @PC+d16 RW4, @RW2+ @PC+d16 MOVW MOVW RW1, @RW3+ RW1, addr16 MOVW RW0, @RW1+ MOVW MOVW RW0, @RW2+ @PC+d16 MOVW MOVW RW0, @RW3+ RW0, addr16 +9 +A +B +C +D +E +F MOVW MOVW RW2, @RW3+ RW2, addr16 MOVW MOVW RW3, @RW3+ RW3, addr16 MOVW MOVW RW5, @RW3+ RW5, addr16 MOVW MOVW RW5, @RW2+ @PC+d16 MOVW MOVW RW6, @RW3+ RW6, addr16 MOVW MOVW RW6, RW6, @RW2+ @PC+d16 MOVW MOVW RW7, @RW3+ RW7, addr16 MOVW MOVW RW7, RW7, @RW2+ @PC+d16 MOVW RW7, @RW1+RW7 MOVW MOVW RW7, RW7,@RW3 @RW3+d16 MOVW MOVW RW7, RW7,@RW2 @RW2+d16 MOVW MOVW RW7, RW7,@RW1 @RW1+d16 MOVW MOVW RW7, RW7,@RW0 @RW0+d16 MOVW MOVW RW7, RW7, RW7 @RW7+d8 MOVW MOVW RW7, RW7, RW6 @RW6+d8 MOVW MOVW RW7, RW7, RW5 @RW5+d8 MOVW MOVW RW7, RW7, RW4 @RW4+d8 MOVW RW6, MOVW @RW1+RW7 RW7, @RW1+ MOVW MOVW RW6, RW6,@RW3 @RW3+d16 MOVW MOVW RW6, RW6,@RW2 @RW2+d16 MOVW MOVW RW6, RW6,@RW1 @RW1+d16 MOVW MOVW RW6, RW6,@RW0 @RW0+d16 MOVW MOVW RW6, RW6, RW7 @RW7+d8 MOVW MOVW RW6, RW6, RW6 @RW6+d8 MOVW MOVW RW6, RW6, RW5 @RW5+d8 MOVW MOVW RW6, RW6, RW4 @RW4+d8 MOVW MOVW @RW1+RW7 RW6, @RW1+ MOVW MOVW RW5, RW5, RW6 @RW6+d8 MOVW MOVW RW5, RW5, RW5 @RW5+d8 MOVW RW4, MOVW @RW1+RW7 RW5, @RW1+ MOVW MOVW RW4, @RW3+ RW4, addr16 MOVW RW3, MOVW @RW1+RW7 RW4, @RW1+ MOVW MOVW RW5, RW5,@RW2 @RW2+d16 MOVW MOVW MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW0,@RW0 @RW0+d16 RW1,@RW0 @RW0+d16 RW2,@RW0 @RW0+d16 RW3,@RW0 @RW0+d16 RW4,@RW0 @RW0+d16 +8 MOVW RW2, MOVW @RW1+RW7 RW3, @RW1+ MOVW MOVW RW5, RW5,@RW1 @RW1+d16 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW7 @RW7+d8 RW2, RW7 @RW7+d8 RW3, RW7 @RW7+d8 RW4, RW7 @RW7+d8 MOVW MOVW RW0, RW7 @RW7+d8 +7 MOVW RW1, MOVW @RW1+RW7 RW2, @RW1+ MOVW MOVW RW5, RW5,@RW0 @RW0+d16 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW6 @RW6+d8 RW2, RW6 @RW6+d8 RW3, RW6 @RW6+d8 RW4, RW6 @RW6+d8 MOVW MOVW RW0, RW6 @RW6+d8 +6 MOVW MOVW @RW1+RW7 RW1, @RW1+ MOVW MOVW RW5, RW5, RW7 @RW7+d8 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW5 @RW5+d8 RW2, RW5 @RW5+d8 RW3, RW5 @RW5+d8 RW4, RW5 @RW5+d8 MOVW MOVW RW0, RW5 @RW5+d8 +5 MOVW MOVW RW5, RW5, RW4 @RW4+d8 MOVW MOVW RW7, RW7, RW3 @RW3+d8 MOVW MOVW RW7, RW7, RW2 @RW2+d8 MOVW MOVW RW7, RW7, RW1 @RW1+d8 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW4 @RW4+d8 RW2, RW4 @RW4+d8 RW3, RW4 @RW4+d8 RW4, RW4 @RW4+d8 MOVW MOVW RW6, RW6, RW3 @RW3+d8 MOVW MOVW RW6, RW6, RW2 @RW2+d8 MOVW MOVW RW6, RW6, RW1 @RW1+d8 MOVW MOVW RW0, RW4 @RW4+d8 MOVW MOVW RW5, RW5, RW3 @RW3+d8 MOVW MOVW RW5, RW5, RW2 @RW2+d8 MOVW MOVW RW5, RW5, RW1 @RW1+d8 +4 F0 MOVW MOVW RW7, RW7, RW0 @RW0+d8 E0 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW3 @RW3+d8 RW2, RW3 @RW3+d8 RW3, RW3 @RW3+d8 RW4, RW3 @RW3+d8 D0 MOVW MOVW RW6, RW6, RW0 @RW0+d8 C0 MOVW MOVW RW0, RW3 @RW3+d8 B0 MOVW MOVW RW5, RW5, RW0 @RW0+d8 A0 +3 90 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW2 @RW2+d8 RW2, RW2 @RW2+d8 RW3, RW2 @RW2+d8 RW4, RW2 @RW2+d8 80 MOVW MOVW RW0, RW2 @RW2+d8 70 +2 60 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW1 @RW1+d8 RW2, RW1 @RW1+d8 RW3, RW1 @RW1+d8 RW4, RW1 @RW1+d8 50 MOVW MOVW RW0, RW1 @RW1+d8 40 +1 30 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW0 @RW0+d8 RW2, RW0 @RW0+d8 RW3, RW0 @RW0+d8 RW4, RW0 @RW0+d8 20 MOVW MOVW RW0, RW0 @RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-17 MOVW RWi, ea Instruction (First Byte = 7BH) 475 476 +F +E +D +C +B +A +9 +8 MOV MOV MOV MOV MOV MOV MOV MOV MOV @RW3+, R1 addr16, R1 MOV MOV @RW3+, R0 addr16, R0 MOV MOV MOV @RW2+, R1 @PC+d16, R1 @RW2+, R0 @PC+d16, R0 MOV MOV MOV MOV MOV @RW0+, R1 @RW0+RW7, R1 MOV @RW3, R1 @RW3+d16, R1 MOV @RW2, R1 @RW2+d16, R1 MOV @RW1, R1 @RW1+d16, R1 MOV @RW1+, R1 @RW1+RW7, R1 MOV MOV @RW0, R1 @RW0+d16, R1 MOV @RW1+, R0 @RW1+RW7, R0 MOV @RW0+, R0 @RW0+RW7, R0 MOV @RW3, R0 @RW3+d16, R0 MOV @RW2, R0 @RW2+d16, R0 MOV @RW1, R0 @RW1+d16, R0 MOV @RW0, R0 @RW0+d16, R0 MOV MOV MOV MOV MOV MOV MOV MOV MOV @RW3+, R2 addr16, R2 MOV @RW2+, R2 @PC+d16, R2 MOV @RW1+, R2 @RW1+RW7, R2 MOV @RW0+, R2 @RW0+RW7, R2 MOV @RW3, R2 @RW3+d16, R2 MOV @RW2, R2 @RW2+d16, R2 MOV @RW1, R2 @RW1+d16, R2 MOV @RW0, R2 @RW0+d16, R2 MOV MOV MOV MOV MOV MOV MOV MOV MOV @RW3+, R3 addr16, R3 MOV @RW2+, R3 @PC+d16, R3 MOV @RW1+, R3 @RW1+RW7, R3 MOV @RW0+, R3 @RW0+RW7, R3 MOV @RW3, R3 @RW3+d16, R3 MOV @RW2, R3 @RW2+d16, R3 MOV @RW1, R3 @RW1+d16, R3 MOV @RW0, R3 @RW0+d16, R3 MOV MOV MOV MOV MOV MOV MOV MOV MOV @RW3+, R4 addr16, R4 MOV @RW2+, R4 @PC+d16, R4 MOV @RW1+, R4 @RW1+RW7, R4 MOV @RW0+, R4 @RW0+RW7, R4 MOV @RW3, R4 @RW3+d16, R4 MOV @RW2, R4 @RW2+d16, R4 MOV @RW1, R4 @RW1+d16, R4 MOV @RW0, R4 @RW0+d16, R4 MOV MOV MOV MOV MOV MOV MOV MOV MOV @RW3+, R5 addr16, R5 MOV @RW2+, R5 @PC+d16, R5 MOV @RW1+, R5 @RW1+RW7, R5 MOV @RW0+, R5 @RW0+RW7, R5 MOV @RW3, R5 @RW3+d16, R5 MOV @RW2, R5 @RW2+d16, R5 MOV @RW1, R5 @RW1+d16, R5 MOV @RW0, R5 @RW0+d16, R5 MOV MOV MOV MOV MOV MOV MOV MOV MOV @RW3+, R6 addr16, R6 MOV @RW2+, R6 @PC+d16, R6 MOV @RW1+, R6 @RW1+RW7, R6 MOV @RW0+, R6 @RW0+RW7, R6 MOV @RW3, R6 @RW3+d16, R6 MOV @RW2, R6 @RW2+d16, R6 MOV @RW1, R6 @RW1+d16, R6 MOV @RW0, R6 @RW0+d16, R6 MOV MOV MOV MOV MOV MOV MOV MOV MOV @RW3+, R7 addr16, R7 MOV @RW2+, R7 @PC+d16, R7 MOV @RW1+, R7 @RW1+RW7, R7 MOV @RW0+, R7 @RW0+RW7, R7 MOV @RW3, R7 @RW3+d16, R7 MOV @RW2, R7 @RW2+d16, R7 MOV @RW1, R7 @RW1+d16, R7 MOV @RW0, R7 @RW0+d16, R7 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R7, R0 @RW7+d8, R0 R7, R1 @RW7+d8, R1 R7, R2 @RW7+d8, R2 R7, R3 @RW7+d8, R3 R7, R4 @RW7+d8, R4 R7, R5 @RW7+d8, R5 R7, R6 @RW7+d8, R6 R7, R7 @RW7+d8, R7 F0 +7 E0 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R6, R0 @RW6+d8, R0 R6, R1 @RW6+d8, R1 R6, R2 @RW6+d8, R2 R6, R3 @RW6+d8, R3 R6, R4 @RW6+d8, R4 R6, R5 @RW6+d8, R5 R6, R6 @RW6+d8, R6 R6, R7 @RW6+d8, R7 D0 +6 C0 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R5, R0 @RW5+d8, R0 R5, R1 @RW5+d8, R1 R5, R2 @RW5+d8, R2 R5, R3 @RW5+d8, R3 R5, R4 @RW5+d8, R4 R5, R5 @RW5+d8, R5 R5, R6 @RW5+d8, R6 R5, R7 @RW5+d8, R7 B0 +5 A0 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R4, R0 @RW4+d8, R0 R4, R1 @RW4+d8, R1 R4, R2 @RW4+d8, R2 R4, R3 @RW4+d8, R3 R4, R4 @RW4+d8, R4 R4, R5 @RW4+d8, R5 R4, R6 @RW4+d8, R6 R4, R7 @RW4+d8, R7 90 +4 80 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R3, R0 @RW3+d8, R0 R3, R1 @RW3+d8, R1 R3, R2 @RW3+d8, R2 R3, R3 @RW3+d8, R3 R3, R4 @RW3+d8, R4 R3, R5 @RW3+d8, R5 R3, R6 @RW3+d8, R6 R3, R7 @RW3+d8, R7 70 +3 60 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R2, R0 @RW2+d8, R0 R2, R1 @RW2+d8, R1 R2, R2 @RW2+d8, R2 R2, R3 @RW2+d8, R3 R2, R4 @RW2+d8, R4 R2, R5 @RW2+d8, R5 R2, R6 @RW2+d8, R6 R2, R7 @RW2+d8, R7 50 +2 40 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R1, R0 @RW1+d8, R0 R1, R1 @RW1+d8, R1 R1, R2 @RW1+d8, R2 R1, R3 @RW1+d8, R3 R1, R4 @RW1+d8, R4 R1, R5 @RW1+d8, R5 R1, R6 @RW1+d8, R6 R1, R7 @RW1+d8, R7 30 +1 20 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R0, R0 @RW0+d8, R0 R0, R1 @RW0+d8, R1 R0, R2 @RW0+d8, R2 R0, R3 @RW0+d8, R3 R0, R4 @RW0+d8, R4 R0, R5 @RW0+d8, R5 R0, R6 @RW0+d8, R6 R0, R7 @RW0+d8, R7 10 +0 00 APPENDIX B Instructions Table B.9-18 MOV ea, Ri Instruction (First Byte = 7CH) MOVW MOVW@RW2 @RW2, RW1 +d16, RW1 MOVW MOVW@RW3 @RW3, RW1 +d16, RW1 MOVW MOVW@RW0 @RW0+, RW1 +RW7,RW1 MOVW MOVW@RW1 @RW1+,RW1 +RW7,RW1 MOVW MOVW@PC @RW2+,RW1 +d16, RW1 MOVW MOVW @RW3+,RW1 addr16, RW1 MOVW MOVW@RW2 @RW2, RW0 +d16, RW0 MOVW MOVW@RW3 @RW3, RW0 +d16, RW0 MOVW MOVW@RW0 @RW0+,RW0 +RW7,RW0 MOVW MOVW@RW1 @RW1+,RW0 +RW7,RW0 MOVW MOVW@PC @RW2+,RW0 +d16, RW0 MOVW MOVW @RW3+,RW0 addr16, RW0 +B +C +D +E +F MOVW MOVW @RW3+,RW2 addr16, RW2 MOVW MOVW@PC @RW2+,RW2 +d16, RW2 MOVW MOVW@RW1 @RW1+,RW2 +RW7,RW2 MOVW MOVW@RW0 @RW0+,RW2 +RW7,RW2 MOVW MOVW@RW3 @RW3, RW2 +d16, RW2 MOVW MOVW@RW2 @RW2, RW2 +d16, RW2 MOVW MOVW @RW3+,RW3 addr16, RW3 MOVW MOVW@PC @RW2+,RW3 +d16, RW3 MOVW MOVW@RW1 @RW1+,RW3 -+RW7,RW3 MOVW MOVW@RW0 @RW0+,RW3 +RW7,RW3 MOVW MOVW@RW3 @RW3, RW3 +d16, RW3 MOVW MOVW@RW2 @RW2, RW3 +d16, RW3 MOVW MOVW@RW1 @RW1, RW3 +d16, RW3 MOVW MOVW @RW3+,RW4 addr16, RW4 MOVW MOVW@PC @RW2+,RW4 +d16, RW4 MOVW MOVW@RW1 @RW1+,RW4 +RW7,RW4 MOVW MOVW@RW0 @RW0+,RW4 +RW7,RW4 MOVW MOVW@RW3 @RW3, RW4 +d16, RW4 MOVW MOVW@RW2 @RW2, RW4 +d16, RW4 MOVW MOVW@RW1 @RW1, RW4 +d16, RW4 MOVW MOVW @RW3+,RW5 addr16, RW5 MOVW MOVW@PC @RW2+,RW5 +d16, RW5 MOVW MOVW@RW1 @RW1+,RW5 +RW7,RW5 MOVW MOVW@RW0 @RW0+,RW5 +RW7,RW5 MOVW MOVW@RW3 @RW3, RW5 +d16, RW5 MOVW MOVW@RW2 @RW2, RW5 +d16, RW5 MOVW MOVW@RW1 @RW1, RW5 +d16, RW5 MOVW MOVW @RW3+,RW6 addr16, RW6 MOVW MOVW @PC @RW2+,RW6 +d16, RW6 MOVW MOVW@RW1 @RW1+,RW6 +RW7,RW6 MOVW MOVW@RW0 @RW0+,RW6 +RW7,RW6 MOVW MOVW@RW3 @RW3, RW6 +d16, RW6 MOVW MOVW@RW2 @RW2, RW6 +d16, RW6 MOVW MOVW@RW1 @RW1, RW6 +d16, RW6 MOVW MOVW @RW3+,RW7 addr16, RW7 MOVW MOVW@PC @RW2+,RW7 +d16, RW7 MOVW MOVW@RW1 @RW1+,RW7 +RW7,RW7 MOVW MOVW@RW0 @RW0+,RW7 +RW7,RW7 MOVW MOVW@RW3 @RW3, RW7 +d16, RW7 MOVW MOVW@RW2 @RW2, RW7 +d16, RW7 MOVW MOVW@RW1 @RW1, RW7 +d16, RW7 MOVW MOVW@RW0 @RW0, RW7 +d16, RW7 +A MOVW MOVW@RW1 @RW1, RW2 +d16, RW2 MOVW MOVW@RW0 @RW0, RW6 +d16, RW6 MOVW MOVW@RW1 @RW1, RW1 +d16, RW1 MOVW MOVW@RW0 @RW0, RW5 +d16, RW5 MOVW MOVW@RW1 @RW1, RW0 +d16, RW0 MOVW MOVW@RW0 @RW0, RW4 +d16, RW4 +9 MOVW MOVW@RW0 @RW0, RW3 +d16, RW3 MOVW MOVW@RW0 @RW0, RW1 +d16, RW1 MOVW MOVW@RW0 @RW0, RW0 +d16, RW0 +8 MOVW MOVW@RW0 @RW0, RW2 +d16, RW2 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW7, RW0 @RW7+d8, RW0 RW7, RW1 @RW7+d8, RW1 RW7, RW2 @RW7+d8, RW2 RW7, RW3 @RW7+d8, RW3 RW7, RW4 @RW7+d8, RW4 RW7, RW5 @RW7+d8, RW5 RW7, RW6 @RW7+d8, RW6 RW7, RW7 @RW7+d8, RW7 F0 +7 E0 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW6, RW0 @RW6+d8, RW0 RW6, RW1 @RW6+d8, RW1 RW6, RW2 @RW6+d8, RW2 RW6, RW3 @RW6+d8, RW3 RW6, RW4 @RW6+d8, RW4 RW6, RW5 @RW6+d8, RW5 RW6, RW6 @RW6+d8, RW6 RW6, RW7 @RW6+d8, RW7 D0 +6 C0 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW5, RW0 @RW5+d8, RW0 RW5, RW1 @RW5+d8, RW1 RW5, RW2 @RW5+d8, RW2 RW5, RW3 @RW5+d8, RW3 RW5, RW4 @RW5+d8, RW4 RW5, RW5 @RW5+d8, RW5 RW5, RW6 @RW5+d8, RW6 RW5, RW7 @RW5+d8, RW7 B0 +5 A0 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW4, RW0 @RW4+d8, RW0 RW4, RW1 @RW4+d8, RW1 RW4, RW2 @RW4+d8, RW2 RW4, RW3 @RW4+d8, RW3 RW4, RW4 @RW4+d8, RW4 RW4, RW5 @RW4+d8, RW5 RW4, RW6 @RW4+d8, RW6 RW4, RW7 @RW4+d8, RW7 90 +4 80 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW3, RW0 @RW3+d8, RW0 RW3, RW1 @RW3+d8, RW1 RW3, RW2 @RW3+d8, RW2 RW3, RW3 @RW3+d8, RW3 RW3, RW4 @RW3+d8, RW4 RW3, RW5 @RW3+d8, RW5 RW3, RW6 @RW3+d8, RW6 RW3, RW7 @RW3+d8, RW7 70 +3 60 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW2, RW0 @RW2+d8, RW0 RW2, RW1 @RW2+d8, RW1 RW2, RW2 @RW2+d8, RW2 RW2, RW3 @RW2+d8, RW3 RW2, RW4 @RW2+d8, RW4 RW2, RW5 @RW2+d8, RW5 RW2, RW6 @RW2+d8, RW6 RW2, RW7 @RW2+d8, RW7 50 +2 40 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW1, RW0 @RW1+d8, RW0 RW1, RW1 @RW1+d8, RW1 RW1, RW2 @RW1+d8, RW2 RW1, RW3 @RW1+d8, RW3 RW1, RW4 @RW1+d8, RW4 RW1, RW5 @RW1+d8, RW5 RW1, RW6 @RW1+d8, RW6 RW1, RW7 @RW1+d8, RW7 30 +1 20 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW0, RW0 @RW0+d8, RW0 RW0, RW1 @RW0+d8, RW1 RW0, RW2 @RW0+d8, RW2 RW0, RW3 @RW0+d8, RW3 RW0, RW4 @RW0+d8, RW4 RW0, RW5 @RW0+d8, RW5 RW0, RW6 @RW0+d8, RW6 RW0, RW7 @RW0+d8, RW7 10 +0 00 APPENDIX B Instructions Table B.9-19 MOVW ea, Rwi Instruction (First Byte = 7DH) 477 478 XCH XCH XCH XCH R1, XCH XCH R1, R1,@RW2 W2+d16, A XCH XCH R2, XCH XCH R2, R2,@RW2 W2+d16, A XCH XCH R3, XCH XCH R3, R3,@RW2 W2+d16, A XCH XCH R4, XCH XCH R4, R4,@RW2 W2+d16, A XCH XCH R5, XCH XCH R5, R5,@RW2 W2+d16, A XCH XCH R6, XCH XCH R6, R6,@RW2 W2+d16, A XCH XCH R7, XCH XCH R7, R7,@RW2 W2+d16, A XCH XCH XCH XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, +F R0,@RW3+ R0, addr16 XCH XCH R1,@RW3+ R1, addr16 XCH XCH R2,@RW3+ R2, addr16 XCH XCH R3,@RW3+ R3, addr16 XCH XCH R4,@RW3+ R4, addr16 XCH XCH R5,@RW3+ R5, addr16 XCH XCH R6,@RW3+ R6, addr16 XCH XCH R7,@RW3+ R7, addr16 +E R0,@RW2+ @PC+d16 R1,@RW2+ @PC+d16 R2,@RW2+ @PC+d16 R3,@RW2+ @PC+d16 R4,@RW2+ @PC+d16 R5,@RW2+ @PC+d16 R6,@RW2+ @PC+d16 R7,@RW2+ @PC+d16 R0, XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, @RW1+RW7 R1,@RW1+ @RW1+RW7 R2,@RW1+ @RW1+RW7 R3,@RW1+ @RW1+RW7 R4,@RW1+ @RW1+RW7 R5,@RW1+ @RW1+RW7 R6,@RW1+ @RW1+RW7 R7,@RW1+ @RW1+RW7 +D R0,@RW1+ XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, @RW0+RW7 R1,@RW0+ @RW0+RW7 R2,@RW0+ @RW0+RW7 R3,@RW0+ @RW0+RW7 R4,@RW0+ @RW0+RW7 R5,@RW0+ @RW0+RW7 R6,@RW0+ @RW0+RW7 R7,@RW0+ @RW0+RW7 XCH +C R0,@RW0+ +B R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16 R0, +A R0,@RW2 W2+d16, A R0, XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16 +9 XCH XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16 +8 XCH XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R7 @RW7+d8 R1, R7 @RW7+d8 R2, R7 @RW7+d8 R3, R7 @RW7+d8 R4, R7 @RW7+d8 R5, R7 @RW7+d8 R6, R7 @RW7+d8 R7, R7 @RW7+d8 F0 +7 E0 XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R6 @RW6+d8 R1, R6 @RW6+d8 R2, R6 @RW6+d8 R3, R6 @RW6+d8 R4, R6 @RW6+d8 R5, R6 @RW6+d8 R6, R6 @RW6+d8 R7, R6 @RW6+d8 D0 +6 C0 XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R5 @RW5+d8 R1, R5 @RW5+d8 R2, R5 @RW5+d8 R3, R5 @RW5+d8 R4, R5 @RW5+d8 R5, R5 @RW5+d8 R6, R5 @RW5+d8 R7, R5 @RW5+d8 B0 +5 A XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R4 @RW4+d8 R1, R4 @RW4+d8 R2, R4 @RW4+d8 R3, R4 @RW4+d8 R4, R4 @RW4+d8 R5, R4 @RW4+d8 R6, R4 @RW4+d8 R7, R4 @RW4+d8 90 +4 80 XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R3 @RW3+d8 R1, R3 @RW3+d8 R2, R3 @RW3+d8 R3, R3 @RW3+d8 R4, R3 @RW3+d8 R5, R3 @RW3+d8 R6, R3 @RW3+d8 R7, R3 @RW3+d8 70 +3 60 XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R2 @RW2+d8 R1, R2 @RW2+d8 R2, R2 @RW2+d8 R3, R2 @RW2+d8 R4, R2 @RW2+d8 R5, R2 @RW2+d8 R6, R2 @RW2+d8 R7, R2 @RW2+d8 50 +2 40 XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R1 @RW1+d8 R1, R1 @RW1+d8 R2, R1 @RW1+d8 R3, R1 @RW1+d8 R4, R1 @RW1+d8 R5, R1 @RW1+d8 R6, R1 @RW1+d8 R7, R1 @RW1+d8 30 +1 20 XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R0 @RW0+d8 R1, R0 @RW0+d8 R2, R0 @RW0+d8 R3, R0 @RW0+d8 R4, R0 @RW0+d8 R5, R0 @RW0+d8 R6, R0 @RW0+d8 R7, R0 @RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-20 XCH Ri, ea Instruction (First Byte = 7EH) XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0,@RW2+ @PC+d16 RW1,@RW2+ @PC+d16 RW2,@RW2+ @PC+d16 RW3,@RW2+ @PC+d16 RW4,@RW2+ @PC+d16 RW5,@RW2+ @PC+d16 RW6,@RW2+ @PC+d16 RW7,@RW2+ @PC+d16 XCHW XCHW RW0,@RW3+ RW0, addr16 +E +F XCHW XCHW RW7,@RW3+ RW7, addr16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0,@RW1+ @RW1+RW7 RW1,@RW1+ @RW1+RW7 RW2,@RW1+ @RW1+RW7 RW3,@RW1+ @RW1+RW7 RW4,@RW1+ @RW1+RW7 RW5,@RW1+ @RW1+RW7 RW6,@RW1+ @RW1+RW7 RW7,@RW1+ @RW1+RW7 +D XCHW XCHW RW6,@RW3+ RW6, addr16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7 +C XCHW XCHW RW5,@RW3+ RW5, addr16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0,@RW3 @RW3+d16 RW1,@RW3 @RW3+d16 RW2,@RW3 @RW3+d16 RW3,@RW3 @RW3+d16 RW4,@RW3 @RW3+d16 RW5,@RW3 @RW3+d16 RW6,@RW3 @RW3+d16 RW7,@RW3 @RW3+d16 +B XCHW XCHW RW4,@RW3+ RW4, addr16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0,@RW2 @RW2+d16 RW1,@RW2 @RW2+d16 RW2,@RW2 @RW2+d16 RW3,@RW2 @RW2+d16 RW4,@RW2 @RW2+d16 RW5,@RW2 @RW2+d16 RW6,@RW2 @RW2+d16 RW7,@RW2 @RW2+d16 +A XCHW XCHW RW3,@RW3+ RW3, addr16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0,@RW1 @RW1+d16 RW1,@RW1 @RW1+d16 RW2,@RW1 @RW1+d16 RW3,@RW1 @RW1+d16 RW4,@RW1 @RW1+d16 RW5,@RW1 @RW1+d16 RW6,@RW1 @RW1+d16 RW7,@RW1 @RW1+d16 +9 XCHW XCHW RW2,@RW3+ RW2, addr16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0,@RW0 @RW0+d16 RW1,@RW0 @RW0+d16 RW2,@RW0 @RW0+d16 RW3,@RW0 @RW0+d16 RW4,@RW0 @RW0+d16 RW5,@RW0 @RW0+d16 RW6,@RW0 @RW0+d16 RW7,@RW0 @RW0+d16 +8 XCHW XCHW RW1,@RW3+ RW1, addr16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW7 @RW7+d8 RW1, RW7 @RW7+d8 RW2, RW7 @RW7+d8 RW3, RW7 @RW7+d8 RW4, RW7 @RW7+d8 RW5, RW7 @RW7+d8 RW6, RW7 @RW7+d8 RW7, RW7 @RW7+d8 F0 +7 E0 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW6 @RW6+d8 RW1, RW6 @RW6+d8 RW2, RW6 @RW6+d8 RW3, RW6 @RW6+d8 RW4, RW6 @RW6+d8 RW5, RW6 @RW6+d8 RW6, RW6 @RW6+d8 RW7, RW6 @RW6+d8 D0 +6 C0 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW5 @RW5+d8 RW1, RW5 @RW5+d8 RW2, RW5 @RW5+d8 RW3, RW5 @RW5+d8 RW4, RW5 @RW5+d8 RW5, RW5 @RW5+d8 RW6, RW5 @RW5+d8 RW7, RW5 @RW5+d8 B0 +5 A0 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW4 @RW4+d8 RW1, RW4 @RW4+d8 RW2, RW4 @RW4+d8 RW3, RW4 @RW4+d8 RW4, RW4 @RW4+d8 RW5, RW4 @RW4+d8 RW6, RW4 @RW4+d8 RW7, RW4 @RW4+d8 90 +4 80 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW3 @RW3+d8 RW1, RW3 @RW3+d8 RW2, RW3 @RW3+d8 RW3, RW3 @RW3+d8 RW4, RW3 @RW3+d8 RW5, RW3 @RW3+d8 RW6, RW3 @RW3+d8 RW7, RW3 @RW3+d8 70 +3 60 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW2 @RW2+d8 RW1, RW2 @RW2+d8 RW2, RW2 @RW2+d8 RW3, RW2 @RW2+d8 RW4, RW2 @RW2+d8 RW5, RW2 @RW2+d8 RW6, RW2 @RW2+d8 RW7, RW2 @RW2+d8 50 +2 40 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW1 @RW1+d8 RW1, RW1 @RW1+d8 RW2, RW1 @RW1+d8 RW3, RW1 @RW1+d8 RW4, RW1 @RW1+d8 RW5, RW1 @RW1+d8 RW6, RW1 @RW1+d8 RW7, RW1 @RW1+d8 30 +1 20 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW0 @RW0+d8 RW1, RW0 @RW0+d8 RW2, RW0 @RW0+d8 RW3, RW0 @RW0+d8 RW4, RW0 @RW0+d8 RW5, RW0 @RW0+d8 RW6, RW0 @RW0+d8 RW7, RW0 @RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-21 XCHW RWi, ea Instruction (First Byte = 7FH) 479 APPENDIX C Timing Diagrams in Flash Memory Mode APPENDIX C Timing Diagrams in Flash Memory Mode Each timing diagram for the external pins of the MB90F598/F598G in the Flash Memory mode is shown below. ■ Data Read by Read Access Figure C-1 Timing Diagram for Read Access tRC Address stable AQ16 to AQ0 tACC CE tDF tOE OE tOEH WE tOH tCE High impedance High impedance DQ7 to DQ0 Output defined ■ Write, Data Polling, Read (WE Control) Figure C-2 Write Data Polling Read (WE Control) Third bus cycle AQ18 to AQ0 Data polling 7AAAAH PA tWC tAS PA tRC tAH CE tGHWL OE tWP tWHWH1 WE tCS DQ7 to DQ0 tOE tWPH tDF tDH A0H PD DQ7 DOUT tDS tOH 5.0 V PA: Write address PD: Write data DQ7: Reverse output of write data DOUT: Output of write data tCE Note: The last two bus cycle sequences out of the four are described. 480 APPENDIX C Timing Diagrams in Flash Memory Mode ■ Write, Data Polling, Read (CE Control) Figure C-3 Timing Diagram for Write Access (CE Control) Third bus cycle Data polling 7AAAAH AQ18 to AQ0 PA tWC tAS PA tAH tWH WE tGHWL OE tCP tWHWH1 CE tCPH tWS tDH A0H PD DQ7 DOUT DQ7 to DQ0 tDS 5.0 V PA: Write address PD: Write data DQ7: Reverse output of write data DOUT: Output of write data Note: The last two bus cycle sequences out of the four are described. ■ Chip Erase/Sector Erase Command Sequence Figure C-4 Timing Diagram for Write Access (Chip Erasing/Sector Erasing) tAS AQ18 to AQ0 7AAAAH tAH 75555H 7AAAAH 7AAAAH 75555H SA* CE tGHWL OE tWP WE tWPH tCS DQ7 to DQ0 tDH AAH 55H 80H AAH 55H 10H/30H tDS VCC tVCS * : SA is the sector address at sector erasing. 7AAAAH (or 6AAAAH) is the address at chip erasing. 481 APPENDIX C Timing Diagrams in Flash Memory Mode ■ Data Polling Figure C-5 Timing Diagram for Data Polling tCH CE tOE tDF OE tOEH WE tCE DQ7 tOH * DQ7 = Valid data DQ7 High impedance tWHWH1 or tWHWH2 DQ6 to DQ0 DQ6toDQ0 = Valid data DQ6 to DQ0 = Invalid tOE * : DQ7 is valid data (The device terminates automatic operation). ■ Toggle Bit Figure C-6 Timing Diagram for Toggle Bit CE tOE H WE tOES OE * Data (DQ7 to DQ0) DQ6 = Toggle DQ6 = Toggle * : DQ6 stops toggling (The device terminates automatic operation). DQ6 = Stop toggling DQ7 to DQ0=Valid tOE ■ RY/BY Timing During Writing/Erasing Figure C-7 Timing Diagram for Output of RY/BY Signal during Writing/Erasing CE Rising edge of last write pulse WE Writing or erasing RY/BY tBUSY 482 APPENDIX C Timing Diagrams in Flash Memory Mode ■ RST and RY/BY Timing Figure C-8 Timing Diagram for Output of RY/BY Signal at Hardware Reset CE RY/BY tRP RST tReady ■ Enable Sector Protect/Verify Sector Protect Figure C-9 Enable Sector Protect/Verify Sector Protect AQ18 to AQ9 SAx AQ8, AQ2, and AQ1 SAy (AQ8, AQ2, AQ1) = (0, 1, 0) MD0 12 V 5V MD2 12 V 5V tVLHT tVLHT OE WE tWPP tOESP CE tCSP DQ7 to DQ0 01H SAx: First sector address SAy: Next sector address tOE 483 APPENDIX C Timing Diagrams in Flash Memory Mode ■ Temporary Sector Protect Cancellation Figure C-10 Temporary Sector Protect Cancellation Write or erase command sequence 484 APPENDIX D List of MB90595 Interrupt Vectors APPENDIX D List of MB90595 Interrupt Vectors The interrupt vector table to be referenced for interrupt processing is allocated to FFFC00H to FFFFFFH in the memory area and also used for software interrupts. ■ List of MB90595 Interrupt Vectors Table D-1 lists the interrupt vectors for the MB90595 series. Table D-1 MB90595 Interrupt Vectors (1/2) Software interrupt instruction Vector address L Vector address M Vector address H Mode register Interrupt No. Hardware interrupt INT 0 FFFFECH FFFFEDH FFFFEEH Unused #0 None . . . . . . . . . . . . . . . . . . . . . INT 7 FFFFE0H FFFFE1H FFFFE2H Unused #7 None INT 8 FFFFDCH FFFFDDH FFFFDEH FFFFDF #8 (RESET vector) INT 9 FFFFD8H FFFFD9H FFFFDAH Unused #9 ROM correction INT 10 FFFFD4H FFFFD5H FFFFD6H Unused #10 <Exception> INT 11 FFFFD0H FFFFD1H FFFFD2H Unused #11 CAN RX INT 12 FFFFCCH FFFFCDH FFFFCEH Unused #12 CAN TX/NS INT 13 FFFFC8H FFFFC9H FFFFCAH Unused #13 External interrupt INT0/INT1 INT 14 FFFFC4H FFFFC5H FFFFC6H Unused #14 Time base timer INT 15 FFFFC0H FFFFC1H FFFFC2H Unused #15 16-bit reload timer 0 INT 16 FFFFBCH FFFFBDH FFFFBEH Unused #16 A/D converter INT 17 FFFFB8H FFFFB9H FFFFBAH Unused #17 Input/output timer INT 18 FFFFB4H FFFFB5H FFFFB6H Unused #18 External interrupt INT2/INT3 INT 19 FFFFB0H FFFFB1H FFFFB2H Unused #19 Serial I/O INT 20 FFFFACH FFFFADH FFFFAEH Unused #20 External interrupt INT4/INT5 INT 21 FFFFA8H FFFFA9H FFFFAAH Unused #21 Input capture 0 INT 22 FFFFA4H FFFFA5H FFFFA6H Unused #22 PPG 0/1 INT 23 FFFFA0H FFFFA1H FFFFA2H Unused #23 Output compare 0 INT 24 FFFF9CH FFFF9DH FFFF9EH Unused #24 PPG 2/3 485 APPENDIX D List of MB90595 Interrupt Vectors Table D-1 MB90595 Interrupt Vectors (2/2) Software interrupt instruction Vector address L Vector address M Vector address H Mode register Interrupt No. INT 25 FFFF98H FFFF99H FFFF9AH Unused #25 External interrupt INT6/INT7 INT 26 FFFF94H FFFF95H FFFF96H Unused #26 Input capture 1 INT 27 FFFF90H FFFF91H FFFF92H Unused #27 PPG 4/5 INT 28 FFFF8CH FFFF8DH FFFF8EH Unused #28 Output compare 1 INT 29 FFFF88H FFFF89H FFFF8AH Unused #29 PPG 6/7 INT 30 FFFF84H FFFF85H FFFF86H Unused #30 Input capture 2 INT 31 FFFF80H FFFF81H FFFF82H Unused #31 PPG 8/9 INT 32 FFFF7CH FFFF7DH FFFF7EH Unused #32 Output compare 2 INT 33 FFFF78H FFFF79H FFFF7AH Unused #33 Input capture 3 INT 34 FFFF74H FFFF75H FFFF76H Unused #34 PPG A/B INT 35 FFFF70H FFFF71H FFFF72H Unused #35 Output compare 3 INT 36 FFFF6CH FFFF6DH FFFF6EH Unused #36 16-bit reload timer 1 INT 37 FFFF68H FFFF69H FFFF6AH Unused #37 UART 0 RX INT 38 FFFF64H FFFF65H FFFF66H Unused #38 UART 0 TX INT 39 FFFF60H FFFF61H FFFF62H Unused #39 UART 1 RX INT 40 FFFF5CH FFFF5DH FFFF5EH Unused #40 UART 1 TX INT 41 FFFF58H FFFF59H FFFF5AH Unused #41 Flash memory INT 42 FFFF54H FFFF55H FFFF56H Unused #42 Delayed interrupt INT 43 FFFF50H FFFF51H FFFF52H Unused #43 None . . . . . . . . . . . . . . . . . . INT 254 FFFC04H FFFC05H FFFC06H Unused #254 None INT 255 FFFC00H FFFC01H FFFC02H Unused #255 None 486 Hardware interrupt . . . APPENDIX D List of MB90595 Interrupt Vectors ■ Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers Table D-2 summarizes the relationships among the interrupt causes, interrupt vectors, and interrupt control registers of the MB90595 series. Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers Interrupt cause EI2OS clear Reset INT9 instruction Exception CAN RX CAN TX/NS External interrupt INT0/INT1 Time base timer 16-bit reload timer 0 A/D converter Input/output timer External interrupt INT2/INT3 Serial I/O External interrupt INT4/INT5 Input capture 0 PPG 0/1 Output compare 0 PPG2/3 External interrupt INT6/INT7 Input capture 1 PPG 4/5 Output compare 1 PPG 6/7 Input capture 2 PPG 8/9 Output compare 2 Input capture 3 PPG A/B Output compare 3 16-bit reload timer 1 UART 0 RX UART 0 TX UART 1 RX UART 1 TX Flash memory Delayed interrupt N N N N N Y1 N Y1 Y1 N Y1 Y1 Y1 Y1 N Y1 N Y1 Y1 N Y1 N Y1 N Y1 Y1 N Y1 Y1 Y2 Y1 Y2 Y1 × × Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 34 35 36 37 38 39 40 41 42 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register Number Address — — — — — — ICR00 0000B0H ICR01 0000B1H ICR02 0000B2H ICR03 0000B3H ICR04 0000B4H ICR05 0000B5H ICR06 0000B6H ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH Y1: An EI2OS interrupt clear signal or EI2OS register read access clears the interrupt request flag. Y2: An EI2OS interrupt clear signal or EI2OS register read access clears the interrupt request flag. A stop request is issued. x: An EI2OS interrupt clear signal does not clear the interrupt request flag. 487 APPENDIX D List of MB90595 Interrupt Vectors Note: For a peripheral module having two interrupt causes for one interrupt number, an EI2OS interrupt clear signal clears both interrupt request flags. When EI2OS ends, an EI2OS clear signal is sent to every interrupt flag assigned to each interrupt number. EI2OS is activated when one of two interrupts assigned to an interrupt control register (ICR) is caused while EI2OS is enabled. This means that an EI2OS descriptor that should essentially be specific to each interrupt cause is shared by two interrupts. Therefore, while one interrupt is enabled, the other interrupt must be disabled. 488 INDEX INDEX The index follows on the next page. This is listed in alphabetic order. 489 INDEX Index Numerics 16-bit Free-run Timer 16-bit Free-run Timer ............................... 122, 124 16-bit Free-run Timer Block Diagram ................ 125 16-bit Free-run Timer Timing............................ 130 Operation of 16-bit Free-run Timer .................... 129 16-bit I/O Timer 16-bit I/O Timer Block Diagram........................ 123 16-bit Input Capture 16-bit Input Capture ......................................... 124 16-bit Output Compare 16-bit Output Compare ..................................... 124 16-bit Reload Register Register Layout of 16-bit Timer Register (TMR)/ 16-bit Reload Register (TMRLR).......... 151 16-bit Reload Timer Block Diagram of 16-bit Reload Timer............... 146 Input Pin Functions of 16-bit Reload Timer (for Internal Clock Mode) .................... 152 Internal Clock Operation of 16-bit Reload Timer .......................................................... 152 Outline of 16-bit Reload Timer (With Event Count Function)............... 146 Output Pin Functions of 16-bit Reload Timer .......................................................... 155 Registers of 16-bit Reload Timer ....................... 147 Underflow Operation of 16-bit Reload Timer .......................................................... 154 16-bit Timer Register Register Layout of 16-bit Timer Register (TMR)/ 16-bit Reload Register (TMRLR).......... 151 1M-bit Flash Memory 1M-bit Flash Memory Features.......................... 358 Example of the 1M-bit Flash Memory Program .......................................................... 390 Sector Configuration of the 1M-bit Flash Memory .......................................................... 360 2 Channels Per One Module Input Capture (2 Channels Per One Module) .......................................................... 123 Output Compare (2 Channels Per One Module) .......................................................... 122 24-bit Operand 24-bit Operand Specification ............................... 23 8/16-bit PPG 8/16-bit PPG Block Diagram ............................. 159 8/16-bit PPG Functions..................................... 158 8/16-bit PPG Operation..................................... 169 8/16-bit PPG Output Operation.......................... 170 490 8/16-bit PPG Registers ..................................... 161 Count Clock Selection of 8/16-bit PPG .............. 171 Default Values of Hardware Components of 8/16-bit PPG....................................... 174 Interrupts of 8/16-bit PPG................................. 173 Pulse Pin Output Control of 8/16-bit PPG .......... 172 Relationship between 8/16-bit PPG Reload Value and Pulse Width........................................ 170 INDEX A A Accumulator (A)................................................ 30 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions ................. 41 Use of the "DIV A, Ri" and "DIVW A, RWi" Instructions without Precautions ............. 42 A/D Converter A/D Converter Block Diagram .......................... 190 A/D Converter Registers................................... 191 Features of A/D Converter ................................ 188 A/D Converter Register A/D Converter Registers................................... 191 Acceptance Filter Acceptance Filtering ........................................ 325 Setting Acceptance Filter .................................. 328 Acceptance Mask Register Acceptance Mask Registers 0 and 1 (AMR0/AMR1) .......................................................... 315 Acceptance Mask Select Register Acceptance Mask Select Register (AMSR)......... 313 Access Accessing Multi-byte Data.................................. 26 Data Read by Read Access................................ 480 Memory Access Modes .................................... 102 Note of Low-power Mode Control Register Access ............................................................ 92 Accumulator Accumulator (A)................................................ 30 Activating Activating the Watch-dog Timer ....................... 120 Activation Example of EI2OS Activation in Continuous Mode .......................................................... 204 Example of EI2OS Activation in Single Mode .......................................................... 202 Example of EI2OS Activation in Stop Mode .......................................................... 206 ADCR Data Registers (ADCR0, ADCR1)..................... 197 ADCS Control Status Register (ADCS1) ...................... 195 Control Status Registers (ADCS0) ..................... 192 Address Field Effective Address Field ............................ 422, 440 Address Generation Address Generation Types .................................. 21 Address Match Detection Function Block Diagram of the Address Match Detection Function............................................. 346 Operation of the Address Match Detection Function .......................................................... 349 System Configuration Example of the Address Match Detection Function .............................. 350 Addressing Addressing.......................................................421 Bank Addressing Types.......................................24 Direct Addressing .............................................423 Indirect Addressing...........................................429 Alternative Mode Alternative Mode..............................................362 AMR Acceptance Mask Registers 0 and 1 (AMR0/AMR1) ..........................................................315 AMSR Acceptance Mask Select Register (AMSR) .........313 Analog Input Enable Register Analog Input Enable Register ....................112, 188 Application Example UART0 Application Example ............................234 Asynchronous Asynchronous (Start-Stop Synchronized) Mode Data Transfer Format...................................252 Asynchronous (Start-Stop Synchronized) Mode Receive Operation ...............................252 Asynchronous (Start-Stop Synchronized) Mode Transmit Operation ..............................252 CLK Asynchronous Baud Rate ..........................223 B Bank Addressing Types Bank Addressing Types.......................................24 Bank Select Prefix Bank Select Prefix ..............................................38 BAP Buffer Address Pointer (BAP) .............................63 Basic Configuration Basic Configuration of F2MC-16LX MB90F598/ F598G Serial Programming Connection ..........................................................396 Baud Rate CLK Asynchronous Baud Rate ..........................223 CLK Synchronous Baud Rate ............................223 Bit Timing Setting Bit Timing ............................................328 Bit Timing Register Bit Timing Register (BTR) ................................298 Block Diagram 16-bit Free-run Timer Block Diagram.................125 16-bit I/O Timer Block Diagram ........................123 8/16-bit PPG Block Diagram .............................159 A/D Converter Block Diagram...........................190 Block Diagram .....................................................5 Block Diagram of 16-bit Reload Timer ...............146 Block Diagram of Delayed Interrupt.....................72 Block Diagram of DTP/External Interrupts .........178 Block Diagram of Low-power Control Circuit ............................................................85 491 INDEX Block Diagram of ROM Mirroring Function Selection Module............................................... 354 Block Diagram of the Address Match Detection Function ............................................. 346 Block Diagram of the Entire Flash Memory........ 360 Block Diagram of Time-base Timer ................... 114 Block Diagram of UART0 ................................ 213 CAN Controller Block Diagram......................... 281 Input Capture Block Diagram ............................ 139 Output Compare Block Diagram........................ 131 Serial I/O Block Diagram.................................. 262 Stepping Motor Controller Block Diagram ......... 338 UART1 Block Diagram .................................... 239 Watch-dog Timer Block Diagram ...................... 118 BTR Bit Timing Register (BTR)................................ 298 Buffer Address Pointer Buffer Address Pointer (BAP) ............................. 63 Bus Mode Setting Bits Bus Mode Setting Bits ...................................... 105 Bus Operation Stop Conditions for Canceling Bus Operation Stop (HALT=0) .......................................... 294 Conditions for Setting Bus Operation Stop (HALT=1) .......................................................... 294 State during Bus Operation Stop (HALT=1) .......................................................... 294 BVAL Caution for Disabling Message Buffers by BVAL Bits .......................................................... 336 BVALR Message Buffer Valid Register (BVALR)........... 301 C Calculating Calculating the Execution Cycle Count .............. 438 CAN Controller CAN Controller Block Diagram......................... 281 CAN Controller Reception Flowchart................. 327 CAN Controller Transmission Flowchart............ 324 Canceling a CAN Controller Transmission Request .......................................................... 323 Completing CAN Controller Transmission ......... 324 Features of CAN Controller............................... 280 Canceling Canceling a CAN Controller Transmission Request .......................................................... 323 Conditions for Canceling Bus Operation Stop (HALT=0) .......................................... 294 Cancellation Delayed Interrupt Cause Issuance/Cancellation Register (DIRR: Delayed Interrupt Request Register)............................................... 73 Temporary Sector Protect Cancellation............... 484 492 Capture Input Input Capture Input Timing............................... 143 Caution Caution for Disabling Message Buffers by BVAL Bits ......................................................... 336 CCR Condition Code Register (CCR) .......................... 32 CDCR UART1 Prescaler Control Register (U1CDCR) ......................................................... 248 CE Control Write, Data Polling, Read (CE Control) ............. 481 Change Flag Change Disable Prefix (NCC) ...................... 39 Channels Input Capture (2 Channels Per One Module) ......................................................... 123 Output Compare (2 Channels Per One Module) ......................................................... 122 Chip Erase Chip Erase/Sector Erase Command Sequence ......................................................... 481 CKSCR Clock Selection Register (CKSCR)...................... 89 Clearing Clearing the Counter by an Overflow................. 129 Clearing the Counter Upon a Match with Output Compare Register 0............................. 130 CLK Asynchronous Baud Rate CLK Asynchronous Baud Rate.......................... 223 CLK Synchronous Baud Rate CLK Synchronous Baud Rate............................ 223 CLK Synchronous Mode CLK Synchronous Mode Data Transfer Format ......................................................... 253 Control Register Settings for CLK Synchronous Mode ......................................................... 254 End of Communication in CLK Synchronous Mode ......................................................... 254 Start of Communication in CLK Synchronous Mode ......................................................... 254 Clock Frequency Oscillating Clock Frequency and Serial Clock Input Frequency .......................................... 399 Clock Generator Note of Clock Generator..................................... 76 Clock Mode External Shift Clock Mode................................ 271 Clock Selection Clock Selection Register (CKSCR)...................... 89 Count Clock Selection of 8/16-bit PPG .............. 171 Status Transition of Clock Selection .................. 100 UART1 Clock Selection ................................... 249 INDEX Clock Selection Register Clock Selection Register (CKSCR)...................... 89 CMR Common Register Bank Prefix (CMR)................. 39 Command Sequence Chip Erase/Sector Erase Command Sequence .......................................................... 481 Command Sequence Table................................ 366 Common Register Bank Prefix Common Register Bank Prefix (CMR)................. 39 Communication End of Communication in CLK Synchronous Mode .......................................................... 254 Start of Communication in CLK Synchronous Mode .......................................................... 254 UART1 Communication Flow Chart.................. 259 Completing Completing CAN Controller Transmission ......... 324 Completing Reception Completing Reception ...................................... 326 Condition Conditions for Canceling Bus Operation Stop (HALT=0).......................................... 294 Conditions for Setting Bus Operation Stop (HALT=1) .......................................................... 294 Condition Code Register Condition Code Register (CCR) .......................... 32 Configuration Basic Configuration of F2MC-16LX MB90F598/ F598G Serial Programming Connection .......................................................... 396 Sector Configuration of the 1M-bit Flash Memory .......................................................... 360 Setting Configuration of Multi-level Message Buffer .......................................................... 334 System Configuration Example of the Address Match Detection Function .............................. 350 UART1 Sample Application (System Configuration in Mode 1)......................................... 259 Consecutive Prefix Codes Consecutive Prefix Codes ................................... 40 Continuous Mode Continuous Mode............................................. 199 Example of EI2OS Activation in Continuous Mode .......................................................... 204 Control Register Control Register Settings for CLK Synchronous Mode .......................................................... 254 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers ................................ 487 Interrupt Control Register (ICR) .......................... 48 List of Total Control Registers .......................... 282 Low-power Mode Control Register (LPMCR) ............................................................ 87 Message Buffer Control Registers ..................... 290 Note of Low-power Mode Control Register Access ............................................................92 PPG0 Operation Mode Control Register (PPGC0) ..........................................................162 PPG0, 1 Output Pin Control Register (PPG01) ..........................................................166 PPG1 Operation Mode Control Register (PPGC1) ..........................................................164 Serial Control Register 1 (SCR1) .......................243 Serial Mode Control Register 0 (UMC0).............215 Time-base Timer Control Register (TBTC) .........115 Total Control Registers .....................................290 UART1 Prescaler Control Register (U1CDCR) ..........................................................248 Watch-dog Timer Control Register (WDTC) ..........................................................118 Control Signals Flash Memory Control Signals...........................363 Control Status Register Control Status Register......................................127 Control Status Register (ADCS1) .......................195 Control Status Register (CSR) ...........................291 Control Status Register of Output Compare ..........................................................133 Control Status Registers (ADCS0) .....................192 Flash Memory Control Status Register (FMCS) ..........................................................364 Input Capture Control Status Register.................140 Program Address Detection Control Status Register (PACSR) ............................................347 Serial Mode Control Status Register (SMCS) ..........................................................264 Structure of Timer Control Status Register (TMCSR) ..........................................................148 Conversion Conversion Data Protection ...............................208 Conversion Using EI2OS...................................201 Count Clock Count Clock Selection of 8/16-bit PPG ...............171 Counter Clearing the Counter by an Overflow .................129 Clearing the Counter Upon a Match with Output Compare Register 0 .............................130 Counter Operation State ....................................156 Data Counter (DCT) ...........................................62 External Event Counter .....................................153 Program Counter (PC).........................................35 Time-base Counter ...........................................116 Watch-dog Counter...........................................120 Counter Operation State Counter Operation State ....................................156 CPU Intermittent CPU Operation .................................98 Outline of CPU...................................................20 Outline of CPU Memory Space............................21 493 INDEX CSR Control Status Register (CSR) ........................... 291 Cycle Count Calculating the Execution Cycle Count .............. 438 Execution Cycle Count ..................................... 437 D Data Counter Data Counter (DCT) ........................................... 62 Data Format Transfer Data Format........................................ 227 Data Frame Processing for Reception of Data Frame and Remote Frame..................................... 326 Data Polling Data Polling..................................................... 482 Data Polling Flag (DQ7) ................................... 370 Write, Data Polling, Read (CE Control).............. 481 Write, Data Polling, Read (WE Control)............. 480 Data Protection Conversion Data Protection............................... 208 Flow of Data Protection Function (When EI2OS is Used) ......................... 209 Data Read Data Read by Read Access ................................ 480 Data Register Data Register ................................................... 126 Data Register x (x=0 to 15) (DTRx) ................... 321 Data Registers (ADCR0, ADCR1) ..................... 197 Input Capture Data Register .............................. 140 Input Data Register 0 (UIDR0 ) and Output Data Register 0 (UODR0) ............................ 219 List of Message Buffers (Data Registers)............ 288 Port Data Registers ........................................... 110 Rate and Data Register 0 (URD0) ...................... 220 Serial Input Data Register 1 (SIDR1)/Serial Output Data Register 1 (SODR1)..................... 245 Serial Shift Data Register (SDR)........................ 268 Data Transfer Asynchronous (Start-Stop Synchronized) Mode Data Transfer Format .................................. 252 CLK Synchronous Mode Data Transfer Format .......................................................... 253 DCT Data Counter (DCT) ........................................... 62 Default Default Values of Hardware Components of 8/16-bit PPG ....................................... 174 Delayed Interrupt Block Diagram of Delayed Interrupt .................... 72 Delayed Interrupt Cause Issuance/Cancellation Register (DIRR: Delayed Interrupt Request Register)............................................... 73 Delayed Interrupt Occurrence .............................. 74 494 Note on Using the Delayed Interrupt Request Lock ........................................................... 72 Description Description of Instruction Presentation Items and Symbols ............................................. 441 Descriptor Extended Intelligent I/O Service Descriptor (ISD) ........................................................... 62 Detailed Explanation Detailed Explanation of Flash Memory Write/Erase ......................................................... 377 Direct Addressing Direct Addressing ............................................ 423 DIRR Delayed Interrupt Cause Issuance/Cancellation Register (DIRR: Delayed Interrupt Request Register) .............................................. 73 Disabling Message Buffer Caution for Disabling Message Buffers by BVAL Bits ......................................................... 336 DIV A, Ri Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions................. 41 Use of the "DIV A, Ri" and "DIVW A, RWi" Instructions without Precautions ............. 42 DIVW A, RWi Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions................. 41 Use of the "DIV A, Ri" and "DIVW A, RWi" Instructions without Precautions ............. 42 DLC Register DLC Register x (x=0 to 15) (DLCRx) ................ 320 List of Message Buffers (DLC Registers) ........... 287 DLCRx DLC Register x (x=0 to 15) (DLCRx) ................ 320 DQ Data Polling Flag (DQ7)................................... 370 Sector Erase Timer Flag (DQ3) ......................... 374 Timing Limit Exceeded Flag (DQ5) .................. 373 Toggle Bit Flag (DQ6) ..................................... 372 Toggle Bit-2 Flag (DQ2) .................................. 375 DTP DTP Operation ................................................ 182 Interrupt/DTP Enable Register (ENIR: Interrupt Request Enable Register) ..................... 180 Interrupt/DTP Source Register (EIRR: External Interrupt Request Register) .................. 180 Switching between External Interrupt and DTP Requests ............................................ 184 DTP/External Interrupt Block Diagram of DTP/External Interrupts......... 178 Notes on Use of DTP/External Interrupts ........... 185 Outline of DTP/External Interrupt ..................... 178 Registers of DTP/External Interrupts ................. 179 INDEX DTRx Data Register x (x=0 to 15) (DTRx)................... 321 E Effective Address Field Effective Address Field ............................ 422, 440 2 EI OS Conversion Using EI2OS .................................. 201 EI2OS Status Register (ISCS).............................. 64 Example of EI2OS Activation in Continuous Mode .......................................................... 204 Example of EI2OS Activation in Single Mode .......................................................... 202 Example of EI2OS Activation in Stop Mode .......................................................... 206 Extended Intelligent I/O Service (EI2OS) ...................................................... 45, 60 Flow of Data Protection Function (When EI2OS is Used)......................... 209 Intelligent I/O Service (EI2OS).......................... 260 Intelligent I/O Service (EI2OS) Function and Interrupts........................................... 146 Operation Sequence of the Extended Intelligent I/O Service (EI2OS) .............................. 66 Structure of Extended Intelligent I/O Service (EI2OS) ............................................................ 61 EI2OS Status Register EI2OS Status Register (ISCS).............................. 64 EIRR Interrupt/DTP Source Register (EIRR: External Interrupt Request Register) .................. 180 ELVR Request Level Setting Register (ELVR: External Level Register) ................................... 181 Enable Sector Protect Enable Sector Protect/Verify Sector Protect .......................................................... 483 End of Communication End of Communication in CLK Synchronous Mode .......................................................... 254 ENIR Interrupt/DTP Enable Register (ENIR: Interrupt Request Enable Register) ..................... 180 Entire Flash Memory Block Diagram of the Entire Flash Memory........ 360 Erase Chip Erase/Sector Erase Command Sequence .......................................................... 481 Detailed Explanation of Flash Memory Write/Erase .......................................................... 377 Sector Erase Timer Flag (DQ3) ......................... 374 Erasing All Data Erasing All Data in the Flash Memory (Erasing Chips) .......................................................... 381 Erasing Chips Erasing All Data in the Flash Memory (Erasing Chips) ..........................................................381 Erasing Optional Data Erasing Optional Data (Erasing Sectors) in the Flash Memory ............................382 Erasing Sector Erasing Optional Data (Erasing Sectors) in the Flash Memory ............................382 Erasing Sectors in the Flash Memory..................382 Error Receive and Transmit Error Counters (RTEC) ..........................................................297 Event Count Function Outline of 16-bit Reload Timer (With Event Count Function) ................146 Example Example of EI2OS Activation in Continuous Mode ..........................................................204 Example of EI2OS Activation in Single Mode ..........................................................202 Example of EI2OS Activation in Stop Mode ..........................................................206 Example of Minimum Connection to the Flash Microcontroller Programmer (Power Supplied from the Programmer) ..........................................................406 Example of Minimum Connection to the Flash Microcontroller Programmer (User Power Supply Used)....................404 Example of Program Patch Processing................351 Example of Serial Programming Connection (Power Supplied from the Programmer) ..........................................................402 Example of Serial Programming Connection (User Power Supply Used)...................400 Example of the 1M-bit Flash Memory Program ..........................................................390 System Configuration Example of the Address Match Detection Function...............................350 UART0 Application Example ............................234 Exception Exception...........................................................46 Exception Due to Execution of an Undefined Instruction.............................................69 Execution Cycle Count Calculating the Execution Cycle Count...............438 Execution Cycle Count......................................437 Extended Intelligent I/O Service Extended Intelligent I/O Service (EI2OS)........45, 60 Extended Intelligent I/O Service Descriptor (ISD) ............................................................62 Operation Sequence of the Extended Intelligent I/O Service (EI2OS) ..............................66 495 INDEX Structure of Extended Intelligent I/O Service (EI2OS) ............................................................ 61 Extended Serial I/O Interrupt Function of Extended Serial I/O Interface .......................................................... 277 External Clock Internal and External Clock ............................... 226 External Event Counter External Event Counter..................................... 153 External Interrupt Block Diagram of DTP/External Interrupts ......... 178 External Interrupts............................................ 182 Interrupt/DTP Source Register (EIRR: External Interrupt Request Register)................... 180 Notes on Use of DTP/External Interrupts............ 185 Outline of DTP/External Interrupt...................... 178 Registers of DTP/External Interrupts.................. 179 Switching between External Interrupt and DTP Requests............................................. 184 External Interrupt Request Register Interrupt/DTP Source Register (EIRR: External Interrupt Request Register)................... 180 External Level Register Request Level Setting Register (ELVR: External Level Register).................................... 181 External Shift Clock Mode External Shift Clock Mode ................................ 271 F F2MC-16LX Basic Configuration of F2MC-16LX MB90F598/ F598G Serial Programming Connection .......................................................... 396 F2MC-16LX Instruction List ............................. 444 Feature 1M-bit Flash Memory Features.......................... 358 Features............................................................... 3 Features of A/D Converter ................................ 188 Features of CAN Controller............................... 280 Features of UART1 .......................................... 238 Flash Security Feature ...................................... 389 Fetch Sample of Input Capture Fetch Timing ............... 142 Flag Data Polling Flag (DQ7) ................................... 370 Flag Change Disable Prefix (NCC) ...................... 39 Flag Setting Timing in Receive Mode (Mode 0, Mode 1, or Mode 3)............... 230 Flag Setting Timing in Receive Mode (mode 2) .......................................................... 231 Flag Setting Timing in Send Mode..................... 232 Hardware Sequence Flags ................................. 368 Sector Erase Timer Flag (DQ3) ......................... 374 Set Timing of Six Flags .................................... 229 496 Status Flag in Transmit/receive Mode ................ 233 Timing Limit Exceeded Flag (DQ5) .................. 373 Toggle Bit Flag (DQ6) ..................................... 372 Toggle Bit-2 Flag (DQ2) .................................. 375 UART1 Flags .................................................. 255 UART1 Interrupts and Flag Set Timing.............. 256 Flash Memory 1M-bit Flash Memory Features ......................... 358 Block Diagram of the Entire Flash Memory ......................................................... 360 Detailed Explanation of Flash Memory Write/Erase ......................................................... 377 Erasing All Data in the Flash Memory (Erasing Chips) ......................................................... 381 Erasing Optional Data (Erasing Sectors) in the Flash Memory ........................... 382 Erasing Sectors in the Flash Memory ................. 382 Example of the 1M-bit Flash Memory Program ......................................................... 390 Flash Memory Control Signals .......................... 363 Flash Memory Control Status Register (FMCS) ......................................................... 364 Flash Memory Mode ........................................ 362 Flash Memory Register .................................... 359 Notes on Using Flash Memory .......................... 386 Reset Vector Address in Flash Memory ............. 388 Restarting Erasing of Flash Memory Sectors ......................................................... 385 Sector Configuration of the 1M-bit Flash Memory ......................................................... 360 Setting the Flash Memory to the Read/Reset State ......................................................... 378 Suspending Erasing of Flash Memory Sectors ......................................................... 384 Writing Data to the Flash Memory..................... 379 Writing to the Flash Memory ............................ 379 Writing to/Erasing Flash Memory...................... 358 Flash Memory Control Status Register Flash Memory Control Status Register (FMCS) ......................................................... 364 Flash Memory Mode Flash Memory Mode ........................................ 362 Flash Memory Register Flash Memory Register .................................... 359 Flash Microcontroller Programmer Example of Minimum Connection to the Flash Microcontroller Programmer (Power Supplied from the Programmer) ......................................................... 406 Example of Minimum Connection to the Flash Microcontroller Programmer (User Power Supply Used)................... 404 Flash Security Flash Security Feature ...................................... 389 INDEX Flow Flow of Data Protection Function (When EI2OS is Used)........................ 209 UART1 Communication Flow Chart.................. 259 Flowchart CAN Controller Reception Flowchart ................ 327 CAN Controller Transmission Flowchart ........... 324 FMCS Flash Memory Control Status Register (FMCS) .......................................................... 364 Format Setting Frame Format ....................................... 328 Transfer Data Format ....................................... 227 Free-run Timer 16-bit Free-run Timer ............................... 122, 124 16-bit Free-run Timer Block Diagram ................ 125 16-bit Free-run Timer Timing ........................... 130 Operation of 16-bit Free-run Timer.................... 129 Function 8/16-bit PPG Functions..................................... 158 Block Diagram of ROM Mirroring Function Selection Module .............................................. 354 Block Diagram of the Address Match Detection Function............................................. 346 Flow of Data Protection Function (When EI2OS is Used)......................... 209 Input Pin Functions of 16-bit Reload Timer (for Internal Clock Mode) .................... 152 Intelligent I/O Service (EI2OS) Function and Interrupts............................................ 146 Interrupt Function of Extended Serial I/O Interface .......................................................... 277 Interval Interrupt Function ................................ 116 Operation of the Address Match Detection Function .......................................................... 349 Output Pin Functions of 16-bit Reload Timer .......................................................... 155 Pin Functions....................................................... 8 ROM Mirroring Function Selection Register (ROMM)............................................ 355 System Configuration Example of the Address Match Detection Function .............................. 350 G General-purpose Register General-purpose Registers .................................. 28 Generation Address Generation Types .................................. 21 H HALT Conditions for Canceling Bus Operation Stop (HALT=0).......................................... 294 Conditions for Setting Bus Operation Stop (HALT=1) ..........................................................294 State during Bus Operation Stop (HALT=1) ..........................................................294 Handling Handling Device.................................................14 Hardware Components Default Values of Hardware Components of 8/16-bit PPG .......................................174 Hardware Interrupt Hardware Interrupt Operation ..............................54 Hardware Interrupts ......................................44, 53 Occurrence and Release of Hardware Interrupt ............................................................55 Structure of Hardware Interrupt ...........................53 Hardware Sequence Flags Hardware Sequence Flags..................................368 Hardware Standby Mode Releasing Hardware Standby Mode ......................97 Transition to Hardware Standby Mode..................97 I I/O 16-bit I/O Timer Block Diagram ........................123 Extended Intelligent I/O Service (EI2OS) ......................................................45, 60 Extended Intelligent I/O Service Descriptor (ISD) ............................................................62 I/O Maps .........................................................410 I/O Port Registers .............................................109 I/O Ports ..........................................................108 I/O Register Address Pointer (IOA)......................62 Intelligent I/O Service (EI2OS) ..........................260 Intelligent I/O Service (EI2OS) Function and Interrupts ............................................146 Interrupt Function of Extended Serial I/O Interface ..........................................................277 Operation Sequence of the Extended Intelligent I/O Service (EI2OS) ..............................66 Serial I/O Block Diagram ..................................262 Serial I/O Operation..........................................270 Serial I/O Operation Status ................................272 Serial I/O Prescaler (SCDCR) ............................269 Serial I/O Registers...........................................263 Structure of Extended Intelligent I/O Service (EI2OS) ............................................................61 I/O Maps I/O Maps .........................................................410 I/O Port I/O Ports ..........................................................108 I/O Port Register I/O Port Registers .............................................109 I/O Register Address Pointer I/O Register Address Pointer (IOA)......................62 497 INDEX I/O Timer 16-bit I/O Timer Block Diagram........................ 123 ICR Interrupt Control Register (ICR) .......................... 48 ID ID Register x (x=0 to 15) (IDRx) ....................... 318 List of Message Buffers (ID Registers)............... 284 Setting ID ........................................................ 328 ID Register ID Register x (x=0 to 15) (IDRx) ....................... 318 List of Message Buffers (ID Registers)............... 284 IDE Register IDE Register (IDER) ........................................ 302 IDER IDE Register (IDER) ........................................ 302 IDRx ID Register x (x=0 to 15) (IDRx) ....................... 318 ILM Interrupt Level Mask Register (ILM) ................... 33 Indirect Addressing Indirect Addressing .......................................... 429 Initial Output Value Sample of a Output Waveform with Two Compare Registers (The Initial Output Value is "0".) .......................................................... 136 Sample of Output Waveform When Compare Registers 0 and 1 are Used (The Initial Output Value is 0.) ............. 136 Initializing Initializing the Machine Clock............................. 99 Input Capture 16-bit Input Capture ......................................... 124 Input Capture ................................................... 138 Input Capture (2 Channels Per One Module) .......................................................... 123 Input Capture Block Diagram ............................ 139 Input Capture Control Status Register ................ 140 Input Capture Input Timing ............................... 143 Sample of Input Capture Fetch Timing ............... 142 Input Capture Control Status Register Input Capture Control Status Register ................ 140 Input Data Register Input Data Register 0 (UIDR0 ) and Output Data Register 0 (UODR0) ............................ 219 Serial Input Data Register 1 (SIDR1)/Serial Output Data Register 1 (SODR1)..................... 245 Input Frequency Oscillating Clock Frequency and Serial Clock Input Frequency........................................... 399 Input Impedance Input Impedance............................................... 189 Input Pin Functions Input Pin Functions of 16-bit Reload Timer (for Internal Clock Mode) ................... 152 498 Input Timing Input Capture Input Timing............................... 143 Input/Output Circuit Input/Output Circuits.......................................... 11 Instruction Interrupt Disable Instructions .............................. 40 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions................. 41 Restrictions on Interrupt Disable Instructions and Prefix Instructions................................. 40 Use of the "DIV A, Ri" and "DIVW A, RWi" Instructions without Precautions ............. 42 Instruction List F2MC-16LX Instruction List............................. 444 Instruction Map Structure of Instruction Map ............................. 458 Instruction Presentation Items Description of Instruction Presentation Items and Symbols ............................................. 441 Instruction Types Instruction Types ............................................. 420 Intelligent I/O Service Extended Intelligent I/O Service (EI2OS) ..................................................... 45, 60 Extended Intelligent I/O Service Descriptor (ISD) ........................................................... 62 Intelligent I/O Service (EI2OS).......................... 260 Intelligent I/O Service (EI2OS) Function and Interrupts ........................................... 146 Operation Sequence of the Extended Intelligent I/O Service (EI2OS) ............................. 66 Structure of Extended Intelligent I/O Service (EI2OS) ........................................................... 61 Interface Interrupt Function of Extended Serial I/O Interface ......................................................... 277 Intermittent CPU Operation Intermittent CPU Operation ................................ 98 Internal and External Clock Internal and External Clock............................... 226 Internal Clock Internal Clock Operation of 16-bit Reload Timer ......................................................... 152 Interrupt Block Diagram of Delayed Interrupt .................... 72 Block Diagram of DTP/External Interrupts......... 178 Delayed Interrupt Cause Issuance/Cancellation Register (DIRR: Delayed Interrupt Request Register) .............................................. 73 Delayed Interrupt Occurrence ............................. 74 External Interrupts ........................................... 182 Hardware Interrupt Operation ............................. 54 Hardware Interrupts ..................................... 44, 53 Intelligent I/O Service (EI2OS) Function and Interrupts ........................................... 146 INDEX Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers ................................ 487 Interrupt Control Register (ICR) .......................... 48 Interrupt Disable Instructions .............................. 40 Interrupt Function of Extended Serial I/O Interface .......................................................... 277 Interrupt Level Mask Register (ILM) ................... 33 Interrupt Operation Sequence .............................. 51 Interrupt Vector List........................................... 47 Interrupt Vectors................................................ 47 Interrupt/DTP Enable Register (ENIR: Interrupt Request Enable Register) ..................... 180 Interrupt/DTP Source Register (EIRR: External Interrupt Request Register) .................. 180 Interrupts of 8/16-bit PPG................................. 173 Interval Interrupt Function ................................ 116 List of MB90595 Interrupt Vectors .............. 58, 485 Multiple Interrupts ............................................. 57 Note on Using the Delayed Interrupt Request Lock ............................................................ 72 Notes on Use of DTP/External Interrupts ........... 185 Occurrence and Release of Hardware Interrupt ............................................................ 55 Operation of Software Interrupts ......................... 58 Outline of DTP/External Interrupt ..................... 178 Reception Interrupt Enable Register (RIER) ....... 312 Registers of DTP/External Interrupts ................. 179 Restrictions on Interrupt Disable Instructions and Prefix Instructions................................. 40 Software Interrupts....................................... 45, 58 Structure of Hardware Interrupt ........................... 53 Structure of Software Interrupts........................... 58 Switching between External Interrupt and DTP Requests .................................... 184 Transmission Interrupt Enable Register (TIER) .......................................................... 308 UART1 Interrupt Sources ................................. 255 UART1 Interrupts and Flag Set Timing.............. 256 Interrupt Causes Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers ................................ 487 Interrupt Control Register Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers ................................ 487 Interrupt Control Register (ICR) .......................... 48 Interrupt Disable Instructions Interrupt Disable Instructions .............................. 40 Restrictions on Interrupt Disable Instructions and Prefix Instructions................................. 40 Interrupt Enable Register Reception Interrupt Enable Register (RIER) .......................................................... 312 Transmission Interrupt Enable Register (TIER) .......................................................... 308 Interrupt Function Interrupt Function of Extended Serial I/O Interface ..........................................................277 Interval Interrupt Function.................................116 Interrupt Level Mask Register Interrupt Level Mask Register (ILM)....................33 Interrupt Request Enable Register Interrupt/DTP Enable Register (ENIR: Interrupt Request Enable Register)......................180 Interrupt Source UART1 Interrupt Sources..................................255 Interrupt Vector Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers .................................487 Interrupt Vector List ...........................................47 Interrupt Vectors ................................................47 List of MB90595 Interrupt Vectors...............58, 485 Interrupt/DTP Enable Register Interrupt/DTP Enable Register (ENIR: Interrupt Request Enable Register)......................180 Interrupt/DTP Source Register Interrupt/DTP Source Register (EIRR: External Interrupt Request Register) ...................180 Interval Interrupt Function Interval Interrupt Function.................................116 IOA I/O Register Address Pointer (IOA)......................62 ISCS EI2OS Status Register (ISCS) ..............................64 ISD Extended Intelligent I/O Service Descriptor (ISD) ............................................................62 L Last Event Indicator Register Last Event Indicator Register (LEIR)..................295 LEIR Last Event Indicator Register (LEIR)..................295 Level Mask Interrupt Level Mask Register (ILM)....................33 List F2MC-16LX Instruction List..............................444 Interrupt Vector List ...........................................47 List of MB90595 Interrupt Vectors...............58, 485 List of Message Buffers (Data Registers) ............288 List of Message Buffers (DLC Registers)............287 List of Message Buffers (ID Registers) ...............284 List of Total Control Registers ...........................282 Low-power Consumption Mode Setting Low-power Consumption Mode..............329 Low-power Control Circuit Block Diagram of Low-power Control Circuit ............................................................85 Outline of Low-power Control Circuit ..................84 499 INDEX Registers of Low-power Control Circuit ............... 86 Low-power Mode Control Register Low-power Mode Control Register (LPMCR) ............................................................ 87 Note of Low-power Mode Control Register Access ............................................................ 92 LPMCR Low-power Mode Control Register (LPMCR) ...... 87 M Machine Clock Initializing the Machine Clock............................. 99 Main Clock Switching between Main Clock and PLL Clock ............................................................ 99 Mask Acceptance Mask Registers 0 and 1 (AMR0/AMR1) .......................................................... 315 Acceptance Mask Select Register (AMSR) ......... 313 Interrupt Level Mask Register (ILM) ................... 33 Memory 1M-bit Flash Memory Features.......................... 358 Block Diagram of the Entire Flash Memory........ 360 Detailed Explanation of Flash Memory Write/Erase .......................................................... 377 Erasing All Data in the Flash Memory (Erasing Chips) .......................................................... 381 Erasing Optional Data (Erasing Sectors) in the Flash Memory ........................... 382 Erasing Sectors in the Flash Memory ................. 382 Example of the 1M-bit Flash Memory Program .......................................................... 390 Flash Memory Control Signals .......................... 363 Flash Memory Control Status Register (FMCS) .......................................................... 364 Flash Memory Mode ........................................ 362 Flash Memory Register..................................... 359 Memory Access Modes..................................... 102 Memory Space Map ........................................... 22 Multi-byte Data in Memory Space ....................... 26 Notes on Using Flash Memory .......................... 386 Outline of CPU Memory Space ........................... 21 Reset Vector Address in Flash Memory.............. 388 Restarting Erasing of Flash Memory Sectors .......................................................... 385 Sector Configuration of the 1M-bit Flash Memory .......................................................... 360 Setting the Flash Memory to the Read/Reset State .......................................................... 378 Suspending Erasing of Flash Memory Sectors .......................................................... 384 Writing Data to the Flash Memory ..................... 379 Writing to the Flash Memory............................. 379 Writing to/Erasing Flash Memory ...................... 358 500 Memory Access Mode Memory Access Modes .................................... 102 Memory Space Memory Space Map ........................................... 22 Multi-byte Data in Memory Space ....................... 26 Outline of CPU Memory Space ........................... 21 Message Buffer Caution for Disabling Message Buffers by BVAL Bits ......................................................... 336 List of Message Buffers (Data Registers) ........... 288 List of Message Buffers (DLC Registers) ........... 287 List of Message Buffers (ID Registers) .............. 284 Message Buffer Control Registers ..................... 290 Message Buffer Valid Register (BVALR) .......... 301 Message Buffers ...................................... 290, 317 Procedure for Reception by Message Buffer (x) ......................................................... 332 Procedure for Transmission by Message Buffer (x) ......................................................... 330 Setting Configuration of Multi-level Message Buffer ......................................................... 334 Message Buffer Control Register Message Buffer Control Registers ..................... 290 Message Buffer Valid Register Message Buffer Valid Register (BVALR) .......... 301 Microcontroller Example of Minimum Connection to the Flash Microcontroller Programmer (Power Supplied from the Programmer) ......................................................... 406 Example of Minimum Connection to the Flash Microcontroller Programmer (User Power Supply Used)................... 404 Minimum Connection Example of Minimum Connection to the Flash Microcontroller Programmer (Power Supplied from the Programmer) ......................................................... 406 Example of Minimum Connection to the Flash Microcontroller Programmer (User Power Supply Used)................... 404 Mode Alternative Mode ............................................. 362 Asynchronous (Start-Stop Synchronized) Mode Data Transfer Format .......................... 252 Asynchronous (Start-Stop Synchronized) Mode Receive Operation............................... 252 Asynchronous (Start-Stop Synchronized) Mode Transmit Operation ............................. 252 Bus Mode Setting Bits...................................... 105 CLK Synchronous Mode Data Transfer Format ......................................................... 253 Continuous Mode............................................. 199 Control Register Settings for CLK Synchronous Mode ......................................................... 254 INDEX End of Communication in CLK Synchronous Mode .......................................................... 254 Example of EI2OS Activation in Continuous Mode .......................................................... 204 Example of EI2OS Activation in Single Mode .......................................................... 202 Example of EI2OS Activation in Stop Mode .......................................................... 206 External Shift Clock Mode................................ 271 Flag Setting Timing in Receive Mode (Mode 0, Mode 1, or Mode 3) .............. 230 Flag Setting Timing in Receive Mode (mode 2) .......................................................... 231 Flag Setting Timing in Send Mode .................... 232 Flash Memory Mode ........................................ 362 Internal Shift Cock Mode.................................. 271 Low-power Mode Control Register (LPMCR) ............................................................ 87 Low-power Mode Operation ............................... 91 Memory Access Modes .................................... 102 Mode Data ...................................................... 104 Mode Pins ....................................................... 103 Note of Low-power Mode Control Register Access ............................................................ 92 Notes on the Transition to Low-power Mode ............................................................ 92 Operating Modes of UART0 ............................. 222 PPG0 Operation Mode Control Register (PPGC0) .......................................................... 162 PPG1 Operation Mode Control Register (PPGC1) .......................................................... 164 Releasing Hardware Standby Mode ..................... 97 Releasing Sleep Mode ........................................ 93 Releasing Stop Mode.......................................... 95 Releasing Timer Mode ....................................... 94 Serial Mode Control Register 0 (UMC0) ............ 215 Serial Mode Control Status Register (SMCS) .......................................................... 264 Serial Mode Register 1 (SMR1)......................... 241 Setting Low-power Consumption Mode ............. 329 Single Mode .................................................... 199 Start of Communication in CLK Synchronous Mode .......................................................... 254 Status Flag in Transmit/receive Mode ................ 233 Stop Mode....................................................... 200 Transition to Hardware Standby Mode ................. 97 Transition to Sleep Mode.................................... 93 Transition to Stop Mode ..................................... 95 Transition to Timer Mode ................................... 94 UART1 Operating Modes ................................. 249 UART1 Sample Application (System Configuration in Mode 1)......................................... 259 Mode Data Asynchronous (Start-Stop Synchronized) Mode Data Transfer Format .................................. 252 CLK Synchronous Mode Data Transfer Format .......................................................... 253 Mode Data .......................................................104 Mode Operation Low-power Mode Operation................................91 Mode Pins Mode Pins........................................................103 Module Block Diagram of ROM Mirroring Function Selection Module ...............................................354 Input Capture (2 Channels Per One Module) ..........................................................123 Output Compare (2 Channels Per One Module) ..........................................................122 Multi-byte Data Accessing Multi-byte Data ..................................26 Multi-byte Data in Memory Space........................26 Multi-level Message Buffer Setting Configuration of Multi-level Message Buffer ..........................................................334 Multiple Interrupt Multiple Interrupts..............................................57 N NCC Flag Change Disable Prefix (NCC).......................39 Negative Clock Operation Negative Clock Operation .................................278 Note Note of Clock Generator .....................................76 Note of Low-power Mode Control Register Access ............................................................92 Note on Using the Delayed Interrupt Request Lock ............................................................72 Notes on the Transition to Low-power Mode ............................................................92 Notes on Use....................................................209 Notes on Use of DTP/External Interrupts ............185 Notes on Using Flash Memory...........................386 O Occurrence Delayed Interrupt Occurrence ..............................74 Occurrence and Release of Hardware Interrupt ............................................................55 Reset Cause Occurrence ......................................77 Operand 24-bit Operand Specification ...............................23 Operating Mode Operating Modes of UART0..............................222 UART1 Operating Modes..................................249 Operation 8/16-bit PPG Operation .....................................169 8/16-bit PPG Output Operation ..........................170 Asynchronous (Start-Stop Synchronized) Mode Receive Operation ...............................252 501 INDEX Asynchronous (Start-Stop Synchronized) Mode Transmit Operation.............................. 252 Conditions for Canceling Bus Operation Stop (HALT=0) .......................................... 294 Conditions for Setting Bus Operation Stop (HALT=1) .......................................................... 294 Counter Operation State.................................... 156 DTP Operation................................................. 182 Hardware Interrupt Operation.............................. 54 Intermittent CPU Operation................................. 98 Internal Clock Operation of 16-bit Reload Timer .......................................................... 152 Interrupt Operation Sequence .............................. 51 Low-power Mode Operation ............................... 91 Negative Clock Operation ................................. 278 Operation after Reset Release .............................. 77 Operation of 16-bit Free-run Timer .................... 129 Operation of Software Interrupts.......................... 58 Operation of the Address Match Detection Function .......................................................... 349 Operation Sequence of the Extended Intelligent I/O Service (EI2OS) .................................... 66 PPG0 Operation Mode Control Register (PPGC0) .......................................................... 162 PPG1 Operation Mode Control Register (PPGC1) .......................................................... 164 Serial I/O Operation ......................................... 270 Serial I/O Operation Status................................ 272 Shift Operation Start/Stop Timing...................... 274 State during Bus Operation Stop (HALT=1) .......................................................... 294 Underflow Operation of 16-bit Reload Timer .......................................................... 154 Oscillating Oscillating Clock Frequency and Serial Clock Input Frequency........................................... 399 Oscillation Stabilization Wait Time Setting the Oscillation Stabilization Wait Time ...................................................... 96, 97 Others Others ............................................................... 59 Outline Outline of 16-bit Reload Timer (With Event Count Function)................ 146 Outline of CPU .................................................. 20 Outline of CPU Memory Space ........................... 21 Outline of DTP/External Interrupt...................... 178 Outline of Low-power Control Circuit.................. 84 Outline of Time-base Timer .............................. 114 Output Compare 16-bit Output Compare ..................................... 124 Clearing the Counter Upon a Match with Output Compare Register 0 ............................. 130 Control Status Register of Output Compare .......................................................... 133 Output Compare............................................... 131 502 Output Compare (2 Channels Per One Module) ......................................................... 122 Output Compare Block Diagram ....................... 131 Output Compare Register Details ...................... 132 Output Compare Timing ................................... 137 Output Compare Register Clearing the Counter Upon a Match with Output Compare Register 0............................. 130 Output Compare Register Details ...................... 132 Output Data Register Input Data Register 0 (UIDR0 ) and Output Data Register 0 (UODR0)............................ 219 Serial Input Data Register 1 (SIDR1)/Serial Output Data Register 1 (SODR1) .................... 245 Output Pin Output Pin Functions of 16-bit Reload Timer ......................................................... 155 PPG0, 1 Output Pin Control Register (PPG01) ......................................................... 166 Output Waveform Sample of a Output Waveform with Two Compare Registers (The Initial Output Value is "0".) ......................................................... 136 Sample of Output Waveform When Compare Registers 0 and 1 are Used (The Initial Output Value is 0.)............ 136 Overview Overview ............................................................ 2 P Package Dimensions Package Dimensions ............................................ 7 PACSR Program Address Detection Control Status Register (PACSR)............................................ 347 PADR Program Address Detection Registers (PADR0 and PADR1) ......................... 347 Parity Bit Parity Bit......................................................... 228 PC Program Counter (PC) ........................................ 35 Pin Assignment Pin Assignment.................................................... 6 Pin Control PPG0, 1 Output Pin Control Register (PPG01) ......................................................... 166 Pin Functions Input Pin Functions of 16-bit Reload Timer (for Internal Clock Mode) ................... 152 Output Pin Functions of 16-bit Reload Timer ......................................................... 155 Pin Functions....................................................... 8 INDEX PLL Clock Switching between Main Clock and PLL Clock ............................................................ 99 Port Data Register Port Data Registers........................................... 110 Port Direction Register Port Direction Register ..................................... 111 Port Register I/O Port Registers............................................. 109 Power Supply Example of Minimum Connection to the Flash Microcontroller Programmer (Power Supplied from the Programmer) .......................................................... 406 Example of Minimum Connection to the Flash Microcontroller Programmer (User Power Supply Used) ................... 404 Example of Serial Programming Connection (Power Supplied from the Programmer) .......................................................... 402 Example of Serial Programming Connection (User Power Supply Used) ................... 400 PPG 8/16-bit PPG Block Diagram............................. 159 8/16-bit PPG Functions..................................... 158 8/16-bit PPG Operation .................................... 169 8/16-bit PPG Output Operation ......................... 170 8/16-bit PPG Registers ..................................... 161 Count Clock Selection of 8/16-bit PPG .............. 171 Default Values of Hardware Components of 8/16-bit PPG....................................... 174 Interrupts of 8/16-bit PPG................................. 173 PPG0, 1 Output Pin Control Register (PPG01) .......................................................... 166 PPG1 Operation Mode Control Register (PPGC1) .......................................................... 164 Pulse Pin Output Control of 8/16-bit PPG........... 172 Relationship between 8/16-bit PPG Reload Value and Pulse Width ........................................ 170 PPG0 PPG0 Operation Mode Control Register (PPGC0) .......................................................... 162 PPG1 Operation Mode Control Register PPG1 Operation Mode Control Register (PPGC1) .......................................................... 164 PPGC PPG1 Operation Mode Control Register (PPGC1) .......................................................... 164 Precautions Precautions for UART1 Use.............................. 260 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions ................. 41 Use of the "DIV A, Ri" and "DIVW A, RWi" Instructions without Precautions ............. 42 Prefix Bank Select Prefix ..............................................38 Common Register Bank Prefix (CMR) .................39 Consecutive Prefix Codes....................................40 Flag Change Disable Prefix (NCC).......................39 Restrictions on Interrupt Disable Instructions and Prefix Instructions..................................40 Prescaler Serial I/O Prescaler (SCDCR) ............................269 UART1 Prescaler Control Register (U1CDCR) ..........................................................248 PRLH Reload Registers (PRLL, PRLH)........................168 PRLL Reload Registers (PRLL, PRLH)........................168 Procedure Procedure for Reception by Message Buffer (x) ..........................................................332 Procedure for Transmission by Message Buffer (x) ..........................................................330 Processing Example of Program Patch Processing................351 Processing for Reception of Data Frame and Remote Frame .....................................326 Processor Status Processor Status (PS) ..........................................32 Program Example of Program Patch Processing................351 Example of the 1M-bit Flash Memory Program ..........................................................390 Program Address Detection Control Status Register (PACSR) ............................................347 Program Address Detection Registers (PADR0 and PADR1) ..........................347 Program Counter (PC).........................................35 Program Address Detection Register Program Address Detection Registers (PADR0 and PADR1)..............................................347 Programmer Example of Minimum Connection to the Flash Microcontroller Programmer (Power Supplied from the Programmer) ..........................................................406 Example of Minimum Connection to the Flash Microcontroller Programmer (User Power Supply Used)....................404 Example of Serial Programming Connection (Power Supplied from the Programmer) ..........................................................402 Programming Connection Basic Configuration of F2MC-16LX MB90F598/ F598G Serial Programming Connection ..........................................................396 503 INDEX Example of Serial Programming Connection (Power Supplied from the Programmer) .......................................................... 402 Example of Serial Programming Connection (User Power Supply Used) ................... 400 Protection Conversion Data Protection............................... 208 Flow of Data Protection Function (When EI2OS is Used) ......................... 209 PS Processor Status (PS).......................................... 32 Pulse Pin Pulse Pin Output Control of 8/16-bit PPG ........... 172 Pulse Width Relationship between 8/16-bit PPG Reload Value and Pulse Width ........................................ 170 PWM PWM Control 0 Register................................... 340 PWM1 and PWM2 Compare Registers............... 341 PWM1 and PWM2 Select Registers ................... 342 PWM Control 0 Register PWM Control 0 Register................................... 340 PWM2 Select Register PWM1 and PWM2 Select Registers ................... 342 R Rate and Data Register Rate and Data Register 0 (URD0) ...................... 220 RCR Reception Complete Register (RCR) .................. 309 Read Data Read by Read Access ................................ 480 Setting the Flash Memory to the Read/Reset State .......................................................... 378 Write, Data Polling, Read (CE Control).............. 481 Write, Data Polling, Read (WE Control)............. 480 Receive and Transmit Error Counters Receive and Transmit Error Counters (RTEC) .......................................................... 297 Receive Operation Asynchronous (Start-Stop Synchronized) Mode Receive Operation ............................... 252 Receive Overrun Receive Overrun .............................................. 326 Receive Overrun Register (ROVRR).................. 311 Receive Overrun Register Receive Overrun Register (ROVRR).................. 311 Received Message Storing Received Message ................................ 325 Reception CAN Controller Reception Flowchart................. 327 Completing Reception ...................................... 326 Procedure for Reception by Message Buffer (x) .......................................................... 332 504 Processing for Reception of Data Frame and Remote Frame ................................................ 326 Reception Complete Register (RCR).................. 309 Reception Interrupt Enable Register (RIER) ......................................................... 312 Reception Complete Register Reception Complete Register (RCR).................. 309 Reception Flowchart CAN Controller Reception Flowchart ................ 327 Reception Interrupt Enable Register Reception Interrupt Enable Register (RIER) ......................................................... 312 Recommended Setting Recommended Setting...................................... 106 Register 8/16-bit PPG Registers ..................................... 161 A/D Converter Registers................................... 191 Acceptance Mask Registers 0 and 1 (AMR0/AMR1) ......................................................... 315 Acceptance Mask Select Register (AMSR)......... 313 Analog Input Enable Register.................... 112, 188 Bit Timing Register (BTR) ............................... 298 Clearing the Counter Upon a Match with Output Compare Register 0............................. 130 Clock Selection Register (CKSCR)...................... 89 Common Register Bank Prefix (CMR)................. 39 Condition Code Register (CCR) .......................... 32 Control Register Settings for CLK Synchronous Mode ......................................................... 254 Control Status Register ..................................... 127 Control Status Register (ADCS1) ...................... 195 Control Status Register (CSR)........................... 291 Control Status Register of Output Compare ......................................................... 133 Control Status Registers (ADCS0)..................... 192 Data Register................................................... 126 Data Register x (x=0 to 15) (DTRx)................... 321 Data Registers (ADCR0, ADCR1)..................... 197 Delayed Interrupt Cause Issuance/Cancellation Register (DIRR: Delayed Interrupt Request Register) .............................................. 73 DLC Register x (x=0 to 15) (DLCRx) ................ 320 EI2OS Status Register (ISCS).............................. 64 Flash Memory Control Status Register (FMCS) ......................................................... 364 Flash Memory Register .................................... 359 General-purpose Registers .................................. 28 I/O Port Registers ............................................ 109 I/O Register Address Pointer (IOA) ..................... 62 ID Register x (x=0 to 15) (IDRx)....................... 318 IDE Register (IDER) ........................................ 302 Input Capture Control Status Register ................ 140 Input Capture Data Register .............................. 140 Input Data Register 0 (UIDR0 ) and Output Data Register 0 (UODR0)............................ 219 INDEX Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers ................................ 487 Interrupt Control Register (ICR) .......................... 48 Interrupt Level Mask Register (ILM) ................... 33 Interrupt/DTP Enable Register (ENIR: Interrupt Request Enable Register) ..................... 180 Interrupt/DTP Source Register (EIRR: External Interrupt Request Register) .................. 180 Last Event Indicator Register (LEIR) ................. 295 List of Message Buffers (Data Registers) ........... 288 List of Message Buffers (DLC Registers) ........... 287 List of Message Buffers (ID Registers) .............. 284 List of Total Control Registers .......................... 282 Low-power Mode Control Register (LPMCR) ............................................................ 87 Message Buffer Control Registers ..................... 290 Message Buffer Valid Register (BVALR) .......... 301 Note of Low-power Mode Control Register Access ............................................................ 92 Output Compare Register Details ...................... 132 Port Data Registers........................................... 110 Port Direction Register ..................................... 111 PPG0 Operation Mode Control Register (PPGC0) .......................................................... 162 PPG0, 1 Output Pin Control Register (PPG01) .......................................................... 166 PPG1 Operation Mode Control Register (PPGC1) .......................................................... 164 Program Address Detection Control Status Register (PACSR)............................................ 347 Program Address Detection Registers (PADR0 and PADR1) ......................... 347 PWM Control 0 Register .................................. 340 PWM1 and PWM2 Compare Registers .............. 341 PWM1 and PWM2 Select Registers................... 342 Rate and Data Register 0 (URD0) ...................... 220 Receive Overrun Register (ROVRR) ................. 311 Reception Complete Register (RCR).................. 309 Reception Interrupt Enable Register (RIER) .......................................................... 312 Register Bank .................................................... 36 Register Bank Pointer (RP) ................................. 33 Register Layout of 16-bit Timer Register (TMR)/ 16-bit Reload Register (TMRLR) ......... 151 Registers not Initialized by Reset Input ................ 78 Registers of 16-bit Reload Timer ....................... 147 Registers of DTP/External Interrupts ................. 179 Registers of Low-power Control Circuit............... 86 Registers of UART0......................................... 214 Reload Registers (PRLL, PRLH) ....................... 168 Remote Frame Receiving Wait Register (RFWTR) .......................................................... 305 Remote Request Receiving Register (RRTRR) .......................................................... 310 Request Level Setting Register (ELVR: External Level Register) ................................... 181 ROM Mirroring Function Selection Register (ROMM) ............................................355 Sample of a Output Waveform with Two Compare Registers (The Initial Output Value is "0".) ..........................................................136 Sample of Output Waveform When Compare Registers 0 and 1 are Used (The Initial Output Value is 0.).............136 Serial Control Register 1 (SCR1) .......................243 Serial I/O Registers...........................................263 Serial Input Data Register 1 (SIDR1)/Serial Output Data Register 1 (SODR1) .....................245 Serial Mode Control Register 0 (UMC0).............215 Serial Mode Control Status Register (SMCS) ..........................................................264 Serial Mode Register 1 (SMR1) .........................241 Serial Shift Data Register (SDR) ........................268 Serial Status Register 1 (SSR1) ..........................246 Special Registers ................................................27 Status Register 0 (USR0)...................................217 Stepping Motor Controller Registers ..................339 Structure of Timer Control Status Register (TMCSR) ..........................................................148 Time-base Timer Control Register (TBTC) .........115 Total Control Registers .....................................290 Transmission Cancel Register (TCANR) ............306 Transmission Complete Register (TCR)..............307 Transmission Interrupt Enable Register (TIER) ..........................................................308 Transmission Request Register (TREQR) ...........303 Transmission RTR Register (TRTRR) ................304 UART1 Prescaler Control Register (U1CDCR) ..........................................................248 UART1 Registers .............................................240 Watch-dog Timer Control Register (WDTC) ..........................................................118 Register Bank Common Register Bank Prefix (CMR) .................39 Register Bank.....................................................36 Register Bank Pointer (RP)..................................33 Relationship Relationship between 8/16-bit PPG Reload Value and Pulse Width.........................................170 Release Occurrence and Release of Hardware Interrupt ............................................................55 Operation after Reset Release ..............................77 Releasing Releasing Hardware Standby Mode ......................97 Releasing Sleep Mode.........................................93 Releasing Stop Mode ..........................................95 Releasing Timer Mode ........................................94 Reload Register Register Layout of 16-bit Timer Register (TMR)/ 16-bit Reload Register (TMRLR) ..........................................................151 505 INDEX Reload Registers (PRLL, PRLH) ....................... 168 Reload Timer Block Diagram of 16-bit Reload Timer............... 146 Input Pin Functions of 16-bit Reload Timer (for Internal Clock Mode) .................... 152 Internal Clock Operation of 16-bit Reload Timer .......................................................... 152 Outline of 16-bit Reload Timer (With Event Count Function)................ 146 Registers of 16-bit Reload Timer ....................... 147 Underflow Operation of 16-bit Reload Timer .......................................................... 154 Reload Value Relationship between 8/16-bit PPG Reload Value and Pulse Width ........................................ 170 Remote Frame Processing for Reception of Data Frame and Remote Frame................................................. 326 Remote Frame Receiving Wait Register (RFWTR) .......................................................... 305 Remote Frame Receiving Wait Register Remote Frame Receiving Wait Register (RFWTR) .......................................................... 305 Remote Request Receiving Register Remote Request Receiving Register (RRTRR) .......................................................... 310 Request Canceling a CAN Controller Transmission Request .......................................................... 323 Delayed Interrupt Cause Issuance/Cancellation Register (DIRR: Delayed Interrupt Request Register)............................................... 73 Interrupt/DTP Enable Register (ENIR: Interrupt Request Enable Register) ..................... 180 Note on Using the Delayed Interrupt Request Lock ............................................................ 72 Remote Request Receiving Register (RRTRR) .......................................................... 310 Request Level Setting Register (ELVR: External Level Register).................................... 181 Switching between External Interrupt and DTP Requests ..................................... 184 Transmission Request Register (TREQR) ........... 303 Request Level Setting Register Request Level Setting Register (ELVR: External Level Register).................................... 181 Reset Operation after Reset Release .............................. 77 Registers not Initialized by Reset Input................. 78 Reset Cause Occurrence...................................... 77 Reset Causes...................................................... 80 Reset Vector Address in Flash Memory.............. 388 Setting the Flash Memory to the Read/Reset State .......................................................... 378 506 Restarting Erasing Restarting Erasing of Flash Memory Sectors ......................................................... 385 Restrictions Restrictions on Interrupt Disable Instructions and Prefix Instructions................................. 40 RFWTR Remote Frame Receiving Wait Register (RFWTR) ......................................................... 305 RIER Reception Interrupt Enable Register (RIER) ......................................................... 312 ROM Mirroring Function Selection Module Block Diagram of ROM Mirroring Function Selection Module .............................................. 354 ROM Mirroring Function Selection Register ROM Mirroring Function Selection Register (ROMM)............................................ 355 ROMM ROM Mirroring Function Selection Register (ROMM)............................................ 355 ROVRR Receive Overrun Register (ROVRR) ................. 311 RP Register Bank Pointer (RP) ................................. 33 RRTRR Remote Request Receiving Register (RRTRR) ......................................................... 310 RST RST and RY/BY Timing .................................. 483 RTEC Receive and Transmit Error Counters (RTEC) ......................................................... 297 RY/BY Timing RST and RY/BY Timing .................................. 483 RY/BY Timing During Writing/Erasing............. 482 S Sample Sample of a Output Waveform with Two Compare Registers (The Initial Output Value is "0".) ......................................................... 136 Sample of Input Capture Fetch Timing............... 142 Sample of Output Waveform When Compare Registers 0 and 1 are Used (The Initial Output Value is 0.)............ 136 UART1 Sample Application (System Configuration in Mode 1)......................................... 259 SCDCR Serial I/O Prescaler (SCDCR) ........................... 269 SCR Serial Control Register 1 (SCR1)....................... 243 SDR Serial Shift Data Register (SDR) ....................... 268 INDEX Sector Chip Erase/Sector Erase Command Sequence .......................................................... 481 Enable Sector Protect/Verify Sector Protect .......................................................... 483 Erasing Optional Data (Erasing Sectors) in the Flash Memory ............................................. 382 Erasing Sectors in the Flash Memory ................. 382 Restarting Erasing of Flash Memory Sectors .......................................................... 385 Sector Configuration of the 1M-bit Flash Memory .......................................................... 360 Sector Erase Timer Flag (DQ3) ......................... 374 Suspending Erasing of Flash Memory Sectors .......................................................... 384 Temporary Sector Protect Cancellation .............. 484 Sector Configuration Sector Configuration of the 1M-bit Flash Memory .......................................................... 360 Sector Erase Chip Erase/Sector Erase Command Sequence .......................................................... 481 Sector Erase Timer Flag (DQ3) ......................... 374 Sector Protect Enable Sector Protect/Verify Sector Protect........ 483 Temporary Sector Protect Cancellation .............. 484 Security Flash Security Feature ...................................... 389 Selection Block Diagram of ROM Mirroring Function Selection Module .............................................. 354 Clock Selection Register (CKSCR)...................... 89 Count Clock Selection of 8/16-bit PPG .............. 171 ROM Mirroring Function Selection Register (ROMM)............................................ 355 Status Transition of Clock Selection .................. 100 UART1 Clock Selection ................................... 249 Serial Clock Input Frequency Oscillating Clock Frequency and Serial Clock Input Frequency .......................................... 399 Serial Control Register Serial Control Register 1 (SCR1)....................... 243 Serial I/O Interrupt Function of Extended Serial I/O Interface .......................................................... 277 Serial I/O Block Diagram ................................. 262 Serial I/O Operation ......................................... 270 Serial I/O Operation Status ............................... 272 Serial I/O Prescaler (SCDCR) ........................... 269 Serial I/O Registers .......................................... 263 Serial I/O Prescaler Serial I/O Prescaler (SCDCR) ........................... 269 Serial Input Data Register Serial Input Data Register 1 (SIDR1)/Serial Output Data Register 1 (SODR1) .................... 245 Serial Mode Control Register Serial Mode Control Register 0 (UMC0).............215 Serial Mode Control Status Register Serial Mode Control Status Register (SMCS) ..........................................................264 Serial Mode Register Serial Mode Register 1 (SMR1) .........................241 Serial Output Data Register Serial Input Data Register 1 (SIDR1)/Serial Output Data Register 1 (SODR1) .....................245 Serial Programming Connection Basic Configuration of F2MC-16LX MB90F598/ F598G Serial Programming Connection ..........................................................396 Example of Serial Programming Connection (Power Supplied from the Programmer) ..........................................................402 Example of Serial Programming Connection (User Power Supply Used)....................400 Serial Shift Data Register Serial Shift Data Register (SDR) ........................268 Serial Status Register Serial Status Register 1 (SSR1) ..........................246 Set Set Timing of Six Flags.....................................229 Setting Acceptance Filter Setting Acceptance Filter...................................328 Setting Bit Timing Setting Bit Timing ............................................328 Setting Configuration Setting Configuration of Multi-level Message Buffer ..........................................................334 Setting Frame Format Setting Frame Format........................................328 Setting ID Setting ID ........................................................328 Setting Low-power Consumption Mode Setting Low-power Consumption Mode..............329 Setting Register Request Level Setting Register (ELVR: External Level Register) ....................................181 Shift Clock Mode External Shift Clock Mode ................................271 Shift Operation Shift Operation Start/Stop Timing ......................274 SIDR Serial Input Data Register 1 (SIDR1)/Serial Output Data Register 1 (SODR1) .....................245 Single Mode Example of EI2OS Activation in Single Mode ..........................................................202 Single Mode.....................................................199 Sleep Mode Releasing Sleep Mode.........................................93 507 INDEX Transition to Sleep Mode .................................... 93 SMCS Serial Mode Control Status Register (SMCS) .......................................................... 264 SMR Serial Mode Register 1 (SMR1)......................... 241 Software Interrupt Operation of Software Interrupts.......................... 58 Software Interrupts ....................................... 45, 58 Structure of Software Interrupts ........................... 58 Source Interrupt/DTP Source Register (EIRR: External Interrupt Request Register)................... 180 UART1 Interrupt Sources ................................. 255 Special Register Special Registers ................................................ 27 Specification 24-bit Operand Specification ............................... 23 SSP User Stack Pointer (USP) and System Stack Pointer (SSP) ................................................... 31 SSR Serial Status Register 1 (SSR1).......................... 246 Stack User Stack Pointer (USP) and System Stack Pointer (SSP) ................................................... 31 Standby Mode Releasing Hardware Standby Mode...................... 97 Transition to Hardware Standby Mode ................. 97 Start Asynchronous (Start-Stop Synchronized) Mode Data Transfer Format .................................. 252 Asynchronous (Start-Stop Synchronized) Mode Receive Operation ............................... 252 Asynchronous (Start-Stop Synchronized) Mode Transmit Operation.............................. 252 Shift Operation Start/Stop Timing...................... 274 Start of Communication in CLK Synchronous Mode .......................................................... 254 Starting Transmission Starting Transmission ....................................... 323 State Counter Operation State.................................... 156 Setting the Flash Memory to the Read/Reset State .......................................................... 378 State during Bus Operation Stop (HALT=1) .......................................................... 294 Status Control Status Register ..................................... 127 Control Status Register (ADCS1)....................... 195 Control Status Register (CSR) ........................... 291 Control Status Register of Output Compare .......................................................... 133 Control Status Registers (ADCS0) ..................... 192 508 EI2OS Status Register (ISCS).............................. 64 Flash Memory Control Status Register (FMCS) ......................................................... 364 Input Capture Control Status Register ................ 140 Processor Status (PS) ......................................... 32 Program Address Detection Control Status Register (PACSR)............................................ 347 Serial I/O Operation Status ............................... 272 Serial Mode Control Status Register (SMCS) ......................................................... 264 Serial Status Register 1 (SSR1) ......................... 246 Status Flag in Transmit/receive Mode ................ 233 Status Register 0 (USR0) .................................. 217 Status Transition of Clock Selection .................. 100 Structure of Timer Control Status Register (TMCSR) ......................................................... 148 Status Flag Status Flag in Transmit/receive Mode ................ 233 Status Register Control Status Register ..................................... 127 Control Status Register (ADCS1) ...................... 195 Control Status Register (CSR)........................... 291 Control Status Register of Output Compare ......................................................... 133 EI2OS Status Register (ISCS).............................. 64 Flash Memory Control Status Register (FMCS) ......................................................... 364 Input Capture Control Status Register ................ 140 Program Address Detection Control Status Register (PACSR)............................................ 347 Serial Mode Control Status Register (SMCS) ......................................................... 264 Serial Status Register 1 (SSR1) ......................... 246 Status Register 0 (USR0) .................................. 217 Structure of Timer Control Status Register (TMCSR) ......................................................... 148 Status Transition Status Transition of Clock Selection .................. 100 Stepping Motor Controller Stepping Motor Controller Block Diagram ......................................................... 338 Stepping Motor Controller Registers.................. 339 Stop Asynchronous (Start-Stop Synchronized) Mode Data Transfer Format ......................... 252 Asynchronous (Start-Stop Synchronized) Mode Receive Operation............................... 252 Asynchronous (Start-Stop Synchronized) Mode Transmit Operation ............................. 252 Conditions for Canceling Bus Operation Stop (HALT=0).......................................... 294 Conditions for Setting Bus Operation Stop (HALT=1) ......................................................... 294 Example of EI2OS Activation in Stop Mode ......................................................... 206 Releasing Stop Mode ......................................... 95 INDEX Shift Operation Start/Stop Timing ..................... 274 State during Bus Operation Stop (HALT=1) .......................................................... 294 Stop Mode....................................................... 200 Transition to Stop Mode ..................................... 95 Watch-dog Stop ............................................... 120 Stop Mode Example of EI2OS Activation in Stop Mode .......................................................... 206 Releasing Stop Mode.......................................... 95 Stop Mode....................................................... 200 Transition to Stop Mode ..................................... 95 Storing Received Message Storing Received Message ................................ 325 Structure Structure of Extended Intelligent I/O Service (EI2OS) ............................................................ 61 Structure of Hardware Interrupt ........................... 53 Structure of Instruction Map ............................. 458 Structure of Software Interrupts........................... 58 Structure of Timer Control Status Register (TMCSR) .......................................................... 148 Suspending Erasing Suspending Erasing of Flash Memory Sectors .......................................................... 384 Switching Switching between External Interrupt and DTP Requests............................................. 184 Switching between Main Clock and PLL Clock ............................................................ 99 Symbols Description of Instruction Presentation Items and Symbols ............................................. 441 Synchronous Baud Rate CLK Synchronous Baud Rate............................ 223 Synchronous Mode CLK Synchronous Mode Data Transfer Format .......................................................... 253 Control Register Settings for CLK Synchronous Mode .......................................................... 254 End of Communication in CLK Synchronous Mode .......................................................... 254 Start of Communication in CLK Synchronous Mode .......................................................... 254 System Configuration System Configuration Example of the Address Match Detection Function .............................. 350 UART1 Sample Application (System Configuration in Mode 1) ............................................. 259 System Stack Pointer User Stack Pointer (USP) and System Stack Pointer (SSP) ................................................... 31 T TBTC Time-base Timer Control Register (TBTC) .........115 TCANR Transmission Cancel Register (TCANR) ............306 TCR Transmission Complete Register (TCR)..............307 Temporary Sector Protect Temporary Sector Protect Cancellation ...............484 TIER Transmission Interrupt Enable Register (TIER) ..........................................................308 Time-base Counter Time-base Counter ...........................................116 Time-base Timer Block Diagram of Time-base Timer ...................114 Outline of Time-base Timer...............................114 Time-base Timer Control Register (TBTC) .........115 Time-base Timer Control Register Time-base Timer Control Register (TBTC) .........115 Timer 16-bit Free-run Timer................................122, 124 16-bit Free-run Timer Block Diagram.................125 16-bit Free-run Timer Timing ............................130 16-bit I/O Timer Block Diagram ........................123 Activating the Watch-dog Timer ........................120 Block Diagram of 16-bit Reload Timer ...............146 Block Diagram of Time-base Timer ...................114 Operation of 16-bit Free-run Timer ....................129 Outline of 16-bit Reload Timer (With Event Count Function) ...............146 Outline of Time-base Timer...............................114 Register Layout of 16-bit Timer Register (TMR)/ 16-bit Reload Register (TMRLR) ..........151 Registers of 16-bit Reload Timer........................147 Releasing Timer Mode ........................................94 Sector Erase Timer Flag (DQ3)..........................374 Structure of Timer Control Status Register (TMCSR) ..........................................................148 Time-base Timer Control Register (TBTC) .........115 Transition to Timer Mode....................................94 Underflow Operation of 16-bit Reload Timer ..........................................................154 Watch-dog Timer Block Diagram ......................118 Watch-dog Timer Control Register (WDTC) ..........................................................118 Timer Control Status Register Structure of Timer Control Status Register (TMCSR) ..........................................................148 Timer Mode Releasing Timer Mode ........................................94 Transition to Timer Mode....................................94 509 INDEX Timer Register Register Layout of 16-bit Timer Register (TMR)/ 16-bit Reload Register (TMRLR).......... 151 Timing 16-bit Free-run Timer Timing............................ 130 Bit Timing Register (BTR)................................ 298 Flag Setting Timing in Receive Mode (Mode 0, Mode 1, or Mode 3).............. 230 Flag Setting Timing in Receive Mode (mode 2) .......................................................... 231 Flag Setting Timing in Send Mode..................... 232 Input Capture Input Timing ............................... 143 Output Compare Timing ................................... 137 RST and RY/BY Timing................................... 483 RY/BY Timing During Writing/Erasing ............. 482 Sample of Input Capture Fetch Timing ............... 142 Set Timing of Six Flags .................................... 229 Setting Bit Timing............................................ 328 Shift Operation Start/Stop Timing...................... 274 Timing Limit Exceeded Flag (DQ5) ................... 373 UART1 Interrupts and Flag Set Timing .............. 256 Timing Limit Exceeded Flag Timing Limit Exceeded Flag (DQ5) ................... 373 TMCSR Structure of Timer Control Status Register (TMCSR) .......................................................... 148 TMR Register Layout of 16-bit Timer Register (TMR)/ 16-bit Reload Register (TMRLR).......... 151 Toggle Bit Toggle Bit ....................................................... 482 Toggle Bit Flag (DQ6)...................................... 372 Toggle Bit-2 Flag (DQ2)................................... 375 Total Total Control Registers ..................................... 290 Transfer Data Format Transfer Data Format........................................ 227 Transfer Format Asynchronous (Start-Stop Synchronized) Mode Data Transfer Format.......................... 252 CLK Synchronous Mode Data Transfer Format .......................................................... 253 Transition Notes on the Transition to Low-power Mode ............................................................ 92 Status Transition of Clock Selection................... 100 Transition to Hardware Standby Mode ................. 97 Transition to Sleep Mode .................................... 93 Transition to Stop Mode...................................... 95 Transition to Timer Mode ................................... 94 Transmission CAN Controller Transmission Flowchart............ 324 Canceling a CAN Controller Transmission Request .......................................................... 323 Completing CAN Controller Transmission ......... 324 510 Procedure for Transmission by Message Buffer (x) ......................................................... 330 Starting Transmission....................................... 323 Transmission Cancel Register (TCANR)............ 306 Transmission Complete Register (TCR) ............. 307 Transmission Interrupt Enable Register (TIER) ......................................................... 308 Transmission Request Register (TREQR)........... 303 Transmission RTR Register (TRTRR) ............... 304 Transmission Cancel Register Transmission Cancel Register (TCANR)............ 306 Transmission Complete Register Transmission Complete Register (TCR) ............. 307 Transmission Flowchart CAN Controller Transmission Flowchart ........... 324 Transmission Interrupt Enable Register Transmission Interrupt Enable Register (TIER) ......................................................... 308 Transmission Request Register Transmission Request Register (TREQR)........... 303 Transmission RTR Register Transmission RTR Register (TRTRR) ............... 304 Transmit Asynchronous (Start-Stop Synchronized) Mode Transmit Operation ............................. 252 Receive and Transmit Error Counters (RTEC) ......................................................... 297 Status Flag in Transmit/receive Mode ................ 233 Transmit Error Counters Receive and Transmit Error Counters (RTEC) ......................................................... 297 Transmit Operation Asynchronous (Start-Stop Synchronized) Mode Transmit Operation ............................. 252 TREQR Transmission Request Register (TREQR)........... 303 TRTRR Transmission RTR Register (TRTRR) ............... 304 Types Address Generation Types .................................. 21 Bank Addressing Types ...................................... 24 Instruction Types ............................................. 420 U UART Block Diagram of UART0 ................................ 213 Features of UART1 .......................................... 238 Operating Modes of UART0 ............................. 222 Precautions for UART1 Use.............................. 260 Registers of UART0......................................... 214 UART0........................................................... 212 UART0 Application Example ........................... 234 UART1 Block Diagram .................................... 239 UART1 Clock Selection ................................... 249 INDEX UART1 Communication Flow Chart.................. 259 UART1 Flags .................................................. 255 UART1 Interrupt Sources ................................. 255 UART1 Interrupts and Flag Set Timing.............. 256 UART1 Operating Modes ................................. 249 UART1 Prescaler Control Register (U1CDCR) .......................................................... 248 UART1 Registers............................................. 240 UART1 Sample Application (System Configuration in Mode 1)......................................... 259 UART1 Prescaler Control Register UART1 Prescaler Control Register (U1CDCR) .......................................................... 248 UART1 Register UART1 Registers............................................. 240 UIDR Input Data Register 0 (UIDR0 ) and Output Data Register 0 (UODR0)............................ 219 UMC Serial Mode Control Register 0 (UMC0) ............ 215 Undefined Instruction Exception Due to Execution of an Undefined Instruction ............................................ 69 Execution of an Undefined Instruction ................. 69 Underflow Operation Underflow Operation of 16-bit Reload Timer .......................................................... 154 UODR Input Data Register 0 (UIDR0 ) and Output Data Register 0 (UODR0)............................ 219 URD Rate and Data Register 0 (URD0) ...................... 220 User Power Supply Example of Minimum Connection to the Flash Microcontroller Programmer (User Power Supply Used) .................. 404 Example of Serial Programming Connection (User Power Supply Used) ................... 400 User Stack Pointer User Stack Pointer (USP) and System Stack Pointer (SSP) ................................................... 31 USP User Stack Pointer (USP) and System Stack Pointer (SSP) ................................................... 31 USR Status Register 0 (USR0) .................................. 217 Reset Vector Address in Flash Memory ..............388 Verify Sector Protect Enable Sector Protect/Verify Sector Protect ........483 W Wait Time Setting the Oscillation Stabilization Wait Time ......................................................96, 97 Watch-dog Counter Watch-dog Counter...........................................120 Watch-dog Stop Watch-dog Stop................................................120 Watch-dog Timer Activating the Watch-dog Timer ........................120 Watch-dog Timer Block Diagram ......................118 Watch-dog Timer Control Register (WDTC) ..........................................................118 Watch-dog Timer Control Register Watch-dog Timer Control Register (WDTC) ..........................................................118 WDTC Watch-dog Timer Control Register (WDTC) ..........................................................118 WE Control Write, Data Polling, Read (WE Control) .............480 Write Detailed Explanation of Flash Memory Write/Erase ..........................................................377 Write, Data Polling, Read (CE Control) ..............481 Write, Data Polling, Read (WE Control) .............480 Writing Data Writing Data to the Flash Memory .....................379 Writing to the Flash Memory Writing to the Flash Memory .............................379 Writing to/Erasing Flash Memory Writing to/Erasing Flash Memory ......................358 X x Data Register x (x=0 to 15) (DTRx) ...................321 DLC Register x (x=0 to 15) (DLCRx).................320 ID Register x (x=0 to 15) (IDRx) .......................318 Procedure for Reception by Message Buffer (x) ..........................................................332 Procedure for Transmission by Message Buffer (x) ..........................................................330 V Vector Interrupt Vector List........................................... 47 511 INDEX 512 CM44-10106-5E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL F2MC-16LX 16-BIT MICROCONTROLLER MB90595 Series HARDWARE MANUAL October 2007 the fifth edition Published FUJITSU LIMITED Edited Business Promotion Dept. Electronic Devices