Corrections of Hardware Manual MB90820 hm90820-draftv1-1-corr-x1-01 © Fujitsu Microelectronics Europe GmbH Addendum, MB90820 Hardware Manual (hm90820-draftv1-1-corr-x1-01) This is the Addendum for the Hardware Manual hm90820-draftv1-1 of the MB90820 microcontroller series. It describes all known discrepancies of the MB90820 microcontroller series Hardware Manual. Ref. Number Date (Internal ref. number) Version Chapter/Page No. (Text Link) dd.mm.yy HWM90820001 HWM90820002 12.05.05 1.00 15.11.05 1.01 HWM90820003 15.11.05 1.01 hm90820-draftv1-1-corr-x1-01.doc Description/Correction Using UART-Reset Transition to standby mode, Standby Cancel failure behavior added F2MC-16LX ADC interrupt problem 1 / 3 HWM90820001 TOP Using the UART-Reset A UART-Reset clears all UART registers. After a UART-Reset the registers have to be reinitialised. Example: ;Config UART MOV I:SSR0, #000H ;No interrupt, LSB first MOV I:SCR0, #013H ;8-bit data, enable RX & TX, 1 stop bit ;mode 0 only allow 7-bit data MOV I:CDCR, #080H MOV I:SMR0, #01DH ;mode0, cs2~cs0=011, Use pin for UART, ;reset UART MOV I:SMR0, #019H ;Not reset UART MOV I:CDCR, #080H ;As reset stopped the prescaler, need to ;restart prescaler MOV I:SCR0, #013H ;8-bit data, enable RX & TX, 1 stop bit ;mode 0 only allow 7-bit data ;Should set SSR0 also. But the setting is also #00h HWM90820002 TOP Transition to standby mode The definition of Standby Cancel Failure is that the CPU will execute wrong instructions when an interrupt is executed during transition to Standby mode1 at a certain time. 1 :Definition of Standby mode Main sleep mode, PLL sleep mode, Sub-sleep mode Time base timer mode, Watch mode, Main watch mode Main stop mode, PLL stop mode, Sub-stop mode In the following cases, no problem occurs: -Standby mode is not used -Standby mode is released only by external reset For further information refer to ‘F2MC16-LX Standby Cancel Failure’ document. hm90820-draftv1-1-corr-x1-01.doc 2 / 3 HWM90820003 TOP F2MC-16LX ADC interrupt problem Under certain conditions the A/D conversion results may get corrupted. When the consecutive ADC operation is paused by the data protection function*1 at the time that the interrupt is cleared, the data protection function malfunctions under certain conditions. The result is that an unnecessary conversion completion interrupt occurs or the A/D conversion result that should be acquired is omitted once. Note that this problem does not occur in any of the following cases. • The A/D converter is not used. • The A/D converter is used with interrupt disabled. • The A/D converter is used with two or less analogue input channels in single-shot conversion mode. • The A/D converter is started by an external trigger or timer in conversion stop mode and used with two or less analogue input channels. • The A/D converter is started in the following procedure by software in conversion stop mode after the A/D conversion ends: (1) Reading A/D conversion data, (2) Clearing interrupt factors, (3) Starting the next A/D conversion. For further information refer to ‘F2MC-16LX ADC Interrupt Problem’ document. (CI-300003-E-V11-16LX_ADC_Interrupt_Problem.pdf) hm90820-draftv1-1-corr-x1-01.doc 3 / 3