HFA5251 Data Sheet September 1998 File Number 3689.4 800MHz Monolithic Pin Driver Features The HFA5251 is a very high speed monolithic pin driver solution for high performance test systems. The device will switch at high data rates between two input voltage levels providing variable amplitude pulses. The output impedance is trimmed to achieve a precision 50Ω source for impedance matching. Two differential ECL/TTL compatible inputs control the operation of the HFA5251, one controlling the VHIGH /VLOW switching and the other controlling the output’s high-impedance state. The HFA5251’s 800MHz data rate makes it compatible with today’s high-speed VLSI test systems and the +7V to -2V output swing allows testing of all common logic families. • High Digital Data Rate . . . . . . . . . . . . . . . . . . . . . 800MHz The HFA5251 is manufactured in Intersil’s proprietary complementary bipolar UHF-1 process. The HFA5251 is offered in die form. Contact your local sales representative for packaging options. • Very Fast Rise/Fall Times. . . . . . . . . . . . . . . . . . . . . 500ps • Wide Output Range . . . . . . . . . . . . . . . . . . . . . +7V to -2V • Precise 50Ω Output Impedance • High Impedance, Three-State Output Control Applications • IC Tester Pin Electronics • Pattern Generators • Pulse Generators • Level Comparator/Translator Pinout HFA5251 (DIE FORM) Functional Diagram INPUT BUFFER VHIGH VCC1 VHIGH VCC2 DATA DATA HiZ HiZ - DATA Q VCC2 DATA + 50Ω Q VOUT + VOUT - VEE2 VLOW HiZ VEE2 HiZ INPUT BUFFER VLOW VEE1 TRUTH TABLE FOR VOUT DATA 0 HiZ 1 0 VLOW VHIGH 1 HiZ HiZ 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HFA5251 Pin Descriptions NAME FUNCTION VCC1 Positive Supply. Nominal value is 10V ±0.2V. Reducing supply voltage below 9.8V will reduce positive output voltage swing. The total supply voltage from VCC1 to VEE1 should not exceed 15.6V for normal operation or exceed 17.0V to prevent damage. Intersil recommends two wire bonds to this pad to provide the lowest possible impedance. In addition, power supply decoupling chip capacitors of 470pF, 0.1µF and a 10µF tantalum are recommended. VEE1 Negative Supply. Nominal value is -5.2V ±0.2V. A supply voltage more positive than -5.0V will reduce negative output voltage swing. The total supply voltage from VCC1 to VEE1 should not exceed 15.6V for normal operation or exceed 17.0V to prevent damage. Intersil recommends two wire bonds to this pad to provide the lowest possible impedance. In addition, power supply decoupling chip capacitors of 470pF, 0.1µF and a 10µF tantalum are recommended. VCC2 Output Stage Positive Supply. Nominal voltage and cautions are the same as for VCC1. Having decoupling chip capacitors close to VCC2 and VEE2 is essential since large AC current will flow through this pad to the output during transients. Normally VCC1 and VCC2 are connected together close to the die and share decoupling capacitors. Intersil recommends two wire bonds for this pad. VEE2 Output Stage Negative Supply. Nominal voltage and cautions are the same as for VEE1. Having decoupling chip capacitors close to VCC2 and VEE2 is essential since large AC current will flow through this pad to the output during transients. Normally VEE1 and VEE2 are connected together close to the die and share decoupling capacitors. Intersil recommends two wire bonds for this pad. VHIGH Input Voltage High is used to set the output high level VOH. VHIGH is sensitive to capacitively coupled AC noise. Protection from high frequency noise can be achieved with a low pass filter consisting of a 50Ω chip resistor and a 470pF chip capacitor. Without this precaution the pin driver may oscillate due to feedback from the output through the PC board ground. VLOW Input Voltage Low is used to set the output low level VOL. VLOW is sensitive to capacitively coupled AC noise. Protection from high frequency noise can be achieved with a low pass filter consisting of a 50Ω chip resistor and a 470pF chip capacitor. Without this precaution the pin driver may oscillate due to feedback from the output through the PC board ground. VOUT Driver Output. The output impedance has been laser trimmed to match a 50Ω transmission line ±2Ω. Custom output impedance trimming is available (contact sales office for details) to provide the best match possible to your 50Ω system. DATA, DATA Differential Digital Inputs used to switch VOUT to the VHIGH or VLOW level. Intersil recommends this input pair be driven by complementary ECL signals to provide optimal switching speeds and timing accuracy. However a large Common Mode and Differential Voltage Range is provided to accommodate a variety of signals including single ended TTL and CMOS. When using single ended signals the other input must be tied to an appropriate threshold. HiZ, HiZ Differential Digital Inputs used to switch VOUT from an Active to a High Impedance State. Intersil recommends that this input pair be driven by complementary ECL signals to provide optimal switching speeds and timing accuracy. However a large Common Mode and Differential Voltage Range is provided to accommodate a variety of signals including single ended TTL and CMOS. When using single ended signals the other input must be tied to an appropriate threshold. 2 HFA5251 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17V Differential Input Voltage (DATA and HiZ) . . . . . . . . . . . . . . . . . . 5V Output Current Continuous (Note 1) . . . . . . . . . . . . . . . . . . . 160mA Input Voltage (Any pin except as specified) . . . . . . . . . . VCC to VEE VOUT Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to -5.5V VHIGH Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC to -3V VLOW Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to VEE VHIGH to VLOW Voltage. . . . . . . . . . . . . . . . . . . . . . .VHIGH > VLOW Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications VCC = +10V, VEE = -5.2V, VIH = -0.9V, VIL = -1.75V, Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP. (oC) MIN TYP MAX UNITS INPUT CHARACTERISTICS (VHIGH, VLOW) VHIGH Input Offset Voltage VOUT = 0V 25 -150 -50 +50 mV VLOW Input Offset Voltage VOUT = 0V 25 -150 -50 +50 mV VHIGH Input Bias Current VHIGH = -2.25V to +7.5V 25 -50 110 300 µA VLOW Input Bias Current VLOW = -2.5V to +7.25V 25 -300 -110 50 µA VHIGH Voltage Range 25 -2.25 - 7.5 V VLOW Voltage Range 25 -2.5 - 7.25 V VHIGH to VLOW Differential Voltage Range 25 0.25 - 10 V VHIGH /VLOW Interaction at 500mV (Note 11) 25 - 2 4 mV VHIGH /VLOW Interaction at 250mV (Note 11) 25 - 20 40 mV 25 -2 - 7 V LOGIC INPUT CHARACTERISTICS (DATA, DATA, HiZ, HiZ) Logic Input Voltage Range Logic Differential Input Voltage 25 0.4 - 5 V DATA/DATA Logic Input High Current VIH = 0V, VIL = -2V 25 -50 110 300 µA DATA/DATA Logic Input Low Current VIH = 0V, VIL = -2V 25 -700 -300 50 µA HiZ/HiZ Logic Input High Current VIH = 0V, VIL = -2V 25 -50 70 200 µA HiZ/HiZ Logic Input Low Current VIH = 0V, VIL = -2V 25 -300 -80 50 µA VHIGH = -1V to 6.5V 25 0.95 - 1 V/V TRANSFER CHARACTERISTICS VHIGH Voltage Gain VLOW Voltage Gain VLOW = -1.5V to 6V 25 0.95 - 1 V/V VHIGH /VLOW Linearity Error (Note 7) Fullscale = 5V 25 -0.5 - 0.5 % VHIGH /VLOW Linearity Error (Note 8) Fullscale = 8.5V 25 -0.75 - 0.75 % VHIGH /VLOW End Point Gain Deviation (Notes 10, 13) 0.5V Steps 25 -2.0 - 2.0 % VHIGH End Point Gain Error (Notes 10 and 14) VOUT = 6.7V to 7.0V 25 -20 - 20 mV VHIGH /VLOW -3dB Bandwidth 200mVP-P 25 - 100 - MHz SWITCHING CHARACTERISTICS (ZLOAD = 16 inches of RG-58 Terminated with 50Ω) Propagation Delay (Notes 2, 17) 25 0.8 - 1.5 ns 25 -100 - 100 ps Rising Edge Propagation Delay vs Duty Cycle (Notes 12, 17) 25 -120 -20 80 ps Falling Edge Propagation Delay vs Duty Cycle (Notes 12, 17) 25 -80 20 120 ps Active to HiZ Delay (Note 17) 25 1.2 1.7 2.2 ns HiZ to Active Delay (Note 17) 25 2.1 2.6 3.1 ns Propagation Delay Match (Notes 2, 17) Rising to Falling Edge TRANSIENT RESPONSE (ZLOAD = 16 inches of RG-58 Terminated with 5pF) Rise/Fall Time (20%-80%) 1VP-P 25 - 450 500 ps Rise/Fall Time (10%-90%) 3VP-P 25 - 890 1000 ps 3 HFA5251 Electrical Specifications VCC = +10V, VEE = -5.2V, VIH = -0.9V, VIL = -1.75V, Unless Otherwise Specified (Continued) PARAMETER Rise/Fall Time (10%-90%) (Note 6) TEST CONDITIONS 5VP-P Rise/Fall Time Match (Note 6) TEMP. (oC) MIN TYP MAX UNITS 25 - 1.5 1.7 ns 25 - 50 150 ps Minimum Pulse Width (Note 16) 1VP-P 25 - 1.0 - ns Minimum Pulse Width (Note 16) 3VP-P 25 - 1.2 - ns Minimum Pulse Width (Note 16) 5VP-P 25 - 2.0 - ns Overshoot/Undershoot/Preshoot 3VP-P 25 - 5 - % 25 - 10 - ns Data Settling Time to 1% (Note 3) OUTPUT CHARACTERISTICS VCC = 10V, VEE = -5.2V 25 -2 - 7 V At Other Supplies 25 VEE +3.2 - VCC -3.0 V DC Output Resistance - Active (Note 18) -2V to 7V 25 45 47 49 Ω Output Leakage - HiZ -2V to 7V 25 -100 ±10 100 nA Output Voltage Swing (No Load) Output Capacitance - HiZ 25 - 5 - pF Output Current - Active 25 70 100 - mA VHIGH 25 - 14 40 mV/V VLOW 25 - 14 40 mV/V Total Supply Current 25 90 94 96 mA Supply Current (ICC1, IEE1) 25 - 74 - mA POWER SUPPLY CHARACTERISTICS Power Supply Rejection Ratio (Note 4) Supply Current (ICC2, IEE2) 25 - 20 - mA Supply Voltage Range (Note 5) VCC 25 9.8 10 10.2 V Supply Voltage Range (Note 5) VEE 25 -5.4 -5.2 -5.0 V Supply Voltage Differential VCC - VEE 25 12 - 15.6 V Power Dissipation No Load At VCC = 10V, VEE = -5.2V 25 - - 1.46 W NOTES: 1. Internal Power Dissipation may limit Output Current below 160mA. 2. 3V Step, 50% duty cycle, 200ns period. 3. 3V Step, measured from 50% of input to ±1% of reference value at 50ns. 4. VHIGH = 2.6V, VLOW = 2.3V, VCC = 9V to 10V, VEE = -4.2V to -5.2V 5. Minimum/maximum output swing will vary with supply voltage. 6. 5V Step, 50% duty cycle, 100ns period. 7. For VHIGH = 0V to 5V, For VLOW = 0V to 5V, Fullscale = 5V, 0.1% = 5mV. 8. For VHIGH = -1.5V to 7V, For VLOW = -2.0V to 6.5V, Fullscale = 8.5V, 0.1% = 8.5mV 9. Shorting the output to a voltage outside the specified range may damage the output. 10. VCC = 9.9V, VEE = -5.1V. 11. VHIGH to VLOW Interaction is measured as the change in VOUT (the active channel) due to a change in the inactive channel. VHIGH Interaction at 250mV is measured as the deviation from 1V as VLOW is changed from 0V to 750mV (Referred to VOUT). VLow Interaction at 250mV is measured as the deviation from 0V as VHIGH is changed from 1V to 250mV (Referred to VOUT). 12. 0V to 3V Step, 200ns period, Pulse Width is varied from 5ns to 195ns. 13. End Point Gain Deviation is the percent deviation of Gain calculated in 0.5V steps at the extremes of output voltage range. For example in the VHIGH range 5.7V to 6.7V, Gain is calculated for VHIGH = 5.7V to 6.2V (Note 15) and VHIGH = 6.2V to 6.7V (Note 15) the difference in gain is calculated and converted to a percentage. The voltage ranges tested are: VHIGH = -1.5V to -0.5V (Note 15) and 5.7V to 6.7V (Note 15), VLOW = -2.0V to -1.0V (Note 15) and 5.5V to 6.5V (Note 15). 14. VHIGH End Point Gain Error is the VOUT absolute error from ideal for a VHIGH change from 6.7V to 7.0V (Note 15). 15. Input voltages VHIGH and VLOW are corrected for Offset Voltage and 7.5V Full Scale Gain Error. 16. Minimum Pulse Width is measured 50% to 50% of specified amplitude with pulse peak at 90% of amplitude. 17. Test is performed into a 50Ω load with a 3V step. Measurement is made from the 50% of input to 50% of output. 18. Dynamic Output Resistance will be higher (typical 48.5Ω) than DC Output Resistance. 4 HFA5251 Application Information The HFA5251 is a pin driver designed for use in automatic test equipment (ATE) and high speed pulse generators. Pin drivers, especially those with very high-speed performance, have generally been implemented with discrete transistors (sometimes GaAs) on a circuit board or in a hybrid. Recent IC process improvements, specifically Intersil's UHF1 process [1], have enabled the manufacturing of this 800MHz silicon monolithic pin driver. The ultra high speed performance of the HFA5251 is a result of UHF1 process leverages: low parasitic collector-tosubstrate capacitance of the bonded wafer, low collector-tobase parasitic capacitance of the self-aligned base/emitter technology and ultra high fT NPN (8GHz) and PNP (5.5GHz) poly-silicon transistors. Functional Block Diagram The HFA5251 functional block diagram is shown in Figure 1. VHIGH offset and offset drift. Stacking two emitter-base junctions allows the VHIGH to VLOW range to be extended to two BVebo's of the process. The speed of the pin driver is largely determined by the current flowing through the switch stage and the collector-base capacitance of the output stage transistors connected to the node VSO. The output stage consists of cascaded emitter followers constructed in a typical push-pull manner as shown in Figure 2. However, transdiodes are added to increase the voltage breakdown characteristics of the output during high impedance mode. HiZ and HiZ control the mode of the output stage. A trimmed, NiCr resistor is added to provide the 50Ω output impedance. Overall, a symmetry of device types and paths is constructed to improve slew and delay symmetry. Both the VHIGH to VOUT path and the VLOW to VOUT path contain three NPN and three PNP transistors operating at similar collector currents. Thus the transient response of VHIGH to VLOW and VLOW to VHIGH are kept symmetrical. Also, a trimmable current reference (not shown) allows the AC parameters to be adjusted to maintain unit to unit consistency. 50Ω DATA VOUT DATA VLOW HiZ HiZ FIGURE 1. BLOCK DIAGRAM The control inputs, DATA and DATA, determine the output level. If DATA is at logic “1” and DATA is at logic “0”, the output level will be the same as VHIGH. If DATA is at logic “0” and DATA is at logic “1”, the output will be the same as VLOW. The control inputs, HiZ and HiZ, make the output either active or high-impedance. If HiZ is at logic “1” and HiZ is at logic “0”, the output will be in high impedance mode. If HiZ is at logic “0” and HiZ is at logic “1”, the output will be enabled. The output impedance in the enabled mode is trimmed to 50Ω. Circuit Schematic The Pin Driver circuit consists of a switch, an output buffer, and two differential control elements as shown in Figure 2. A two stage approach, separating the switch from the output buffer, allows the speed and accuracy requirements of the switch to be de-coupled from the load driving capability of the buffer. The patent pending switch circuitry[2] uses cascaded emitter followers as input buffers and also to switch the input VHIGH and VLOW to node VSO. Dual differential pairs controlled by the data timing (DATA and DATA) direct current to select either the VHIGH or VLOW switch. Matching transistor types and transdiodes improve linearity and lowers the voltage 5 Speed Advantage Intersil Pin Drivers on bonded-wafer technology definitely have a speed advantage, coming from the low collector-tosubstrate capacitance and the high fT of the transistors. In addition, the patent-pending switching stage which fits uniquely to Intersil's UHF1 process is another big contributor for the high speed. This switching circuitry requires low seriesresistance NPN and PNP transdiodes available in UHF1. The rise and fall times of the pin driver are largely determined by the slew rate at the node VSO in Figure 2. The dominant mechanism for the slew rate is the charging/discharging of the collector-base capacitors of the transistors connected to the node VSO. The charging/discharging currents are coming from the switching stage current sources. The fast rise and fall times are achieved because of the negligible collector-tosubstrate capacitance and the small base-collector capacitance due to the self-aligned recessed oxide [1]. HFA5251 VHIGH /VLOW CONTROL VCC1 SWITCHING STAGE OUTPUT STAGE VCC2 HIZ CONTROL HIZ HIZ DATA DATA VLOW VHIGH VOUT VSO VEE1 VEE2 FIGURE 2. CIRCUIT SCHEMATIC higher power supply current. Currently the pin driver has rise/fall times of less than 1ns (10% to 90% of 5VP-P) when ICC is trimmed to 125mA. Further speed enhancement will be made if there is a market demand. 7V 2.2V/DIV. 5V 3V Basic ATE System Application 1V 0V -2V 411ns 2ns/DIV. 431ns FIGURE 3. OUTPUT RESPONSE WITH VARIOUS VLOW AND VHIGH CONDITIONS The DATA/DATA differential stage is not a factor for the speed if its current sources have enough current not to bottleneck the transient. However it should be noted that the propagation delay mismatch is determined by this stage. Sufficient current is allocated to the differential stage current sources to best match the low-to-high and high-to-low transient propagation delays. Figure 3 shows various output responses, 0V to 1V, 0V to 3V, 0V to 5V, and -2V to 7V (full swing). The load condition is a 16 inch 50Ω SMA cable with a 5pF capacitor at the end of the cable. The rise/fall time with 5VP-P is typically 1.45ns for the HFA5251. Pin drivers, built out of the same circuit structure as shown in Figure 2, can be made faster by trimming for a 6 Figure 3 shows a pin driver in a typical per-pin ATE system. The pin driver works closely with the dual-level comparator and the active load. When the DUT pin acts as an input waiting for a series of digital signals, the pin driver becomes active with a logic “0” applied on the HiZ pin and provides the DUT pin with digital signals. When the DUT pin acts as an output, the pin driver output will be in high impedance mode (HiZ) with a logic “1” applied to the “HiZ” pin of the pin driver. During this high impedance mode the pin driver presents a capacitance of less than 5pF to the DUT. Special care has to be taken to match the impedance (to 50Ω) at the pin driver output to minimize reflections. The dual level comparator detects the logic levels of the DUT pin when it acts as an output. The comparator has two threshold level inputs, VCH and VCL. The logic level information of DUT pin output is sent to the edge/window comparator through the dual level comparator. The edge/window comparator interprets this information in terms of corresponding transient performance in conjunction with the timing information. Thus it detects any possible failure transients. HFA5251 chip capacitors and chip resistors. Figures 5 and 6 refer to a proven decoupling circuit currently working in the lab and a 1X scale film of its associated PC board (metal level). The formatter sends a sequence of digital information to the pin driver which contains logic information over time. The active load is enabled when the DUT pin acts as an output. It simulates the load of the DUT pin by sinking or sourcing programmed current. Finally the sequencer controls the overall activities of the automatic testing. The control pins, DATA, DATA, HiZ, and HiZ are fed ECL signals through 50Ω micro-strip lines terminated with 50Ω for impedance matching since the input impedance at these pins is much higher than 50Ω. At the end of the micro-strip lines there is usually a high-speed pulse generator with an output impedance of 50Ω. A 50Ω micro-strip line is connected to each of the pins, DATA and HiZ through a 50Ω chip resistor to monitor the pulse signals. Decoupling Circuit for Oscillation-Free Operation To insure the oscillation-free operation in ATE or pulse generator applications, the pin driver needs an appropriate decoupling circuit on a printed circuit board which consists of CLOCK, START ACTIVE LOAD TIMING HiZ DATA MEMORY 50Ω FORMATTER DUT DATA DATA MEMORY PIN DRIVER EDGE/ WINDOW COMPARATOR VCH VCL DUAL LEVEL COMPARATOR FAIL FAIL MEMORY SEQUENCER TIMING FIGURE 4. TYPICAL ATE SYSTEM VHIGH 50Ω VCC 470pF 470pF PIN 1 0.1µF µ- STRIP VHIGH VCC1 VHIGH VCC1 10µF 50Ω µ- STRIP DATA 100Ω µ- STRIP VCC2 DATA VCC2 VOUT 50Ω VOUT µ- STRIP HiZ VEE2 50Ω µ- STRIP µ- STRIP 470pF FIGURE 6. 1X FILM OF THE EVALUATION BOARD METAL VEE2 HiZ VEE 50Ω 100Ω µ- STRIP 470pF 0.1µF VLOW VEE1 VEE1 V LOW 50Ω VLOW 470pF 470pF 10µF GROUND FIGURE 5. DECOUPLING CIRCUIT OF 28 PIN SOIC HFA5251 FOR OSCILLATION-FREE OPERATION 7 The two input voltage pins, VHIGH and VLOW, need to be protected from any capacitively coupled AC noise. Normally this protection can be achieved by having a low pass filter consisting of a 50Ω chip resistor and a 470pF chip capacitor. Without this protection circuit the pin driver may oscillate due to signals fed back from the output through the PC board ground. The power supply pins, VCC1, VCC2, VEE1, and VEE2, require decoupling chip capacitors of 470pF, 0.1µF, 10µF. Having decoupling capacitors close to VCC2 and VEE2 is HFA5251 essential since large AC current will flow through either VCC2 or VEE2 during transients. The output of the pin driver is usually connected to the device-under-test (DUT) through 50Ω micro-strip line and coaxial cable which carries the signal to a high input impedance DUT pin. References 1. Chris K. Davis et. al., “UHF1: A High Speed Complementary Bipolar Analog Process on SOI,” Bipolar Circuits and Technology Meeting Proceedings, pp260-263, October 1992. 8.5V. Data is measured at 0.5V steps from -1.5V to 7V for VHIGH and -2V to 6.5V for VLOW. The Linearity Error equation is as follows for 8.5V fullscale: V OUT V OUT ( IDEAL ) = ---------------- – OFFSET GAIN V OUT – V OUT ( IDEAL ) LINEARITYERROR = -------------------------------------------------------------8.5 The Linearity Error equation is as follows for 5V fullscale: V OUT – V OUT ( IDEAL ) LINEARITY ERROR = -------------------------------------------------------------5 2. Donald K. Whitney Jr., “Symmetrical, High Speed, Voltage Switching Circuit,” United States Patent Pending, Filed November 1991. Linearity Error is calculated for every data point in the range and the worst case value is recorded. Definition of Terms End Point Deviation VOH and VOL Output High Voltage and Output Low Voltage. VOH is the voltage at VOUT when the HiZ input is Low and the DATA input is High. VOL is the voltage at VOUT when HiZ is Low and DATA is Low. The VOH and VOL levels are set with the VHIGH and VLOW inputs respectively. Offset Voltage Offset Voltage is the DC error between the voltage placed on VHIGH or VLOW and the resulting VOH and VOL. VHIGH Offset Voltage Error is obtained by measuring VOH with VHIGH set to 0V and VLOW set to -2.5V to minimize interaction effects. VLOW Offset Voltage Error is the measurement of VOL with VLOW set to 0V and VHIGH set to +7.5V. End Point Deviation is the percent change of gain in the 1V range at the extremes of output voltage. Gain is calculated for each 0.5V step and then compared to the adjacent step for a percentage change. This specification is designed to quantify the amount of curvature present at the end points of output swing. VHIGH and VLOW inputs are corrected for gain and offset to provide more accurate VOH and VOL levels. For example VOH End Point Deviation is tested in the range 5.7V to 6.7V as shown below: V OH ( V HIGH at 6.7V ) – V OH ( V HIGH at 6.2V ) GAIN 6.7 – 6.2 = -------------------------------------------------------------------------------------------------------------------------0.5 V OH ( V HIGH at 6.2V ) – V OH ( V HIGH at 5.7V ) GAIN 6.2 – 5.7 = -------------------------------------------------------------------------------------------------------------------------0.5 END POINT DEVIATION = GAIN 6.7 – 6.2 – GAIN 6.2 – 5.7 × 100 Gain Gain is defined as the ratio of output voltage change to input voltage change for a defined range. VHIGH Gain is calculated with the following equation with VLOW fixed at -2.5V End Point Gain Error V OH ( V HIGH at 6.5V ) – V OH ( V HIGH at -1V ) V HIGH GAIN = ----------------------------------------------------------------------------------------------------------------------7.5 End Point Gain Error (EPGE) is the VOUT absolute error in millivolts for a VHIGH change from 6.7V to 7V. The VHIGH input is corrected for gain and offset to provide a more accurate VOH level. VLOW Gain is calculated in a similar manner. EPGE = VOH (VHIGH at 7V) - VOH (VHIGH at 6.7V) - 0.3 V OL ( V LOW at 6V ) – V OL ( V LOW at -1.5V ) V LOW GAIN = -----------------------------------------------------------------------------------------------------------------7.5 VHIGH is held fixed at 7.5V. These Gain calculations minimize the effects of Interaction and End Point Nonlinearities. Linearity Error Linearity Error is a measure of output voltage worst case deviation from a straight line that has been corrected for offset and 7.5V Gain. Linearity Error is given as a percentage of fullscale and is done in two ranges 5V and 8 VHIGH to VLOW Interaction VHIGH to VLOW Interaction is the change in VOUT (the active channel) due to the inactive channel. VHIGH Interaction is measured as the change in VOH from 1V as VLOW is moved from 0V to 750mV (VLOW is corrected for gain and offset errors). VLOW Interaction is measured as the change in VOL from 0V as VHIGH is moved from 1V to 250mV (with VHIGH corrected for gain and offset errors). The minimum recommended difference between VHIGH and VLOW for the HFA5251 is 250mV. HFA5251 Typical Performance Curves DISCONTINUITY REFLECTION 1000 4 800 OUTPUT (mV) OUTPUT (V) 5 3 2 1 0 600 400 200 0 DISCONTINUITY REFLECTION ZLOAD = 16 INCHES OF RG-58 INTO 1kΩ 0 ZLOAD = 16 INCHES OF RG-58 INTO 1kΩ 25 TIME (ns) 0 50 25 50 TIME (ns) FIGURE 7. LARGE SIGNAL RESPONSE FIGURE 8. SMALL SIGNAL RESPONSE 3 VHIGH (ACTIVE) 3 GAIN ERROR (%) OUTPUT (V) 2 2 1 0 1 0 -1 -2 1.087ns -3 VLOW (ACTIVE) 0 2.5 TIME (ns) -4 5 -3 FIGURE 9. MINIMUM PULSE WIDTH -2 -1 0 1 2 3 VIN (V) 4 5 6 7 8 1 1.1 FIGURE 10. GAIN ERROR (FULLSCALE = 8.5V) 0.01 1.06 MINIMUM RECOMMENDED VHIGH TO VLOW VOLTAGE 1.05 0 1.03 VOUT (V) VOUT (V) 1.04 1.02 1.01 -0.01 -0.02 1 MINIMUM RECOMMENDED VHIGH TO VLOW VOLTAGE -0.03 0.99 0.98 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VLOW INPUT (V) FIGURE 11. VHIGH /VLOW INTERACTION, VHIGH ACTIVE (NOMINAL 1.0V) 9 1 -0.04 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 VHIGH INPUT (V) 0.8 0.9 FIGURE 12. VHIGH /VLOW INTERACTION, VLOW ACTIVE (NOMINAL 0.0V) HFA5251 Die Characteristics DIE DIMENSIONS: 2670µm x 1730µm x 525µm PASSIVATION: Nitride, 4kÅ ±0.5kÅ METALLIZATION: Type: Metal 1: Cu (2%) SiAl/TiW Thickness: Metal 1: 8kÅ ±0.4kÅ Backside: Gold TRANSISTOR COUNT: 115 SUBSTRATE POTENTIAL: Type: Metal 2: Cu (2%) Al Floating Thickness: Metal 2: 16kÅ ±0.8kÅ Metallization Mask Layout HFA5251 VHIGH VCC1 DATA VCC2 DATA VOUT HiZ VEE2 HiZ VLOW VEE1 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 10 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029