AD AD8391AR-REEL

a
xDSL Line Driver
3 V to 12 V with Power-Down
AD8391
FEATURES
Ideal xDSL Line Driver for VoDSL or Low Power
Applications such as USB, PCMCIA, or PCI-Based
Customer Premise Equipment (CPE)
High Output Voltage and Current Drive
340 mA Output Drive Current
Low Power Operation
3 V to 12 V Power Supply Range
1-Pin Logic Controlled Standby, Shutdown
Low Supply Current of 19 mA (Typical)
Low Distortion
–82 dBc SFDR, 12 V p-p into Differential 21 @ 100 kHz
4.5 nV/√Hz Input Voltage Noise Density, 100 kHz
Out-of-Band SFDR = –72 dBc, 144 kHz to 500 kHz,
ZLINE = 100 , PLINE = 13.5 dBm
High Speed
40 MHz Bandwidth (–3 dB)
375 V/s Slew Rate
PIN CONFIGURATION
8-Lead SOIC
(Thermal Coastline)
VS
IN1 1
PWDN 2
VMID
VS
IN2
7
VMID
6
–VS
5
VOUT2
+VS 3
VOUT1
8
4
AD8391
APPLICATIONS
VoDSL Modems
xDSL USB, PCI, PCMCIA Cards
Line Powered or Battery Backup xDSL Modems
The AD8391 consists of two parallel, low cost xDSL line drive
amplifiers capable of driving low distortion signals while running on
both 3 V to 12 V single-supply or equivalent dual-supply rails. It is
primarily intended for use in single-supply xDSL systems where low
power is essential, such as line powered and battery backup systems.
Each amplifier output drives more than 250 mA of current while
maintaining –82 dBc of SFDR at 100 kHz on 12 V, outstanding
performance for any xDSL CPE application.
The AD8391 provides a flexible power-down feature consisting of
a 1-pin digital control line. This allows biasing of the AD8391 to
full power (Logic “1”), Standby (Logic “tri-state” maintains low
amplifier output impedance), and Shutdown (Logic “0” places
amplifier outputs in a high impedance state). PWDN is referenced to –VS.
Fabricated on ADI’s high-speed XFCB process, the high bandwidth
and fast slew rate of the AD8391 keep distortion to a minimum,
while dissipating a minimum of power. The quiescent current of the
AD8391 is low; 19 mA total static current draw. The AD8391
comes in a compact 8-lead SOIC “Thermal Coastline” package, and
operates over the temperature range –40°C to +85°C.
UPSTREAM POWER – 10dB/DIV
PRODUCT DESCRIPTION
EMPTY BIN
25
137.5
250
FREQUENCY – kHz
Figure 1. Upstream Transit Spectrum with Empty Bin
at 45 kHz; Line Power = 12.5 dBm into 100 Ω
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD8391–SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
0.1 dB Bandwidth
Large Signal Bandwidth
Slew Rate
Rise and Fall Time
Settling Time
NOISE/HARMONIC
PERFORMANCE
Distortion, G = –5 (RG = 178 Ω)
2nd Harmonic
3rd Harmonic
MTPR (In-Band)
SFDR (Out-of-Band)
Input Noise Voltage
Input Noise Current
Crosstalk
DC PERFORMANCE
Input Offset Voltage
(@ 25C, VS = 12 V, RL = 10 , VMID = VS /2, G = –2, RF = 909 , RG = 453 ,
unless otherwise noted. See TPC 1 for Basic Circuit Configuration.)
Conditions
Min
INPUT CHARACTERISTICS
Input Resistance
Input Bias Current
Input Bias Current Match
CMRR
Input CM Voltage Range
VMID Accuracy
VMID Input Resistance
VMID Input Capacitance
OUTPUT CHARACTERISTICS
Output Resistance
Output Resistance
Output Voltage Swing
Linear Output Current
Short Circuit Current
POWER SUPPLY
Supply Current
STBY Supply Current
SHUTDOWN Supply Current
Operating Range
Power Supply Rejection Ratio
LOGIC INPUT (PWDN)
Logic “1” Voltage
Logic “0” Voltage
Logic Input Bias Current
Turn On Time
Max
Unit
G = –1, VOUT < 0.4 V p-p, RG = 909 Ω
G = –2, VOUT < 0.4 V p-p
VOUT < 0.4 V p-p
VOUT = 4 V p-p
VOUT = 4 V p-p
VOUT = 4 V p-p
0.1%, VOUT = 2 V p-p
40
38
4
50
375
8
60
MHz
MHz
MHz
MHz
V/µs
ns
ns
VOUT = 8 V p-p (Differential)
100 kHz, RL = 21 Ω
100 kHz, RL = 21 Ω
25 kHz to 138 kHz, RL = 21 Ω
144 kHz to 500 kHz, RL = 21 Ω
f = 100 kHz Differential
f = 100 kHz
f = 1 MHz, G = –2, Output to Output
–82
–95
–70
–72
4.5
9
64
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
dB
±2
±3
±2
± 0.25
± 0.35
10
VMID = +VS/2
TMIN to TMAX
VMID = “Float”
Input Offset Voltage Match
Transimpedance
Typ
TMIN to TMAX
∆VOUT = 5 V
In1, In2 pins
In1 – In2
VMID = VIN = 5.5 V to 6.5 V, ∆VOS /∆VIN, cm
VMID = “Float” Delta from +VS/2
Frequency = 100 kHz, PWDN “1”
Frequency = 100 kHz, PWDN “0”
RLOAD = 100 Ω
SFDR < –75 dBc, f = 100 kHz, RL = 21 Ω
PWDN = “1”
TMIN to TMAX
PWDN = “Open or Three-State”
PWDN = “0”
Single Supply
VMID = VS /2, ∆VS = ± 0.5 V
± 15
± 2.6
125
2.5
10
± 0.5
±6
48
1.2 to 10.8
±5
± 30
2.5
10
Ω
µA
µA
dB
V
mV
kΩ
pF
0.3
3
Ω
kΩ
V
mA
mA
0.1
11.9
340
1500
16
19
22
10
4
3.0
21
6
12
55
–VS + 2.0
RL = 21 Ω, IS = 90% of Typical
mV
mV
mV
mV
mV
MΩ
± 300
200
–VS + 0.8
mA
mA
mA
mA
V
dB
V
V
µA
ns
Specifications subject to change without notice.
–2–
REV. 0
AD8391
V = 3 V, R = 10 , V = V /2, G = –2, R = 909 , R = 453 , unless otherwise noted.
SPECIFICATIONS (@See25C,
TPC 1 for Basic Circuit Configuration.)
S
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
0.1dB Bandwidth
Large Signal Bandwidth
Slew Rate
Rise and Fall Time
Settling Time
NOISE/HARMONIC
PERFORMANCE
Distortion
2nd Harmonic
3rd Harmonic
Input Noise Voltage
Input Noise Current
DC PERFORMANCE
Input Offset Voltage
L
MID
S
F
Conditions
G
Min
INPUT CHARACTERISTICS
Input Resistance
Input Bias Current
Input Bias Current Match
CMRR
Input CM Voltage Range
VMID Accuracy
VMID Input Resistance
VMID Input Capacitance
OUTPUT CHARACTERISTICS
Output Resistance
Output Resistance
Output Voltage Swing
Linear Output Current
Short Circuit Current
POWER SUPPLY
Supply Current
STBY Supply Current
SHUTDOWN Supply Current
Operating Range
Power Supply Rejection Ratio
LOGIC INPUTS (PWDN [1,0])
Logic “1” Voltage
Logic “0” Voltage
Logic Input Bias Current
Turn On Time
Unit
37
36
3.5
30
50
15
110
MHz
MHz
MHz
MHz
V/µs
ns
ns
VOUT = 4 V p-p (Differential)
100 kHz, RL = 21 Ω
100 kHz, RL = 21 Ω
f = 100 kHz Differential
f = 100 kHz
–81
–97
4.5
9
dBc
dBc
nV/√Hz
pA/√Hz
±3
±4
±3
± 0.1
± 0.2
8
VMID = +VS/2
TMIN to TMAX
VMID = “Float”
TMIN to TMAX
∆VOUT = 1 V
In1, In2 pins
In1 – In2
VMID = VIN = 1.3 V to 1.5 V, ∆VOS /∆VIN, cm
VMID = “Float,” Delta from +V S /2
Frequency = 100 kHz, PWDN “1”
Frequency = 100 kHz, PWDN “0”
RL = 100 Ω
SFDR < –82 dBc, f = 100 kHz, RL = 21 Ω
PWDN = “1”
TMIN to TMAX
PWDN = “Open or Three-State”
PWDN = “0”
Single Supply
VMID = VS/2, ∆VS = ± 0.5 V
± 15
± 2.6
Ω
µA
µA
dB
V
mV
kΩ
pF
0.2
9
Ω
kΩ
V
mA
mA
0.1
2.9
125
1000
13
RL = 21 Ω, IS = 90% of Typical
–3–
mV
mV
mV
mV
mV
MΩ
125
1
7
± 0.5
±4
48
1.2 to 2.1
±5
± 30
2.5
10
16
19
8
1
3.0
18
2
12
55
–VS + 2.0
Specifications subject to change without notice.
REV. 0
Max
G = –1, VOUT < 0.4 V p-p
G = –2, VOUT < 0.4 V p-p
VOUT < 0.4 V p-p
VOUT = 2 V p-p
VOUT = 2 V p-p
Differential, VOUT = 1 V p-p
0.1%, VOUT = 2 V p-p
Input Offset Voltage Match
Transimpedance
Typ
± 60
200
–VS + 0.8
mA
mA
mA
mA
V
dB
V
V
µA
ns
AD8391
ABSOLUTE MAXIMUM RATINGS 1
MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
Internal Power Dissipation2
Small Outline Package (R) . . . . . . . . . . . . . . . . . . . 650 mW
Input Voltage (Common-Mode) . . . . . . . . . . . . . . . . . . . . ± VS
Logic Voltage, PWDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curve
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
The maximum power that can be safely dissipated by the
AD8391 is limited by the associated rise in junction temperature.
The maximum safe junction temperature for a plastic encapsulated device is determined by the glass transition temperature of
the plastic, approximately 150°C. Temporarily exceeding this
limit may cause a shift in parametric performance due to a change
in the stresses exerted on the die by the package.
To ensure proper operation, it is necessary to observe the maximum power derating curve.
ORDERING GUIDE
Model
AD8391AR
AD8391AR–REEL
AD8391AR–REEL7
AD8391AR–EVAL
Temperature
Range
Package
Description
–40°C to +85°C 8-Lead Plastic
SOIC
–40°C to +85°C 8-Lead SOIC
–40°C to +85°C 8-Lead SOIC
Evaluation Board
Package
Option
SO-8
2.0
TJ = 150C
MAXIMUM POWER DISSIPATION – W
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device on a four-layer board in free air at 85°C: 8-Lead SOIC
package: ␪JA = 100°C/W.
1.5
8-LEAD SOIC PACKAGE
1.0
0.5
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70
AMBIENT TEMPERATURE – C
SO-8
SO-8
SO-8
80 90
Figure 2. Plot of Maximum Power Dissipation
vs. Temperature
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8391 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
Typical Performance Characteristics–AD8391
0.4
VS = 1.5V
G = –2
RL = 10
CF
0.3
CF = 0pF
RF
VOUT
~
VIN
0.2
OUTPUT VOLTAGE – V
RG
RL
VMID
0.1F
0.1F
0.1F
+
+
+VS
6.8F
0.1
CF = 3pF
0
–0.1
–0.2
6.8F
–0.3
–VS
–0.4
0
25
50
75
100
125
150
175
200
225
250
TIME – ns
TPC 4. Small Signal Step Response
TPC 1. Single-Ended Test Circuit
2.0
0.4
VS = 6V
G = –2
RL = 10
0.3
CF = 0pF
CF = 0pF
1.0
OUTPUT VOLTAGE – V
OUTPUT VOLTAGE – V
0.2
0.1
CF = 3pF
0
–0.1
0.5
CF = 3pF
0
–0.5
–0.2
–1.0
–0.3
–1.5
–0.4
0
VS = 1.5V
G = –2
RL = 10
1.5
–2.0
25
50
75
100
125
150
175
200
225
0
250
25
50
75
100
125
150
175
200
225
250
TIME – ns
TIME – ns
TPC 5. Large Signal Step Response
TPC 2. Small Signal Step Response
0.01
4
3
VS = 6V
G = –2
RL = 10
CF = 0pF
VS = 6V
0.008
G = –2
0.006
OUTPUT ERROR – V
OUTPUT VOLTAGE – V
2
CF = 3pF
1
0
–1
0.004
VIN = 1V p-p
0.002
0
–0.002
OUTPUT ERROR
–0.004
–2
–0.006
–3
–0.008
–0.01
–4
0
25
50
75
100
125
150
175
200
225
0
250
TPC 3. Large Signal Step Response
REV. 0
50
100
150
200
TIME – ns
TIME – ns
TPC 6. 0.1% Settling Time
–5–
250
300
AD8391
12
6
VS = 6V
RL = 10
G = –2
9
0
OUTPUT VOLTAGE – dBV
OUTPUT VOLTAGE – dBV
6
3
0
–3
–6
–9
–3
–6
–9
–12
–15
–12
–18
–15
–21
–18
0.1
1
10
VS = 1.5V
RL = 10
G = –2
3
100
–24
0.1
1000
1
10
FREQUENCY – MHz
TPC 7. Output Voltage vs. Frequency
1200
VS = 6V
VS = 1.5V
OUTPUT SATURATION VOLTAGE – m V
1250
VOH @+85C
VOH @+25C
VOH @–40C
1000
750
500
VOL @+85C
VOL @+25C
250
VOL @–40C
100
VOH @+85C
[email protected] –40C
VOH @+25C
VOH @ –40C
800
600
400
200
[email protected] +25C
[email protected]+85C
0
0
0
100
200
300
400
500
600
700
800
900 1000
0
50
100
150
LOAD CURRENT – mA
250
300
350
400
450
500
TPC 11. Output Saturation Voltage vs. Load
TPC 8. Output Saturation Voltage vs. Load
18
18
VS = 6V
RL = 10
G = 2
15
12
VS = 1.5V
RL = 10
G = 2
15
12
STANDBY
STANDBY
9
9
6
3
0
6
3
0
FULL POWER
–3
–3
–6
–6
–9
0.1
200
LOAD CURRENT – mA
GAIN – dB
OUTPUT SATURATION VOLTAGE – m V
1000
TPC 10. Output Voltage vs. Frequency
1500
GAIN – dB
100
FREQUENCY – MHz
1
10
100
–9
0.1
1000
FULL POWER
1
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
TPC 12. Small Signal Frequency Response
TPC 9. Small Signal Frequency Response
–6–
REV. 0
AD8391
60
140
120
CURRENT NOISE – pA/ Hz
VOLTAGE NOISE – nV/ Hz
50
VS = 6V
40
30
20
VS = 1.5V
10
0
VS = 1.5V
100
80
60
40
20
10
100
1k
10k
100k
VS = 6V
0
10
1M
100
1k
FREQUENCY – Hz
10k
TPC 13. Voltage Noise vs. Frequency (RTI)
10k
VS = 6V
VS = 1.5V
1k
POWER-DOWN
OUTPUT IMPEDANCE – OUTPUT IMPEDANCE – 1k
100
10
0.1
0.01
1
0.1
POWER-DOWN
100
10
POWER-UP
1
POWER-UP
1
10
100
0.1
0.01
1k
0.1
1
FREQUENCY – MHz
10
–15
VS = 6V
RL = 10
POWER-DOWN
VIN = 10dBm
–20
SIGNAL FEEDTHROUGH – dB
0
–20
POWER-UP
–60
–80
VIN = 10dBm
VS = 6V
RL = 10
G = –2
POWER-DOWN
–100
–120
0.1
1
10
FREQUENCY – MHz
1k
TPC 17. Output Impedance vs. Frequency
20
–40
100
FREQUENCY – MHz
TPC 14. Output Impedance vs. Frequency
CROSSTALK – dB
1M
TPC 16. Current Noise vs. Frequency (RTI)
10k
100
–25
–30
–35
G = –5, RG = 178, RF = 909
–40
–45
G = –2, RG = 453, RF = 909
–50
–55
0.1
1k
1
10
100
FREQUENCY – MHz
TPC 15. Crosstalk (Output to Output)
vs. Frequency
REV. 0
100k
FREQUENCY – Hz
TPC 18. Signal Feedthrough vs. Frequency
–7–
1k
AD8391
RG
–30
RF
RL = 21
FOR VS = 6V, V OUT = 8V p-p
FOR VS = 1.5V, V OUT = 2V p-p
G = –5
–40
DIFFERENTIAL DISTORTION – dBc
VIN+
VOUT–
VMID
RL
CMID
VOUT+
RG
RF
–50
–60
HD2 @VS = 1.5V
–70
HD2 @ VS = 6V
–80
–90
HD3 @VS = 1.5V
–100
VIN–
HD3 @VS = 6V
–110
0.01
0.1
10
1
FREQUENCY – MHz
TPC 19. Differential Output Test Setup
TPC 22. Differential Distortion vs. Frequency
–30
–30
VS = 6V
G = –5, (RG = 178)
–50
–60
VS = 1.5V
–40
RL = 21
DIFFERENTIAL DISTORTION – dBc
DIFFERENTIAL DISTORTION – dBc
–40
HD3 (FO = 500kHz)
HD2 (FO = 500kHz)
–70
–80
–90
HD2 (FO = 100kHz)
G = –5, (RG = 178)
–50
–60
HD2 (FO = 500kHz)
–70
HD3 (FO = 500kHz)
–80
HD2 (FO = 100kHz)
–90
–100
HD3 (FO = 100kHz)
–100
RL = 21
HD3 (FO = 100kHz)
–110
–110
2
6
10
14
18
0
22
1
TPC 20. Differential Distortion vs. Output Voltage
4
5
6
–50
VS = 6V
RLINE = 100
–35
–55
–45
–60
13.5dBm 14dBm
13dBm
–55
–65
VS = 6V
RLINE = 100
13.5dBm
14dBm
13dBm
–65
–70
–75
–75
12.5dBm
–85
1.7
3
TPC 23. Differential Distortion vs. Output Voltage
SFDR – dBc
MTPR – dBc
–25
2
OUTPUT VOLTAGE – V p-p
OUTPUT VOLTAGE – V p-p
1.8
12dBm
1.9
12.5dBm
2.0
2.1
2.2
–80
1.7
2.3
1.8
12dBm
1.9
2.0
2.1
2.2
2.3
TRANSFORMER TURNS RATIO
TRANSFORMER TURNS RATIO
TPC 21. MTPR vs. Transformer Turns Ratio
TPC 24. SFDR vs. Transformer Turns Ratio
–8–
REV. 0
AD8391
–30
–30
SINGLE-ENDED DISTORTION – dBc
–40
G = –5, (RG = 178)
SINGLE-ENDED DISTORTION – dBc
VS = 6V
HD3 (FO = 500kHz)
–50
–60
HD2 (FO = 500kHz)
–70
–80
–90
HD2 (FO = 100kHz)
–100
VS = 1.5V
–40
G = –5, (RG = 178)
HD2 (FO = 500kHz)
–50
HD3 (FO = 500kHz)
–60
–70
–80
HD2 (FO = 100kHz)
–90
–100
HD3 (FO = 100kHz)
–110
25
150
275
400
HD3 (FO = 100kHz)
525
–110
25
650
75
125
175
TPC 25. Single-Ended Distortion vs. Peak
Output Current
TPC 27. Single-Ended Distortion vs. Peak
Output Current
VS = 1.5V
VIN = 500mV/DIV
VOUT = 500mV/DIV
G = –5
RL = 10
VOUT
VOUT
0V
VIN
VIN
0V
0V
TIME – ns (100ns/DIV)
TIME – ns (100ns/DIV)
TPC 26. Overload Recovery
REV. 0
275
PEAK OUTPUT CURRENT – mA
VS = 6V
VIN = 1V/DIV
VOUT = 2V/DIV
G = –5
RL = 10
0V
225
PEAK OUTPUT CURRENT – mA
TPC 28. Overload Recovery
–9–
AD8391
GENERAL INFORMATION
Theory of Operation
The AD8391 is a dual current feedback amplifier with high
output current capability. It is fabricated on Analog Devices’
proprietary eXtra Fast Complementary Bipolar Process (XFCB) that
enables the construction of PNP and NPN transistors with fT’s
greater than 3 GHz. The process uses dielectrically isolated
transistors to eliminate the parasitic and latch-up problems caused
by junction isolation. These features enable the construction of
high-frequency, low-distortion amplifiers.
VO
VP
BIAS
VN
The AD8391 has a unique pin out. The two noninverting inputs
of the amplifier are connected to the VMID pin, which is internally
biased by two 5 kΩ resistors forming a voltage divider between
+VS and –VS. VMID is accessible through Pin 7. There is also a
10 pF internal capacitor from VMID to –VS. The two inverting pins
are available at Pin 1 and Pin 8, allowing the gain of the amplifiers to
be set with external resistors. See the front page for a connection
diagram of the AD8391.
Figure 3. Simplified Schematic
A simplified schematic of an amplifier is shown in Figure 3. Emitter
followers buffer the positive input, VP, to provide low-input current
and current noise. The low-impedance current feedback summing
junction is at the negative input, VN. The output stage is another
high-gain amplifier used as an integrator to provide frequency compensation. The complementary common-emitter output provides the
extended output swing.
G=1
+
VO
VIN
RIN
IIN
IT = IIN
CT
RT
+
–
VOUT
–
A current feedback amplifier’s bandwidth and distortion
performance are relatively insensitive to its closed-loop signal gain,
which is a distinct advantage over a voltage-feedback architecture.
Figure 4 shows a simplified model of a current feedback amplifier.
The feedback signal is an error current that flows into the inverting
node. RIN is inversely proportional to the transconductance of
the amplifier’s input stage, gmi. Circuit analysis of the pictured
follower with gain circuit yields:
RF
RG
Figure 4. Model of Current Feedback Amplifier
Feedback Resistor Selection
VOUT
G × Tz( s)
=
VIN
Tz( s) + RF + G × RIN
RF
RG
In current feedback amplifiers, selection of the feedback and
gain resistors will impact distortion, bandwidth, noise, and gain
flatness. Care should be exercised in the selection of these resistors
so that the optimum performance is achieved. Table I shows the
recommended resistor values for use in a variety of gain settings for
the test circuits in TPC 1 and TPC 19. These values are only
intended to be a starting point when designing for any application.
Tz( s) =
RF
1 + sCT ( RT )
Table I. Resistor Selection Guide
RIN =
1
≅ 125 Ω
gmi
where:
G =1+
Recognizing that G × RIN << RF , and that the –3 dB point is set
when Tz(s) = RF, one can see that the amplifier’s bandwidth
depends primarily on the feedback resistor. There is a value of
RF below which the amplifier will be unstable, as the amplifier
will have additional poles that will contribute excess phase shift.
The optimum value for RF depends on the gain and the amount
of peaking tolerable in the application. For more information
about current feedback amplifiers, see ADI’s High-Speed Design
Techniques at www.analog.com/technology/amplifiersLinear/
designTools/evaluationBoards/pdf/1.pdf.
–10–
Gain
RF ()
RG ()
–1
–2
–3
–4
–5
909
909
909
909
909
909
453
303
227
178
REV. 0
AD8391
Power-Down Feature
Power Dissipation
A three-state power-down function is available via the PWDN pin.
It allows the user to select among three operating conditions: full on,
standby, or shutdown. The –VS pin is the logic reference for the
PWDN function. The full shutdown state is maintained when the
PWDN is at 0.8 V or less above –VS. In shutdown the AD8391 will
draw only 4 mA. If the PWDN pin floats, the AD8391 operates in
a standby mode with low impedance outputs and draws approximately 10 mA.
It is important to consider the total power dissipation of the
AD8391 to size the heat sink area of an application properly.
Figure 5 is a simple representation of a differential driver. With
some simplifying assumptions the total power dissipated in this
circuit can be estimated. If the output current is large compared to
the quiescent current, computing the dissipation in the output
devices and adding it to the quiescent power dissipation will give
a close approximation of the total power dissipation in the package. A factor α corrects for the slight error due to the Class A/B
operation of the output stage. The value of α depends on what
portion of the quiescent current is in the output stage and varies
from 0 to 1. For the AD8391, α ≅ 0.72.
Power Supply and Decoupling
The AD8391 can be powered with a good quality (i.e., low-noise)
supply anywhere in the range from 3 V to 12 V. The AD8391
can also operate on dual supplies, from ± 1.5 V to ± 6 V. In order
to optimize the ADSL upstream drive capability of +13 dBm and
maintain the best Spurious Free Dynamic Range (SFDR), the
AD8391 circuit should be powered with a well-regulated supply.
+VS
Careful attention must be paid to decoupling the power supply.
High-quality capacitors with low equivalent series resistance
(ESR) such as multilayer ceramic capacitors (MLCCs) should
be used to minimize supply voltage ripple and power dissipation.
In addition, 0.1 µF MLCC decoupling capacitors should be located
no more than 1⁄8 inch away from each of the power supply pins.
A large, usually tantalum, 10 µF capacitor is required to provide
good decoupling for lower frequency signals and to supply current
for fast, large signal changes at the AD8391 outputs.
Bypassing capacitors should be laid out in such a manner to keep
return currents away from the inputs of the amplifiers. This will
minimize any voltage drops that can develop due to ground currents flowing through the ground plane. A large ground plane
will also provide a low impedance path for the return currents.
The VMID pin should also be decoupled to ground by using a 0.1 µF
ceramic capacitor. This will help prevent any high frequency
components from finding their way to the noninverting inputs of
the amplifiers.
+VO
When VMID is left floating, a change in the power supply voltage
(∆V) will result in a change of one-half ∆V at the VMID pin. If
the amplifiers’ inverting inputs are ac-coupled, one-half ∆V will
appear at the output, resulting in a PSRR of –6 dB. If the inputs
are dc-coupled, ∆V × (1 + Rf /Rg) will appear at the outputs.
–VO
RL
–VS
–VS
Figure 5. Simplified Differential Driver
Remembering that each output device only dissipates power for
half the time gives a simple integral that computes the power for
each device:
1
2

∫ (V
S
– VO ) ×
2 VO 

RL 
The total supply power can then be computed as:
Design Considerations
There are some unique considerations that must be taken into
account when designing with the AD8391. The VMID pin is internally
biased by two 5 kΩ resistors forming a voltage divider between
VCC and ground. These resistors will contribute approximately
6.3 nV/√Hz of input-referred (RTI) noise. This noise source is
common mode and will not contribute to the output noise when
the AD8391 is used differentially. In a single-supply system,
this is unavoidable. In a dual-supply system, VMID can be connected
directly to ground, eliminating this source of noise.
+VS
(
PTOT = 4 VS ∫|VO| − ∫ VO
2
) × R1
+ 2 α IQ VS
L
In this differential driver, VO is the voltage at the output of one
amplifier, so 2 VO is the voltage across RL. RL is the total impedance seen by the differential driver, including any back termination.
Now, with two observations the integrals are easily evaluated.
First, the integral of VO2 is simply the square of the rms value of
VO. Second, the integral of |VO| is equal to the average rectified
value of VO, sometimes called the mean average deviation, or
MAD. It can be shown that for a DMT signal, the MAD value
is equal to 0.8 times the rms value:
PTOT = 4 (0.8 VO rms VS – VO rms2 ) ×
1
+ 2 α IQ VS
RL
For the AD8391 operating on a single 12 V supply and delivering
a total of 16 dBm (13 dBm to the line and 3 dBm to account for
the matching network) into 50 Ω (100 Ω reflected back through
a 1:2 transformer plus back termination), the dissipated power
is 395 mW.
REV. 0
–11–
AD8391
Using these calculations and a θJA of 100°C/W for the SOIC,
Table II shows junction temperature versus power delivered to
the line for several supply voltages while operating at an ambient
temperature of 85°C. Operation at a junction temperature over
the absolute maximum rating of 150°C should be avoided.
VSUPPLY
12
12.5
13
14
15
125
127
129
126
129
131
Transformer Selection
Thermal stitching, which connects the outer layers to the internal
ground planes(s), can help to use the thermal mass of the PCB to
draw heat away from the line driver and other active components.
Layout Considerations
As is the case with all high-speed applications, careful attention
to printed circuit board layout details will prevent associated
board parasitics from becoming problematic. Proper RF design
techniques are mandatory. The PCB should have a ground plane
covering all unused portions of the component side of the board
to provide a low-impedance return path. Removing the ground
plane on all layers from the areas near the input and output pins
will reduce stray capacitance, particularly in the area of the
inverting inputs. The signal routing should be short and direct in
order to minimize parasitic inductance and capacitance associated
with these traces. Termination resistors and loads should be located
as close as possible to their respective inputs and outputs.
Input and output traces should be kept as far apart as possible
to minimize coupling (crosstalk) through the board. Wherever
there are complementary signals, a symmetrical layout should be
provided to the extent possible to maximize balanced performance. When running differential signals over a long distance, the
traces on the PCB should be close. This will reduce the radiated
energy and make the circuit less susceptible to RF interference.
Adherence to stripline design techniques for long signal traces
(greater than about one inch) is recommended.
453
+
909
12.5
1:2
1F
0.1F
8
7
6
5
+VS
VIN
VMID
RL
AD8391
–VS
1
–
453
2
3
909
4
+3V
+
–
The AD8391 is available installed on an evaluation board.
Figure 10 shows the schematics for the evaluation board. ACcoupling capacitors of 0.1 µF, C6 and C11, in combination with
10 kΩ, resistors R25 and R26, will form a first order high-pass
pole at 160 Hz.
The bill of materials included as Table III represents the components that are installed in the evaluation board when it is
shipped to a customer. There are footprints for additional components,
such as an AD8138, that will convert a single-ended signal into a
differential signal. There is also a place for an AD9632, which can
be used to convert a differential signal into a single-ended signal.
Table II. Junction Temperature vs. Line Power
and Operating Voltage for SOIC at 858C Ambient
PLINE, dBm
Evaluation Board
12.5
Customer premise ADSL requires the transmission of a 13 dBm
(20 mW) DMT signal. The DMT signal has a crest factor of 5.3,
requiring the line driver to provide peak line power of 560 mW.
560 mW peak line power translates into a 7.5 V peak voltage on a
100 Ω telephone line. Assuming that the maximum low distortion
output swing available from the AD8391 line driver on a 12 V
supply is 11 V, and taking into account the power lost due to the
termination resistance, a step-up transformer with turns ratio of
1:2 is adequate for most applications. If the modem designer desires
to transmit more than 13 dBm down the twisted pair, a higher
turns ratio can be used for the transformer. This trade-off comes
at the expense of higher power dissipation by the line driver as
well as increased attenuation of the downstream signal that is
received by the transceiver.
In the simplified differential drive circuit shown in Figure 6 the
AD8391 is coupled to the phone line through a step-up transformer
with a 1:2 turns ratio. R45 and R46 are back termination or line
matching resistors, each 12.5 Ω [1/2 (100 Ω/22 )] where 100 Ω is
the approximate phone line impedance. A transformer reflects
impedance from the line side to the IC side as a value inversely
proportional to the square of the turns ratio. The total differential
load for the AD8391, including the termination resistors, is 50 Ω.
Even under these conditions the AD8391 provides low distortion
signals to within 0.5 V of the power supply rails.
One must take care to minimize any capacitance present at the
outputs of a line driver. The sources of such capacitance can
include but are not limited to EMI suppression capacitors,
overvoltage protection devices and the transformers used in the
hybrid. Transformers have two kinds of parasitic capacitances:
distributed or bulk capacitance, and interwinding capacitance.
Distributed capacitance is a result of the capacitance created
between each adjacent winding on a transformer. Interwinding
capacitance is the capacitance that exists between the windings
on the primary and secondary sides of the transformer. The
existence of these capacitances is unavoidable and limiting both
distributed and interwinding capacitance to less than 20 pF each
should be sufficient for most applications.
It is also important that the transformer operates in its linear
region throughout the entire dynamic range of the driver.
Distortion introduced by the transformer can severely degrade
DSL performance, especially when operating at long loop lengths.
1F
0.1F
+
10F
VCC
Figure 6. Single-Supply Voltage Differential Drive Circuit
–12–
REV. 0
AD8391
Receive Channel Considerations
A transformer used at the output of the differential line driver to
step up the differential output voltage to the line has the inverse
effect on signals received from the line. A voltage reduction or
attenuation equal to the inverse of the turns ratio is realized in the
receive channel of a typical bridge hybrid. The turns ratio of the
transformer may also be dictated by the ability of the receive
circuitry to resolve low-level signals in the noisy twisted pair telephone plant. While higher turns ratio transformers boost transmit
signals to the appropriate level, they also effectively reduce the
received signal-to-noise ratio due to the reduction in the
received signal strength. Using a transformer with as low a turns
ratio as possible will limit degradation of the received signal.
The AD8022, a dual amplifier with typical RTI voltage noise of
only 2.5 nV/√Hz and a low supply current of 4 mA/amplifier is
recommended for the receive channel. If power-down is required
for the receive amplifier, two AD8021 low-noise amplifiers can
be used instead.
Conventional methods of expressing the output signal integrity of
line drivers such as single-tone harmonic distortion or THD, twotone InterModulation Distortion (IMD) and third order intercept
(IP3) become significantly less meaningful when amplifiers are
required to process DMT and other heavily modulated waveforms.
A typical ADSL upstream DMT signal can contain as many as
27 carriers (subbands or tones) of QAM signals. Multitone Power
Ratio (MTPR) is the relative difference between the measured
power in a typical subband (at one tone or carrier) versus the
power at another subband specifically selected to contain no
QAM data. In other words, a selected subband (or tone) remains
open or void of intentional power (without a QAM signal) yielding
an empty frequency bin. MTPR, sometimes referred to as the
“empty bin test,” is typically expressed in dBc, similar to expressing the relative difference between single-tone fundamentals and
second or third harmonic distortion components. Measurements
of MTPR are typically made on the line side or secondary side
of the transformer.
DMT Modulation, Multitone Power Ratio (MTPR) and
Out-of-Band SFDR
4
ADSL systems rely on Discrete Multitone (DMT) modulation
to carry digital data over phone lines. DMT modulation appears
in the frequency domain as power contained in several individual
frequency subbands, sometimes referred to as tones or bins,
each of which are uniformly separated in frequency. A uniquely
encoded, Quadrature Amplitude Modulation (QAM) like signal
occurs at the center frequency of each subband or tone. See
Figure 7 for an example of a DMT waveform in the frequency
domain, and Figure 8 for a time domain waveform. Difficulties
will exist when decoding these subbands if a QAM signal from
one subband is corrupted by the QAM signal(s) from other
subbands regardless of whether the corruption comes from an
adjacent subband or harmonics of other subbands.
3
VOLTS
2
–2
–3
–0.25
–0.2
–1.5
–1.0
–0.05
0
TIME – ms
0.05
1.0
1.5
0.2
Figure 8. DMT Signal in the Time Domain
0
POWER – dBm
0
–1
20
–20
–40
–60
–80
0
50
100
FREQUENCY – kHz
150
Figure 7. DMT Waveform in the Frequency Domain
REV. 0
1
TPC 21 and TPC 24 depict MTPR and SFDR versus transformer
turns respectively for a variety of line power ranging from 12 dBm to
14 dBm. As the turns ratio increases, the driver hybrid can deliver more
undistorted power to the load due to the high output current capability of the AD8391. Significant degradation of MTPR will occur
if the output transistors of the driver saturate, causing clipping at the
DMT voltage peaks. Driving DMT signals to such extremes not only
compromises “in-band” MTPR, but will also produce spurs that exist
outside of the frequency spectrum containing the transmitted signal.
“Out-of-band” spurious-free dynamic range (SFDR) can be defined
as the relative difference in amplitude between these spurs and a tone
in one of the upstream bins. Compromising out-of-band SFDR is
the equivalent to increasing near-end crosstalk (NEXT). Regardless
of terminology, maintaining high out-of-band SFDR while reducing
NEXT will improve the overall performance of the modems connected
at either end of the twisted pair.
–13–
AD8391
Generating DMT Signals
Video Driver
At this time, DMT-modulated waveforms are not typically menuselectable items contained within arbitrary waveform generators.
Even using AWG software to generate DMT signals, AWGs that
are available today may not deliver DMT signals sufficient in
performance with regard to MTPR due to limitations in the
D/A converters and output drivers used by AWG manufacturers.
MTPR evaluation requires a DMT signal generator capable of
delivering MTPR performance better than that of the driver under
evaluation. Generating DMT signals can be accomplished using a
Tektronics AWG 2021 equipped with option 4, (12-/24-bit, TTL
Digital Data Out), digitally coupled to Analog Devices’ AD9754,
a 14-bit TxDAC, buffered by an AD8002 amplifier configured
as a differential driver. Note that the DMT waveforms, available
on the Analog Devices website (www.analog.com) are similar.
WFM files are needed to produce the necessary digital data
required to drive the TxDAC from the optional TTL Digital
Data output of the TEK AWG2021.
The AD8391 can be used as a noninverting amplifier by applying a
signal at the VMID pin and grounding the gain resistors. See
Figure 9 for an example circuit. The signal applied to the VMID
pin would be present at both outputs, making this circuit ideal
for any application where one signal needs to be sent to two
different locations, such as a video distribution system. As previously stated, the AD8391 can operate on split supplies in this
case, eliminating the need for ac-coupling.
The termination resistor should be 76.8 Ω to maintain a 75 Ω
input impedance.
VEE
0.1F
909
909
10F
+
0.1F
8
7
VIN
75
6
75
5
–
+VS
+
VMID
76.8
AD8391
–VS
+
–
1
+3V
2
3
4
75
909
909
0.1F
10F
75
+
VCC
Figure 9. Driving Two Video Loads from the Same Source
–14–
REV. 0
REV. 0
Figure 10. Evaluation Board Schematic
–15–
–V
GND
+V
AGND
TP3
TP2
TP1
DNI
DNI
1F
C9
AGND
C10
AGND
0
R19
C28
VNEG
VPOS
R18
49.9
DNI
R46
DNI
R45
AGND
IN_NEG
IN_POS
TB
TA
DNI
C26
0
R20
DNI
C17
R14
C16
R13
AGND
DNI
C27
26
4
1F
C24
1F
–VOUT
DNI
C25
+VOUT
SHORT
C6
TP4
1F
C8
1F
C7
DNI
R25
DNI
0
R1
0
49.9
8
+IN
7
NC
6
V–
5
–OUT
R22
1F
C1
R21
DNI
7
9
8
2
3
SO8
DNI
C23
0
R23
1
–IN
2
V
3 MID
V+
4
+OUT
AGND
DNI
DNI
10
T1
1
C11
1F
1F
453
R27
TP5
L2
L1
+V
PWRBLK
PB3
–V
GND
AGND
R28
BI
BI
BI
BI
BI
BI
R26 453
DNI
AGND
C12
SHORT
AGND
R24
TP9
DNI VNEG
C29
DNI
R47
DNI
TP8
+VOUT
909
R29
J1 [21:6]
J1 [21:6]
J1 [21:6]
J1 [21:6]
J1 [21:6]
J1 [21:6]
PWDN
AGND
C13
DNI
R30
DNI
VMID
DNI
R2
R31
DNI
C14
DNI
AGND
VOUT2
7
VMID
6
–VS
5
8
R32
909
C3
DNI
C5
–VOUT
TB
R39
DNI
R36
0
AGND
C15
DNI
VNEG
DNI
C22
DNI
8
8
7
+VS
6
OUT
5
5
AD9632
1
1
2
–IN
3
+IN
4
–VS
*DNI = DO NOT INSTALL
TP7
R35
0
SHORT
DNI
R33
DNI
R40
0
R17
DNI
TA
R38
IN2
AD8391
1
IN1
2
PWDN
3
+VS
4
VOUT1
SHORT
C2
TP6
VPOS
DNI
OUT
R42
DNI
R41
DNI
AD8391
AD8391
Figure 11. Layer 1—Primary Side
Figure 12. Silkscreen—Primary Side
–16–
REV. 0
AD8391
Figure 13. Layer 2—Ground Plane
Figure 14. Layer 3—Power Plane
REV. 0
–17–
AD8391
Figure 15. Layer 4—Secondary Side
Figure 16. Layer 4—Silkscreen
–18–
REV. 0
AD8391
Table III. Evaluation Board Bill of Materials
Qty.
Description
Vendor
Ref Des
4
4
14
0.1 µF 50 V 1206 Size Ceramic Chip Capacitor
0 Ω 5% 1/8 W 1206-Size Chip Resistor
DNI
ADS #4-5-18
ADS #3-18-88
2
4
10 µF 16 V ‘B’-Size Tantalum Chip Capacitor
SMA End Launch Jack (E F JOHNSON #142-0701-801)
ADS #4-7-24
ADS #12-1-31
1
1
2
1
1
2
2
1
2
6
12
DNI
AMP #555154-1 MOD. JACK (SHIELDED) 6 6
FERRITE CORE 1/8 inch BEAD FB43101
DNI
3 Green Terminal Block ONSHORE #EDZ250/3
0 Ω 5% 1/8 W 1206-Size Chip Resistor
DNI
DNI
49.9 Ω Metal Film Resistor
0 Ω Metal Film Resistor
DNI
2
2
2
1
2
1
2
2
2
1
1
1
4
4
DNI
453 Ω Metal Film Resistor
909 Ω Metal Film Resistor
DNI
Red Test Point
Black Test Point
Blue Test Point
Orange Test Point
White Test Point
AD9632 (DNI)
AD8391
AD8138 (DNI)
#4-40 ⫻ 1/4 inch STAINLESS Panhead Machine Screw
#4-40 ⫻ 3/4 inch-long Aluminum Round Stand-Off
C1, C7–C9
C2, C3, C6, C11
C5, C10, C12–C17
C22, C25–C29
C23–C24
IN_NEG, IN_POS
PWDN, VMID
OUT
J1
L1, L2
PB1
PB3
R1, R23
R2, R33
R17
R18, R21
R19, R20, R22, R24, R35, R38
R25, R26, R30, R31, R39, R40
R42, R43, R44, R45, R46, R47
R36, R41
R27, R28
R29, R32
T1
TP1, TP4
TP2
TP3, TP5
TP6, TP7
TP8, TP9
Z4
Z5
Z6
REV. 0
D-K #A 9024
ADS #48-1-1
ADS #12-19-14
ADS #3-18-88
ADS #3-15-3
ADS #3-2-177
–19–
ADS #3-53-1
ADS #3-53-2
ADS #12-18-43
ADS #12-18-44
ADS #12-18-62
ADS #12-18-60
ADS #12-18-42
ADI #AD9632AR
ADI #AD8391AR
ADI #AD8138AR
ADS #30-1-1
ADS #30-16-3
AD8391
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC
(R-8)
0.1574 (4.00)
0.1497 (3.80)
8
5
1
4
C02719–.8–10/01(0)
0.1968 (5.00)
0.1890 (4.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0196 (0.50)
45
0.0099 (0.25)
0.0500 (1.27)
BSC
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
0.0688 (1.75)
0.0532 (1.35)
8
0.0500 (1.27)
0.0098 (0.25) 0
0.0160 (0.41)
0.0075 (0.19)
0.0192 (0.49)
0.0138 (0.35)
PRINTED IN U.S.A.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS, INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
–20–
REV. 0