AN1269

AN1269
Using C30 Compiler to Interface Serial SRAM Devices
to dsPIC33F and PIC24F
Author:
Pinakin K Makwana
Microchip Technology Inc.
INTRODUCTION
Microchip’s serial SRAM product line represents a new
way to add additional RAM to an application. With the
small, 8-pin packages and the SPI interface these
devices give designers added system flexibility. The
23XXXX series of serial SRAM devices from Microchip
Technology support a half-duplex protocol that
functions on a master-slave paradigm that is ideally
suited to data stream applications.
This application note is part of a series that provide
source code to help the user implement the protocol
with minimal effort.
Figure 1 describes the hardware schematic for the
interface between Microchip’s 23XXXX series devices
and the dsPIC33F DSC or the PIC24F MCU. The
schematic shows the connections necessary between
either controller and the serial SRAM as tested, and the
software was written assuming these connections. The
HOLD pin is tied to VCC because this feature is not
used in the examples provided.
The bus is controlled by the microcontroller (master),
which accesses the 23XXXX using the SPI peripheral
built into the MCU. The SPI bus can operate at speeds
up to 20 MHz for enhanced throughput. Communications can be paused using the HOLD pin.
CIRCUIT FOR dsPIC33FJ256GP710, PIC24FJ128GA010 AND 23XXXX SERIES
DEVICE
100-Pin TQFP
VSS
VDD
IC7/U1CTS/CN20/RD14
IC8/U1RTS/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
dsPIC33FJ256GP710
PIC24FJ128GA010
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
VCC
CS
1
SO
2
NC
3
VSS
4
23XXXX
FIGURE 1:
8
VCC
7
HOLD
6
SCK
5
SI
Note: CS and HOLD pins should all have pull-up resistors (~10k-ohms). See recommended usage application note.
© 2009 Microchip Technology Inc.
DS01269A-page 1
AN1269
FIRMWARE DESCRIPTION
The purpose of this application note is to offer the
designer a set of examples for the read and write
functions for using the Microchip SPI Serial SRAM.
Examples are included for the following modes: Byte,
Page and sequential Read and Writes. The code uses
the on-chip SPI hardware peripheral to communicate
with the serial SRAM.
The code was tested using the 23K256 SRAM
mounted to one of the SPI PIM modules. The code is
compatible with the PIC24F, PIC24H and dsPIC33F
families of MCU.
Oscilloscope screen shots are shown in this application
note. The MCU was configured to use the crystal on the
Explorer 16 board, the internal PLL was enabled and
the SPI peripheral was configured to generate a serial
clock rate of 4 MHz.
The following functions are provided to access the
serial SRAM:
•
•
•
•
•
•
•
•
SRAMWriteStatusReg
SRAMReadStatusReg
SRAMWriteByte
SRAMReadByte
SRAMWritePage
SRAMReadPage
SRAMWriteSeq
SRAMReadSeq
DS01269A-page 2
© 2009 Microchip Technology Inc.
AN1269
INITIALIZATION
WRITE STATUS REGISTER
Only one function needs to be called to initialize the
SRAM. Using the on-chip SPI peripheral makes communication easier than bit-banging the I/O ports. The
InitSRAM() function initializes the SPI module and
configures the I/O ports. Some devices support Peripheral Pin Select feature (PPS) and the SPI peripheral is
one peripheral that is remappable. If the MCU that you
are using supports this feature, additional steps must
be taken to map the SCK, SDI and SDO pins
accordingly.
The default mode of operation for the serial SRAM is
Byte mode and the user must select the appropriate
mode before the read or write operation. The functions
that are provided configure the SRAM for the correct
mode of operation, for example, if a SRAMWritePage
command is called, then the appropriate operating
mode is selected. The STATUS register also has provision for enabling the HOLD feature, but this is not used
in these examples. Figure 2 shows an example of the
Write Status Register command. Chip Select is brought
low (active) and the opcode is sent out through the SPI
port. The Write Status command is given followed by
the data to be written, in this case Page mode is
selected.
© 2009 Microchip Technology Inc.
DS01269A-page 3
AN1269
FIGURE 2:
WRITE STATUS REGISTER
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
Data to STATUS Register
0
0
0
1
7
6
5
4
3
2
High-Impedance
SO
DS01269A-page 4
© 2009 Microchip Technology Inc.
AN1269
READ STATUS REGISTER
Figure 3 shows an example of the Read Status
Register command to check for the mode of operation
and also the current status of the HOLD function.
FIGURE 3:
READ STATUS REGISTER
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
0
1
0
1
Data from STATUS Register
High-Impedance
SO
© 2009 Microchip Technology Inc.
7
6
5
4
3
2
DS01269A-page 5
AN1269
BYTE WRITE
The byte write operation consists of the following
sequence: The Write command followed by the word
address and data byte. The serial SRAM uses a 16-bit
address, so two bytes must be transmitted for the entire
word address, with the Most Significant Byte (MSB)
first.
FIGURE 4:
Figure 4 shows an example of the Write command. For
this, the device is selected and the opcode, 0x02, is
sent. The High Address byte is given 0x00, followed by
the Low Address byte, 0x10. Finally, the data is clocked
in last, in this case, 0x28.
BYTE WRITE COMMAND, ADDRESS AND DATA
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
0
0
0
16-bit Address
0
1
0 15 14 13 12
Data Byte
2
1
0
7
6
5
4
3
2
1
0
High-Impedance
SO
DS01269A-page 6
© 2009 Microchip Technology Inc.
AN1269
BYTE READ
The byte read operation can be used to read data from
the serial SRAM. The MCU/DSC sends the command
byte followed by the word address. Figure 5 shows an
example of the Read command, followed by the MSB
and LSB address bytes, followed by the read byte.
FIGURE 5:
BYTE READ (COMMAND BYTE, WORD ADDRESS AND READ BYTE)
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
0
0
0
16-bit Address
0
1
1 15 14 13 12
2
1
0
Data Out
High-Impedance
SO
© 2009 Microchip Technology Inc.
7
6
5
4
3
2
1
0
DS01269A-page 7
AN1269
PAGE WRITE
Page write operations provide a technique for increasing throughput when writing large blocks of data. The
serial SRAM features a 32-byte page. By using the
page write feature, up to 1 full page of data can be written consecutively. It is important to point out that page
write operations are limited to writing bytes within a single physical page regardless of the number of bytes
being written. Physical page boundaries start at
FIGURE 6:
addresses that are integer multiples of the page size
and end at addresses that are [integer multiples of the
page size] - 1. Attempting to write across a page
boundary results in the data being wrapped back to the
beginning of the current page. Figure 6 shows the
Write command, address and data byte during a page
write operation.
PAGE WRITE (FIRST DATA BYTE)
CS
0
1
2
3
4
5
6
Instruction
SI
0
0
0
0
0
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
Page X, Word Y
16-bit Address
0 1
0 15 14 13 12
2
1
0
7
6
5
4
3
2
1
0
Page X, Word Y
DS01269A-page 8
© 2009 Microchip Technology Inc.
AN1269
PAGE READ
Page read operations read a complete string, starting
with the specified address. The page read operation
also works similar to page write operation and thus a
FIGURE 7:
maximum of 32 bytes can be read consecutively.
Figure 7 shows an example of the entire sequence of
commands necessary to perform the page read
operation. For clarity, only the first byte is shown.
PAGE READ (FIRST READ DATA BYTE)
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
0
0
0
16-bit Address
0 1
1 15 14 13 12
2
1
0
Page X, Word Y
SO
© 2009 Microchip Technology Inc.
Page X, Word Y
High Impedance
7
6
5
4
3
2
1
0
DS01269A-page 9
AN1269
SEQUENTIAL WRITE
This operation is very useful while writing a long string,
which is more than the page size (32 bytes). This operation needs a Write command (0x02) to be sent followed by upper address byte and lower address byte.
The SRAM keeps writing data as long as it receives
clock and valid data. When the last location of memory
FIGURE 8:
is reached, the next location that is written is the first
address (0x0000), that is, the internal address counter
rolls over. Figure 8 depicts the entire sequence of
commands necessary to perform the sequential write
operation. For clarity, only the first byte is shown.
SEQUENTIAL WRITE (FIRST DATA BYTE)
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
DS01269A-page 10
0
0
0
16-bit Address
0 1
0 15 14 13 12
Data Byte 1
2
1
0
7
6
5
4
3
2
1
0
© 2009 Microchip Technology Inc.
AN1269
SEQUENTIAL READ
Sequential read operation allows the entire array to be
read from the SRAM. The internal address counter
automatically increments and page boundaries are
FIGURE 9:
ignored. When the internal address counter reaches
the end of the array, the address counter will roll over
to 0x0000. Figure 9 shows an example of the sequence
of commands necessary to perform a sequential write
operation.
SEQUENTIAL READ (FIRST READ DATA BYTE)
CS
0
1
2
0
0
0
3
4
5
6
Instruction
SI
0
0
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
16-bit Address
0 1
1 15 14 13 12
2
1
0
Page X, Word Y
SO
© 2009 Microchip Technology Inc.
7
6
5
4
3
2
1
0
DS01269A-page 11
AN1269
CONCLUSION
This application note offers designers a set of firmware
routines to access SPI serial SRAM. The code demonstrates byte, page and sequential operations. All the
routines were written in C using the C30 package from
Microchip. The code was tested on Microchip’s
Explorer 16 Development Board with the connections
shown in Figure 1 with the PIC24FJ128GA010 PIM
module.
DS01269A-page 12
© 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Hampshire, Linear Active Thermistor, MXDEV,
MXLAB, SEEVAL, SmartSensor and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Total Endurance, TSHARC, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
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SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2009 Microchip Technology Inc.
DS01269A-page 13
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DS01269A-page 14
© 2009 Microchip Technology Inc.
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