AN1797

AN1797
Interfacing 23X512/1024 SDI/SQI Serial SRAM Devices
to NXP LPC18XX/43XX Microcontrollers Using the SPIFI Peripheral
Author:
This application note is targeted at customers using
MCUs that offer Quad mode SPI capabilities, and who
want to take advantage of the higher throughput
capabilities offered by Microchip’s Serial SRAM, when
operated in the SQI mode.
Dragos Ciofu
Microchip Technology Inc.
INTRODUCTION
Microchip’s serial SRAM product line represents a
flexible way to add additional RAM to an application.
Available in PDIP, TSSOP and SOIC packages,
Microchip’s serial SRAM gives designers added
flexibility when it comes to compatibility and cost
effectiveness. With added Quad-SPI (SQI) capabilities
and high clock rates, the 23X512/1024 devices
eliminate the throughput penalty of a serial bus, while
keeping the PCB impact and BOM costs to a minimum.
The 23X512/1024 devices are also capable of
operating in SDI and SPI mode. With clock rates up to
20 MHz, the 23X512/1024 SRAM provides a
theoretical throughput of 80 Mbit/sec in SQI mode.
FIGURE 1:
The serial bus is controlled by the microcontroller
(master) which accesses the 23X512/1024 device
using the MCUs SPIFI peripheral, configured for
manual operation (as opposed to Flash operation).
Figure 1 describes the hardware schematic for the
interface between a Microchip 23X512/1024 device
and an NXP LPC4357 device in an LBGA256 package.
The 23X512/1024 device pinout does not vary with
package, as opposed to third party microcontrollers.
Users are advised to consult their chosen master
device’s data sheet and manufacturer notes to ensure
pin-to-pin compatibility between families of microcontrollers. The schematic shows the connections
between the SRAM and microcontroller, and the
software is provided assuming these connections. The
HOLD pin is tied to SPI_SIO3, being used as the fourth
lane in the SQI bus.
SCHEMATIC
SPI_CS
SPI_CLK
C10
B14
SPI_SIO3
A15
SPI_SIO2
C12
SPI_MOSI
C11
B13
SPI_MISO
LPC4357
FET256
Vcc
SO/SIO1
SIO2
VSS
 2014 Microchip Technology Inc.
VCC
CS
HOLD/SIO3
23X512/1024
SCK
SO/SIO0
DS00001797A-page 1
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FIRMWARE DESCRIPTION
The scope of this application note is to highlight the
capabilities of Microchip’s SRAM range. Bus protocol
implementations
vary
from
manufacturer
to
manufacturer, but Microchip’s SRAM devices boast
excellent compatibility, provided the protocol standards
are adhered to. The provided firmware targets an NXP
LPC4357 microcontroller, but the firmware is
compatible with all devices from NXP’s 18xx and 43xx
families. The code targets NXP’s proprietary SPIFI
peripheral (port) and controls it with a command API
available for the user of the 23X512/1024 device.
The firmware was tested using a 23A1024 SQI SRAM
device, attached to a LPC4357-EVB produced by
EMBEST. This particular EVB implements an LPC4357
part that has on-chip Flash. The on-chip Flash option is
necessary in order to have the SPIFI port available for
other slave devices (in this case the Microchip
23A1024 SRAM).
The ports employed for connecting the SRAM to the
LPC device are pictured in the schematic in Figure 1.
The SPIFI peripheral has a configurable clock
frequency, as set from the firmware, and the 23A1024
SRAM device can operate with a clock frequency of up
to 20 MHz without any explicit clock configuration
sequence.
The IDE used for developing the firmware is Keil
uVision V4.74.0.22.
In order to build the target, the LPCOpen v2.09 chip
support library is needed, available on the MCU
vendor’s web site (http://www.lpcware.com/system/
files/lpcopen_2_09_keil_iar_keil_mcb_4357_1.zip).
Both oscilloscope screen captures and logic analyzer
screen shots are shown in this application note.
DS00001797A-page 2
The following functions are provided to access the
Serial SRAM:
•
•
•
•
•
•
•
•
•
•
SRAMWriteSeq
SRAMReadSeq
SRAMWriteByte
SRAMReadByte
SRAMWritePage
SRAMReadPage
SRAMSetIOMode
SRAMResetIOMode
SRAMReadModeReg
SRAMWriteModeReg
The above functions are defined in the driver files
SRAM_Driver.c, with respective declarations in
SRAM_Driver.h. This file pair can be directly
imported into the user’s application code. The functions
are called from Main_Demo.c. The main demo file
cycles through all possible bus modes (SPI/SDI/SQI)
while performing IO operations in all different memory
modes (BYTE, PAGE, SEQUENTIAL).
INITIALIZATION
The 23X512/1024 devices do not require any specific
initialization. The internal state machine drives the
outputs and coordinates the read/write operations
based on the external clock issued by the master
device. However, in this case, the LPC microcontroller
needs initialization, which is done by calling the
included functions:
• spifiPeripheralConfig
• spifiPeripheralInit
The peripheral configuration function must be called
with the desired frequency (in Hz) as a parameter,
while the peripheral initialization function needs the
reference to a variable mapped in the peripheral
memory addressable range. This latter variable acts as
a handle for all operations using the SPIFI peripheral,
whose registers are addressable starting from the
0x40003000 or (LPC_SPIFI_BASE) address.
 2014 Microchip Technology Inc.
AN1797
BUS MODES
The 23X512/1024 part can be accessed via a simple
Serial Peripheral Interface (SPI) compatible serial bus.
The bus signals required are a clock input (SCK) and
separate data in (SI) and data out (SO) pins. Access is
controlled through a Chip Select (CS) input.
Additionally, SDI (Serial Dual Interface) and SQI (Serial
Quad Interface) are supported if the application needs
faster data rates. In SDI mode, the SI and SO lines are
half duplex and behave as SIO0 and SIO1 (from the
microcontroller’s point of view). In SQI mode, the SI,
SO, SIO2 and SIO3 behave as a half-duplex four lane
bus, and the HOLD/SIO3 pin loses its HOLD alternate
function.
INSTRUCTION SET
TABLE 1:
INSTRUCTION SET
Instruction Format
Hex
Code
Description
READ
0000 0011
0x03
Read data from memory array beginning at selected address
WRITE
0000 0010
0x02
Write data to memory array beginning at selected address
EDIO
0011 1011
0x3B
Enter Dual I/O access
Instruction Name
EQIO
0011 1000
0x38
Enter Quad I/O access
RSTIO
1111 1111
0xFF
Reset Dual and Quad I/O access
RDMR
0000 0101
0x05
Read Mode Register
WRMR
0000 0001
0x01
Write Mode Register
 2014 Microchip Technology Inc.
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ENTER DUAL I/O ACCESS
Figure 2 represents the transmission of an EDIO
(0x3B) instruction using the SPI protocol.
To set SDI as a bus mode the EDIO (0x3B) instruction
must be clocked in. The master device must be aware
if the bus mode has been changed before issuing any
bus mode change instructions. EDIO can be
transmitted if the bus is in SPI or SQI modes. If the bus
is already in SDI mode, the EDIO instruction will not
reset the bus mode and will have no effect.
FIGURE 2:
The corresponding function call in the provided
firmware is:
• SRAMSetIOMode(SDI, SPI)
ENTER DUAL I/O ACCESS (SPI MODE)
0
0
1
1
0
0
0
0
MSB
1
0
1
1
0
0
0
0
MSB
Enter SDI Mode (EDIO) from SPI Mode
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
1
1
1
0
1
1
High-Impedance
SO
DS00001797A-page 4
 2014 Microchip Technology Inc.
AN1797
Figure 3 represents the transmission of an EDIO
(0x3B) instruction using the SQI protocol
The corresponding function call in the provided
firmware is:
• SRAMSetIOMode(SDI, SQI)
FIGURE 3:
ENTER DUAL I/O ACCESS (SQI MODE)
1
1
1
1
0
0
0
1
MSB
3B
 2014 Microchip Technology Inc.
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ENTER QUAD I/O ACCESS
To set SQI as a bus mode the EQIO (0x38) instruction
must be clocked in. The master device must be aware
if the bus mode has been changed before transmitting
any bus mode change instructions. EQIO can be
transmitted if the bus is in SPI or SDI modes. If the bus
is already in SQI mode, the EQIO instruction will not
reset the bus mode and will have no effect.
Figure 4 represents the transmission of an EQIO (0x38)
instruction using the SPI protocol.
The corresponding function call in the provided
firmware is:
• SRAMSetIOMode(SQI, SPI)
FIGURE 4:
ENTER QUAD I/O ACCESS (SPI MODE)
0
0
1
1
0
0
0
0
MSB
1
0
0
0
0
0
0
0
MSB
Enter SQI Mode (EQIO) From SPI Mode
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
1
1
1
0
0
0
High-Impedance
SO
DS00001797A-page 6
 2014 Microchip Technology Inc.
AN1797
Figure 5 represents the transmission of an EQIO (0x38)
instruction using the SDI protocol
The corresponding function call in the provided
firmware is:
• SRAMSetIOMode(SQI, SDI)
FIGURE 5:
ENTER QUAD I/O ACCESS (SDI MODE)
0
1
0
0
0
1
1
0
MSB
38
 2014 Microchip Technology Inc.
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RESET DUAL AND QUAD I/O ACCESS
If the bus mode is not known, the master device can
transmit two RSTIO instructions using both the SDI and
SQI formats to ensure a proper reset to SPI mode. This
double transmit has no side effects over the SRAM.
This is highlighted in the provided firmware, and
corresponding function call is:
To reset the bus mode from SQI or SDI modes back to
SPI mode, the RSTIO (0xFF) instruction must be
clocked in. The master device must be aware of the
current bus mode before issuing the RSTIO instruction.
The corresponding function call in this case is one of
the following:
• SRAMResetIOMode (TBD)
Figure 6 represents the transmission of an RSTIO
(0xFF) instruction using the SDI protocol.
• SRAMResetIOMode (SDI)
Or
• SRAMResetIOMode (SQI)
FIGURE 6:
RESET DUAL AND QUAD I/O ACCESS (SDI MODE)
1
1
1
1
1
1
1
1
MSB
01
DS00001797A-page 8
 2014 Microchip Technology Inc.
AN1797
Figure 7 represents the transmission of an RSTIO
(0xFF) instruction using the SQI protocol, followed by
the same instruction on the SDI protocol, as mentioned
above.
FIGURE 7:
RESET DUAL AND QUAD I/O ACCESS (SQI MODE, SDI MODES)
1
1
1
1
1
1
1
1
MSB
FF
 2014 Microchip Technology Inc.
1
1
1
1
1
1
1
1
MSB
FF
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WRITE MODE REGISTER
Figure 8 represents the transmission of a WRMR (0x01)
instruction with the Page bits (0x80) as the parameter,
using the SPI protocol.
The default mode of operation for the 23X512/1024
devices is Sequential mode, and the user must select
the appropriate mode before any IO operation. The
Write Mode Register instruction (WRMR) allows the
users to write the bits 7 and 6 in the Mode register
•
•
•
•
The corresponding function call in the provided
firmware is:
• SRAMWriteModeReg(PAGE,SPI)
00 = Byte mode
10 = Page mode
01 = Sequential mode (default operation)
11 = Reserved
FIGURE 8:
WRITE MODE REGISTER (SPI MODE)
0
0
0
0
0
0
0
0
MSB
0
0
0
1
0
0
0
0
MSB
1
0
0
0
0
0
0
0
MSB
0
0
0
0
0
0
0
0
MSB
Write Mode Register Timing Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
Data to Mode Register
0
0
0
1
7
6
5
4
3
2
High-Impedance
SO
DS00001797A-page 10
 2014 Microchip Technology Inc.
AN1797
Figure 9 represents the transmission of a WRMR (0x01)
instruction with the PAGE bits (0x80) as the parameter,
using the SDI protocol. On each clock, two bits are
transmitted and the MSB is found on the SIO1 line.
Only eight clock cycles are required to shift 2 bytes of
data.
The corresponding function call in the provided
firmware is:
• SRAMWriteModeReg(PAGE,SDI)
FIGURE 9:
WRITE MODE REGISTER (SDI MODE)
0
0
0
1
0
0
0
0
MSB
01
 2014 Microchip Technology Inc.
0
0
0
0
1
0
0
0
MSB
80
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AN1797
Figure 10 represents the transmission of a WRMR (0x01)
instruction with the PAGE bits (0x80) as the parameter,
using the SQI protocol. On each clock, the MSB is
found on the SIO3 line and the LSB on the SIO0 line. A
4-bit nibble is transmitted on each clock pulse. Only
four clocks are required to shift two bytes of data.
FIGURE 10:
The corresponding function call in the provided
firmware is:
• SRAMWriteModeReg(PAGE,SQI)
WRITE MODE REGISTER (SQI MODE)
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
MSB
01
DS00001797A-page 12
MSB
80
 2014 Microchip Technology Inc.
AN1797
READ MODE REGISTER
The Read Mode Register instruction (RDMR) provides
access to the 23X512/1024 SRAM’s Mode register.
Figure 11 represents the transmission of a RDMR (0x05)
instruction using the SPI protocol. The PAGE bits
(0x80) are expected on the MISO line.
The corresponding function call in the provided
firmware is:
• SRAMReadModeReg(SPI)
FIGURE 11:
READ MODE REGISTER (SPI MODE)
0
0
0
0
0
0
0
0
MSB
0
1
0
1
0
0
0
0
MSB
0
0
0
0
1
0
0
0
MSB
0
0
0
0
0
0
0
0
MSB
Read Mode Register Timing Sequence (RDMR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
0
1
0
1
Data from Mode Register
High-Impedance
SO
 2014 Microchip Technology Inc.
7
6
5
4
3
2
DS00001797A-page 13
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Figure 12 represents the transmission of a RDMR (0x05)
instruction using the SDI protocol. In this case, the SEQ
bits (0x40) are expected on the SIO1 and SIO0 lines.
The MSB is found on the SIO1 line.
The corresponding function call in the provided
firmware is:
• SRAMReadModeReg(SDI)
FIGURE 12:
READ MODE REGISTER (SDI MODE)
0
0
1
1
0
0
0
0
MSB
05
DS00001797A-page 14
1
0
0
0
0
0
0
0
MSB
80
 2014 Microchip Technology Inc.
AN1797
Figure 13 represents the transmission of a RDMR (0x05)
instruction using the SQI protocol. In this case the
PAGE bits (0x80) are expected on the SIO3 through
SIO0 lines. The MSB is found on the SIO3 line. A 4-bit
nibble is transmitted on each clock pulse. Only four
clocks are required to shift two bytes of data, one in
each direction.
• SRAMReadModeReg(SQI)
FIGURE 13:
READ MODE REGISTER (SQI MODE)
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
MSB
05
 2014 Microchip Technology Inc.
MSB
80
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BYTE WRITE
In order to write a byte in either mode, the WRITE
instruction (0x02) must be transmitted by the master,
followed by the 24-bit address and the 8-bit data to be
written. This is depicted in Figure 14.
FIGURE 14:
BYTE WRITE (SPI MODE)
0 00 0 0 01 0 00 0 0 000 10 0 1 000 11 1 0 101 01 1 0 11 1 10 1 0
MSB
The corresponding function call in the provided
firmware is:
• SRAMWriteByte(0x0123AB, data, SPI)
(where *data=0x7A)
DS00001797A-page 16
 2014 Microchip Technology Inc.
AN1797
Figure 15 represents a WRITE instruction in SDI mode.
The corresponding function call is:
• SRAMWriteByte(0x0123AB, data, SDI)
FIGURE 15:
BYTE WRITE (SDI MODE)
0
0
0
0
0
0
0
1
MSB
02
 2014 Microchip Technology Inc.
0
0
0
1
0
0
0
0
MSB
01
0
0
0
1
0
1
0
1
MSB
23
0
0
0
1 1
1
0
1
1
1
1
1 0
1
1
1
MSB
AB
MSB
7B
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Figure 16 represents a WRITE instruction in SQI mode.
The corresponding function call is:
• SRAMWriteByte(0x0123AB, data, SQI)
(where *data=0x7A)
FIGURE 16:
BYTE WRITE (SQI MODE)
0
0
0
1
0
1
0
1
1
1
0
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
1
MSB
02
DS00001797A-page 18
MSB
01
MSB
23
MSB
AB
MSB
7B
 2014 Microchip Technology Inc.
AN1797
BYTE READ
In order to read a byte in either mode, the READ
instruction (0x03) must be transmitted by the master,
followed by the 24-bit address. In SDI and SQI modes,
one more additional dummy byte must be clocked
before any actual data is sent on the bus by the SRAM.
Figure 17 represents a READ instruction in SPI mode.
The corresponding function call is:
• SRAMReadByte(0x0123AB, data, SPI)
FIGURE 17:
BYTE WRITE (SPI MODE)
0 00 0 0 01 0 00 0 0 000 10 0 1 00 0 11 1 0 101 01 1
MSB
0 111 10 1 0
MSB
 2014 Microchip Technology Inc.
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Figure 18 represents a READ instruction in SDI mode.
Notice that clocks 16 through 19 are the dummy byte
clocks. The corresponding function call is:
• SRAMReadByte(0x0123AB, data, SDI)
FIGURE 18:
BYTE READ (SDI MODE)
0
0
0
1
0
0
0
1
MSB
03
DS00001797A-page 20
0
0
0
1
0
0
0
0
MSB
01
0
0
0
1
0
1
0
1
MSB
23
0
0
0
1 1
1
1
1 1
1
0
1
1
1
1
1 1
1
1
1
0
1
1
1
MSB
AB
MSB
FF
MSB
7B
 2014 Microchip Technology Inc.
AN1797
Figure 19 represents a READ instruction in SQI mode.
The corresponding function call is:
• SRAMReadByte(0x0123AB, data, SQI)
The waveform is similar to the WRITE waveform, the
differences lie in the command word and the extra
dummy byte that is “read”.
FIGURE 19:
BYTE READ (SQI MODE)
0
1
0
1
0
1
0
1
1
1
1
1
0
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
0
1
MSB
03
 2014 Microchip Technology Inc.
MSB
01
MSB
23
MSB
AB
MSB
BB
MSB
7B
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PAGE AND SEQUENTIAL MODES
Sequential operation allows the entire array to be
written to and read from. The internal address counter
is automatically incremented and page boundaries are
ignored. When the internal address counter reaches
the end of the array, the address counter will roll over
to 0x00000;
The 23X512/1024 parts have three modes of operation
that are selected by setting bits 7 and 6 in the Mode
register, as specified above in the Write Mode
Register section.
In Page mode, the read and write operations are limited
to within the addressed page (the address is
automatically incremented internally). If the data being
read or written reaches the page boundary, then the
internal address counter will increment to the start of
the page.
FIGURE 20:
Figure 20 represents a two-byte-wide sequential write.
The number of clocks required is two for the instruction,
six for the address and four for the two bytes of data.
The corresponding function call is:
• SRAMWriteSeq (0x123AB, data, 2, SQI)
SEQUENTIAL WRITE - 2 BYTES (SQI MODE)
00
00
00
1
1
0
0
11
00
11
11
11
11
00
00
11
00
0
0
1
1
11
11
11
11
11
11
00
00
00
00
0
0
0
0
00
00
00
11
00
11
11
00
00
0
0
00
00
00
11
11
00
11
00
11
MSB
02
03
DS00001797A-page 22
MSB
01
01
MSB
2323
MSB
AB
AB
MSB
7B
BB
MSB
7C
7B
 2014 Microchip Technology Inc.
AN1797
CONCLUSION
This application note offers designers a set of firmware
routines to access Microchip SPI/SDI/SQI serial
SRAMs from another target than the PIC® device
series of microcontrollers. This demonstrates
Microchip’s SRAM series’ excellent compatibility,
translated into lower development costs and faster time
to market.
 2014 Microchip Technology Inc.
DS00001797A-page 23
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APPENDIX A:
REVISION HISTORY
Revision A (09/2014)
Initial release of this document.
DS00001797A-page 24
 2014 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
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CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
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Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2014, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-63276-556-7
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2014 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS00001797A-page 25
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Austin, TX
Tel: 512-257-3370
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
DS00001797A-page 26
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Dusseldorf
Tel: 49-2129-3766400
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Pforzheim
Tel: 49-7231-424750
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Poland - Warsaw
Tel: 48-22-3325737
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
03/25/14
 2014 Microchip Technology Inc.
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