NCP383 D

NCP383
Adjustable Current-Limiting
Power-Distribution
Switches
The NCP383 is a single input dual outputs power−distribution
switch designed for applications where heavy capacitive loads and
short−circuits are likely to be encountered, incorporating two very low
RDS(on), N−channel MOSFETs in a single package. Each channel of
the device limits the output current to a desired level by switching into
a constant−current mode when the output load exceeds the
current−limit threshold or a short circuit is present. The current−limit
threshold is externally fixed by a pull down resistor placed between
Ilim and GND. The power−switches rise and fall times are controlled to
minimize current ringing during turn on/off.
An internal reverse−voltage detection comparator disables the
power−switch if the output voltage is higher than the input voltage to
protect devices on the input side of the switches.
The /FLAGx logic output asserts low during over−current,
reverse−voltage or over temperature conditions. The switch is
controlled by a logic enable input active low.
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MARKING
DIAGRAM
383
ALYWG
G
UDFN10
CASE 517CC
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(*Note: Microdot may be in either location)
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2.7 V – 5.5 V Operating Range
Current limit: Adjustable up to 2.8 A
± 7.5% Current Limit Accuracy at 2.8 A
Very fast Over−Current Detection Response: 2 ms (typ)
1 mA Maximum Standby Supply Current
Under Voltage Lock−out (UVLO)
Soft−Start Prevents Inrush Current
Thermal Protection
Soft Turn−off
Reverse Voltage Protection
Enable Active Low
mDFN 3x3 mm
Compliance to IEC61000−4−2 (Level 4)
8.0 kV (Contact) − 15 kV (Air)
UL Listed – File E343275
CB − IEC60950−ED2 Certified
CB – IEC60950−ED2−AM1 Certified
This is a Pb−Free Device
PIN CONNECTIONS
GND
1
10 /FLAG1
IN 2
9 OUT1
IN 3
8 OUT2
EN1 4
7 ILIM
EN2 5
6 /FLAG2
(Top View)
Exposed pad must be soldered to PCB Ground plane.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Typical Applications
• Laptops
• USB Ports/Hubs
• TVs
© Semiconductor Components Industries, LLC, 2012
October, 2012 − Rev. 2
1
Publication Order Number:
NCP383/D
NCP383
USB
Data
USB INPUT
5V
IN
1 mF
Rfault
100 kW
D+
D−
VBUS
GND
OUT1
IN
120 mF
USB
Port
NCP383
USB
Data
/FLAG1
FLAG1
/EN1
EN1
ILIM
/FLAG2
FLAG2
EN2
D+
D−
VBUS
GND
OUT2
120 mF
/EN2
USB
Port
GND
Figure 1. Typical Application Circuit: NCP383xMUAJxx
Adjustable Current limit on Channel 1 and Channel 2
PIN FUNCTION DESCRIPTION
Pin Name
Number
Type
Description
GND
1
P
Ground connection.
IN
2, 3
P
Power−switch input voltage; connect a 1 mF or greater ceramic capacitor from IN to GND as
close as possible to the IC. Both IN pins must be hardwired together on the PCB.
/EN1
4
I
Enable 1 input, logic low turns on power switch 1 – If channel 1 is not used, do not leave this
pin unconnected. Pull it to VIN
/EN2
5
I
Enable 2 input, logic low turns on power switch 2. If channel 2 is not used, do not leave this
pin unconnected. Pull it to VIN
/FLAG2
6
O
Active−low open−drain output 2, asserted during overcurrent, overtemperature, or reverse−
voltage conditions. Connect a 10kW or greater resistor pull−up, otherwise leave unconnected.
ILIM
7
O
External resistor used to set current−limit threshold; recommended 20kW < RILIM < 120 kW.
OUT2
8
O
Power−switch output2; connect a 1 mF ceramic capacitor from OUT2 to GND as close as
possible to the IC is recommended. A 120 mF or greater ceramic capacitor from OUT2 to
GND must be connected if the USB requirement is not met.
OUT1
9
O
Power−switch output1; connect a 1 mF ceramic capacitor from OUT1 to GND as close as
possible to the IC is recommended. A 120 mF or greater ceramic capacitor from OUT1 to
GND must be connected if the USB requirement is not met.
O
Active−low open−drain output 1, asserted during overcurrent, overtemperature, or reverse−
voltage conditions. Connect a 10 kW or greater resistor pull−up, otherwise leave unconnected.
/FLAG1
10
PAD
11
Therm
Exposed Thermal Pad: Must be soldered to PCB Ground plane
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2
NCP383
/EN1
EN block
Control logic
and timer
To ILIM
Flag
Current
Limiter
/FLAG1
Charge Pump
Gate Driver
GND
OUT1
IN
Osc
Vref
UVLO
TSD
Blocking control
Blocking control
OUT2
ILIM
Current
Limiter
Charge Pump
Gate Driver
Flag
/EN2
EN block
Control logic
and timer
Figure 2. Block Diagram
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/FLAT2
NCP383
MAXIMUM RATINGS
Symbol
Value
Unit
From IN to OUT1, From IN to OUT2 Supply Voltage
(Note 1)
Rating
VIN , VOUT1,VOUT2
−7.0 to +7.0
V
IN, OUT1,OUT2, /EN1, /EN2, /FLAG1, /FLAG2, ILIM
Pins: In/Output (Note 1)
VIN , VOUT1, VOUT2,VEN1 , VEN2 ,
VFLAG1,VFLAG2, VILIM,
−0.3 to +7.0
V
ISINK
2
mA
ESD IEC
15 Air, 8 contact
kV
Human Body Model (HBM) ESD Rating are (Note 2)
ESD HBM
2000
V
Machine Model (MM) ESD Rating are (Note 2)
ESD MM
200
V
LU
100
mA
TJ
−40 to + TSD
°C
Storage Temperature Range
TSTG
−40 to + 150
°C
Moisture Sensitivity (Note 5)
MSL
Level 1
/FLAG1, /FLAG2 Sink Current
ESD Withstand Voltage (IEC 61000−4−2) (output only,
when bypassed with 1.0 mF capacitor minimum)
Latch−up protection (All Pins) (Note 3)
Maximum Junction Temperature (Note 4)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. According to JEDEC standard JESD22−A108
2. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) ±200 V per JEDEC standard: JESD22−A115 for all pins.
3. Latch up Current Maximum Rating: +100 mA per JEDEC standard: JESD78 class II.
4. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020
OPERATING CONDITIONS
Symbol
VIN
VENX
TA
ISINK
CIN
COUTX
RqJA
TJ
IOUTX
PD
Parameter
Conditions
Operational Power Supply
Enable Voltage
Ambient Temperature Range
Min
Max
Unit
2.7
5.5
V
0
5.5
−40
Typ
25
/FLAG sink current
Decoupling input capacitor
Decoupling output capacitor
Thermal Resistance Junction to Air
USB port per Hub
Power Dissipation Rating (Note 8)
mA
mF
120
mF
85
−40
Recommended Maximum DC current
°C
1
1
DFN−10−12 package (Notes 6 and 7)
Junction Temperature Range
+85
Per Channel
25
°C/W
+125
2.5
TA ≤ 25 °C
DFN−10 package
850
TA = 85 °C
DFN−10 package
428
°C
A
mW
6. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020
7. The RqJA is dependent of the PCB heat dissipation. Announced thermal resistance is the unless PCB dissipation and can be improve with
final PCB layout.
8. The maximum power dissipation (PD) is given by the following formula:
PD +
TJMAX * TA
R qJA
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4
NCP383
ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −40°C to +85°C and TJ up to + 125°C for VIN between
2.5 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C and VIN = 5 V.
Symbol
Parameter
Conditions
Conditions
Min
Typ
Max
45
70
Unit
POWER SWITCH
RDS(on)
Static drain−source on−state
resistance, per channel
TJ = 25°C
–40°C < TJ < 125°C
TR
Output rise time
VIN = 5 V
TF
Output fall time
VIN = 5 V
CLOAD = 1mF,
RLOAD = 100 W
(Note 9)
95
1.5
2.5
0.1
4
0.5
mW
ms
Logic Pins
VIHEN
High−level input voltage
VILEN
Low−level input voltage
IENx
Input current
TON
Turn on time
TOFF
Turn off time
1.2
VENx = 0 V, V/ENx = 5 V
CLOAD = 1mF, RLOAD = 100 W (Note 9)
V
−0.5
1
−
1
0.4
V
0.5
mA
9
ms
3
ms
CURRENT LIMIT
Ilimx = 90k (Note 10)
0.5
0.6
0.7
Ilimx = 56k
0.9
1
1.1
Ilimx = 20k (Note 10)
2.58
2.8
3.01
IOCP
Current−limit threshold (Maximum DC output current
IOUTX delivered to load)
TDET
Response time to short circuit
VIN = 5 V (Note 10)
TREG
Regulation time
1
2
3
ms
TOCP
Over current protection time
19
24
29
ms
2.45
2.5
2
A
ms
UNDERVOLTAGE LOCKOUT
VUVLO
IN pin low−level input voltage
VIN rising
−
VHYST
IN pin hysteresis
TJ = 25°C
25
TRUVLO
Re−arming Time
7
V
mV
12
15
ms
SUPPLY CURRENT
IINOFF
Low−level output supply current.
VIN = 5 V, No load on OUTX, Device OFF
VENX= 0 V or V/ENX= 5 V – TJ = 25°C
1
mA
IINON
High−level output supply current.
VIN = 5 V, No load on OUTX
Device ON − RILIM = 56 kW − VENX= 5 V
99
mA
IREV
Reverse leakage current
VOUTX = 5 V,
VIN = 0 V
1
mA
400
mV
TJ = 25°C
/FLAGx PINS
VOL
/FLAGX output low voltage
I/FLAGX = 1 mA
ILEAK
Off−state leakage
V/FLAGX = 5 V
1
mA
TFGL
/FLAGX deglitch
/FLAGX de−assertion time due to overcurrent
3
5
7
ms
TFOCP
/FLAGX deglitch
/FLAGX assertion due to overcurrent
5
7
12
ms
TFREV
/FLAGX deglitch
/FLAGX assertion due to reverse−voltage
3
5
7
ms
REVERSE VOLTAGE PROTECTION
VREV
Reverse voltage threshold
VOUT − VIN drop
150
mV
VRHYST
Reverse voltage threshold
hysteresis
VOUT − VIN drop decrease
30
mV
THERMAL SHUTDOWN
TSD
Thermal shutdown threshold
140
°C
TSDOCP
Thermal regulation threshold
125
°C
TRST
Thermal regulation rearming
threshold
115
°C
9. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground.
10. Guaranteed by design and by characterization
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NCP383
TF
TR
50%
VEN
90%
VOUT
10%
TOFF
TON
10%
90%
VOUT
10%
Figure 3. Ton, Toff, Trise, and Tfall
FUNCTIONAL DESCRIPTION
Overview
VOUTX
The NCP383 is a dual high side N channel MOSFET
power distribution switches designed to protect the input
supply voltage in case of heavy capacitive loads, short
circuit or over current. In addition, the high side MOSFETs
are turned off during under voltage, thermal shutdown or
reverse voltage condition. Thanks to the soft start circuitry,
NCP383 is able to limit large current and voltage surges.
IOCP x RLOAD
IOUTX
IOCP
Figure 5. Overload
Overcurrent Protection
NCP383 switches into a constant current regulation mode
when the output current is above the IOCP threshold.
Depending on the load, the output voltage is decreased
accordingly.
− In case of hot plug with heavy capacitive load, the
output voltage is brought down to the capacitor voltage.
The NCP383 will limit the current to the IOCP threshold
value until the charge of the capacitor is completed.
− In case of short circuit or huge load, the current is
limited to the IOCP value within TDET time until the
short condition is removed. If the output remains
shorted or tied to a very low voltage, the junction
temperature of the chip exceeds TSDOCP value and the
device enters in thermal shutdown (MOSFET is
turned−off).
VOUTX
VOUTX
Drop due to
capacitor charge
Thermal
Regulation
Threshold
Timer
Regulation
Mode
IOUTX
IOUTX
IOCP
IOCP
TOCP
Figure 4. Heavy Capacitive Load
Figure 6. Short Circuit
− In case of overload, the current is limited to the IOCP
value and the voltage value is reduced according to the
load by the following relation:
V OUTX + R LOADX
IOCP
TREG
Then, the device enters in timer regulation mode,
described in 2 phases:
(eq. 1)
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NCP383
− Off−phase: Power MOSFET is off during TOCP to allow
the die temperature to drop.
− On−phase: regulation current mode during TREG. The
current is regulated to the IOCP level.
The timer regulation mode allows the device to handle
high thermal dissipation (in case of short circuit for
example) within temperature operating condition.
NCP383 stays in on−phase/off−phase loop until the over
current condition is removed or enable pin is toggled.
Remark: other regulation mode can be available for
different
applications.
Please
contact
our
ON Semiconductor representative for availability.
temperature conditions. When an over current or a reverse
voltage fault is detected on the power path, /FLAGx pins are
asserted low at the end of the associate deglitch time (see
electrical characteristics). Due to this feature, the /FLAGx
pins are not tied low during the charge of a heavy capacitive
load or a voltage transient on output. Deglitch time is TFOCP
for over current fault and TFREV for reverse voltage. The
/FLAGx pins remain low until the fault is removed. Then,
the /FLAG pins go high at the end of TFGL
Undervoltage Lock−out
Due to a built−in under voltage lockout (UVLO) circuitry,
the output remains disconnected from input until VIN
voltage is above VUVLO. This circuit has a VHYST hysteresis
witch provides noise immunity to transient condition.
Adjustable Current−Limit Programming
NCP383xMUAJxx Version
The RLIM resistor connected between ILIM pin and GND
determine the current limit threshold according to the
electrical characteristic table.
Thermal Sense
Thermal shutdown turns off the power MOSFET if the die
temperature exceeds TSD. A Hysteresis of THYST prevents
the part from turning on until the die temperature cools at
TSD − THYST.
Enable Input
Enable pin must be driven by a logic signal (CMOS or
TTL compatible) or connected to the GND or VIN. A logic
low turns−on the device. A logic high on /ENX turns off
device and reduce the current consumption down to IINOFF.
Remark: Active high can be available for different
applications. Please contact our ON Semiconductor
representative for availability.
Blocking Control
The blocking control circuitry switches the bulk of the
power MOS. When the part is off, the body diode limits the
leakage current IREV from OUTX to IN. In this mode, anode
of the body diode is connected to IN pin and cathode is
connected to OUTX pin. In operating condition, anode of
the body diode is connected to OUTX pin and cathode is
connected to IN pin preventing the discharge of the power
supply.
Figure 7. Typical Ilim Curve vs Rlim External Resistor
/FLAGx Indicators
The /FLAGx pin are an open−drain MOSFET asserted
low during over current, reverse−voltage or over
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NCP383
APPLICATION INFORMATION
Power Dissipation
Power dissipation in regulation mode can be calculated by
taking into account the drop VIN −VOUTX link to the load by
the following relation:
The device’s junction temperature depends on different
contributor factor such as board layout, ambient
temperature, device environment, etc... Yet, the main
contributor in term of junction temperature is the power
dissipation of the power MOSFET. Assuming this, the
power dissipation and the junction temperature in normal
mode can be calculated with the following equations:
P D + R DS(on)
PD
RDS(on)
IOUTx
Ǔ
OUT1
2
) ǒI OUTǓ
Ǔ
2
R qJA ) T A
ǒǒVIN * RLOAD1
I OCPǓ ) ǒV IN * R LOAD2
I OCPǓ
Ǔ
I OCP
PD
VIN
RLOADX
IOCP
(eq. 2)
= Power dissipation (W)
= Power MOSFET on resistance (W)
= Output current in channel X (A)
TJ + PD
= Power dissipation (W)
= Input Voltage (V)
= Load Resistance on channel X (W)
= Output regulated current (A)
PCB Recommendations
The NCP383 integrates two up to 3 A rated NMOS FETs,
and the PCB design rules must be respected to properly
evacuate the heat out of the silicon. The DFN10 PAD1 must
be connected to ground plane to increase the heat transfer if
necessary. Of course, in any case, this pad must not connect
to any other potential. By increasing PCB area, the RqJA of
the package can be decreased, allowing higher current.
(eq. 3)
= Junction temperature (°C)
= Package thermal resistance (°C/W)
= Ambient temperature (°C)
CIN / COUT1 / COUT2:
* AS CLOSE AS POSSIBLE TO NCP383
* DIRECTLY CONNECTED TO GND PLANE (LOW IMPEDANCE CONNECTION)
* TRY TO AVOID VIAS BETWEEN PIN AND CAPACITOR
* IF 120 mF COUT1 and COUT2 ARE LOCATED FAR AWAY FROM NCP383, TRY TO ADD
EXTRA LOWER VALUE ( ~ 0.1 mF) CAPACITOR AS CLOSE AS POSSIBLE TO NCP383
AS MUCH AS POSSIBLE VIA TO INNER
GROUND PLANE (BEST POWER DISSIPATION)
GND TOP LAYER PLANE
COUT1
CIN
VOUT1 TOP LAYER PLANE
NCP383
TJ
RqJA
TA
ǒǒI
PD
(eq. 4)
VOUT2 TOP LAYER PLANE
COUT2
+5V Local Plane
GND TOP LAYER PLANE
Figure 8. Layout Recommendations
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RLIM
NCP383
ORDERING INFORMATION
Device
Package
Shipping†
NCP383LMUAJAATXG
UDFN10
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCP383xMUAJxxTXG
Tape and Reel for UDFN
d. Regulation option
c. Auto−discharge option
b. Current option
UDFN Package
a. I = Active Low
Code
Contents
a
L: active low
b
AJ: adjustable current limit
c
A: No autodischarge output path
d
A: standard regulation (CC + TSD warning +
timer)
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NCP383
PACKAGE DIMENSIONS
UDFN10 3x3, 0.5P (Leads 2 & 3 Tied)
CASE 517CC
ISSUE O
D
EXPOSED Cu
ÍÍÍ
ÍÍÍ
ÍÍÍ
ALTERNATE
CONSTRUCTION
E
(0.17)
0.15 C
2X
0.15 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MOLD CMPD
DETAIL B
PIN ONE
REFERENCE
2X
ÉÉÉ
ÇÇÇ
ÉÉÉ
A B
L1
L
TOP VIEW
A
DETAIL B
0.10 C
A3
L
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
A1
0.08 C
NOTE 4
C
SIDE VIEW
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
D2
DETAIL A
1
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.15
0.25
3.00 BSC
2.39
2.59
3.00 BSC
1.59
1.79
0.50 BSC
0.35
0.45
--0.15
DIM
A
A1
A3
b
D
D2
E
E2
e
L
L1
2.63
10X
0.62
5
0.50
PITCH
E2
1.81 3.30
10X
10
L
6
e
PACKAGE
OUTLINE
10X
b
0.10 C A
BOTTOM VIEW
0.05 C
1
B
NOTE 3
0.80
9X
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
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USA/Canada
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Phone: 421 33 790 2910
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Phone: 81−3−5817−1050
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Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCP383/D